1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
1
Last lot of target-arm changes to squeeze in before rc1:
2
* various minor Arm bug fixes
3
* David Carlier's Haiku build portability fixes
4
* Wentong Wu's fixes for icount handling in the nios2 target
2
5
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
6
The following changes since commit 00ce6c36b35e0eb8cc5d68a28f288a6335848813:
7
8
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-07-13' into staging (2020-07-13 13:01:30 +0100)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200713
8
13
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
14
for you to fetch changes up to 756f739b1682bf131994ec96dad7fbdf8b54493a:
10
15
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
16
hw/arm/aspeed: Do not create and attach empty SD cards by default (2020-07-13 14:36:12 +0100)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
target-arm queue:
19
target-arm queue:
15
* Fix coverity nit in int_to_float code
20
* hw/arm/bcm2836: Remove unused 'cpu_type' field
16
* Don't set Invalid for float-to-int(MAXINT)
21
* target/arm: Fix mtedesc for do_mem_zpz
17
* Fix fp_status_f16 tininess before rounding
22
* Add the ability to change the FEC PHY MDIO device number on i.MX25/i.MX6/i.MX7
18
* Add various missing insns from the v8.2-FP16 extension
23
* target/arm: Don't do raw writes for PMINTENCLR
19
* Fix sqrt_f16 exception raising
24
* virtio-iommu: Fix coverity issue in virtio_iommu_handle_command()
20
* sdcard: Correct CRC16 offset in sd_function_switch()
25
* build: Fix various issues with building on Haiku
21
* tcg: Optionally log FPU state in TCG -d cpu logging
26
* target/nios2: fix wrctl behaviour when using icount
27
* hw/arm/tosa: Encapsulate misc GPIO handling in a device
28
* hw/arm/palm.c: Encapsulate misc GPIO handling in a device
29
* hw/arm/aspeed: Do not create and attach empty SD cards by default
22
30
23
----------------------------------------------------------------
31
----------------------------------------------------------------
24
Alex Bennée (5):
32
Aaron Lindsay (1):
25
fpu/softfloat: int_to_float ensure r fully initialised
33
target/arm: Don't do raw writes for PMINTENCLR
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
30
34
31
Peter Maydell (3):
35
David CARLIER (8):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
36
build: Enable BSD symbols for Haiku
33
target/arm: Fix fp_status_f16 tininess before rounding
37
util/qemu-openpty.c: Don't assume pty.h is glibc-only
34
tcg: Optionally log FPU state in TCG -d cpu logging
38
build: Check that mlockall() exists
39
osdep.h: Always include <sys/signal.h> if it exists
40
osdep.h: For Haiku, define SIGIO as equivalent to SIGPOLL
41
bswap.h: Include <endian.h> on Haiku for bswap operations
42
util/compatfd.c: Only include <sys/syscall.h> if CONFIG_SIGNALFD
43
util/oslib-posix.c: Implement qemu_init_exec_dir() for Haiku
35
44
36
Philippe Mathieu-Daudé (1):
45
Eric Auger (1):
37
sdcard: Correct CRC16 offset in sd_function_switch()
46
virtio-iommu: Fix coverity issue in virtio_iommu_handle_command()
38
47
39
Richard Henderson (7):
48
Gerd Hoffmann (1):
40
target/arm: Implement FMOV (general) for fp16
49
util/drm: make portable by avoiding struct dirent d_type
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
47
50
48
include/qemu/log.h | 1 +
51
Jean-Christophe Dubois (3):
49
target/arm/helper-a64.h | 2 +
52
Add the ability to change the FEC PHY MDIO device number on i.MX25 processor
50
target/arm/helper.h | 6 +
53
Add the ability to change the FEC PHY MDIO device number on i.MX6 processor
51
accel/tcg/cpu-exec.c | 9 +-
54
Add the ability to change the FEC PHY MDIO devices numbers on i.MX7 processor
52
fpu/softfloat.c | 6 +-
53
hw/sd/sd.c | 2 +-
54
target/arm/cpu.c | 2 +
55
target/arm/helper-a64.c | 10 ++
56
target/arm/helper.c | 38 +++-
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
58
util/log.c | 2 +
59
11 files changed, 428 insertions(+), 71 deletions(-)
60
55
56
Peter Maydell (4):
57
hw/arm/tosa.c: Detabify
58
hw/arm/tosa: Encapsulate misc GPIO handling in a device
59
hw/arm/palm.c: Detabify
60
hw/arm/palm.c: Encapsulate misc GPIO handling in a device
61
62
Philippe Mathieu-Daudé (2):
63
hw/arm/bcm2836: Remove unused 'cpu_type' field
64
hw/arm/aspeed: Do not create and attach empty SD cards by default
65
66
Richard Henderson (1):
67
target/arm: Fix mtedesc for do_mem_zpz
68
69
Wentong Wu (4):
70
target/nios2: add DISAS_NORETURN case for nothing more to generate
71
target/nios2: in line the semantics of DISAS_UPDATE with other targets
72
target/nios2: Use gen_io_start around wrctl instruction
73
hw/nios2: exit to main CPU loop only when unmasking interrupts
74
75
configure | 38 ++++++++++++-
76
include/hw/arm/bcm2836.h | 1 -
77
include/hw/arm/fsl-imx25.h | 1 +
78
include/hw/arm/fsl-imx6.h | 1 +
79
include/hw/arm/fsl-imx7.h | 1 +
80
include/qemu/bswap.h | 2 +
81
include/qemu/osdep.h | 6 +-
82
hw/arm/aspeed.c | 9 +--
83
hw/arm/fsl-imx25.c | 7 +++
84
hw/arm/fsl-imx6.c | 7 +++
85
hw/arm/fsl-imx7.c | 9 +++
86
hw/arm/palm.c | 111 +++++++++++++++++++++++++------------
87
hw/arm/tosa.c | 132 +++++++++++++++++++++++++++++---------------
88
hw/nios2/cpu_pic.c | 3 +-
89
hw/virtio/virtio-iommu.c | 1 +
90
hw/xen/xen-legacy-backend.c | 1 -
91
os-posix.c | 4 ++
92
target/arm/helper.c | 4 +-
93
target/arm/translate-sve.c | 2 +-
94
target/nios2/translate.c | 12 +++-
95
util/compatfd.c | 2 +
96
util/drm.c | 19 +++++--
97
util/oslib-posix.c | 20 ++++++-
98
util/qemu-openpty.c | 2 +-
99
24 files changed, 292 insertions(+), 103 deletions(-)
100
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
The 'cpu_type' has been moved from BCM283XState to BCM283XClass
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
in commit 210f47840d, but we forgot to remove the old variable.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Do it now.
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
7
Fixes: 210f47840d ("hw/arm/bcm2836: Hardcode correct CPU type")
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20200703200459.23294-1-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
13
include/hw/arm/bcm2836.h | 1 -
11
1 file changed, 15 insertions(+), 2 deletions(-)
14
1 file changed, 1 deletion(-)
12
15
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
18
--- a/include/hw/arm/bcm2836.h
16
+++ b/target/arm/translate-a64.c
19
+++ b/include/hw/arm/bcm2836.h
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
18
bool sf = extract32(insn, 31, 1);
21
DeviceState parent_obj;
19
bool itof;
22
/*< public >*/
20
23
21
- if (sbit || (type > 1)
24
- char *cpu_type;
22
- || (!sf && scale < 32)) {
25
uint32_t enabled_cpus;
23
+ if (sbit || (!sf && scale < 32)) {
26
24
+ unallocated_encoding(s);
27
struct {
25
+ return;
26
+ }
27
+
28
+ switch (type) {
29
+ case 0: /* float32 */
30
+ case 1: /* float64 */
31
+ break;
32
+ case 3: /* float16 */
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
34
+ break;
35
+ }
36
+ /* fallthru */
37
+ default:
38
unallocated_encoding(s);
39
return;
40
}
41
--
28
--
42
2.17.0
29
2.20.1
43
30
44
31
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
No sense in emitting code after the exception.
3
The mtedesc that was constructed was not actually passed in.
4
Found by Coverity (CID 1429996).
4
5
6
Fixes: d28d12f008e
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
9
Message-id: 20200706202345.193676-1-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 2 +-
12
target/arm/translate-sve.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
19
default:
20
desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);
20
/* all other sf/type/rmode combinations are invalid */
21
desc <<= SVE_MTEDESC_SHIFT;
21
unallocated_encoding(s);
22
}
22
- break;
23
- desc = simd_desc(vsz, vsz, scale);
23
+ return;
24
+ desc = simd_desc(vsz, vsz, desc | scale);
24
}
25
t_desc = tcg_const_i32(desc);
25
26
26
if (!fp_access_check(s)) {
27
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
27
--
28
--
28
2.17.0
29
2.20.1
29
30
30
31
diff view generated by jsdifflib
New patch
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
4
Message-id: 9f8923ecd974160ae8f634c275b1100c2cbe66d7.1593806826.git.jcd@tribudubois.net
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
[PMM: updated for object_property_set_uint() argument reordering]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/arm/fsl-imx25.h | 1 +
10
hw/arm/fsl-imx25.c | 7 +++++++
11
2 files changed, 8 insertions(+)
12
13
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/fsl-imx25.h
16
+++ b/include/hw/arm/fsl-imx25.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
18
MemoryRegion rom[2];
19
MemoryRegion iram;
20
MemoryRegion iram_alias;
21
+ uint32_t phy_num;
22
} FslIMX25State;
23
24
/**
25
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/fsl-imx25.c
28
+++ b/hw/arm/fsl-imx25.c
29
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
30
epit_table[i].irq));
31
}
32
33
+ object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err);
34
qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
35
36
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) {
37
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
38
&s->iram_alias);
39
}
40
41
+static Property fsl_imx25_properties[] = {
42
+ DEFINE_PROP_UINT32("fec-phy-num", FslIMX25State, phy_num, 0),
43
+ DEFINE_PROP_END_OF_LIST(),
44
+};
45
+
46
static void fsl_imx25_class_init(ObjectClass *oc, void *data)
47
{
48
DeviceClass *dc = DEVICE_CLASS(oc);
49
50
+ device_class_set_props(dc, fsl_imx25_properties);
51
dc->realize = fsl_imx25_realize;
52
dc->desc = "i.MX25 SOC";
53
/*
54
--
55
2.20.1
56
57
diff view generated by jsdifflib
New patch
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
4
Message-id: 05a64e83eb1c0c865ac077b22c599425c024c02c.1593806826.git.jcd@tribudubois.net
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
[PMM: updated for object_property_set_uint() argument reordering]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/arm/fsl-imx6.h | 1 +
10
hw/arm/fsl-imx6.c | 7 +++++++
11
2 files changed, 8 insertions(+)
12
13
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/fsl-imx6.h
16
+++ b/include/hw/arm/fsl-imx6.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
18
MemoryRegion caam;
19
MemoryRegion ocram;
20
MemoryRegion ocram_alias;
21
+ uint32_t phy_num;
22
} FslIMX6State;
23
24
25
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/fsl-imx6.c
28
+++ b/hw/arm/fsl-imx6.c
29
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
30
spi_table[i].irq));
31
}
32
33
+ object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
34
qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
35
if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
36
return;
37
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
38
&s->ocram_alias);
39
}
40
41
+static Property fsl_imx6_properties[] = {
42
+ DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0),
43
+ DEFINE_PROP_END_OF_LIST(),
44
+};
45
+
46
static void fsl_imx6_class_init(ObjectClass *oc, void *data)
47
{
48
DeviceClass *dc = DEVICE_CLASS(oc);
49
50
+ device_class_set_props(dc, fsl_imx6_properties);
51
dc->realize = fsl_imx6_realize;
52
dc->desc = "i.MX6 SOC";
53
/* Reason: Uses serial_hd() in the realize() function */
54
--
55
2.20.1
56
57
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
We missed all of the scalar fp16 fma operations.
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
4
4
Message-id: c850187322be9930e47c8b234c385a7d0da245cb.1593806826.git.jcd@tribudubois.net
5
Cc: qemu-stable@nongnu.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
[PMM: updated for object_property_set_uint() argument reordering]
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
9
include/hw/arm/fsl-imx7.h | 1 +
13
1 file changed, 48 insertions(+)
10
hw/arm/fsl-imx7.c | 9 +++++++++
11
2 files changed, 10 insertions(+)
14
12
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
15
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/target/arm/translate-a64.c
16
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
17
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX7State {
20
tcg_temp_free_i64(tcg_res);
18
IMX7GPRState gpr;
19
ChipideaState usb[FSL_IMX7_NUM_USBS];
20
DesignwarePCIEHost pcie;
21
+ uint32_t phy_num[FSL_IMX7_NUM_ETHS];
22
} FslIMX7State;
23
24
enum FslIMX7MemoryMap {
25
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/fsl-imx7.c
28
+++ b/hw/arm/fsl-imx7.c
29
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
30
FSL_IMX7_ENET2_ADDR,
31
};
32
33
+ object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
34
+ s->phy_num[i], &error_abort);
35
object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
36
FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort);
37
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
38
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
39
FSL_IMX7_PCIE_PHY_SIZE);
21
}
40
}
22
41
23
+/* Floating-point data-processing (3 source) - half precision */
42
+static Property fsl_imx7_properties[] = {
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
43
+ DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
25
+ int rd, int rn, int rm, int ra)
44
+ DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
26
+{
45
+ DEFINE_PROP_END_OF_LIST(),
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
46
+};
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
30
+
47
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
48
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
32
+ tcg_op2 = read_fp_hreg(s, rm);
49
{
33
+ tcg_op3 = read_fp_hreg(s, ra);
50
DeviceClass *dc = DEVICE_CLASS(oc);
34
+
51
35
+ /* These are fused multiply-add, and must be done as one
52
+ device_class_set_props(dc, fsl_imx7_properties);
36
+ * floating point operation with no rounding between the
53
dc->realize = fsl_imx7_realize;
37
+ * multiplication and addition steps.
54
38
+ * NB that doing the negations here as separate steps is
55
/* Reason: Uses serial_hds and nd_table in realize() directly */
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
42
+ if (o1 == true) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
44
+ }
45
+
46
+ if (o0 != o1) {
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
48
+ }
49
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
51
+
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
59
+}
60
+
61
/* Floating point data-processing (3 source)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
65
}
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
67
break;
68
+ case 3:
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
+ unallocated_encoding(s);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
80
}
81
--
56
--
82
2.17.0
57
2.20.1
83
58
84
59
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
2
2
3
Cc: qemu-stable@nongnu.org
3
Raw writes to this register when in KVM mode can cause interrupts to be
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
raised (even when the PMU is disabled). Because the underlying state is
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
already aliased to PMINTENSET (which already provides raw write
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
functions), we can safely disable raw accesses to PMINTENCLR entirely.
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
7
8
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
9
Message-id: 20200707152616.1917154-1-aaron@os.amperecomputing.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/helper.h | 6 +++
13
target/arm/helper.c | 4 ++--
11
target/arm/helper.c | 38 ++++++++++++++-
14
1 file changed, 2 insertions(+), 2 deletions(-)
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
15
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
44
#undef VFP_CONV_FIX_A64
21
.resetvalue = 0x0 },
45
22
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
23
.access = PL1_RW, .accessfn = access_tpm,
47
- * Therefore we convert to f64 (which does not round), scale,
24
- .type = ARM_CP_ALIAS | ARM_CP_IO,
48
- * and then convert f64 to f16 (which may round).
25
+ .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
26
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
50
+ * vice versa for conversion to integer.
27
.writefn = pmintenclr_write, },
51
+ *
28
{ .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
29
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
53
+ * For 64-bit integers, any integer that would cause rounding will also
30
.access = PL1_RW, .accessfn = access_tpm,
54
+ * overflow to f16 infinity, so there is no double rounding problem.
31
- .type = ARM_CP_ALIAS | ARM_CP_IO,
55
*/
32
+ .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
56
33
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
34
.writefn = pmintenclr_write },
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
35
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
61
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
65
+}
66
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
68
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
70
+}
71
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
36
--
266
2.17.0
37
2.20.1
267
38
268
39
diff view generated by jsdifflib
New patch
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
Coverity points out (CID 1430180) that the new case is missing
4
break or a /* fallthrough */ comment. Break is the right thing to
5
do as in that case, tail is not used.
6
7
Fixes 1733eebb9e ("virtio-iommu: Implement RESV_MEM probe request")
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Reported-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20200708160147.18426-1-eric.auger@redhat.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/virtio/virtio-iommu.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/virtio/virtio-iommu.c
20
+++ b/hw/virtio/virtio-iommu.c
21
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
22
ptail = (struct virtio_iommu_req_tail *)
23
(buf + s->config.probe_size);
24
ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
25
+ break;
26
}
27
default:
28
tail.status = VIRTIO_IOMMU_S_UNSUPP;
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
1
In float-to-integer conversion, if the floating point input
1
From: David CARLIER <devnexen@gmail.com>
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
2
9
Fix the boundary case to take the right half of the if()
3
Tell Haiku to provide various BSD functions by setting BSD_SOURCE
10
statements.
4
and linking libbsd.
11
5
12
This fixes a regression from 2.11 introduced by the softfloat
6
Signed-off-by: David Carlier <devnexen@gmail.com>
13
refactoring.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200703145614.16684-2-peter.maydell@linaro.org
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
10
[PMM: expanded commit message]
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
13
---
21
fpu/softfloat.c | 4 ++--
14
configure | 4 ++--
22
1 file changed, 2 insertions(+), 2 deletions(-)
15
1 file changed, 2 insertions(+), 2 deletions(-)
23
16
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
17
diff --git a/configure b/configure
25
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100755
26
--- a/fpu/softfloat.c
19
--- a/configure
27
+++ b/fpu/softfloat.c
20
+++ b/configure
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
21
@@ -XXX,XX +XXX,XX @@ SunOS)
29
r = UINT64_MAX;
22
;;
30
}
23
Haiku)
31
if (p.sign) {
24
haiku="yes"
32
- if (r < -(uint64_t) min) {
25
- QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS $QEMU_CFLAGS"
33
+ if (r <= -(uint64_t) min) {
26
- LIBS="-lposix_error_mapper -lnetwork $LIBS"
34
return -r;
27
+ QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -DBSD_SOURCE $QEMU_CFLAGS"
35
} else {
28
+ LIBS="-lposix_error_mapper -lnetwork -lbsd $LIBS"
36
s->float_exception_flags = orig_flags | float_flag_invalid;
29
;;
37
return min;
30
Linux)
38
}
31
audio_drv_list="try-pa oss"
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
45
--
32
--
46
2.17.0
33
2.20.1
47
34
48
35
diff view generated by jsdifflib
New patch
1
From: David CARLIER <devnexen@gmail.com>
1
2
3
Instead of using an OS-specific ifdef test to select the "openpty()
4
is in pty.h" codepath, make configure check for the existence of
5
the header and use the new CONFIG_PTY instead.
6
7
This is necessary to build on Haiku, which also provides openpty()
8
via pty.h.
9
10
Signed-off-by: David Carlier <devnexen@gmail.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20200703145614.16684-3-peter.maydell@linaro.org
14
[PMM: Expanded commit message; rename to HAVE_PTY_H]
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
configure | 9 +++++++++
19
util/qemu-openpty.c | 2 +-
20
2 files changed, 10 insertions(+), 1 deletion(-)
21
22
diff --git a/configure b/configure
23
index XXXXXXX..XXXXXXX 100755
24
--- a/configure
25
+++ b/configure
26
@@ -XXX,XX +XXX,XX @@ else
27
l2tpv3=no
28
fi
29
30
+if check_include "pty.h" ; then
31
+ pty_h=yes
32
+else
33
+ pty_h=no
34
+fi
35
+
36
#########################################
37
# vhost interdependencies and host support
38
39
@@ -XXX,XX +XXX,XX @@ fi
40
if test "$sheepdog" = "yes" ; then
41
echo "CONFIG_SHEEPDOG=y" >> $config_host_mak
42
fi
43
+if test "$pty_h" = "yes" ; then
44
+ echo "HAVE_PTY_H=y" >> $config_host_mak
45
+fi
46
if test "$fuzzing" = "yes" ; then
47
if test "$have_fuzzer" = "yes"; then
48
FUZZ_LDFLAGS=" -fsanitize=address,fuzzer"
49
diff --git a/util/qemu-openpty.c b/util/qemu-openpty.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/util/qemu-openpty.c
52
+++ b/util/qemu-openpty.c
53
@@ -XXX,XX +XXX,XX @@
54
#include "qemu/osdep.h"
55
#include "qemu-common.h"
56
57
-#if defined(__GLIBC__)
58
+#if defined HAVE_PTY_H
59
# include <pty.h>
60
#elif defined CONFIG_BSD
61
# include <termios.h>
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
New patch
1
From: David CARLIER <devnexen@gmail.com>
1
2
3
Instead of assuming that all POSIX platforms provide mlockall(),
4
test for it in configure. If the host doesn't provide this platform
5
then os_mlock() will fail -ENOSYS, as it does already on Windows.
6
7
This is necessary for Haiku, which does not have mlockall().
8
9
Signed-off-by: David Carlier <devnexen@gmail.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20200703145614.16684-4-peter.maydell@linaro.org
13
[PMM: Expanded commit message; rename to HAVE_MLOCKALL]
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
configure | 15 +++++++++++++++
18
os-posix.c | 4 ++++
19
2 files changed, 19 insertions(+)
20
21
diff --git a/configure b/configure
22
index XXXXXXX..XXXXXXX 100755
23
--- a/configure
24
+++ b/configure
25
@@ -XXX,XX +XXX,XX @@ else
26
pty_h=no
27
fi
28
29
+cat > $TMPC <<EOF
30
+#include <sys/mman.h>
31
+int main(int argc, char *argv[]) {
32
+ return mlockall(MCL_FUTURE);
33
+}
34
+EOF
35
+if compile_prog "" "" ; then
36
+ have_mlockall=yes
37
+else
38
+ have_mlockall=no
39
+fi
40
+
41
#########################################
42
# vhost interdependencies and host support
43
44
@@ -XXX,XX +XXX,XX @@ fi
45
if test "$pty_h" = "yes" ; then
46
echo "HAVE_PTY_H=y" >> $config_host_mak
47
fi
48
+if test "$have_mlockall" = "yes" ; then
49
+ echo "HAVE_MLOCKALL=y" >> $config_host_mak
50
+fi
51
if test "$fuzzing" = "yes" ; then
52
if test "$have_fuzzer" = "yes"; then
53
FUZZ_LDFLAGS=" -fsanitize=address,fuzzer"
54
diff --git a/os-posix.c b/os-posix.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/os-posix.c
57
+++ b/os-posix.c
58
@@ -XXX,XX +XXX,XX @@ bool is_daemonized(void)
59
60
int os_mlock(void)
61
{
62
+#ifdef HAVE_MLOCKALL
63
int ret = 0;
64
65
ret = mlockall(MCL_CURRENT | MCL_FUTURE);
66
@@ -XXX,XX +XXX,XX @@ int os_mlock(void)
67
}
68
69
return ret;
70
+#else
71
+ return -ENOSYS;
72
+#endif
73
}
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
New patch
1
From: David CARLIER <devnexen@gmail.com>
1
2
3
Regularize our handling of <sys/signal.h>: currently we include it in
4
osdep.h, but only for OpenBSD, and we include it without an ifdef
5
guard in a couple of C files. This causes problems for Haiku, which
6
doesn't have that header.
7
8
Instead, check in configure whether sys/signal.h exists, and if it
9
does then always include it from osdep.h.
10
11
Signed-off-by: David Carlier <devnexen@gmail.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Thomas Huth <thuth@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20200703145614.16684-5-peter.maydell@linaro.org
17
[PMM: Expanded commit message; rename to HAVE_SYS_SIGNAL_H]
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
configure | 10 ++++++++++
22
include/qemu/osdep.h | 2 +-
23
hw/xen/xen-legacy-backend.c | 1 -
24
util/oslib-posix.c | 1 -
25
4 files changed, 11 insertions(+), 3 deletions(-)
26
27
diff --git a/configure b/configure
28
index XXXXXXX..XXXXXXX 100755
29
--- a/configure
30
+++ b/configure
31
@@ -XXX,XX +XXX,XX @@ if check_include "libdrm/drm.h" ; then
32
have_drm_h=yes
33
fi
34
35
+#########################################
36
+# sys/signal.h check
37
+have_sys_signal_h=no
38
+if check_include "sys/signal.h" ; then
39
+ have_sys_signal_h=yes
40
+fi
41
+
42
##########################################
43
# VTE probe
44
45
@@ -XXX,XX +XXX,XX @@ fi
46
if test "$have_openpty" = "yes" ; then
47
echo "HAVE_OPENPTY=y" >> $config_host_mak
48
fi
49
+if test "$have_sys_signal_h" = "yes" ; then
50
+ echo "HAVE_SYS_SIGNAL_H=y" >> $config_host_mak
51
+fi
52
53
# Work around a system header bug with some kernel/XFS header
54
# versions where they both try to define 'struct fsxattr':
55
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/include/qemu/osdep.h
58
+++ b/include/qemu/osdep.h
59
@@ -XXX,XX +XXX,XX @@ extern int daemon(int, int);
60
#include <setjmp.h>
61
#include <signal.h>
62
63
-#ifdef __OpenBSD__
64
+#ifdef HAVE_SYS_SIGNAL_H
65
#include <sys/signal.h>
66
#endif
67
68
diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/xen/xen-legacy-backend.c
71
+++ b/hw/xen/xen-legacy-backend.c
72
@@ -XXX,XX +XXX,XX @@
73
*/
74
75
#include "qemu/osdep.h"
76
-#include <sys/signal.h>
77
78
#include "hw/sysbus.h"
79
#include "hw/boards.h"
80
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/util/oslib-posix.c
83
+++ b/util/oslib-posix.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "qemu/sockets.h"
86
#include "qemu/thread.h"
87
#include <libgen.h>
88
-#include <sys/signal.h>
89
#include "qemu/cutils.h"
90
91
#ifdef CONFIG_LINUX
92
--
93
2.20.1
94
95
diff view generated by jsdifflib
New patch
1
From: David CARLIER <devnexen@gmail.com>
1
2
3
Haiku doesn't provide SIGIO; fix this up in osdep.h by defining it as
4
equal to SIGPOLL.
5
6
Signed-off-by: David Carlier <devnexen@gmail.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Thomas Huth <thuth@redhat.com>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20200703145614.16684-6-peter.maydell@linaro.org
11
[PMM: Expanded commit message]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/qemu/osdep.h | 4 ++++
16
1 file changed, 4 insertions(+)
17
18
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/qemu/osdep.h
21
+++ b/include/qemu/osdep.h
22
@@ -XXX,XX +XXX,XX @@ void qemu_anon_ram_free(void *ptr, size_t size);
23
#define HAVE_CHARDEV_PARPORT 1
24
#endif
25
26
+#if defined(__HAIKU__)
27
+#define SIGIO SIGPOLL
28
+#endif
29
+
30
#if defined(CONFIG_LINUX)
31
#ifndef BUS_MCEERR_AR
32
#define BUS_MCEERR_AR 4
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
New patch
1
From: David CARLIER <devnexen@gmail.com>
1
2
3
Haiku puts the bswap* functions in <endian.h>; pull in that
4
include file on that platform.
5
6
Signed-off-by: David Carlier <devnexen@gmail.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Thomas Huth <thuth@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200703145614.16684-7-peter.maydell@linaro.org
12
[PMM: Expanded commit message]
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/qemu/bswap.h | 2 ++
17
1 file changed, 2 insertions(+)
18
19
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/qemu/bswap.h
22
+++ b/include/qemu/bswap.h
23
@@ -XXX,XX +XXX,XX @@
24
# include <machine/bswap.h>
25
#elif defined(__FreeBSD__)
26
# include <sys/endian.h>
27
+#elif defined(__HAIKU__)
28
+# include <endian.h>
29
#elif defined(CONFIG_BYTESWAP_H)
30
# include <byteswap.h>
31
32
--
33
2.20.1
34
35
diff view generated by jsdifflib
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
From: David CARLIER <devnexen@gmail.com>
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
8
2
9
Add the missing initialization.
3
util/compatfd.c includes <sys/syscall.h> so that the CONFIG_SIGNALFD
4
code can use SYS_signalfd. Guard the #include with CONFIG_SIGNALFD
5
to avoid portability issues on hosts like Haiku which do not
6
provide that header file.
10
7
11
Fixes: d81ce0ef2c4f105
8
Signed-off-by: David Carlier <devnexen@gmail.com>
12
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Thomas Huth <thuth@redhat.com>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
12
Message-id: 20200703145614.16684-8-peter.maydell@linaro.org
13
[PMM: Expanded commit message]
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
16
---
18
target/arm/cpu.c | 2 ++
17
util/compatfd.c | 2 ++
19
1 file changed, 2 insertions(+)
18
1 file changed, 2 insertions(+)
20
19
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
20
diff --git a/util/compatfd.c b/util/compatfd.c
22
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
22
--- a/util/compatfd.c
24
+++ b/target/arm/cpu.c
23
+++ b/util/compatfd.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
24
@@ -XXX,XX +XXX,XX @@
26
&env->vfp.fp_status);
25
#include "qemu/osdep.h"
27
set_float_detect_tininess(float_tininess_before_rounding,
26
#include "qemu/thread.h"
28
&env->vfp.standard_fp_status);
27
29
+ set_float_detect_tininess(float_tininess_before_rounding,
28
+#if defined(CONFIG_SIGNALFD)
30
+ &env->vfp.fp_status_f16);
29
#include <sys/syscall.h>
31
#ifndef CONFIG_USER_ONLY
30
+#endif
32
if (kvm_enabled()) {
31
33
kvm_arm_reset_vcpu(cpu);
32
struct sigfd_compat_info
33
{
34
--
34
--
35
2.17.0
35
2.20.1
36
36
37
37
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: David CARLIER <devnexen@gmail.com>
2
2
3
Adding the fp16 moves to/from general registers.
3
The qemu_init_exec_dir() function is inherently non-portable;
4
provide an implementation for Haiku hosts.
4
5
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: David Carlier <devnexen@gmail.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Message-id: 20200703145614.16684-9-peter.maydell@linaro.org
10
[PMM: Expanded commit message]
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
14
util/oslib-posix.c | 19 +++++++++++++++++++
13
1 file changed, 21 insertions(+)
15
1 file changed, 19 insertions(+)
14
16
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
19
--- a/util/oslib-posix.c
18
+++ b/target/arm/translate-a64.c
20
+++ b/util/oslib-posix.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
21
@@ -XXX,XX +XXX,XX @@
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
22
#include <mach-o/dyld.h>
21
clear_vec_high(s, true, rd);
23
#endif
22
break;
24
23
+ case 3:
25
+#ifdef __HAIKU__
24
+ /* 16 bit */
26
+#include <kernel/image.h>
25
+ tmp = tcg_temp_new_i64();
27
+#endif
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
28
+
27
+ write_fp_dreg(s, rd, tmp);
29
#include "qemu/mmap-alloc.h"
28
+ tcg_temp_free_i64(tmp);
30
29
+ break;
31
#ifdef CONFIG_DEBUG_STACK_USAGE
30
+ default:
32
@@ -XXX,XX +XXX,XX @@ void qemu_init_exec_dir(const char *argv0)
31
+ g_assert_not_reached();
33
}
32
}
33
} else {
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
36
/* 64 bits from top half */
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
34
}
46
}
35
}
47
}
36
+#elif defined(__HAIKU__)
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
37
+ {
49
case 0xa: /* 64 bit */
38
+ image_info ii;
50
case 0xd: /* 64 bit to top half of quad */
39
+ int32_t c = 0;
51
break;
40
+
52
+ case 0x6: /* 16-bit float, 32-bit int */
41
+ *buf = '\0';
53
+ case 0xe: /* 16-bit float, 64-bit int */
42
+ while (get_next_image_info(0, &c, &ii) == B_OK) {
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
43
+ if (ii.type == B_APP_IMAGE) {
44
+ strncpy(buf, ii.name, sizeof(buf));
45
+ buf[sizeof(buf) - 1] = 0;
46
+ p = buf;
55
+ break;
47
+ break;
56
+ }
48
+ }
57
+ /* fallthru */
49
+ }
58
default:
50
+ }
59
/* all other sf/type/rmode combinations are invalid */
51
#endif
60
unallocated_encoding(s);
52
/* If we don't have any way of figuring out the actual executable
53
location then try argv[0]. */
61
--
54
--
62
2.17.0
55
2.20.1
63
56
64
57
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Gerd Hoffmann <kraxel@redhat.com>
2
2
3
All the hard work is already done by vfp_expand_imm, we just need to
3
Given this isn't perforance critical at all lets avoid the non-portable
4
make sure we pick up the correct size.
4
d_type and use fstat instead to check whenever the file is a chardev.
5
5
6
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
7
Reported-by: David Carlier <devnexen@gmail.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20200703145614.16684-10-peter.maydell@linaro.org
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200701180302.14821-1-kraxel@redhat.com
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
13
[PMM: fixed comment style; tweaked subject line]
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
17
util/drm.c | 19 ++++++++++++++-----
17
1 file changed, 17 insertions(+), 3 deletions(-)
18
1 file changed, 14 insertions(+), 5 deletions(-)
18
19
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
diff --git a/util/drm.c b/util/drm.c
20
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
22
--- a/util/drm.c
22
+++ b/target/arm/translate-a64.c
23
+++ b/util/drm.c
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
24
@@ -XXX,XX +XXX,XX @@ int qemu_drm_rendernode_open(const char *rendernode)
24
{
25
{
25
int rd = extract32(insn, 0, 5);
26
DIR *dir;
26
int imm8 = extract32(insn, 13, 8);
27
struct dirent *e;
27
- int is_double = extract32(insn, 22, 2);
28
- int r, fd;
28
+ int type = extract32(insn, 22, 2);
29
+ struct stat st;
29
uint64_t imm;
30
+ int r, fd, ret;
30
TCGv_i64 tcg_res;
31
char *p;
31
+ TCGMemOp sz;
32
32
33
if (rendernode) {
33
- if (is_double > 1) {
34
@@ -XXX,XX +XXX,XX @@ int qemu_drm_rendernode_open(const char *rendernode)
34
+ switch (type) {
35
35
+ case 0:
36
fd = -1;
36
+ sz = MO_32;
37
while ((e = readdir(dir))) {
37
+ break;
38
- if (e->d_type != DT_CHR) {
38
+ case 1:
39
- continue;
39
+ sz = MO_64;
40
- }
40
+ break;
41
-
41
+ case 3:
42
if (strncmp(e->d_name, "renderD", 7)) {
42
+ sz = MO_16;
43
continue;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
44
}
44
+ break;
45
@@ -XXX,XX +XXX,XX @@ int qemu_drm_rendernode_open(const char *rendernode)
46
g_free(p);
47
continue;
48
}
49
+
50
+ /*
51
+ * prefer fstat() over checking e->d_type == DT_CHR for
52
+ * portability reasons
53
+ */
54
+ ret = fstat(r, &st);
55
+ if (ret < 0 || (st.st_mode & S_IFMT) != S_IFCHR) {
56
+ close(r);
57
+ g_free(p);
58
+ continue;
45
+ }
59
+ }
46
+ /* fallthru */
60
+
47
+ default:
61
fd = r;
48
unallocated_encoding(s);
62
g_free(p);
49
return;
63
break;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
52
return;
53
}
54
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
56
+ imm = vfp_expand_imm(sz, imm8);
57
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
60
--
64
--
61
2.17.0
65
2.20.1
62
66
63
67
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Wentong Wu <wentong.wu@intel.com>
2
2
3
Cc: qemu-stable@nongnu.org
3
Add DISAS_NORETURN case for nothing more to generate because at runtime
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
execution will never return from some helper call. And at the same time
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
replace DISAS_UPDATE in t_gen_helper_raise_exception and gen_exception
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
with the newly added DISAS_NORETURN.
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
7
8
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
9
Message-id: 20200710233433.19729-1-wentong.wu@intel.com
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
13
target/nios2/translate.c | 5 +++--
11
1 file changed, 14 insertions(+), 16 deletions(-)
14
1 file changed, 3 insertions(+), 2 deletions(-)
12
15
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
18
--- a/target/nios2/translate.c
16
+++ b/target/arm/translate-a64.c
19
+++ b/target/nios2/translate.c
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
20
@@ -XXX,XX +XXX,XX @@ static void t_gen_helper_raise_exception(DisasContext *dc,
18
return v;
21
tcg_gen_movi_tl(dc->cpu_R[R_PC], dc->pc);
22
gen_helper_raise_exception(dc->cpu_env, tmp);
23
tcg_temp_free_i32(tmp);
24
- dc->is_jmp = DISAS_UPDATE;
25
+ dc->is_jmp = DISAS_NORETURN;
19
}
26
}
20
27
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
28
static bool use_goto_tb(DisasContext *dc, uint32_t dest)
22
+{
29
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *dc, uint32_t excp)
23
+ TCGv_i32 v = tcg_temp_new_i32();
30
tcg_gen_movi_tl(cpu_R[R_PC], dc->pc);
24
+
31
gen_helper_raise_exception(cpu_env, tmp);
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
32
tcg_temp_free_i32(tmp);
26
+ return v;
33
- dc->is_jmp = DISAS_UPDATE;
27
+}
34
+ dc->is_jmp = DISAS_NORETURN;
28
+
35
}
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
36
30
* If SVE is not enabled, then there are only 128 bits in the vector.
37
/* generate intermediate code for basic block 'tb'. */
31
*/
38
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
39
tcg_gen_exit_tb(NULL, 0);
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
40
break;
34
{
41
35
TCGv_ptr fpst = NULL;
42
+ case DISAS_NORETURN:
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
43
case DISAS_TB_JUMP:
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
44
/* nothing more to generate */
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
45
break;
39
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
41
-
42
switch (opcode) {
43
case 0x0: /* FMOV */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
48
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
79
80
if (is_scalar) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
90
--
46
--
91
2.17.0
47
2.20.1
92
48
93
49
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Wentong Wu <wentong.wu@intel.com>
2
2
3
These were missed out from the rest of the half-precision work.
3
In line the semantics of DISAS_UPDATE on nios2 target with other targets
4
which is to explicitly write the PC back into the cpu state before doing
5
a tcg_gen_exit_tb().
4
6
5
Cc: qemu-stable@nongnu.org
7
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200710233433.19729-2-wentong.wu@intel.com
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
12
target/nios2/translate.c | 2 +-
16
1 file changed, 25 insertions(+), 6 deletions(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
17
14
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
17
--- a/target/nios2/translate.c
21
+++ b/target/arm/translate-a64.c
18
+++ b/target/nios2/translate.c
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
23
unsigned int mos, type, rm, cond, rn, rd;
20
/* Indicate where the next block should start */
24
TCGv_i64 t_true, t_false, t_zero;
21
switch (dc->is_jmp) {
25
DisasCompare64 c;
22
case DISAS_NEXT:
26
+ TCGMemOp sz;
23
+ case DISAS_UPDATE:
27
24
/* Save the current PC back into the CPU register */
28
mos = extract32(insn, 29, 3);
25
tcg_gen_movi_tl(cpu_R[R_PC], dc->pc);
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
26
tcg_gen_exit_tb(NULL, 0);
30
+ type = extract32(insn, 22, 2);
27
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
31
rm = extract32(insn, 16, 5);
28
32
cond = extract32(insn, 12, 4);
29
default:
33
rn = extract32(insn, 5, 5);
30
case DISAS_JUMP:
34
rd = extract32(insn, 0, 5);
31
- case DISAS_UPDATE:
35
32
/* The jump will already have updated the PC register */
36
- if (mos || type > 1) {
33
tcg_gen_exit_tb(NULL, 0);
37
+ if (mos) {
34
break;
38
+ unallocated_encoding(s);
39
+ return;
40
+ }
41
+
42
+ switch (type) {
43
+ case 0:
44
+ sz = MO_32;
45
+ break;
46
+ case 1:
47
+ sz = MO_64;
48
+ break;
49
+ case 3:
50
+ sz = MO_16;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
52
+ break;
53
+ }
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
60
return;
61
}
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
83
--
35
--
84
2.17.0
36
2.20.1
85
37
86
38
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Wentong Wu <wentong.wu@intel.com>
2
2
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
3
wrctl instruction on nios2 target will cause checking cpu
4
later on so we might as well mirror that.
4
interrupt but tcg_handle_interrupt() will call cpu_abort()
5
if the CPU gets an interrupt while it's not in 'can do IO'
6
state, so add gen_io_start around wrctl instruction. Also
7
at the same time, end the onging TB with DISAS_UPDATE.
5
8
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200710233433.19729-3-wentong.wu@intel.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
fpu/softfloat.c | 2 +-
14
target/nios2/translate.c | 5 +++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 5 insertions(+)
13
16
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
17
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
19
--- a/target/nios2/translate.c
17
+++ b/fpu/softfloat.c
20
+++ b/target/nios2/translate.c
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
21
@@ -XXX,XX +XXX,XX @@
19
22
#include "exec/cpu_ldst.h"
20
static FloatParts int_to_float(int64_t a, float_status *status)
23
#include "exec/translator.h"
21
{
24
#include "qemu/qemu-print.h"
22
- FloatParts r;
25
+#include "exec/gen-icount.h"
23
+ FloatParts r = {};
26
24
if (a == 0) {
27
/* is_jmp field values */
25
r.cls = float_class_zero;
28
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
26
r.sign = false;
29
@@ -XXX,XX +XXX,XX @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
30
/* If interrupts were enabled using WRCTL, trigger them. */
31
#if !defined(CONFIG_USER_ONLY)
32
if ((instr.imm5 + CR_BASE) == CR_STATUS) {
33
+ if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
34
+ gen_io_start();
35
+ }
36
gen_helper_check_interrupts(dc->cpu_env);
37
+ dc->is_jmp = DISAS_UPDATE;
38
}
39
#endif
40
}
27
--
41
--
28
2.17.0
42
2.20.1
29
43
30
44
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Wentong Wu <wentong.wu@intel.com>
2
2
3
We are meant to explicitly pass fpst, not cpu_env.
3
Only when guest code is unmasking interrupts, terminate the excution
4
of translated code and exit to the main CPU loop to handle previous
5
pended interrupts because of the interrupts mask by guest code.
4
6
5
Cc: qemu-stable@nongnu.org
7
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200710233433.19729-4-wentong.wu@intel.com
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/translate-a64.c | 3 ++-
12
hw/nios2/cpu_pic.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 2 insertions(+), 1 deletion(-)
15
14
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
17
--- a/hw/nios2/cpu_pic.c
19
+++ b/target/arm/translate-a64.c
18
+++ b/hw/nios2/cpu_pic.c
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
19
@@ -XXX,XX +XXX,XX @@ static void nios2_pic_cpu_handler(void *opaque, int irq, int level)
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
20
22
break;
21
void nios2_check_interrupts(CPUNios2State *env)
23
case 0x3: /* FSQRT */
22
{
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
23
- if (env->irq_pending) {
25
+ fpst = get_fpstatus_ptr(true);
24
+ if (env->irq_pending &&
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
25
+ (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
27
break;
26
env->irq_pending = 0;
28
case 0x8: /* FRINTN */
27
cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
29
case 0x9: /* FRINTP */
28
}
30
--
29
--
31
2.17.0
30
2.20.1
32
31
33
32
diff view generated by jsdifflib
New patch
1
Remove the hardcoded tabs from hw/arm/tosa.c. There aren't
2
many, but since they're all in constant #defines they're not
3
going to go away with our usual "only when we touch a function"
4
policy on reformatting.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200628203748.14250-2-peter.maydell@linaro.org
9
---
10
hw/arm/tosa.c | 44 ++++++++++++++++++++++----------------------
11
1 file changed, 22 insertions(+), 22 deletions(-)
12
13
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/tosa.c
16
+++ b/hw/arm/tosa.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/sysbus.h"
19
#include "exec/address-spaces.h"
20
21
-#define TOSA_RAM 0x04000000
22
-#define TOSA_ROM    0x00800000
23
+#define TOSA_RAM 0x04000000
24
+#define TOSA_ROM 0x00800000
25
26
-#define TOSA_GPIO_USB_IN        (5)
27
-#define TOSA_GPIO_nSD_DETECT    (9)
28
-#define TOSA_GPIO_ON_RESET        (19)
29
-#define TOSA_GPIO_CF_IRQ        (21)    /* CF slot0 Ready */
30
-#define TOSA_GPIO_CF_CD            (13)
31
-#define TOSA_GPIO_TC6393XB_INT (15)
32
-#define TOSA_GPIO_JC_CF_IRQ        (36)    /* CF slot1 Ready */
33
+#define TOSA_GPIO_USB_IN (5)
34
+#define TOSA_GPIO_nSD_DETECT (9)
35
+#define TOSA_GPIO_ON_RESET (19)
36
+#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
37
+#define TOSA_GPIO_CF_CD (13)
38
+#define TOSA_GPIO_TC6393XB_INT (15)
39
+#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
40
41
-#define TOSA_SCOOP_GPIO_BASE    1
42
-#define TOSA_GPIO_IR_POWERDWN    (TOSA_SCOOP_GPIO_BASE + 2)
43
-#define TOSA_GPIO_SD_WP            (TOSA_SCOOP_GPIO_BASE + 3)
44
-#define TOSA_GPIO_PWR_ON        (TOSA_SCOOP_GPIO_BASE + 4)
45
+#define TOSA_SCOOP_GPIO_BASE 1
46
+#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
47
+#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
48
+#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
49
50
-#define TOSA_SCOOP_JC_GPIO_BASE        1
51
-#define TOSA_GPIO_BT_LED        (TOSA_SCOOP_JC_GPIO_BASE + 0)
52
-#define TOSA_GPIO_NOTE_LED        (TOSA_SCOOP_JC_GPIO_BASE + 1)
53
-#define TOSA_GPIO_CHRG_ERR_LED        (TOSA_SCOOP_JC_GPIO_BASE + 2)
54
-#define TOSA_GPIO_TC6393XB_L3V_ON    (TOSA_SCOOP_JC_GPIO_BASE + 5)
55
-#define TOSA_GPIO_WLAN_LED        (TOSA_SCOOP_JC_GPIO_BASE + 7)
56
+#define TOSA_SCOOP_JC_GPIO_BASE 1
57
+#define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0)
58
+#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
59
+#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
60
+#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
61
+#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
62
63
-#define    DAC_BASE    0x4e
64
-#define DAC_CH1        0
65
-#define DAC_CH2        1
66
+#define DAC_BASE 0x4e
67
+#define DAC_CH1 0
68
+#define DAC_CH2 1
69
70
static void tosa_microdrive_attach(PXA2xxState *cpu)
71
{
72
--
73
2.20.1
74
75
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently we have a free-floating set of IRQs and a function
2
tosa_out_switch() which handle the GPIO lines on the tosa board which
3
connect to LEDs, and another free-floating IRQ and tosa_reset()
4
function to handle the GPIO line that resets the system. Encapsulate
5
this behaviour in a simple QOM device.
2
6
3
We missed all of the scalar fp16 binary operations.
7
This commit fixes Coverity issue CID 1421929 (which pointed out that
8
the 'outsignals' in tosa_gpio_setup() were leaked), because it
9
removes the use of the qemu_allocate_irqs() API from this code
10
entirely.
4
11
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200628203748.14250-3-peter.maydell@linaro.org
11
---
15
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
16
hw/arm/tosa.c | 88 +++++++++++++++++++++++++++++++++++++--------------
13
1 file changed, 65 insertions(+)
17
1 file changed, 64 insertions(+), 24 deletions(-)
14
18
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
21
--- a/hw/arm/tosa.c
18
+++ b/target/arm/translate-a64.c
22
+++ b/hw/arm/tosa.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
23
@@ -XXX,XX +XXX,XX @@ static void tosa_microdrive_attach(PXA2xxState *cpu)
20
tcg_temp_free_i64(tcg_res);
24
pxa2xx_pcmcia_attach(cpu->pcmcia[0], md);
21
}
25
}
22
26
23
+/* Floating-point data-processing (2 source) - half precision */
27
-static void tosa_out_switch(void *opaque, int line, int level)
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
28
+/*
25
+ int rd, int rn, int rm)
29
+ * Encapsulation of some GPIO line behaviour for the Tosa board
26
+{
30
+ *
27
+ TCGv_i32 tcg_op1;
31
+ * QEMU interface:
28
+ TCGv_i32 tcg_op2;
32
+ * + named GPIO inputs "leds[0..3]": assert to light LEDs
29
+ TCGv_i32 tcg_res;
33
+ * + named GPIO input "reset": when asserted, resets the system
30
+ TCGv_ptr fpst;
34
+ */
31
+
35
+
32
+ tcg_res = tcg_temp_new_i32();
36
+#define TYPE_TOSA_MISC_GPIO "tosa-misc-gpio"
33
+ fpst = get_fpstatus_ptr(true);
37
+#define TOSA_MISC_GPIO(obj) \
34
+ tcg_op1 = read_fp_hreg(s, rn);
38
+ OBJECT_CHECK(TosaMiscGPIOState, (obj), TYPE_TOSA_MISC_GPIO)
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
39
+
37
+ switch (opcode) {
40
+typedef struct TosaMiscGPIOState {
38
+ case 0x0: /* FMUL */
41
+ SysBusDevice parent_obj;
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
42
+} TosaMiscGPIOState;
43
+
44
+static void tosa_gpio_leds(void *opaque, int line, int level)
45
{
46
switch (line) {
47
- case 0:
48
- fprintf(stderr, "blue LED %s.\n", level ? "on" : "off");
49
- break;
50
- case 1:
51
- fprintf(stderr, "green LED %s.\n", level ? "on" : "off");
52
- break;
53
- case 2:
54
- fprintf(stderr, "amber LED %s.\n", level ? "on" : "off");
55
- break;
56
- case 3:
57
- fprintf(stderr, "wlan LED %s.\n", level ? "on" : "off");
58
- break;
59
- default:
60
- fprintf(stderr, "Uhandled out event: %d = %d\n", line, level);
61
- break;
62
+ case 0:
63
+ fprintf(stderr, "blue LED %s.\n", level ? "on" : "off");
40
+ break;
64
+ break;
41
+ case 0x1: /* FDIV */
65
+ case 1:
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
66
+ fprintf(stderr, "green LED %s.\n", level ? "on" : "off");
43
+ break;
67
+ break;
44
+ case 0x2: /* FADD */
68
+ case 2:
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
69
+ fprintf(stderr, "amber LED %s.\n", level ? "on" : "off");
46
+ break;
70
+ break;
47
+ case 0x3: /* FSUB */
71
+ case 3:
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
72
+ fprintf(stderr, "wlan LED %s.\n", level ? "on" : "off");
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
73
+ break;
66
+ default:
74
+ default:
67
+ g_assert_not_reached();
75
+ g_assert_not_reached();
68
+ }
76
}
77
}
78
79
@@ -XXX,XX +XXX,XX @@ static void tosa_reset(void *opaque, int line, int level)
80
}
81
}
82
83
+static void tosa_misc_gpio_init(Object *obj)
84
+{
85
+ DeviceState *dev = DEVICE(obj);
69
+
86
+
70
+ write_fp_sreg(s, rd, tcg_res);
87
+ qdev_init_gpio_in_named(dev, tosa_gpio_leds, "leds", 4);
71
+
88
+ qdev_init_gpio_in_named(dev, tosa_reset, "reset", 1);
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
89
+}
77
+
90
+
78
/* Floating point data-processing (2 source)
91
static void tosa_gpio_setup(PXA2xxState *cpu,
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
92
DeviceState *scp0,
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
93
DeviceState *scp1,
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
94
TC6393xbState *tmio)
82
}
95
{
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
96
- qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4);
84
break;
97
- qemu_irq reset;
85
+ case 3:
98
+ DeviceState *misc_gpio;
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
99
+
87
+ unallocated_encoding(s);
100
+ misc_gpio = sysbus_create_simple(TYPE_TOSA_MISC_GPIO, -1, NULL);
88
+ return;
101
89
+ }
102
/* MMC/SD host */
90
+ if (!fp_access_check(s)) {
103
pxa2xx_mmci_handlers(cpu->mmc,
91
+ return;
104
@@ -XXX,XX +XXX,XX @@ static void tosa_gpio_setup(PXA2xxState *cpu,
92
+ }
105
qemu_irq_invert(qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_nSD_DETECT)));
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
106
94
+ break;
107
/* Handle reset */
95
default:
108
- reset = qemu_allocate_irq(tosa_reset, cpu, 0);
96
unallocated_encoding(s);
109
- qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET, reset);
97
}
110
+ qdev_connect_gpio_out(cpu->gpio, TOSA_GPIO_ON_RESET,
111
+ qdev_get_gpio_in_named(misc_gpio, "reset", 0));
112
113
/* PCMCIA signals: card's IRQ and Card-Detect */
114
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
115
@@ -XXX,XX +XXX,XX @@ static void tosa_gpio_setup(PXA2xxState *cpu,
116
qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_JC_CF_IRQ),
117
NULL);
118
119
- qdev_connect_gpio_out(scp1, TOSA_GPIO_BT_LED, outsignals[0]);
120
- qdev_connect_gpio_out(scp1, TOSA_GPIO_NOTE_LED, outsignals[1]);
121
- qdev_connect_gpio_out(scp1, TOSA_GPIO_CHRG_ERR_LED, outsignals[2]);
122
- qdev_connect_gpio_out(scp1, TOSA_GPIO_WLAN_LED, outsignals[3]);
123
+ qdev_connect_gpio_out(scp1, TOSA_GPIO_BT_LED,
124
+ qdev_get_gpio_in_named(misc_gpio, "leds", 0));
125
+ qdev_connect_gpio_out(scp1, TOSA_GPIO_NOTE_LED,
126
+ qdev_get_gpio_in_named(misc_gpio, "leds", 1));
127
+ qdev_connect_gpio_out(scp1, TOSA_GPIO_CHRG_ERR_LED,
128
+ qdev_get_gpio_in_named(misc_gpio, "leds", 2));
129
+ qdev_connect_gpio_out(scp1, TOSA_GPIO_WLAN_LED,
130
+ qdev_get_gpio_in_named(misc_gpio, "leds", 3));
131
132
qdev_connect_gpio_out(scp1, TOSA_GPIO_TC6393XB_L3V_ON, tc6393xb_l3v_get(tmio));
133
134
@@ -XXX,XX +XXX,XX @@ static const TypeInfo tosa_ssp_info = {
135
.class_init = tosa_ssp_class_init,
136
};
137
138
+static const TypeInfo tosa_misc_gpio_info = {
139
+ .name = "tosa-misc-gpio",
140
+ .parent = TYPE_SYS_BUS_DEVICE,
141
+ .instance_size = sizeof(TosaMiscGPIOState),
142
+ .instance_init = tosa_misc_gpio_init,
143
+ /*
144
+ * No class init required: device has no internal state so does not
145
+ * need to set up reset or vmstate, and has no realize method.
146
+ */
147
+};
148
+
149
static void tosa_register_types(void)
150
{
151
type_register_static(&tosa_dac_info);
152
type_register_static(&tosa_ssp_info);
153
+ type_register_static(&tosa_misc_gpio_info);
154
}
155
156
type_init(tosa_register_types)
98
--
157
--
99
2.17.0
158
2.20.1
100
159
101
160
diff view generated by jsdifflib
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
Remove hard-tabs from palm.c.
2
to diagnose problems, but sometimes you want to see the state of
3
the floating point registers as well. We don't want to enable that
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
6
2
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Li Qiang <liq3ea@gmail.com>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20200628214230.2592-2-peter.maydell@linaro.org
10
---
7
---
11
include/qemu/log.h | 1 +
8
hw/arm/palm.c | 64 +++++++++++++++++++++++++--------------------------
12
accel/tcg/cpu-exec.c | 9 ++++++---
9
1 file changed, 32 insertions(+), 32 deletions(-)
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
10
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
11
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
13
--- a/hw/arm/palm.c
19
+++ b/include/qemu/log.h
14
+++ b/hw/arm/palm.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
15
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
21
#define CPU_LOG_PAGE (1 << 14)
16
/* Palm Tunsgten|E support */
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
17
23
#define CPU_LOG_TB_OP_IND (1 << 16)
18
/* Shared GPIOs */
24
+#define CPU_LOG_TB_FPU (1 << 17)
19
-#define PALMTE_USBDETECT_GPIO    0
25
20
-#define PALMTE_USB_OR_DC_GPIO    1
26
/* Lock output for a series of related logs. Since this is not needed
21
-#define PALMTE_TSC_GPIO        4
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
22
-#define PALMTE_PINTDAV_GPIO    6
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
23
-#define PALMTE_MMC_WP_GPIO    8
29
index XXXXXXX..XXXXXXX 100644
24
-#define PALMTE_MMC_POWER_GPIO    9
30
--- a/accel/tcg/cpu-exec.c
25
-#define PALMTE_HDQ_GPIO        11
31
+++ b/accel/tcg/cpu-exec.c
26
-#define PALMTE_HEADPHONES_GPIO    14
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
27
-#define PALMTE_SPEAKER_GPIO    15
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
28
+#define PALMTE_USBDETECT_GPIO 0
34
&& qemu_log_in_addr_range(itb->pc)) {
29
+#define PALMTE_USB_OR_DC_GPIO 1
35
qemu_log_lock();
30
+#define PALMTE_TSC_GPIO 4
36
+ int flags = 0;
31
+#define PALMTE_PINTDAV_GPIO 6
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
32
+#define PALMTE_MMC_WP_GPIO 8
38
+ flags |= CPU_DUMP_FPU;
33
+#define PALMTE_MMC_POWER_GPIO 9
39
+ }
34
+#define PALMTE_HDQ_GPIO 11
40
#if defined(TARGET_I386)
35
+#define PALMTE_HEADPHONES_GPIO 14
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
36
+#define PALMTE_SPEAKER_GPIO 15
42
-#else
37
/* MPU private GPIOs */
43
- log_cpu_state(cpu, 0);
38
-#define PALMTE_DC_GPIO        2
44
+ flags |= CPU_DUMP_CCOP;
39
-#define PALMTE_MMC_SWITCH_GPIO    4
45
#endif
40
-#define PALMTE_MMC1_GPIO    6
46
+ log_cpu_state(cpu, flags);
41
-#define PALMTE_MMC2_GPIO    7
47
qemu_log_unlock();
42
-#define PALMTE_MMC3_GPIO    11
48
}
43
+#define PALMTE_DC_GPIO 2
49
#endif /* DEBUG_DISAS */
44
+#define PALMTE_MMC_SWITCH_GPIO 4
50
diff --git a/util/log.c b/util/log.c
45
+#define PALMTE_MMC1_GPIO 6
51
index XXXXXXX..XXXXXXX 100644
46
+#define PALMTE_MMC2_GPIO 7
52
--- a/util/log.c
47
+#define PALMTE_MMC3_GPIO 11
53
+++ b/util/log.c
48
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
49
static MouseTransformInfo palmte_pointercal = {
55
"show trace before each executed TB (lots of logs)" },
50
.x = 320,
56
{ CPU_LOG_TB_CPU, "cpu",
51
@@ -XXX,XX +XXX,XX @@ static struct {
57
"show CPU registers before entering a TB (lots of logs)" },
52
int column;
58
+ { CPU_LOG_TB_FPU, "fpu",
53
} palmte_keymap[0x80] = {
59
+ "include FPU registers in the 'cpu' logging" },
54
[0 ... 0x7f] = { -1, -1 },
60
{ CPU_LOG_MMU, "mmu",
55
- [0x3b] = { 0, 0 },    /* F1    -> Calendar */
61
"log MMU-related activities" },
56
- [0x3c] = { 1, 0 },    /* F2    -> Contacts */
62
{ CPU_LOG_PCALL, "pcall",
57
- [0x3d] = { 2, 0 },    /* F3    -> Tasks List */
58
- [0x3e] = { 3, 0 },    /* F4    -> Note Pad */
59
- [0x01] = { 4, 0 },    /* Esc    -> Power */
60
- [0x4b] = { 0, 1 },    /*      Left */
61
- [0x50] = { 1, 1 },    /*      Down */
62
- [0x48] = { 2, 1 },    /*     Up */
63
- [0x4d] = { 3, 1 },    /*     Right */
64
- [0x4c] = { 4, 1 },    /*      Centre */
65
- [0x39] = { 4, 1 },    /* Spc    -> Centre */
66
+ [0x3b] = { 0, 0 }, /* F1 -> Calendar */
67
+ [0x3c] = { 1, 0 }, /* F2 -> Contacts */
68
+ [0x3d] = { 2, 0 }, /* F3 -> Tasks List */
69
+ [0x3e] = { 3, 0 }, /* F4 -> Note Pad */
70
+ [0x01] = { 4, 0 }, /* Esc -> Power */
71
+ [0x4b] = { 0, 1 }, /* Left */
72
+ [0x50] = { 1, 1 }, /* Down */
73
+ [0x48] = { 2, 1 }, /* Up */
74
+ [0x4d] = { 3, 1 }, /* Right */
75
+ [0x4c] = { 4, 1 }, /* Centre */
76
+ [0x39] = { 4, 1 }, /* Spc -> Centre */
77
};
78
79
static void palmte_button_event(void *opaque, int keycode)
80
@@ -XXX,XX +XXX,XX @@ static void palmte_gpio_setup(struct omap_mpu_state_s *cpu)
81
[PALMTE_MMC_SWITCH_GPIO]));
82
83
misc_gpio = qemu_allocate_irqs(palmte_onoff_gpios, cpu, 7);
84
- qdev_connect_gpio_out(cpu->gpio, PALMTE_MMC_POWER_GPIO,    misc_gpio[0]);
85
- qdev_connect_gpio_out(cpu->gpio, PALMTE_SPEAKER_GPIO,    misc_gpio[1]);
86
- qdev_connect_gpio_out(cpu->gpio, 11,            misc_gpio[2]);
87
- qdev_connect_gpio_out(cpu->gpio, 12,            misc_gpio[3]);
88
- qdev_connect_gpio_out(cpu->gpio, 13,            misc_gpio[4]);
89
- omap_mpuio_out_set(cpu->mpuio, 1,                misc_gpio[5]);
90
- omap_mpuio_out_set(cpu->mpuio, 3,                misc_gpio[6]);
91
+ qdev_connect_gpio_out(cpu->gpio, PALMTE_MMC_POWER_GPIO, misc_gpio[0]);
92
+ qdev_connect_gpio_out(cpu->gpio, PALMTE_SPEAKER_GPIO, misc_gpio[1]);
93
+ qdev_connect_gpio_out(cpu->gpio, 11, misc_gpio[2]);
94
+ qdev_connect_gpio_out(cpu->gpio, 12, misc_gpio[3]);
95
+ qdev_connect_gpio_out(cpu->gpio, 13, misc_gpio[4]);
96
+ omap_mpuio_out_set(cpu->mpuio, 1, misc_gpio[5]);
97
+ omap_mpuio_out_set(cpu->mpuio, 3, misc_gpio[6]);
98
99
/* Reset some inputs to initial state. */
100
qemu_irq_lower(qdev_get_gpio_in(cpu->gpio, PALMTE_USBDETECT_GPIO));
63
--
101
--
64
2.17.0
102
2.20.1
65
103
66
104
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Replace the free-floating set of IRQs and palmte_onoff_gpios()
2
function with a simple QOM device that encapsulates this
3
behaviour.
2
4
3
These where missed out from the rest of the half-precision work.
5
This fixes Coverity issue CID 1421944, which points out that
6
the memory returned by qemu_allocate_irqs() is leaked.
4
7
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Li Qiang <liq3ea@gmail.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200628214230.2592-3-peter.maydell@linaro.org
14
---
12
---
15
target/arm/helper-a64.h | 2 +
13
hw/arm/palm.c | 61 +++++++++++++++++++++++++++++++++++++++++++--------
16
target/arm/helper-a64.c | 10 +++++
14
1 file changed, 52 insertions(+), 9 deletions(-)
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
15
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
16
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
18
--- a/hw/arm/palm.c
23
+++ b/target/arm/helper-a64.h
19
+++ b/hw/arm/palm.c
24
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void palmte_button_event(void *opaque, int keycode)
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
21
!(keycode & 0x80));
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
36
+++ b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
38
return flags;
39
}
22
}
40
23
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
24
+/*
25
+ * Encapsulation of some GPIO line behaviour for the Palm board
26
+ *
27
+ * QEMU interface:
28
+ * + unnamed GPIO inputs 0..6: for the various miscellaneous input lines
29
+ */
30
+
31
+#define TYPE_PALM_MISC_GPIO "palm-misc-gpio"
32
+#define PALM_MISC_GPIO(obj) \
33
+ OBJECT_CHECK(PalmMiscGPIOState, (obj), TYPE_PALM_MISC_GPIO)
34
+
35
+typedef struct PalmMiscGPIOState {
36
+ SysBusDevice parent_obj;
37
+} PalmMiscGPIOState;
38
+
39
static void palmte_onoff_gpios(void *opaque, int line, int level)
40
{
41
switch (line) {
42
@@ -XXX,XX +XXX,XX @@ static void palmte_onoff_gpios(void *opaque, int line, int level)
43
}
44
}
45
46
+static void palm_misc_gpio_init(Object *obj)
42
+{
47
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
48
+ DeviceState *dev = DEVICE(obj);
49
+
50
+ qdev_init_gpio_in(dev, palmte_onoff_gpios, 7);
44
+}
51
+}
45
+
52
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
53
+static const TypeInfo palm_misc_gpio_info = {
54
+ .name = TYPE_PALM_MISC_GPIO,
55
+ .parent = TYPE_SYS_BUS_DEVICE,
56
+ .instance_size = sizeof(PalmMiscGPIOState),
57
+ .instance_init = palm_misc_gpio_init,
58
+ /*
59
+ * No class init required: device has no internal state so does not
60
+ * need to set up reset or vmstate, and has no realize method.
61
+ */
62
+};
63
+
64
static void palmte_gpio_setup(struct omap_mpu_state_s *cpu)
65
{
66
- qemu_irq *misc_gpio;
67
+ DeviceState *misc_gpio;
68
+
69
+ misc_gpio = sysbus_create_simple(TYPE_PALM_MISC_GPIO, -1, NULL);
70
71
omap_mmc_handlers(cpu->mmc,
72
qdev_get_gpio_in(cpu->gpio, PALMTE_MMC_WP_GPIO),
73
qemu_irq_invert(omap_mpuio_in_get(cpu->mpuio)
74
[PALMTE_MMC_SWITCH_GPIO]));
75
76
- misc_gpio = qemu_allocate_irqs(palmte_onoff_gpios, cpu, 7);
77
- qdev_connect_gpio_out(cpu->gpio, PALMTE_MMC_POWER_GPIO, misc_gpio[0]);
78
- qdev_connect_gpio_out(cpu->gpio, PALMTE_SPEAKER_GPIO, misc_gpio[1]);
79
- qdev_connect_gpio_out(cpu->gpio, 11, misc_gpio[2]);
80
- qdev_connect_gpio_out(cpu->gpio, 12, misc_gpio[3]);
81
- qdev_connect_gpio_out(cpu->gpio, 13, misc_gpio[4]);
82
- omap_mpuio_out_set(cpu->mpuio, 1, misc_gpio[5]);
83
- omap_mpuio_out_set(cpu->mpuio, 3, misc_gpio[6]);
84
+ qdev_connect_gpio_out(cpu->gpio, PALMTE_MMC_POWER_GPIO,
85
+ qdev_get_gpio_in(misc_gpio, 0));
86
+ qdev_connect_gpio_out(cpu->gpio, PALMTE_SPEAKER_GPIO,
87
+ qdev_get_gpio_in(misc_gpio, 1));
88
+ qdev_connect_gpio_out(cpu->gpio, 11, qdev_get_gpio_in(misc_gpio, 2));
89
+ qdev_connect_gpio_out(cpu->gpio, 12, qdev_get_gpio_in(misc_gpio, 3));
90
+ qdev_connect_gpio_out(cpu->gpio, 13, qdev_get_gpio_in(misc_gpio, 4));
91
+ omap_mpuio_out_set(cpu->mpuio, 1, qdev_get_gpio_in(misc_gpio, 5));
92
+ omap_mpuio_out_set(cpu->mpuio, 3, qdev_get_gpio_in(misc_gpio, 6));
93
94
/* Reset some inputs to initial state. */
95
qemu_irq_lower(qdev_get_gpio_in(cpu->gpio, PALMTE_USBDETECT_GPIO));
96
@@ -XXX,XX +XXX,XX @@ static void palmte_machine_init(MachineClass *mc)
97
}
98
99
DEFINE_MACHINE("cheetah", palmte_machine_init)
100
+
101
+static void palm_register_types(void)
47
+{
102
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
103
+ type_register_static(&palm_misc_gpio_info);
49
+}
104
+}
50
+
105
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
106
+type_init(palm_register_types)
52
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
60
}
61
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
63
+static void handle_fp_compare(DisasContext *s, int size,
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
165
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
107
--
215
2.17.0
108
2.20.1
216
109
217
110
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
3
Since added in commit 2bea128c3d, each SDHCI is wired with a SD
4
card, using empty card when no block drive provided. This is not
5
the desired behavior. The SDHCI exposes a SD bus to plug cards
6
on, if no card available, it is fine to have an unplugged bus.
4
7
5
The block length is predefined to 512 bits
8
Avoid creating unnecessary SD card device when no block drive
9
provided.
6
10
7
and "4.10.2 SD Status":
11
Fixes: 2bea128c3d ("hw/sd/aspeed_sdhci: New device")
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
13
Message-id: 20200705173402.15620-1-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
16
---
21
hw/sd/sd.c | 2 +-
17
hw/arm/aspeed.c | 9 +++++----
22
1 file changed, 1 insertion(+), 1 deletion(-)
18
1 file changed, 5 insertions(+), 4 deletions(-)
23
19
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
20
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
25
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
22
--- a/hw/arm/aspeed.c
27
+++ b/hw/sd/sd.c
23
+++ b/hw/arm/aspeed.c
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
24
@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
25
{
30
}
26
DeviceState *card;
31
memset(&sd->data[17], 0, 47);
27
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
28
- card = qdev_new(TYPE_SD_CARD);
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
29
- if (dinfo) {
34
}
30
- qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
35
31
- &error_fatal);
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
32
+ if (!dinfo) {
33
+ return;
34
}
35
+ card = qdev_new(TYPE_SD_CARD);
36
+ qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
37
+ &error_fatal);
38
qdev_realize_and_unref(card,
39
qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
40
&error_fatal);
37
--
41
--
38
2.17.0
42
2.20.1
39
43
40
44
diff view generated by jsdifflib