The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

* Fix coverity nit in int_to_float code

* Don't set Invalid for float-to-int(MAXINT)

* Fix fp_status_f16 tininess before rounding

* Add various missing insns from the v8.2-FP16 extension

* Fix sqrt_f16 exception raising

* sdcard: Correct CRC16 offset in sd_function_switch()

* tcg: Optionally log FPU state in TCG -d cpu logging

Alex Bennée (5):

fpu/softfloat: int_to_float ensure r fully initialised

target/arm: Implement FCMP for fp16

target/arm: Implement FCSEL for fp16

target/arm: Implement FMOV (immediate) for fp16

target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):

fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

target/arm: Fix fp_status_f16 tininess before rounding

tcg: Optionally log FPU state in TCG -d cpu logging

sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):

target/arm: Implement FMOV (general) for fp16

target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

target/arm: Implement FCVT (scalar, integer) for fp16

target/arm: Implement FCVT (scalar, fixed-point) for fp16

target/arm: Introduce and use read_fp_hreg

target/arm: Implement FP data-processing (2 source) for fp16

target/arm: Implement FP data-processing (3 source) for fp16

include/qemu/log.h | 1 +

target/arm/helper-a64.h | 2 +

target/arm/helper.h | 6 +

accel/tcg/cpu-exec.c | 9 +-

fpu/softfloat.c | 6 +-

hw/sd/sd.c | 2 +-

target/arm/cpu.c | 2 +

target/arm/helper-a64.c | 10 ++

target/arm/helper.c | 38 +++-

target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------

util/log.c | 2 +

11 files changed, 428 insertions(+), 71 deletions(-)

Usually the logging of the CPU state produced by -d cpu is sufficient

to diagnose problems, but sometimes you want to see the state of

the floating point registers as well. We don't want to enable that

by default as it adds a lot of extra data to the log; instead,

allow it to be optionally enabled via -d fpu.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180510130024.31678-1-peter.maydell@linaro.org

include/qemu/log.h | 1 +

accel/tcg/cpu-exec.c | 9 ++++++---

util/log.c | 2 ++

3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/qemu/log.h b/include/qemu/log.h

--- a/include/qemu/log.h

+++ b/include/qemu/log.h

@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)

#define CPU_LOG_PAGE (1 << 14)

/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */

#define CPU_LOG_TB_OP_IND (1 << 16)

+#define CPU_LOG_TB_FPU (1 << 17)

/* Lock output for a series of related logs. Since this is not needed

* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)

if (qemu_loglevel_mask(CPU_LOG_TB_CPU)

&& qemu_log_in_addr_range(itb->pc)) {

qemu_log_lock();

+ int flags = 0;

+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {

+ flags |= CPU_DUMP_FPU;

+ }

#if defined(TARGET_I386)

- log_cpu_state(cpu, CPU_DUMP_CCOP);

-#else

- log_cpu_state(cpu, 0);

+ flags |= CPU_DUMP_CCOP;

#endif

+ log_cpu_state(cpu, flags);

qemu_log_unlock();

}

#endif /* DEBUG_DISAS */

diff --git a/util/log.c b/util/log.c

index XXXXXXX..XXXXXXX 100644

--- a/util/log.c

+++ b/util/log.c

@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {

"show trace before each executed TB (lots of logs)" },

{ CPU_LOG_TB_CPU, "cpu",

"show CPU registers before entering a TB (lots of logs)" },

+ { CPU_LOG_TB_FPU, "fpu",

+ "include FPU registers in the 'cpu' logging" },

{ CPU_LOG_MMU, "mmu",

"log MMU-related activities" },

{ CPU_LOG_PCALL, "pcall",

2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

Cc: qemu-stable@nongnu.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-6-richard.henderson@linaro.org

target/arm/translate-a64.c | 30 ++++++++++++++----------------

1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)

return v;

+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)

+ TCGv_i32 v = tcg_temp_new_i32();

+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));

+ return v;

/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).

* If SVE is not enabled, then there are only 128 bits in the vector.

*/

@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)

static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)

TCGv_ptr fpst = NULL;

- TCGv_i32 tcg_op = tcg_temp_new_i32();

+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);

TCGv_i32 tcg_res = tcg_temp_new_i32();

- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);

-

switch (opcode) {

case 0x0: /* FMOV */

tcg_gen_mov_i32(tcg_res, tcg_op);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)

tcg_temp_free_i64(tcg_op2);

tcg_temp_free_i64(tcg_res);

} else {

- TCGv_i32 tcg_op1 = tcg_temp_new_i32();

- TCGv_i32 tcg_op2 = tcg_temp_new_i32();

+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);

+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);

TCGv_i64 tcg_res = tcg_temp_new_i64();

- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);

- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);

-

gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);

gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,

fpst = get_fpstatus_ptr(true);

- tcg_op1 = tcg_temp_new_i32();

- tcg_op2 = tcg_temp_new_i32();

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

tcg_res = tcg_temp_new_i32();

- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);

- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);

-

switch (fpopcode) {

case 0x03: /* FMULX */

gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)

if (is_scalar) {

- TCGv_i32 tcg_op = tcg_temp_new_i32();

+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);

TCGv_i32 tcg_res = tcg_temp_new_i32();

- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);

-

switch (fpop) {

case 0x1a: /* FCVTNS */

case 0x1b: /* FCVTMS */

2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

We missed all of the scalar fp16 fma operations.

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-8-richard.henderson@linaro.org

target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++

1 file changed, 48 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,

tcg_temp_free_i64(tcg_res);

+/* Floating-point data-processing (3 source) - half precision */

+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,

+ int rd, int rn, int rm, int ra)

+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;

+ TCGv_i32 tcg_res = tcg_temp_new_i32();

+ TCGv_ptr fpst = get_fpstatus_ptr(true);

+

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

+ tcg_op3 = read_fp_hreg(s, ra);

+

+ /* These are fused multiply-add, and must be done as one

+ * floating point operation with no rounding between the

+ * multiplication and addition steps.

+ * NB that doing the negations here as separate steps is

+ * correct : an input NaN should come out with its sign bit

+ * flipped if it is a negated-input.

+ */

+ if (o1 == true) {

+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);

+ }

+

+ if (o0 != o1) {

+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);

+ }

+

+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);

+

+ write_fp_sreg(s, rd, tcg_res);

+

+ tcg_temp_free_ptr(fpst);

+ tcg_temp_free_i32(tcg_op1);

+ tcg_temp_free_i32(tcg_op2);

+ tcg_temp_free_i32(tcg_op3);

+ tcg_temp_free_i32(tcg_res);

/* Floating point data-processing (3 source)

* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0

* +---+---+---+-----------+------+----+------+----+------+------+------+

@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)

}

handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);

break;

+ case 3:

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ unallocated_encoding(s);

+ return;

+ }

+ if (!fp_access_check(s)) {

+ return;

+ }

+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);

+ break;

default:

unallocated_encoding(s);

}

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These where missed out from the rest of the half-precision work.

Cc: qemu-stable@nongnu.org

target/arm/helper-a64.h | 2 +

target/arm/helper-a64.c | 10 +++++

target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------

3 files changed, 83 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h

--- a/target/arm/helper-a64.h

+++ b/target/arm/helper-a64.h

DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)

DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)

DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)

+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)

+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)

DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper-a64.c

+++ b/target/arm/helper-a64.c

@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)

return flags;

+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)

+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));

+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)

+ return float_rel_to_flags(float16_compare(x, y, fp_status));

uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)

{

return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)

}

}

-static void handle_fp_compare(DisasContext *s, bool is_double,

+static void handle_fp_compare(DisasContext *s, int size,

unsigned int rn, unsigned int rm,

bool cmp_with_zero, bool signal_all_nans)

{

TCGv_i64 tcg_flags = tcg_temp_new_i64();

- TCGv_ptr fpst = get_fpstatus_ptr(false);

+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);

- if (is_double) {

+ if (size == MO_64) {

TCGv_i64 tcg_vn, tcg_vm;

tcg_vn = read_fp_dreg(s, rn);

@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,

tcg_temp_free_i64(tcg_vn);

tcg_temp_free_i64(tcg_vm);

} else {

- TCGv_i32 tcg_vn, tcg_vm;

+ TCGv_i32 tcg_vn = tcg_temp_new_i32();

+ TCGv_i32 tcg_vm = tcg_temp_new_i32();

- tcg_vn = read_fp_sreg(s, rn);

+ read_vec_element_i32(s, tcg_vn, rn, 0, size);

if (cmp_with_zero) {

- tcg_vm = tcg_const_i32(0);

+ tcg_gen_movi_i32(tcg_vm, 0);

} else {

- tcg_vm = read_fp_sreg(s, rm);

+ read_vec_element_i32(s, tcg_vm, rm, 0, size);

}

- if (signal_all_nans) {

- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

- } else {

- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ switch (size) {

+ case MO_32:

+ if (signal_all_nans) {

+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ } else {

+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ }

+ break;

+ case MO_16:

+ if (signal_all_nans) {

+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ } else {

+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ }

+ break;

+ default:

+ g_assert_not_reached();

}

+

tcg_temp_free_i32(tcg_vn);

tcg_temp_free_i32(tcg_vm);

}

@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,

static void disas_fp_compare(DisasContext *s, uint32_t insn)

{

unsigned int mos, type, rm, op, rn, opc, op2r;

+ int size;

mos = extract32(insn, 29, 3);

- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */

+ type = extract32(insn, 22, 2);

rm = extract32(insn, 16, 5);

op = extract32(insn, 14, 2);

rn = extract32(insn, 5, 5);

opc = extract32(insn, 3, 2);

op2r = extract32(insn, 0, 3);

- if (mos || op || op2r || type > 1) {

+ if (mos || op || op2r) {

+ unallocated_encoding(s);

+ switch (type) {

+ case 0:

+ size = MO_32;

+ break;

+ case 1:

+ size = MO_64;

+ break;

+ case 3:

+ size = MO_16;

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)

return;

}

- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);

+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);

}

/* Floating point conditional compare

@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)

unsigned int mos, type, rm, cond, rn, op, nzcv;

TCGv_i64 tcg_flags;

TCGLabel *label_continue = NULL;

+ int size;

mos = extract32(insn, 29, 3);

- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */

+ type = extract32(insn, 22, 2);

rm = extract32(insn, 16, 5);

cond = extract32(insn, 12, 4);

rn = extract32(insn, 5, 5);

op = extract32(insn, 4, 1);

nzcv = extract32(insn, 0, 4);

- if (mos || type > 1) {

+ if (mos) {

+ unallocated_encoding(s);

+ switch (type) {

+ case 0:

+ size = MO_32;

+ break;

+ case 1:

+ size = MO_64;

+ break;

+ case 3:

+ size = MO_16;

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ }

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)

gen_set_label(label_match);

}

- handle_fp_compare(s, type, rn, rm, false, op);

+ handle_fp_compare(s, size, rn, rm, false, op);

if (cond < 0x0e) {

gen_set_label(label_continue);

2.17.0

Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":

The block length is predefined to 512 bits

and "4.10.2 SD Status":

The SD Status contains status bits that are related to the SD Memory Card

proprietary features and may be used for future application-specific usage.

The size of the SD Status is one data block of 512 bit. The content of this

register is transmitted to the Host over the DAT bus along with a 16-bit CRC.

Thus the 16-bit CRC goes at offset 64.

Message-id: 20180509060104.4458-3-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/sd/sd.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c

--- a/hw/sd/sd.c

+++ b/hw/sd/sd.c

@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)

sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);

}

memset(&sd->data[17], 0, 47);

- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));

+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));

}

static inline bool sd_wp_addr(SDState *sd, uint64_t addr)

2.17.0