The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

* Fix coverity nit in int_to_float code

* Don't set Invalid for float-to-int(MAXINT)

* Fix fp_status_f16 tininess before rounding

* Add various missing insns from the v8.2-FP16 extension

* Fix sqrt_f16 exception raising

* sdcard: Correct CRC16 offset in sd_function_switch()

* tcg: Optionally log FPU state in TCG -d cpu logging

Alex Bennée (5):

fpu/softfloat: int_to_float ensure r fully initialised

target/arm: Implement FCMP for fp16

target/arm: Implement FCSEL for fp16

target/arm: Implement FMOV (immediate) for fp16

target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):

fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

target/arm: Fix fp_status_f16 tininess before rounding

tcg: Optionally log FPU state in TCG -d cpu logging

sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):

target/arm: Implement FMOV (general) for fp16

target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

target/arm: Implement FCVT (scalar, integer) for fp16

target/arm: Implement FCVT (scalar, fixed-point) for fp16

target/arm: Introduce and use read_fp_hreg

target/arm: Implement FP data-processing (2 source) for fp16

target/arm: Implement FP data-processing (3 source) for fp16

From: Richard Henderson <richard.henderson@linaro.org>

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-4-richard.henderson@linaro.org

target/arm/helper.h | 6 +++

target/arm/helper.c | 38 ++++++++++++++-

target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------

3 files changed, 122 insertions(+), 18 deletions(-)

@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)

#undef VFP_CONV_FIX_A64

/* Conversion to/from f16 can overflow to infinity before/after scaling.

- * Therefore we convert to f64 (which does not round), scale,

- * and then convert f64 to f16 (which may round).

+ * Therefore we convert to f64, scale, and then convert f64 to f16; or

+ * vice versa for conversion to integer.

+ *

+ * For 16- and 32-bit integers, the conversion to f64 never rounds.

+ * For 64-bit integers, any integer that would cause rounding will also

+ * overflow to f16 infinity, so there is no double rounding problem.

*/

static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)

@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)

return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);

}

+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)

+{

+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);

+}

+

+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)

+{

+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);

+}

+

static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)

{

if (unlikely(float16_is_any_nan(f))) {

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)

return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);

}

+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

/* Set the current fp rounding mode and return the old one.

* The argument is a softfloat float_round_ value.

*/

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

bool itof, int rmode, int scale, int sf, int type)

{

bool is_signed = !(opcode & 1);

- bool is_double = type;

TCGv_ptr tcg_fpstatus;

- TCGv_i32 tcg_shift;

+ TCGv_i32 tcg_shift, tcg_single;

+ TCGv_i64 tcg_double;

- tcg_fpstatus = get_fpstatus_ptr(false);

+ tcg_fpstatus = get_fpstatus_ptr(type == 3);

tcg_shift = tcg_const_i32(64 - scale);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_int = tcg_extend;

}

- if (is_double) {

- TCGv_i64 tcg_double = tcg_temp_new_i64();

+ switch (type) {

+ case 1: /* float64 */

+ tcg_double = tcg_temp_new_i64();

if (is_signed) {

gen_helper_vfp_sqtod(tcg_double, tcg_int,

tcg_shift, tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

}

write_fp_dreg(s, rd, tcg_double);

tcg_temp_free_i64(tcg_double);

- } else {

- TCGv_i32 tcg_single = tcg_temp_new_i32();

+ break;

+

+ case 0: /* float32 */

+ tcg_single = tcg_temp_new_i32();

if (is_signed) {

gen_helper_vfp_sqtos(tcg_single, tcg_int,

tcg_shift, tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

}

write_fp_sreg(s, rd, tcg_single);

tcg_temp_free_i32(tcg_single);

+ break;

+

+ case 3: /* float16 */

+ tcg_single = tcg_temp_new_i32();

+ if (is_signed) {

+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,

+ tcg_shift, tcg_fpstatus);

+ }

+ write_fp_sreg(s, rd, tcg_single);

+ tcg_temp_free_i32(tcg_single);

+ break;

+

+ default:

+ g_assert_not_reached();

}

} else {

TCGv_i64 tcg_int = cpu_reg(s, rd);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);

- if (is_double) {

- TCGv_i64 tcg_double = read_fp_dreg(s, rn);

+ switch (type) {

+ case 1: /* float64 */

+ tcg_double = read_fp_dreg(s, rn);

if (is_signed) {

if (!sf) {

gen_helper_vfp_tosld(tcg_int, tcg_double,

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_shift, tcg_fpstatus);

}

}

+ if (!sf) {

+ tcg_gen_ext32u_i64(tcg_int, tcg_int);

+ }

tcg_temp_free_i64(tcg_double);

- } else {

- TCGv_i32 tcg_single = read_fp_sreg(s, rn);

+ break;

+

+ case 0: /* float32 */

+ tcg_single = read_fp_sreg(s, rn);

if (sf) {

if (is_signed) {

gen_helper_vfp_tosqs(tcg_int, tcg_single,

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_temp_free_i32(tcg_dest);

}

tcg_temp_free_i32(tcg_single);

+ break;

+

+ case 3: /* float16 */

+ tcg_single = read_fp_sreg(s, rn);

+ if (sf) {

+ if (is_signed) {

+ gen_helper_vfp_tosqh(tcg_int, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_touqh(tcg_int, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ }

+ } else {

+ TCGv_i32 tcg_dest = tcg_temp_new_i32();

+ if (is_signed) {

+ gen_helper_vfp_toslh(tcg_dest, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_toulh(tcg_dest, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ }

+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);

+ tcg_temp_free_i32(tcg_dest);

+ }

+ tcg_temp_free_i32(tcg_single);

+ break;

+

+ default:

+ g_assert_not_reached();

}

gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);

tcg_temp_free_i32(tcg_rmode);

-

- if (!sf) {

- tcg_gen_ext32u_i64(tcg_int, tcg_int);

- }

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These where missed out from the rest of the half-precision work.

target/arm/helper-a64.h | 2 +

target/arm/helper-a64.c | 10 +++++

target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------

3 files changed, 83 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h

--- a/target/arm/helper-a64.h

+++ b/target/arm/helper-a64.h

DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)

DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)

DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)

+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)

+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)

DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

--- a/target/arm/helper-a64.c

+++ b/target/arm/helper-a64.c

@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)

return flags;

}

+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)

+{

+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));

+}

+

+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)

+{

+ return float_rel_to_flags(float16_compare(x, y, fp_status));

+}

+

uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)

{

return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)

2.17.0

In commit d81ce0ef2c4f105 we added an extra float_status field

fp_status_fp16 for Arm, but forgot to initialize it correctly

by setting it to float_tininess_before_rounding. This currently

will only cause problems for the new V8_FP16 feature, since the

float-to-float conversion code doesn't use it yet. The effect

would be that we failed to set the Underflow IEEE exception flag

in all the cases where we should.

Add the missing initialization.

Fixes: d81ce0ef2c4f105

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512004311.9299-16-richard.henderson@linaro.org

target/arm/cpu.c | 2 ++

1 file changed, 2 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

&env->vfp.fp_status);

set_float_detect_tininess(float_tininess_before_rounding,

&env->vfp.standard_fp_status);

+ set_float_detect_tininess(float_tininess_before_rounding,

+ &env->vfp.fp_status_f16);

#ifndef CONFIG_USER_ONLY

if (kvm_enabled()) {

kvm_arm_reset_vcpu(cpu);

2.17.0