The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

* Fix coverity nit in int_to_float code

* Don't set Invalid for float-to-int(MAXINT)

* Fix fp_status_f16 tininess before rounding

* Add various missing insns from the v8.2-FP16 extension

* Fix sqrt_f16 exception raising

* sdcard: Correct CRC16 offset in sd_function_switch()

* tcg: Optionally log FPU state in TCG -d cpu logging

Alex Bennée (5):

fpu/softfloat: int_to_float ensure r fully initialised

target/arm: Implement FCMP for fp16

target/arm: Implement FCSEL for fp16

target/arm: Implement FMOV (immediate) for fp16

target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):

fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

target/arm: Fix fp_status_f16 tininess before rounding

tcg: Optionally log FPU state in TCG -d cpu logging

sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):

target/arm: Implement FMOV (general) for fp16

target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

target/arm: Implement FCVT (scalar, integer) for fp16

target/arm: Implement FCVT (scalar, fixed-point) for fp16

target/arm: Introduce and use read_fp_hreg

target/arm: Implement FP data-processing (2 source) for fp16

target/arm: Implement FP data-processing (3 source) for fp16

include/qemu/log.h | 1 +

target/arm/helper-a64.h | 2 +

target/arm/helper.h | 6 +

accel/tcg/cpu-exec.c | 9 +-

fpu/softfloat.c | 6 +-

hw/sd/sd.c | 2 +-

target/arm/cpu.c | 2 +

target/arm/helper-a64.c | 10 ++

target/arm/helper.c | 38 +++-

target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------

util/log.c | 2 +

11 files changed, 428 insertions(+), 71 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Adding the fp16 moves to/from general registers.

Cc: qemu-stable@nongnu.org

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-2-richard.henderson@linaro.org

target/arm/translate-a64.c | 21 +++++++++++++++++++++

1 file changed, 21 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)

tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));

clear_vec_high(s, true, rd);

break;

+ case 3:

+ /* 16 bit */

+ tmp = tcg_temp_new_i64();

+ tcg_gen_ext16u_i64(tmp, tcg_rn);

+ write_fp_dreg(s, rd, tmp);

+ tcg_temp_free_i64(tmp);

+ break;

+ default:

+ g_assert_not_reached();

}

} else {

TCGv_i64 tcg_rd = cpu_reg(s, rd);

@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)

/* 64 bits from top half */

tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));

break;

+ case 3:

+ /* 16 bit */

+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));

+ break;

+ default:

+ g_assert_not_reached();

}

}

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)

case 0xa: /* 64 bit */

case 0xd: /* 64 bit to top half of quad */

break;

+ case 0x6: /* 16-bit float, 32-bit int */

+ case 0xe: /* 16-bit float, 64-bit int */

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ }

+ /* fallthru */

default:

/* all other sf/type/rmode combinations are invalid */

unallocated_encoding(s);

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These where missed out from the rest of the half-precision work.

Cc: qemu-stable@nongnu.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180512003217.9105-9-richard.henderson@linaro.org

[rth: Diagnose lack of FP16 before fp_access_check]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper-a64.h | 2 +

target/arm/helper-a64.c | 10 +++++

target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------

3 files changed, 83 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h

--- a/target/arm/helper-a64.h

+++ b/target/arm/helper-a64.h

DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)

DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)

DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)

+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)

+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)

DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

--- a/target/arm/helper-a64.c

+++ b/target/arm/helper-a64.c

@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)

return flags;

+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)

+{

+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));

+}

+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)

+{

+ return float_rel_to_flags(float16_compare(x, y, fp_status));

+}

+

uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)

return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)

2.17.0

In float-to-integer conversion, if the floating point input

converts exactly to the largest or smallest integer that

fits in to the result type, this is not an overflow.

In this situation we were producing the correct result value,

but were incorrectly setting the Invalid flag.

For example for Arm A64, "FCVTAS w0, d0" on an input of

0x41dfffffffc00000 should produce 0x7fffffff and set no flags.

Message-id: 20180510140141.12120-1-peter.maydell@linaro.org

fpu/softfloat.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c

--- a/fpu/softfloat.c

+++ b/fpu/softfloat.c

@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,

r = UINT64_MAX;

}

if (p.sign) {

- if (r < -(uint64_t) min) {

+ if (r <= -(uint64_t) min) {

return -r;

} else {

s->float_exception_flags = orig_flags | float_flag_invalid;

return min;

}

} else {

- if (r < max) {

+ if (r <= max) {

return r;

} else {

s->float_exception_flags = orig_flags | float_flag_invalid;

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

Reported by Coverity (CID1390635). We ensure this for uint_to_float

later on so we might as well mirror that.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

fpu/softfloat.c | 2 +-

diff --git a/fpu/softfloat.c b/fpu/softfloat.c

--- a/fpu/softfloat.c

+++ b/fpu/softfloat.c

@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)

static FloatParts int_to_float(int64_t a, float_status *status)

{

- FloatParts r;

+ FloatParts r = {};

if (a == 0) {

r.cls = float_class_zero;

r.sign = false;

2.17.0

Usually the logging of the CPU state produced by -d cpu is sufficient

to diagnose problems, but sometimes you want to see the state of

the floating point registers as well. We don't want to enable that

by default as it adds a lot of extra data to the log; instead,

allow it to be optionally enabled via -d fpu.

Message-id: 20180510130024.31678-1-peter.maydell@linaro.org

include/qemu/log.h | 1 +

accel/tcg/cpu-exec.c | 9 ++++++---

util/log.c | 2 ++

3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/qemu/log.h b/include/qemu/log.h

--- a/include/qemu/log.h

+++ b/include/qemu/log.h

@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)

#define CPU_LOG_PAGE (1 << 14)

/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */

#define CPU_LOG_TB_OP_IND (1 << 16)

+#define CPU_LOG_TB_FPU (1 << 17)

/* Lock output for a series of related logs. Since this is not needed

* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)

if (qemu_loglevel_mask(CPU_LOG_TB_CPU)

&& qemu_log_in_addr_range(itb->pc)) {

qemu_log_lock();

+ int flags = 0;

+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {

+ flags |= CPU_DUMP_FPU;

#if defined(TARGET_I386)

- log_cpu_state(cpu, CPU_DUMP_CCOP);

-#else

- log_cpu_state(cpu, 0);

+ flags |= CPU_DUMP_CCOP;

#endif

+ log_cpu_state(cpu, flags);

qemu_log_unlock();

}

#endif /* DEBUG_DISAS */

diff --git a/util/log.c b/util/log.c

index XXXXXXX..XXXXXXX 100644

--- a/util/log.c

+++ b/util/log.c

@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {

"show trace before each executed TB (lots of logs)" },

{ CPU_LOG_TB_CPU, "cpu",

"show CPU registers before entering a TB (lots of logs)" },

+ { CPU_LOG_TB_FPU, "fpu",

+ "include FPU registers in the 'cpu' logging" },

{ CPU_LOG_MMU, "mmu",

"log MMU-related activities" },

{ CPU_LOG_PCALL, "pcall",

2.17.0

We missed all of the scalar fp16 binary operations.

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-7-richard.henderson@linaro.org

target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++

1 file changed, 65 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,

tcg_temp_free_i64(tcg_res);

+/* Floating-point data-processing (2 source) - half precision */

+static void handle_fp_2src_half(DisasContext *s, int opcode,

+ int rd, int rn, int rm)

+{

+ TCGv_i32 tcg_op1;

+ TCGv_i32 tcg_op2;

+ TCGv_i32 tcg_res;

+ TCGv_ptr fpst;

+

+ tcg_res = tcg_temp_new_i32();

+ fpst = get_fpstatus_ptr(true);

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

+

+ switch (opcode) {

+ case 0x0: /* FMUL */

+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x1: /* FDIV */

+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x2: /* FADD */

+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x3: /* FSUB */

+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x4: /* FMAX */

+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x5: /* FMIN */

+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x6: /* FMAXNM */

+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x7: /* FMINNM */

+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x8: /* FNMUL */

+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);

+ break;

+ default:

+ g_assert_not_reached();

+ }

+

+ write_fp_sreg(s, rd, tcg_res);

+

+ tcg_temp_free_ptr(fpst);

+ tcg_temp_free_i32(tcg_op1);

+ tcg_temp_free_i32(tcg_op2);

+ tcg_temp_free_i32(tcg_res);

+}

+

/* Floating point data-processing (2 source)

* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0

* +---+---+---+-----------+------+---+------+--------+-----+------+------+

@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)

}

handle_fp_2src_double(s, opcode, rd, rn, rm);

break;

+ case 3:

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ unallocated_encoding(s);

+ return;

+ }

+ if (!fp_access_check(s)) {

+ return;

+ }

+ handle_fp_2src_half(s, opcode, rd, rn, rm);

+ break;

default:

unallocated_encoding(s);

2.17.0

We missed all of the scalar fp16 fma operations.

Cc: qemu-stable@nongnu.org

Message-id: 20180512003217.9105-8-richard.henderson@linaro.org

target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++

1 file changed, 48 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,

tcg_temp_free_i64(tcg_res);

+/* Floating-point data-processing (3 source) - half precision */

+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,

+ int rd, int rn, int rm, int ra)

+{

+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;

+ TCGv_i32 tcg_res = tcg_temp_new_i32();

+ TCGv_ptr fpst = get_fpstatus_ptr(true);

+

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

+ tcg_op3 = read_fp_hreg(s, ra);

+

+ /* These are fused multiply-add, and must be done as one

+ * floating point operation with no rounding between the

+ * multiplication and addition steps.

+ * NB that doing the negations here as separate steps is

+ * correct : an input NaN should come out with its sign bit

+ * flipped if it is a negated-input.

+ */

+ if (o1 == true) {

+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);

+ }

+

+ if (o0 != o1) {

+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);

+ }

+

+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);

+

+ write_fp_sreg(s, rd, tcg_res);

+

+ tcg_temp_free_ptr(fpst);

+ tcg_temp_free_i32(tcg_op1);

+ tcg_temp_free_i32(tcg_op2);

+ tcg_temp_free_i32(tcg_op3);

+ tcg_temp_free_i32(tcg_res);

+}

+

/* Floating point data-processing (3 source)

* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0

* +---+---+---+-----------+------+----+------+----+------+------+------+

@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)

}

handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);

break;

+ case 3:

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ unallocated_encoding(s);

+ return;

+ }

+ if (!fp_access_check(s)) {

+ return;

+ }

+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);

+ break;

default:

unallocated_encoding(s);

}

2.17.0

Cc: qemu-stable@nongnu.org

Message-id: 20180512003217.9105-4-richard.henderson@linaro.org

target/arm/helper.h | 6 +++

target/arm/helper.c | 38 ++++++++++++++-

target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------

3 files changed, 122 insertions(+), 18 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)

DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)

+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)

+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)

+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)

+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)

DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)

DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)

DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)

DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)

+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)

+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)

DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)

DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)

#undef VFP_CONV_FIX_A64

/* Conversion to/from f16 can overflow to infinity before/after scaling.

- * Therefore we convert to f64 (which does not round), scale,

- * and then convert f64 to f16 (which may round).

+ * Therefore we convert to f64, scale, and then convert f64 to f16; or

+ * vice versa for conversion to integer.

+ *

+ * For 16- and 32-bit integers, the conversion to f64 never rounds.

+ * For 64-bit integers, any integer that would cause rounding will also

+ * overflow to f16 infinity, so there is no double rounding problem.

*/

static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)

@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)

return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);

}

+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)

+{

+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);

+}

+

+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)

+{

+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);

+}

+

static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)

{

if (unlikely(float16_is_any_nan(f))) {

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)

return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);

}

+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

/* Set the current fp rounding mode and return the old one.

* The argument is a softfloat float_round_ value.

*/

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

bool itof, int rmode, int scale, int sf, int type)

{

bool is_signed = !(opcode & 1);

- bool is_double = type;

TCGv_ptr tcg_fpstatus;

- TCGv_i32 tcg_shift;

+ TCGv_i32 tcg_shift, tcg_single;

+ TCGv_i64 tcg_double;

- tcg_fpstatus = get_fpstatus_ptr(false);

+ tcg_fpstatus = get_fpstatus_ptr(type == 3);

tcg_shift = tcg_const_i32(64 - scale);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_int = tcg_extend;

- if (is_double) {

- TCGv_i64 tcg_double = tcg_temp_new_i64();

+ switch (type) {

+ case 1: /* float64 */

+ tcg_double = tcg_temp_new_i64();

if (is_signed) {

gen_helper_vfp_sqtod(tcg_double, tcg_int,

tcg_shift, tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

}

write_fp_dreg(s, rd, tcg_double);

tcg_temp_free_i64(tcg_double);

- } else {

- TCGv_i32 tcg_single = tcg_temp_new_i32();

+ break;

+

+ case 0: /* float32 */

+ tcg_single = tcg_temp_new_i32();

if (is_signed) {

gen_helper_vfp_sqtos(tcg_single, tcg_int,

tcg_shift, tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

}

write_fp_sreg(s, rd, tcg_single);

tcg_temp_free_i32(tcg_single);

+ break;

+

+ case 3: /* float16 */

+ tcg_single = tcg_temp_new_i32();

+ if (is_signed) {

+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,

+ tcg_shift, tcg_fpstatus);

+ }

+ write_fp_sreg(s, rd, tcg_single);

+ tcg_temp_free_i32(tcg_single);

+ break;

+

+ default:

+ g_assert_not_reached();

} else {

TCGv_i64 tcg_int = cpu_reg(s, rd);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);

- if (is_double) {

- TCGv_i64 tcg_double = read_fp_dreg(s, rn);

+ switch (type) {

+ case 1: /* float64 */

+ tcg_double = read_fp_dreg(s, rn);

if (is_signed) {

if (!sf) {

gen_helper_vfp_tosld(tcg_int, tcg_double,

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_shift, tcg_fpstatus);

}

}

+ if (!sf) {

+ tcg_gen_ext32u_i64(tcg_int, tcg_int);

+ }

tcg_temp_free_i64(tcg_double);

- } else {

- TCGv_i32 tcg_single = read_fp_sreg(s, rn);

+ break;

+

+ case 0: /* float32 */

+ tcg_single = read_fp_sreg(s, rn);

if (sf) {

if (is_signed) {

gen_helper_vfp_tosqs(tcg_int, tcg_single,

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_temp_free_i32(tcg_dest);

}

tcg_temp_free_i32(tcg_single);

+ break;

+

+ case 3: /* float16 */

+ tcg_single = read_fp_sreg(s, rn);

+ if (sf) {

+ if (is_signed) {

+ gen_helper_vfp_tosqh(tcg_int, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_touqh(tcg_int, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ }

+ } else {

+ TCGv_i32 tcg_dest = tcg_temp_new_i32();

+ if (is_signed) {

+ gen_helper_vfp_toslh(tcg_dest, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_toulh(tcg_dest, tcg_single,

+ tcg_shift, tcg_fpstatus);

+ }

+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);

+ tcg_temp_free_i32(tcg_dest);

+ }

+ tcg_temp_free_i32(tcg_single);

+ break;

+

+ default:

+ g_assert_not_reached();

}

gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);

tcg_temp_free_i32(tcg_rmode);

-

- if (!sf) {

- tcg_gen_ext32u_i64(tcg_int, tcg_int);

tcg_temp_free_ptr(tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)

/* actual FP conversions */

bool itof = extract32(opcode, 1, 1);

- if (type > 1 || (rmode != 0 && opcode > 1)) {

+ if (rmode != 0 && opcode > 1) {

+ unallocated_encoding(s);

+ return;

+ }

+ switch (type) {

+ case 0: /* float32 */

+ case 1: /* float64 */

+ break;

+ case 3: /* float16 */

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ }

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

2.17.0

Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":

The block length is predefined to 512 bits

and "4.10.2 SD Status":

The SD Status contains status bits that are related to the SD Memory Card

proprietary features and may be used for future application-specific usage.

The size of the SD Status is one data block of 512 bit. The content of this

register is transmitted to the Host over the DAT bus along with a 16-bit CRC.

Thus the 16-bit CRC goes at offset 64.

Message-id: 20180509060104.4458-3-f4bug@amsat.org

hw/sd/sd.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c

--- a/hw/sd/sd.c

+++ b/hw/sd/sd.c

@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)

sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);

}

memset(&sd->data[17], 0, 47);

- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));

+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));

static inline bool sd_wp_addr(SDState *sd, uint64_t addr)