target-arm queue: Eric's SMMUv3 patchset, and an array

of minor bugfixes and improvements from various others.

The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9:

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180504

for you to fetch changes up to 5680740c92993e9b3f3e011f2a2c394070e33f56:

hw/arm/virt: Introduce the iommu option (2018-05-04 18:05:52 +0100)

* Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board

if the commandline includes "-machine iommu=smmuv3"

* target/arm: Implement v8M VLLDM and VLSTM

* hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode

* Some fixes to silence Coverity false-positives

* arm: boot: set boot_info starting from first_cpu

(fixes a technical bug not visible in practice)

* hw/net/smc91c111: Convert away from old_mmio

* hw/usb/tusb6010: Convert away from old_mmio

* hw/char/cmsdk-apb-uart.c: Accept more input after character read

* target/arm: Make MPUIR write-ignored on OMAP, StrongARM

* hw/arm/virt: Add linux,pci-domain property

Eric Auger (11):

hw/arm/smmu-common: smmu base device and datatypes

hw/arm/smmu-common: IOMMU memory region and address space setup

hw/arm/smmu-common: VMSAv8-64 page table walk

hw/arm/smmuv3: Wired IRQ and GERROR helpers

hw/arm/smmuv3: Queue helpers

hw/arm/smmuv3: Implement MMIO write operations

hw/arm/smmuv3: Event queue recording helper

hw/arm/smmuv3: Implement translate callback

hw/arm/smmuv3: Abort on vfio or vhost case

target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route

hw/arm/virt: Introduce the iommu option

Igor Mammedov (1):

arm: boot: set boot_info starting from first_cpu

Jan Kiszka (1):

hw/arm/virt: Add linux,pci-domain property

Mathew Maidment (1):

target/arm: Correct MPUIR privilege level in register_cp_regs_for_features() conditional case

Patrick Oppenlander (1):

hw/char/cmsdk-apb-uart.c: Accept more input after character read

Peter Maydell (3):

hw/usb/tusb6010: Convert away from old_mmio

hw/net/smc91c111: Convert away from old_mmio

target/arm: Implement v8M VLLDM and VLSTM

Prem Mallappa (3):

hw/arm/smmuv3: Skeleton

hw/arm/virt: Add SMMUv3 to the virt board

hw/arm/virt-acpi-build: Add smmuv3 node in IORT table

Richard Henderson (2):

target/arm: Tidy conditions in handle_vec_simd_shri

target/arm: Tidy condition in disas_simd_two_reg_misc

Thomas Huth (1):

hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode

From: Patrick Oppenlander <patrick.oppenlander@gmail.com>

The character frontend needs to be notified that the uart receive buffer

is empty and ready to handle another character.

Previously, the uart only worked correctly when receiving one character

at a time.

Signed-off-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>

Message-id: CAEg67GkRTw=cXei3o9hvpxG_L4zSrNzR0bFyAgny+sSEUb_kPw@mail.gmail.com

hw/char/cmsdk-apb-uart.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c

--- a/hw/char/cmsdk-apb-uart.c

+++ b/hw/char/cmsdk-apb-uart.c

@@ -XXX,XX +XXX,XX @@ static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size)

r = s->rxbuf;

s->state &= ~R_STATE_RXFULL_MASK;

cmsdk_apb_uart_update(s);

+ qemu_chr_fe_accept_input(&s->chr);

break;

case A_STATE:

r = s->state;

2.17.0

From: Eric Auger <eric.auger@redhat.com>

This patch implements the page table walk for VMSAv8-64.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com>

Message-id: 1524665762-31355-4-git-send-email-eric.auger@redhat.com

hw/arm/smmu-internal.h | 99 ++++++++++++++++

include/hw/arm/smmu-common.h | 14 +++

hw/arm/smmu-common.c | 222 +++++++++++++++++++++++++++++++++++

hw/arm/trace-events | 9 +-

4 files changed, 343 insertions(+), 1 deletion(-)

create mode 100644 hw/arm/smmu-internal.h

diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h

+++ b/hw/arm/smmu-internal.h

+ * ARM SMMU support - Internal API

+ * Copyright (c) 2017 Red Hat, Inc.

+ * Copyright (C) 2014-2016 Broadcom Corporation

+ * Written by Prem Mallappa, Eric Auger

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License along

+ * with this program; if not, see <http://www.gnu.org/licenses/>.

+#ifndef HW_ARM_SMMU_INTERNAL_H

+#define HW_ARM_SMMU_INTERNAL_H

+#define TBI0(tbi) ((tbi) & 0x1)

+#define TBI1(tbi) ((tbi) & 0x2 >> 1)

+/* PTE Manipulation */

+

+#define ARM_LPAE_PTE_TYPE_SHIFT 0

+#define ARM_LPAE_PTE_TYPE_MASK 0x3

+

+#define ARM_LPAE_PTE_TYPE_BLOCK 1

+#define ARM_LPAE_PTE_TYPE_TABLE 3

+

+#define ARM_LPAE_L3_PTE_TYPE_RESERVED 1

+#define ARM_LPAE_L3_PTE_TYPE_PAGE 3

+

+#define ARM_LPAE_PTE_VALID (1 << 0)

+

+#define PTE_ADDRESS(pte, shift) \

+ (extract64(pte, shift, 47 - shift + 1) << shift)

+

+#define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID))

+

+#define is_reserved_pte(pte, level) \

+ ((level == 3) && \

+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))

+

+#define is_block_pte(pte, level) \

+ ((level < 3) && \

+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))

+

+#define is_table_pte(pte, level) \

+ ((level < 3) && \

+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))

+

+#define is_page_pte(pte, level) \

+ ((level == 3) && \

+ ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE))

+

+/* access permissions */

+

+#define PTE_AP(pte) \

+ (extract64(pte, 6, 2))

+

+#define PTE_APTABLE(pte) \

+ (extract64(pte, 61, 2))

+

+/*

+ * TODO: At the moment all transactions are considered as privileged (EL1)

+ * as IOMMU translation callback does not pass user/priv attributes.

+ */

+#define is_permission_fault(ap, perm) \

+ (((perm) & IOMMU_WO) && ((ap) & 0x2))

+

+#define PTE_AP_TO_PERM(ap) \

+ (IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))

+

+/* Level Indexing */

+

+static inline int level_shift(int level, int granule_sz)

+{

+ return granule_sz + (3 - level) * (granule_sz - 3);

+}

+

+static inline uint64_t level_page_mask(int level, int granule_sz)

+{

+ return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz)));

+}

+

+static inline

+uint64_t iova_level_offset(uint64_t iova, int inputsize,

+ int level, int gsz)

+{

+ return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) &

+ MAKE_64BIT_MASK(0, gsz - 3);

+}

+

+#endif

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h

--- a/include/hw/arm/smmu-common.h

+++ b/include/hw/arm/smmu-common.h

@@ -XXX,XX +XXX,XX @@ static inline uint16_t smmu_get_sid(SMMUDevice *sdev)

{

return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);

}

+

+/**

+ * smmu_ptw - Perform the page table walk for a given iova / access flags

+ * pair, according to @cfg translation config

+ */

+int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,

+ IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);

+

+/**

+ * select_tt - compute which translation table shall be used according to

+ * the input iova and translation config and return the TT specific info

+ */

+SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);

+

#endif /* HW_ARM_SMMU_COMMON */

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/smmu-common.c

+++ b/hw/arm/smmu-common.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/error-report.h"

#include "hw/arm/smmu-common.h"

+#include "smmu-internal.h"

+

+/* VMSAv8-64 Translation */

+

+/**

+ * get_pte - Get the content of a page table entry located at

+ * @base_addr[@index]

+ */

+static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,

+ SMMUPTWEventInfo *info)

+{

+ int ret;

+ dma_addr_t addr = baseaddr + index * sizeof(*pte);

+

+ /* TODO: guarantee 64-bit single-copy atomicity */

+ ret = dma_memory_read(&address_space_memory, addr,

+ (uint8_t *)pte, sizeof(*pte));

+

+ if (ret != MEMTX_OK) {

+ info->type = SMMU_PTW_ERR_WALK_EABT;

+ info->addr = addr;

+ return -EINVAL;

+ }

+ trace_smmu_get_pte(baseaddr, index, addr, *pte);

+ return 0;

+}

+

+/* VMSAv8-64 Translation Table Format Descriptor Decoding */

+

+/**

+ * get_page_pte_address - returns the L3 descriptor output address,

+ * ie. the page frame

+ * ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format

+ */

+static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz)

+{

+ return PTE_ADDRESS(pte, granule_sz);

+}

+

+/**

+ * get_table_pte_address - return table descriptor output address,

+ * ie. address of next level table

+ * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats

+ */

+static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)

+{

+ return PTE_ADDRESS(pte, granule_sz);

+}

+

+/**

+ * get_block_pte_address - return block descriptor output address and block size

+ * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats

+ */

+static inline hwaddr get_block_pte_address(uint64_t pte, int level,

+ int granule_sz, uint64_t *bsz)

+{

+ int n = (granule_sz - 3) * (4 - level) + 3;

+

+ *bsz = 1 << n;

+ return PTE_ADDRESS(pte, n);

+}

+

+SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)

+{

+ bool tbi = extract64(iova, 55, 1) ? TBI1(cfg->tbi) : TBI0(cfg->tbi);

+ uint8_t tbi_byte = tbi * 8;

+

+ if (cfg->tt[0].tsz &&

+ !extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - tbi_byte)) {

+ /* there is a ttbr0 region and we are in it (high bits all zero) */

+ return &cfg->tt[0];

+ } else if (cfg->tt[1].tsz &&

+ !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {

+ /* there is a ttbr1 region and we are in it (high bits all one) */

+ return &cfg->tt[1];

+ } else if (!cfg->tt[0].tsz) {

+ /* ttbr0 region is "everything not in the ttbr1 region" */

+ return &cfg->tt[0];

+ } else if (!cfg->tt[1].tsz) {

+ /* ttbr1 region is "everything not in the ttbr0 region" */

+ return &cfg->tt[1];

+ }

+ /* in the gap between the two regions, this is a Translation fault */

+ return NULL;

+}

+

+/**

+ * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA

+ * @cfg: translation config

+ * @iova: iova to translate

+ * @perm: access type

+ * @tlbe: IOMMUTLBEntry (out)

+ * @info: handle to an error info

+ *

+ * Return 0 on success, < 0 on error. In case of error, @info is filled

+ * and tlbe->perm is set to IOMMU_NONE.

+ * Upon success, @tlbe is filled with translated_addr and entry

+ * permission rights.

+ */

+static int smmu_ptw_64(SMMUTransCfg *cfg,

+ dma_addr_t iova, IOMMUAccessFlags perm,

+ IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)

+{

+ dma_addr_t baseaddr, indexmask;

+ int stage = cfg->stage;

+ SMMUTransTableInfo *tt = select_tt(cfg, iova);

+ uint8_t level, granule_sz, inputsize, stride;

+

+ if (!tt || tt->disabled) {

+ info->type = SMMU_PTW_ERR_TRANSLATION;

+ goto error;

+ }

+

+ granule_sz = tt->granule_sz;

+ stride = granule_sz - 3;

+ inputsize = 64 - tt->tsz;

+ level = 4 - (inputsize - 4) / stride;

+ indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;

+ baseaddr = extract64(tt->ttb, 0, 48);

+ baseaddr &= ~indexmask;

+

+ tlbe->iova = iova;

+ tlbe->addr_mask = (1 << granule_sz) - 1;

+

+ while (level <= 3) {

+ uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);

+ uint64_t mask = subpage_size - 1;

+ uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);

+ uint64_t pte;

+ dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);

+ uint8_t ap;

+

+ if (get_pte(baseaddr, offset, &pte, info)) {

+ goto error;

+ }

+ trace_smmu_ptw_level(level, iova, subpage_size,

+ baseaddr, offset, pte);

+

+ if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {

+ trace_smmu_ptw_invalid_pte(stage, level, baseaddr,

+ pte_addr, offset, pte);

+ info->type = SMMU_PTW_ERR_TRANSLATION;

+ goto error;

+ }

+

+ if (is_page_pte(pte, level)) {

+ uint64_t gpa = get_page_pte_address(pte, granule_sz);

+

+ ap = PTE_AP(pte);

+ if (is_permission_fault(ap, perm)) {

+ info->type = SMMU_PTW_ERR_PERMISSION;

+ goto error;

+ }

+

+ tlbe->translated_addr = gpa + (iova & mask);

+ tlbe->perm = PTE_AP_TO_PERM(ap);

+ trace_smmu_ptw_page_pte(stage, level, iova,

+ baseaddr, pte_addr, pte, gpa);

+ return 0;

+ }

+ if (is_block_pte(pte, level)) {

+ uint64_t block_size;

+ hwaddr gpa = get_block_pte_address(pte, level, granule_sz,

+ &block_size);

+

+ ap = PTE_AP(pte);

+ if (is_permission_fault(ap, perm)) {

+ info->type = SMMU_PTW_ERR_PERMISSION;

+ goto error;

+ }

+

+ trace_smmu_ptw_block_pte(stage, level, baseaddr,

+ pte_addr, pte, iova, gpa,

+ block_size >> 20);

+

+ tlbe->translated_addr = gpa + (iova & mask);

+ tlbe->perm = PTE_AP_TO_PERM(ap);

+ return 0;

+ }

+

+ /* table pte */

+ ap = PTE_APTABLE(pte);

+

+ if (is_permission_fault(ap, perm)) {

+ info->type = SMMU_PTW_ERR_PERMISSION;

+ goto error;

+ }

+ baseaddr = get_table_pte_address(pte, granule_sz);

+ level++;

+ }

+

+ info->type = SMMU_PTW_ERR_TRANSLATION;

+

+error:

+ tlbe->perm = IOMMU_NONE;

+ return -EINVAL;

+}

+

+/**

+ * smmu_ptw - Walk the page tables for an IOVA, according to @cfg

+ *

+ * @cfg: translation configuration

+ * @iova: iova to translate

+ * @perm: tentative access type

+ * @tlbe: returned entry

+ * @info: ptw event handle

+ *

+ * return 0 on success

+ */

+inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,

+ IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)

+{

+ if (!cfg->aa64) {

+ /*

+ * This code path is not entered as we check this while decoding

+ * the configuration data in the derived SMMU model.

+ */

+ g_assert_not_reached();

+ }

+

+ return smmu_ptw_64(cfg, iova, perm, tlbe, info);

+}

/**

* The bus number is used for lookup when SID based invalidation occurs.

diff --git a/hw/arm/trace-events b/hw/arm/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/trace-events

+++ b/hw/arm/trace-events

@@ -XXX,XX +XXX,XX @@

virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."

# hw/arm/smmu-common.c

-smmu_add_mr(const char *name) "%s"

\ No newline at end of file

+smmu_add_mr(const char *name) "%s"

+smmu_page_walk(int stage, uint64_t baseaddr, int first_level, uint64_t start, uint64_t end) "stage=%d, baseaddr=0x%"PRIx64", first level=%d, start=0x%"PRIx64", end=0x%"PRIx64

+smmu_lookup_table(int level, uint64_t baseaddr, int granule_sz, uint64_t start, uint64_t end, int flags, uint64_t subpage_size) "level=%d baseaddr=0x%"PRIx64" granule=%d, start=0x%"PRIx64" end=0x%"PRIx64" flags=%d subpage_size=0x%"PRIx64

+smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%lx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64

+smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64

+smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64

+smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"

+smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64

2.17.0

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180501180455.11214-2-richard.henderson@linaro.org

target/arm/translate-a64.c | 6 +-----

1 file changed, 1 insertion(+), 5 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,

unallocated_encoding(s);

-

- if (size > 3 && !is_q) {

- unallocated_encoding(s);

- return;

- }

+ tcg_debug_assert(size <= 3);

if (!fp_access_check(s)) {

return;

2.17.0

From: Eric Auger <eric.auger@redhat.com>

In case the MSI is translated by an IOMMU we need to fixup the

MSI route with the translated address.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>

Message-id: 1524665762-31355-12-git-send-email-eric.auger@redhat.com

target/arm/kvm.c | 38 +++++++++++++++++++++++++++++++++++++-

target/arm/trace-events | 3 +++

2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c

--- a/target/arm/kvm.c

+++ b/target/arm/kvm.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/kvm.h"

#include "kvm_arm.h"

#include "cpu.h"

+#include "trace.h"

#include "internals.h"

#include "hw/arm/arm.h"

+#include "hw/pci/pci.h"

#include "exec/memattrs.h"

#include "exec/address-spaces.h"

#include "hw/boards.h"

@@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void)

int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,

uint64_t address, uint32_t data, PCIDevice *dev)

- return 0;

+ AddressSpace *as = pci_device_iommu_address_space(dev);

+ hwaddr xlat, len, doorbell_gpa;

+ MemoryRegionSection mrs;

+ MemoryRegion *mr;

+ int ret = 1;

+

+ if (as == &address_space_memory) {

+ return 0;

+ }

+

+ /* MSI doorbell address is translated by an IOMMU */

+

+ rcu_read_lock();

+ mr = address_space_translate(as, address, &xlat, &len, true);

+ if (!mr) {

+ goto unlock;

+ }

+ mrs = memory_region_find(mr, xlat, 1);

+ if (!mrs.mr) {

+ goto unlock;

+ }

+

+ doorbell_gpa = mrs.offset_within_address_space;

+ memory_region_unref(mrs.mr);

+

+ route->u.msi.address_lo = doorbell_gpa;

+ route->u.msi.address_hi = doorbell_gpa >> 32;

+

+ trace_kvm_arm_fixup_msi_route(address, doorbell_gpa);

+

+ ret = 0;

+

+unlock:

+ rcu_read_unlock();

+ return ret;

}

int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,

diff --git a/target/arm/trace-events b/target/arm/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/trace-events

+++ b/target/arm/trace-events

@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"

arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64

arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK toggle, new irqstate %d"

arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64

+

+# target/arm/kvm.c

+kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64

2.17.0

From: Eric Auger <eric.auger@redhat.com>

Let's introduce a helper function aiming at recording an

event in the event queue.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

hw/arm/smmuv3-internal.h | 148 ++++++++++++++++++++++++++++++++++++++-

hw/arm/smmuv3.c | 108 ++++++++++++++++++++++++++--

hw/arm/trace-events | 1 +

3 files changed, 249 insertions(+), 8 deletions(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h

--- a/hw/arm/smmuv3-internal.h

+++ b/hw/arm/smmuv3-internal.h

@@ -XXX,XX +XXX,XX @@ static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)

s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);

}

-void smmuv3_write_eventq(SMMUv3State *s, Evt *evt);

-

/* Commands */

typedef enum SMMUCommandType {

@@ -XXX,XX +XXX,XX @@ enum { /* Command completion notification */

#define SMMU_FEATURE_2LVL_STE (1 << 0)

+/* Events */

+

+typedef enum SMMUEventType {

+ SMMU_EVT_OK = 0x00,

+ SMMU_EVT_F_UUT ,

+ SMMU_EVT_C_BAD_STREAMID ,

+ SMMU_EVT_F_STE_FETCH ,

+ SMMU_EVT_C_BAD_STE ,

+ SMMU_EVT_F_BAD_ATS_TREQ ,

+ SMMU_EVT_F_STREAM_DISABLED ,

+ SMMU_EVT_F_TRANS_FORBIDDEN ,

+ SMMU_EVT_C_BAD_SUBSTREAMID ,

+ SMMU_EVT_F_CD_FETCH ,

+ SMMU_EVT_C_BAD_CD ,

+ SMMU_EVT_F_WALK_EABT ,

+ SMMU_EVT_F_TRANSLATION = 0x10,

+ SMMU_EVT_F_ADDR_SIZE ,

+ SMMU_EVT_F_ACCESS ,

+ SMMU_EVT_F_PERMISSION ,

+ SMMU_EVT_F_TLB_CONFLICT = 0x20,

+ SMMU_EVT_F_CFG_CONFLICT ,

+ SMMU_EVT_E_PAGE_REQ = 0x24,

+} SMMUEventType;

+

+static const char *event_stringify[] = {

+ [SMMU_EVT_OK] = "SMMU_EVT_OK",

+ [SMMU_EVT_F_UUT] = "SMMU_EVT_F_UUT",

+ [SMMU_EVT_C_BAD_STREAMID] = "SMMU_EVT_C_BAD_STREAMID",

+ [SMMU_EVT_F_STE_FETCH] = "SMMU_EVT_F_STE_FETCH",

+ [SMMU_EVT_C_BAD_STE] = "SMMU_EVT_C_BAD_STE",

+ [SMMU_EVT_F_BAD_ATS_TREQ] = "SMMU_EVT_F_BAD_ATS_TREQ",

+ [SMMU_EVT_F_STREAM_DISABLED] = "SMMU_EVT_F_STREAM_DISABLED",

+ [SMMU_EVT_F_TRANS_FORBIDDEN] = "SMMU_EVT_F_TRANS_FORBIDDEN",

+ [SMMU_EVT_C_BAD_SUBSTREAMID] = "SMMU_EVT_C_BAD_SUBSTREAMID",

+ [SMMU_EVT_F_CD_FETCH] = "SMMU_EVT_F_CD_FETCH",

+ [SMMU_EVT_C_BAD_CD] = "SMMU_EVT_C_BAD_CD",

+ [SMMU_EVT_F_WALK_EABT] = "SMMU_EVT_F_WALK_EABT",

+ [SMMU_EVT_F_TRANSLATION] = "SMMU_EVT_F_TRANSLATION",

+ [SMMU_EVT_F_ADDR_SIZE] = "SMMU_EVT_F_ADDR_SIZE",

+ [SMMU_EVT_F_ACCESS] = "SMMU_EVT_F_ACCESS",

+ [SMMU_EVT_F_PERMISSION] = "SMMU_EVT_F_PERMISSION",

+ [SMMU_EVT_F_TLB_CONFLICT] = "SMMU_EVT_F_TLB_CONFLICT",

+ [SMMU_EVT_F_CFG_CONFLICT] = "SMMU_EVT_F_CFG_CONFLICT",

+ [SMMU_EVT_E_PAGE_REQ] = "SMMU_EVT_E_PAGE_REQ",

+};

+

+static inline const char *smmu_event_string(SMMUEventType type)

+{

+ if (type < ARRAY_SIZE(event_stringify)) {

+ return event_stringify[type] ? event_stringify[type] : "UNKNOWN";

+ } else {

+ return "INVALID";

+ }

+}

+

+/* Encode an event record */

+typedef struct SMMUEventInfo {

+ SMMUEventType type;

+ uint32_t sid;

+ bool recorded;

+ bool record_trans_faults;

+ union {

+ struct {

+ uint32_t ssid;

+ bool ssv;

+ dma_addr_t addr;

+ bool rnw;

+ bool pnu;

+ bool ind;

+ } f_uut;

+ struct SSIDInfo {

+ uint32_t ssid;

+ bool ssv;

+ } c_bad_streamid;

+ struct SSIDAddrInfo {

+ uint32_t ssid;

+ bool ssv;

+ dma_addr_t addr;

+ } f_ste_fetch;

+ struct SSIDInfo c_bad_ste;

+ struct {

+ dma_addr_t addr;

+ bool rnw;

+ } f_transl_forbidden;

+ struct {

+ uint32_t ssid;

+ } c_bad_substream;

+ struct SSIDAddrInfo f_cd_fetch;

+ struct SSIDInfo c_bad_cd;

+ struct FullInfo {

+ bool stall;

+ uint16_t stag;

+ uint32_t ssid;

+ bool ssv;

+ bool s2;

+ dma_addr_t addr;

+ bool rnw;

+ bool pnu;

+ bool ind;

+ uint8_t class;

+ dma_addr_t addr2;

+ } f_walk_eabt;

+ struct FullInfo f_translation;

+ struct FullInfo f_addr_size;

+ struct FullInfo f_access;

+ struct FullInfo f_permission;

+ struct SSIDInfo f_cfg_conflict;

+ /**

+ * not supported yet:

+ * F_BAD_ATS_TREQ