1
First arm pullreq of the 2.13 cycle!
1
Arm queue; bugfixes only.
2
2
3
thanks
3
-- PMM
4
-- PMM
4
5
5
The following changes since commit 4743c23509a51bd4ee85cc272287a41917d1be35:
6
The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:
6
7
7
Update version for v2.12.0 release (2018-04-24 16:44:55 +0100)
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)
8
9
9
are available in the Git repository at:
10
are available in the Git repository at:
10
11
11
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180426
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117
12
13
13
for you to fetch changes up to fbf32752663878947de455ff57cb5b9318f14bec:
14
for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:
14
15
15
xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo (2018-04-26 11:04:40 +0100)
16
tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
target-arm queue:
19
target-arm queue:
19
* xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
20
* hw/arm/virt: ARM_VIRT must select ARM_GIC
20
* timer/aspeed: fix vmstate version id
21
* exynos: Fix bad printf format specifiers
21
* hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
22
* hw/input/ps2.c: Remove remnants of printf debug
22
* hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
23
* target/openrisc: Remove dead code attempting to check "is timer disabled"
23
* hw/arm/highbank: don't make sysram 'nomigrate'
24
* register: Remove unnecessary NULL check
24
* hw/arm/raspi: Don't bother setting default_cpu_type
25
* util/cutils: Fix Coverity array overrun in freq_to_str()
25
* PMU emulation: some minor bugfixes and preparation for
26
* configure: Make "does libgio work" test pull in some actual functions
26
support of other events than just the cycle counter
27
* tmp105: reset the T_low and T_High registers
27
* target/arm: Use v7m_stack_read() for reading the frame signature
28
* tmp105: Correct handling of temperature limit checks
28
* target/arm: Remove stale TODO comment
29
* arm: always start from first_cpu when registering loader cpu reset callback
30
* device_tree: Increase FDT_MAX_SIZE to 1 MiB
31
29
32
----------------------------------------------------------------
30
----------------------------------------------------------------
33
Aaron Lindsay (9):
31
Alex Chen (1):
34
target/arm: Check PMCNTEN for whether PMCCNTR is enabled
32
exynos: Fix bad printf format specifiers
35
target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
36
target/arm: Mask PMU register writes based on PMCR_EL0.N
37
target/arm: Fetch GICv3 state directly from CPUARMState
38
target/arm: Support multiple EL change hooks
39
target/arm: Add pre-EL change hooks
40
target/arm: Allow EL change hooks to do IO
41
target/arm: Fix bitmask for PMCCFILTR writes
42
target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide
43
33
44
Cédric Le Goater (1):
34
Alistair Francis (1):
45
timer/aspeed: fix vmstate version id
35
register: Remove unnecessary NULL check
46
36
47
Geert Uytterhoeven (1):
37
Andrew Jones (1):
48
device_tree: Increase FDT_MAX_SIZE to 1 MiB
38
hw/arm/virt: ARM_VIRT must select ARM_GIC
49
39
50
Igor Mammedov (1):
40
Peter Maydell (5):
51
arm: always start from first_cpu when registering loader cpu reset callback
41
hw/input/ps2.c: Remove remnants of printf debug
42
target/openrisc: Remove dead code attempting to check "is timer disabled"
43
configure: Make "does libgio work" test pull in some actual functions
44
hw/misc/tmp105: reset the T_low and T_High registers
45
tmp105: Correct handling of temperature limit checks
52
46
53
Peter Maydell (6):
47
Philippe Mathieu-Daudé (1):
54
target/arm: Remove stale TODO comment
48
util/cutils: Fix Coverity array overrun in freq_to_str()
55
target/arm: Use v7m_stack_read() for reading the frame signature
56
hw/arm/raspi: Don't bother setting default_cpu_type
57
hw/arm/highbank: don't make sysram 'nomigrate'
58
hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
59
hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
60
49
61
Sai Pavan Boddu (1):
50
configure | 11 +++++--
62
xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
51
hw/misc/tmp105.h | 7 +++++
52
hw/core/register.c | 4 ---
53
hw/input/ps2.c | 9 ------
54
hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------
55
hw/timer/exynos4210_mct.c | 4 +--
56
hw/timer/exynos4210_pwm.c | 8 ++---
57
target/openrisc/sys_helper.c | 3 --
58
util/cutils.c | 3 +-
59
hw/arm/Kconfig | 1 +
60
10 files changed, 89 insertions(+), 34 deletions(-)
63
61
64
target/arm/cpu.h | 48 +++++++++++++++++-------------
65
target/arm/internals.h | 14 +++++++--
66
device_tree.c | 2 +-
67
hw/arm/aspeed.c | 2 +-
68
hw/arm/aspeed_soc.c | 3 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/highbank.c | 2 +-
71
hw/arm/raspi.c | 2 --
72
hw/intc/arm_gicv3_cpuif.c | 10 ++-----
73
hw/ssi/xilinx_spips.c | 3 +-
74
hw/timer/aspeed_timer.c | 2 +-
75
target/arm/cpu.c | 37 +++++++++++++++++++----
76
target/arm/helper.c | 73 ++++++++++++++++++++++++++--------------------
77
target/arm/op_helper.c | 8 +++++
78
target/arm/translate-a64.c | 6 ++++
79
target/arm/translate.c | 12 ++++++++
80
16 files changed, 148 insertions(+), 78 deletions(-)
81
diff view generated by jsdifflib
Deleted patch
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
2
1
3
It is not uncommon for a contemporary FDT to be larger than 64 KiB,
4
leading to failures loading the device tree from sysfs:
5
6
qemu-system-aarch64: qemu_fdt_setprop: Couldn't set ...: FDT_ERR_NOSPACE
7
8
Hence increase the limit to 1 MiB, like on PPC.
9
10
For reference, the largest arm64 DTB created from the Linux sources is
11
ca. 75 KiB large (100 KiB when built with symbols/fixup support).
12
13
Cc: qemu-stable@nongnu.org
14
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
15
Message-id: 1523541337-23919-1-git-send-email-geert+renesas@glider.be
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
device_tree.c | 2 +-
20
1 file changed, 1 insertion(+), 1 deletion(-)
21
22
diff --git a/device_tree.c b/device_tree.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/device_tree.c
25
+++ b/device_tree.c
26
@@ -XXX,XX +XXX,XX @@
27
28
#include <libfdt.h>
29
30
-#define FDT_MAX_SIZE 0x10000
31
+#define FDT_MAX_SIZE 0x100000
32
33
void *create_device_tree(int *sizep)
34
{
35
--
36
2.17.0
37
38
diff view generated by jsdifflib
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
SNOOP_NONE state handle is moved above in the if ladder, as it's same
3
The removal of the selection of A15MPCORE from ARM_VIRT also
4
as SNOOP_STRIPPING during data cycles.
4
removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
5
5
6
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
6
Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals")
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Message-id: 1524119244-1240-1-git-send-email-saipava@xilinx.com
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20201111143440.112763-1-drjones@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
hw/ssi/xilinx_spips.c | 3 ++-
14
hw/arm/Kconfig | 1 +
12
1 file changed, 2 insertions(+), 1 deletion(-)
15
1 file changed, 1 insertion(+)
13
16
14
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
17
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/ssi/xilinx_spips.c
19
--- a/hw/arm/Kconfig
17
+++ b/hw/ssi/xilinx_spips.c
20
+++ b/hw/arm/Kconfig
18
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
21
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
19
if (fifo8_is_empty(&s->tx_fifo)) {
22
imply VFIO_PLATFORM
20
xilinx_spips_update_ixr(s);
23
imply VFIO_XGMAC
21
return;
24
imply TPM_TIS_SYSBUS
22
- } else if (s->snoop_state == SNOOP_STRIPING) {
25
+ select ARM_GIC
23
+ } else if (s->snoop_state == SNOOP_STRIPING ||
26
select ACPI
24
+ s->snoop_state == SNOOP_NONE) {
27
select ARM_SMMUV3
25
for (i = 0; i < num_effective_busses(s); ++i) {
28
select GPIO_KEY
26
tx_rx[i] = fifo8_pop(&s->tx_fifo);
27
}
28
--
29
--
29
2.17.0
30
2.20.1
30
31
31
32
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Alex Chen <alex.chen@huawei.com>
2
2
3
Because the design of the PMU requires that the counter values be
3
We should use printf format specifier "%u" instead of "%d" for
4
converted between their delta and guest-visible forms for mode
4
argument of type "unsigned int".
5
filtering, an additional hook which occurs before the EL is changed is
6
necessary.
7
5
8
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
6
Reported-by: Euler Robot <euler.robot@huawei.com>
9
Message-id: 1523997485-1905-8-git-send-email-alindsay@codeaurora.org
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/cpu.h | 22 +++++++++++++++++++---
12
hw/timer/exynos4210_mct.c | 4 ++--
14
target/arm/internals.h | 7 +++++++
13
hw/timer/exynos4210_pwm.c | 8 ++++----
15
target/arm/cpu.c | 16 ++++++++++++++++
14
2 files changed, 6 insertions(+), 6 deletions(-)
16
target/arm/helper.c | 14 ++++++++------
17
target/arm/op_helper.c | 8 ++++++++
18
5 files changed, 58 insertions(+), 9 deletions(-)
19
15
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
18
--- a/hw/timer/exynos4210_mct.c
23
+++ b/target/arm/cpu.h
19
+++ b/hw/timer/exynos4210_mct.c
24
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
25
*/
21
/* If CSTAT is pending and IRQ is enabled */
26
bool cfgend;
22
if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
27
23
(s->reg.int_enb & G_INT_ENABLE(id))) {
28
+ QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
24
- DPRINTF("gcmp timer[%d] IRQ\n", id);
29
QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
25
+ DPRINTF("gcmp timer[%u] IRQ\n", id);
30
26
qemu_irq_raise(s->irq[id]);
31
int32_t node_id; /* NUMA node this CPU belongs to */
27
}
32
@@ -XXX,XX +XXX,XX @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
28
}
33
#endif
29
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
34
30
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
35
/**
31
36
- * arm_register_el_change_hook:
32
if (freq != s->freq) {
37
- * Register a hook function which will be called back whenever this
33
- DPRINTF("freq=%dHz\n", s->freq);
38
+ * arm_register_pre_el_change_hook:
34
+ DPRINTF("freq=%uHz\n", s->freq);
39
+ * Register a hook function which will be called immediately before this
35
40
* CPU changes exception level or mode. The hook function will be
36
/* global timer */
41
* passed a pointer to the ARMCPU and the opaque data pointer passed
37
tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
42
* to this function when the hook was registered.
38
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
43
+ *
44
+ * Note that if a pre-change hook is called, any registered post-change hooks
45
+ * are guaranteed to subsequently be called.
46
*/
47
-void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
48
+void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
49
void *opaque);
50
+/**
51
+ * arm_register_el_change_hook:
52
+ * Register a hook function which will be called immediately after this
53
+ * CPU changes exception level or mode. The hook function will be
54
+ * passed a pointer to the ARMCPU and the opaque data pointer passed
55
+ * to this function when the hook was registered.
56
+ *
57
+ * Note that any registered hooks registered here are guaranteed to be called
58
+ * if pre-change hooks have been.
59
+ */
60
+void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
61
+ *opaque);
62
63
/**
64
* aa32_vfp_dreg:
65
diff --git a/target/arm/internals.h b/target/arm/internals.h
66
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/internals.h
40
--- a/hw/timer/exynos4210_pwm.c
68
+++ b/target/arm/internals.h
41
+++ b/hw/timer/exynos4210_pwm.c
69
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
42
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
70
MemTxResult response, uintptr_t retaddr);
43
71
44
if (freq != s->timer[id].freq) {
72
/* Call any registered EL change hooks */
45
ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
73
+static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
46
- DPRINTF("freq=%dHz\n", s->timer[id].freq);
74
+{
47
+ DPRINTF("freq=%uHz\n", s->timer[id].freq);
75
+ ARMELChangeHook *hook, *next;
48
}
76
+ QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
77
+ hook->hook(cpu, hook->opaque);
78
+ }
79
+}
80
static inline void arm_call_el_change_hook(ARMCPU *cpu)
81
{
82
ARMELChangeHook *hook, *next;
83
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/cpu.c
86
+++ b/target/arm/cpu.c
87
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
88
| CPU_INTERRUPT_EXITTB);
89
}
49
}
90
50
91
+void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
92
+ void *opaque)
52
uint32_t id = s->id;
93
+{
53
bool cmp;
94
+ ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
54
95
+
55
- DPRINTF("timer %d tick\n", id);
96
+ entry->hook = hook;
56
+ DPRINTF("timer %u tick\n", id);
97
+ entry->opaque = opaque;
57
98
+
58
/* set irq status */
99
+ QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
59
p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
100
+}
60
101
+
61
/* raise IRQ */
102
void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
62
if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
103
void *opaque)
63
- DPRINTF("timer %d IRQ\n", id);
104
{
64
+ DPRINTF("timer %u IRQ\n", id);
105
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
65
qemu_irq_raise(p->timer[id].irq);
106
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
107
g_free, g_free);
108
109
+ QLIST_INIT(&cpu->pre_el_change_hooks);
110
QLIST_INIT(&cpu->el_change_hooks);
111
112
#ifndef CONFIG_USER_ONLY
113
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
114
115
g_hash_table_destroy(cpu->cp_regs);
116
117
+ QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
118
+ QLIST_REMOVE(hook, node);
119
+ g_free(hook);
120
+ }
121
QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
122
QLIST_REMOVE(hook, node);
123
g_free(hook);
124
diff --git a/target/arm/helper.c b/target/arm/helper.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/target/arm/helper.c
127
+++ b/target/arm/helper.c
128
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
129
return;
130
}
66
}
131
67
132
+ /* Hooks may change global state so BQL should be held, also the
68
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
133
+ * BQL needs to be held for any modification of
134
+ * cs->interrupt_request.
135
+ */
136
+ g_assert(qemu_mutex_iothread_locked());
137
+
138
+ arm_call_pre_el_change_hook(cpu);
139
+
140
assert(!excp_is_internal(cs->exception_index));
141
if (arm_el_is_aa64(env, new_el)) {
142
arm_cpu_do_interrupt_aarch64(cs);
143
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
144
arm_cpu_do_interrupt_aarch32(cs);
145
}
69
}
146
70
147
- /* Hooks may change global state so BQL should be held, also the
71
if (cmp) {
148
- * BQL needs to be held for any modification of
72
- DPRINTF("auto reload timer %d count to %x\n", id,
149
- * cs->interrupt_request.
73
+ DPRINTF("auto reload timer %u count to %x\n", id,
150
- */
74
p->timer[id].reg_tcntb);
151
- g_assert(qemu_mutex_iothread_locked());
75
ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
152
-
76
ptimer_run(p->timer[id].ptimer, 1);
153
arm_call_el_change_hook(cpu);
154
155
if (!kvm_enabled()) {
156
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/target/arm/op_helper.c
159
+++ b/target/arm/op_helper.c
160
@@ -XXX,XX +XXX,XX @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
161
/* Write the CPSR for a 32-bit exception return */
162
void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
163
{
164
+ qemu_mutex_lock_iothread();
165
+ arm_call_pre_el_change_hook(arm_env_get_cpu(env));
166
+ qemu_mutex_unlock_iothread();
167
+
168
cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
169
170
/* Generated code has already stored the new PC value, but
171
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
172
goto illegal_return;
173
}
174
175
+ qemu_mutex_lock_iothread();
176
+ arm_call_pre_el_change_hook(arm_env_get_cpu(env));
177
+ qemu_mutex_unlock_iothread();
178
+
179
if (!return_to_aa64) {
180
env->aarch64 = 0;
181
/* We do a raw CPSR write because aarch64_sync_64_to_32()
182
--
77
--
183
2.17.0
78
2.20.1
184
79
185
80
diff view generated by jsdifflib
1
Currently we use memory_region_init_ram_nomigrate() to create
1
In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
2
the "aspeed.boot_rom" memory region, and we don't manually
2
and mouse emulation. However we didn't remove all the debug-by-printf
3
register it with vmstate_register_ram(). This currently
3
support. In fact there is only one printf() remaining, and it is
4
means that its contents are migrated but as a ram block
4
redundant with the trace_ps2_write_mouse() event next to it.
5
whose name is the empty string; in future it may mean they
5
Remove the printf() and the now-unused DEBUG* macros.
6
are not migrated at all. Use memory_region_init_ram() instead.
7
8
Note that would be a cross-version migration compatibility break
9
for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines,
10
but migration is currently broken for them.
11
6
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Cédric Le Goater <clg@kaod.org>
9
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
15
Message-id: 20180420124835.7268-3-peter.maydell@linaro.org
10
Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
16
---
11
---
17
hw/arm/aspeed.c | 2 +-
12
hw/input/ps2.c | 9 ---------
18
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 9 deletions(-)
19
14
20
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
15
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed.c
17
--- a/hw/input/ps2.c
23
+++ b/hw/arm/aspeed.c
18
+++ b/hw/input/ps2.c
24
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
19
@@ -XXX,XX +XXX,XX @@
25
* SoC and 128MB for the AST2500 SoC, which is twice as big as
20
26
* needed by the flash modules of the Aspeed machines.
21
#include "trace.h"
27
*/
22
28
- memory_region_init_rom_nomigrate(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
23
-/* debug PC keyboard */
29
+ memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
24
-//#define DEBUG_KBD
30
fl->size, &error_abort);
25
-
31
memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
26
-/* debug PC keyboard : only mouse */
32
boot_rom);
27
-//#define DEBUG_MOUSE
28
-
29
/* Keyboard Commands */
30
#define KBD_CMD_SET_LEDS    0xED    /* Set keyboard leds */
31
#define KBD_CMD_ECHO     0xEE
32
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
33
PS2MouseState *s = (PS2MouseState *)opaque;
34
35
trace_ps2_write_mouse(opaque, val);
36
-#ifdef DEBUG_MOUSE
37
- printf("kbd: write mouse 0x%02x\n", val);
38
-#endif
39
switch(s->common.write_cmd) {
40
default:
41
case -1:
33
--
42
--
34
2.17.0
43
2.20.1
35
44
36
45
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
In the mtspr helper we attempt to check for "is the timer disabled"
2
with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE
3
is zero and the condition is always false (Coverity complains about
4
the dead code.)
2
5
3
commit 1d3e65aa7ac5 ("hw/timer: Add value matching support to
6
The correct check would be to test whether the TTMR_M field in the
4
aspeed_timer") increased the vmstate version of aspeed.timer because
7
register is equal to TIMER_NONE instead. However, the
5
the state had changed, but it also bumped the version of the
8
cpu_openrisc_timer_update() function checks whether the timer is
6
VMSTATE_STRUCT_ARRAY under the aspeed.timerctrl which did not need to.
9
enabled (it looks at cpu->env.is_counting, which is set to 0 via
10
cpu_openrisc_count_stop() when the TTMR_M field is set to
11
TIMER_NONE), so there's no need to check for "timer disabled" in the
12
target/openrisc code. Instead, simply remove the dead code.
7
13
8
Change back this version to fix migration.
14
Fixes: Coverity CID 1005812
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Acked-by: Stafford Horne <shorne@gmail.com>
17
Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
18
---
19
target/openrisc/sys_helper.c | 3 ---
20
1 file changed, 3 deletions(-)
9
21
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
22
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
11
Message-id: 20180423101433.17759-1-clg@kaod.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/timer/aspeed_timer.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
19
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/timer/aspeed_timer.c
24
--- a/target/openrisc/sys_helper.c
21
+++ b/hw/timer/aspeed_timer.c
25
+++ b/target/openrisc/sys_helper.c
22
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_timer_state = {
26
@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
23
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
27
24
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
28
case TO_SPR(10, 1): /* TTCR */
25
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
29
cpu_openrisc_count_set(cpu, rb);
26
- ASPEED_TIMER_NR_TIMERS, 2, vmstate_aspeed_timer,
30
- if (env->ttmr & TIMER_NONE) {
27
+ ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
31
- return;
28
AspeedTimer),
32
- }
29
VMSTATE_END_OF_LIST()
33
cpu_openrisc_timer_update(cpu);
30
}
34
break;
35
#endif
31
--
36
--
32
2.17.0
37
2.20.1
33
38
34
39
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
This is a bug fix to ensure 64-bit reads of these registers don't read
3
This patch fixes CID 1432800 by removing an unnecessary check.
4
adjacent data.
5
4
6
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 1523997485-1905-13-git-send-email-alindsay@codeaurora.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
target/arm/cpu.h | 4 ++--
9
hw/core/register.c | 4 ----
12
target/arm/helper.c | 5 +++--
10
1 file changed, 4 deletions(-)
13
2 files changed, 5 insertions(+), 4 deletions(-)
14
11
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
diff --git a/hw/core/register.c b/hw/core/register.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
14
--- a/hw/core/register.c
18
+++ b/target/arm/cpu.h
15
+++ b/hw/core/register.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
16
@@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner,
20
uint32_t c9_data;
17
int index = rae[i].addr / data_size;
21
uint64_t c9_pmcr; /* performance monitor control register */
18
RegisterInfo *r = &ri[index];
22
uint64_t c9_pmcnten; /* perf monitor counter enables */
19
23
- uint32_t c9_pmovsr; /* perf monitor overflow status */
20
- if (data + data_size * index == 0 || !&rae[i]) {
24
- uint32_t c9_pmuserenr; /* perf monitor user enable */
21
- continue;
25
+ uint64_t c9_pmovsr; /* perf monitor overflow status */
22
- }
26
+ uint64_t c9_pmuserenr; /* perf monitor user enable */
23
-
27
uint64_t c9_pmselr; /* perf monitor counter selection register */
24
/* Init the register, this will zero it. */
28
uint64_t c9_pminten; /* perf monitor interrupt enables */
25
object_initialize((void *)r, sizeof(*r), TYPE_REGISTER);
29
union { /* Memory attribute redirection */
26
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
35
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
36
.writefn = pmcntenclr_write },
37
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
38
- .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
39
+ .access = PL0_RW,
40
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
41
.accessfn = pmreg_access,
42
.writefn = pmovsr_write,
43
.raw_writefn = raw_write },
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
45
.accessfn = pmreg_access_xevcntr },
46
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
47
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
48
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
49
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
50
.resetvalue = 0,
51
.writefn = pmuserenr_write, .raw_writefn = raw_write },
52
{ .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
53
--
27
--
54
2.17.0
28
2.20.1
55
29
56
30
diff view generated by jsdifflib
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
if arm_load_kernel() were passed non first_cpu, QEMU would end up
3
Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN):
4
with partially set do_cpu_reset() callback leaving some CPUs without it.
5
4
6
Make sure that do_cpu_reset() is registered for all CPUs by enumerating
5
>>> Overrunning array "suffixes" of 7 8-byte elements at element
7
CPUs from first_cpu.
6
index 7 (byte offset 63) using index "idx" (which evaluates to 7).
8
7
9
(In practice every board that we have was passing us the first CPU
8
Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
10
as the boot CPU, either directly or indirectly, so this wasn't
9
which is ~18.446 EHz, less than 1000 EHz.
11
causing incorrect behaviour.)
12
10
13
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
11
Reported-by: Eduardo Habkost <ehabkost@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a note that this isn't a behaviour change]
14
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
16
Message-id: 20201101215755.2021421-1-f4bug@amsat.org
17
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
20
---
18
hw/arm/boot.c | 2 +-
21
util/cutils.c | 3 ++-
19
1 file changed, 1 insertion(+), 1 deletion(-)
22
1 file changed, 2 insertions(+), 1 deletion(-)
20
23
21
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
24
diff --git a/util/cutils.c b/util/cutils.c
22
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/boot.c
26
--- a/util/cutils.c
24
+++ b/hw/arm/boot.c
27
+++ b/util/cutils.c
25
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
28
@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
26
* actually loading a kernel, the handler is also responsible for
29
double freq = freq_hz;
27
* arranging that we start it correctly.
30
size_t idx = 0;
28
*/
31
29
- for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
32
- while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
30
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
33
+ while (freq >= 1000.0) {
31
qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
34
freq /= 1000.0;
35
idx++;
32
}
36
}
37
+ assert(idx < ARRAY_SIZE(suffixes));
38
39
return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
33
}
40
}
34
--
41
--
35
2.17.0
42
2.20.1
36
43
37
44
diff view generated by jsdifflib
Deleted patch
1
Remove a stale TODO comment -- we have now made the arm_ldl_ptw()
2
and arm_ldq_ptw() functions propagate physical memory read errors
3
out to their callers.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180419142151.9862-1-peter.maydell@linaro.org
8
---
9
target/arm/helper.c | 8 +-------
10
1 file changed, 1 insertion(+), 7 deletions(-)
11
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.c
15
+++ b/target/arm/helper.c
16
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
17
return addr;
18
}
19
20
-/* All loads done in the course of a page table walk go through here.
21
- * TODO: rather than ignoring errors from physical memory reads (which
22
- * are external aborts in ARM terminology) we should propagate this
23
- * error out so that we can turn it into a Data Abort if this walk
24
- * was being done for a CPU load/store or an address translation instruction
25
- * (but not if it was for a debug access).
26
- */
27
+/* All loads done in the course of a page table walk go through here. */
28
static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
29
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
30
{
31
--
32
2.17.0
33
34
diff view generated by jsdifflib
Deleted patch
1
In commit 95695effe8caa552b8f2 we changed the v7M/v8M stack
2
pop code to use a new v7m_stack_read() function that checks
3
whether the read should fail due to an MPU or bus abort.
4
We missed one call though, the one which reads the signature
5
word for the callee-saved register part of the frame.
6
1
7
Correct the omission.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20180419142106.9694-1-peter.maydell@linaro.org
13
---
14
target/arm/helper.c | 9 +++++----
15
1 file changed, 5 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
20
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu)
22
static void do_v7m_exception_exit(ARMCPU *cpu)
23
{
24
CPUARMState *env = &cpu->env;
25
- CPUState *cs = CPU(cpu);
26
uint32_t excret;
27
uint32_t xpsr;
28
bool ufault = false;
29
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
30
((excret & R_V7M_EXCRET_ES_MASK) == 0 ||
31
(excret & R_V7M_EXCRET_DCRS_MASK) == 0)) {
32
uint32_t expected_sig = 0xfefa125b;
33
- uint32_t actual_sig = ldl_phys(cs->as, frameptr);
34
+ uint32_t actual_sig;
35
36
- if (expected_sig != actual_sig) {
37
+ pop_ok = v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx);
38
+
39
+ if (pop_ok && expected_sig != actual_sig) {
40
/* Take a SecureFault on the current stack */
41
env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK;
42
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
43
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
44
return;
45
}
46
47
- pop_ok =
48
+ pop_ok = pop_ok &&
49
v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) &&
50
v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) &&
51
v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx) &&
52
--
53
2.17.0
54
55
diff view generated by jsdifflib
Deleted patch
1
From: Aaron Lindsay <alindsay@codeaurora.org>
2
1
3
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 1523997485-1905-2-git-send-email-alindsay@codeaurora.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@ static inline bool arm_ccnt_enabled(CPUARMState *env)
16
{
17
/* This does not support checking PMCCFILTR_EL0 register */
18
19
- if (!(env->cp15.c9_pmcr & PMCRE)) {
20
+ if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) {
21
return false;
22
}
23
24
--
25
2.17.0
26
27
diff view generated by jsdifflib
Deleted patch
1
From: Aaron Lindsay <alindsay@codeaurora.org>
2
1
3
They share the same underlying state
4
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1523997485-1905-3-git-send-email-alindsay@codeaurora.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
18
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
19
.writefn = pmselr_write, .raw_writefn = raw_write, },
20
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
21
- .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
22
+ .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
23
.readfn = pmccntr_read, .writefn = pmccntr_write32,
24
.accessfn = pmreg_access_ccntr },
25
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
26
--
27
2.17.0
28
29
diff view generated by jsdifflib
Deleted patch
1
From: Aaron Lindsay <alindsay@codeaurora.org>
2
1
3
This is in preparation for enabling counters other than PMCCNTR
4
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1523997485-1905-5-git-send-email-alindsay@codeaurora.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 31 ++++++++++++++++++++++---------
11
1 file changed, 22 insertions(+), 9 deletions(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
18
static void v8m_security_lookup(CPUARMState *env, uint32_t address,
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
V8M_SAttributes *sattrs);
21
-
22
-/* Definitions for the PMCCNTR and PMCR registers */
23
-#define PMCRD 0x8
24
-#define PMCRC 0x4
25
-#define PMCRE 0x1
26
#endif
27
28
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
29
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
30
REGINFO_SENTINEL
31
};
32
33
+/* Definitions for the PMU registers */
34
+#define PMCRN_MASK 0xf800
35
+#define PMCRN_SHIFT 11
36
+#define PMCRD 0x8
37
+#define PMCRC 0x4
38
+#define PMCRE 0x1
39
+
40
+static inline uint32_t pmu_num_counters(CPUARMState *env)
41
+{
42
+ return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
43
+}
44
+
45
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
46
+static inline uint64_t pmu_counter_mask(CPUARMState *env)
47
+{
48
+ return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
49
+}
50
+
51
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
52
bool isread)
53
{
54
@@ -XXX,XX +XXX,XX @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
55
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
56
uint64_t value)
57
{
58
- value &= (1 << 31);
59
+ value &= pmu_counter_mask(env);
60
env->cp15.c9_pmcnten |= value;
61
}
62
63
static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
64
uint64_t value)
65
{
66
- value &= (1 << 31);
67
+ value &= pmu_counter_mask(env);
68
env->cp15.c9_pmcnten &= ~value;
69
}
70
71
@@ -XXX,XX +XXX,XX @@ static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
uint64_t value)
73
{
74
/* We have no event counters so only the C bit can be changed */
75
- value &= (1 << 31);
76
+ value &= pmu_counter_mask(env);
77
env->cp15.c9_pminten |= value;
78
}
79
80
static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
81
uint64_t value)
82
{
83
- value &= (1 << 31);
84
+ value &= pmu_counter_mask(env);
85
env->cp15.c9_pminten &= ~value;
86
}
87
88
--
89
2.17.0
90
91
diff view generated by jsdifflib
Deleted patch
1
From: Aaron Lindsay <alindsay@codeaurora.org>
2
1
3
This eliminates the need for fetching it from el_change_hook_opaque, and
4
allows for supporting multiple el_change_hooks without having to hack
5
something together to find the registered opaque belonging to GICv3.
6
7
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 1523997485-1905-6-git-send-email-alindsay@codeaurora.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 10 ----------
13
hw/intc/arm_gicv3_cpuif.c | 10 ++--------
14
2 files changed, 2 insertions(+), 18 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
21
void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
22
void *opaque);
23
24
-/**
25
- * arm_get_el_change_hook_opaque:
26
- * Return the opaque data that will be used by the el_change_hook
27
- * for this CPU.
28
- */
29
-static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
30
-{
31
- return cpu->el_change_hook_opaque;
32
-}
33
-
34
/**
35
* aa32_vfp_dreg:
36
* Return a pointer to the Dn register within env in 32-bit mode.
37
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/intc/arm_gicv3_cpuif.c
40
+++ b/hw/intc/arm_gicv3_cpuif.c
41
@@ -XXX,XX +XXX,XX @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
42
43
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
44
{
45
- /* Given the CPU, find the right GICv3CPUState struct.
46
- * Since we registered the CPU interface with the EL change hook as
47
- * the opaque pointer, we can just directly get from the CPU to it.
48
- */
49
- return arm_get_el_change_hook_opaque(arm_env_get_cpu(env));
50
+ return env->gicv3state;
51
}
52
53
static bool gicv3_use_ns_bank(CPUARMState *env)
54
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
55
* it might be with code translated by CPU 0 but run by CPU 1, in
56
* which case we'd get the wrong value.
57
* So instead we define the regs with no ri->opaque info, and
58
- * get back to the GICv3CPUState from the ARMCPU by reading back
59
- * the opaque pointer from the el_change_hook, which we're going
60
- * to need to register anyway.
61
+ * get back to the GICv3CPUState from the CPUARMState.
62
*/
63
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
64
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
65
--
66
2.17.0
67
68
diff view generated by jsdifflib
Deleted patch
1
From: Aaron Lindsay <alindsay@codeaurora.org>
2
1
3
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
4
Message-id: 1523997485-1905-7-git-send-email-alindsay@codeaurora.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/cpu.h | 20 ++++++++++----------
9
target/arm/internals.h | 7 ++++---
10
target/arm/cpu.c | 21 ++++++++++++++++-----
11
3 files changed, 30 insertions(+), 18 deletions(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
18
} CPUARMState;
19
20
/**
21
- * ARMELChangeHook:
22
+ * ARMELChangeHookFn:
23
* type of a function which can be registered via arm_register_el_change_hook()
24
* to get callbacks when the CPU changes its exception level or mode.
25
*/
26
-typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
27
-
28
+typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
29
+typedef struct ARMELChangeHook ARMELChangeHook;
30
+struct ARMELChangeHook {
31
+ ARMELChangeHookFn *hook;
32
+ void *opaque;
33
+ QLIST_ENTRY(ARMELChangeHook) node;
34
+};
35
36
/* These values map onto the return values for
37
* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
38
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
39
*/
40
bool cfgend;
41
42
- ARMELChangeHook *el_change_hook;
43
- void *el_change_hook_opaque;
44
+ QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
45
46
int32_t node_id; /* NUMA node this CPU belongs to */
47
48
@@ -XXX,XX +XXX,XX @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
49
* CPU changes exception level or mode. The hook function will be
50
* passed a pointer to the ARMCPU and the opaque data pointer passed
51
* to this function when the hook was registered.
52
- *
53
- * Note that we currently only support registering a single hook function,
54
- * and will assert if this function is called twice.
55
- * This facility is intended for the use of the GICv3 emulation.
56
*/
57
-void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
58
+void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
59
void *opaque);
60
61
/**
62
diff --git a/target/arm/internals.h b/target/arm/internals.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/internals.h
65
+++ b/target/arm/internals.h
66
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
67
int mmu_idx, MemTxAttrs attrs,
68
MemTxResult response, uintptr_t retaddr);
69
70
-/* Call the EL change hook if one has been registered */
71
+/* Call any registered EL change hooks */
72
static inline void arm_call_el_change_hook(ARMCPU *cpu)
73
{
74
- if (cpu->el_change_hook) {
75
- cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
76
+ ARMELChangeHook *hook, *next;
77
+ QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
78
+ hook->hook(cpu, hook->opaque);
79
}
80
}
81
82
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/cpu.c
85
+++ b/target/arm/cpu.c
86
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
87
| CPU_INTERRUPT_EXITTB);
88
}
89
90
-void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
91
+void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
92
void *opaque)
93
{
94
- /* We currently only support registering a single hook function */
95
- assert(!cpu->el_change_hook);
96
- cpu->el_change_hook = hook;
97
- cpu->el_change_hook_opaque = opaque;
98
+ ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
99
+
100
+ entry->hook = hook;
101
+ entry->opaque = opaque;
102
+
103
+ QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
104
}
105
106
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
107
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
108
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
109
g_free, g_free);
110
111
+ QLIST_INIT(&cpu->el_change_hooks);
112
+
113
#ifndef CONFIG_USER_ONLY
114
/* Our inbound IRQ and FIQ lines */
115
if (kvm_enabled()) {
116
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
117
static void arm_cpu_finalizefn(Object *obj)
118
{
119
ARMCPU *cpu = ARM_CPU(obj);
120
+ ARMELChangeHook *hook, *next;
121
+
122
g_hash_table_destroy(cpu->cp_regs);
123
+
124
+ QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
125
+ QLIST_REMOVE(hook, node);
126
+ g_free(hook);
127
+ }
128
}
129
130
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
131
--
132
2.17.0
133
134
diff view generated by jsdifflib
Deleted patch
1
From: Aaron Lindsay <alindsay@codeaurora.org>
2
1
3
During code generation, surround CPSR writes and exception returns which
4
call the EL change hooks with gen_io_start/end. The immediate need is
5
for the PMU to access the clock and icount during EL change to support
6
mode filtering.
7
8
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
9
Message-id: 1523997485-1905-9-git-send-email-alindsay@codeaurora.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-a64.c | 6 ++++++
14
target/arm/translate.c | 12 ++++++++++++
15
2 files changed, 18 insertions(+)
16
17
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-a64.c
20
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
22
unallocated_encoding(s);
23
return;
24
}
25
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
26
+ gen_io_start();
27
+ }
28
gen_helper_exception_return(cpu_env);
29
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
30
+ gen_io_end();
31
+ }
32
/* Must exit loop to check un-masked IRQs */
33
s->base.is_jmp = DISAS_EXIT;
34
return;
35
diff --git a/target/arm/translate.c b/target/arm/translate.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/translate.c
38
+++ b/target/arm/translate.c
39
@@ -XXX,XX +XXX,XX @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
40
* appropriately depending on the new Thumb bit, so it must
41
* be called after storing the new PC.
42
*/
43
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
44
+ gen_io_start();
45
+ }
46
gen_helper_cpsr_write_eret(cpu_env, cpsr);
47
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
48
+ gen_io_end();
49
+ }
50
tcg_temp_free_i32(cpsr);
51
/* Must exit loop to check un-masked IRQs */
52
s->base.is_jmp = DISAS_EXIT;
53
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
54
if (exc_return) {
55
/* Restore CPSR from SPSR. */
56
tmp = load_cpu_field(spsr);
57
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
58
+ gen_io_start();
59
+ }
60
gen_helper_cpsr_write_eret(cpu_env, tmp);
61
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
62
+ gen_io_end();
63
+ }
64
tcg_temp_free_i32(tmp);
65
/* Must exit loop to check un-masked IRQs */
66
s->base.is_jmp = DISAS_EXIT;
67
--
68
2.17.0
69
70
diff view generated by jsdifflib
1
Currently we use memory_region_init_ram_nomigrate() to create
1
In commit 76346b6264a9b01979 we tried to add a configure check that
2
the "highbank.sysram" memory region, and we don't manually
2
the libgio pkg-config data was correct, which builds an executable
3
register it with vmstate_register_ram(). This currently
3
linked against it. Unfortunately this doesn't catch the problem
4
means that its contents are migrated but as a ram block
4
(missing static library dependency info), because a "do nothing" test
5
whose name is the empty string; in future it may mean they
5
source file doesn't have any symbol references that cause the linker
6
are not migrated at all. Use memory_region_init_ram() instead.
6
to pull in .o files from libgio.a, and so we don't see the "missing
7
symbols from libmount" error that a full QEMU link triggers.
7
8
8
Note that this is a cross-version migration compatibility
9
(The ineffective test went unnoticed because of a typo that
9
break for the "highbank" and "midway" machines.
10
effectively disabled libgio unconditionally, but after commit
11
3569a5dfc11f2 fixed that, a static link of the system emulator on
12
Ubuntu stopped working again.)
13
14
Improve the gio test by having the test source fragment reference a
15
g_dbus function (which is what is indirectly causing us to end up
16
wanting functions from libmount).
10
17
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20180420124835.7268-2-peter.maydell@linaro.org
19
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
20
Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
13
---
21
---
14
hw/arm/highbank.c | 2 +-
22
configure | 11 +++++++++--
15
1 file changed, 1 insertion(+), 1 deletion(-)
23
1 file changed, 9 insertions(+), 2 deletions(-)
16
24
17
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
25
diff --git a/configure b/configure
18
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100755
19
--- a/hw/arm/highbank.c
27
--- a/configure
20
+++ b/hw/arm/highbank.c
28
+++ b/configure
21
@@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
29
@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
22
memory_region_add_subregion(sysmem, 0, dram);
30
# Check that the libraries actually work -- Ubuntu 18.04 ships
23
31
# with pkg-config --static --libs data for gio-2.0 that is missing
24
sysram = g_new(MemoryRegion, 1);
32
# -lblkid and will give a link error.
25
- memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000,
33
- write_c_skeleton
26
+ memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
34
- if compile_prog "" "$gio_libs" ; then
27
&error_fatal);
35
+ cat > $TMPC <<EOF
28
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
36
+#include <gio/gio.h>
29
if (bios_name != NULL) {
37
+int main(void)
38
+{
39
+ g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
40
+ return 0;
41
+}
42
+EOF
43
+ if compile_prog "$gio_cflags" "$gio_libs" ; then
44
gio=yes
45
else
46
gio=no
30
--
47
--
31
2.17.0
48
2.20.1
32
49
33
50
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
2
power-up reset values for the T_low and T_high registers are 80 degrees C
3
and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These
4
values are then shifted right by four bits to give the register reset
5
values, since both registers store the 12 bits of temperature data in bits
6
[15..4] of a 16 bit register.
2
7
3
It was shifted to the left one bit too few.
8
We were resetting these registers to zero, which is problematic for Linux
9
guests which enable the alert interrupt and then immediately take an
10
unexpected overtemperature alert because the current temperature is above
11
freezing...
4
12
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1523997485-1905-10-git-send-email-alindsay@codeaurora.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
9
---
16
---
10
target/arm/helper.c | 2 +-
17
hw/misc/tmp105.c | 3 +++
11
1 file changed, 1 insertion(+), 1 deletion(-)
18
1 file changed, 3 insertions(+)
12
19
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
22
--- a/hw/misc/tmp105.c
16
+++ b/target/arm/helper.c
23
+++ b/hw/misc/tmp105.c
17
@@ -XXX,XX +XXX,XX @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
24
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
18
uint64_t value)
25
s->faults = tmp105_faultq[(s->config >> 3) & 3];
19
{
26
s->alarm = 0;
20
pmccntr_sync(env);
27
21
- env->cp15.pmccfiltr_el0 = value & 0x7E000000;
28
+ s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
22
+ env->cp15.pmccfiltr_el0 = value & 0xfc000000;
29
+ s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
23
pmccntr_sync(env);
30
+
31
tmp105_interrupt_update(s);
24
}
32
}
25
33
26
--
34
--
27
2.17.0
35
2.20.1
28
36
29
37
diff view generated by jsdifflib
Deleted patch
1
In commit 210f47840dd62, we changed the bcm2836 SoC object to
2
always create a CPU of the correct type for that SoC model. This
3
makes the default_cpu_type settings in the MachineClass structs
4
for the raspi2 and raspi3 boards redundant. We didn't change
5
those at the time because it would have meant a temporary
6
regression in a corner case of error handling if the user
7
requested a non-existing CPU type. The -cpu parse handling
8
changes in 2278b93941d42c3 mean that it no longer implicitly
9
depends on default_cpu_type for this to work, so we can now
10
delete the redundant default_cpu_type fields.
11
1
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20180420155547.9497-1-peter.maydell@linaro.org
15
---
16
hw/arm/raspi.c | 2 --
17
1 file changed, 2 deletions(-)
18
19
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/raspi.c
22
+++ b/hw/arm/raspi.c
23
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
24
mc->no_parallel = 1;
25
mc->no_floppy = 1;
26
mc->no_cdrom = 1;
27
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
28
mc->max_cpus = BCM283X_NCPUS;
29
mc->min_cpus = BCM283X_NCPUS;
30
mc->default_cpus = BCM283X_NCPUS;
31
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
32
mc->no_parallel = 1;
33
mc->no_floppy = 1;
34
mc->no_cdrom = 1;
35
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
36
mc->max_cpus = BCM283X_NCPUS;
37
mc->min_cpus = BCM283X_NCPUS;
38
mc->default_cpus = BCM283X_NCPUS;
39
--
40
2.17.0
41
42
diff view generated by jsdifflib
1
Currently we use vmstate_register_ram_global() for the SRAM;
1
The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
2
this is not a good idea for devices, because it means that
2
signals an alert when the temperature equals or exceeds the T_high value and
3
you can only ever create one instance of the device, as
3
then remains high until a device register is read or the device responds to
4
the second instance would get a RAM block name clash.
4
the SMBUS Alert Response address, or the device is put into Shutdown Mode.
5
Instead, use memory_region_init_ram(), which automatically
5
Thereafter the Alert pin will only be re-signalled when temperature falls
6
registers the RAM block with a local-to-the-device name.
6
below T_low; alert can then be cleared in the same set of ways, and the
7
device returns to its initial "alert when temperature goes above T_high"
8
mode. (If this textual description is confusing, see figure 3 in the
9
TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)
7
10
8
Note that this would be a cross-version migration compatibility break
11
We were misimplementing this as a simple "always alert if temperature is
9
for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines,
12
above T_high or below T_low" condition, which gives a spurious alert on
10
but migration is currently broken for them.
13
startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
14
limit values.
15
16
Implement the correct (hysteresis) behaviour by tracking whether we
17
are currently looking for the temperature to rise over T_high or
18
for it to fall below T_low. Our implementation of the comparator
19
mode (TM==0) wasn't wrong, but rephrase it to match the way that
20
interrupt mode is now handled for clarity.
11
21
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Cédric Le Goater <clg@kaod.org>
23
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
Tested-by: Cédric Le Goater <clg@kaod.org>
24
Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
15
Message-id: 20180420124835.7268-4-peter.maydell@linaro.org
16
---
25
---
17
hw/arm/aspeed_soc.c | 3 +--
26
hw/misc/tmp105.h | 7 +++++
18
1 file changed, 1 insertion(+), 2 deletions(-)
27
hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
28
2 files changed, 68 insertions(+), 9 deletions(-)
19
29
20
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
30
diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
21
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed_soc.c
32
--- a/hw/misc/tmp105.h
23
+++ b/hw/arm/aspeed_soc.c
33
+++ b/hw/misc/tmp105.h
24
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
34
@@ -XXX,XX +XXX,XX @@ struct TMP105State {
35
int16_t limit[2];
36
int faults;
37
uint8_t alarm;
38
+ /*
39
+ * The TMP105 initially looks for a temperature rising above T_high;
40
+ * once this is detected, the condition it looks for next is the
41
+ * temperature falling below T_low. This flag is false when initially
42
+ * looking for T_high, true when looking for T_low.
43
+ */
44
+ bool detect_falling;
45
};
46
47
#endif
48
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/misc/tmp105.c
51
+++ b/hw/misc/tmp105.c
52
@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
53
return;
25
}
54
}
26
55
27
/* SRAM */
56
- if ((s->config >> 1) & 1) {                    /* TM */
28
- memory_region_init_ram_nomigrate(&s->sram, OBJECT(dev), "aspeed.sram",
57
- if (s->temperature >= s->limit[1])
29
+ memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
58
- s->alarm = 1;
30
sc->info->sram_size, &err);
59
- else if (s->temperature < s->limit[0])
31
if (err) {
60
- s->alarm = 1;
32
error_propagate(errp, err);
61
+ if (s->config >> 1 & 1) {
33
return;
62
+ /*
63
+ * TM == 1 : Interrupt mode. We signal Alert when the
64
+ * temperature rises above T_high, and expect the guest to clear
65
+ * it (eg by reading a device register).
66
+ */
67
+ if (s->detect_falling) {
68
+ if (s->temperature < s->limit[0]) {
69
+ s->alarm = 1;
70
+ s->detect_falling = false;
71
+ }
72
+ } else {
73
+ if (s->temperature >= s->limit[1]) {
74
+ s->alarm = 1;
75
+ s->detect_falling = true;
76
+ }
77
+ }
78
} else {
79
- if (s->temperature >= s->limit[1])
80
- s->alarm = 1;
81
- else if (s->temperature < s->limit[0])
82
- s->alarm = 0;
83
+ /*
84
+ * TM == 0 : Comparator mode. We signal Alert when the temperature
85
+ * rises above T_high, and stop signalling it when the temperature
86
+ * falls below T_low.
87
+ */
88
+ if (s->detect_falling) {
89
+ if (s->temperature < s->limit[0]) {
90
+ s->alarm = 0;
91
+ s->detect_falling = false;
92
+ }
93
+ } else {
94
+ if (s->temperature >= s->limit[1]) {
95
+ s->alarm = 1;
96
+ s->detect_falling = true;
97
+ }
98
+ }
34
}
99
}
35
- vmstate_register_ram_global(&s->sram);
100
36
memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
101
tmp105_interrupt_update(s);
37
&s->sram);
102
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
38
103
return 0;
104
}
105
106
+static bool detect_falling_needed(void *opaque)
107
+{
108
+ TMP105State *s = opaque;
109
+
110
+ /*
111
+ * We only need to migrate the detect_falling bool if it's set;
112
+ * for migration from older machines we assume that it is false
113
+ * (ie temperature is not out of range).
114
+ */
115
+ return s->detect_falling;
116
+}
117
+
118
+static const VMStateDescription vmstate_tmp105_detect_falling = {
119
+ .name = "TMP105/detect-falling",
120
+ .version_id = 1,
121
+ .minimum_version_id = 1,
122
+ .needed = detect_falling_needed,
123
+ .fields = (VMStateField[]) {
124
+ VMSTATE_BOOL(detect_falling, TMP105State),
125
+ VMSTATE_END_OF_LIST()
126
+ }
127
+};
128
+
129
static const VMStateDescription vmstate_tmp105 = {
130
.name = "TMP105",
131
.version_id = 0,
132
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
133
VMSTATE_UINT8(alarm, TMP105State),
134
VMSTATE_I2C_SLAVE(i2c, TMP105State),
135
VMSTATE_END_OF_LIST()
136
+ },
137
+ .subsections = (const VMStateDescription*[]) {
138
+ &vmstate_tmp105_detect_falling,
139
+ NULL
140
}
141
};
142
143
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
144
s->config = 0;
145
s->faults = tmp105_faultq[(s->config >> 3) & 3];
146
s->alarm = 0;
147
+ s->detect_falling = false;
148
149
s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
150
s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
39
--
151
--
40
2.17.0
152
2.20.1
41
153
42
154
diff view generated by jsdifflib