1
First arm pullreq of the 2.13 cycle!
1
Patches for rc1: nothing major, just some minor bugfixes and
2
code cleanups.
2
3
3
-- PMM
4
-- PMM
4
5
5
The following changes since commit 4743c23509a51bd4ee85cc272287a41917d1be35:
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
6
7
7
Update version for v2.12.0 release (2018-04-24 16:44:55 +0100)
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
8
9
9
are available in the Git repository at:
10
are available in the Git repository at:
10
11
11
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180426
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
12
13
13
for you to fetch changes up to fbf32752663878947de455ff57cb5b9318f14bec:
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
14
15
15
xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo (2018-04-26 11:04:40 +0100)
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
target-arm queue:
19
target-arm queue:
19
* xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
20
* timer/aspeed: fix vmstate version id
21
* Minor coding style fixes
21
* hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
22
* docs: add some notes on the sbsa-ref machine
22
* hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
23
* hw/arm/highbank: don't make sysram 'nomigrate'
24
* target/arm: Fix neon VTBL/VTBX for len > 1
24
* hw/arm/raspi: Don't bother setting default_cpu_type
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
25
* PMU emulation: some minor bugfixes and preparation for
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
26
support of other events than just the cycle counter
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
27
* target/arm: Use v7m_stack_read() for reading the frame signature
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
28
* target/arm: Remove stale TODO comment
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
29
* arm: always start from first_cpu when registering loader cpu reset callback
30
* hw/arm/nseries: Check return value from load_image_targphys()
30
* device_tree: Increase FDT_MAX_SIZE to 1 MiB
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
31
33
32
----------------------------------------------------------------
34
----------------------------------------------------------------
33
Aaron Lindsay (9):
35
Alex Bennée (1):
34
target/arm: Check PMCNTEN for whether PMCCNTR is enabled
36
docs: add some notes on the sbsa-ref machine
35
target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
36
target/arm: Mask PMU register writes based on PMCR_EL0.N
37
target/arm: Fetch GICv3 state directly from CPUARMState
38
target/arm: Support multiple EL change hooks
39
target/arm: Add pre-EL change hooks
40
target/arm: Allow EL change hooks to do IO
41
target/arm: Fix bitmask for PMCCFILTR writes
42
target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide
43
37
44
Cédric Le Goater (1):
38
AlexChen (1):
45
timer/aspeed: fix vmstate version id
39
ssi: Fix bad printf format specifiers
46
40
47
Geert Uytterhoeven (1):
41
Andrew Jones (1):
48
device_tree: Increase FDT_MAX_SIZE to 1 MiB
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
49
43
50
Igor Mammedov (1):
44
Havard Skinnemoen (1):
51
arm: always start from first_cpu when registering loader cpu reset callback
45
tests/qtest/npcm7xx_rng-test: count runs properly
52
46
53
Peter Maydell (6):
47
Peter Maydell (2):
54
target/arm: Remove stale TODO comment
48
hw/arm/nseries: Check return value from load_image_targphys()
55
target/arm: Use v7m_stack_read() for reading the frame signature
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
56
hw/arm/raspi: Don't bother setting default_cpu_type
57
hw/arm/highbank: don't make sysram 'nomigrate'
58
hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
59
hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
60
50
61
Sai Pavan Boddu (1):
51
Philippe Mathieu-Daudé (6):
62
xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
63
58
64
target/arm/cpu.h | 48 +++++++++++++++++-------------
59
Richard Henderson (1):
65
target/arm/internals.h | 14 +++++++--
60
target/arm: Fix neon VTBL/VTBX for len > 1
66
device_tree.c | 2 +-
67
hw/arm/aspeed.c | 2 +-
68
hw/arm/aspeed_soc.c | 3 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/highbank.c | 2 +-
71
hw/arm/raspi.c | 2 --
72
hw/intc/arm_gicv3_cpuif.c | 10 ++-----
73
hw/ssi/xilinx_spips.c | 3 +-
74
hw/timer/aspeed_timer.c | 2 +-
75
target/arm/cpu.c | 37 +++++++++++++++++++----
76
target/arm/helper.c | 73 ++++++++++++++++++++++++++--------------------
77
target/arm/op_helper.c | 8 +++++
78
target/arm/translate-a64.c | 6 ++++
79
target/arm/translate.c | 12 ++++++++
80
16 files changed, 148 insertions(+), 78 deletions(-)
81
61
62
Xinhao Zhang (3):
63
target/arm: add spaces around operator
64
target/arm: Don't use '#' flag of printf format
65
target/arm: add space before the open parenthesis '('
66
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
1
Currently we use memory_region_init_ram_nomigrate() to create
1
From: Andrew Jones <drjones@redhat.com>
2
the "aspeed.boot_rom" memory region, and we don't manually
3
register it with vmstate_register_ram(). This currently
4
means that its contents are migrated but as a ram block
5
whose name is the empty string; in future it may mean they
6
are not migrated at all. Use memory_region_init_ram() instead.
7
2
8
Note that would be a cross-version migration compatibility break
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
9
for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines,
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
10
but migration is currently broken for them.
5
in the build when building armv7m_systick.
11
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
Tested-by: Cédric Le Goater <clg@kaod.org>
15
Message-id: 20180420124835.7268-3-peter.maydell@linaro.org
16
---
11
---
17
hw/arm/aspeed.c | 2 +-
12
hw/arm/Kconfig | 1 +
18
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+)
19
14
20
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed.c
17
--- a/hw/arm/Kconfig
23
+++ b/hw/arm/aspeed.c
18
+++ b/hw/arm/Kconfig
24
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
25
* SoC and 128MB for the AST2500 SoC, which is twice as big as
20
26
* needed by the flash modules of the Aspeed machines.
21
config ARM_V7M
27
*/
22
bool
28
- memory_region_init_rom_nomigrate(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
23
+ select PTIMER
29
+ memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
24
30
fl->size, &error_abort);
25
config ALLWINNER_A10
31
memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
26
bool
32
boot_rom);
33
--
27
--
34
2.17.0
28
2.20.1
35
29
36
30
diff view generated by jsdifflib
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
if arm_load_kernel() were passed non first_cpu, QEMU would end up
3
We should use printf format specifier "%u" instead of "%d" for
4
with partially set do_cpu_reset() callback leaving some CPUs without it.
4
argument of type "unsigned int".
5
5
6
Make sure that do_cpu_reset() is registered for all CPUs by enumerating
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
CPUs from first_cpu.
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
(In practice every board that we have was passing us the first CPU
9
Message-id: 5FA280F5.8060902@huawei.com
10
as the boot CPU, either directly or indirectly, so this wasn't
11
causing incorrect behaviour.)
12
13
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a note that this isn't a behaviour change]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
11
---
18
hw/arm/boot.c | 2 +-
12
hw/ssi/imx_spi.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
13
hw/ssi/xilinx_spi.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
20
15
21
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/boot.c
18
--- a/hw/ssi/imx_spi.c
24
+++ b/hw/arm/boot.c
19
+++ b/hw/ssi/imx_spi.c
25
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
26
* actually loading a kernel, the handler is also responsible for
21
case ECSPI_MSGDATA:
27
* arranging that we start it correctly.
22
return "ECSPI_MSGDATA";
28
*/
23
default:
29
- for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
24
- sprintf(unknown, "%d ?", reg);
30
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
25
+ sprintf(unknown, "%u ?", reg);
31
qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
26
return unknown;
32
}
27
}
33
}
28
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/ssi/xilinx_spi.c
32
+++ b/hw/ssi/xilinx_spi.c
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
34
irq chain unless things really changed. */
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
34
--
42
--
35
2.17.0
43
2.20.1
36
44
37
45
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
They share the same underlying state
3
Fix code style. Operator needs spaces both sides.
4
4
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1523997485-1905-3-git-send-email-alindsay@codeaurora.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/helper.c | 2 +-
11
target/arm/arch_dump.c | 8 ++++----
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
target/arm/arm-semi.c | 8 ++++----
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
12
15
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/arch_dump.c
19
+++ b/target/arm/arch_dump.c
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
21
22
for (i = 0; i < 32; ++i) {
23
uint64_t *q = aa64_vfp_qreg(env, i);
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
28
}
29
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
83
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
84
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
85
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
18
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
87
uint32_t sum;
19
.writefn = pmselr_write, .raw_writefn = raw_write, },
88
sum = do_usad(a, b);
20
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
89
sum += do_usad(a >> 8, b >> 8);
21
- .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
90
- sum += do_usad(a >> 16, b >>16);
22
+ .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
91
+ sum += do_usad(a >> 16, b >> 16);
23
.readfn = pmccntr_read, .writefn = pmccntr_write32,
92
sum += do_usad(a >> 24, b >> 24);
24
.accessfn = pmreg_access_ccntr },
93
return sum;
25
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
94
}
26
--
95
--
27
2.17.0
96
2.20.1
28
97
29
98
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
During code generation, surround CPSR writes and exception returns which
3
Fix code style. Don't use '#' flag of printf format ('%#') in
4
call the EL change hooks with gen_io_start/end. The immediate need is
4
format strings, use '0x' prefix instead
5
for the PMU to access the clock and icount during EL change to support
6
mode filtering.
7
5
8
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
9
Message-id: 1523997485-1905-9-git-send-email-alindsay@codeaurora.org
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/translate-a64.c | 6 ++++++
12
target/arm/translate-a64.c | 4 ++--
14
target/arm/translate.c | 12 ++++++++++++
13
1 file changed, 2 insertions(+), 2 deletions(-)
15
2 files changed, 18 insertions(+)
16
14
17
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
20
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
22
unallocated_encoding(s);
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
23
return;
21
break;
24
}
22
default:
25
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
26
+ gen_io_start();
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
27
+ }
25
__func__, insn, fpopcode, s->pc_curr);
28
gen_helper_exception_return(cpu_env);
26
g_assert_not_reached();
29
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
27
}
30
+ gen_io_end();
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
31
+ }
29
case 0x7f: /* FSQRT (vector) */
32
/* Must exit loop to check un-masked IRQs */
30
break;
33
s->base.is_jmp = DISAS_EXIT;
31
default:
34
return;
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
35
diff --git a/target/arm/translate.c b/target/arm/translate.c
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
36
index XXXXXXX..XXXXXXX 100644
34
g_assert_not_reached();
37
--- a/target/arm/translate.c
35
}
38
+++ b/target/arm/translate.c
36
39
@@ -XXX,XX +XXX,XX @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
40
* appropriately depending on the new Thumb bit, so it must
41
* be called after storing the new PC.
42
*/
43
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
44
+ gen_io_start();
45
+ }
46
gen_helper_cpsr_write_eret(cpu_env, cpsr);
47
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
48
+ gen_io_end();
49
+ }
50
tcg_temp_free_i32(cpsr);
51
/* Must exit loop to check un-masked IRQs */
52
s->base.is_jmp = DISAS_EXIT;
53
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
54
if (exc_return) {
55
/* Restore CPSR from SPSR. */
56
tmp = load_cpu_field(spsr);
57
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
58
+ gen_io_start();
59
+ }
60
gen_helper_cpsr_write_eret(cpu_env, tmp);
61
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
62
+ gen_io_end();
63
+ }
64
tcg_temp_free_i32(tmp);
65
/* Must exit loop to check un-masked IRQs */
66
s->base.is_jmp = DISAS_EXIT;
67
--
37
--
68
2.17.0
38
2.20.1
69
39
70
40
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
3
Fix code style. Space required before the open parenthesis '('.
4
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 1523997485-1905-2-git-send-email-alindsay@codeaurora.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/helper.c | 2 +-
11
target/arm/translate.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
10
13
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
16
--- a/target/arm/translate.c
14
+++ b/target/arm/helper.c
17
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static inline bool arm_ccnt_enabled(CPUARMState *env)
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
16
{
19
- Hardware watchpoints.
17
/* This does not support checking PMCCFILTR_EL0 register */
20
Hardware breakpoints have already been handled and skip this code.
18
21
*/
19
- if (!(env->cp15.c9_pmcr & PMCRE)) {
22
- switch(dc->base.is_jmp) {
20
+ if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) {
23
+ switch (dc->base.is_jmp) {
21
return false;
24
case DISAS_NEXT:
22
}
25
case DISAS_TOO_MANY:
23
26
gen_goto_tb(dc, 1, dc->base.pc_next);
24
--
27
--
25
2.17.0
28
2.20.1
26
29
27
30
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
This eliminates the need for fetching it from el_change_hook_opaque, and
3
We should at least document what this machine is about.
4
allows for supporting multiple el_change_hooks without having to hack
5
something together to find the registered opaque belonging to GICv3.
6
4
7
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 1523997485-1905-6-git-send-email-alindsay@codeaurora.org
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/cpu.h | 10 ----------
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
13
hw/intc/arm_gicv3_cpuif.c | 10 ++--------
15
docs/system/target-arm.rst | 1 +
14
2 files changed, 2 insertions(+), 18 deletions(-)
16
2 files changed, 33 insertions(+)
17
create mode 100644 docs/system/arm/sbsa.rst
15
18
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/docs/system/arm/sbsa.rst
24
@@ -XXX,XX +XXX,XX @@
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
26
+==================================================================
27
+
28
+While the `virt` board is a generic board platform that doesn't match
29
+any real hardware the `sbsa-ref` board intends to look like real
30
+hardware. The `Server Base System Architecture
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
39
+
40
+It is intended to be a machine for developing firmware and testing
41
+standards compliance with operating systems.
42
+
43
+Supported devices
44
+"""""""""""""""""
45
+
46
+The sbsa-ref board supports:
47
+
48
+ - A configurable number of AArch64 CPUs
49
+ - GIC version 3
50
+ - System bus AHCI controller
51
+ - System bus EHCI controller
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
56
+
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
17
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
59
--- a/docs/system/target-arm.rst
19
+++ b/target/arm/cpu.h
60
+++ b/docs/system/target-arm.rst
20
@@ -XXX,XX +XXX,XX @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
21
void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
62
arm/mps2
22
void *opaque);
63
arm/musca
23
64
arm/realview
24
-/**
65
+ arm/sbsa
25
- * arm_get_el_change_hook_opaque:
66
arm/versatile
26
- * Return the opaque data that will be used by the el_change_hook
67
arm/vexpress
27
- * for this CPU.
68
arm/aspeed
28
- */
29
-static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
30
-{
31
- return cpu->el_change_hook_opaque;
32
-}
33
-
34
/**
35
* aa32_vfp_dreg:
36
* Return a pointer to the Dn register within env in 32-bit mode.
37
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/intc/arm_gicv3_cpuif.c
40
+++ b/hw/intc/arm_gicv3_cpuif.c
41
@@ -XXX,XX +XXX,XX @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
42
43
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
44
{
45
- /* Given the CPU, find the right GICv3CPUState struct.
46
- * Since we registered the CPU interface with the EL change hook as
47
- * the opaque pointer, we can just directly get from the CPU to it.
48
- */
49
- return arm_get_el_change_hook_opaque(arm_env_get_cpu(env));
50
+ return env->gicv3state;
51
}
52
53
static bool gicv3_use_ns_bank(CPUARMState *env)
54
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
55
* it might be with code translated by CPU 0 but run by CPU 1, in
56
* which case we'd get the wrong value.
57
* So instead we define the regs with no ri->opaque info, and
58
- * get back to the GICv3CPUState from the ARMCPU by reading back
59
- * the opaque pointer from the el_change_hook, which we're going
60
- * to need to register anyway.
61
+ * get back to the GICv3CPUState from the CPUARMState.
62
*/
63
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
64
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
65
--
69
--
66
2.17.0
70
2.20.1
67
71
68
72
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
This is a bug fix to ensure 64-bit reads of these registers don't read
3
When using a Cortex-A15, the Virt machine does not use any
4
adjacent data.
4
MPCore peripherals. Remove the dependency.
5
5
6
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
7
Message-id: 1523997485-1905-13-git-send-email-alindsay@codeaurora.org
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/cpu.h | 4 ++--
13
hw/arm/Kconfig | 1 -
12
target/arm/helper.c | 5 +++--
14
1 file changed, 1 deletion(-)
13
2 files changed, 5 insertions(+), 4 deletions(-)
14
15
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
--- a/hw/arm/Kconfig
18
+++ b/target/arm/cpu.h
19
+++ b/hw/arm/Kconfig
19
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
20
uint32_t c9_data;
21
imply VFIO_PLATFORM
21
uint64_t c9_pmcr; /* performance monitor control register */
22
imply VFIO_XGMAC
22
uint64_t c9_pmcnten; /* perf monitor counter enables */
23
imply TPM_TIS_SYSBUS
23
- uint32_t c9_pmovsr; /* perf monitor overflow status */
24
- select A15MPCORE
24
- uint32_t c9_pmuserenr; /* perf monitor user enable */
25
select ACPI
25
+ uint64_t c9_pmovsr; /* perf monitor overflow status */
26
select ARM_SMMUV3
26
+ uint64_t c9_pmuserenr; /* perf monitor user enable */
27
select GPIO_KEY
27
uint64_t c9_pmselr; /* perf monitor counter selection register */
28
uint64_t c9_pminten; /* perf monitor interrupt enables */
29
union { /* Memory attribute redirection */
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
35
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
36
.writefn = pmcntenclr_write },
37
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
38
- .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
39
+ .access = PL0_RW,
40
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
41
.accessfn = pmreg_access,
42
.writefn = pmovsr_write,
43
.raw_writefn = raw_write },
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
45
.accessfn = pmreg_access_xevcntr },
46
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
47
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
48
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
49
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
50
.resetvalue = 0,
51
.writefn = pmuserenr_write, .raw_writefn = raw_write },
52
{ .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
53
--
28
--
54
2.17.0
29
2.20.1
55
30
56
31
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Because the design of the PMU requires that the counter values be
3
The helper function did not get updated when we reorganized
4
converted between their delta and guest-visible forms for mode
4
the vector register file for SVE. Since then, the neon dregs
5
filtering, an additional hook which occurs before the EL is changed is
5
are non-sequential and cannot be simply indexed.
6
necessary.
7
6
8
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
7
At the same time, make the helper function operate on 64-bit
9
Message-id: 1523997485-1905-8-git-send-email-alindsay@codeaurora.org
8
quantities so that we do not have to call it twice.
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
17
---
13
target/arm/cpu.h | 22 +++++++++++++++++++---
18
target/arm/helper.h | 2 +-
14
target/arm/internals.h | 7 +++++++
19
target/arm/op_helper.c | 23 +++++++++--------
15
target/arm/cpu.c | 16 ++++++++++++++++
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
16
target/arm/helper.c | 14 ++++++++------
21
3 files changed, 29 insertions(+), 40 deletions(-)
17
target/arm/op_helper.c | 8 ++++++++
18
5 files changed, 58 insertions(+), 9 deletions(-)
19
22
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
21
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
25
--- a/target/arm/helper.h
23
+++ b/target/arm/cpu.h
26
+++ b/target/arm/helper.h
24
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
25
*/
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
26
bool cfgend;
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
27
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
28
+ QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
29
QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
30
33
31
int32_t node_id; /* NUMA node this CPU belongs to */
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
32
@@ -XXX,XX +XXX,XX @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
33
#endif
34
35
/**
36
- * arm_register_el_change_hook:
37
- * Register a hook function which will be called back whenever this
38
+ * arm_register_pre_el_change_hook:
39
+ * Register a hook function which will be called immediately before this
40
* CPU changes exception level or mode. The hook function will be
41
* passed a pointer to the ARMCPU and the opaque data pointer passed
42
* to this function when the hook was registered.
43
+ *
44
+ * Note that if a pre-change hook is called, any registered post-change hooks
45
+ * are guaranteed to subsequently be called.
46
*/
47
-void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
48
+void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
49
void *opaque);
50
+/**
51
+ * arm_register_el_change_hook:
52
+ * Register a hook function which will be called immediately after this
53
+ * CPU changes exception level or mode. The hook function will be
54
+ * passed a pointer to the ARMCPU and the opaque data pointer passed
55
+ * to this function when the hook was registered.
56
+ *
57
+ * Note that any registered hooks registered here are guaranteed to be called
58
+ * if pre-change hooks have been.
59
+ */
60
+void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
61
+ *opaque);
62
63
/**
64
* aa32_vfp_dreg:
65
diff --git a/target/arm/internals.h b/target/arm/internals.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/internals.h
68
+++ b/target/arm/internals.h
69
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
70
MemTxResult response, uintptr_t retaddr);
71
72
/* Call any registered EL change hooks */
73
+static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
74
+{
75
+ ARMELChangeHook *hook, *next;
76
+ QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
77
+ hook->hook(cpu, hook->opaque);
78
+ }
79
+}
80
static inline void arm_call_el_change_hook(ARMCPU *cpu)
81
{
82
ARMELChangeHook *hook, *next;
83
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/cpu.c
86
+++ b/target/arm/cpu.c
87
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
88
| CPU_INTERRUPT_EXITTB);
89
}
90
91
+void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
92
+ void *opaque)
93
+{
94
+ ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
95
+
96
+ entry->hook = hook;
97
+ entry->opaque = opaque;
98
+
99
+ QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
100
+}
101
+
102
void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
103
void *opaque)
104
{
105
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
106
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
107
g_free, g_free);
108
109
+ QLIST_INIT(&cpu->pre_el_change_hooks);
110
QLIST_INIT(&cpu->el_change_hooks);
111
112
#ifndef CONFIG_USER_ONLY
113
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
114
115
g_hash_table_destroy(cpu->cp_regs);
116
117
+ QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
118
+ QLIST_REMOVE(hook, node);
119
+ g_free(hook);
120
+ }
121
QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
122
QLIST_REMOVE(hook, node);
123
g_free(hook);
124
diff --git a/target/arm/helper.c b/target/arm/helper.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/target/arm/helper.c
127
+++ b/target/arm/helper.c
128
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
129
return;
130
}
131
132
+ /* Hooks may change global state so BQL should be held, also the
133
+ * BQL needs to be held for any modification of
134
+ * cs->interrupt_request.
135
+ */
136
+ g_assert(qemu_mutex_iothread_locked());
137
+
138
+ arm_call_pre_el_change_hook(cpu);
139
+
140
assert(!excp_is_internal(cs->exception_index));
141
if (arm_el_is_aa64(env, new_el)) {
142
arm_cpu_do_interrupt_aarch64(cs);
143
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
144
arm_cpu_do_interrupt_aarch32(cs);
145
}
146
147
- /* Hooks may change global state so BQL should be held, also the
148
- * BQL needs to be held for any modification of
149
- * cs->interrupt_request.
150
- */
151
- g_assert(qemu_mutex_iothread_locked());
152
-
153
arm_call_el_change_hook(cpu);
154
155
if (!kvm_enabled()) {
156
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
157
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
158
--- a/target/arm/op_helper.c
38
--- a/target/arm/op_helper.c
159
+++ b/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
160
@@ -XXX,XX +XXX,XX @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
161
/* Write the CPSR for a 32-bit exception return */
41
cpu_loop_exit_restore(cs, ra);
162
void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
163
{
48
{
164
+ qemu_mutex_lock_iothread();
49
- uint32_t val, shift;
165
+ arm_call_pre_el_change_hook(arm_env_get_cpu(env));
50
- uint64_t *table = vn;
166
+ qemu_mutex_unlock_iothread();
51
+ uint64_t tmp, val = 0;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
53
+ uint32_t base_reg = desc >> 2;
54
+ uint32_t shift, index, reg;
55
56
- val = 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
167
+
141
+
168
cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
142
+ tcg_temp_free_i64(def);
169
143
+ tcg_temp_free_i64(val);
170
/* Generated code has already stored the new PC value, but
144
+ tcg_temp_free_i32(desc);
171
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
145
return true;
172
goto illegal_return;
146
}
173
}
147
174
175
+ qemu_mutex_lock_iothread();
176
+ arm_call_pre_el_change_hook(arm_env_get_cpu(env));
177
+ qemu_mutex_unlock_iothread();
178
+
179
if (!return_to_aa64) {
180
env->aarch64 = 0;
181
/* We do a raw CPSR write because aarch64_sync_64_to_32()
182
--
148
--
183
2.17.0
149
2.20.1
184
150
185
151
diff view generated by jsdifflib
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
SNOOP_NONE state handle is moved above in the if ladder, as it's same
3
We can use one MPC per SRAM bank, but we currently only wire the
4
as SNOOP_STRIPPING during data cycles.
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
5
6
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 1524119244-1240-1-git-send-email-saipava@xilinx.com
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/ssi/xilinx_spips.c | 3 ++-
12
hw/arm/armsse.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
14
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/ssi/xilinx_spips.c
17
--- a/hw/arm/armsse.c
17
+++ b/hw/ssi/xilinx_spips.c
18
+++ b/hw/arm/armsse.c
18
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
19
if (fifo8_is_empty(&s->tx_fifo)) {
20
qdev_get_gpio_in(dev_splitter, 0));
20
xilinx_spips_update_ixr(s);
21
qdev_connect_gpio_out(dev_splitter, 0,
21
return;
22
qdev_get_gpio_in_named(dev_secctl,
22
- } else if (s->snoop_state == SNOOP_STRIPING) {
23
- "mpc_status", 0));
23
+ } else if (s->snoop_state == SNOOP_STRIPING ||
24
+ "mpc_status",
24
+ s->snoop_state == SNOOP_NONE) {
25
+ i - IOTS_NUM_EXP_MPC));
25
for (i = 0; i < num_effective_busses(s); ++i) {
26
}
26
tx_rx[i] = fifo8_pop(&s->tx_fifo);
27
27
}
28
qdev_connect_gpio_out(dev_splitter, 1,
28
--
29
--
29
2.17.0
30
2.20.1
30
31
31
32
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This is in preparation for enabling counters other than PMCCNTR
3
The system configuration controller (SYSCFG) doesn't have
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
Remove the invalid code.
4
6
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1523997485-1905-5-git-send-email-alindsay@codeaurora.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/helper.c | 31 ++++++++++++++++++++++---------
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
11
1 file changed, 22 insertions(+), 9 deletions(-)
14
hw/arm/stm32f205_soc.c | 1 -
15
hw/misc/stm32f2xx_syscfg.c | 2 --
16
3 files changed, 5 deletions(-)
12
17
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
16
+++ b/target/arm/helper.c
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct V8M_SAttributes {
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
18
static void v8m_security_lookup(CPUARMState *env, uint32_t address,
23
uint32_t syscfg_exticr3;
19
MMUAccessType access_type, ARMMMUIdx mmu_idx,
24
uint32_t syscfg_exticr4;
20
V8M_SAttributes *sattrs);
25
uint32_t syscfg_cmpcr;
21
-
26
-
22
-/* Definitions for the PMCCNTR and PMCR registers */
27
- qemu_irq irq;
23
-#define PMCRD 0x8
24
-#define PMCRC 0x4
25
-#define PMCRE 0x1
26
#endif
27
28
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
29
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
30
REGINFO_SENTINEL
31
};
28
};
32
29
33
+/* Definitions for the PMU registers */
30
#endif /* HW_STM32F2XX_SYSCFG_H */
34
+#define PMCRN_MASK 0xf800
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
35
+#define PMCRN_SHIFT 11
32
index XXXXXXX..XXXXXXX 100644
36
+#define PMCRD 0x8
33
--- a/hw/arm/stm32f205_soc.c
37
+#define PMCRC 0x4
34
+++ b/hw/arm/stm32f205_soc.c
38
+#define PMCRE 0x1
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
39
+
36
}
40
+static inline uint32_t pmu_num_counters(CPUARMState *env)
37
busdev = SYS_BUS_DEVICE(dev);
41
+{
38
sysbus_mmio_map(busdev, 0, 0x40013800);
42
+ return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
43
+}
40
44
+
41
/* Attach UART (uses USART registers) and USART controllers */
45
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
42
for (i = 0; i < STM_NUM_USARTS; i++) {
46
+static inline uint64_t pmu_counter_mask(CPUARMState *env)
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
47
+{
44
index XXXXXXX..XXXXXXX 100644
48
+ return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
45
--- a/hw/misc/stm32f2xx_syscfg.c
49
+}
46
+++ b/hw/misc/stm32f2xx_syscfg.c
50
+
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
51
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
52
bool isread)
53
{
48
{
54
@@ -XXX,XX +XXX,XX @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
55
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
50
56
uint64_t value)
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
57
{
52
-
58
- value &= (1 << 31);
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
59
+ value &= pmu_counter_mask(env);
54
TYPE_STM32F2XX_SYSCFG, 0x400);
60
env->cp15.c9_pmcnten |= value;
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
61
}
62
63
static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
64
uint64_t value)
65
{
66
- value &= (1 << 31);
67
+ value &= pmu_counter_mask(env);
68
env->cp15.c9_pmcnten &= ~value;
69
}
70
71
@@ -XXX,XX +XXX,XX @@ static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
uint64_t value)
73
{
74
/* We have no event counters so only the C bit can be changed */
75
- value &= (1 << 31);
76
+ value &= pmu_counter_mask(env);
77
env->cp15.c9_pminten |= value;
78
}
79
80
static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
81
uint64_t value)
82
{
83
- value &= (1 << 31);
84
+ value &= pmu_counter_mask(env);
85
env->cp15.c9_pminten &= ~value;
86
}
87
88
--
56
--
89
2.17.0
57
2.20.1
90
58
91
59
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
commit 1d3e65aa7ac5 ("hw/timer: Add value matching support to
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
4
aspeed_timer") increased the vmstate version of aspeed.timer because
4
OMAP2 chip support") takes care of creating the 3 UARTs.
5
the state had changed, but it also bumped the version of the
6
VMSTATE_STRUCT_ARRAY under the aspeed.timerctrl which did not need to.
7
5
8
Change back this version to fix migration.
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
9
11
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
11
Message-id: 20180423101433.17759-1-clg@kaod.org
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
21
---
15
hw/timer/aspeed_timer.c | 2 +-
22
hw/arm/nseries.c | 11 -----------
16
1 file changed, 1 insertion(+), 1 deletion(-)
23
1 file changed, 11 deletions(-)
17
24
18
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
19
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/timer/aspeed_timer.c
27
--- a/hw/arm/nseries.c
21
+++ b/hw/timer/aspeed_timer.c
28
+++ b/hw/arm/nseries.c
22
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_timer_state = {
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
23
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
24
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
31
}
25
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
32
26
- ASPEED_TIMER_NR_TIMERS, 2, vmstate_aspeed_timer,
33
-static void n8x0_uart_setup(struct n800_s *s)
27
+ ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
34
-{
28
AspeedTimer),
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
29
VMSTATE_END_OF_LIST()
36
- /*
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
38
- * here, but this code has been removed with the bluetooth backend.
39
- */
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
41
-}
42
-
43
static void n8x0_usb_setup(struct n800_s *s)
44
{
45
SysBusDevice *dev;
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
47
n8x0_spi_setup(s);
48
n8x0_dss_setup(s);
49
n8x0_cbus_setup(s);
50
- n8x0_uart_setup(s);
51
if (machine_usb(machine)) {
52
n8x0_usb_setup(s);
30
}
53
}
31
--
54
--
32
2.17.0
55
2.20.1
33
56
34
57
diff view generated by jsdifflib
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
It is not uncommon for a contemporary FDT to be larger than 64 KiB,
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
leading to failures loading the device tree from sysfs:
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
5
9
6
qemu-system-aarch64: qemu_fdt_setprop: Couldn't set ...: FDT_ERR_NOSPACE
10
This kind of wiring needs an explicitly created OR gate; add one.
7
11
8
Hence increase the limit to 1 MiB, like on PPC.
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
9
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
For reference, the largest arm64 DTB created from the Linux sources is
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
11
ca. 75 KiB large (100 KiB when built with symbols/fixup support).
12
13
Cc: qemu-stable@nongnu.org
14
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
15
Message-id: 1523541337-23919-1-git-send-email-geert+renesas@glider.be
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
17
---
19
device_tree.c | 2 +-
18
hw/arm/musicpal.c | 17 +++++++++++++----
20
1 file changed, 1 insertion(+), 1 deletion(-)
19
hw/arm/Kconfig | 1 +
20
2 files changed, 14 insertions(+), 4 deletions(-)
21
21
22
diff --git a/device_tree.c b/device_tree.c
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
23
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
24
--- a/device_tree.c
24
--- a/hw/arm/musicpal.c
25
+++ b/device_tree.c
25
+++ b/hw/arm/musicpal.c
26
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@
27
27
#include "ui/console.h"
28
#include <libfdt.h>
28
#include "hw/i2c/i2c.h"
29
29
#include "hw/irq.h"
30
-#define FDT_MAX_SIZE 0x10000
30
+#include "hw/or-irq.h"
31
+#define FDT_MAX_SIZE 0x100000
31
#include "hw/audio/wm8750.h"
32
32
#include "sysemu/block-backend.h"
33
void *create_device_tree(int *sizep)
33
#include "sysemu/runstate.h"
34
{
34
@@ -XXX,XX +XXX,XX @@
35
#define MP_TIMER4_IRQ 7
36
#define MP_EHCI_IRQ 8
37
#define MP_ETH_IRQ 9
38
-#define MP_UART1_IRQ 11
39
-#define MP_UART2_IRQ 11
40
+#define MP_UART_SHARED_IRQ 11
41
#define MP_GPIO_IRQ 12
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
62
+
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
64
+ qdev_get_gpio_in(uart_orgate, 0),
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
68
+ qdev_get_gpio_in(uart_orgate, 1),
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
70
71
/* Register flash */
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/arm/Kconfig
75
+++ b/hw/arm/Kconfig
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
77
78
config MUSICPAL
79
bool
80
+ select OR_IRQ
81
select BITBANG_I2C
82
select MARVELL_88W8618
83
select PTIMER
35
--
84
--
36
2.17.0
85
2.20.1
37
86
38
87
diff view generated by jsdifflib
Deleted patch
1
Remove a stale TODO comment -- we have now made the arm_ldl_ptw()
2
and arm_ldq_ptw() functions propagate physical memory read errors
3
out to their callers.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180419142151.9862-1-peter.maydell@linaro.org
8
---
9
target/arm/helper.c | 8 +-------
10
1 file changed, 1 insertion(+), 7 deletions(-)
11
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.c
15
+++ b/target/arm/helper.c
16
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
17
return addr;
18
}
19
20
-/* All loads done in the course of a page table walk go through here.
21
- * TODO: rather than ignoring errors from physical memory reads (which
22
- * are external aborts in ARM terminology) we should propagate this
23
- * error out so that we can turn it into a Data Abort if this walk
24
- * was being done for a CPU load/store or an address translation instruction
25
- * (but not if it was for a debug access).
26
- */
27
+/* All loads done in the course of a page table walk go through here. */
28
static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
29
ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
30
{
31
--
32
2.17.0
33
34
diff view generated by jsdifflib
Deleted patch
1
In commit 95695effe8caa552b8f2 we changed the v7M/v8M stack
2
pop code to use a new v7m_stack_read() function that checks
3
whether the read should fail due to an MPU or bus abort.
4
We missed one call though, the one which reads the signature
5
word for the callee-saved register part of the frame.
6
1
7
Correct the omission.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20180419142106.9694-1-peter.maydell@linaro.org
13
---
14
target/arm/helper.c | 9 +++++----
15
1 file changed, 5 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
20
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu)
22
static void do_v7m_exception_exit(ARMCPU *cpu)
23
{
24
CPUARMState *env = &cpu->env;
25
- CPUState *cs = CPU(cpu);
26
uint32_t excret;
27
uint32_t xpsr;
28
bool ufault = false;
29
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
30
((excret & R_V7M_EXCRET_ES_MASK) == 0 ||
31
(excret & R_V7M_EXCRET_DCRS_MASK) == 0)) {
32
uint32_t expected_sig = 0xfefa125b;
33
- uint32_t actual_sig = ldl_phys(cs->as, frameptr);
34
+ uint32_t actual_sig;
35
36
- if (expected_sig != actual_sig) {
37
+ pop_ok = v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx);
38
+
39
+ if (pop_ok && expected_sig != actual_sig) {
40
/* Take a SecureFault on the current stack */
41
env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK;
42
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
43
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
44
return;
45
}
46
47
- pop_ok =
48
+ pop_ok = pop_ok &&
49
v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) &&
50
v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) &&
51
v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx) &&
52
--
53
2.17.0
54
55
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
3
We don't need to fill the full pic[] array if we only use
4
Message-id: 1523997485-1905-7-git-send-email-alindsay@codeaurora.org
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
when necessary.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/cpu.h | 20 ++++++++++----------
12
hw/arm/musicpal.c | 25 +++++++++++++------------
9
target/arm/internals.h | 7 ++++---
13
1 file changed, 13 insertions(+), 12 deletions(-)
10
target/arm/cpu.c | 21 ++++++++++++++++-----
11
3 files changed, 30 insertions(+), 18 deletions(-)
12
14
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
17
--- a/hw/arm/musicpal.c
16
+++ b/target/arm/cpu.h
18
+++ b/hw/arm/musicpal.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
18
} CPUARMState;
20
static void musicpal_init(MachineState *machine)
19
20
/**
21
- * ARMELChangeHook:
22
+ * ARMELChangeHookFn:
23
* type of a function which can be registered via arm_register_el_change_hook()
24
* to get callbacks when the CPU changes its exception level or mode.
25
*/
26
-typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
27
-
28
+typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
29
+typedef struct ARMELChangeHook ARMELChangeHook;
30
+struct ARMELChangeHook {
31
+ ARMELChangeHookFn *hook;
32
+ void *opaque;
33
+ QLIST_ENTRY(ARMELChangeHook) node;
34
+};
35
36
/* These values map onto the return values for
37
* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
38
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
39
*/
40
bool cfgend;
41
42
- ARMELChangeHook *el_change_hook;
43
- void *el_change_hook_opaque;
44
+ QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
45
46
int32_t node_id; /* NUMA node this CPU belongs to */
47
48
@@ -XXX,XX +XXX,XX @@ static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
49
* CPU changes exception level or mode. The hook function will be
50
* passed a pointer to the ARMCPU and the opaque data pointer passed
51
* to this function when the hook was registered.
52
- *
53
- * Note that we currently only support registering a single hook function,
54
- * and will assert if this function is called twice.
55
- * This facility is intended for the use of the GICv3 emulation.
56
*/
57
-void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
58
+void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
59
void *opaque);
60
61
/**
62
diff --git a/target/arm/internals.h b/target/arm/internals.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/internals.h
65
+++ b/target/arm/internals.h
66
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
67
int mmu_idx, MemTxAttrs attrs,
68
MemTxResult response, uintptr_t retaddr);
69
70
-/* Call the EL change hook if one has been registered */
71
+/* Call any registered EL change hooks */
72
static inline void arm_call_el_change_hook(ARMCPU *cpu)
73
{
21
{
74
- if (cpu->el_change_hook) {
22
ARMCPU *cpu;
75
- cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
23
- qemu_irq pic[32];
76
+ ARMELChangeHook *hook, *next;
24
DeviceState *dev;
77
+ QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
25
+ DeviceState *pic;
78
+ hook->hook(cpu, hook->opaque);
26
DeviceState *uart_orgate;
79
}
27
DeviceState *i2c_dev;
80
}
28
DeviceState *lcd_dev;
81
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
82
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
&error_fatal);
83
index XXXXXXX..XXXXXXX 100644
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
84
--- a/target/arm/cpu.c
32
85
+++ b/target/arm/cpu.c
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
86
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
87
| CPU_INTERRUPT_EXITTB);
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
88
}
36
- for (i = 0; i < 32; i++) {
89
37
- pic[i] = qdev_get_gpio_in(dev, i);
90
-void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
38
- }
91
+void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
92
void *opaque)
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
93
{
41
- pic[MP_TIMER4_IRQ], NULL);
94
- /* We currently only support registering a single hook function */
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
95
- assert(!cpu->el_change_hook);
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
96
- cpu->el_change_hook = hook;
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
97
- cpu->el_change_hook_opaque = opaque;
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
98
+ ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
99
+
47
100
+ entry->hook = hook;
48
/* Logically OR both UART IRQs together */
101
+ entry->opaque = opaque;
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
102
+
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
103
+ QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
104
}
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
105
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
106
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
107
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
55
108
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
109
g_free, g_free);
57
qdev_get_gpio_in(uart_orgate, 0),
110
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
111
+ QLIST_INIT(&cpu->el_change_hooks);
59
OBJECT(get_system_memory()), &error_fatal);
112
+
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
113
#ifndef CONFIG_USER_ONLY
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
114
/* Our inbound IRQ and FIQ lines */
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
115
if (kvm_enabled()) {
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
116
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
117
static void arm_cpu_finalizefn(Object *obj)
65
118
{
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
119
ARMCPU *cpu = ARM_CPU(obj);
67
120
+ ARMELChangeHook *hook, *next;
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
121
+
69
122
g_hash_table_destroy(cpu->cp_regs);
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
123
+
71
- pic[MP_GPIO_IRQ]);
124
+ QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
125
+ QLIST_REMOVE(hook, node);
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
126
+ g_free(hook);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
127
+ }
75
128
}
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
129
77
NULL);
130
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
131
--
85
--
132
2.17.0
86
2.20.1
133
87
134
88
diff view generated by jsdifflib
1
In commit 210f47840dd62, we changed the bcm2836 SoC object to
1
The nseries machines have a codepath that allows them to load a
2
always create a CPU of the correct type for that SoC model. This
2
secondary bootloader. This code wasn't checking that the
3
makes the default_cpu_type settings in the MachineClass structs
3
load_image_targphys() succeeded. Check the return value and report
4
for the raspi2 and raspi3 boards redundant. We didn't change
4
the error to the user.
5
those at the time because it would have meant a temporary
6
regression in a corner case of error handling if the user
7
requested a non-existing CPU type. The -cpu parse handling
8
changes in 2278b93941d42c3 mean that it no longer implicitly
9
depends on default_cpu_type for this to work, so we can now
10
delete the redundant default_cpu_type fields.
11
5
6
While we're in the vicinity, fix the comment style of the
7
comment documenting what this image load is doing.
8
9
Fixes: Coverity CID 1192904
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20180420155547.9497-1-peter.maydell@linaro.org
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
15
---
13
---
16
hw/arm/raspi.c | 2 --
14
hw/arm/nseries.c | 15 +++++++++++----
17
1 file changed, 2 deletions(-)
15
1 file changed, 11 insertions(+), 4 deletions(-)
18
16
19
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/raspi.c
19
--- a/hw/arm/nseries.c
22
+++ b/hw/arm/raspi.c
20
+++ b/hw/arm/nseries.c
23
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
24
mc->no_parallel = 1;
22
/* No, wait, better start at the ROM. */
25
mc->no_floppy = 1;
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
26
mc->no_cdrom = 1;
24
27
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
25
- /* This is intended for loading the `secondary.bin' program from
28
mc->max_cpus = BCM283X_NCPUS;
26
+ /*
29
mc->min_cpus = BCM283X_NCPUS;
27
+ * This is intended for loading the `secondary.bin' program from
30
mc->default_cpus = BCM283X_NCPUS;
28
* Nokia images (the NOLO bootloader). The entry point seems
31
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
29
* to be at OMAP2_Q2_BASE + 0x400000.
32
mc->no_parallel = 1;
30
*
33
mc->no_floppy = 1;
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
34
mc->no_cdrom = 1;
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
35
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
33
*
36
mc->max_cpus = BCM283X_NCPUS;
34
* The code above is for loading the `zImage' file from Nokia
37
mc->min_cpus = BCM283X_NCPUS;
35
- * images. */
38
mc->default_cpus = BCM283X_NCPUS;
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
37
- machine->ram_size - 0x400000);
38
+ * images.
39
+ */
40
+ if (load_image_targphys(option_rom[0].name,
41
+ OMAP2_Q2_BASE + 0x400000,
42
+ machine->ram_size - 0x400000) < 0) {
43
+ error_report("Failed to load secondary bootloader %s",
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
39
--
50
--
40
2.17.0
51
2.20.1
41
52
42
53
diff view generated by jsdifflib
1
From: Aaron Lindsay <alindsay@codeaurora.org>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
It was shifted to the left one bit too few.
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
4
plus one. Currently, it's counting the number of times these transitions
5
do _not_ happen, plus one.
4
6
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
7
Source:
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1523997485-1905-10-git-send-email-alindsay@codeaurora.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
10
target/arm/helper.c | 2 +-
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
12
18
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
21
--- a/tests/qtest/npcm7xx_rng-test.c
16
+++ b/target/arm/helper.c
22
+++ b/tests/qtest/npcm7xx_rng-test.c
17
@@ -XXX,XX +XXX,XX @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
18
uint64_t value)
24
pi = (double)nr_ones / nr_bits;
19
{
25
20
pmccntr_sync(env);
26
for (k = 0; k < nr_bits - 1; k++) {
21
- env->cp15.pmccfiltr_el0 = value & 0x7E000000;
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
22
+ env->cp15.pmccfiltr_el0 = value & 0xfc000000;
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
23
pmccntr_sync(env);
29
}
24
}
30
vn_obs += 1;
25
31
26
--
32
--
27
2.17.0
33
2.20.1
28
34
29
35
diff view generated by jsdifflib
Deleted patch
1
Currently we use memory_region_init_ram_nomigrate() to create
2
the "highbank.sysram" memory region, and we don't manually
3
register it with vmstate_register_ram(). This currently
4
means that its contents are migrated but as a ram block
5
whose name is the empty string; in future it may mean they
6
are not migrated at all. Use memory_region_init_ram() instead.
7
1
8
Note that this is a cross-version migration compatibility
9
break for the "highbank" and "midway" machines.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20180420124835.7268-2-peter.maydell@linaro.org
13
---
14
hw/arm/highbank.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/highbank.c
20
+++ b/hw/arm/highbank.c
21
@@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
22
memory_region_add_subregion(sysmem, 0, dram);
23
24
sysram = g_new(MemoryRegion, 1);
25
- memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000,
26
+ memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
27
&error_fatal);
28
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
29
if (bios_name != NULL) {
30
--
31
2.17.0
32
33
diff view generated by jsdifflib
1
Currently we use vmstate_register_ram_global() for the SRAM;
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
2
this is not a good idea for devices, because it means that
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
you can only ever create one instance of the device, as
3
trans function up above the access check.
4
the second instance would get a RAM block name clash.
5
Instead, use memory_region_init_ram(), which automatically
6
registers the RAM block with a local-to-the-device name.
7
8
Note that this would be a cross-version migration compatibility break
9
for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines,
10
but migration is currently broken for them.
11
4
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Cédric Le Goater <clg@kaod.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Tested-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
15
Message-id: 20180420124835.7268-4-peter.maydell@linaro.org
16
---
8
---
17
hw/arm/aspeed_soc.c | 3 +--
9
target/arm/translate-neon.c.inc | 8 ++++----
18
1 file changed, 1 insertion(+), 2 deletions(-)
10
1 file changed, 4 insertions(+), 4 deletions(-)
19
11
20
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/aspeed_soc.c
14
--- a/target/arm/translate-neon.c.inc
23
+++ b/hw/arm/aspeed_soc.c
15
+++ b/target/arm/translate-neon.c.inc
24
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
17
return false;
25
}
18
}
26
19
27
/* SRAM */
20
- if (!vfp_access_check(s)) {
28
- memory_region_init_ram_nomigrate(&s->sram, OBJECT(dev), "aspeed.sram",
21
- return true;
29
+ memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
22
- }
30
sc->info->sram_size, &err);
23
-
31
if (err) {
24
if ((a->vn + a->len + 1) > 32) {
32
error_propagate(errp, err);
25
/*
33
return;
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
28
return false;
34
}
29
}
35
- vmstate_register_ram_global(&s->sram);
30
36
memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
31
+ if (!vfp_access_check(s)) {
37
&s->sram);
32
+ return true;
38
33
+ }
34
+
35
desc = tcg_const_i32((a->vn << 2) | a->len);
36
def = tcg_temp_new_i64();
37
if (a->op) {
39
--
38
--
40
2.17.0
39
2.20.1
41
40
42
41
diff view generated by jsdifflib