1
Arm patch queue -- these are all bug fix patches but we might
1
Here's another arm pullreq; nothing too exciting in here I think.
2
as well put them in to rc0...
3
2
4
thanks
3
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
6
The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:
8
7
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
8
Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430
14
13
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
14
for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:
16
15
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
16
tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
20
* hw/core/clock: allow clock_propagate on child clocks
22
* dump: Update correct kdump phys_base field for AArch64
21
* hvf: arm: Remove unused PL1_WRITE_MASK define
23
* char: i.MX: Add support for "TX complete" interrupt
22
* target/arm: Restrict translation disabled alignment check to VMSA
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
23
* docs/system/arm/emulation.rst: Add missing implemented features
25
to boot a Debian Linux kernel on raspi3
24
* target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
25
* tests/avocado: update sunxi kernel from armbian to 6.6.16
26
* target/arm: Make new CPUs default to 1GHz generic timer
27
* hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
28
* hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
29
* hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
30
* hw/arm: Add DM163 display to B-L475E-IOT01A board
26
31
27
----------------------------------------------------------------
32
----------------------------------------------------------------
28
Andrey Smirnov (2):
33
Alexandra Diupina (1):
29
char: i.MX: Simplify imx_update()
34
hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
30
char: i.MX: Add support for "TX complete" interrupt
31
35
32
Guenter Roeck (1):
36
Inès Varhol (5):
33
fsl-imx6: Swap Ethernet interrupt defines
37
hw/display : Add device DM163
38
hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
39
hw/arm : Create Bl475eMachineState
40
hw/arm : Connect DM163 to B-L475E-IOT01A
41
tests/qtest : Add testcase for DM163
34
42
35
Peter Maydell (9):
43
Peter Maydell (10):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
44
docs/system/arm/emulation.rst: Add missing implemented features
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
45
target/arm: Enable FEAT_CSV2_3 for -cpu max
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
46
target/arm: Enable FEAT_ETS2 for -cpu max
39
hw/arm/bcm2386: Fix parent type of bcm2386
47
target/arm: Implement ID_AA64MMFR3_EL1
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
48
target/arm: Enable FEAT_Spec_FPACC for -cpu max
41
hw/arm/bcm2836: Create proper bcm2837 device
49
tests/avocado: update sunxi kernel from armbian to 6.6.16
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
50
target/arm: Refactor default generic timer frequency handling
43
hw/arm/bcm2836: Hardcode correct CPU type
51
hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
52
hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
53
target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
45
54
46
Wei Huang (1):
55
Philippe Mathieu-Daudé (1):
47
dump: Update correct kdump phys_base field for AArch64
56
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
48
57
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
58
Raphael Poggi (1):
50
include/hw/arm/fsl-imx6.h | 4 +-
59
hw/core/clock: allow clock_propagate on child clocks
51
include/hw/char/imx_serial.h | 3 ++
52
dump.c | 14 +++++--
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
54
hw/arm/boot.c | 12 ++++++
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
57
hw/net/imx_fec.c | 28 +++++++++++++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
59
60
61
Richard Henderson (1):
62
target/arm: Restrict translation disabled alignment check to VMSA
63
64
Thomas Huth (1):
65
hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
66
67
Zenghui Yu (1):
68
hvf: arm: Remove PL1_WRITE_MASK
69
70
docs/system/arm/b-l475e-iot01a.rst | 3 +-
71
docs/system/arm/emulation.rst | 42 ++++-
72
include/hw/display/dm163.h | 59 ++++++
73
include/hw/watchdog/sbsa_gwdt.h | 3 +-
74
target/arm/cpu.h | 28 +++
75
target/arm/internals.h | 15 +-
76
hw/arm/b-l475e-iot01a.c | 105 +++++++++--
77
hw/arm/npcm7xx.c | 3 +-
78
hw/arm/sbsa-ref.c | 16 ++
79
hw/arm/stm32l4x5_soc.c | 6 +-
80
hw/char/stm32l4x5_usart.c | 1 +
81
hw/core/clock.c | 1 -
82
hw/core/machine.c | 4 +-
83
hw/display/dm163.c | 349 ++++++++++++++++++++++++++++++++++++
84
hw/dma/xlnx_dpdma.c | 20 +--
85
hw/watchdog/sbsa_gwdt.c | 15 +-
86
target/arm/cpu.c | 42 +++--
87
target/arm/cpu64.c | 2 +
88
target/arm/helper.c | 22 +--
89
target/arm/hvf/hvf.c | 3 +-
90
target/arm/kvm.c | 2 +
91
target/arm/tcg/cpu32.c | 6 +-
92
target/arm/tcg/cpu64.c | 28 ++-
93
target/arm/tcg/hflags.c | 12 +-
94
tests/qtest/dm163-test.c | 194 ++++++++++++++++++++
95
tests/qtest/stm32l4x5_gpio-test.c | 13 +-
96
tests/qtest/stm32l4x5_syscfg-test.c | 17 +-
97
hw/arm/Kconfig | 1 +
98
hw/display/Kconfig | 3 +
99
hw/display/meson.build | 1 +
100
hw/display/trace-events | 14 ++
101
tests/avocado/boot_linux_console.py | 70 ++++----
102
tests/avocado/replay_kernel.py | 8 +-
103
tests/qtest/meson.build | 2 +
104
34 files changed, 987 insertions(+), 123 deletions(-)
105
create mode 100644 include/hw/display/dm163.h
106
create mode 100644 hw/display/dm163.c
107
create mode 100644 tests/qtest/dm163-test.c
108
diff view generated by jsdifflib
New patch
1
From: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
1
2
3
clock_propagate() has an assert that clk->source is NULL, i.e. that
4
you are calling it on a clock which has no source clock. This made
5
sense in the original design where the only way for a clock's
6
frequency to change if it had a source clock was when that source
7
clock changed. However, we subsequently added multiplier/divider
8
support, but didn't look at what that meant for propagation.
9
10
If a clock-management device changes the multiplier or divider value
11
on a clock, it needs to propagate that change down to child clocks,
12
even if the clock has a source clock set. So the assertion is now
13
incorrect.
14
15
Remove the assertion.
16
17
Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
18
Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
[PMM: Rewrote the commit message]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/core/clock.c | 1 -
24
1 file changed, 1 deletion(-)
25
26
diff --git a/hw/core/clock.c b/hw/core/clock.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/core/clock.c
29
+++ b/hw/core/clock.c
30
@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
31
32
void clock_propagate(Clock *clk)
33
{
34
- assert(clk->source == NULL);
35
trace_clock_propagate(CLOCK_PATH(clk));
36
clock_propagate_period(clk, true);
37
}
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
1
From: Zenghui Yu <zenghui.yu@linux.dev>
1
2
3
As it had never been used since the first commit a1477da3ddeb ("hvf: Add
4
Apple Silicon support").
5
6
Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
7
Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/hvf/hvf.c | 1 -
12
1 file changed, 1 deletion(-)
13
14
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/hvf/hvf.c
17
+++ b/target/arm/hvf/hvf.c
18
@@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void)
19
20
#define HVF_SYSREG(crn, crm, op0, op1, op2) \
21
ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
22
-#define PL1_WRITE_MASK 0x4
23
24
#define SYSREG_OP0_SHIFT 20
25
#define SYSREG_OP0_MASK 0x3
26
--
27
2.34.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
For cpus using PMSA, when the MPU is disabled, the default memory
4
type is Normal, Non-cachable. This means that it should not
5
have alignment restrictions enforced.
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
9
Reported-by: Clément Chigot <chigot@adacore.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Tested-by: Clément Chigot <chigot@adacore.com>
13
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
14
[PMM: trivial comment, commit message tweaks]
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/tcg/hflags.c | 12 ++++++++++--
18
1 file changed, 10 insertions(+), 2 deletions(-)
19
20
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/tcg/hflags.c
23
+++ b/target/arm/tcg/hflags.c
24
@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
25
}
26
27
/*
28
- * If translation is disabled, then the default memory type is
29
- * Device(-nGnRnE) instead of Normal, which requires that alignment
30
+ * With PMSA, when the MPU is disabled, all memory types in the
31
+ * default map are Normal, so don't need aligment enforcing.
32
+ */
33
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
34
+ return false;
35
+ }
36
+
37
+ /*
38
+ * With VMSA, if translation is disabled, then the default memory type
39
+ * is Device(-nGnRnE) instead of Normal, which requires that alignment
40
* be enforced. Since this affects all ram, it is most efficient
41
* to handle this during translation.
42
*/
43
--
44
2.34.1
45
46
diff view generated by jsdifflib
New patch
1
As of version DDI0487K.a of the Arm ARM, some architectural features
2
which previously didn't have official names have been named. Add
3
these to the list of features which QEMU's TCG emulation supports.
4
Mostly these are features which we thought of as part of baseline 8.0
5
support. For SVE and SVE2, the names have been brought into line
6
with the FEAT_* naming convention of other extensions, and some
7
sub-components split into separate FEAT_ items. In a few cases (eg
8
FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
13
---
14
docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++--
15
1 file changed, 36 insertions(+), 2 deletions(-)
16
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
20
+++ b/docs/system/arm/emulation.rst
21
@@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for
22
the following architecture extensions:
23
24
- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
25
+- FEAT_AA32EL0 (Support for AArch32 at EL0)
26
+- FEAT_AA32EL1 (Support for AArch32 at EL1)
27
+- FEAT_AA32EL2 (Support for AArch32 at EL2)
28
+- FEAT_AA32EL3 (Support for AArch32 at EL3)
29
- FEAT_AA32HPD (AArch32 hierarchical permission disables)
30
- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
31
+- FEAT_AA64EL0 (Support for AArch64 at EL0)
32
+- FEAT_AA64EL1 (Support for AArch64 at EL1)
33
+- FEAT_AA64EL2 (Support for AArch64 at EL2)
34
+- FEAT_AA64EL3 (Support for AArch64 at EL3)
35
+- FEAT_AdvSIMD (Advanced SIMD Extension)
36
- FEAT_AES (AESD and AESE instructions)
37
+- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
38
+- FEAT_ASID16 (16 bit ASID)
39
- FEAT_BBM at level 2 (Translation table break-before-make levels)
40
- FEAT_BF16 (AArch64 BFloat16 instructions)
41
- FEAT_BTI (Branch Target Identification)
42
+- FEAT_CCIDX (Extended cache index)
43
- FEAT_CRC32 (CRC32 instructions)
44
+- FEAT_Crypto (Cryptographic Extension)
45
- FEAT_CSV2 (Cache speculation variant 2)
46
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
47
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
48
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
49
- FEAT_DGH (Data gathering hint)
50
- FEAT_DIT (Data Independent Timing instructions)
51
- FEAT_DPB (DC CVAP instruction)
52
+- FEAT_DPB2 (DC CVADP instruction)
53
+- FEAT_Debugv8p1 (Debug with VHE)
54
- FEAT_Debugv8p2 (Debug changes for v8.2)
55
- FEAT_Debugv8p4 (Debug changes for v8.4)
56
- FEAT_DotProd (Advanced SIMD dot product instructions)
57
- FEAT_DoubleFault (Double Fault Extension)
58
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
59
- FEAT_ECV (Enhanced Counter Virtualization)
60
+- FEAT_EL0 (Support for execution at EL0)
61
+- FEAT_EL1 (Support for execution at EL1)
62
+- FEAT_EL2 (Support for execution at EL2)
63
+- FEAT_EL3 (Support for execution at EL3)
64
- FEAT_EPAC (Enhanced pointer authentication)
65
- FEAT_ETS (Enhanced Translation Synchronization)
66
- FEAT_EVT (Enhanced Virtualization Traps)
67
+- FEAT_F32MM (Single-precision Matrix Multiplication)
68
+- FEAT_F64MM (Double-precision Matrix Multiplication)
69
- FEAT_FCMA (Floating-point complex number instructions)
70
- FEAT_FGT (Fine-Grained Traps)
71
- FEAT_FHM (Floating-point half-precision multiplication instructions)
72
+- FEAT_FP (Floating Point extensions)
73
- FEAT_FP16 (Half-precision floating-point data processing)
74
- FEAT_FPAC (Faulting on AUT* instructions)
75
- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
76
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
77
- FEAT_LSE (Large System Extensions)
78
- FEAT_LSE2 (Large System Extensions v2)
79
- FEAT_LVA (Large Virtual Address space)
80
+- FEAT_MixedEnd (Mixed-endian support)
81
+- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
82
- FEAT_MOPS (Standardization of memory operations)
83
- FEAT_MTE (Memory Tagging Extension)
84
- FEAT_MTE2 (Memory Tagging Extension)
85
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
86
+- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
87
- FEAT_NMI (Non-maskable Interrupt)
88
- FEAT_NV (Nested Virtualization)
89
- FEAT_NV2 (Enhanced nested virtualization support)
90
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
91
- FEAT_PAuth (Pointer authentication)
92
- FEAT_PAuth2 (Enhancements to pointer authentication)
93
- FEAT_PMULL (PMULL, PMULL2 instructions)
94
+- FEAT_PMUv3 (PMU extension version 3)
95
- FEAT_PMUv3p1 (PMU Extensions v3.1)
96
- FEAT_PMUv3p4 (PMU Extensions v3.4)
97
- FEAT_PMUv3p5 (PMU Extensions v3.5)
98
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
99
- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
100
- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
101
- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
102
+- FEAT_SVE (Scalable Vector Extension)
103
+- FEAT_SVE_AES (Scalable Vector AES instructions)
104
+- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
105
+- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
106
+- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
107
+- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
108
+- FEAT_SVE2 (Scalable Vector Extension version 2)
109
- FEAT_SPECRES (Speculation restriction instructions)
110
- FEAT_SSBS (Speculative Store Bypass Safe)
111
+- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
112
+- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
113
+- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
114
- FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
115
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
116
- FEAT_TLBIRANGE (TLB invalidate range instructions)
117
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
118
- FEAT_VHE (Virtualization Host Extensions)
119
- FEAT_VMID16 (16-bit VMID)
120
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
121
-- SVE (The Scalable Vector Extension)
122
-- SVE2 (The Scalable Vector Extension v2)
123
124
For information on the specifics of these extensions, please refer
125
to the `Armv8-A Arm Architecture Reference Manual
126
--
127
2.34.1
diff view generated by jsdifflib
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
2
information about whether branch targets and branch history trained
3
is required for Linux to boot.
3
in one hardware described context can control speculative execution
4
in a different hardware context.
5
6
There is no branch prediction in TCG, so we don't need to do anything
7
to be compliant with this. Upadte the '-cpu max' ID registers to
8
advertise the feature.
4
9
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
13
Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
9
---
14
---
10
hw/arm/bcm2836.c | 11 +++++++----
15
docs/system/arm/emulation.rst | 1 +
11
1 file changed, 7 insertions(+), 4 deletions(-)
16
target/arm/tcg/cpu64.c | 4 ++--
17
2 files changed, 3 insertions(+), 2 deletions(-)
12
18
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
21
--- a/docs/system/arm/emulation.rst
16
+++ b/hw/arm/bcm2836.c
22
+++ b/docs/system/arm/emulation.rst
17
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
24
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
19
struct BCM283XInfo {
25
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
20
const char *name;
26
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
21
+ int clusterid;
27
+- FEAT_CSV2_3 (Cache speculation variant 2, version 3)
22
};
28
- FEAT_CSV3 (Cache speculation variant 3)
23
29
- FEAT_DGH (Data gathering hint)
24
static const BCM283XInfo bcm283x_socs[] = {
30
- FEAT_DIT (Data Independent Timing instructions)
25
{
31
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
26
.name = TYPE_BCM2836,
32
index XXXXXXX..XXXXXXX 100644
27
+ .clusterid = 0xf,
33
--- a/target/arm/tcg/cpu64.c
28
},
34
+++ b/target/arm/tcg/cpu64.c
29
{
35
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
30
.name = TYPE_BCM2837,
36
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
31
+ .clusterid = 0x0,
37
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
32
},
38
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
33
};
39
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
34
40
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
41
t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
42
cpu->isar.id_aa64pfr0 = t;
37
{
43
38
BCM283XState *s = BCM283X(dev);
44
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
45
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
40
+ const BCM283XInfo *info = bc->info;
46
t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
41
Object *obj;
47
t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
42
Error *err = NULL;
48
- t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
43
int n;
49
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
50
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
51
cpu->isar.id_aa64pfr1 = t;
46
52
47
for (n = 0; n < BCM283X_NCPUS; n++) {
48
- /* Mirror bcm2836, which has clusterid set to 0xf
49
- * TODO: this should be converted to a property of ARM_CPU
50
- */
51
- s->cpus[n].mp_affinity = 0xF00 | n;
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
53
--
58
2.16.2
54
2.34.1
59
55
60
56
diff view generated by jsdifflib
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
FEAT_ETS2 is a tighter set of guarantees about memory ordering
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
2
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
3
but the BCM2386State struct only defines the parent_obj field
3
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
4
as DeviceState. This would have caused problems if anything
4
now gives no greater guarantees than ETS == 0.
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
5
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
6
FEAT_ETS2 requires:
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
7
* the virtual address of a load or store that appears in program
8
provides.
8
order after a DSB cannot be translated until after the DSB
9
completes (section B2.10.9)
10
* TLB maintenance operations that only affect translations without
11
execute permission are guaranteed complete after a DSB
12
(R_BLDZX)
13
* if a memory access RW2 is ordered-before memory access RW2,
14
then RW1 is also ordered-before any translation table walk
15
generated by RW2 that generates a Translation, Address size
16
or Access flag fault (R_NNFPF, I_CLGHP)
17
18
As with FEAT_ETS, QEMU is already compliant, because we do not
19
reorder translation table walk memory accesses relative to other
20
memory accesses, and we always guarantee to have finished TLB
21
maintenance as soon as the TLB op is done.
22
23
Update the documentation to list FEAT_ETS2 instead of the
24
no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.
9
25
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
29
Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
14
---
30
---
15
hw/arm/bcm2836.c | 2 +-
31
docs/system/arm/emulation.rst | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
32
target/arm/tcg/cpu32.c | 2 +-
33
target/arm/tcg/cpu64.c | 2 +-
34
3 files changed, 3 insertions(+), 3 deletions(-)
17
35
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
36
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
38
--- a/docs/system/arm/emulation.rst
21
+++ b/hw/arm/bcm2836.c
39
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
40
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
41
- FEAT_EL2 (Support for execution at EL2)
24
static const TypeInfo bcm2836_type_info = {
42
- FEAT_EL3 (Support for execution at EL3)
25
.name = TYPE_BCM2836,
43
- FEAT_EPAC (Enhanced pointer authentication)
26
- .parent = TYPE_SYS_BUS_DEVICE,
44
-- FEAT_ETS (Enhanced Translation Synchronization)
27
+ .parent = TYPE_DEVICE,
45
+- FEAT_ETS2 (Enhanced Translation Synchronization)
28
.instance_size = sizeof(BCM2836State),
46
- FEAT_EVT (Enhanced Virtualization Traps)
29
.instance_init = bcm2836_init,
47
- FEAT_F32MM (Single-precision Matrix Multiplication)
30
.class_init = bcm2836_class_init,
48
- FEAT_F64MM (Double-precision Matrix Multiplication)
49
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/tcg/cpu32.c
52
+++ b/target/arm/tcg/cpu32.c
53
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
54
cpu->isar.id_mmfr4 = t;
55
56
t = cpu->isar.id_mmfr5;
57
- t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
58
+ t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
59
cpu->isar.id_mmfr5 = t;
60
61
t = cpu->isar.id_pfr0;
62
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/tcg/cpu64.c
65
+++ b/target/arm/tcg/cpu64.c
66
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
67
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
68
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
69
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
70
- t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
71
+ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */
72
t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
73
t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
74
cpu->isar.id_aa64mmfr1 = t;
31
--
75
--
32
2.16.2
76
2.34.1
33
77
34
78
diff view generated by jsdifflib
1
If we're directly booting a Linux kernel and the CPU supports both
1
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
2
ID_AA64MMFR3_EL1. Implement this register, so that we can set the
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
3
fields if we need to. There's no behaviour change here since we
4
instruction is enabled rather than UNDEFing. Otherwise at least some
4
don't currently set the register value to non-zero.
5
kernels will panic when trying to initialize KVM in the guest.
6
5
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
9
---
10
---
10
hw/arm/boot.c | 5 +++++
11
target/arm/cpu.h | 17 +++++++++++++++++
11
1 file changed, 5 insertions(+)
12
target/arm/helper.c | 6 ++++--
13
target/arm/hvf/hvf.c | 2 ++
14
target/arm/kvm.c | 2 ++
15
4 files changed, 25 insertions(+), 2 deletions(-)
12
16
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
19
--- a/target/arm/cpu.h
16
+++ b/hw/arm/boot.c
20
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
21
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
18
assert(!info->secure_board_setup);
22
uint64_t id_aa64mmfr0;
19
}
23
uint64_t id_aa64mmfr1;
20
24
uint64_t id_aa64mmfr2;
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
25
+ uint64_t id_aa64mmfr3;
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
26
uint64_t id_aa64dfr0;
23
+ env->cp15.scr_el3 |= SCR_HCE;
27
uint64_t id_aa64dfr1;
24
+ }
28
uint64_t id_aa64zfr0;
29
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
30
FIELD(ID_AA64MMFR2, EVT, 56, 4)
31
FIELD(ID_AA64MMFR2, E0PD, 60, 4)
32
33
+FIELD(ID_AA64MMFR3, TCRX, 0, 4)
34
+FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
35
+FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
36
+FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
37
+FIELD(ID_AA64MMFR3, S1POE, 16, 4)
38
+FIELD(ID_AA64MMFR3, S2POE, 20, 4)
39
+FIELD(ID_AA64MMFR3, AIE, 24, 4)
40
+FIELD(ID_AA64MMFR3, MEC, 28, 4)
41
+FIELD(ID_AA64MMFR3, D128, 32, 4)
42
+FIELD(ID_AA64MMFR3, D128_2, 36, 4)
43
+FIELD(ID_AA64MMFR3, SNERR, 40, 4)
44
+FIELD(ID_AA64MMFR3, ANERR, 44, 4)
45
+FIELD(ID_AA64MMFR3, SDERR, 52, 4)
46
+FIELD(ID_AA64MMFR3, ADERR, 56, 4)
47
+FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
25
+
48
+
26
/* Set to non-secure if not a secure boot */
49
FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
27
if (!info->secure_boot &&
50
FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
28
(cs != first_cpu || !info->secure_board_setup)) {
51
FIELD(ID_AA64DFR0, PMUVER, 8, 4)
52
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/helper.c
55
+++ b/target/arm/helper.c
56
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
57
.access = PL1_R, .type = ARM_CP_CONST,
58
.accessfn = access_aa64_tid3,
59
.resetvalue = cpu->isar.id_aa64mmfr2 },
60
- { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
61
+ { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
62
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
63
.access = PL1_R, .type = ARM_CP_CONST,
64
.accessfn = access_aa64_tid3,
65
- .resetvalue = 0 },
66
+ .resetvalue = cpu->isar.id_aa64mmfr3 },
67
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
68
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
69
.access = PL1_R, .type = ARM_CP_CONST,
70
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
71
.exported_bits = R_ID_AA64MMFR1_AFP_MASK },
72
{ .name = "ID_AA64MMFR2_EL1",
73
.exported_bits = R_ID_AA64MMFR2_AT_MASK },
74
+ { .name = "ID_AA64MMFR3_EL1",
75
+ .exported_bits = 0 },
76
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
77
.is_glob = true },
78
{ .name = "ID_AA64DFR0_EL1",
79
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/arm/hvf/hvf.c
82
+++ b/target/arm/hvf/hvf.c
83
@@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = {
84
#endif
85
{ HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
86
{ HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
87
+ /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
88
89
{ HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
90
{ HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
91
@@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
92
{ HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
93
{ HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
94
{ HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
95
+ /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
96
};
97
hv_vcpu_t fd;
98
hv_return_t r = HV_SUCCESS;
99
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/kvm.c
102
+++ b/target/arm/kvm.c
103
@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
104
ARM64_SYS_REG(3, 0, 0, 7, 1));
105
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
106
ARM64_SYS_REG(3, 0, 0, 7, 2));
107
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
108
+ ARM64_SYS_REG(3, 0, 0, 7, 3));
109
110
/*
111
* Note that if AArch32 support is not present in the host,
29
--
112
--
30
2.16.2
113
2.34.1
31
114
32
115
diff view generated by jsdifflib
1
Add some assertions that if we're about to boot an AArch64 kernel,
1
FEAT_Spec_FPACC is a feature describing speculative behaviour in the
2
the board code has not mistakenly set either secure_boot or
2
event of a PAC authontication failure when FEAT_FPACCOMBINE is
3
secure_board_setup. It doesn't make sense to set secure_boot,
3
implemented. FEAT_Spec_FPACC means that the speculative use of
4
because all AArch64 kernels must be booted in non-secure mode.
4
pointers processed by a PAC Authentication is not materially
5
different in terms of the impact on cached microarchitectural state
6
(caches, TLBs, etc) between passing and failing of the PAC
7
Authentication.
5
8
6
It might in theory make sense to set secure_board_setup, but
9
QEMU doesn't do speculative execution, so we can advertise
7
we don't currently support that, because only the AArch32
10
this feature.
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
9
Since we don't have a current need for this functionality, just
10
assert that we don't try to use it. If it's needed we'll add
11
it later.
12
11
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
16
---
16
---
17
hw/arm/boot.c | 7 +++++++
17
docs/system/arm/emulation.rst | 1 +
18
1 file changed, 7 insertions(+)
18
target/arm/tcg/cpu64.c | 4 ++++
19
2 files changed, 5 insertions(+)
19
20
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
--- a/docs/system/arm/emulation.rst
23
+++ b/hw/arm/boot.c
24
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
25
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
} else {
26
- FEAT_FP16 (Half-precision floating-point data processing)
26
env->pstate = PSTATE_MODE_EL1h;
27
- FEAT_FPAC (Faulting on AUT* instructions)
27
}
28
- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
28
+ /* AArch64 kernels never boot in secure mode */
29
+- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
29
+ assert(!info->secure_boot);
30
- FEAT_FRINTTS (Floating-point to integer instructions)
30
+ /* This hook is only supported for AArch32 currently:
31
- FEAT_FlagM (Flag manipulation instructions v2)
31
+ * bootloader_aarch64[] will not call the hook, and
32
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
32
+ * the code above has already dropped us into EL2 or EL1.
33
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
33
+ */
34
index XXXXXXX..XXXXXXX 100644
34
+ assert(!info->secure_board_setup);
35
--- a/target/arm/tcg/cpu64.c
35
}
36
+++ b/target/arm/tcg/cpu64.c
36
37
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
37
/* Set to non-secure if not a secure boot */
38
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
39
cpu->isar.id_aa64mmfr2 = t;
40
41
+ t = cpu->isar.id_aa64mmfr3;
42
+ t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
43
+ cpu->isar.id_aa64mmfr3 = t;
44
+
45
t = cpu->isar.id_aa64zfr0;
46
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
47
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
38
--
48
--
39
2.16.2
49
2.34.1
40
50
41
51
diff view generated by jsdifflib
New patch
1
The Linux kernel 5.10.16 binary for sunxi has been removed from
2
apt.armbian.com. This means that the avocado tests for these machines
3
will be skipped (status CANCEL) if the old binary isn't present in
4
the avocado cache.
1
5
6
Update to 6.6.16, in the same way we did in commit e384db41d8661
7
when we moved to 5.10.16 in 2021.
8
9
Cc: qemu-stable@nongnu.org
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
13
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
16
---
17
tests/avocado/boot_linux_console.py | 70 ++++++++++++++---------------
18
tests/avocado/replay_kernel.py | 8 ++--
19
2 files changed, 39 insertions(+), 39 deletions(-)
20
21
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tests/avocado/boot_linux_console.py
24
+++ b/tests/avocado/boot_linux_console.py
25
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
26
:avocado: tags=accel:tcg
27
"""
28
deb_url = ('https://apt.armbian.com/pool/main/l/'
29
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
30
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
31
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
32
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
33
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
34
kernel_path = self.extract_from_deb(deb_path,
35
- '/boot/vmlinuz-5.10.16-sunxi')
36
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
37
+ '/boot/vmlinuz-6.6.16-current-sunxi')
38
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
39
dtb_path = self.extract_from_deb(deb_path, dtb_path)
40
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
41
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
42
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
43
:avocado: tags=accel:tcg
44
"""
45
deb_url = ('https://apt.armbian.com/pool/main/l/'
46
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
47
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
48
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
49
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
50
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
51
kernel_path = self.extract_from_deb(deb_path,
52
- '/boot/vmlinuz-5.10.16-sunxi')
53
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
54
+ '/boot/vmlinuz-6.6.16-current-sunxi')
55
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
56
dtb_path = self.extract_from_deb(deb_path, dtb_path)
57
rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
58
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
59
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self):
60
:avocado: tags=machine:bpim2u
61
:avocado: tags=accel:tcg
62
"""
63
- deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
64
- 'linux-image-current-sunxi_21.02.2_armhf.deb')
65
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
66
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
67
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
68
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
69
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
70
kernel_path = self.extract_from_deb(deb_path,
71
- '/boot/vmlinuz-5.10.16-sunxi')
72
- dtb_path = ('/usr/lib/linux-image-current-sunxi/'
73
+ '/boot/vmlinuz-6.6.16-current-sunxi')
74
+ dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
75
'sun8i-r40-bananapi-m2-ultra.dtb')
76
dtb_path = self.extract_from_deb(deb_path, dtb_path)
77
78
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self):
79
:avocado: tags=accel:tcg
80
:avocado: tags=machine:bpim2u
81
"""
82
- deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
83
- 'linux-image-current-sunxi_21.02.2_armhf.deb')
84
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
85
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
86
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
87
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
88
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
89
kernel_path = self.extract_from_deb(deb_path,
90
- '/boot/vmlinuz-5.10.16-sunxi')
91
- dtb_path = ('/usr/lib/linux-image-current-sunxi/'
92
+ '/boot/vmlinuz-6.6.16-current-sunxi')
93
+ dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
94
'sun8i-r40-bananapi-m2-ultra.dtb')
95
dtb_path = self.extract_from_deb(deb_path, dtb_path)
96
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
97
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self):
98
"""
99
self.require_netdev('user')
100
101
- deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
102
- 'linux-image-current-sunxi_21.02.2_armhf.deb')
103
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
104
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
105
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
106
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
107
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
108
kernel_path = self.extract_from_deb(deb_path,
109
- '/boot/vmlinuz-5.10.16-sunxi')
110
- dtb_path = ('/usr/lib/linux-image-current-sunxi/'
111
+ '/boot/vmlinuz-6.6.16-current-sunxi')
112
+ dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
113
'sun8i-r40-bananapi-m2-ultra.dtb')
114
dtb_path = self.extract_from_deb(deb_path, dtb_path)
115
rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
116
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
117
:avocado: tags=accel:tcg
118
"""
119
deb_url = ('https://apt.armbian.com/pool/main/l/'
120
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
121
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
122
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
123
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
124
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
125
kernel_path = self.extract_from_deb(deb_path,
126
- '/boot/vmlinuz-5.10.16-sunxi')
127
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
128
+ '/boot/vmlinuz-6.6.16-current-sunxi')
129
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
130
dtb_path = self.extract_from_deb(deb_path, dtb_path)
131
132
self.vm.set_console()
133
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
134
:avocado: tags=machine:orangepi-pc
135
"""
136
deb_url = ('https://apt.armbian.com/pool/main/l/'
137
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
138
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
139
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
140
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
141
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
142
kernel_path = self.extract_from_deb(deb_path,
143
- '/boot/vmlinuz-5.10.16-sunxi')
144
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
145
+ '/boot/vmlinuz-6.6.16-current-sunxi')
146
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
147
dtb_path = self.extract_from_deb(deb_path, dtb_path)
148
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
149
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
150
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
151
self.require_netdev('user')
152
153
deb_url = ('https://apt.armbian.com/pool/main/l/'
154
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
155
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
156
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
157
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
158
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
159
kernel_path = self.extract_from_deb(deb_path,
160
- '/boot/vmlinuz-5.10.16-sunxi')
161
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
162
+ '/boot/vmlinuz-6.6.16-current-sunxi')
163
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
164
dtb_path = self.extract_from_deb(deb_path, dtb_path)
165
rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
166
'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz')
167
diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
168
index XXXXXXX..XXXXXXX 100644
169
--- a/tests/avocado/replay_kernel.py
170
+++ b/tests/avocado/replay_kernel.py
171
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
172
:avocado: tags=machine:cubieboard
173
"""
174
deb_url = ('https://apt.armbian.com/pool/main/l/'
175
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
176
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
177
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
178
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
179
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
180
kernel_path = self.extract_from_deb(deb_path,
181
- '/boot/vmlinuz-5.10.16-sunxi')
182
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
183
+ '/boot/vmlinuz-6.6.16-current-sunxi')
184
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
185
dtb_path = self.extract_from_deb(deb_path, dtb_path)
186
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
187
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
188
--
189
2.34.1
diff view generated by jsdifflib
1
Our BCM2836 type is really a generic one that can be any of
1
The generic timer frequency is settable by board code via a QOM
2
the bcm283x family. Rename it accordingly. We change only
2
property "cntfrq", but otherwise defaults to 62.5MHz. The way this
3
the names which are visible via the header file to the
3
is done includes some complication resulting from how this was
4
rest of the QEMU code, leaving private function names
4
originally a fixed value with no QOM property. Clean it up:
5
in bcm2836.c as they are.
6
5
7
This is a preliminary to making bcm283x be an abstract
6
* always set cpu->gt_cntfrq_hz to some sensible value, whether
8
parent class to specific types for the bcm2836 and bcm2837.
7
the CPU has the generic timer or not, and whether it's system
8
or user-only emulation
9
* this means we can always use gt_cntfrq_hz, and never need
10
the old GTIMER_SCALE define
11
* set the default value in exactly one place, in the realize fn
12
13
The aim here is to pave the way for handling the ARMv8.6 requirement
14
that the generic timer frequency is always 1GHz. We're going to do
15
that by having old CPU types keep their legacy-in-QEMU behaviour and
16
having the default for any new CPU types be a 1GHz rather han 62.5MHz
17
cntfrq, so we want the point where the default is decided to be in
18
one place, and in code, not in a DEFINE_PROP_UINT64() initializer.
19
20
This commit should have no behavioural changes.
9
21
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
25
Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
14
---
26
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
27
target/arm/internals.h | 7 ++++---
16
hw/arm/bcm2836.c | 17 +++++++++--------
28
target/arm/cpu.c | 31 +++++++++++++++++--------------
17
hw/arm/raspi.c | 16 ++++++++--------
29
target/arm/helper.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
30
3 files changed, 29 insertions(+), 25 deletions(-)
19
31
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
32
diff --git a/target/arm/internals.h b/target/arm/internals.h
21
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
34
--- a/target/arm/internals.h
23
+++ b/include/hw/arm/bcm2836.h
35
+++ b/target/arm/internals.h
24
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
25
#include "hw/arm/bcm2835_peripherals.h"
37
|| excp == EXCP_SEMIHOST;
26
#include "hw/intc/bcm2836_control.h"
38
}
27
39
28
-#define TYPE_BCM2836 "bcm2836"
40
-/* Scale factor for generic timers, ie number of ns per tick.
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
41
- * This gives a 62.5MHz timer.
30
+#define TYPE_BCM283X "bcm283x"
42
+/*
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
43
+ * Default frequency for the generic timer, in Hz.
32
44
+ * This is 62.5MHz, which gives a 16 ns tick period.
33
-#define BCM2836_NCPUS 4
45
*/
34
+#define BCM283X_NCPUS 4
46
-#define GTIMER_SCALE 16
35
47
+#define GTIMER_DEFAULT_HZ 62500000
36
-typedef struct BCM2836State {
48
37
+typedef struct BCM283XState {
49
/* Bit definitions for the v7M CONTROL register */
38
/*< private >*/
50
FIELD(V7M_CONTROL, NPRIV, 0, 1)
39
DeviceState parent_obj;
51
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
40
/*< public >*/
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
42
char *cpu_type;
43
uint32_t enabled_cpus;
44
45
- ARMCPU cpus[BCM2836_NCPUS];
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
BCM2836ControlState control;
48
BCM2835PeripheralState peripherals;
49
-} BCM2836State;
50
+} BCM283XState;
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
53
--- a/target/arm/cpu.c
56
+++ b/hw/arm/bcm2836.c
54
+++ b/target/arm/cpu.c
57
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
58
56
}
59
static void bcm2836_init(Object *obj)
60
{
61
- BCM2836State *s = BCM2836(obj);
62
+ BCM283XState *s = BCM283X(obj);
63
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
67
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
69
{
70
- BCM2836State *s = BCM2836(dev);
71
+ BCM283XState *s = BCM283X(dev);
72
Object *obj;
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
57
}
95
58
96
static Property bcm2836_props[] = {
59
+/*
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
60
+ * 0 means "unset, use the default value". That default might vary depending
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
61
+ * on the CPU type, and is set in the realize fn.
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
62
+ */
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
63
static Property arm_cpu_gt_cntfrq_property =
101
+ BCM283X_NCPUS),
64
- DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
102
DEFINE_PROP_END_OF_LIST()
65
- NANOSECONDS_PER_SECOND / GTIMER_SCALE);
66
+ DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
67
68
static Property arm_cpu_reset_cbar_property =
69
DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
70
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
71
return;
72
}
73
74
+ if (!cpu->gt_cntfrq_hz) {
75
+ /*
76
+ * 0 means "the board didn't set a value, use the default".
77
+ * The default value of the generic timer frequency (as seen in
78
+ * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
79
+ * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
80
+ * board doesn't set it.
81
+ */
82
+ cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
83
+ }
84
+
85
#ifndef CONFIG_USER_ONLY
86
/* The NVIC and M-profile CPU are two halves of a single piece of
87
* hardware; trying to use one without the other is a command line
88
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
89
}
90
91
{
92
- uint64_t scale;
93
-
94
- if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
95
- if (!cpu->gt_cntfrq_hz) {
96
- error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
97
- cpu->gt_cntfrq_hz);
98
- return;
99
- }
100
- scale = gt_cntfrq_period_ns(cpu);
101
- } else {
102
- scale = GTIMER_SCALE;
103
- }
104
+ uint64_t scale = gt_cntfrq_period_ns(cpu);
105
106
cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
107
arm_gt_ptimer_cb, cpu);
108
diff --git a/target/arm/helper.c b/target/arm/helper.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/arm/helper.c
111
+++ b/target/arm/helper.c
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
113
.resetvalue = 0 },
103
};
114
};
104
115
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
116
+static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
117
+{
118
+ ARMCPU *cpu = env_archcpu(env);
119
+
120
+ cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
121
+}
122
+
123
#ifndef CONFIG_USER_ONLY
124
125
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
126
@@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque)
127
gt_recalc_timer(cpu, GTIMER_HYPVIRT);
106
}
128
}
107
129
108
static const TypeInfo bcm2836_type_info = {
130
-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
109
- .name = TYPE_BCM2836,
131
-{
110
+ .name = TYPE_BCM283X,
132
- ARMCPU *cpu = env_archcpu(env);
111
.parent = TYPE_DEVICE,
133
-
112
- .instance_size = sizeof(BCM2836State),
134
- cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
113
+ .instance_size = sizeof(BCM283XState),
135
-}
114
.instance_init = bcm2836_init,
136
-
115
.class_init = bcm2836_class_init,
137
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
116
};
138
/*
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
139
* Note that CNTFRQ is purely reads-as-written for the benefit
118
index XXXXXXX..XXXXXXX 100644
140
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
119
--- a/hw/arm/raspi.c
141
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
120
+++ b/hw/arm/raspi.c
142
.type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
121
@@ -XXX,XX +XXX,XX @@
143
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
144
- .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
123
145
+ .resetfn = arm_gt_cntfrq_reset,
124
typedef struct RasPiState {
146
},
125
- BCM2836State soc;
147
{ .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
126
+ BCM283XState soc;
148
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
127
MemoryRegion ram;
128
} RasPiState;
129
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
165
--
149
--
166
2.16.2
150
2.34.1
167
151
168
152
diff view generated by jsdifflib
1
For the rpi1 and 2 we want to boot the Linux kernel via some
1
Currently QEMU CPUs always run with a generic timer counter frequency
2
custom setup code that makes sure that the SMC instruction
2
of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of
3
acts as a no-op, because it's used for cache maintenance.
3
the TF-A firmware that sbsa-ref runs, the frequency of the generic
4
The rpi3 boots AArch64 kernels, which don't need SMC for
4
timer is hardcoded into the firmware, and so if the CPU actually has
5
cache maintenance and always expect to be booted non-secure.
5
a different frequency then timers in the guest will be set
6
Don't fill in the aarch32-specific parts of the binfo struct.
6
incorrectly.
7
8
The default frequency used by the 'max' CPU is about to change, so
9
make the sbsa-ref board force the CPU frequency to the value which
10
the firmware expects.
11
12
Newer versions of TF-A will read the frequency from the CPU's
13
CNTFRQ_EL0 register:
14
https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
15
so in the longer term we could make this board use the 1GHz
16
frequency. We will need to make sure we update the binaries used
17
by our avocado test
18
Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
19
before we can do that.
7
20
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
24
Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
12
---
25
---
13
hw/arm/raspi.c | 17 +++++++++++++----
26
hw/arm/sbsa-ref.c | 15 +++++++++++++++
14
1 file changed, 13 insertions(+), 4 deletions(-)
27
1 file changed, 15 insertions(+)
15
28
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
29
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
17
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
31
--- a/hw/arm/sbsa-ref.c
19
+++ b/hw/arm/raspi.c
32
+++ b/hw/arm/sbsa-ref.c
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
33
@@ -XXX,XX +XXX,XX @@
21
binfo.board_id = raspi_boardid[version];
34
#define NUM_SMMU_IRQS 4
22
binfo.ram_size = ram_size;
35
#define NUM_SATA_PORTS 6
23
binfo.nb_cpus = smp_cpus;
36
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
37
+/*
25
- binfo.write_board_setup = write_board_setup;
38
+ * Generic timer frequency in Hz (which drives both the CPU generic timers
26
- binfo.secure_board_setup = true;
39
+ * and the SBSA watchdog-timer). Older versions of the TF-A firmware
27
- binfo.secure_boot = true;
40
+ * typically used with sbsa-ref (including the binaries in our Avocado test
41
+ * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
42
+ * assume it is this value.
43
+ *
44
+ * TODO: this value is not architecturally correct for an Armv8.6 or
45
+ * better CPU, so we should move to 1GHz once the TF-A fix above has
46
+ * made it into a release and into our Avocado test.
47
+ */
48
+#define SBSA_GTIMER_HZ 62500000
28
+
49
+
29
+ if (version <= 2) {
50
enum {
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
51
SBSA_FLASH,
31
+ * mode before booting a kernel (to set up the SMC vectors so
52
SBSA_MEM,
32
+ * that we get a no-op SMC; this is used by Linux to call the
53
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
33
+ * firmware for some cache maintenance operations.
54
&error_abort);
34
+ * The rpi3 doesn't need this.
55
}
35
+ */
56
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
57
+ object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
37
+ binfo.write_board_setup = write_board_setup;
58
+
38
+ binfo.secure_board_setup = true;
59
object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
39
+ binfo.secure_boot = true;
60
&error_abort);
40
+ }
61
41
42
/* Pi2 and Pi3 requires SMP setup */
43
if (version >= 2) {
44
--
62
--
45
2.16.2
63
2.34.1
46
64
47
65
diff view generated by jsdifflib
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
Currently the sbsa_gdwt watchdog device hardcodes its frequency at
2
just hard-code the CPU type they use rather than having it passed
2
62.5MHz. In real hardware, this watchdog is supposed to be driven
3
through as an object property. This then lets us put the initialization
3
from the system counter, which also drives the CPU generic timers.
4
of the CPU object in init rather than realize.
4
Newer CPU types (in particular from Armv8.6) should have a CPU
5
generic timer frequency of 1GHz, so we can't leave the watchdog
6
on the old QEMU default of 62.5GHz.
5
7
6
Note that this change means that it's no longer possible on
8
Make the frequency a QOM property so it can be set by the board,
7
the command line to use -cpu to ask for a different kind of
9
and have our only board that uses this device set that frequency
8
CPU than the SoC supports. This was never a supported thing to
10
to the same value it sets the CPU frequency.
9
do anyway; we were just not sanity-checking the command line.
10
11
This does require us to only build the bcm2837 object on
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
13
due to the missing cortex-a53 device and "make check" will fail.
14
11
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
15
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
16
include/hw/watchdog/sbsa_gwdt.h | 3 +--
21
hw/arm/raspi.c | 2 --
17
hw/arm/sbsa-ref.c | 1 +
22
2 files changed, 15 insertions(+), 11 deletions(-)
18
hw/watchdog/sbsa_gwdt.c | 15 ++++++++++++++-
19
3 files changed, 16 insertions(+), 3 deletions(-)
23
20
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
21
diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
23
--- a/include/hw/watchdog/sbsa_gwdt.h
27
+++ b/hw/arm/bcm2836.c
24
+++ b/include/hw/watchdog/sbsa_gwdt.h
28
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@
29
26
#define SBSA_GWDT_RMMIO_SIZE 0x1000
30
struct BCM283XInfo {
27
#define SBSA_GWDT_CMMIO_SIZE 0x1000
31
const char *name;
28
32
+ const char *cpu_type;
29
-#define SBSA_TIMER_FREQ 62500000 /* Hz */
33
int clusterid;
30
-
34
};
31
typedef struct SBSA_GWDTState {
35
32
/* <private> */
36
static const BCM283XInfo bcm283x_socs[] = {
33
SysBusDevice parent_obj;
37
{
34
@@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState {
38
.name = TYPE_BCM2836,
35
qemu_irq irq;
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
36
40
.clusterid = 0xf,
37
QEMUTimer *timer;
41
},
38
+ uint64_t freq;
42
+#ifdef TARGET_AARCH64
39
43
{
40
uint32_t id;
44
.name = TYPE_BCM2837,
41
uint32_t wcs;
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
42
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
46
.clusterid = 0x0,
43
index XXXXXXX..XXXXXXX 100644
47
},
44
--- a/hw/arm/sbsa-ref.c
48
+#endif
45
+++ b/hw/arm/sbsa-ref.c
49
};
46
@@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms)
50
47
SysBusDevice *s = SYS_BUS_DEVICE(dev);
51
static void bcm2836_init(Object *obj)
48
int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
49
50
+ qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
51
sysbus_realize_and_unref(s, &error_fatal);
52
sysbus_mmio_map(s, 0, rbase);
53
sysbus_mmio_map(s, 1, cbase);
54
diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/watchdog/sbsa_gwdt.c
57
+++ b/hw/watchdog/sbsa_gwdt.c
58
@@ -XXX,XX +XXX,XX @@
59
#include "qemu/osdep.h"
60
#include "sysemu/reset.h"
61
#include "sysemu/watchdog.h"
62
+#include "hw/qdev-properties.h"
63
#include "hw/watchdog/sbsa_gwdt.h"
64
#include "qemu/timer.h"
65
#include "migration/vmstate.h"
66
@@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
67
timeout = s->woru;
68
timeout <<= 32;
69
timeout |= s->worl;
70
- timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
71
+ timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq);
72
timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
73
74
if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
75
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
76
dev);
77
}
78
79
+static Property wdt_sbsa_gwdt_props[] = {
80
+ /*
81
+ * Timer frequency in Hz. This must match the frequency used by
82
+ * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy
83
+ * CPU timer frequency default.
84
+ */
85
+ DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq,
86
+ 62500000),
87
+ DEFINE_PROP_END_OF_LIST(),
88
+};
89
+
90
static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
52
{
91
{
53
BCM283XState *s = BCM283X(obj);
92
DeviceClass *dc = DEVICE_CLASS(klass);
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
93
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
55
+ const BCM283XInfo *info = bc->info;
94
set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
56
+ int n;
95
dc->vmsd = &vmstate_sbsa_gwdt;
57
+
96
dc->desc = "SBSA-compliant generic watchdog device";
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
97
+ device_class_set_props(dc, wdt_sbsa_gwdt_props);
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
60
+ info->cpu_type);
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
62
+ &error_abort);
63
+ }
64
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
68
69
/* common peripherals from bcm2835 */
70
71
- obj = OBJECT(dev);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
74
- s->cpu_type);
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
98
}
84
99
85
static Property bcm2836_props[] = {
100
static const TypeInfo wdt_sbsa_gwdt_info = {
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
101
--
104
2.16.2
102
2.34.1
105
103
106
104
diff view generated by jsdifflib
New patch
1
1
In previous versions of the Arm architecture, the frequency of the
2
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
3
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
4
In Armv8.6, the architecture standardized this frequency to 1GHz.
5
6
Because there is no ID register feature field that indicates whether
7
a CPU is v8.6 or that it ought to have this counter frequency, we
8
implement this by changing our default CNTFRQ value for all CPUs,
9
with exceptions for backwards compatibility:
10
11
* CPU types which we already implement will retain the old
12
default value. None of these are v8.6 CPUs, so this is
13
architecturally OK.
14
* CPUs used in versioned machine types with a version of 9.0
15
or earlier will retain the old default value.
16
17
The upshot is that the only CPU type that changes is 'max'; but any
18
new type we add in future (whether v8.6 or not) will also get the new
19
1GHz default.
20
21
It remains the case that the machine model can override the default
22
value via the 'cntfrq' QOM property (regardless of the CPU type).
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
27
Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
28
---
29
target/arm/cpu.h | 11 +++++++++++
30
target/arm/internals.h | 12 ++++++++++--
31
hw/core/machine.c | 4 +++-
32
target/arm/cpu.c | 23 +++++++++++++++++------
33
target/arm/cpu64.c | 2 ++
34
target/arm/tcg/cpu32.c | 4 ++++
35
target/arm/tcg/cpu64.c | 18 ++++++++++++++++++
36
7 files changed, 65 insertions(+), 9 deletions(-)
37
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu.h
41
+++ b/target/arm/cpu.h
42
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
43
*/
44
bool host_cpu_probe_failed;
45
46
+ /* QOM property to indicate we should use the back-compat CNTFRQ default */
47
+ bool backcompat_cntfrq;
48
+
49
/* Specify the number of cores in this CPU cluster. Used for the L2CTLR
50
* register.
51
*/
52
@@ -XXX,XX +XXX,XX @@ enum arm_features {
53
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
54
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
55
ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
56
+ /*
57
+ * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
58
+ * if the board doesn't set a value, instead of 1GHz. It is for backwards
59
+ * compatibility and used only with CPU definitions that were already
60
+ * in QEMU before we changed the default. It should not be set on any
61
+ * CPU types added in future.
62
+ */
63
+ ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
64
};
65
66
static inline int arm_feature(CPUARMState *env, int feature)
67
diff --git a/target/arm/internals.h b/target/arm/internals.h
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/internals.h
70
+++ b/target/arm/internals.h
71
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
72
73
/*
74
* Default frequency for the generic timer, in Hz.
75
- * This is 62.5MHz, which gives a 16 ns tick period.
76
+ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
77
+ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
78
+ * which gives a 16ns tick period.
79
+ *
80
+ * We will use the back-compat value:
81
+ * - for QEMU CPU types added before we standardized on 1GHz
82
+ * - for versioned machine types with a version of 9.0 or earlier
83
+ * In any case, the machine model may override via the cntfrq property.
84
*/
85
-#define GTIMER_DEFAULT_HZ 62500000
86
+#define GTIMER_DEFAULT_HZ 1000000000
87
+#define GTIMER_BACKCOMPAT_HZ 62500000
88
89
/* Bit definitions for the v7M CONTROL register */
90
FIELD(V7M_CONTROL, NPRIV, 0, 1)
91
diff --git a/hw/core/machine.c b/hw/core/machine.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/core/machine.c
94
+++ b/hw/core/machine.c
95
@@ -XXX,XX +XXX,XX @@
96
#include "hw/virtio/virtio-iommu.h"
97
#include "audio/audio.h"
98
99
-GlobalProperty hw_compat_9_0[] = {};
100
+GlobalProperty hw_compat_9_0[] = {
101
+ {"arm-cpu", "backcompat-cntfrq", "true" },
102
+};
103
const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
104
105
GlobalProperty hw_compat_8_2[] = {
106
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/cpu.c
109
+++ b/target/arm/cpu.c
110
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
111
112
if (!cpu->gt_cntfrq_hz) {
113
/*
114
- * 0 means "the board didn't set a value, use the default".
115
- * The default value of the generic timer frequency (as seen in
116
- * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
117
- * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
118
- * board doesn't set it.
119
+ * 0 means "the board didn't set a value, use the default". (We also
120
+ * get here for the CONFIG_USER_ONLY case.)
121
+ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
122
+ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
123
+ * which gives a 16ns tick period.
124
+ *
125
+ * We will use the back-compat value:
126
+ * - for QEMU CPU types added before we standardized on 1GHz
127
+ * - for versioned machine types with a version of 9.0 or earlier
128
*/
129
- cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
130
+ if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
131
+ cpu->backcompat_cntfrq) {
132
+ cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
133
+ } else {
134
+ cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
135
+ }
136
}
137
138
#ifndef CONFIG_USER_ONLY
139
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {
140
mp_affinity, ARM64_AFFINITY_INVALID),
141
DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
142
DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
143
+ /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
144
+ DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
145
DEFINE_PROP_END_OF_LIST()
146
};
147
148
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/cpu64.c
151
+++ b/target/arm/cpu64.c
152
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
153
set_feature(&cpu->env, ARM_FEATURE_V8);
154
set_feature(&cpu->env, ARM_FEATURE_NEON);
155
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
156
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
157
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
158
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
159
set_feature(&cpu->env, ARM_FEATURE_EL2);
160
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
161
set_feature(&cpu->env, ARM_FEATURE_V8);
162
set_feature(&cpu->env, ARM_FEATURE_NEON);
163
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
164
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
165
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
166
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
167
set_feature(&cpu->env, ARM_FEATURE_EL2);
168
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/tcg/cpu32.c
171
+++ b/target/arm/tcg/cpu32.c
172
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
173
set_feature(&cpu->env, ARM_FEATURE_NEON);
174
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
175
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
176
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
177
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
178
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
179
set_feature(&cpu->env, ARM_FEATURE_EL2);
180
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
181
set_feature(&cpu->env, ARM_FEATURE_NEON);
182
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
183
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
184
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
185
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
186
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
187
set_feature(&cpu->env, ARM_FEATURE_EL2);
188
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
189
set_feature(&cpu->env, ARM_FEATURE_PMSA);
190
set_feature(&cpu->env, ARM_FEATURE_NEON);
191
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
192
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
193
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
194
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
195
cpu->midr = 0x411fd133; /* r1p3 */
196
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
197
set_feature(&cpu->env, ARM_FEATURE_V8);
198
set_feature(&cpu->env, ARM_FEATURE_NEON);
199
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
200
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
201
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
202
set_feature(&cpu->env, ARM_FEATURE_EL2);
203
set_feature(&cpu->env, ARM_FEATURE_EL3);
204
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/tcg/cpu64.c
207
+++ b/target/arm/tcg/cpu64.c
208
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
209
set_feature(&cpu->env, ARM_FEATURE_V8);
210
set_feature(&cpu->env, ARM_FEATURE_NEON);
211
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
212
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
213
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
214
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
215
set_feature(&cpu->env, ARM_FEATURE_EL2);
216
@@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj)
217
set_feature(&cpu->env, ARM_FEATURE_V8);
218
set_feature(&cpu->env, ARM_FEATURE_NEON);
219
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
220
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
221
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
222
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
223
set_feature(&cpu->env, ARM_FEATURE_EL2);
224
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
225
set_feature(&cpu->env, ARM_FEATURE_V8);
226
set_feature(&cpu->env, ARM_FEATURE_NEON);
227
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
228
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
229
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
230
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
231
set_feature(&cpu->env, ARM_FEATURE_EL2);
232
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
233
set_feature(&cpu->env, ARM_FEATURE_V8);
234
set_feature(&cpu->env, ARM_FEATURE_NEON);
235
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
236
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
237
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
238
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
239
set_feature(&cpu->env, ARM_FEATURE_EL2);
240
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
241
set_feature(&cpu->env, ARM_FEATURE_V8);
242
set_feature(&cpu->env, ARM_FEATURE_NEON);
243
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
244
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
245
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
246
set_feature(&cpu->env, ARM_FEATURE_EL2);
247
set_feature(&cpu->env, ARM_FEATURE_EL3);
248
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
249
set_feature(&cpu->env, ARM_FEATURE_V8);
250
set_feature(&cpu->env, ARM_FEATURE_NEON);
251
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
252
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
253
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
254
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
255
set_feature(&cpu->env, ARM_FEATURE_EL2);
256
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
257
set_feature(&cpu->env, ARM_FEATURE_V8);
258
set_feature(&cpu->env, ARM_FEATURE_NEON);
259
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
260
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
261
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
262
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
263
set_feature(&cpu->env, ARM_FEATURE_EL2);
264
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
265
set_feature(&cpu->env, ARM_FEATURE_V8);
266
set_feature(&cpu->env, ARM_FEATURE_NEON);
267
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
268
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
269
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
270
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
271
set_feature(&cpu->env, ARM_FEATURE_EL2);
272
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj)
273
set_feature(&cpu->env, ARM_FEATURE_V8);
274
set_feature(&cpu->env, ARM_FEATURE_NEON);
275
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
277
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
278
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
279
set_feature(&cpu->env, ARM_FEATURE_EL2);
280
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
281
uint64_t t;
282
uint32_t u;
283
284
+ /*
285
+ * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
286
+ * to because we started with aarch64_a57_initfn(). A 'max' CPU might
287
+ * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
288
+ * because it is our "may change" CPU type we are OK with it not being
289
+ * backwards-compatible with how it worked in old QEMU.
290
+ */
291
+ unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
292
+
293
/*
294
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
295
* one and try to apply errata workarounds or use impdef features we
296
--
297
2.34.1
298
299
diff view generated by jsdifflib
New patch
1
From: Alexandra Diupina <adiupina@astralinux.ru>
1
2
3
The DMA descriptor structures for this device have
4
a set of "address extension" fields which extend the 32
5
bit source addresses with an extra 16 bits to give a
6
48 bit address:
7
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
8
9
However, we misimplemented this address extension in several ways:
10
* we only extracted 12 bits of the extension fields, not 16
11
* we didn't shift the extension field up far enough
12
* we accidentally did the shift as 32-bit arithmetic, which
13
meant that we would have an overflow instead of setting
14
bits [47:32] of the resulting 64-bit address
15
16
Add a type cast and use extract64() instead of extract32()
17
to avoid integer overflow on addition. Fix bit fields
18
extraction according to documentation.
19
20
Found by Linux Verification Center (linuxtesting.org) with SVACE.
21
22
Cc: qemu-stable@nongnu.org
23
Fixes: d3c6369a96 ("introduce xlnx-dpdma")
24
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
25
Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
26
[PMM: adjusted commit message]
27
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
30
hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
31
1 file changed, 10 insertions(+), 10 deletions(-)
32
33
diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/dma/xlnx_dpdma.c
36
+++ b/hw/dma/xlnx_dpdma.c
37
@@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
38
39
switch (frag) {
40
case 0:
41
- addr = desc->source_address
42
- + (extract32(desc->address_extension, 16, 12) << 20);
43
+ addr = (uint64_t)desc->source_address
44
+ + (extract64(desc->address_extension, 16, 16) << 32);
45
break;
46
case 1:
47
- addr = desc->source_address2
48
- + (extract32(desc->address_extension_23, 0, 12) << 8);
49
+ addr = (uint64_t)desc->source_address2
50
+ + (extract64(desc->address_extension_23, 0, 16) << 32);
51
break;
52
case 2:
53
- addr = desc->source_address3
54
- + (extract32(desc->address_extension_23, 16, 12) << 20);
55
+ addr = (uint64_t)desc->source_address3
56
+ + (extract64(desc->address_extension_23, 16, 16) << 32);
57
break;
58
case 3:
59
- addr = desc->source_address4
60
- + (extract32(desc->address_extension_45, 0, 12) << 8);
61
+ addr = (uint64_t)desc->source_address4
62
+ + (extract64(desc->address_extension_45, 0, 16) << 32);
63
break;
64
case 4:
65
- addr = desc->source_address5
66
- + (extract32(desc->address_extension_45, 16, 12) << 20);
67
+ addr = (uint64_t)desc->source_address5
68
+ + (extract64(desc->address_extension_45, 16, 16) << 32);
69
break;
70
default:
71
addr = 0;
72
--
73
2.34.1
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
"make check-qtest-aarch64" recently started failing on FreeBSD builds,
4
it is needed to support guests other than Linux.
4
and valgrind on Linux also detected that there is something fishy with
5
the new stm32l4x5-usart: The code forgot to set the correct class_size
6
here, so the various class_init functions in this file wrote beyond
7
the allocated buffer when setting the subc->type field.
5
8
6
Based on the patch by Bill Paul as found here:
9
Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
7
https://bugs.launchpad.net/qemu/+bug/1753314
10
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Cc: qemu-devel@nongnu.org
12
Message-id: 20240429075908.36302-1-thuth@redhat.com
10
Cc: qemu-arm@nongnu.org
11
Cc: Bill Paul <wpaul@windriver.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
14
---
19
include/hw/char/imx_serial.h | 3 +++
15
hw/char/stm32l4x5_usart.c | 1 +
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
16
1 file changed, 1 insertion(+)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
17
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
18
diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
20
--- a/hw/char/stm32l4x5_usart.c
26
+++ b/include/hw/char/imx_serial.h
21
+++ b/hw/char/stm32l4x5_usart.c
27
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = {
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
23
.parent = TYPE_SYS_BUS_DEVICE,
29
#define UCR2_SRST (1<<0) /* Reset complete */
24
.instance_size = sizeof(Stm32l4x5UsartBaseState),
30
25
.instance_init = stm32l4x5_usart_base_init,
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
26
+ .class_size = sizeof(Stm32l4x5UsartBaseClass),
32
+
27
.class_init = stm32l4x5_usart_base_class_init,
33
#define UTS1_TXEMPTY (1<<6)
28
.abstract = true,
34
#define UTS1_RXEMPTY (1<<5)
29
}, {
35
#define UTS1_TXFULL (1<<4)
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
37
uint32_t ubmr;
38
uint32_t ubrc;
39
uint32_t ucr3;
40
+ uint32_t ucr4;
41
42
qemu_irq irq;
43
CharBackend chr;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
98
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
30
--
114
2.16.2
31
2.34.1
115
32
116
33
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
Use little endian for derivative OTP fuse key.
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
5
controller which is supported in QEMU using the imx_fec.c module
6
(actually called imx.enet for this model.)
7
4
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
5
Cc: qemu-stable@nongnu.org
9
imx.enet device like this:
6
Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
10
7
Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
#define FSL_IMX6_ENET_MAC_IRQ 119
9
Message-id: 20240422125813.1403-1-philmd@linaro.org
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
12
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
13
hw/arm/npcm7xx.c | 3 ++-
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
46
2 files changed, 29 insertions(+), 3 deletions(-)
47
15
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
16
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
49
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
18
--- a/hw/arm/npcm7xx.c
51
+++ b/include/hw/arm/fsl-imx6.h
19
+++ b/hw/arm/npcm7xx.c
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
20
@@ -XXX,XX +XXX,XX @@
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
21
#include "hw/qdev-clock.h"
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
22
#include "hw/qdev-properties.h"
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
23
#include "qapi/error.h"
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
24
+#include "qemu/bswap.h"
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
25
#include "qemu/units.h"
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
26
#include "sysemu/sysemu.h"
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
27
#include "target/arm/cpu-qom.h"
60
#define FSL_IMX6_PCIE1_IRQ 120
28
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
61
#define FSL_IMX6_PCIE2_IRQ 121
29
* The initial mask of disabled modules indicates the chip derivative (e.g.
62
#define FSL_IMX6_PCIE3_IRQ 122
30
* NPCM750 or NPCM730).
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
31
*/
64
index XXXXXXX..XXXXXXX 100644
32
- value = tswap32(nc->disabled_modules);
65
--- a/hw/net/imx_fec.c
33
+ value = cpu_to_le32(nc->disabled_modules);
66
+++ b/hw/net/imx_fec.c
34
npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
35
sizeof(value));
68
36
}
69
static void imx_eth_update(IMXFECState *s)
70
{
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
72
+ /*
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
75
+ * and older) since Linux associated both interrupt lines with Ethernet
76
+ * MAC interrupts. Specifically,
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
79
+ * with swapped interrupt assignments.
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
82
+ * work, though that is accidental.
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
88
+ * Linux instead received MAC interrupts on the timer interrupt.
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
90
+ * albeit accidentally, but qemu versions with the correct interrupt
91
+ * assignment fail.
92
+ *
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
94
+ * interrrupts on both interrupt lines. This should be changed if and when
95
+ * qemu supports IOMUX.
96
+ */
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
99
qemu_set_irq(s->irq[1], 1);
100
} else {
101
qemu_set_irq(s->irq[1], 0);
102
--
37
--
103
2.16.2
38
2.34.1
104
39
105
40
diff view generated by jsdifflib
1
From: Wei Huang <wei@redhat.com>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
This device implements the IM120417002 colors shield v1.1 for Arduino
4
time when guest VM runs. To find the physical base address correctly,
4
(which relies on the DM163 8x3-channel led driving logic) and features
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
5
a simple display of an 8x8 RGB matrix. The columns of the matrix are
6
However this string pattern is only available on x86_64. AArch64 uses a
6
driven by the DM163 and the rows are driven externally.
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
7
10
Signed-off-by: Wei Huang <wei@redhat.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
9
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
10
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
13
[PMM: updated to new reset hold method prototype]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
---
15
dump.c | 14 +++++++++++---
16
docs/system/arm/b-l475e-iot01a.rst | 3 +-
16
1 file changed, 11 insertions(+), 3 deletions(-)
17
include/hw/display/dm163.h | 59 +++++
18
hw/display/dm163.c | 349 +++++++++++++++++++++++++++++
19
hw/display/Kconfig | 3 +
20
hw/display/meson.build | 1 +
21
hw/display/trace-events | 14 ++
22
6 files changed, 428 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/display/dm163.h
24
create mode 100644 hw/display/dm163.c
17
25
18
diff --git a/dump.c b/dump.c
26
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
19
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
28
--- a/docs/system/arm/b-l475e-iot01a.rst
21
+++ b/dump.c
29
+++ b/docs/system/arm/b-l475e-iot01a.rst
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
30
@@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors.
23
31
Supported devices
24
lines = g_strsplit((char *)vmci, "\n", -1);
32
"""""""""""""""""
25
for (i = 0; lines[i]; i++) {
33
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
34
-Currently B-L475E-IOT01A machine's only supports the following devices:
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
35
+Currently B-L475E-IOT01A machines support the following devices:
28
+ const char *prefix = NULL;
36
29
+
37
- Cortex-M4F based STM32L4x5 SoC
30
+ if (s->dump_info.d_machine == EM_X86_64) {
38
- STM32L4x5 EXTI (Extended interrupts and events controller)
31
+ prefix = "NUMBER(phys_base)=";
39
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
40
- STM32L4x5 RCC (Reset and clock control)
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
41
- STM32L4x5 GPIOs (General-purpose I/Os)
42
- STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
43
+- optional 8x8 led display (based on DM163 driver)
44
45
Missing devices
46
"""""""""""""""
47
diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h
48
new file mode 100644
49
index XXXXXXX..XXXXXXX
50
--- /dev/null
51
+++ b/include/hw/display/dm163.h
52
@@ -XXX,XX +XXX,XX @@
53
+/*
54
+ * QEMU DM163 8x3-channel constant current led driver
55
+ * driving columns of associated 8x8 RGB matrix.
56
+ *
57
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
58
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
59
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
60
+ *
61
+ * SPDX-License-Identifier: GPL-2.0-or-later
62
+ */
63
+
64
+#ifndef HW_DISPLAY_DM163_H
65
+#define HW_DISPLAY_DM163_H
66
+
67
+#include "qom/object.h"
68
+#include "hw/qdev-core.h"
69
+
70
+#define TYPE_DM163 "dm163"
71
+OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
72
+
73
+#define RGB_MATRIX_NUM_ROWS 8
74
+#define RGB_MATRIX_NUM_COLS 8
75
+#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
76
+/* The last row is filled with 0 (turned off row) */
77
+#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
78
+
79
+typedef struct DM163State {
80
+ DeviceState parent_obj;
81
+
82
+ /* DM163 driver */
83
+ uint64_t bank0_shift_register[3];
84
+ uint64_t bank1_shift_register[3];
85
+ uint16_t latched_outputs[DM163_NUM_LEDS];
86
+ uint16_t outputs[DM163_NUM_LEDS];
87
+ qemu_irq sout;
88
+
89
+ uint8_t sin;
90
+ uint8_t dck;
91
+ uint8_t rst_b;
92
+ uint8_t lat_b;
93
+ uint8_t selbk;
94
+ uint8_t en_b;
95
+
96
+ /* IM120417002 colors shield */
97
+ uint8_t activated_rows;
98
+
99
+ /* 8x8 RGB matrix */
100
+ QemuConsole *console;
101
+ uint8_t redraw;
102
+ /* Rows currently being displayed on the matrix. */
103
+ /* The last row is filled with 0 (turned off row) */
104
+ uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
105
+ uint8_t last_buffer_idx;
106
+ uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
107
+ /* Used to simulate retinal persistence of rows */
108
+ uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
109
+} DM163State;
110
+
111
+#endif /* HW_DISPLAY_DM163_H */
112
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
113
new file mode 100644
114
index XXXXXXX..XXXXXXX
115
--- /dev/null
116
+++ b/hw/display/dm163.c
117
@@ -XXX,XX +XXX,XX @@
118
+/*
119
+ * QEMU DM163 8x3-channel constant current led driver
120
+ * driving columns of associated 8x8 RGB matrix.
121
+ *
122
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
123
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
124
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
125
+ *
126
+ * SPDX-License-Identifier: GPL-2.0-or-later
127
+ */
128
+
129
+/*
130
+ * The reference used for the DM163 is the following :
131
+ * http://www.siti.com.tw/product/spec/LED/DM163.pdf
132
+ */
133
+
134
+#include "qemu/osdep.h"
135
+#include "qapi/error.h"
136
+#include "migration/vmstate.h"
137
+#include "hw/irq.h"
138
+#include "hw/qdev-properties.h"
139
+#include "hw/display/dm163.h"
140
+#include "ui/console.h"
141
+#include "trace.h"
142
+
143
+#define LED_SQUARE_SIZE 100
144
+/* Number of frames a row stays visible after being turned off. */
145
+#define ROW_PERSISTENCE 3
146
+#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
147
+
148
+static const VMStateDescription vmstate_dm163 = {
149
+ .name = TYPE_DM163,
150
+ .version_id = 1,
151
+ .minimum_version_id = 1,
152
+ .fields = (const VMStateField[]) {
153
+ VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
154
+ VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
155
+ VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS),
156
+ VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS),
157
+ VMSTATE_UINT8(dck, DM163State),
158
+ VMSTATE_UINT8(en_b, DM163State),
159
+ VMSTATE_UINT8(lat_b, DM163State),
160
+ VMSTATE_UINT8(rst_b, DM163State),
161
+ VMSTATE_UINT8(selbk, DM163State),
162
+ VMSTATE_UINT8(sin, DM163State),
163
+ VMSTATE_UINT8(activated_rows, DM163State),
164
+ VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE,
165
+ RGB_MATRIX_NUM_COLS),
166
+ VMSTATE_UINT8(last_buffer_idx, DM163State),
167
+ VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS),
168
+ VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State,
169
+ RGB_MATRIX_NUM_ROWS),
170
+ VMSTATE_END_OF_LIST()
171
+ }
172
+};
173
+
174
+static void dm163_reset_hold(Object *obj, ResetType type)
175
+{
176
+ DM163State *s = DM163(obj);
177
+
178
+ s->sin = 0;
179
+ s->dck = 0;
180
+ s->rst_b = 0;
181
+ /* Ensuring the first falling edge of lat_b isn't missed */
182
+ s->lat_b = 1;
183
+ s->selbk = 0;
184
+ s->en_b = 0;
185
+ /* Reset stops the PWM, not the shift and latched registers. */
186
+ memset(s->outputs, 0, sizeof(s->outputs));
187
+
188
+ s->activated_rows = 0;
189
+ s->redraw = 0;
190
+ trace_dm163_redraw(s->redraw);
191
+ for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) {
192
+ memset(s->buffer[i], 0, sizeof(s->buffer[0]));
193
+ }
194
+ s->last_buffer_idx = 0;
195
+ memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row));
196
+ memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay));
197
+}
198
+
199
+static void dm163_dck_gpio_handler(void *opaque, int line, int new_state)
200
+{
201
+ DM163State *s = opaque;
202
+
203
+ if (new_state && !s->dck) {
204
+ /*
205
+ * On raising dck, sample selbk to get the bank to use, and
206
+ * sample sin for the bit to enter into the bank shift buffer.
207
+ */
208
+ uint64_t *sb =
209
+ s->selbk ? s->bank1_shift_register : s->bank0_shift_register;
210
+ /* Output the outgoing bit on sout */
211
+ const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) :
212
+ sb[2] & MAKE_64BIT_MASK(15, 1)) != 0;
213
+ qemu_set_irq(s->sout, sout);
214
+ /* Enter sin into the shift buffer */
215
+ sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1);
216
+ sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1);
217
+ sb[0] = (sb[0] << 1) | s->sin;
218
+ }
219
+
220
+ s->dck = new_state;
221
+ trace_dm163_dck(new_state);
222
+}
223
+
224
+static void dm163_propagate_outputs(DM163State *s)
225
+{
226
+ s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS;
227
+ /* Values are output when reset is high and enable is low. */
228
+ if (s->rst_b && !s->en_b) {
229
+ memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs));
230
+ } else {
231
+ memset(s->outputs, 0, sizeof(s->outputs));
232
+ }
233
+ for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) {
234
+ /* Grouping the 3 RGB channels in a pixel value */
235
+ const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8);
236
+ const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8);
237
+ const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8);
238
+ uint32_t rgba = 0;
239
+
240
+ trace_dm163_channels(3 * x + 2, r);
241
+ trace_dm163_channels(3 * x + 1, g);
242
+ trace_dm163_channels(3 * x + 0, b);
243
+
244
+ rgba = deposit32(rgba, 0, 8, r);
245
+ rgba = deposit32(rgba, 8, 8, g);
246
+ rgba = deposit32(rgba, 16, 8, b);
247
+
248
+ /* Led values are sent from the last one to the first one */
249
+ s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba;
250
+ }
251
+ for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
252
+ if (s->activated_rows & (1 << row)) {
253
+ s->buffer_idx_of_row[row] = s->last_buffer_idx;
254
+ s->redraw |= (1 << row);
255
+ trace_dm163_redraw(s->redraw);
34
+ }
256
+ }
35
+
257
+ }
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
258
+}
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
259
+
38
&phys_base) < 0) {
260
+static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state)
39
- warn_report("Failed to read NUMBER(phys_base)=");
261
+{
40
+ warn_report("Failed to read %s", prefix);
262
+ DM163State *s = opaque;
41
} else {
263
+
42
s->dump_info.phys_base = phys_base;
264
+ s->en_b = new_state;
43
}
265
+ dm163_propagate_outputs(s);
266
+ trace_dm163_en_b(new_state);
267
+}
268
+
269
+static uint8_t dm163_bank0(const DM163State *s, uint8_t led)
270
+{
271
+ /*
272
+ * Bank 0 uses 6 bits per led, so a value may be stored accross
273
+ * two uint64_t entries.
274
+ */
275
+ const uint8_t low_bit = 6 * led;
276
+ const uint8_t low_word = low_bit / 64;
277
+ const uint8_t high_word = (low_bit + 5) / 64;
278
+ const uint8_t low_shift = low_bit % 64;
279
+
280
+ if (low_word == high_word) {
281
+ /* Simple case: the value belongs to one entry. */
282
+ return extract64(s->bank0_shift_register[low_word], low_shift, 6);
283
+ }
284
+
285
+ const uint8_t nb_bits_in_low_word = 64 - low_shift;
286
+ const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word;
287
+
288
+ const uint64_t bits_in_low_word = \
289
+ extract64(s->bank0_shift_register[low_word], low_shift,
290
+ nb_bits_in_low_word);
291
+ const uint64_t bits_in_high_word = \
292
+ extract64(s->bank0_shift_register[high_word], 0,
293
+ nb_bits_in_high_word);
294
+ uint8_t val = 0;
295
+
296
+ val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word);
297
+ val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word,
298
+ bits_in_high_word);
299
+
300
+ return val;
301
+}
302
+
303
+static uint8_t dm163_bank1(const DM163State *s, uint8_t led)
304
+{
305
+ const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS];
306
+ return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8);
307
+}
308
+
309
+static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state)
310
+{
311
+ DM163State *s = opaque;
312
+
313
+ if (s->lat_b && !new_state) {
314
+ for (int led = 0; led < DM163_NUM_LEDS; led++) {
315
+ s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led);
316
+ }
317
+ dm163_propagate_outputs(s);
318
+ }
319
+
320
+ s->lat_b = new_state;
321
+ trace_dm163_lat_b(new_state);
322
+}
323
+
324
+static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state)
325
+{
326
+ DM163State *s = opaque;
327
+
328
+ s->rst_b = new_state;
329
+ dm163_propagate_outputs(s);
330
+ trace_dm163_rst_b(new_state);
331
+}
332
+
333
+static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state)
334
+{
335
+ DM163State *s = opaque;
336
+
337
+ s->selbk = new_state;
338
+ trace_dm163_selbk(new_state);
339
+}
340
+
341
+static void dm163_sin_gpio_handler(void *opaque, int line, int new_state)
342
+{
343
+ DM163State *s = opaque;
344
+
345
+ s->sin = new_state;
346
+ trace_dm163_sin(new_state);
347
+}
348
+
349
+static void dm163_rows_gpio_handler(void *opaque, int line, int new_state)
350
+{
351
+ DM163State *s = opaque;
352
+
353
+ if (new_state) {
354
+ s->activated_rows |= (1 << line);
355
+ s->buffer_idx_of_row[line] = s->last_buffer_idx;
356
+ s->redraw |= (1 << line);
357
+ trace_dm163_redraw(s->redraw);
358
+ } else {
359
+ s->activated_rows &= ~(1 << line);
360
+ s->row_persistence_delay[line] = ROW_PERSISTENCE;
361
+ }
362
+ trace_dm163_activated_rows(s->activated_rows);
363
+}
364
+
365
+static void dm163_invalidate_display(void *opaque)
366
+{
367
+ DM163State *s = (DM163State *)opaque;
368
+ s->redraw = 0xFF;
369
+ trace_dm163_redraw(s->redraw);
370
+}
371
+
372
+static void update_row_persistence_delay(DM163State *s, unsigned row)
373
+{
374
+ if (s->row_persistence_delay[row]) {
375
+ s->row_persistence_delay[row]--;
376
+ } else {
377
+ /*
378
+ * If the ROW_PERSISTENCE delay is up,
379
+ * the row is turned off.
380
+ */
381
+ s->buffer_idx_of_row[row] = TURNED_OFF_ROW;
382
+ s->redraw |= (1 << row);
383
+ trace_dm163_redraw(s->redraw);
384
+ }
385
+}
386
+
387
+static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest,
388
+ unsigned row)
389
+{
390
+ for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) {
391
+ for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) {
392
+ /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */
393
+ *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE];
394
+ }
395
+ }
396
+
397
+ dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row,
398
+ RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE);
399
+ s->redraw &= ~(1 << row);
400
+ trace_dm163_redraw(s->redraw);
401
+
402
+ return dest;
403
+}
404
+
405
+static void dm163_update_display(void *opaque)
406
+{
407
+ DM163State *s = (DM163State *)opaque;
408
+ DisplaySurface *surface = qemu_console_surface(s->console);
409
+ uint32_t *dest;
410
+
411
+ dest = surface_data(surface);
412
+ for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
413
+ update_row_persistence_delay(s, row);
414
+ if (!extract8(s->redraw, row, 1)) {
415
+ dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS;
416
+ continue;
417
+ }
418
+ dest = update_display_of_row(s, dest, row);
419
+ }
420
+}
421
+
422
+static const GraphicHwOps dm163_ops = {
423
+ .invalidate = dm163_invalidate_display,
424
+ .gfx_update = dm163_update_display,
425
+};
426
+
427
+static void dm163_realize(DeviceState *dev, Error **errp)
428
+{
429
+ DM163State *s = DM163(dev);
430
+
431
+ qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS);
432
+ qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1);
433
+ qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1);
434
+ qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1);
435
+ qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1);
436
+ qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1);
437
+ qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1);
438
+ qdev_init_gpio_out_named(dev, &s->sout, "sout", 1);
439
+
440
+ s->console = graphic_console_init(dev, 0, &dm163_ops, s);
441
+ qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE,
442
+ RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE);
443
+}
444
+
445
+static void dm163_class_init(ObjectClass *klass, void *data)
446
+{
447
+ DeviceClass *dc = DEVICE_CLASS(klass);
448
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
449
+
450
+ dc->desc = "DM163";
451
+ dc->vmsd = &vmstate_dm163;
452
+ dc->realize = dm163_realize;
453
+ rc->phases.hold = dm163_reset_hold;
454
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
455
+}
456
+
457
+static const TypeInfo dm163_types[] = {
458
+ {
459
+ .name = TYPE_DM163,
460
+ .parent = TYPE_DEVICE,
461
+ .instance_size = sizeof(DM163State),
462
+ .class_init = dm163_class_init
463
+ }
464
+};
465
+
466
+DEFINE_TYPES(dm163_types)
467
diff --git a/hw/display/Kconfig b/hw/display/Kconfig
468
index XXXXXXX..XXXXXXX 100644
469
--- a/hw/display/Kconfig
470
+++ b/hw/display/Kconfig
471
@@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT
472
bool
473
# defaults to "N", enabled by specific boards
474
depends on PIXMAN
475
+
476
+config DM163
477
+ bool
478
diff --git a/hw/display/meson.build b/hw/display/meson.build
479
index XXXXXXX..XXXXXXX 100644
480
--- a/hw/display/meson.build
481
+++ b/hw/display/meson.build
482
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c'))
483
484
system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
485
system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c'))
486
+system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c'))
487
488
if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
489
config_all_devices.has_key('CONFIG_VGA_PCI') or
490
diff --git a/hw/display/trace-events b/hw/display/trace-events
491
index XXXXXXX..XXXXXXX 100644
492
--- a/hw/display/trace-events
493
+++ b/hw/display/trace-events
494
@@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI
495
macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
496
macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
497
macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d"
498
+
499
+# dm163.c
500
+dm163_redraw(uint8_t redraw) "0x%02x"
501
+dm163_dck(unsigned new_state) "dck : %u"
502
+dm163_en_b(unsigned new_state) "en_b : %u"
503
+dm163_rst_b(unsigned new_state) "rst_b : %u"
504
+dm163_lat_b(unsigned new_state) "lat_b : %u"
505
+dm163_sin(unsigned new_state) "sin : %u"
506
+dm163_selbk(unsigned new_state) "selbk : %u"
507
+dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 ""
508
+dm163_bits_ppi(unsigned dest_width) "dest_width : %u"
509
+dm163_leds(int led, uint32_t value) "led %d: 0x%x"
510
+dm163_channels(int channel, uint8_t value) "channel %d: 0x%x"
511
+dm163_refresh_rate(uint32_t rr) "refresh rate %d"
44
--
512
--
45
2.16.2
513
2.34.1
46
514
47
515
diff view generated by jsdifflib
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
code for keeping the secondary CPUs in a pen needs to have
3
a version for A64 as well as A32. Without this, the
4
secondary CPUs go into an infinite loop of taking undefined
5
instruction exceptions.
6
2
3
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
4
to the optional DM163 display from the board code (GPIOs outputs need
5
to be connected to both SYSCFG inputs and DM163 inputs).
6
7
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
8
9
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
10
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
10
---
14
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
15
hw/arm/stm32l4x5_soc.c | 6 ++++--
12
1 file changed, 40 insertions(+), 1 deletion(-)
16
tests/qtest/stm32l4x5_gpio-test.c | 13 ++++++++-----
17
tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++-------
18
3 files changed, 22 insertions(+), 14 deletions(-)
13
19
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
20
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
22
--- a/hw/arm/stm32l4x5_soc.c
17
+++ b/hw/arm/raspi.c
23
+++ b/hw/arm/stm32l4x5_soc.c
18
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
25
/*
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
26
* STM32L4x5 SoC family
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
27
*
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
28
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
23
29
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
24
/* Table of Linux board IDs for different Pi versions */
30
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
31
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
32
*
27
info->smp_loader_start);
33
* SPDX-License-Identifier: GPL-2.0-or-later
34
*
35
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
36
}
37
}
38
39
+ qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL);
40
+
41
/* EXTI device */
42
busdev = SYS_BUS_DEVICE(&s->exti);
43
if (!sysbus_realize(busdev, errp)) {
44
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/tests/qtest/stm32l4x5_gpio-test.c
47
+++ b/tests/qtest/stm32l4x5_gpio-test.c
48
@@ -XXX,XX +XXX,XX @@
49
#define OTYPER_PUSH_PULL 0
50
#define OTYPER_OPEN_DRAIN 1
51
52
+/* SoC forwards GPIOs to SysCfg */
53
+#define SYSCFG "/machine/soc"
54
+
55
const uint32_t moder_reset[NUM_GPIOS] = {
56
0xABFFFFFF,
57
0xFFFFFEBF,
58
@@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data)
59
uint32_t gpio = test_gpio_addr(data);
60
unsigned int gpio_id = get_gpio_id(gpio);
61
62
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
63
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
64
65
/* Set a bit in ODR and check nothing happens */
66
gpio_set_bit(gpio, ODR, pin, 1);
67
@@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data)
68
uint32_t gpio = test_gpio_addr(data);
69
unsigned int gpio_id = get_gpio_id(gpio);
70
71
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
72
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
73
74
/* Configure a line as input, raise it, and check that the pin is high */
75
gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
76
@@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data)
77
uint32_t gpio = test_gpio_addr(data);
78
unsigned int gpio_id = get_gpio_id(gpio);
79
80
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
81
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
82
83
/* Configure a line as input with pull-up, check the line is set high */
84
gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
85
@@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data)
86
uint32_t gpio = test_gpio_addr(data);
87
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
88
89
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
90
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
91
92
/* Setting a line high externally, configuring it in push-pull output */
93
/* And checking the pin was disconnected */
94
@@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data)
95
uint32_t gpio = test_gpio_addr(data);
96
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
97
98
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
99
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
100
101
/* Setting a line high externally, configuring it in open-drain output */
102
/* And checking the pin was disconnected */
103
diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/tests/qtest/stm32l4x5_syscfg-test.c
106
+++ b/tests/qtest/stm32l4x5_syscfg-test.c
107
@@ -XXX,XX +XXX,XX @@
108
/*
109
* QTest testcase for STM32L4x5_SYSCFG
110
*
111
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
112
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
113
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
114
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
115
*
116
* This work is licensed under the terms of the GNU GPL, version 2 or later.
117
* See the COPYING file in the top-level directory.
118
@@ -XXX,XX +XXX,XX @@
119
#define SYSCFG_SWPR2 0x28
120
#define INVALID_ADDR 0x2C
121
122
+/* SoC forwards GPIOs to SysCfg */
123
+#define SYSCFG "/machine/soc"
124
+#define EXTI "/machine/soc/exti"
125
+
126
static void syscfg_writel(unsigned int offset, uint32_t value)
127
{
128
writel(SYSCFG_BASE_ADDR + offset, value);
129
@@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset)
130
131
static void syscfg_set_irq(int num, int level)
132
{
133
- qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
134
- NULL, num, level);
135
+ qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
28
}
136
}
29
137
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
138
static void system_reset(void)
31
+{
139
@@ -XXX,XX +XXX,XX @@ static void test_interrupt(void)
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
140
* Test that GPIO rising lines result in an irq
33
+ * The mechanism for doing the spin-table is also entirely different.
141
* with the right configuration
34
+ * We must have four 64-bit fields at absolute addresses
142
*/
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
143
- qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
36
+ * our CPUs, and which we must ensure are zero initialized before
144
+ qtest_irq_intercept_in(global_qtest, EXTI);
37
+ * the primary CPU goes into the kernel. We put these variables inside
145
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
146
/* GPIOA is the default source for EXTI lines 0 to 15 */
39
+ */
147
40
+ static const uint32_t smpboot[] = {
148
@@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void)
41
+ 0xd2801b05, /* mov x5, 0xd8 */
149
* Test that syscfg irq sets the right exti irq
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
150
*/
43
+ 0x924004c6, /* and x6, x6, #0x3 */
151
44
+ 0xd503205f, /* spin: wfe */
152
- qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
153
+ qtest_irq_intercept_in(global_qtest, EXTI);
46
+ 0xb4ffffc4, /* cbz x4, spin */
154
47
+ 0xd2800000, /* mov x0, #0x0 */
155
syscfg_set_irq(0, 1);
48
+ 0xd2800001, /* mov x1, #0x0 */
156
49
+ 0xd2800002, /* mov x2, #0x0 */
157
@@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void)
50
+ 0xd2800003, /* mov x3, #0x0 */
158
* Test that an irq is generated only by the right GPIO
51
+ 0xd61f0080, /* br x4 */
159
*/
52
+ };
160
53
+
161
- qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
54
+ static const uint64_t spintables[] = {
162
+ qtest_irq_intercept_in(global_qtest, EXTI);
55
+ 0, 0, 0, 0
163
56
+ };
164
/* GPIOA is the default source for EXTI lines 0 to 15 */
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
63
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
65
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
68
/* Pi2 and Pi3 requires SMP setup */
69
if (version >= 2) {
70
binfo.smp_loader_start = SMPBOOT_ADDR;
71
- binfo.write_secondary_boot = write_smpboot;
72
+ if (version == 2) {
73
+ binfo.write_secondary_boot = write_smpboot;
74
+ } else {
75
+ binfo.write_secondary_boot = write_smpboot64;
76
+ }
77
binfo.secondary_cpu_reset_hook = reset_secondary;
78
}
79
165
80
--
166
--
81
2.16.2
167
2.34.1
82
168
83
169
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
doesn't really corespond to anything in real hardware and server as a
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
kitchensink accumulating events normally reported via USR1 and USR2
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
registers.
6
Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
7
8
Change the code to explicitly evaluate state of interrupts reported
9
via USR1 and USR2 against corresponding masking bits and use the to
10
detemine if IRQ line should be asserted or not.
11
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
13
reasons:
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
8
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
9
hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
34
1 file changed, 16 insertions(+), 8 deletions(-)
10
1 file changed, 32 insertions(+), 14 deletions(-)
35
11
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
12
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
37
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
14
--- a/hw/arm/b-l475e-iot01a.c
39
+++ b/hw/char/imx_serial.c
15
+++ b/hw/arm/b-l475e-iot01a.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
16
@@ -XXX,XX +XXX,XX @@
41
17
* B-L475E-IOT01A Discovery Kit machine
42
static void imx_update(IMXSerialState *s)
18
* (B-L475E-IOT01A IoT Node)
19
*
20
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
21
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
22
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
23
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
24
*
25
* SPDX-License-Identifier: GPL-2.0-or-later
26
*
27
@@ -XXX,XX +XXX,XX @@
28
29
/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
30
31
-static void b_l475e_iot01a_init(MachineState *machine)
32
+#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
33
+OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
34
+
35
+typedef struct Bl475eMachineState {
36
+ MachineState parent_obj;
37
+
38
+ Stm32l4x5SocState soc;
39
+} Bl475eMachineState;
40
+
41
+static void bl475e_init(MachineState *machine)
43
{
42
{
44
- uint32_t flags;
43
+ Bl475eMachineState *s = B_L475E_IOT01A(machine);
45
+ uint32_t usr1;
44
const Stm32l4x5SocClass *sc;
46
+ uint32_t usr2;
45
- DeviceState *dev;
47
+ uint32_t mask;
46
48
47
- dev = qdev_new(TYPE_STM32L4X5XG_SOC);
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
48
- object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
49
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
50
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
52
- } else {
51
+ TYPE_STM32L4X5XG_SOC);
53
- flags &= ~USR1_TRDY;
52
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
54
- }
53
55
+ /*
54
- sc = STM32L4X5_SOC_GET_CLASS(dev);
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
55
- armv7m_load_kernel(ARM_CPU(first_cpu),
57
+ * UCR1, so we can get away with something as simple as the
56
- machine->kernel_filename,
58
+ * following:
57
- 0, sc->flash_size);
59
+ */
58
+ sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
59
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
61
+ /*
60
+ sc->flash_size);
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
61
}
71
62
72
static void imx_serial_reset(IMXSerialState *s)
63
-static void b_l475e_iot01a_machine_init(MachineClass *mc)
64
+static void bl475e_machine_init(ObjectClass *oc, void *data)
65
{
66
+ MachineClass *mc = MACHINE_CLASS(oc);
67
static const char *machine_valid_cpu_types[] = {
68
ARM_CPU_TYPE_NAME("cortex-m4"),
69
NULL
70
};
71
mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
72
- mc->init = b_l475e_iot01a_init;
73
+ mc->init = bl475e_init;
74
mc->valid_cpu_types = machine_valid_cpu_types;
75
76
/* SRAM pre-allocated as part of the SoC instantiation */
77
mc->default_ram_size = 0;
78
}
79
80
-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
81
+static const TypeInfo bl475e_machine_type[] = {
82
+ {
83
+ .name = TYPE_B_L475E_IOT01A,
84
+ .parent = TYPE_MACHINE,
85
+ .instance_size = sizeof(Bl475eMachineState),
86
+ .class_init = bl475e_machine_init,
87
+ }
88
+};
89
+
90
+DEFINE_TYPES(bl475e_machine_type)
73
--
91
--
74
2.16.2
92
2.34.1
75
93
76
94
diff view generated by jsdifflib
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
some differences. Notably, the MPIDR affinity aff1 values it
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
2
6
Rather than trying to have one device with properties that
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
7
configure it differently for the two cases, create two
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
8
separate QOM devices for the two SoCs. We use the same approach
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
as hw/arm/aspeed_soc.c and share code and have a data table
6
Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
10
that might differ per-SoC. For the moment the two types don't
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
actually have different behaviour.
8
---
9
hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++--
10
hw/arm/Kconfig | 1 +
11
2 files changed, 58 insertions(+), 2 deletions(-)
12
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
19
hw/arm/raspi.c | 3 ++-
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
15
--- a/hw/arm/b-l475e-iot01a.c
25
+++ b/include/hw/arm/bcm2836.h
16
+++ b/hw/arm/b-l475e-iot01a.c
26
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@
27
18
#include "hw/boards.h"
28
#define BCM283X_NCPUS 4
19
#include "hw/qdev-properties.h"
29
20
#include "qemu/error-report.h"
30
+/* These type names are for specific SoCs; other than instantiating
21
-#include "hw/arm/stm32l4x5_soc.h"
31
+ * them, code using these devices should always handle them via the
22
#include "hw/arm/boot.h"
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
23
+#include "hw/core/split-irq.h"
24
+#include "hw/arm/stm32l4x5_soc.h"
25
+#include "hw/gpio/stm32l4x5_gpio.h"
26
+#include "hw/display/dm163.h"
27
28
-/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
29
+/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
30
+
31
+/*
32
+ * There are actually 14 input pins in the DM163 device.
33
+ * Here the DM163 input pin EN isn't connected to the STM32L4x5
34
+ * GPIOs as the IM120417002 colors shield doesn't actually use
35
+ * this pin to drive the RGB matrix.
33
+ */
36
+ */
34
+#define TYPE_BCM2836 "bcm2836"
37
+#define NUM_DM163_INPUTS 13
35
+#define TYPE_BCM2837 "bcm2837"
36
+
38
+
37
typedef struct BCM283XState {
39
+static const unsigned dm163_input[NUM_DM163_INPUTS] = {
38
/*< private >*/
40
+ 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */
39
DeviceState parent_obj;
41
+ 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
42
+ 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */
41
BCM2835PeripheralState peripherals;
43
+ 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */
42
} BCM283XState;
44
+ 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */
43
45
+ 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */
44
+typedef struct BCM283XInfo BCM283XInfo;
46
+ 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */
47
+ 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */
48
+ 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */
49
+ 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */
50
+ 2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */
51
+ 2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */
52
+ 2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */
53
+};
54
55
#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
56
OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
57
@@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState {
58
MachineState parent_obj;
59
60
Stm32l4x5SocState soc;
61
+ SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
62
+ DM163State dm163;
63
} Bl475eMachineState;
64
65
static void bl475e_init(MachineState *machine)
66
{
67
Bl475eMachineState *s = B_L475E_IOT01A(machine);
68
const Stm32l4x5SocClass *sc;
69
+ DeviceState *dev, *gpio_out_splitter;
70
+ unsigned gpio, pin;
71
72
object_initialize_child(OBJECT(machine), "soc", &s->soc,
73
TYPE_STM32L4X5XG_SOC);
74
@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)
75
sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
76
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
77
sc->flash_size);
45
+
78
+
46
+typedef struct BCM283XClass {
79
+ if (object_class_by_name(TYPE_DM163)) {
47
+ DeviceClass parent_class;
80
+ object_initialize_child(OBJECT(machine), "dm163",
48
+ const BCM283XInfo *info;
81
+ &s->dm163, TYPE_DM163);
49
+} BCM283XClass;
82
+ dev = DEVICE(&s->dm163);
83
+ qdev_realize(dev, NULL, &error_abort);
50
+
84
+
51
+#define BCM283X_CLASS(klass) \
85
+ for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
86
+ object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
53
+#define BCM283X_GET_CLASS(obj) \
87
+ &s->gpio_splitters[i], TYPE_SPLIT_IRQ);
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
88
+ gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
89
+ qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
90
+ qdev_realize(gpio_out_splitter, NULL, &error_fatal);
55
+
91
+
56
#endif /* BCM2836_H */
92
+ qdev_connect_gpio_out(gpio_out_splitter, 0,
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
93
+ qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
58
index XXXXXXX..XXXXXXX 100644
94
+ qdev_connect_gpio_out(gpio_out_splitter, 1,
59
--- a/hw/arm/bcm2836.c
95
+ qdev_get_gpio_in(dev, i));
60
+++ b/hw/arm/bcm2836.c
96
+ gpio = dm163_input[i] / GPIO_NUM_PINS;
61
@@ -XXX,XX +XXX,XX @@
97
+ pin = dm163_input[i] % GPIO_NUM_PINS;
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
98
+ qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
63
#define BCM2836_CONTROL_BASE 0x40000000
99
+ qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
64
100
+ }
65
+struct BCM283XInfo {
66
+ const char *name;
67
+};
68
+
69
+static const BCM283XInfo bcm283x_socs[] = {
70
+ {
71
+ .name = TYPE_BCM2836,
72
+ },
73
+ {
74
+ .name = TYPE_BCM2837,
75
+ },
76
+};
77
+
78
static void bcm2836_init(Object *obj)
79
{
80
BCM283XState *s = BCM283X(obj);
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
82
DEFINE_PROP_END_OF_LIST()
83
};
84
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
96
97
-static const TypeInfo bcm2836_type_info = {
98
+static const TypeInfo bcm283x_type_info = {
99
.name = TYPE_BCM283X,
100
.parent = TYPE_DEVICE,
101
.instance_size = sizeof(BCM283XState),
102
.instance_init = bcm2836_init,
103
- .class_init = bcm2836_class_init,
104
+ .class_size = sizeof(BCM283XClass),
105
+ .abstract = true,
106
};
107
108
static void bcm2836_register_types(void)
109
{
110
- type_register_static(&bcm2836_type_info);
111
+ int i;
112
+
113
+ type_register_static(&bcm283x_type_info);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
115
+ TypeInfo ti = {
116
+ .name = bcm283x_socs[i].name,
117
+ .parent = TYPE_BCM283X,
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
101
+ }
123
}
102
}
124
103
125
type_init(bcm2836_register_types)
104
static void bl475e_machine_init(ObjectClass *oc, void *data)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
105
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
127
index XXXXXXX..XXXXXXX 100644
106
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/raspi.c
107
--- a/hw/arm/Kconfig
129
+++ b/hw/arm/raspi.c
108
+++ b/hw/arm/Kconfig
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
109
@@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A
131
BusState *bus;
110
default y
132
DeviceState *carddev;
111
depends on TCG && ARM
133
112
select STM32L4X5_SOC
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
113
+ imply DM163
135
+ object_initialize(&s->soc, sizeof(s->soc),
114
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
115
config STM32L4X5_SOC
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
116
bool
138
&error_abort);
139
140
--
117
--
141
2.16.2
118
2.34.1
142
119
143
120
diff view generated by jsdifflib
New patch
1
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
3
`test_dm163_bank()`
4
Checks that the pin "sout" of the DM163 led driver outputs the values
5
received on pin "sin" with the expected latency (depending on the bank).
6
7
`test_dm163_gpio_connection()`
8
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
9
DM163 device.
10
11
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
12
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
13
Acked-by: Thomas Huth <thuth@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++
19
tests/qtest/meson.build | 2 +
20
2 files changed, 196 insertions(+)
21
create mode 100644 tests/qtest/dm163-test.c
22
23
diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c
24
new file mode 100644
25
index XXXXXXX..XXXXXXX
26
--- /dev/null
27
+++ b/tests/qtest/dm163-test.c
28
@@ -XXX,XX +XXX,XX @@
29
+/*
30
+ * QTest testcase for DM163
31
+ *
32
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
33
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
34
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
35
+ *
36
+ * SPDX-License-Identifier: GPL-2.0-or-later
37
+ */
38
+
39
+#include "qemu/osdep.h"
40
+#include "libqtest.h"
41
+
42
+enum DM163_INPUTS {
43
+ SIN = 8,
44
+ DCK = 9,
45
+ RST_B = 10,
46
+ LAT_B = 11,
47
+ SELBK = 12,
48
+ EN_B = 13
49
+};
50
+
51
+#define DEVICE_NAME "/machine/dm163"
52
+#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name, \
53
+ value)
54
+#define GPIO_PULSE(name) \
55
+ do { \
56
+ GPIO_OUT(name, 1); \
57
+ GPIO_OUT(name, 0); \
58
+ } while (0)
59
+
60
+
61
+static void rise_gpio_pin_dck(QTestState *qts)
62
+{
63
+ /* Configure output mode for pin PB1 */
64
+ qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
65
+ /* Write 1 in ODR for PB1 */
66
+ qtest_writel(qts, 0x48000414, 0x00000002);
67
+}
68
+
69
+static void lower_gpio_pin_dck(QTestState *qts)
70
+{
71
+ /* Configure output mode for pin PB1 */
72
+ qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
73
+ /* Write 0 in ODR for PB1 */
74
+ qtest_writel(qts, 0x48000414, 0x00000000);
75
+}
76
+
77
+static void rise_gpio_pin_selbk(QTestState *qts)
78
+{
79
+ /* Configure output mode for pin PC5 */
80
+ qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
81
+ /* Write 1 in ODR for PC5 */
82
+ qtest_writel(qts, 0x48000814, 0x00000020);
83
+}
84
+
85
+static void lower_gpio_pin_selbk(QTestState *qts)
86
+{
87
+ /* Configure output mode for pin PC5 */
88
+ qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
89
+ /* Write 0 in ODR for PC5 */
90
+ qtest_writel(qts, 0x48000814, 0x00000000);
91
+}
92
+
93
+static void rise_gpio_pin_lat_b(QTestState *qts)
94
+{
95
+ /* Configure output mode for pin PC4 */
96
+ qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
97
+ /* Write 1 in ODR for PC4 */
98
+ qtest_writel(qts, 0x48000814, 0x00000010);
99
+}
100
+
101
+static void lower_gpio_pin_lat_b(QTestState *qts)
102
+{
103
+ /* Configure output mode for pin PC4 */
104
+ qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
105
+ /* Write 0 in ODR for PC4 */
106
+ qtest_writel(qts, 0x48000814, 0x00000000);
107
+}
108
+
109
+static void rise_gpio_pin_rst_b(QTestState *qts)
110
+{
111
+ /* Configure output mode for pin PC3 */
112
+ qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
113
+ /* Write 1 in ODR for PC3 */
114
+ qtest_writel(qts, 0x48000814, 0x00000008);
115
+}
116
+
117
+static void lower_gpio_pin_rst_b(QTestState *qts)
118
+{
119
+ /* Configure output mode for pin PC3 */
120
+ qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
121
+ /* Write 0 in ODR for PC3 */
122
+ qtest_writel(qts, 0x48000814, 0x00000000);
123
+}
124
+
125
+static void rise_gpio_pin_sin(QTestState *qts)
126
+{
127
+ /* Configure output mode for pin PA4 */
128
+ qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
129
+ /* Write 1 in ODR for PA4 */
130
+ qtest_writel(qts, 0x48000014, 0x00000010);
131
+}
132
+
133
+static void lower_gpio_pin_sin(QTestState *qts)
134
+{
135
+ /* Configure output mode for pin PA4 */
136
+ qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
137
+ /* Write 0 in ODR for PA4 */
138
+ qtest_writel(qts, 0x48000014, 0x00000000);
139
+}
140
+
141
+static void test_dm163_bank(const void *opaque)
142
+{
143
+ const unsigned bank = (uintptr_t) opaque;
144
+ const int width = bank ? 192 : 144;
145
+
146
+ QTestState *qts = qtest_initf("-M b-l475e-iot01a");
147
+ qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
148
+ GPIO_OUT(RST_B, 1);
149
+ GPIO_OUT(EN_B, 0);
150
+ GPIO_OUT(DCK, 0);
151
+ GPIO_OUT(SELBK, bank);
152
+ GPIO_OUT(LAT_B, 1);
153
+
154
+ /* Fill bank with zeroes */
155
+ GPIO_OUT(SIN, 0);
156
+ for (int i = 0; i < width; i++) {
157
+ GPIO_PULSE(DCK);
158
+ }
159
+ /* Fill bank with ones, check that we get the previous zeroes */
160
+ GPIO_OUT(SIN, 1);
161
+ for (int i = 0; i < width; i++) {
162
+ GPIO_PULSE(DCK);
163
+ g_assert(!qtest_get_irq(qts, 0));
164
+ }
165
+
166
+ /* Pulse one more bit in the bank, check that we get a one */
167
+ GPIO_PULSE(DCK);
168
+ g_assert(qtest_get_irq(qts, 0));
169
+
170
+ qtest_quit(qts);
171
+}
172
+
173
+static void test_dm163_gpio_connection(void)
174
+{
175
+ QTestState *qts = qtest_init("-M b-l475e-iot01a");
176
+ qtest_irq_intercept_in(qts, DEVICE_NAME);
177
+
178
+ g_assert_false(qtest_get_irq(qts, SIN));
179
+ g_assert_false(qtest_get_irq(qts, DCK));
180
+ g_assert_false(qtest_get_irq(qts, RST_B));
181
+ g_assert_false(qtest_get_irq(qts, LAT_B));
182
+ g_assert_false(qtest_get_irq(qts, SELBK));
183
+
184
+ rise_gpio_pin_dck(qts);
185
+ g_assert_true(qtest_get_irq(qts, DCK));
186
+ lower_gpio_pin_dck(qts);
187
+ g_assert_false(qtest_get_irq(qts, DCK));
188
+
189
+ rise_gpio_pin_lat_b(qts);
190
+ g_assert_true(qtest_get_irq(qts, LAT_B));
191
+ lower_gpio_pin_lat_b(qts);
192
+ g_assert_false(qtest_get_irq(qts, LAT_B));
193
+
194
+ rise_gpio_pin_selbk(qts);
195
+ g_assert_true(qtest_get_irq(qts, SELBK));
196
+ lower_gpio_pin_selbk(qts);
197
+ g_assert_false(qtest_get_irq(qts, SELBK));
198
+
199
+ rise_gpio_pin_rst_b(qts);
200
+ g_assert_true(qtest_get_irq(qts, RST_B));
201
+ lower_gpio_pin_rst_b(qts);
202
+ g_assert_false(qtest_get_irq(qts, RST_B));
203
+
204
+ rise_gpio_pin_sin(qts);
205
+ g_assert_true(qtest_get_irq(qts, SIN));
206
+ lower_gpio_pin_sin(qts);
207
+ g_assert_false(qtest_get_irq(qts, SIN));
208
+
209
+ g_assert_false(qtest_get_irq(qts, DCK));
210
+ g_assert_false(qtest_get_irq(qts, LAT_B));
211
+ g_assert_false(qtest_get_irq(qts, SELBK));
212
+ g_assert_false(qtest_get_irq(qts, RST_B));
213
+}
214
+
215
+int main(int argc, char **argv)
216
+{
217
+ g_test_init(&argc, &argv, NULL);
218
+ qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
219
+ qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
220
+ qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
221
+ return g_test_run();
222
+}
223
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
224
index XXXXXXX..XXXXXXX 100644
225
--- a/tests/qtest/meson.build
226
+++ b/tests/qtest/meson.build
227
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
228
(config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
229
(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
230
(config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
231
+ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
232
+ config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
233
['arm-cpu-features',
234
'boot-serial-test']
235
236
--
237
2.34.1
238
239
diff view generated by jsdifflib