1
Arm patch queue -- these are all bug fix patches but we might
1
It's been quiet on the arm front this week, so all I have is
2
as well put them in to rc0...
2
these coverity fixes I posted a while back...
3
3
4
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
6
The following changes since commit 853546f8128476eefb701d4a55b2781bb3a46faa:
8
7
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
8
Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into staging (2024-03-22 10:59:57 +0000)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240325
14
13
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
14
for you to fetch changes up to 55c79639d553c1b7a82b4cde781ad5f316f45b0e:
16
15
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
16
tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25 10:41:01 +0000)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
20
* Fixes for seven minor coverity issues
22
* dump: Update correct kdump phys_base field for AArch64
23
* char: i.MX: Add support for "TX complete" interrupt
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
25
to boot a Debian Linux kernel on raspi3
26
21
27
----------------------------------------------------------------
22
----------------------------------------------------------------
28
Andrey Smirnov (2):
23
Peter Maydell (7):
29
char: i.MX: Simplify imx_update()
24
tests/qtest/npcm7xx_emc_test: Don't leak cmd_line
30
char: i.MX: Add support for "TX complete" interrupt
25
tests/unit/socket-helpers: Don't close(-1)
26
net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp()
27
hw/misc/pca9554: Correct error check bounds in get/set pin functions
28
hw/nvram/mac_nvram: Report failure to write data
29
tests/unit/test-throttle: Avoid unintended integer division
30
tests/qtest/libqtest.c: Check for g_setenv() failure
31
31
32
Guenter Roeck (1):
32
hw/misc/pca9554.c | 4 ++--
33
fsl-imx6: Swap Ethernet interrupt defines
33
hw/nvram/mac_nvram.c | 5 ++++-
34
34
net/af-xdp.c | 3 +--
35
Peter Maydell (9):
35
tests/qtest/libqtest.c | 6 +++++-
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
36
tests/qtest/npcm7xx_emc-test.c | 4 ++--
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
37
tests/unit/socket-helpers.c | 4 +++-
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
38
tests/unit/test-throttle.c | 4 ++--
39
hw/arm/bcm2386: Fix parent type of bcm2386
39
7 files changed, 19 insertions(+), 11 deletions(-)
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
41
hw/arm/bcm2836: Create proper bcm2837 device
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
43
hw/arm/bcm2836: Hardcode correct CPU type
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
46
Wei Huang (1):
47
dump: Update correct kdump phys_base field for AArch64
48
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
50
include/hw/arm/fsl-imx6.h | 4 +-
51
include/hw/char/imx_serial.h | 3 ++
52
dump.c | 14 +++++--
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
54
hw/arm/boot.c | 12 ++++++
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
57
hw/net/imx_fec.c | 28 +++++++++++++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
59
diff view generated by jsdifflib
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
The sabrelite machine model used by qemu-system-arm is based on the
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
5
controller which is supported in QEMU using the imx_fec.c module
6
(actually called imx.enet for this model.)
7
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
9
imx.enet device like this:
10
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
12
#define FSL_IMX6_ENET_MAC_IRQ 119
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
46
2 files changed, 29 insertions(+), 3 deletions(-)
47
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
51
+++ b/include/hw/arm/fsl-imx6.h
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
60
#define FSL_IMX6_PCIE1_IRQ 120
61
#define FSL_IMX6_PCIE2_IRQ 121
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
66
+++ b/hw/net/imx_fec.c
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
68
69
static void imx_eth_update(IMXFECState *s)
70
{
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
72
+ /*
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
75
+ * and older) since Linux associated both interrupt lines with Ethernet
76
+ * MAC interrupts. Specifically,
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
79
+ * with swapped interrupt assignments.
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
82
+ * work, though that is accidental.
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
88
+ * Linux instead received MAC interrupts on the timer interrupt.
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
90
+ * albeit accidentally, but qemu versions with the correct interrupt
91
+ * assignment fail.
92
+ *
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
94
+ * interrrupts on both interrupt lines. This should be changed if and when
95
+ * qemu supports IOMUX.
96
+ */
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
99
qemu_set_irq(s->irq[1], 1);
100
} else {
101
qemu_set_irq(s->irq[1], 0);
102
--
103
2.16.2
104
105
diff view generated by jsdifflib
Deleted patch
1
From: Wei Huang <wei@redhat.com>
2
1
3
For guest kernel that supports KASLR, the load address can change every
4
time when guest VM runs. To find the physical base address correctly,
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
10
Signed-off-by: Wei Huang <wei@redhat.com>
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
dump.c | 14 +++++++++++---
16
1 file changed, 11 insertions(+), 3 deletions(-)
17
18
diff --git a/dump.c b/dump.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
21
+++ b/dump.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
23
24
lines = g_strsplit((char *)vmci, "\n", -1);
25
for (i = 0; lines[i]; i++) {
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
28
+ const char *prefix = NULL;
29
+
30
+ if (s->dump_info.d_machine == EM_X86_64) {
31
+ prefix = "NUMBER(phys_base)=";
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
34
+ }
35
+
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
38
&phys_base) < 0) {
39
- warn_report("Failed to read NUMBER(phys_base)=");
40
+ warn_report("Failed to read %s", prefix);
41
} else {
42
s->dump_info.phys_base = phys_base;
43
}
44
--
45
2.16.2
46
47
diff view generated by jsdifflib
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
In test_rx() and test_tx() we allocate a GString *cmd_line
2
code for keeping the secondary CPUs in a pen needs to have
2
but never free it. This is pretty harmless in a test case, but
3
a version for A64 as well as A32. Without this, the
3
Coverity spotted it.
4
secondary CPUs go into an infinite loop of taking undefined
5
instruction exceptions.
6
4
5
Resolves: Coverity CID 1507122
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
8
Reviewed-by: Thomas Huth <thuth@redhat.com>
9
Message-id: 20240312183810.557768-2-peter.maydell@linaro.org
10
---
10
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
11
tests/qtest/npcm7xx_emc-test.c | 4 ++--
12
1 file changed, 40 insertions(+), 1 deletion(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
13
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
16
--- a/tests/qtest/npcm7xx_emc-test.c
17
+++ b/hw/arm/raspi.c
17
+++ b/tests/qtest/npcm7xx_emc-test.c
18
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
19
static void test_tx(gconstpointer test_data)
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
23
24
/* Table of Linux board IDs for different Pi versions */
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
27
info->smp_loader_start);
28
}
29
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
31
+{
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
33
+ * The mechanism for doing the spin-table is also entirely different.
34
+ * We must have four 64-bit fields at absolute addresses
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
36
+ * our CPUs, and which we must ensure are zero initialized before
37
+ * the primary CPU goes into the kernel. We put these variables inside
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
39
+ */
40
+ static const uint32_t smpboot[] = {
41
+ 0xd2801b05, /* mov x5, 0xd8 */
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
43
+ 0x924004c6, /* and x6, x6, #0x3 */
44
+ 0xd503205f, /* spin: wfe */
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
46
+ 0xb4ffffc4, /* cbz x4, spin */
47
+ 0xd2800000, /* mov x0, #0x0 */
48
+ 0xd2800001, /* mov x1, #0x0 */
49
+ 0xd2800002, /* mov x2, #0x0 */
50
+ 0xd2800003, /* mov x3, #0x0 */
51
+ 0xd61f0080, /* br x4 */
52
+ };
53
+
54
+ static const uint64_t spintables[] = {
55
+ 0, 0, 0, 0
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
63
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
65
{
20
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
21
const TestData *td = test_data;
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
22
- GString *cmd_line = g_string_new("-machine quanta-gsj");
68
/* Pi2 and Pi3 requires SMP setup */
23
+ g_autoptr(GString) cmd_line = g_string_new("-machine quanta-gsj");
69
if (version >= 2) {
24
int *test_sockets = packet_test_init(emc_module_index(td->module),
70
binfo.smp_loader_start = SMPBOOT_ADDR;
25
cmd_line);
71
- binfo.write_secondary_boot = write_smpboot;
26
QTestState *qts = qtest_init(cmd_line->str);
72
+ if (version == 2) {
27
@@ -XXX,XX +XXX,XX @@ static void test_tx(gconstpointer test_data)
73
+ binfo.write_secondary_boot = write_smpboot;
28
static void test_rx(gconstpointer test_data)
74
+ } else {
29
{
75
+ binfo.write_secondary_boot = write_smpboot64;
30
const TestData *td = test_data;
76
+ }
31
- GString *cmd_line = g_string_new("-machine quanta-gsj");
77
binfo.secondary_cpu_reset_hook = reset_secondary;
32
+ g_autoptr(GString) cmd_line = g_string_new("-machine quanta-gsj");
78
}
33
int *test_sockets = packet_test_init(emc_module_index(td->module),
79
34
cmd_line);
35
QTestState *qts = qtest_init(cmd_line->str);
80
--
36
--
81
2.16.2
37
2.34.1
82
83
diff view generated by jsdifflib
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
In socket_check_afunix_support() we call socket(PF_UNIX, SOCK_STREAM, 0)
2
just hard-code the CPU type they use rather than having it passed
2
to see if it works, but we call close() on the result whether it
3
through as an object property. This then lets us put the initialization
3
worked or not. Only close the fd if the socket() call succeeded.
4
of the CPU object in init rather than realize.
4
Spotted by Coverity.
5
5
6
Note that this change means that it's no longer possible on
6
Resolves: Coverity CID 1497481
7
the command line to use -cpu to ask for a different kind of
8
CPU than the SoC supports. This was never a supported thing to
9
do anyway; we were just not sanity-checking the command line.
10
11
This does require us to only build the bcm2837 object on
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
13
due to the missing cortex-a53 device and "make check" will fail.
14
7
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Thomas Huth <thuth@redhat.com>
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
11
Message-id: 20240312183810.557768-3-peter.maydell@linaro.org
19
---
12
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
13
tests/unit/socket-helpers.c | 4 +++-
21
hw/arm/raspi.c | 2 --
14
1 file changed, 3 insertions(+), 1 deletion(-)
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
15
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
16
diff --git a/tests/unit/socket-helpers.c b/tests/unit/socket-helpers.c
25
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
18
--- a/tests/unit/socket-helpers.c
27
+++ b/hw/arm/bcm2836.c
19
+++ b/tests/unit/socket-helpers.c
28
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ void socket_check_afunix_support(bool *has_afunix)
29
21
int fd;
30
struct BCM283XInfo {
22
31
const char *name;
23
fd = socket(PF_UNIX, SOCK_STREAM, 0);
32
+ const char *cpu_type;
24
- close(fd);
33
int clusterid;
25
34
};
26
#ifdef _WIN32
35
27
*has_afunix = (fd != (int)INVALID_SOCKET);
36
static const BCM283XInfo bcm283x_socs[] = {
28
@@ -XXX,XX +XXX,XX @@ void socket_check_afunix_support(bool *has_afunix)
37
{
29
*has_afunix = (fd >= 0);
38
.name = TYPE_BCM2836,
30
#endif
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
31
40
.clusterid = 0xf,
32
+ if (*has_afunix) {
41
},
33
+ close(fd);
42
+#ifdef TARGET_AARCH64
43
{
44
.name = TYPE_BCM2837,
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
46
.clusterid = 0x0,
47
},
48
+#endif
49
};
50
51
static void bcm2836_init(Object *obj)
52
{
53
BCM283XState *s = BCM283X(obj);
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
55
+ const BCM283XInfo *info = bc->info;
56
+ int n;
57
+
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
60
+ info->cpu_type);
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
62
+ &error_abort);
63
+ }
34
+ }
64
35
return;
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
68
69
/* common peripherals from bcm2835 */
70
71
- obj = OBJECT(dev);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
74
- s->cpu_type);
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
36
}
84
85
static Property bcm2836_props[] = {
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
37
--
104
2.16.2
38
2.34.1
105
106
diff view generated by jsdifflib
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
In net_init_af_xdp() we parse the arguments and allocate
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
2
a buffer of ints into sock_fds. However, although we
3
is required for Linux to boot.
3
free this in the error exit path, we don't ever free it
4
in the successful return path. Coverity spots this leak.
4
5
6
Switch to g_autofree so we don't need to manually free the
7
array.
8
9
Resolves: Coverity CID 1534906
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
13
Message-id: 20240312183810.557768-4-peter.maydell@linaro.org
9
---
14
---
10
hw/arm/bcm2836.c | 11 +++++++----
15
net/af-xdp.c | 3 +--
11
1 file changed, 7 insertions(+), 4 deletions(-)
16
1 file changed, 1 insertion(+), 2 deletions(-)
12
17
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
18
diff --git a/net/af-xdp.c b/net/af-xdp.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
20
--- a/net/af-xdp.c
16
+++ b/hw/arm/bcm2836.c
21
+++ b/net/af-xdp.c
17
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ int net_init_af_xdp(const Netdev *netdev,
18
23
NetClientState *nc, *nc0 = NULL;
19
struct BCM283XInfo {
24
unsigned int ifindex;
20
const char *name;
25
uint32_t prog_id = 0;
21
+ int clusterid;
26
- int *sock_fds = NULL;
22
};
27
+ g_autofree int *sock_fds = NULL;
23
28
int64_t i, queues;
24
static const BCM283XInfo bcm283x_socs[] = {
25
{
26
.name = TYPE_BCM2836,
27
+ .clusterid = 0xf,
28
},
29
{
30
.name = TYPE_BCM2837,
31
+ .clusterid = 0x0,
32
},
33
};
34
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
37
{
38
BCM283XState *s = BCM283X(dev);
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
40
+ const BCM283XInfo *info = bc->info;
41
Object *obj;
42
Error *err = NULL;
29
Error *err = NULL;
43
int n;
30
AFXDPState *s;
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
31
@@ -XXX,XX +XXX,XX @@ int net_init_af_xdp(const Netdev *netdev,
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
32
return 0;
46
33
47
for (n = 0; n < BCM283X_NCPUS; n++) {
34
err:
48
- /* Mirror bcm2836, which has clusterid set to 0xf
35
- g_free(sock_fds);
49
- * TODO: this should be converted to a property of ARM_CPU
36
if (nc0) {
50
- */
37
qemu_del_net_client(nc0);
51
- s->cpus[n].mp_affinity = 0xF00 | n;
38
}
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
39
--
58
2.16.2
40
2.34.1
59
60
diff view generated by jsdifflib
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
In pca9554_get_pin() and pca9554_set_pin(), we try to detect an
2
some differences. Notably, the MPIDR affinity aff1 values it
2
incorrect pin value, but we get the condition wrong, using ">"
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
3
when ">=" was intended.
4
uses, and if this is wrong Linux will not boot.
5
4
6
Rather than trying to have one device with properties that
5
This has no actual effect, because in pca9554_initfn() we
7
configure it differently for the two cases, create two
6
use the correct test when creating the properties and so
8
separate QOM devices for the two SoCs. We use the same approach
7
we'll never be called with an out of range value. However,
9
as hw/arm/aspeed_soc.c and share code and have a data table
8
Coverity complains about the mismatch between the check and
10
that might differ per-SoC. For the moment the two types don't
9
the later use of the pin value in a shift operation.
11
actually have different behaviour.
12
10
11
Use the correct condition.
12
13
Resolves: Coverity CID 1534917
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240312183810.557768-5-peter.maydell@linaro.org
16
---
18
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
19
hw/misc/pca9554.c | 4 ++--
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
20
1 file changed, 2 insertions(+), 2 deletions(-)
19
hw/arm/raspi.c | 3 ++-
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
21
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
22
diff --git a/hw/misc/pca9554.c b/hw/misc/pca9554.c
23
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
24
--- a/hw/misc/pca9554.c
25
+++ b/include/hw/arm/bcm2836.h
25
+++ b/hw/misc/pca9554.c
26
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ static void pca9554_get_pin(Object *obj, Visitor *v, const char *name,
27
27
error_setg(errp, "%s: error reading %s", __func__, name);
28
#define BCM283X_NCPUS 4
28
return;
29
29
}
30
+/* These type names are for specific SoCs; other than instantiating
30
- if (pin < 0 || pin > PCA9554_PIN_COUNT) {
31
+ * them, code using these devices should always handle them via the
31
+ if (pin < 0 || pin >= PCA9554_PIN_COUNT) {
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
32
error_setg(errp, "%s invalid pin %s", __func__, name);
33
+ */
33
return;
34
+#define TYPE_BCM2836 "bcm2836"
34
}
35
+#define TYPE_BCM2837 "bcm2837"
35
@@ -XXX,XX +XXX,XX @@ static void pca9554_set_pin(Object *obj, Visitor *v, const char *name,
36
+
36
error_setg(errp, "%s: error reading %s", __func__, name);
37
typedef struct BCM283XState {
37
return;
38
/*< private >*/
38
}
39
DeviceState parent_obj;
39
- if (pin < 0 || pin > PCA9554_PIN_COUNT) {
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
40
+ if (pin < 0 || pin >= PCA9554_PIN_COUNT) {
41
BCM2835PeripheralState peripherals;
41
error_setg(errp, "%s invalid pin %s", __func__, name);
42
} BCM283XState;
42
return;
43
43
}
44
+typedef struct BCM283XInfo BCM283XInfo;
45
+
46
+typedef struct BCM283XClass {
47
+ DeviceClass parent_class;
48
+ const BCM283XInfo *info;
49
+} BCM283XClass;
50
+
51
+#define BCM283X_CLASS(klass) \
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
53
+#define BCM283X_GET_CLASS(obj) \
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
55
+
56
#endif /* BCM2836_H */
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/bcm2836.c
60
+++ b/hw/arm/bcm2836.c
61
@@ -XXX,XX +XXX,XX @@
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
63
#define BCM2836_CONTROL_BASE 0x40000000
64
65
+struct BCM283XInfo {
66
+ const char *name;
67
+};
68
+
69
+static const BCM283XInfo bcm283x_socs[] = {
70
+ {
71
+ .name = TYPE_BCM2836,
72
+ },
73
+ {
74
+ .name = TYPE_BCM2837,
75
+ },
76
+};
77
+
78
static void bcm2836_init(Object *obj)
79
{
80
BCM283XState *s = BCM283X(obj);
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
82
DEFINE_PROP_END_OF_LIST()
83
};
84
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
96
97
-static const TypeInfo bcm2836_type_info = {
98
+static const TypeInfo bcm283x_type_info = {
99
.name = TYPE_BCM283X,
100
.parent = TYPE_DEVICE,
101
.instance_size = sizeof(BCM283XState),
102
.instance_init = bcm2836_init,
103
- .class_init = bcm2836_class_init,
104
+ .class_size = sizeof(BCM283XClass),
105
+ .abstract = true,
106
};
107
108
static void bcm2836_register_types(void)
109
{
110
- type_register_static(&bcm2836_type_info);
111
+ int i;
112
+
113
+ type_register_static(&bcm283x_type_info);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
115
+ TypeInfo ti = {
116
+ .name = bcm283x_socs[i].name,
117
+ .parent = TYPE_BCM283X,
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
123
}
124
125
type_init(bcm2836_register_types)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/raspi.c
129
+++ b/hw/arm/raspi.c
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
135
+ object_initialize(&s->soc, sizeof(s->soc),
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
138
&error_abort);
139
140
--
44
--
141
2.16.2
45
2.34.1
142
143
diff view generated by jsdifflib
1
Our BCM2836 type is really a generic one that can be any of
1
There's no way for the macio_nvram device to report failure to write
2
the bcm283x family. Rename it accordingly. We change only
2
data, but we can at least report it to the user with error_report()
3
the names which are visible via the header file to the
3
as we do in other devices like xlnx-efuse.
4
rest of the QEMU code, leaving private function names
5
in bcm2836.c as they are.
6
4
7
This is a preliminary to making bcm283x be an abstract
5
Spotted by Coverity.
8
parent class to specific types for the bcm2836 and bcm2837.
9
6
7
Resolves: Coverity CID 1507628
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240312183810.557768-6-peter.maydell@linaro.org
14
---
13
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
14
hw/nvram/mac_nvram.c | 5 ++++-
16
hw/arm/bcm2836.c | 17 +++++++++--------
15
1 file changed, 4 insertions(+), 1 deletion(-)
17
hw/arm/raspi.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
16
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
17
diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
19
--- a/hw/nvram/mac_nvram.c
23
+++ b/include/hw/arm/bcm2836.h
20
+++ b/hw/nvram/mac_nvram.c
24
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void macio_nvram_writeb(void *opaque, hwaddr addr,
25
#include "hw/arm/bcm2835_peripherals.h"
22
trace_macio_nvram_write(addr, value);
26
#include "hw/intc/bcm2836_control.h"
23
s->data[addr] = value;
27
24
if (s->blk) {
28
-#define TYPE_BCM2836 "bcm2836"
25
- blk_pwrite(s->blk, addr, 1, &s->data[addr], 0);
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
26
+ if (blk_pwrite(s->blk, addr, 1, &s->data[addr], 0) < 0) {
30
+#define TYPE_BCM283X "bcm283x"
27
+ error_report("%s: write of NVRAM data to backing store failed",
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
28
+ blk_name(s->blk));
32
29
+ }
33
-#define BCM2836_NCPUS 4
30
}
34
+#define BCM283X_NCPUS 4
35
36
-typedef struct BCM2836State {
37
+typedef struct BCM283XState {
38
/*< private >*/
39
DeviceState parent_obj;
40
/*< public >*/
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
42
char *cpu_type;
43
uint32_t enabled_cpus;
44
45
- ARMCPU cpus[BCM2836_NCPUS];
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
BCM2836ControlState control;
48
BCM2835PeripheralState peripherals;
49
-} BCM2836State;
50
+} BCM283XState;
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
56
+++ b/hw/arm/bcm2836.c
57
@@ -XXX,XX +XXX,XX @@
58
59
static void bcm2836_init(Object *obj)
60
{
61
- BCM2836State *s = BCM2836(obj);
62
+ BCM283XState *s = BCM283X(obj);
63
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
67
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
69
{
70
- BCM2836State *s = BCM2836(dev);
71
+ BCM283XState *s = BCM283X(dev);
72
Object *obj;
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
31
}
95
32
96
static Property bcm2836_props[] = {
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
101
+ BCM283X_NCPUS),
102
DEFINE_PROP_END_OF_LIST()
103
};
104
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
106
}
107
108
static const TypeInfo bcm2836_type_info = {
109
- .name = TYPE_BCM2836,
110
+ .name = TYPE_BCM283X,
111
.parent = TYPE_DEVICE,
112
- .instance_size = sizeof(BCM2836State),
113
+ .instance_size = sizeof(BCM283XState),
114
.instance_init = bcm2836_init,
115
.class_init = bcm2836_class_init,
116
};
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/arm/raspi.c
120
+++ b/hw/arm/raspi.c
121
@@ -XXX,XX +XXX,XX @@
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
123
124
typedef struct RasPiState {
125
- BCM2836State soc;
126
+ BCM283XState soc;
127
MemoryRegion ram;
128
} RasPiState;
129
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
165
--
33
--
166
2.16.2
34
2.34.1
167
35
168
36
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
In test_compute_wait() we do
2
double units = bkt.max / 10;
3
which does an integer division and then assigns it to a double variable,
4
and similarly later on in the expression for an assertion.
2
5
3
Code of imx_update() is slightly confusing since the "flags" variable
6
Use 10.0 so that we do a floating point division and calculate the
4
doesn't really corespond to anything in real hardware and server as a
7
exact value, rather than doing an integer division.
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
8
8
Change the code to explicitly evaluate state of interrupts reported
9
Spotted by Coverity.
9
via USR1 and USR2 against corresponding masking bits and use the to
10
detemine if IRQ line should be asserted or not.
11
10
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
11
Resolves: Coverity CID 1432564
13
reasons:
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
16
Message-id: 20240312183810.557768-7-peter.maydell@linaro.org
17
---
18
tests/unit/test-throttle.c | 4 ++--
19
1 file changed, 2 insertions(+), 2 deletions(-)
14
20
15
1. Emulation code implements a single character FIFO, so this flag
21
diff --git a/tests/unit/test-throttle.c b/tests/unit/test-throttle.c
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
34
1 file changed, 16 insertions(+), 8 deletions(-)
35
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
37
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
23
--- a/tests/unit/test-throttle.c
39
+++ b/hw/char/imx_serial.c
24
+++ b/tests/unit/test-throttle.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
25
@@ -XXX,XX +XXX,XX @@ static void test_compute_wait(void)
41
26
bkt.avg = 10;
42
static void imx_update(IMXSerialState *s)
27
bkt.max = 200;
43
{
28
for (i = 0; i < 22; i++) {
44
- uint32_t flags;
29
- double units = bkt.max / 10;
45
+ uint32_t usr1;
30
+ double units = bkt.max / 10.0;
46
+ uint32_t usr2;
31
bkt.level += units;
47
+ uint32_t mask;
32
bkt.burst_level += units;
48
33
throttle_leak_bucket(&bkt, NANOSECONDS_PER_SECOND / 10);
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
34
wait = throttle_compute_wait(&bkt);
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
35
g_assert(double_cmp(bkt.burst_level, 0));
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
36
- g_assert(double_cmp(bkt.level, (i + 1) * (bkt.max - bkt.avg) / 10));
52
- } else {
37
+ g_assert(double_cmp(bkt.level, (i + 1) * (bkt.max - bkt.avg) / 10.0));
53
- flags &= ~USR1_TRDY;
38
/* We can do bursts for the 2 seconds we have configured in
54
- }
39
* burst_length. We have 100 extra milliseconds of burst
55
+ /*
40
* because bkt.level has been leaking during this time.
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
57
+ * UCR1, so we can get away with something as simple as the
58
+ * following:
59
+ */
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
71
72
static void imx_serial_reset(IMXSerialState *s)
73
--
41
--
74
2.16.2
42
2.34.1
75
43
76
44
diff view generated by jsdifflib
Deleted patch
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
2
1
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
4
it is needed to support guests other than Linux.
5
6
Based on the patch by Bill Paul as found here:
7
https://bugs.launchpad.net/qemu/+bug/1753314
8
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Cc: Bill Paul <wpaul@windriver.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/char/imx_serial.h | 3 +++
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
26
+++ b/include/hw/char/imx_serial.h
27
@@ -XXX,XX +XXX,XX @@
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
29
#define UCR2_SRST (1<<0) /* Reset complete */
30
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
32
+
33
#define UTS1_TXEMPTY (1<<6)
34
#define UTS1_RXEMPTY (1<<5)
35
#define UTS1_TXFULL (1<<4)
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
37
uint32_t ubmr;
38
uint32_t ubrc;
39
uint32_t ucr3;
40
+ uint32_t ucr4;
41
42
qemu_irq irq;
43
CharBackend chr;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
98
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
114
2.16.2
115
116
diff view generated by jsdifflib
Deleted patch
1
For the rpi1 and 2 we want to boot the Linux kernel via some
2
custom setup code that makes sure that the SMC instruction
3
acts as a no-op, because it's used for cache maintenance.
4
The rpi3 boots AArch64 kernels, which don't need SMC for
5
cache maintenance and always expect to be booted non-secure.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
13
hw/arm/raspi.c | 17 +++++++++++++----
14
1 file changed, 13 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
21
binfo.board_id = raspi_boardid[version];
22
binfo.ram_size = ram_size;
23
binfo.nb_cpus = smp_cpus;
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
25
- binfo.write_board_setup = write_board_setup;
26
- binfo.secure_board_setup = true;
27
- binfo.secure_boot = true;
28
+
29
+ if (version <= 2) {
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
31
+ * mode before booting a kernel (to set up the SMC vectors so
32
+ * that we get a no-op SMC; this is used by Linux to call the
33
+ * firmware for some cache maintenance operations.
34
+ * The rpi3 doesn't need this.
35
+ */
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
37
+ binfo.write_board_setup = write_board_setup;
38
+ binfo.secure_board_setup = true;
39
+ binfo.secure_boot = true;
40
+ }
41
42
/* Pi2 and Pi3 requires SMP setup */
43
if (version >= 2) {
44
--
45
2.16.2
46
47
diff view generated by jsdifflib
Deleted patch
1
Add some assertions that if we're about to boot an AArch64 kernel,
2
the board code has not mistakenly set either secure_boot or
3
secure_board_setup. It doesn't make sense to set secure_boot,
4
because all AArch64 kernels must be booted in non-secure mode.
5
1
6
It might in theory make sense to set secure_board_setup, but
7
we don't currently support that, because only the AArch32
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
9
Since we don't have a current need for this functionality, just
10
assert that we don't try to use it. If it's needed we'll add
11
it later.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
16
---
17
hw/arm/boot.c | 7 +++++++
18
1 file changed, 7 insertions(+)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
+++ b/hw/arm/boot.c
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
25
} else {
26
env->pstate = PSTATE_MODE_EL1h;
27
}
28
+ /* AArch64 kernels never boot in secure mode */
29
+ assert(!info->secure_boot);
30
+ /* This hook is only supported for AArch32 currently:
31
+ * bootloader_aarch64[] will not call the hook, and
32
+ * the code above has already dropped us into EL2 or EL1.
33
+ */
34
+ assert(!info->secure_board_setup);
35
}
36
37
/* Set to non-secure if not a secure boot */
38
--
39
2.16.2
40
41
diff view generated by jsdifflib
Deleted patch
1
If we're directly booting a Linux kernel and the CPU supports both
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
4
instruction is enabled rather than UNDEFing. Otherwise at least some
5
kernels will panic when trying to initialize KVM in the guest.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
9
---
10
hw/arm/boot.c | 5 +++++
11
1 file changed, 5 insertions(+)
12
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
16
+++ b/hw/arm/boot.c
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
18
assert(!info->secure_board_setup);
19
}
20
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
23
+ env->cp15.scr_el3 |= SCR_HCE;
24
+ }
25
+
26
/* Set to non-secure if not a secure boot */
27
if (!info->secure_boot &&
28
(cs != first_cpu || !info->secure_board_setup)) {
29
--
30
2.16.2
31
32
diff view generated by jsdifflib
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
Coverity points out that g_setenv() can fail and we don't
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
2
check for this in qtest_inproc_init(). In practice this will
3
but the BCM2386State struct only defines the parent_obj field
3
only fail if a memory allocation failed in setenv() or if
4
as DeviceState. This would have caused problems if anything
4
the caller passed an invalid architecture name (e.g. one
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
5
with an '=' in it), so rather than requiring the callsite
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
6
to check for failure, make g_setenv() failure fatal here,
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
7
similarly to what we did in commit aca68d95c515.
8
provides.
9
8
9
Resolves: Coverity CID 1497485
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20240312183810.557768-8-peter.maydell@linaro.org
14
---
15
---
15
hw/arm/bcm2836.c | 2 +-
16
tests/qtest/libqtest.c | 6 +++++-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 5 insertions(+), 1 deletion(-)
17
18
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
19
diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
21
--- a/tests/qtest/libqtest.c
21
+++ b/hw/arm/bcm2836.c
22
+++ b/tests/qtest/libqtest.c
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
23
@@ -XXX,XX +XXX,XX @@ QTestState *qtest_inproc_init(QTestState **s, bool log, const char* arch,
23
24
* way, qtest_get_arch works for inproc qtest.
24
static const TypeInfo bcm2836_type_info = {
25
*/
25
.name = TYPE_BCM2836,
26
gchar *bin_path = g_strconcat("/qemu-system-", arch, NULL);
26
- .parent = TYPE_SYS_BUS_DEVICE,
27
- g_setenv("QTEST_QEMU_BINARY", bin_path, 0);
27
+ .parent = TYPE_DEVICE,
28
+ if (!g_setenv("QTEST_QEMU_BINARY", bin_path, 0)) {
28
.instance_size = sizeof(BCM2836State),
29
+ fprintf(stderr,
29
.instance_init = bcm2836_init,
30
+ "Could not set environment variable QTEST_QEMU_BINARY\n");
30
.class_init = bcm2836_class_init,
31
+ exit(1);
32
+ }
33
g_free(bin_path);
34
35
return qts;
31
--
36
--
32
2.16.2
37
2.34.1
33
38
34
39
diff view generated by jsdifflib