Hi; here's a queue of arm patches (plus a few elf2dmp changes);

mostly these are minor cleanups and bugfixes.

The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800:

Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into staging (2023-10-18 06:21:15 -0400)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231019

for you to fetch changes up to 2a052b4ee01b3c413cef2ef49cb780cde17d4ba1:

contrib/elf2dmp: Use g_malloc(), g_new() and g_free() (2023-10-19 14:32:13 +0100)

* hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder

* hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot'

* xlnx devices: remove deprecated device reset

* xlnx-bbram: hw/nvram: Use dot in device type name

* elf2dmp: fix coverity issues

* elf2dmp: convert to g_malloc, g_new and g_free

* target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0

* hw/arm: refactor virt PPI logic

* arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg

* target/arm: Permit T32 LDM with single register

* smmuv3: Advertise SMMUv3.1-XNX

* target/arm: Implement FEAT_HPMN0

* Remove some unnecessary include lines

* target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL

* hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

Chris Rauer (1):

hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

Cornelia Huck (2):

arm/kvm: convert to kvm_set_one_reg

arm/kvm: convert to kvm_get_one_reg

Leif Lindholm (3):

{include/}hw/arm: refactor virt PPI logic

include/hw/arm: move BSA definitions to bsa.h

hw/arm/sbsa-ref: use bsa.h for PPI definitions

Michal Orzel (1):

target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0

Peter Maydell (8):

target/arm: Permit T32 LDM with single register

hw/arm/smmuv3: Update ID register bit field definitions

hw/arm/smmuv3: Sort ID register setting into field order

hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature

target/arm: Implement FEAT_HPMN0

target/arm/kvm64.c: Remove unused include

target/arm/common-semi-target.h: Remove unnecessary boot.h include

target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL

From: Thomas Huth <thuth@redhat.com>

MAINTAINERS | 2 +-

include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0

hw/misc/bcm2835_property.c | 2 +-

3 files changed, 2 insertions(+), 2 deletions(-)

rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)

diff --git a/MAINTAINERS b/MAINTAINERS

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ S: Odd Fixes

F: hw/arm/raspi.c

F: hw/arm/raspi_platform.h

F: hw/*/bcm283*

-F: include/hw/arm/raspi*

+F: include/hw/arm/rasp*

F: include/hw/*/bcm283*

F: docs/system/arm/raspi.rst

diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/arm/raspberrypi-fw-defs.h

similarity index 100%

rename from include/hw/misc/raspberrypi-fw-defs.h

rename to include/hw/arm/raspberrypi-fw-defs.h

diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/bcm2835_property.c

+++ b/hw/misc/bcm2835_property.c

@@ -XXX,XX +XXX,XX @@

#include "migration/vmstate.h"

#include "hw/irq.h"

#include "hw/misc/bcm2835_mbox_defs.h"

-#include "hw/misc/raspberrypi-fw-defs.h"

+#include "hw/arm/raspberrypi-fw-defs.h"

#include "sysemu/dma.h"

#include "qemu/log.h"

#include "qemu/module.h"

2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

include/hw/arm/exynos4210.h | 2 +-

target/arm/cpu-qom.h | 2 --

2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h

--- a/include/hw/arm/exynos4210.h

+++ b/include/hw/arm/exynos4210.h

@@ -XXX,XX +XXX,XX @@

#include "hw/intc/exynos4210_gic.h"

#include "hw/intc/exynos4210_combiner.h"

#include "hw/core/split-irq.h"

-#include "target/arm/cpu-qom.h"

+#include "hw/arm/boot.h"

#include "qom/object.h"

#define EXYNOS4210_NCPUS 2

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu-qom.h

+++ b/target/arm/cpu-qom.h

@@ -XXX,XX +XXX,XX @@

#include "hw/core/cpu.h"

#include "qom/object.h"

-struct arm_boot_info;

-

#define TYPE_ARM_CPU "arm-cpu"

OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)

2.34.1

From: Tong Ho <tong.ho@amd.com>

hw/nvram/xlnx-bbram.c | 8 +++++---

1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c

--- a/hw/nvram/xlnx-bbram.c

+++ b/hw/nvram/xlnx-bbram.c

* QEMU model of the Xilinx BBRAM Battery Backed RAM

*

* Copyright (c) 2014-2021 Xilinx Inc.

+ * Copyright (c) 2023 Advanced Micro Devices, Inc.

*

* Permission is hereby granted, free of charge, to any person obtaining a copy

* of this software and associated documentation files (the "Software"), to deal

@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {

}

-static void bbram_ctrl_reset(DeviceState *dev)

+static void bbram_ctrl_reset_hold(Object *obj)

- XlnxBBRam *s = XLNX_BBRAM(dev);

+ XlnxBBRam *s = XLNX_BBRAM(obj);

unsigned int i;

for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {

@@ -XXX,XX +XXX,XX @@ static Property bbram_ctrl_props[] = {

static void bbram_ctrl_class_init(ObjectClass *klass, void *data)

{

DeviceClass *dc = DEVICE_CLASS(klass);

+ ResettableClass *rc = RESETTABLE_CLASS(klass);

- dc->reset = bbram_ctrl_reset;

+ rc->phases.hold = bbram_ctrl_reset_hold;

dc->realize = bbram_ctrl_realize;

dc->vmsd = &vmstate_bbram_ctrl;

device_class_set_props(dc, bbram_ctrl_props);

2.34.1

From: Viktor Prutyanov <viktor@daynix.com>

Index in file_size array must be checked against num_files, because the

entries we are looking for may be absent in the PDB.

Fixes: Coverity CID 1521597

Signed-off-by: Viktor Prutyanov <viktor@daynix.com>

Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20230930235317.11469-3-viktor@daynix.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

contrib/elf2dmp/pdb.c | 13 +++++++++----

1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c

--- a/contrib/elf2dmp/pdb.c

+++ b/contrib/elf2dmp/pdb.c

static uint32_t pdb_get_file_size(const struct pdb_reader *r, unsigned idx)

+ if (idx >= r->ds.toc->num_files) {

+ return 0;

+ }

return r->ds.toc->file_size[idx];

}

@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read_file(struct pdb_reader* r, uint32_t file_number)

static int pdb_init_segments(struct pdb_reader *r)

{

- char *segs;

unsigned stream_idx = r->segments;

- segs = pdb_ds_read_file(r, stream_idx);

- if (!segs) {

+ r->segs = pdb_ds_read_file(r, stream_idx);

+ if (!r->segs) {

return 1;

}

- r->segs = segs;

r->segs_size = pdb_get_file_size(r, stream_idx);

+ if (!r->segs_size) {

+ return 1;

return 0;

2.34.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.

As in, PPI0 is INTID16 .. PPI15 is INTID31.

Arm's Base System Architecture specification (BSA) lists the mandated and

recommended private interrupt IDs by INTID, not by PPI index. But current

definitions in virt define them by PPI index, complicating cross

referencing.

Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,

converting a PPI index to an INTID.

Resolve this by redefining the BSA-allocated PPIs by their INTIDs,

and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>

Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

include/hw/arm/virt.h | 14 +++++++-------

hw/arm/virt-acpi-build.c | 12 ++++++------

hw/arm/virt.c | 24 ++++++++++++++----------

3 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h

--- a/include/hw/arm/virt.h

+++ b/include/hw/arm/virt.h

@@ -XXX,XX +XXX,XX @@

#define NUM_VIRTIO_TRANSPORTS 32

#define NUM_SMMU_IRQS 4

-#define ARCH_GIC_MAINT_IRQ 9

+#define ARCH_GIC_MAINT_IRQ 25

-#define ARCH_TIMER_VIRT_IRQ 11

-#define ARCH_TIMER_S_EL1_IRQ 13

-#define ARCH_TIMER_NS_EL1_IRQ 14

-#define ARCH_TIMER_NS_EL2_IRQ 10

+#define ARCH_TIMER_VIRT_IRQ 27

+#define ARCH_TIMER_S_EL1_IRQ 29

+#define ARCH_TIMER_NS_EL1_IRQ 30

+#define ARCH_TIMER_NS_EL2_IRQ 26

-#define VIRTUAL_PMU_IRQ 7

+#define VIRTUAL_PMU_IRQ 23

-#define PPI(irq) ((irq) + 16)

+#define INTID_TO_PPI(irq) ((irq) - 16)

/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */

#define PVTIME_SIZE_PER_CPU 64

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt-acpi-build.c

+++ b/hw/arm/virt-acpi-build.c

@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

* The interrupt values are the same with the device tree when adding 16

*/

/* Secure EL1 timer GSIV */

- build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);

+ build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);

/* Secure EL1 timer Flags */

build_append_int_noprefix(table_data, irqflags, 4);

/* Non-Secure EL1 timer GSIV */

- build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);

+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);

/* Non-Secure EL1 timer Flags */

build_append_int_noprefix(table_data, irqflags |

1UL << 2, /* Always-on Capability */

4);

/* Virtual timer GSIV */

- build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);

+ build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);

/* Virtual Timer Flags */

build_append_int_noprefix(table_data, irqflags, 4);

/* Non-Secure EL2 timer GSIV */

- build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);

+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);

/* Non-Secure EL2 timer Flags */

build_append_int_noprefix(table_data, irqflags, 4);

/* CntReadBase Physical address */

@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));

uint64_t physical_base_address = 0, gich = 0, gicv = 0;

- uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;

+ uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;

uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?

- PPI(VIRTUAL_PMU_IRQ) : 0;

+ VIRTUAL_PMU_IRQ : 0;

if (vms->gic_version == VIRT_GIC_VERSION_2) {

physical_base_address = memmap[VIRT_GIC_CPU].base;

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)

}

qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);

qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",

- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,

- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,

- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,

- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);

+ GIC_FDT_IRQ_TYPE_PPI,

+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,

+ GIC_FDT_IRQ_TYPE_PPI,

+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,

+ GIC_FDT_IRQ_TYPE_PPI,

+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,

+ GIC_FDT_IRQ_TYPE_PPI,

+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);

}

static void fdt_add_cpu_nodes(const VirtMachineState *vms)

@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)

*/

for (i = 0; i < smp_cpus; i++) {

DeviceState *cpudev = DEVICE(qemu_get_cpu(i));

- int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;

+ int intidbase = NUM_IRQS + i * GIC_INTERNAL;

/* Mapping from the output timer irq lines from the CPU to the

* GIC PPI inputs we use for the virt board.

*/

@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)

for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {

qdev_connect_gpio_out(cpudev, irq,

qdev_get_gpio_in(vms->gic,

- ppibase + timer_irq[irq]));

+ intidbase + timer_irq[irq]));

}

if (vms->gic_version != VIRT_GIC_VERSION_2) {

qemu_irq irq = qdev_get_gpio_in(vms->gic,

- ppibase + ARCH_GIC_MAINT_IRQ);

+ intidbase + ARCH_GIC_MAINT_IRQ);

qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",

0, irq);

} else if (vms->virt) {

qemu_irq irq = qdev_get_gpio_in(vms->gic,

- ppibase + ARCH_GIC_MAINT_IRQ);

+ intidbase + ARCH_GIC_MAINT_IRQ);

sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);

}

qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,

- qdev_get_gpio_in(vms->gic, ppibase

+ qdev_get_gpio_in(vms->gic, intidbase

+ VIRTUAL_PMU_IRQ));

sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));

@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)

if (pmu) {

assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));

if (kvm_irqchip_in_kernel()) {

- kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));

+ kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);

}

kvm_arm_pmu_init(cpu);

2.34.1

From: Cornelia Huck <cohuck@redhat.com>

We can neaten the code by switching to the kvm_set_one_reg function.

Reviewed-by: Gavin Shan <gshan@redhat.com>

Signed-off-by: Cornelia Huck <cohuck@redhat.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20231010142453.224369-2-cohuck@redhat.com

target/arm/kvm.c | 13 +++------

target/arm/kvm64.c | 66 +++++++++++++---------------------------------

2 files changed, 21 insertions(+), 58 deletions(-)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c

--- a/target/arm/kvm.c

+++ b/target/arm/kvm.c

@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)

bool ok = true;

for (i = 0; i < cpu->cpreg_array_len; i++) {

- struct kvm_one_reg r;

uint64_t regidx = cpu->cpreg_indexes[i];

uint32_t v32;

int ret;

@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)

continue;

}

- r.id = regidx;

switch (regidx & KVM_REG_SIZE_MASK) {

case KVM_REG_SIZE_U32:

v32 = cpu->cpreg_values[i];

- r.addr = (uintptr_t)&v32;

+ ret = kvm_set_one_reg(cs, regidx, &v32);

break;

case KVM_REG_SIZE_U64:

- r.addr = (uintptr_t)(cpu->cpreg_values + i);

+ ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i);

break;

default:

g_assert_not_reached();

}

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);

if (ret) {

/* We might fail for "unknown register" and also for

* "you tried to set a register which is constant with

@@ -XXX,XX +XXX,XX @@ void kvm_arm_get_virtual_time(CPUState *cs)

void kvm_arm_put_virtual_time(CPUState *cs)

{

ARMCPU *cpu = ARM_CPU(cs);

- struct kvm_one_reg reg = {

- .id = KVM_REG_ARM_TIMER_CNT,

- .addr = (uintptr_t)&cpu->kvm_vtime,

- };

int ret;

if (!cpu->kvm_vtime_dirty) {

return;

}

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);

if (ret) {

error_report("Failed to set KVM_REG_ARM_TIMER_CNT");

abort();

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm64.c

+++ b/target/arm/kvm64.c

@@ -XXX,XX +XXX,XX @@ static int kvm_arm_sve_set_vls(CPUState *cs)

{

ARMCPU *cpu = ARM_CPU(cs);

uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };

- struct kvm_one_reg reg = {

- .id = KVM_REG_ARM64_SVE_VLS,

- .addr = (uint64_t)&vls[0],

- };

assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);

- return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]);

#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5

@@ -XXX,XX +XXX,XX @@ static void kvm_inject_arm_sea(CPUState *c)

static int kvm_arch_put_fpsimd(CPUState *cs)

{

CPUARMState *env = &ARM_CPU(cs)->env;

- struct kvm_one_reg reg;

int i, ret;

for (i = 0; i < 32; i++) {

uint64_t *q = aa64_vfp_qreg(env, i);

#if HOST_BIG_ENDIAN

uint64_t fp_val[2] = { q[1], q[0] };

- reg.addr = (uintptr_t)fp_val;

+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]),

+ fp_val);

#else

- reg.addr = (uintptr_t)q;

+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);

#endif

- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)

CPUARMState *env = &cpu->env;

uint64_t tmp[ARM_MAX_VQ * 2];

uint64_t *r;

- struct kvm_one_reg reg;

int n, ret;

for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {

r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);

- reg.addr = (uintptr_t)r;

- reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)

for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {

r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],

DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));

- reg.addr = (uintptr_t)r;

- reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)

r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],

DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));

- reg.addr = (uintptr_t)r;

- reg.id = KVM_REG_ARM64_SVE_FFR(0);

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)

int kvm_arch_put_registers(CPUState *cs, int level)

{

- struct kvm_one_reg reg;

uint64_t val;

uint32_t fpr;

int i, ret;

@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)

}

for (i = 0; i < 31; i++) {

- reg.id = AARCH64_CORE_REG(regs.regs[i]);

- reg.addr = (uintptr_t) &env->xregs[i];

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),

+ &env->xregs[i]);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)

*/

aarch64_save_sp(env, 1);

- reg.id = AARCH64_CORE_REG(regs.sp);

- reg.addr = (uintptr_t) &env->sp_el[0];

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);

if (ret) {

return ret;

}

- reg.id = AARCH64_CORE_REG(sp_el1);

- reg.addr = (uintptr_t) &env->sp_el[1];

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)

} else {

val = cpsr_read(env);

}

- reg.id = AARCH64_CORE_REG(regs.pstate);

- reg.addr = (uintptr_t) &val;

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);

if (ret) {

return ret;

}

- reg.id = AARCH64_CORE_REG(regs.pc);

- reg.addr = (uintptr_t) &env->pc;

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);

if (ret) {

return ret;

}

- reg.id = AARCH64_CORE_REG(elr_el1);

- reg.addr = (uintptr_t) &env->elr_el[1];

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)

/* KVM 0-4 map to QEMU banks 1-5 */

for (i = 0; i < KVM_NR_SPSR; i++) {

- reg.id = AARCH64_CORE_REG(spsr[i]);

- reg.addr = (uintptr_t) &env->banked_spsr[i + 1];

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]),

+ &env->banked_spsr[i + 1]);

if (ret) {

return ret;

}

@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)

return ret;

}

- reg.addr = (uintptr_t)(&fpr);

fpr = vfp_get_fpsr(env);

- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);

- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);