Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[PULL 00/21] target-arm queue
-Arm patch queue -- these are all bug fix patches but we might
+The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
 as well put them in to rc0...
-thanks
+  Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)
 -- PMM
 The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306
-for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
+for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
-  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
+  hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * fsl-imx6: Fix incorrect Ethernet interrupt defines
+ * allwinner-h3: Fix I2C controller model for Sun6i SoCs
- * dump: Update correct kdump phys_base field for AArch64
+ * allwinner-h3: Add missing i2c controllers
- * char: i.MX: Add support for "TX complete" interrupt
+ * Expose M-profile system registers to gdbstub
- * bcm2836/raspi: Fix various bugs resulting in panics trying
+ * Expose pauth information to gdbstub
-   to boot a Debian Linux kernel on raspi3
+ * Support direct boot for Linux/arm64 EFI zboot images
  * Fix incorrect stage 2 MMU setup validation
 ----------------------------------------------------------------
-Andrey Smirnov (2):
+Ard Biesheuvel (1):
-      char: i.MX: Simplify imx_update()
+      hw: arm: Support direct boot for Linux/arm64 EFI zboot images
       char: i.MX: Add support for "TX complete" interrupt
-Guenter Roeck (1):
+David Reiss (2):
-      fsl-imx6: Swap Ethernet interrupt defines
+      target/arm: Export arm_v7m_mrs_control
       target/arm: Export arm_v7m_get_sp_ptr
-Peter Maydell (9):
+Richard Henderson (16):
-      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+      target/arm: Normalize aarch64 gdbstub get/set function names
-      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+      target/arm: Unexport arm_gen_dynamic_sysreg_xml
-      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+      target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
-      hw/arm/bcm2386: Fix parent type of bcm2386
+      target/arm: Split out output_vector_union_type
-      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+      target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
-      hw/arm/bcm2836: Create proper bcm2837 device
+      target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
-      hw/arm/bcm2836: Use correct affinity values for BCM2837
+      target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
-      hw/arm/bcm2836: Hardcode correct CPU type
+      target/arm: Add name argument to output_vector_union_type
-      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
+      target/arm: Simplify iteration over bit widths
       target/arm: Create pauth_ptr_mask
       target/arm: Implement gdbstub pauth extension
       target/arm: Implement gdbstub m-profile systemreg and secext
       target/arm: Handle m-profile in arm_is_secure
       target/arm: Stub arm_hcr_el2_eff for m-profile
       target/arm: Diagnose incorrect usage of arm_is_secure subroutines
       target/arm: Rewrite check_s2_mmu_setup
-Wei Huang (1):
+qianfan Zhao (2):
-      dump: Update correct kdump phys_base field for AArch64
+      hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
       hw: arm: allwinner-h3: Fix and complete H3 i2c devices
- include/hw/arm/bcm2836.h     | 31 +++++++++++++---
+ configs/targets/aarch64-linux-user.mak    |   2 +-
- include/hw/arm/fsl-imx6.h    |  4 +-
+ configs/targets/aarch64-softmmu.mak       |   2 +-
- include/hw/char/imx_serial.h |  3 ++
+ configs/targets/aarch64_be-linux-user.mak |   2 +-
- dump.c                       | 14 +++++--
+ include/hw/arm/allwinner-h3.h             |   6 +
- hw/arm/bcm2836.c             | 87 +++++++++++++++++++++++++++++++-------------
+ include/hw/i2c/allwinner-i2c.h            |   6 +
- hw/arm/boot.c                | 12 ++++++
+ include/hw/loader.h                       |  19 ++
- hw/arm/raspi.c               | 77 +++++++++++++++++++++++++++++++--------
+ target/arm/cpu.h                          |  17 +-
- hw/char/imx_serial.c         | 44 ++++++++++++++++------
+ target/arm/internals.h                    |  34 +++-
- hw/net/imx_fec.c             | 28 +++++++++++++-
+ hw/arm/allwinner-h3.c                     |  29 +++-
-files changed, 237 insertions(+), 63 deletions(-)
+ hw/arm/boot.c                             |   6 +
+ hw/core/loader.c                          |  91 ++++++++++
  hw/i2c/allwinner-i2c.c                    |  26 ++-
  target/arm/gdbstub.c                      | 278 ++++++++++++++++++------------
  target/arm/gdbstub64.c                    | 175 ++++++++++++++++++-
  target/arm/helper.c                       |   3 +
  target/arm/ptw.c                          | 173 +++++++++++--------
  target/arm/tcg/m_helper.c                 |  90 +++++-----
  target/arm/tcg/pauth_helper.c             |  26 ++-
  gdb-xml/aarch64-pauth.xml                 |  15 ++
 files changed, 742 insertions(+), 258 deletions(-)
  create mode 100644 gdb-xml/aarch64-pauth.xml

-[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
+[PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names
-The bcm2837 is pretty similar to the bcm2836, but it does have
+From: Richard Henderson <richard.henderson@linaro.org>
 some differences. Notably, the MPIDR affinity aff1 values it
 sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
 uses, and if this is wrong Linux will not boot.
-Rather than trying to have one device with properties that
+Make the form of the function names between fp and sve the same:
-configure it differently for the two cases, create two
+  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
-separate QOM devices for the two SoCs. We use the same approach
+  - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
 as hw/arm/aspeed_soc.c and share code and have a data table
 that might differ per-SoC. For the moment the two types don't
 actually have different behaviour.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
+ target/arm/internals.h | 8 ++++----
- hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
+ target/arm/gdbstub.c   | 9 +++++----
- hw/arm/raspi.c           |  3 ++-
+ target/arm/gdbstub64.c | 8 ++++----
-files changed, 53 insertions(+), 6 deletions(-)
+files changed, 13 insertions(+), 12 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/target/arm/internals.h
-+++ b/include/hw/arm/bcm2836.h
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
+ }
- #define BCM283X_NCPUS 4
+ #ifdef TARGET_AARCH64
-+/* These type names are for specific SoCs; other than instantiating
+-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
-+ * them, code using these devices should always handle them via the
+-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
-+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-+ */
+-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
-+#define TYPE_BCM2836 "bcm2836"
++int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
-+#define TYPE_BCM2837 "bcm2837"
++int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
-+
++int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
- typedef struct BCM283XState {
++int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
-     /*< private >*/
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
-     DeviceState parent_obj;
+ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
+ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
-     BCM2835PeripheralState peripherals;
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
  } BCM283XState;
 +typedef struct BCM283XInfo BCM283XInfo;
 +
 +typedef struct BCM283XClass {
 +    DeviceClass parent_class;
 +    const BCM283XInfo *info;
 +} BCM283XClass;
 +
 +#define BCM283X_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
 +#define BCM283X_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
 +
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/gdbstub.c
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
- /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
+          */
- #define BCM2836_CONTROL_BASE    0x40000000
+ #ifdef TARGET_AARCH64
+         if (isar_feature_aa64_sve(&cpu->isar)) {
-+struct BCM283XInfo {
+-            gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
-+    const char *name;
+-                                     arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
-+};
++            int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
-+
++            gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
-+static const BCM283XInfo bcm283x_socs[] = {
++                                     aarch64_gdb_set_sve_reg, nreg,
-+    {
+                                      "sve-registers.xml", 0);
-+        .name = TYPE_BCM2836,
+         } else {
-+    },
+-            gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
-+    {
+-                                     aarch64_fpu_gdb_set_reg,
-+        .name = TYPE_BCM2837,
++            gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
-+    },
++                                     aarch64_gdb_set_fpu_reg,
-+};
+, "aarch64-fpu.xml", 0);
-+
+         }
- static void bcm2836_init(Object *obj)
+ #endif
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub64.c
 +++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
      return 0;
  }
 -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
 +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
  {
-     BCM283XState *s = BCM283X(obj);
+     switch (reg) {
-@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
+     case 0 ... 31:
-     DEFINE_PROP_END_OF_LIST()
+@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
- };
+     }
+ }
--static void bcm2836_class_init(ObjectClass *oc, void *data)
-+static void bcm283x_class_init(ObjectClass *oc, void *data)
+-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
  {
-     DeviceClass *dc = DEVICE_CLASS(oc);
+     switch (reg) {
-+    BCM283XClass *bc = BCM283X_CLASS(oc);
+     case 0 ... 31:
+@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
--    dc->props = bcm2836_props;
+     }
 +    bc->info = data;
      dc->realize = bcm2836_realize;
 +    dc->props = bcm2836_props;
  }
--static const TypeInfo bcm2836_type_info = {
+-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
-+static const TypeInfo bcm283x_type_info = {
++int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
      .name = TYPE_BCM283X,
      .parent = TYPE_DEVICE,
      .instance_size = sizeof(BCM283XState),
      .instance_init = bcm2836_init,
 -    .class_init = bcm2836_class_init,
 +    .class_size = sizeof(BCM283XClass),
 +    .abstract = true,
  };
  static void bcm2836_register_types(void)
  {
--    type_register_static(&bcm2836_type_info);
+     ARMCPU *cpu = env_archcpu(env);
-+    int i;
-+
+@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
-+    type_register_static(&bcm283x_type_info);
+     return 0;
 +    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
 +        TypeInfo ti = {
 +            .name = bcm283x_socs[i].name,
 +            .parent = TYPE_BCM283X,
 +            .class_init = bcm283x_class_init,
 +            .class_data = (void *) &bcm283x_socs[i],
 +        };
 +        type_register(&ti);
 +    }
  }
- type_init(bcm2836_register_types)
+-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
++int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/hw/arm/raspi.c
+     ARMCPU *cpu = env_archcpu(env);
 +++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
      BusState *bus;
      DeviceState *carddev;
 -    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
 +    object_initialize(&s->soc, sizeof(s->soc),
 +                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
      object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                                &error_abort);
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
+[PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml
-The TypeInfo and state struct for bcm2386 disagree about what the
+From: Richard Henderson <richard.henderson@linaro.org>
 parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
 but the BCM2386State struct only defines the parent_obj field
 as DeviceState. This would have caused problems if anything
 actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
 Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
 need any of the additional functionality TYPE_SYS_BUS_DEVICE
 provides.
+This function is not used outside gdbstub.c.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 2 +-
+ target/arm/cpu.h     | 1 -
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/gdbstub.c | 2 +-
 files changed, 1 insertion(+), 2 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/cpu.h
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+  * Helpers to dynamically generates XML descriptions of the sysregs
- static const TypeInfo bcm2836_type_info = {
+  * and SVE registers. Returns the number of registers in each set.
-     .name = TYPE_BCM2836,
+  */
--    .parent = TYPE_SYS_BUS_DEVICE,
+-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
-+    .parent = TYPE_DEVICE,
+ int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
-     .instance_size = sizeof(BCM2836State),
-     .instance_init = bcm2836_init,
+ /* Returns the dynamically generated XML for the gdb stub.
-     .class_init = bcm2836_class_init,
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
      }
  }
 -int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
 +static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
  {
      ARMCPU *cpu = ARM_CPU(cs);
      GString *s = g_string_new(NULL);
 --
-.16.2
+.34.1

-New patch
+[PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
+From: Richard Henderson <richard.henderson@linaro.org>
 The function is only used for aarch64, so move it to the
 file that has the other aarch64 gdbstub stuff.  Move the
 declaration to internals.h.
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h       |   6 ---
  target/arm/internals.h |   1 +
  target/arm/gdbstub.c   | 120 -----------------------------------------
  target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
 files changed, 119 insertions(+), 126 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
  int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 -/*
 - * Helpers to dynamically generates XML descriptions of the sysregs
 - * and SVE registers. Returns the number of registers in each set.
 - */
 -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 -
  /* Returns the dynamically generated XML for the gdb stub.
   * Returns a pointer to the XML contents for the specified XML file or NULL
   * if the XML name doesn't match the predefined one.
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
  }
  #ifdef TARGET_AARCH64
 +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
  int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
  int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
  int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
      return cpu->dyn_sysreg_xml.num;
  }
 -struct TypeSize {
 -    const char *gdb_type;
 -    int  size;
 -    const char sz, suffix;
 -};
 -
 -static const struct TypeSize vec_lanes[] = {
 -    /* quads */
 -    { "uint128", 128, 'q', 'u' },
 -    { "int128", 128, 'q', 's' },
 -    /* 64 bit */
 -    { "ieee_double", 64, 'd', 'f' },
 -    { "uint64", 64, 'd', 'u' },
 -    { "int64", 64, 'd', 's' },
 -    /* 32 bit */
 -    { "ieee_single", 32, 's', 'f' },
 -    { "uint32", 32, 's', 'u' },
 -    { "int32", 32, 's', 's' },
 -    /* 16 bit */
 -    { "ieee_half", 16, 'h', 'f' },
 -    { "uint16", 16, 'h', 'u' },
 -    { "int16", 16, 'h', 's' },
 -    /* bytes */
 -    { "uint8", 8, 'b', 'u' },
 -    { "int8", 8, 'b', 's' },
 -};
 -
 -
 -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 -{
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    GString *s = g_string_new(NULL);
 -    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 -    g_autoptr(GString) ts = g_string_new("");
 -    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 -    info->num = 0;
 -    g_string_printf(s, "<?xml version=\"1.0\"?>");
 -    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 -    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 -
 -    /* First define types and totals in a whole VL */
 -    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 -        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
 -        g_string_append_printf(s,
 -                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 -                               ts->str, vec_lanes[i].gdb_type, count);
 -    }
 -    /*
 -     * Now define a union for each size group containing unsigned and
 -     * signed and potentially float versions of each size from 128 to
 -     * 8 bits.
 -     */
 -    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 -        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
 -            if (vec_lanes[j].size == bits) {
 -                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 -                                       vec_lanes[j].suffix,
 -                                       vec_lanes[j].sz, vec_lanes[j].suffix);
 -            }
 -        }
 -        g_string_append(s, "</union>");
 -    }
 -    /* And now the final union of unions */
 -    g_string_append(s, "<union id=\"svev\">");
 -    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 -                               suf[i], suf[i]);
 -    }
 -    g_string_append(s, "</union>");
 -
 -    /* Finally the sve prefix type */
 -    g_string_append_printf(s,
 -                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
 -                           reg_width / 8);
 -
 -    /* Then define each register in parts for each vq */
 -    for (i = 0; i < 32; i++) {
 -        g_string_append_printf(s,
 -                               "<reg name=\"z%d\" bitsize=\"%d\""
 -                               " regnum=\"%d\" type=\"svev\"/>",
 -                               i, reg_width, base_reg++);
 -        info->num++;
 -    }
 -    /* fpscr & status registers */
 -    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 -                           " regnum=\"%d\" group=\"float\""
 -                           " type=\"int\"/>", base_reg++);
 -    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 -                           " regnum=\"%d\" group=\"float\""
 -                           " type=\"int\"/>", base_reg++);
 -    info->num += 2;
 -
 -    for (i = 0; i < 16; i++) {
 -        g_string_append_printf(s,
 -                               "<reg name=\"p%d\" bitsize=\"%d\""
 -                               " regnum=\"%d\" type=\"svep\"/>",
 -                               i, cpu->sve_max_vq * 16, base_reg++);
 -        info->num++;
 -    }
 -    g_string_append_printf(s,
 -                           "<reg name=\"ffr\" bitsize=\"%d\""
 -                           " regnum=\"%d\" group=\"vector\""
 -                           " type=\"svep\"/>",
 -                           cpu->sve_max_vq * 16, base_reg++);
 -    g_string_append_printf(s,
 -                           "<reg name=\"vg\" bitsize=\"64\""
 -                           " regnum=\"%d\" type=\"int\"/>",
 -                           base_reg++);
 -    info->num += 2;
 -    g_string_append_printf(s, "</feature>");
 -    cpu->dyn_svereg_xml.desc = g_string_free(s, false);
 -
 -    return cpu->dyn_svereg_xml.num;
 -}
 -
 -
  const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
  {
      ARMCPU *cpu = ARM_CPU(cs);
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub64.c
 +++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
      return 0;
  }
 +
 +struct TypeSize {
 +    const char *gdb_type;
 +    short size;
 +    char sz, suffix;
 +};
 +
 +static const struct TypeSize vec_lanes[] = {
 +    /* quads */
 +    { "uint128", 128, 'q', 'u' },
 +    { "int128", 128, 'q', 's' },
 +    /* 64 bit */
 +    { "ieee_double", 64, 'd', 'f' },
 +    { "uint64", 64, 'd', 'u' },
 +    { "int64", 64, 'd', 's' },
 +    /* 32 bit */
 +    { "ieee_single", 32, 's', 'f' },
 +    { "uint32", 32, 's', 'u' },
 +    { "int32", 32, 's', 's' },
 +    /* 16 bit */
 +    { "ieee_half", 16, 'h', 'f' },
 +    { "uint16", 16, 'h', 'u' },
 +    { "int16", 16, 'h', 's' },
 +    /* bytes */
 +    { "uint8", 8, 'b', 'u' },
 +    { "int8", 8, 'b', 's' },
 +};
 +
 +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    GString *s = g_string_new(NULL);
 +    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 +    g_autoptr(GString) ts = g_string_new("");
 +    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 +    info->num = 0;
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 +
 +    /* First define types and totals in a whole VL */
 +    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 +        int count = reg_width / vec_lanes[i].size;
 +        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
 +        g_string_append_printf(s,
 +                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 +                               ts->str, vec_lanes[i].gdb_type, count);
 +    }
 +    /*
 +     * Now define a union for each size group containing unsigned and
 +     * signed and potentially float versions of each size from 128 to
 +     * 8 bits.
 +     */
 +    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 +        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 +        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 +        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
 +            if (vec_lanes[j].size == bits) {
 +                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 +                                       vec_lanes[j].suffix,
 +                                       vec_lanes[j].sz, vec_lanes[j].suffix);
 +            }
 +        }
 +        g_string_append(s, "</union>");
 +    }
 +    /* And now the final union of unions */
 +    g_string_append(s, "<union id=\"svev\">");
 +    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 +        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 +        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 +                               suf[i], suf[i]);
 +    }
 +    g_string_append(s, "</union>");
 +
 +    /* Finally the sve prefix type */
 +    g_string_append_printf(s,
 +                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
 +                           reg_width / 8);
 +
 +    /* Then define each register in parts for each vq */
 +    for (i = 0; i < 32; i++) {
 +        g_string_append_printf(s,
 +                               "<reg name=\"z%d\" bitsize=\"%d\""
 +                               " regnum=\"%d\" type=\"svev\"/>",
 +                               i, reg_width, base_reg++);
 +        info->num++;
 +    }
 +    /* fpscr & status registers */
 +    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 +                           " regnum=\"%d\" group=\"float\""
 +                           " type=\"int\"/>", base_reg++);
 +    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 +                           " regnum=\"%d\" group=\"float\""
 +                           " type=\"int\"/>", base_reg++);
 +    info->num += 2;
 +
 +    for (i = 0; i < 16; i++) {
 +        g_string_append_printf(s,
 +                               "<reg name=\"p%d\" bitsize=\"%d\""
 +                               " regnum=\"%d\" type=\"svep\"/>",
 +                               i, cpu->sve_max_vq * 16, base_reg++);
 +        info->num++;
 +    }
 +    g_string_append_printf(s,
 +                           "<reg name=\"ffr\" bitsize=\"%d\""
 +                           " regnum=\"%d\" group=\"vector\""
 +                           " type=\"svep\"/>",
 +                           cpu->sve_max_vq * 16, base_reg++);
 +    g_string_append_printf(s,
 +                           "<reg name=\"vg\" bitsize=\"64\""
 +                           " regnum=\"%d\" type=\"int\"/>",
 +                           base_reg++);
 +    info->num += 2;
 +    g_string_append_printf(s, "</feature>");
 +    info->desc = g_string_free(s, false);
 +
 +    return info->num;
 +}
 --
 .34.1

-[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
+[PULL 04/21] target/arm: Split out output_vector_union_type
-The raspi3 has AArch64 CPUs, which means that our smpboot
+From: Richard Henderson <richard.henderson@linaro.org>
 code for keeping the secondary CPUs in a pen needs to have
 a version for A64 as well as A32. Without this, the
 secondary CPUs go into an infinite loop of taking undefined
 instruction exceptions.
+Create a subroutine for creating the union of unions
+of the various type sizes that a vector may contain.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
+ target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
-file changed, 40 insertions(+), 1 deletion(-)
+file changed, 45 insertions(+), 38 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/arm/raspi.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
- #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
+     return 0;
  #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
  #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
 +#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
  /* Table of Linux board IDs for different Pi versions */
  static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                         info->smp_loader_start);
  }
-+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+-struct TypeSize {
-+{
+-    const char *gdb_type;
-+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+-    short size;
-+     * The mechanism for doing the spin-table is also entirely different.
+-    char sz, suffix;
-+     * We must have four 64-bit fields at absolute addresses
+-};
-+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+-
-+     * our CPUs, and which we must ensure are zero initialized before
+-static const struct TypeSize vec_lanes[] = {
-+     * the primary CPU goes into the kernel. We put these variables inside
+-    /* quads */
-+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+-    { "uint128", 128, 'q', 'u' },
-+     */
+-    { "int128", 128, 'q', 's' },
-+    static const uint32_t smpboot[] = {
+-    /* 64 bit */
-+        0xd2801b05, /*        mov     x5, 0xd8 */
+-    { "ieee_double", 64, 'd', 'f' },
-+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+-    { "uint64", 64, 'd', 'u' },
-+        0x924004c6, /*        and     x6, x6, #0x3 */
+-    { "int64", 64, 'd', 's' },
-+        0xd503205f, /* spin:  wfe */
+-    /* 32 bit */
-+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+-    { "ieee_single", 32, 's', 'f' },
-+        0xb4ffffc4, /*        cbz     x4, spin */
+-    { "uint32", 32, 's', 'u' },
-+        0xd2800000, /*        mov     x0, #0x0 */
+-    { "int32", 32, 's', 's' },
-+        0xd2800001, /*        mov     x1, #0x0 */
+-    /* 16 bit */
-+        0xd2800002, /*        mov     x2, #0x0 */
+-    { "ieee_half", 16, 'h', 'f' },
-+        0xd2800003, /*        mov     x3, #0x0 */
+-    { "uint16", 16, 'h', 'u' },
-+        0xd61f0080, /*        br      x4 */
+-    { "int16", 16, 'h', 's' },
 -    /* bytes */
 -    { "uint8", 8, 'b', 'u' },
 -    { "int8", 8, 'b', 's' },
 -};
 -
 -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 +static void output_vector_union_type(GString *s, int reg_width)
  {
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    GString *s = g_string_new(NULL);
 -    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 +    struct TypeSize {
 +        const char *gdb_type;
 +        short size;
 +        char sz, suffix;
 +    };
 +
-+    static const uint64_t spintables[] = {
++    static const struct TypeSize vec_lanes[] = {
-+        0, 0, 0, 0
++        /* quads */
 +        { "uint128", 128, 'q', 'u' },
 +        { "int128", 128, 'q', 's' },
 +        /* 64 bit */
 +        { "ieee_double", 64, 'd', 'f' },
 +        { "uint64", 64, 'd', 'u' },
 +        { "int64", 64, 'd', 's' },
 +        /* 32 bit */
 +        { "ieee_single", 32, 's', 'f' },
 +        { "uint32", 32, 's', 'u' },
 +        { "int32", 32, 's', 's' },
 +        /* 16 bit */
 +        { "ieee_half", 16, 'h', 'f' },
 +        { "uint16", 16, 'h', 'u' },
 +        { "int16", 16, 'h', 's' },
 +        /* bytes */
 +        { "uint8", 8, 'b', 'u' },
 +        { "int8", 8, 'b', 's' },
 +    };
 +
-+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
++    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-+                       info->smp_loader_start);
++
-+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+     g_autoptr(GString) ts = g_string_new("");
-+                       SPINTABLE_ADDR);
+-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 -    info->num = 0;
 -    g_string_printf(s, "<?xml version=\"1.0\"?>");
 -    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 -    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 +    int i, j, bits;
      /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
       * 8 bits.
       */
      for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
          g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
          for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
              if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
      /* And now the final union of unions */
      g_string_append(s, "<union id=\"svev\">");
      for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
          g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
                                 suf[i], suf[i]);
      }
      g_string_append(s, "</union>");
 +}
 +
- static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
++int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
- {
++{
-     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
++    ARMCPU *cpu = ARM_CPU(cs);
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
++    GString *s = g_string_new(NULL);
-     /* Pi2 and Pi3 requires SMP setup */
++    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-     if (version >= 2) {
++    int i, reg_width = (cpu->sve_max_vq * 128);
-         binfo.smp_loader_start = SMPBOOT_ADDR;
++    info->num = 0;
--        binfo.write_secondary_boot = write_smpboot;
++    g_string_printf(s, "<?xml version=\"1.0\"?>");
-+        if (version == 2) {
++    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-+            binfo.write_secondary_boot = write_smpboot;
++    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
-+        } else {
++
-+            binfo.write_secondary_boot = write_smpboot64;
++    output_vector_union_type(s, reg_width);
-+        }
-         binfo.secondary_cpu_reset_hook = reset_secondary;
+     /* Finally the sve prefix type */
-     }
+     g_string_append_printf(s,
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
-If we're directly booting a Linux kernel and the CPU supports both
+From: Richard Henderson <richard.henderson@linaro.org>
 EL3 and EL2, we start the kernel in EL2, as it expects. We must also
 set the SCR_EL3.HCE bit in this situation, so that the HVC
 instruction is enabled rather than UNDEFing. Otherwise at least some
 kernels will panic when trying to initialize KVM in the guest.
+Rather than increment base_reg and num, compute num from the change
+to base_reg at the end.  Clean up some nearby comments.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 5 +++++
+ target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
-file changed, 5 insertions(+)
+file changed, 16 insertions(+), 11 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/arm/boot.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
-                     assert(!info->secure_board_setup);
+     g_string_append(s, "</union>");
-                 }
+ }
-+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
-+                    /* If we have EL2 then Linux expects the HVC insn to work */
++int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
-+                    env->cp15.scr_el3 |= SCR_HCE;
+ {
-+                }
+     ARMCPU *cpu = ARM_CPU(cs);
      GString *s = g_string_new(NULL);
      DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 -    int i, reg_width = (cpu->sve_max_vq * 128);
 -    info->num = 0;
 +    int reg_width = cpu->sve_max_vq * 128;
 +    int base_reg = orig_base_reg;
 +    int i;
 +
-                 /* Set to non-secure if not a secure boot */
+     g_string_printf(s, "<?xml version=\"1.0\"?>");
-                 if (!info->secure_boot &&
+     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-                     (cs != first_cpu || !info->secure_board_setup)) {
+     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 +    /* Create the vector union type. */
      output_vector_union_type(s, reg_width);
 -    /* Finally the sve prefix type */
 +    /* Create the predicate vector type. */
      g_string_append_printf(s,
                             "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
                             reg_width / 8);
 -    /* Then define each register in parts for each vq */
 +    /* Define the vector registers. */
      for (i = 0; i < 32; i++) {
          g_string_append_printf(s,
                                 "<reg name=\"z%d\" bitsize=\"%d\""
                                 " regnum=\"%d\" type=\"svev\"/>",
                                 i, reg_width, base_reg++);
 -        info->num++;
      }
 +
      /* fpscr & status registers */
      g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
                             " regnum=\"%d\" group=\"float\""
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
      g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
                             " regnum=\"%d\" group=\"float\""
                             " type=\"int\"/>", base_reg++);
 -    info->num += 2;
 +    /* Define the predicate registers. */
      for (i = 0; i < 16; i++) {
          g_string_append_printf(s,
                                 "<reg name=\"p%d\" bitsize=\"%d\""
                                 " regnum=\"%d\" type=\"svep\"/>",
                                 i, cpu->sve_max_vq * 16, base_reg++);
 -        info->num++;
      }
      g_string_append_printf(s,
                             "<reg name=\"ffr\" bitsize=\"%d\""
                             " regnum=\"%d\" group=\"vector\""
                             " type=\"svep\"/>",
                             cpu->sve_max_vq * 16, base_reg++);
 +
 +    /* Define the vector length pseudo-register. */
      g_string_append_printf(s,
                             "<reg name=\"vg\" bitsize=\"64\""
                             " regnum=\"%d\" type=\"int\"/>",
                             base_reg++);
 -    info->num += 2;
 -    g_string_append_printf(s, "</feature>");
 -    info->desc = g_string_free(s, false);
 +    g_string_append_printf(s, "</feature>");
 +
 +    info->desc = g_string_free(s, false);
 +    info->num = base_reg - orig_base_reg;
      return info->num;
  }
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
+[PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Code of imx_update() is slightly confusing since the "flags" variable
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
-doesn't really corespond to anything in real hardware and server as a
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-kitchensink accumulating events normally reported via USR1 and USR2
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-registers.
+Message-id: 20230227213329.793795-7-richard.henderson@linaro.org
 Change the code to explicitly evaluate state of interrupts reported
 via USR1 and USR2 against corresponding masking bits and use the to
 detemine if IRQ line should be asserted or not.
 NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
 reasons:
 . Emulation code implements a single character FIFO, so this flag
        will always be set since characters are trasmitted as a part of
        the code emulating "push" into the FIFO
 . imx_update() is really just a function doing ORing and maksing
        of reported events, so checking for UTS1_TXEMPTY should happen,
        if it's ever really needed should probably happen outside of
        it.
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/imx_serial.c | 24 ++++++++++++++++--------
+ target/arm/gdbstub64.c | 5 +++--
-file changed, 16 insertions(+), 8 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/char/imx_serial.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+     GString *s = g_string_new(NULL);
- static void imx_update(IMXSerialState *s)
+     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
- {
+     int reg_width = cpu->sve_max_vq * 128;
--    uint32_t flags;
++    int pred_width = cpu->sve_max_vq * 16;
-+    uint32_t usr1;
+     int base_reg = orig_base_reg;
-+    uint32_t usr2;
+     int i;
-+    uint32_t mask;
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
--    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
+         g_string_append_printf(s,
--    if (s->ucr1 & UCR1_TXMPTYEN) {
+                                "<reg name=\"p%d\" bitsize=\"%d\""
--        flags |= (s->uts1 & UTS1_TXEMPTY);
+                                " regnum=\"%d\" type=\"svep\"/>",
--    } else {
+-                               i, cpu->sve_max_vq * 16, base_reg++);
--        flags &= ~USR1_TRDY;
++                               i, pred_width, base_reg++);
--    }
+     }
-+    /*
+     g_string_append_printf(s,
-+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+                            "<reg name=\"ffr\" bitsize=\"%d\""
-+     * UCR1, so we can get away with something as simple as the
+                            " regnum=\"%d\" group=\"vector\""
-+     * following:
+                            " type=\"svep\"/>",
-+     */
+-                           cpu->sve_max_vq * 16, base_reg++);
-+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
++                           pred_width, base_reg++);
-+    /*
-+     * Bits that we want in USR2 are not as conveniently laid out,
+     /* Define the vector length pseudo-register. */
-+     * unfortunately.
+     g_string_append_printf(s,
 +     */
 +    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    usr2 = s->usr2 & mask;
 -    qemu_set_irq(s->irq, !!flags);
 +    qemu_set_irq(s->irq, usr1 || usr2);
  }
  static void imx_serial_reset(IMXSerialState *s)
 --
-.16.2
+.34.1

-New patch
+[PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
+From: Richard Henderson <richard.henderson@linaro.org>
+Define svep based on the size of the predicates,
+not the primary vector registers.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+     /* Create the predicate vector type. */
+     g_string_append_printf(s,
+                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+-                           reg_width / 8);
++                           pred_width / 8);
+     /* Define the vector registers. */
+     for (i = 0; i < 32; i++) {
+--
+.34.1

-[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+[PULL 08/21] target/arm: Add name argument to output_vector_union_type
-For the rpi1 and 2 we want to boot the Linux kernel via some
+From: Richard Henderson <richard.henderson@linaro.org>
 custom setup code that makes sure that the SMC instruction
 acts as a no-op, because it's used for cache maintenance.
 The rpi3 boots AArch64 kernels, which don't need SMC for
 cache maintenance and always expect to be booted non-secure.
 Don't fill in the aarch32-specific parts of the binfo struct.
+This will make the function usable between SVE and SME.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 17 +++++++++++++----
+ target/arm/gdbstub64.c | 28 ++++++++++++++--------------
-file changed, 13 insertions(+), 4 deletions(-)
+file changed, 14 insertions(+), 14 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/arm/raspi.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
-     binfo.board_id = raspi_boardid[version];
+     return 0;
-     binfo.ram_size = ram_size;
+ }
-     binfo.nb_cpus = smp_cpus;
--    binfo.board_setup_addr = BOARDSETUP_ADDR;
+-static void output_vector_union_type(GString *s, int reg_width)
--    binfo.write_board_setup = write_board_setup;
++static void output_vector_union_type(GString *s, int reg_width,
--    binfo.secure_board_setup = true;
++                                     const char *name)
--    binfo.secure_boot = true;
+ {
      struct TypeSize {
          const char *gdb_type;
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
      };
      static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -
 -    g_autoptr(GString) ts = g_string_new("");
      int i, j, bits;
      /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 -        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
          g_string_append_printf(s,
 -                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 -                               ts->str, vec_lanes[i].gdb_type, count);
 +                               "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
 +                               name, vec_lanes[i].sz, vec_lanes[i].suffix,
 +                               vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
      }
 +
-+    if (version <= 2) {
+     /*
-+        /* The rpi1 and 2 require some custom setup code to run in Secure
+      * Now define a union for each size group containing unsigned and
-+         * mode before booting a kernel (to set up the SMC vectors so
+      * signed and potentially float versions of each size from 128 to
-+         * that we get a no-op SMC; this is used by Linux to call the
+      * 8 bits.
-+         * firmware for some cache maintenance operations.
+      */
-+         * The rpi3 doesn't need this.
+     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-+         */
+-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
-+        binfo.board_setup_addr = BOARDSETUP_ADDR;
++        g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
-+        binfo.write_board_setup = write_board_setup;
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
-+        binfo.secure_board_setup = true;
+             if (vec_lanes[j].size == bits) {
-+        binfo.secure_boot = true;
+-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-+    }
+-                                       vec_lanes[j].suffix,
++                g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
-     /* Pi2 and Pi3 requires SMP setup */
++                                       vec_lanes[j].suffix, name,
-     if (version >= 2) {
+                                        vec_lanes[j].sz, vec_lanes[j].suffix);
              }
          }
          g_string_append(s, "</union>");
      }
 +
      /* And now the final union of unions */
 -    g_string_append(s, "<union id=\"svev\">");
 +    g_string_append_printf(s, "<union id=\"%s\">", name);
      for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 -                               suf[i], suf[i]);
 +        g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
 +                               suf[i], name, suf[i]);
      }
      g_string_append(s, "</union>");
  }
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
      g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
      /* Create the vector union type. */
 -    output_vector_union_type(s, reg_width);
 +    output_vector_union_type(s, reg_width, "svev");
      /* Create the predicate vector type. */
      g_string_append_printf(s,
 --
-.16.2
+.34.1

-New patch
+[PULL 09/21] target/arm: Simplify iteration over bit widths
+From: Richard Henderson <richard.henderson@linaro.org>
+Order suf[] by the log8 of the width.
+Use ARRAY_SIZE instead of hard-coding 128.
+This changes the order of the union definitions,
+but retains the order of the union-of-union members.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 10 ++++++----
+file changed, 6 insertions(+), 4 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+         { "int8", 8, 'b', 's' },
+     };
+-    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+-    int i, j, bits;
++    static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
++    int i, j;
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+      * signed and potentially float versions of each size from 128 to
+      * 8 bits.
+      */
+-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
++    for (i = 0; i < ARRAY_SIZE(suf); i++) {
++        int bits = 8 << i;
++
+         g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+             if (vec_lanes[j].size == bits) {
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+     /* And now the final union of unions */
+     g_string_append_printf(s, "<union id=\"%s\">", name);
+-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
++    for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
+         g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
+                                suf[i], name, suf[i]);
+     }
+--
+.34.1

-New patch
+[PULL 10/21] target/arm: Create pauth_ptr_mask
+From: Richard Henderson <richard.henderson@linaro.org>
+Keep the logic for pauth within pauth_helper.c, and expose
+a helper function for use with the gdbstub pac extension.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h        | 10 ++++++++++
+ target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
+files changed, 32 insertions(+), 4 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
+ bool arm_singlestep_active(CPUARMState *env);
+ bool arm_generate_debug_exceptions(CPUARMState *env);
++/**
++ * pauth_ptr_mask:
++ * @env: cpu context
++ * @ptr: selects between TTBR0 and TTBR1
++ * @data: selects between TBI and TBID
++ *
++ * Return a mask of the bits of @ptr that contain the authentication code.
++ */
++uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
++
+ /* Add the cpreg definitions for debug related system registers */
+ void define_debug_regs(ARMCPU *cpu);
+diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/pauth_helper.c
++++ b/target/arm/tcg/pauth_helper.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
+     return pac | ext | ptr;
+ }
+-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
++static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
+ {
+-    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+-    uint64_t extfield = sextract64(ptr, 55, 1);
+     int bot_pac_bit = 64 - param.tsz;
+     int top_pac_bit = 64 - 8 * param.tbi;
+-    return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
++    return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
++}
++
++static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
++{
++    uint64_t mask = pauth_ptr_mask_internal(param);
++
++    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
++    if (extract64(ptr, 55, 1)) {
++        return ptr | mask;
++    } else {
++        return ptr & ~mask;
++    }
++}
++
++uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
++{
++    ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
++    ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
++
++    return pauth_ptr_mask_internal(param);
+ }
+ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
+--
+.34.1

-New patch
+[PULL 11/21] target/arm: Implement gdbstub pauth extension
+From: Richard Henderson <richard.henderson@linaro.org>
+The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
+ptrace register set.
+The original gdb feature consists of two masks, data and code, which are
+used to mask out the authentication code within a pointer.  Following
+discussion with Luis Machado, add two more masks in order to support
+pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ configs/targets/aarch64-linux-user.mak    |  2 +-
+ configs/targets/aarch64-softmmu.mak       |  2 +-
+ configs/targets/aarch64_be-linux-user.mak |  2 +-
+ target/arm/internals.h                    |  2 ++
+ target/arm/gdbstub.c                      |  5 ++++
+ target/arm/gdbstub64.c                    | 34 +++++++++++++++++++++++
+ gdb-xml/aarch64-pauth.xml                 | 15 ++++++++++
+files changed, 59 insertions(+), 3 deletions(-)
+ create mode 100644 gdb-xml/aarch64-pauth.xml
+diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/targets/aarch64-linux-user.mak
++++ b/configs/targets/aarch64-linux-user.mak
+@@ -XXX,XX +XXX,XX @@
+ TARGET_ARCH=aarch64
+ TARGET_BASE_ARCH=arm
+-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
++TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
+ TARGET_HAS_BFLT=y
+ CONFIG_SEMIHOSTING=y
+ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/targets/aarch64-softmmu.mak
++++ b/configs/targets/aarch64-softmmu.mak
+@@ -XXX,XX +XXX,XX @@
+ TARGET_ARCH=aarch64
+ TARGET_BASE_ARCH=arm
+ TARGET_SUPPORTS_MTTCG=y
+-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
++TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
+ TARGET_NEED_FDT=y
+diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/targets/aarch64_be-linux-user.mak
++++ b/configs/targets/aarch64_be-linux-user.mak
+@@ -XXX,XX +XXX,XX @@
+ TARGET_ARCH=aarch64
+ TARGET_BASE_ARCH=arm
+ TARGET_BIG_ENDIAN=y
+-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
++TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
+ TARGET_HAS_BFLT=y
+ CONFIG_SEMIHOSTING=y
+ CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
+ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
+ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
+ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
++int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
++int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
+ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub.c
++++ b/target/arm/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
+                                      aarch64_gdb_set_fpu_reg,
+, "aarch64-fpu.xml", 0);
+         }
++        if (isar_feature_aa64_pauth(&cpu->isar)) {
++            gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
++                                     aarch64_gdb_set_pauth_reg,
++                                     4, "aarch64-pauth.xml", 0);
++        }
+ #endif
+     } else {
+         if (arm_feature(env, ARM_FEATURE_NEON)) {
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
+     return 0;
+ }
++int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
++{
++    switch (reg) {
++    case 0: /* pauth_dmask */
++    case 1: /* pauth_cmask */
++    case 2: /* pauth_dmask_high */
++    case 3: /* pauth_cmask_high */
++        /*
++         * Note that older versions of this feature only contained
++         * pauth_{d,c}mask, for use with Linux user processes, and
++         * thus exclusively in the low half of the address space.
++         *
++         * To support system mode, and to debug kernels, two new regs
++         * were added to cover the high half of the address space.
++         * For the purpose of pauth_ptr_mask, we can use any well-formed
++         * address within the address space half -- here, 0 and -1.
++         */
++        {
++            bool is_data = !(reg & 1);
++            bool is_high = reg & 2;
++            uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
++            return gdb_get_reg64(buf, mask);
++        }
++    default:
++        return 0;
++    }
++}
++
++int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
++{
++    /* All pseudo registers are read-only. */
++    return 0;
++}
++
+ static void output_vector_union_type(GString *s, int reg_width,
+                                      const char *name)
+ {
+diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/gdb-xml/aarch64-pauth.xml
+@@ -XXX,XX +XXX,XX @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.aarch64.pauth">
++  <reg name="pauth_dmask" bitsize="64"/>
++  <reg name="pauth_cmask" bitsize="64"/>
++  <reg name="pauth_dmask_high" bitsize="64"/>
++  <reg name="pauth_cmask_high" bitsize="64"/>
++</feature>
++
+--
+.34.1

-[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
+[PULL 12/21] target/arm: Export arm_v7m_mrs_control
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: David Reiss <dreiss@meta.com>
-Add support for "TX complete"/TXDC interrupt generate by real HW since
+Allow the function to be used outside of m_helper.c.
-it is needed to support guests other than Linux.
+Rename with an "arm_" prefix.
-Based on the patch by Bill Paul as found here:
-https://bugs.launchpad.net/qemu/+bug/1753314
-Cc: qemu-devel@nongnu.org
-Cc: qemu-arm@nongnu.org
-Cc: Bill Paul <wpaul@windriver.com>
-Cc: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Bill Paul <wpaul@windriver.com>
-Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
-Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: David Reiss <dreiss@meta.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
+[rth: Split out of a larger patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/char/imx_serial.h |  3 +++
+ target/arm/internals.h    | 3 +++
- hw/char/imx_serial.c         | 20 +++++++++++++++++---
+ target/arm/tcg/m_helper.c | 6 +++---
-files changed, 20 insertions(+), 3 deletions(-)
+files changed, 6 insertions(+), 3 deletions(-)
-diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/imx_serial.h
+--- a/target/arm/internals.h
-+++ b/include/hw/char/imx_serial.h
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
- #define UCR2_RXEN       (1<<1)    /* Receiver enable */
+ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
- #define UCR2_SRST       (1<<0)    /* Reset complete */
+ #endif
-+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
++/* Read the CONTROL register as the MRS instruction would. */
 +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
 +
- #define UTS1_TXEMPTY    (1<<6)
+ #ifdef CONFIG_USER_ONLY
- #define UTS1_RXEMPTY    (1<<5)
+ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
- #define UTS1_TXFULL     (1<<4)
+ #else
-@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
+diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
      uint32_t ubmr;
      uint32_t ubrc;
      uint32_t ucr3;
 +    uint32_t ucr4;
      qemu_irq irq;
      CharBackend chr;
 diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/target/arm/tcg/m_helper.c
-+++ b/hw/char/imx_serial.c
++++ b/target/arm/tcg/m_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
+     return xpsr_read(env) & mask;
- static const VMStateDescription vmstate_imx_serial = {
+ }
-     .name = TYPE_IMX_SERIAL,
--    .version_id = 1,
+-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
--    .minimum_version_id = 1,
++uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
-+    .version_id = 2,
+ {
-+    .minimum_version_id = 2,
+     uint32_t value = env->v7m.control[secure];
-     .fields = (VMStateField[]) {
-         VMSTATE_INT32(readbuff, IMXSerialState),
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
-         VMSTATE_UINT32(usr1, IMXSerialState),
+     case 0 ... 7: /* xPSR sub-fields */
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+         return v7m_mrs_xpsr(env, reg, 0);
-         VMSTATE_UINT32(ubmr, IMXSerialState),
+     case 20: /* CONTROL */
-         VMSTATE_UINT32(ubrc, IMXSerialState),
+-        return v7m_mrs_control(env, 0);
-         VMSTATE_UINT32(ucr3, IMXSerialState),
++        return arm_v7m_mrs_control(env, 0);
-+        VMSTATE_UINT32(ucr4, IMXSerialState),
+     default:
-         VMSTATE_END_OF_LIST()
+         /* Unprivileged reads others as zero.  */
-     },
+         return 0;
- };
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
-@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
+     case 0 ... 7: /* xPSR sub-fields */
-      * unfortunately.
+         return v7m_mrs_xpsr(env, reg, el);
-      */
+     case 20: /* CONTROL */
-     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+-        return v7m_mrs_control(env, env->v7m.secure);
-+    /*
++        return arm_v7m_mrs_control(env, env->v7m.secure);
-+     * TCEN and TXDC are both bit 3
+     case 0x94: /* CONTROL_NS */
-+     */
+         /*
-+    mask |= s->ucr4 & UCR4_TCEN;
+          * We have to handle this here because unprivileged Secure code
 +
      usr2 = s->usr2 & mask;
      qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
          return s->ucr3;
      case 0x23: /* UCR4 */
 +        return s->ucr4;
 +
      case 0x29: /* BRM Incremental */
          return 0x0; /* TODO */
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
               * qemu_chr_fe_write and background I/O callbacks */
              qemu_chr_fe_write_all(&s->chr, &ch, 1);
              s->usr1 &= ~USR1_TRDY;
 +            s->usr2 &= ~USR2_TXDC;
              imx_update(s);
              s->usr1 |= USR1_TRDY;
 +            s->usr2 |= USR2_TXDC;
              imx_update(s);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
          s->ucr3 = value & 0xffff;
          break;
 -    case 0x2d: /* UTS1 */
      case 0x23: /* UCR4 */
 +        s->ucr4 = value & 0xffff;
 +        imx_update(s);
 +        break;
 +
 +    case 0x2d: /* UTS1 */
          qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                        HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
          /* TODO */
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+[PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr
-Our BCM2836 type is really a generic one that can be any of
+From: David Reiss <dreiss@meta.com>
 the bcm283x family. Rename it accordingly. We change only
 the names which are visible via the header file to the
 rest of the QEMU code, leaving private function names
 in bcm2836.c as they are.
-This is a preliminary to making bcm283x be an abstract
+Allow the function to be used outside of m_helper.c.
-parent class to specific types for the bcm2836 and bcm2837.
+Move to be outside of ifndef CONFIG_USER_ONLY block.
 Rename from get_v7m_sp_ptr.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: David Reiss <dreiss@meta.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
+[rth: Split out of a larger patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 12 ++++++------
+ target/arm/internals.h    | 10 +++++
- hw/arm/bcm2836.c         | 17 +++++++++--------
+ target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
- hw/arm/raspi.c           | 16 ++++++++--------
+files changed, 51 insertions(+), 43 deletions(-)
 files changed, 23 insertions(+), 22 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/target/arm/internals.h
-+++ b/include/hw/arm/bcm2836.h
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
- #include "hw/arm/bcm2835_peripherals.h"
+ /* Read the CONTROL register as the MRS instruction would. */
- #include "hw/intc/bcm2836_control.h"
+ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
--#define TYPE_BCM2836 "bcm2836"
++/*
--#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
++ * Return a pointer to the location where we currently store the
-+#define TYPE_BCM283X "bcm283x"
++ * stack pointer for the requested security state and thread mode.
-+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
++ * This pointer will become invalid if the CPU state is updated
++ * such that the stack pointers are switched around (eg changing
--#define BCM2836_NCPUS 4
++ * the SPSEL control bit).
-+#define BCM283X_NCPUS 4
++ */
++uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
--typedef struct BCM2836State {
++                             bool threadmode, bool spsel);
-+typedef struct BCM283XState {
++
-     /*< private >*/
+ #ifdef CONFIG_USER_ONLY
-     DeviceState parent_obj;
+ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
-     /*< public >*/
+ #else
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
+diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
      char *cpu_type;
      uint32_t enabled_cpus;
 -    ARMCPU cpus[BCM2836_NCPUS];
 +    ARMCPU cpus[BCM283X_NCPUS];
      BCM2836ControlState control;
      BCM2835PeripheralState peripherals;
 -} BCM2836State;
 +} BCM283XState;
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/tcg/m_helper.c
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/tcg/m_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+     arm_rebuild_hflags(env);
- static void bcm2836_init(Object *obj)
+ }
 -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
 -                                bool spsel)
 -{
 -    /*
 -     * Return a pointer to the location where we currently store the
 -     * stack pointer for the requested security state and thread mode.
 -     * This pointer will become invalid if the CPU state is updated
 -     * such that the stack pointers are switched around (eg changing
 -     * the SPSEL control bit).
 -     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
 -     * Unlike that pseudocode, we require the caller to pass us in the
 -     * SPSEL control bit value; this is because we also use this
 -     * function in handling of pushing of the callee-saves registers
 -     * part of the v8M stack frame (pseudocode PushCalleeStack()),
 -     * and in the tailchain codepath the SPSEL bit comes from the exception
 -     * return magic LR value from the previous exception. The pseudocode
 -     * opencodes the stack-selection in PushCalleeStack(), but we prefer
 -     * to make this utility function generic enough to do the job.
 -     */
 -    bool want_psp = threadmode && spsel;
 -
 -    if (secure == env->v7m.secure) {
 -        if (want_psp == v7m_using_psp(env)) {
 -            return &env->regs[13];
 -        } else {
 -            return &env->v7m.other_sp;
 -        }
 -    } else {
 -        if (want_psp) {
 -            return &env->v7m.other_ss_psp;
 -        } else {
 -            return &env->v7m.other_ss_msp;
 -        }
 -    }
 -}
 -
  static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
                                  uint32_t *pvec)
  {
--    BCM2836State *s = BCM2836(obj);
+@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
-+    BCM283XState *s = BCM283X(obj);
+             !mode;
-     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
+         mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
-     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
+-        frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
+-                                    lr & R_V7M_EXCRET_SPSEL_MASK);
++        frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
- static void bcm2836_realize(DeviceState *dev, Error **errp)
++                                        lr & R_V7M_EXCRET_SPSEL_MASK);
- {
+         want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
--    BCM2836State *s = BCM2836(dev);
+         if (want_psp) {
-+    BCM283XState *s = BCM283X(dev);
+             limit = env->v7m.psplim[M_REG_S];
-     Object *obj;
+@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
-     Error *err = NULL;
+          * use 'frame_sp_p' after we do something that makes it invalid.
      int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      /* common peripherals from bcm2835 */
      obj = OBJECT(dev);
 -    for (n = 0; n < BCM2836_NCPUS; n++) {
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
          object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                            s->cpu_type);
          object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
          qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 -    for (n = 0; n < BCM2836_NCPUS; n++) {
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
          /* Mirror bcm2836, which has clusterid set to 0xf
           * TODO: this should be converted to a property of ARM_CPU
           */
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+         bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
 -        uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
 -                                              return_to_secure,
 -                                              !return_to_handler,
 -                                              spsel);
 +        uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
 +                                                  !return_to_handler, spsel);
          uint32_t frameptr = *frame_sp_p;
          bool pop_ok = true;
          ARMMMUIdx mmu_idx;
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
          threadmode = !arm_v7m_is_handler_mode(env);
          spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
 -        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
 +        frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
          frameptr = *frame_sp_p;
          /*
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
  }
- static Property bcm2836_props[] = {
+ #endif /* !CONFIG_USER_ONLY */
--    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
++
--    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
++uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
-+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
++                             bool spsel)
-+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
++{
-+                       BCM283X_NCPUS),
++    /*
-     DEFINE_PROP_END_OF_LIST()
++     * Return a pointer to the location where we currently store the
- };
++     * stack pointer for the requested security state and thread mode.
++     * This pointer will become invalid if the CPU state is updated
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
++     * such that the stack pointers are switched around (eg changing
- }
++     * the SPSEL control bit).
++     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
- static const TypeInfo bcm2836_type_info = {
++     * Unlike that pseudocode, we require the caller to pass us in the
--    .name = TYPE_BCM2836,
++     * SPSEL control bit value; this is because we also use this
-+    .name = TYPE_BCM283X,
++     * function in handling of pushing of the callee-saves registers
-     .parent = TYPE_DEVICE,
++     * part of the v8M stack frame (pseudocode PushCalleeStack()),
--    .instance_size = sizeof(BCM2836State),
++     * and in the tailchain codepath the SPSEL bit comes from the exception
-+    .instance_size = sizeof(BCM283XState),
++     * return magic LR value from the previous exception. The pseudocode
-     .instance_init = bcm2836_init,
++     * opencodes the stack-selection in PushCalleeStack(), but we prefer
-     .class_init = bcm2836_class_init,
++     * to make this utility function generic enough to do the job.
- };
++     */
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
++    bool want_psp = threadmode && spsel;
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/arm/raspi.c
++    if (secure == env->v7m.secure) {
-+++ b/hw/arm/raspi.c
++        if (want_psp == v7m_using_psp(env)) {
-@@ -XXX,XX +XXX,XX @@
++            return &env->regs[13];
- static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
++        } else {
++            return &env->v7m.other_sp;
- typedef struct RasPiState {
++        }
--    BCM2836State soc;
++    } else {
-+    BCM283XState soc;
++        if (want_psp) {
-     MemoryRegion ram;
++            return &env->v7m.other_ss_psp;
- } RasPiState;
++        } else {
++            return &env->v7m.other_ss_msp;
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
++        }
-     BusState *bus;
++    }
-     DeviceState *carddev;
++}
 -    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
 +    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
      object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                                &error_abort);
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
      mc->no_floppy = 1;
      mc->no_cdrom = 1;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 -    mc->max_cpus = BCM2836_NCPUS;
 -    mc->min_cpus = BCM2836_NCPUS;
 -    mc->default_cpus = BCM2836_NCPUS;
 +    mc->max_cpus = BCM283X_NCPUS;
 +    mc->min_cpus = BCM283X_NCPUS;
 +    mc->default_cpus = BCM283X_NCPUS;
      mc->default_ram_size = 1024 * 1024 * 1024;
      mc->ignore_memory_transaction_failures = true;
  };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
      mc->no_floppy = 1;
      mc->no_cdrom = 1;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
 -    mc->max_cpus = BCM2836_NCPUS;
 -    mc->min_cpus = BCM2836_NCPUS;
 -    mc->default_cpus = BCM2836_NCPUS;
 +    mc->max_cpus = BCM283X_NCPUS;
 +    mc->min_cpus = BCM283X_NCPUS;
 +    mc->default_cpus = BCM283X_NCPUS;
      mc->default_ram_size = 1024 * 1024 * 1024;
  }
  DEFINE_MACHINE("raspi3", raspi3_machine_init)
 --
-.16.2
+.34.1

-New patch
+[PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext
+From: Richard Henderson <richard.henderson@linaro.org>
 The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
 go ahead and implement the other system registers as well.
 Since there is significant overlap between the two, implement
 them with common code.  The only exception is the systemreg
 view of CONTROL, which merges the banked bits as per MRS.
 Signed-off-by: David Reiss <dreiss@meta.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
 [rth: Substatial rewrite using enumerator and shared code.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h     |   2 +
  target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 files changed, 180 insertions(+)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      DynamicGDBXMLInfo dyn_sysreg_xml;
      DynamicGDBXMLInfo dyn_svereg_xml;
 +    DynamicGDBXMLInfo dyn_m_systemreg_xml;
 +    DynamicGDBXMLInfo dyn_m_secextreg_xml;
      /* Timers used by the generic (architected) timer */
      QEMUTimer *gt_timer[NUM_GTIMERS];
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
      return cpu->dyn_sysreg_xml.num;
  }
 +typedef enum {
 +    M_SYSREG_MSP,
 +    M_SYSREG_PSP,
 +    M_SYSREG_PRIMASK,
 +    M_SYSREG_CONTROL,
 +    M_SYSREG_BASEPRI,
 +    M_SYSREG_FAULTMASK,
 +    M_SYSREG_MSPLIM,
 +    M_SYSREG_PSPLIM,
 +} MProfileSysreg;
 +
 +static const struct {
 +    const char *name;
 +    int feature;
 +} m_sysreg_def[] = {
 +    [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
 +    [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
 +    [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
 +    [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
 +    [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
 +    [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
 +    [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
 +    [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
 +};
 +
 +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
 +{
 +    uint32_t *ptr;
 +
 +    switch (reg) {
 +    case M_SYSREG_MSP:
 +        ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
 +        break;
 +    case M_SYSREG_PSP:
 +        ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
 +        break;
 +    case M_SYSREG_MSPLIM:
 +        ptr = &env->v7m.msplim[sec];
 +        break;
 +    case M_SYSREG_PSPLIM:
 +        ptr = &env->v7m.psplim[sec];
 +        break;
 +    case M_SYSREG_PRIMASK:
 +        ptr = &env->v7m.primask[sec];
 +        break;
 +    case M_SYSREG_BASEPRI:
 +        ptr = &env->v7m.basepri[sec];
 +        break;
 +    case M_SYSREG_FAULTMASK:
 +        ptr = &env->v7m.faultmask[sec];
 +        break;
 +    case M_SYSREG_CONTROL:
 +        ptr = &env->v7m.control[sec];
 +        break;
 +    default:
 +        return NULL;
 +    }
 +    return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
 +}
 +
 +static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
 +                        MProfileSysreg reg, bool secure)
 +{
 +    uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
 +
 +    if (ptr == NULL) {
 +        return 0;
 +    }
 +    return gdb_get_reg32(buf, *ptr);
 +}
 +
 +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
 +{
 +    /*
 +     * Here, we emulate MRS instruction, where CONTROL has a mix of
 +     * banked and non-banked bits.
 +     */
 +    if (reg == M_SYSREG_CONTROL) {
 +        return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
 +    }
 +    return m_sysreg_get(env, buf, reg, env->v7m.secure);
 +}
 +
 +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
 +{
 +    return 0; /* TODO */
 +}
 +
 +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    GString *s = g_string_new(NULL);
 +    int base_reg = orig_base_reg;
 +    int i;
 +
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
 +
 +    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
 +        if (arm_feature(env, m_sysreg_def[i].feature)) {
 +            g_string_append_printf(s,
 +                "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +                m_sysreg_def[i].name, base_reg++);
 +        }
 +    }
 +
 +    g_string_append_printf(s, "</feature>");
 +    cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
 +    cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
 +
 +    return cpu->dyn_m_systemreg_xml.num;
 +}
 +
 +#ifndef CONFIG_USER_ONLY
 +/*
 + * For user-only, we see the non-secure registers via m_systemreg above.
 + * For secext, encode the non-secure view as even and secure view as odd.
 + */
 +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
 +{
 +    return m_sysreg_get(env, buf, reg >> 1, reg & 1);
 +}
 +
 +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
 +{
 +    return 0; /* TODO */
 +}
 +
 +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    GString *s = g_string_new(NULL);
 +    int base_reg = orig_base_reg;
 +    int i;
 +
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
 +
 +    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
 +        g_string_append_printf(s,
 +            "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +            m_sysreg_def[i].name, base_reg++);
 +        g_string_append_printf(s,
 +            "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +            m_sysreg_def[i].name, base_reg++);
 +    }
 +
 +    g_string_append_printf(s, "</feature>");
 +    cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
 +    cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
 +
 +    return cpu->dyn_m_secextreg_xml.num;
 +}
 +#endif
 +
  const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
  {
      ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
          return cpu->dyn_sysreg_xml.desc;
      } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
          return cpu->dyn_svereg_xml.desc;
 +    } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
 +        return cpu->dyn_m_systemreg_xml.desc;
 +#ifndef CONFIG_USER_ONLY
 +    } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
 +        return cpu->dyn_m_secextreg_xml.desc;
 +#endif
      }
      return NULL;
  }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                               arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                               "system-registers.xml", 0);
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        gdb_register_coprocessor(cs,
 +            arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
 +            arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
 +            "arm-m-system.xml", 0);
 +#ifndef CONFIG_USER_ONLY
 +        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 +            gdb_register_coprocessor(cs,
 +                arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
 +                arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
 +                "arm-m-secext.xml", 0);
 +        }
 +#endif
 +    }
  }
 --
 .34.1

-New patch
+[PULL 15/21] target/arm: Handle m-profile in arm_is_secure
+From: Richard Henderson <richard.henderson@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-2-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
+ /* Return true if the processor is in secure state */
+ static inline bool arm_is_secure(CPUARMState *env)
+ {
++    if (arm_feature(env, ARM_FEATURE_M)) {
++        return env->v7m.secure;
++    }
+     if (arm_is_el3_or_mon(env)) {
+         return true;
+     }
+--
+.34.1

-New patch
+[PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile
+From: Richard Henderson <richard.henderson@linaro.org>
+M-profile doesn't have HCR_EL2.  While we could test features
+before each call, zero is a generally safe return value to
+disable the code in the caller.  This test is required to
+avoid an assert in arm_is_secure_below_el3.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
+ uint64_t arm_hcr_el2_eff(CPUARMState *env)
+ {
++    if (arm_feature(env, ARM_FEATURE_M)) {
++        return 0;
++    }
+     return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
+ }
+--
+.34.1

-[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
+[PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines
-From: Guenter Roeck <linux@roeck-us.net>
+From: Richard Henderson <richard.henderson@linaro.org>
-The sabrelite machine model used by qemu-system-arm is based on the
+In several places we use arm_is_secure_below_el3 and
-Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
+arm_is_el3_or_mon separately from arm_is_secure.
-controller which is supported in QEMU using the imx_fec.c module
+These functions make no sense for m-profile, and
-(actually called imx.enet for this model.)
+would indicate prior incorrect feature testing.
-The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
-imx.enet device like this:
- #define FSL_IMX6_ENET_MAC_1588_IRQ 118
- #define FSL_IMX6_ENET_MAC_IRQ 119
-According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
-page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
-interrupts are as follows.
-ENET MAC 0 IRQ
-ENET MAC 0 1588 Timer interrupt
-where
-- 32 == 118
-- 32 == 119
-In other words, the vector definitions in the fsl-imx6.h file are reversed.
-Fixing the interrupts alone causes problems with older Linux kernels:
-The Ethernet interface will fail to probe with Linux v4.9 and earlier.
-Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
-error handling. This is a Linux kernel problem, not a qemu problem:
-the Linux kernel only worked by accident since it requested both interrupts.
-For backward compatibility, generate the Ethernet interrupt on both interrupt
-lines. This was shown to work from all Linux kernel releases starting with
-v3.16.
-Link: https://bugs.launchpad.net/qemu/+bug/1753309
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6.h |  4 ++--
+ target/arm/cpu.h | 5 ++++-
- hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
+file changed, 4 insertions(+), 1 deletion(-)
 files changed, 29 insertions(+), 3 deletions(-)
-diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
+--- a/target/arm/cpu.h
-+++ b/include/hw/arm/fsl-imx6.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
+@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
- #define FSL_IMX6_HDMI_MASTER_IRQ 115
+ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
- #define FSL_IMX6_HDMI_CEC_IRQ 116
- #define FSL_IMX6_MLB150_LOW_IRQ 117
+ #if !defined(CONFIG_USER_ONLY)
--#define FSL_IMX6_ENET_MAC_1588_IRQ 118
+-/* Return true if exception levels below EL3 are in secure state,
--#define FSL_IMX6_ENET_MAC_IRQ 119
++/*
-+#define FSL_IMX6_ENET_MAC_IRQ 118
++ * Return true if exception levels below EL3 are in secure state,
-+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
+  * or would be following an exception return to that level.
- #define FSL_IMX6_PCIE1_IRQ 120
+  * Unlike arm_is_secure() (which is always a question about the
- #define FSL_IMX6_PCIE2_IRQ 121
+  * _current_ state of the CPU) this doesn't care about the current
- #define FSL_IMX6_PCIE3_IRQ 122
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
-diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
+  */
-index XXXXXXX..XXXXXXX 100644
+ static inline bool arm_is_secure_below_el3(CPUARMState *env)
 --- a/hw/net/imx_fec.c
 +++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
  static void imx_eth_update(IMXFECState *s)
  {
--    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
++    assert(!arm_feature(env, ARM_FEATURE_M));
-+    /*
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
-+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+         return !(env->cp15.scr_el3 & SCR_NS);
 +     * interrupts swapped. This worked with older versions of Linux (4.14
 +     * and older) since Linux associated both interrupt lines with Ethernet
 +     * MAC interrupts. Specifically,
 +     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
 +     *   timer interrupts. Those versions of Linux fail with versions of QEMU
 +     *   with swapped interrupt assignments.
 +     * - In linux 4.14, both interrupt lines were registered with the Ethernet
 +     *   MAC interrupt handler. As a result, all versions of qemu happen to
 +     *   work, though that is accidental.
 +     * - In Linux 4.9 and older, the timer interrupt was registered directly
 +     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
 +     *   redirected to a GPIO interrupt to work around erratum ERR006687.
 +     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
 +     *   interrupt never fired since IOMUX is currently not supported in qemu.
 +     *   Linux instead received MAC interrupts on the timer interrupt.
 +     *   As a result, qemu versions with the swapped interrupt assignment work,
 +     *   albeit accidentally, but qemu versions with the correct interrupt
 +     *   assignment fail.
 +     *
 +     * To ensure that all versions of Linux work, generate ENET_INT_MAC
 +     * interrrupts on both interrupt lines. This should be changed if and when
 +     * qemu supports IOMUX.
 +     */
 +    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
 +        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
          qemu_set_irq(s->irq[1], 1);
      } else {
-         qemu_set_irq(s->irq[1], 0);
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
  /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
  static inline bool arm_is_el3_or_mon(CPUARMState *env)
  {
 +    assert(!arm_feature(env, ARM_FEATURE_M));
      if (arm_feature(env, ARM_FEATURE_EL3)) {
          if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
              /* CPU currently in AArch64 state and EL3 */
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
+[PULL 18/21] target/arm: Rewrite check_s2_mmu_setup
-From: Wei Huang <wei@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-For guest kernel that supports KASLR, the load address can change every
+Integrate neighboring code from get_phys_addr_lpae which computed
-time when guest VM runs. To find the physical base address correctly,
+starting level, as it is easier to validate when doing both at the
-current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
+same time.  Mirror the checks at the start of AArch{64,32}.S2Walk,
-However this string pattern is only available on x86_64. AArch64 uses a
+especially S2InvalidSL and S2InconsistentSL.
-different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
-QEMU dump uses the correct string on AArch64.
+This reverts 49ba115bb74, which was incorrect -- there is nothing
+in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
-Signed-off-by: Wei Huang <wei@redhat.com>
+pseudocode is consistent in referencing PAMax.
-Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
-Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
+Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- dump.c | 14 +++++++++++---
+ target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
-file changed, 11 insertions(+), 3 deletions(-)
+file changed, 97 insertions(+), 76 deletions(-)
-diff --git a/dump.c b/dump.c
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/dump.c
+--- a/target/arm/ptw.c
-+++ b/dump.c
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
+@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
+  * check_s2_mmu_setup
-     lines = g_strsplit((char *)vmci, "\n", -1);
+  * @cpu:        ARMCPU
-     for (i = 0; lines[i]; i++) {
+  * @is_aa64:    True if the translation regime is in AArch64 state
--        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
+- * @startlevel: Suggested starting level
--            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+- * @inputsize:  Bitsize of IPAs
-+        const char *prefix = NULL;
++ * @tcr:        VTCR_EL2 or VSTCR_EL2
-+
++ * @ds:         Effective value of TCR.DS.
-+        if (s->dump_info.d_machine == EM_X86_64) {
++ * @iasize:     Bitsize of IPAs
-+            prefix = "NUMBER(phys_base)=";
+  * @stride:     Page-table stride (See the ARM ARM)
-+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+  *
-+            prefix = "NUMBER(PHYS_OFFSET)=";
+- * Returns true if the suggested S2 translation parameters are OK and
 - * false otherwise.
 + * Decode the starting level of the S2 lookup, returning INT_MIN if
 + * the configuration is invalid.
   */
 -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
 -                               int inputsize, int stride, int outputsize)
 +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
 +                              bool ds, int iasize, int stride)
  {
 -    const int grainsize = stride + 3;
 -    int startsizecheck;
 -
 -    /*
 -     * Negative levels are usually not allowed...
 -     * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
 -     * begins with level -1.  Note that previous feature tests will have
 -     * eliminated this combination if it is not enabled.
 -     */
 -    if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
 -        return false;
 -    }
 -
 -    startsizecheck = inputsize - ((3 - level) * stride + grainsize);
 -    if (startsizecheck < 1 || startsizecheck > stride + 4) {
 -        return false;
 -    }
 +    int sl0, sl2, startlevel, granulebits, levels;
 +    int s1_min_iasize, s1_max_iasize;
 +    sl0 = extract32(tcr, 6, 2);
      if (is_aa64) {
 +        /*
 +         * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
 +         * get_phys_addr_lpae, that used aa64_va_parameters which apply
 +         * to aarch64.  If Stage1 is aarch32, the min_txsz is larger.
 +         * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
 +         * inputsize is 64 - 24 = 40.
 +         */
 +        if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
 +            goto fail;
 +        }
 +
-+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
++        /*
-+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
++         * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
-                               &phys_base) < 0) {
++         * so interleave AArch64.S2StartLevel.
--                warn_report("Failed to read NUMBER(phys_base)=");
++         */
-+                warn_report("Failed to read %s", prefix);
+         switch (stride) {
-             } else {
+-        case 13: /* 64KB Pages.  */
-                 s->dump_info.phys_base = phys_base;
+-            if (level == 0 || (level == 1 && outputsize <= 42)) {
 -                return false;
 +        case 9: /* 4KB */
 +            /* SL2 is RES0 unless DS=1 & 4KB granule. */
 +            sl2 = extract64(tcr, 33, 1);
 +            if (ds && sl2) {
 +                if (sl0 != 0) {
 +                    goto fail;
 +                }
 +                startlevel = -1;
 +            } else {
 +                startlevel = 2 - sl0;
 +                switch (sl0) {
 +                case 2:
 +                    if (arm_pamax(cpu) < 44) {
 +                        goto fail;
 +                    }
 +                    break;
 +                case 3:
 +                    if (!cpu_isar_feature(aa64_st, cpu)) {
 +                        goto fail;
 +                    }
 +                    startlevel = 3;
 +                    break;
 +                }
              }
+             break;
+-        case 11: /* 16KB Pages.  */
+-            if (level == 0 || (level == 1 && outputsize <= 40)) {
+-                return false;
++        case 11: /* 16KB */
++            switch (sl0) {
++            case 2:
++                if (arm_pamax(cpu) < 42) {
++                    goto fail;
++                }
++                break;
++            case 3:
++                if (!ds) {
++                    goto fail;
++                }
++                break;
+             }
++            startlevel = 3 - sl0;
+             break;
+-        case 9: /* 4KB Pages.  */
+-            if (level == 0 && outputsize <= 42) {
+-                return false;
++        case 13: /* 64KB */
++            switch (sl0) {
++            case 2:
++                if (arm_pamax(cpu) < 44) {
++                    goto fail;
++                }
++                break;
++            case 3:
++                goto fail;
+             }
++            startlevel = 3 - sl0;
+             break;
+         default:
+             g_assert_not_reached();
+         }
+-
+-        /* Inputsize checks.  */
+-        if (inputsize > outputsize &&
+-            (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
+-            /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
+-            return false;
+-        }
+     } else {
+-        /* AArch32 only supports 4KB pages. Assert on that.  */
++        /*
++         * Things are simpler for AArch32 EL2, with only 4k pages.
++         * There is no separate S2InvalidSL function, but AArch32.S2Walk
++         * begins with walkparms.sl0 in {'1x'}.
++         */
+         assert(stride == 9);
+-
+-        if (level == 0) {
+-            return false;
++        if (sl0 >= 2) {
++            goto fail;
+         }
++        startlevel = 2 - sl0;
+     }
+-    return true;
++
++    /* AArch{64,32}.S2InconsistentSL are functionally equivalent.  */
++    levels = 3 - startlevel;
++    granulebits = stride + 3;
++
++    s1_min_iasize = levels * stride + granulebits + 1;
++    s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
++
++    if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
++        return startlevel;
++    }
++
++ fail:
++    return INT_MIN;
+ }
+ /**
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
+          */
+         level = 4 - (inputsize - 4) / stride;
+     } else {
+-        /*
+-         * For stage 2 translations the starting level is specified by the
+-         * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
+-         */
+-        uint32_t sl0 = extract32(tcr, 6, 2);
+-        uint32_t sl2 = extract64(tcr, 33, 1);
+-        int32_t startlevel;
+-        bool ok;
+-
+-        /* SL2 is RES0 unless DS=1 & 4kb granule. */
+-        if (param.ds && stride == 9 && sl2) {
+-            if (sl0 != 0) {
+-                level = 0;
+-                goto do_translation_fault;
+-            }
+-            startlevel = -1;
+-        } else if (!aarch64 || stride == 9) {
+-            /* AArch32 or 4KB pages */
+-            startlevel = 2 - sl0;
+-
+-            if (cpu_isar_feature(aa64_st, cpu)) {
+-                startlevel &= 3;
+-            }
+-        } else {
+-            /* 16KB or 64KB pages */
+-            startlevel = 3 - sl0;
+-        }
+-
+-        /* Check that the starting level is valid. */
+-        ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
+-                                inputsize, stride, outputsize);
+-        if (!ok) {
++        int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
++                                            inputsize, stride);
++        if (startlevel == INT_MIN) {
++            level = 0;
+             goto do_translation_fault;
+         }
+         level = startlevel;
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+[PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images
-Add some assertions that if we're about to boot an AArch64 kernel,
+From: Ard Biesheuvel <ardb@kernel.org>
 the board code has not mistakenly set either secure_boot or
 secure_board_setup. It doesn't make sense to set secure_boot,
 because all AArch64 kernels must be booted in non-secure mode.
-It might in theory make sense to set secure_board_setup, but
+Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
-we don't currently support that, because only the AArch32
+format, using gzip compression for the payload.
 bootloader[] code calls this hook; bootloader_aarch64[] does not.
 Since we don't have a current need for this functionality, just
 assert that we don't try to use it. If it's needed we'll add
 it later.
+For doing EFI boot in QEMU, this is completely transparent, as the
+firmware or bootloader will take care of this. However, for direct
+kernel boot without firmware, we will lose the ability to boot such
+distro kernels unless we deal with the new format directly.
+EFI zboot images contain metadata in the header regarding the placement
+of the compressed payload inside the image, and the type of compression
+used. This means we can wire up the existing gzip support without too
+much hassle, by parsing the header and grabbing the payload from inside
+the loaded zboot image.
+Cc: Peter Maydell <peter.maydell@linaro.org>
+Cc: Alex Bennée <alex.bennee@linaro.org>
+Cc: Richard Henderson <richard.henderson@linaro.org>
+Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Message-id: 20230303160109.3626966-1-ardb@kernel.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+[PMM: tweaked comment formatting, fixed checkpatch nits]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 7 +++++++
+ include/hw/loader.h | 19 ++++++++++
-file changed, 7 insertions(+)
+ hw/arm/boot.c       |  6 +++
  hw/core/loader.c    | 91 +++++++++++++++++++++++++++++++++++++++++++++
 files changed, 116 insertions(+)
+diff --git a/include/hw/loader.h b/include/hw/loader.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/loader.h
++++ b/include/hw/loader.h
+@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
+                                   uint8_t **buffer);
+ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
++/**
++ * unpack_efi_zboot_image:
++ * @buffer: pointer to a variable holding the address of a buffer containing the
++ *          image
++ * @size: pointer to a variable holding the size of the buffer
++ *
++ * Check whether the buffer contains a EFI zboot image, and if it does, extract
++ * the compressed payload and decompress it into a new buffer. If successful,
++ * the old buffer is freed, and the *buffer and size variables pointed to by the
++ * function arguments are updated to refer to the newly populated buffer.
++ *
++ * Returns 0 if the image could not be identified as a EFI zboot image.
++ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
++ * unpacking failed for any reason.
++ * Returns the size of the decompressed payload if decompression was performed
++ * successfully.
++ */
++ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
++
+ #define ELF_LOAD_FAILED       -1
+ #define ELF_LOAD_NOT_ELF      -2
+ #define ELF_LOAD_WRONG_ARCH   -3
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/boot.c
 +++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
-                     } else {
+             return -1;
-                         env->pstate = PSTATE_MODE_EL1h;
+         }
-                     }
+         size = len;
-+                    /* AArch64 kernels never boot in secure mode */
++
-+                    assert(!info->secure_boot);
++        /* Unpack the image if it is a EFI zboot image */
-+                    /* This hook is only supported for AArch32 currently:
++        if (unpack_efi_zboot_image(&buffer, &size) < 0) {
-+                     * bootloader_aarch64[] will not call the hook, and
++            g_free(buffer);
-+                     * the code above has already dropped us into EL2 or EL1.
++            return -1;
-+                     */
++        }
-+                    assert(!info->secure_board_setup);
+     }
-                 }
+     /* check the arm64 magic header value -- very old kernels may not have it */
-                 /* Set to non-secure if not a secure boot */
+diff --git a/hw/core/loader.c b/hw/core/loader.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/loader.c
 +++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
      return bytes;
  }
 +/* The PE/COFF MS-DOS stub magic number */
 +#define EFI_PE_MSDOS_MAGIC        "MZ"
 +
 +/*
 + * The Linux header magic number for a EFI PE/COFF
 + * image targetting an unspecified architecture.
 + */
 +#define EFI_PE_LINUX_MAGIC        "\xcd\x23\x82\x81"
 +
 +/*
 + * Bootable Linux kernel images may be packaged as EFI zboot images, which are
 + * self-decompressing executables when loaded via EFI. The compressed payload
 + * can also be extracted from the image and decompressed by a non-EFI loader.
 + *
 + * The de facto specification for this format is at the following URL:
 + *
 + * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
 + *
 + * This definition is based on Linux upstream commit 29636a5ce87beba.
 + */
 +struct linux_efi_zboot_header {
 +    uint8_t     msdos_magic[2];         /* PE/COFF 'MZ' magic number */
 +    uint8_t     reserved0[2];
 +    uint8_t     zimg[4];                /* "zimg" for Linux EFI zboot images */
 +    uint32_t    payload_offset;         /* LE offset to compressed payload */
 +    uint32_t    payload_size;           /* LE size of the compressed payload */
 +    uint8_t     reserved1[8];
 +    char        compression_type[32];   /* Compression type, NUL terminated */
 +    uint8_t     linux_magic[4];         /* Linux header magic */
 +    uint32_t    pe_header_offset;       /* LE offset to the PE header */
 +};
 +
 +/*
 + * Check whether *buffer points to a Linux EFI zboot image in memory.
 + *
 + * If it does, attempt to decompress it to a new buffer, and free the old one.
 + * If any of this fails, return an error to the caller.
 + *
 + * If the image is not a Linux EFI zboot image, do nothing and return success.
 + */
 +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
 +{
 +    const struct linux_efi_zboot_header *header;
 +    uint8_t *data = NULL;
 +    int ploff, plsize;
 +    ssize_t bytes;
 +
 +    /* ignore if this is too small to be a EFI zboot image */
 +    if (*size < sizeof(*header)) {
 +        return 0;
 +    }
 +
 +    header = (struct linux_efi_zboot_header *)*buffer;
 +
 +    /* ignore if this is not a Linux EFI zboot image */
 +    if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
 +        memcmp(&header->zimg, "zimg", 4) != 0 ||
 +        memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
 +        return 0;
 +    }
 +
 +    if (strcmp(header->compression_type, "gzip") != 0) {
 +        fprintf(stderr,
 +                "unable to handle EFI zboot image with \"%.*s\" compression\n",
 +                (int)sizeof(header->compression_type) - 1,
 +                header->compression_type);
 +        return -1;
 +    }
 +
 +    ploff = ldl_le_p(&header->payload_offset);
 +    plsize = ldl_le_p(&header->payload_size);
 +
 +    if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
 +        fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
 +        return -1;
 +    }
 +
 +    data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
 +    bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
 +    if (bytes < 0) {
 +        fprintf(stderr, "failed to decompress EFI zboot image\n");
 +        g_free(data);
 +        return -1;
 +    }
 +
 +    g_free(*buffer);
 +    *buffer = g_realloc(data, bytes);
 +    *size = bytes;
 +    return bytes;
 +}
 +
  /*
   * Functions for reboot-persistent memory regions.
   *  - used for vga bios and option roms.
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
+[PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
-Now we have separate types for BCM2386 and BCM2387, we might as well
+From: qianfan Zhao <qianfanguijin@163.com>
 just hard-code the CPU type they use rather than having it passed
 through as an object property. This then lets us put the initialization
 of the CPU object in init rather than realize.
-Note that this change means that it's no longer possible on
+TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
-the command line to use -cpu to ask for a different kind of
+register on SUN6i based SoCs, we should lower interrupt when the guest
-CPU than the SoC supports. This was never a supported thing to
+set this bit.
 do anyway; we were just not sanity-checking the command line.
-This does require us to only build the bcm2837 object on
+The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
-TARGET_AARCH64 configs, since otherwise it won't instantiate
+device connected on the i2c bus, next is the trace log:
 due to the missing cortex-a53 device and "make check" will fail.
+allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
+allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
+allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
+allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
+allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
+allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
+allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
+...
+Fix it.
+Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 24 +++++++++++++++---------
+ include/hw/i2c/allwinner-i2c.h |  6 ++++++
- hw/arm/raspi.c   |  2 --
+ hw/i2c/allwinner-i2c.c         | 26 ++++++++++++++++++++++++--
-files changed, 15 insertions(+), 11 deletions(-)
+files changed, 30 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/include/hw/i2c/allwinner-i2c.h
-+++ b/hw/arm/bcm2836.c
++++ b/include/hw/i2c/allwinner-i2c.h
 @@ -XXX,XX +XXX,XX @@
+ #include "qom/object.h"
- struct BCM283XInfo {
-     const char *name;
+ #define TYPE_AW_I2C "allwinner.i2c"
-+    const char *cpu_type;
++
-     int clusterid;
++/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
 +#define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
 +
  OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
  #define AW_I2C_MEM_SIZE         0x24
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
      uint8_t srst;
      uint8_t efr;
      uint8_t lcr;
 +
 +    bool irq_clear_inverted;
  };
- static const BCM283XInfo bcm283x_socs[] = {
+ #endif /* ALLWINNER_I2C_H */
-     {
+diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
-         .name = TYPE_BCM2836,
+index XXXXXXX..XXXXXXX 100644
-+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
+--- a/hw/i2c/allwinner-i2c.c
-         .clusterid = 0xf,
++++ b/hw/i2c/allwinner-i2c.c
-     },
+@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
-+#ifdef TARGET_AARCH64
+                 s->stat = STAT_FROM_STA(STAT_IDLE);
-     {
+                 s->cntr &= ~TWI_CNTR_M_STP;
-         .name = TYPE_BCM2837,
+             }
-+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
+-            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
-         .clusterid = 0x0,
+-                /* Interrupt flag cleared */
-     },
++
-+#endif
++            if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
 +                /* Write 0 to clear this flag */
 +                qemu_irq_lower(s->irq);
 +            } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
 +                /* Write 1 to clear this flag */
 +                s->cntr &= ~TWI_CNTR_INT_FLAG;
                  qemu_irq_lower(s->irq);
              }
 +
              if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
                  if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
                      s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
      .class_init = allwinner_i2c_class_init,
  };
- static void bcm2836_init(Object *obj)
++static void allwinner_i2c_sun6i_init(Object *obj)
 +{
 +    AWI2CState *s = AW_I2C(obj);
 +
 +    s->irq_clear_inverted = true;
 +}
 +
 +static const TypeInfo allwinner_i2c_sun6i_type_info = {
 +    .name = TYPE_AW_I2C_SUN6I,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(AWI2CState),
 +    .instance_init = allwinner_i2c_sun6i_init,
 +    .class_init = allwinner_i2c_class_init,
 +};
 +
  static void allwinner_i2c_register_types(void)
  {
-     BCM283XState *s = BCM283X(obj);
+     type_register_static(&allwinner_i2c_type_info);
-+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
++    type_register_static(&allwinner_i2c_sun6i_type_info);
 +    const BCM283XInfo *info = bc->info;
 +    int n;
 +
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
 +        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 +                          info->cpu_type);
 +        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 +                                  &error_abort);
 +    }
      object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
      object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      /* common peripherals from bcm2835 */
 -    obj = OBJECT(dev);
 -    for (n = 0; n < BCM283X_NCPUS; n++) {
 -        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 -                          s->cpu_type);
 -        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 -                                  &error_abort);
 -    }
 -
      obj = object_property_get_link(OBJECT(dev), "ram", &err);
      if (obj == NULL) {
          error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
  }
- static Property bcm2836_props[] = {
+ type_init(allwinner_i2c_register_types)
 -    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
      DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                         BCM283X_NCPUS),
      DEFINE_PROP_END_OF_LIST()
 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/raspi.c
 +++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
      /* Setup the SOC */
      object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                     &error_abort);
 -    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
 -                            &error_abort);
      object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                              &error_abort);
      int board_rev = version == 3 ? 0xa02082 : 0xa21041;
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
+[PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices
-The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
+From: qianfan Zhao <qianfanguijin@163.com>
 CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
 is required for Linux to boot.
+Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
+The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
+control register's INT_FLAG bit.
+Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 11 +++++++----
+ include/hw/arm/allwinner-h3.h |  6 ++++++
-file changed, 7 insertions(+), 4 deletions(-)
+ hw/arm/allwinner-h3.c         | 29 +++++++++++++++++++++++++----
 files changed, 31 insertions(+), 4 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/include/hw/arm/allwinner-h3.h
-+++ b/hw/arm/bcm2836.c
++++ b/include/hw/arm/allwinner-h3.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ enum {
+     AW_H3_DEV_UART3,
- struct BCM283XInfo {
+     AW_H3_DEV_EMAC,
-     const char *name;
+     AW_H3_DEV_TWI0,
-+    int clusterid;
++    AW_H3_DEV_TWI1,
 +    AW_H3_DEV_TWI2,
      AW_H3_DEV_DRAMCOM,
      AW_H3_DEV_DRAMCTL,
      AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ enum {
      AW_H3_DEV_GIC_VCPU,
      AW_H3_DEV_RTC,
      AW_H3_DEV_CPUCFG,
 +    AW_H3_DEV_R_TWI,
      AW_H3_DEV_SDRAM
  };
- static const BCM283XInfo bcm283x_socs[] = {
+@@ -XXX,XX +XXX,XX @@ struct AwH3State {
-     {
+     AwSidState sid;
-         .name = TYPE_BCM2836,
+     AwSdHostState mmc0;
-+        .clusterid = 0xf,
+     AWI2CState i2c0;
-     },
++    AWI2CState i2c1;
-     {
++    AWI2CState i2c2;
-         .name = TYPE_BCM2837,
++    AWI2CState r_twi;
-+        .clusterid = 0x0,
+     AwSun8iEmacState emac;
-     },
+     AwRtcState rtc;
      GICState gic;
 diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/allwinner-h3.c
 +++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
      [AW_H3_DEV_UART2]      = 0x01c28800,
      [AW_H3_DEV_UART3]      = 0x01c28c00,
      [AW_H3_DEV_TWI0]       = 0x01c2ac00,
 +    [AW_H3_DEV_TWI1]       = 0x01c2b000,
 +    [AW_H3_DEV_TWI2]       = 0x01c2b400,
      [AW_H3_DEV_EMAC]       = 0x01c30000,
      [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
      [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
      [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
      [AW_H3_DEV_RTC]        = 0x01f00000,
      [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
 +    [AW_H3_DEV_R_TWI]      = 0x01f02400,
      [AW_H3_DEV_SDRAM]      = 0x40000000
  };
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
- static void bcm2836_realize(DeviceState *dev, Error **errp)
+     { "uart1",     0x01c28400, 1 * KiB },
- {
+     { "uart2",     0x01c28800, 1 * KiB },
-     BCM283XState *s = BCM283X(dev);
+     { "uart3",     0x01c28c00, 1 * KiB },
-+    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
+-    { "twi1",      0x01c2b000, 1 * KiB },
-+    const BCM283XInfo *info = bc->info;
+-    { "twi2",      0x01c2b400, 1 * KiB },
-     Object *obj;
+     { "scr",       0x01c2c400, 1 * KiB },
-     Error *err = NULL;
+     { "gpu",       0x01c40000, 64 * KiB },
-     int n;
+     { "hstmr",     0x01c60000, 4 * KiB },
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
+     { "r_prcm",    0x01f01400, 1 * KiB },
+     { "r_twd",     0x01f01800, 1 * KiB },
-     for (n = 0; n < BCM283X_NCPUS; n++) {
+     { "r_cir-rx",  0x01f02000, 1 * KiB },
--        /* Mirror bcm2836, which has clusterid set to 0xf
+-    { "r_twi",     0x01f02400, 1 * KiB },
--         * TODO: this should be converted to a property of ARM_CPU
+     { "r_uart",    0x01f02800, 1 * KiB },
--         */
+     { "r_pio",     0x01f02c00, 1 * KiB },
--        s->cpus[n].mp_affinity = 0xF00 | n;
+     { "r_pwm",     0x01f03800, 1 * KiB },
-+        /* TODO: this should be converted to a property of ARM_CPU */
+@@ -XXX,XX +XXX,XX @@ enum {
-+        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
+     AW_H3_GIC_SPI_UART2     =  2,
+     AW_H3_GIC_SPI_UART3     =  3,
-         /* set periphbase/CBAR value for CPU-local registers */
+     AW_H3_GIC_SPI_TWI0      =  6,
-         object_property_set_int(OBJECT(&s->cpus[n]),
++    AW_H3_GIC_SPI_TWI1      =  7,
 +    AW_H3_GIC_SPI_TWI2      =  8,
      AW_H3_GIC_SPI_TIMER0    = 18,
      AW_H3_GIC_SPI_TIMER1    = 19,
 +    AW_H3_GIC_SPI_R_TWI     = 44,
      AW_H3_GIC_SPI_MMC0      = 60,
      AW_H3_GIC_SPI_EHCI0     = 72,
      AW_H3_GIC_SPI_OHCI0     = 73,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
 -    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
 +    object_initialize_child(obj, "twi0",  &s->i2c0,  TYPE_AW_I2C_SUN6I);
 +    object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
 +    object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
 +    object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
  }
  static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
                         qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
 +    sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
 +
      /* Unimplemented devices */
      for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
          create_unimplemented_device(unimplemented[i].device_name,
 --
-.16.2
+.34.1

Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3

----------------------------------------------------------------
Andrey Smirnov (2):
      char: i.MX: Simplify imx_update()
      char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
      fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
      hw/arm/bcm2386: Fix parent type of bcm2386
      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
      hw/arm/bcm2836: Create proper bcm2837 device
      hw/arm/bcm2836: Use correct affinity values for BCM2837
      hw/arm/bcm2836: Hardcode correct CPU type
      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
      dump: Update correct kdump phys_base field for AArch64

From: Guenter Roeck <linux@roeck-us.net>

The sabrelite machine model used by qemu-system-arm is based on the
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
controller which is supported in QEMU using the imx_fec.c module
(actually called imx.enet for this model.)

The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
imx.enet device like this:

#define FSL_IMX6_ENET_MAC_1588_IRQ 118
 #define FSL_IMX6_ENET_MAC_IRQ 119

According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
interrupts are as follows.

150 ENET MAC 0 IRQ
151 ENET MAC 0 1588 Timer interrupt

where

150 - 32 == 118
151 - 32 == 119

In other words, the vector definitions in the fsl-imx6.h file are reversed.

Fixing the interrupts alone causes problems with older Linux kernels:
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
error handling. This is a Linux kernel problem, not a qemu problem:
the Linux kernel only worked by accident since it requested both interrupts.

For backward compatibility, generate the Ethernet interrupt on both interrupt
lines. This was shown to work from all Linux kernel releases starting with
v3.16.

Link: https://bugs.launchpad.net/qemu/+bug/1753309
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  4 ++--
 hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
 #define FSL_IMX6_HDMI_MASTER_IRQ 115
 #define FSL_IMX6_HDMI_CEC_IRQ 116
 #define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
-#define FSL_IMX6_ENET_MAC_IRQ 119
+#define FSL_IMX6_ENET_MAC_IRQ 118
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
 #define FSL_IMX6_PCIE1_IRQ 120
 #define FSL_IMX6_PCIE2_IRQ 121
 #define FSL_IMX6_PCIE3_IRQ 122
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
 
 static void imx_eth_update(IMXFECState *s)
 {
-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+    /*
+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+     * interrupts swapped. This worked with older versions of Linux (4.14
+     * and older) since Linux associated both interrupt lines with Ethernet
+     * MAC interrupts. Specifically,
+     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
+     *   timer interrupts. Those versions of Linux fail with versions of QEMU
+     *   with swapped interrupt assignments.
+     * - In linux 4.14, both interrupt lines were registered with the Ethernet
+     *   MAC interrupt handler. As a result, all versions of qemu happen to
+     *   work, though that is accidental.
+     * - In Linux 4.9 and older, the timer interrupt was registered directly
+     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
+     *   redirected to a GPIO interrupt to work around erratum ERR006687.
+     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
+     *   interrupt never fired since IOMUX is currently not supported in qemu.
+     *   Linux instead received MAC interrupts on the timer interrupt.
+     *   As a result, qemu versions with the swapped interrupt assignment work,
+     *   albeit accidentally, but qemu versions with the correct interrupt
+     *   assignment fail.
+     *
+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
+     * interrrupts on both interrupt lines. This should be changed if and when
+     * qemu supports IOMUX.
+     */
+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
         qemu_set_irq(s->irq[1], 1);
     } else {
         qemu_set_irq(s->irq[1], 0);
-- 
2.16.2

From: Wei Huang <wei@redhat.com>

For guest kernel that supports KASLR, the load address can change every
time when guest VM runs. To find the physical base address correctly,
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
However this string pattern is only available on x86_64. AArch64 uses a
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
QEMU dump uses the correct string on AArch64.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 dump.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/dump.c b/dump.c
index XXXXXXX..XXXXXXX 100644
--- a/dump.c
+++ b/dump.c
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
 
     lines = g_strsplit((char *)vmci, "\n", -1);
     for (i = 0; lines[i]; i++) {
-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+        const char *prefix = NULL;
+
+        if (s->dump_info.d_machine == EM_X86_64) {
+            prefix = "NUMBER(phys_base)=";
+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+            prefix = "NUMBER(PHYS_OFFSET)=";
+        }
+
+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
                               &phys_base) < 0) {
-                warn_report("Failed to read NUMBER(phys_base)=");
+                warn_report("Failed to read %s", prefix);
             } else {
                 s->dump_info.phys_base = phys_base;
             }
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Code of imx_update() is slightly confusing since the "flags" variable
doesn't really corespond to anything in real hardware and server as a
kitchensink accumulating events normally reported via USR1 and USR2
registers.

Change the code to explicitly evaluate state of interrupts reported
via USR1 and USR2 against corresponding masking bits and use the to
detemine if IRQ line should be asserted or not.

NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
reasons:

1. Emulation code implements a single character FIFO, so this flag
       will always be set since characters are trasmitted as a part of
       the code emulating "push" into the FIFO

2. imx_update() is really just a function doing ORing and maksing
       of reported events, so checking for UTS1_TXEMPTY should happen,
       if it's ever really needed should probably happen outside of
       it.

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/imx_serial.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
 
 static void imx_update(IMXSerialState *s)
 {
-    uint32_t flags;
+    uint32_t usr1;
+    uint32_t usr2;
+    uint32_t mask;
 
-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
-    if (s->ucr1 & UCR1_TXMPTYEN) {
-        flags |= (s->uts1 & UTS1_TXEMPTY);
-    } else {
-        flags &= ~USR1_TRDY;
-    }
+    /*
+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+     * UCR1, so we can get away with something as simple as the
+     * following:
+     */
+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+    /*
+     * Bits that we want in USR2 are not as conveniently laid out,
+     * unfortunately.
+     */
+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    usr2 = s->usr2 & mask;
 
-    qemu_set_irq(s->irq, !!flags);
+    qemu_set_irq(s->irq, usr1 || usr2);
 }
 
 static void imx_serial_reset(IMXSerialState *s)
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.

Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/imx_serial.h |  3 +++
 hw/char/imx_serial.c         | 20 +++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -XXX,XX +XXX,XX @@
 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
 #define UCR2_SRST       (1<<0)    /* Reset complete */
 
+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+
 #define UTS1_TXEMPTY    (1<<6)
 #define UTS1_RXEMPTY    (1<<5)
 #define UTS1_TXFULL     (1<<4)
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
     uint32_t ubmr;
     uint32_t ubrc;
     uint32_t ucr3;
+    uint32_t ucr4;
 
     qemu_irq irq;
     CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
 
 static const VMStateDescription vmstate_imx_serial = {
     .name = TYPE_IMX_SERIAL,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_INT32(readbuff, IMXSerialState),
         VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
         VMSTATE_UINT32(ubmr, IMXSerialState),
         VMSTATE_UINT32(ubrc, IMXSerialState),
         VMSTATE_UINT32(ucr3, IMXSerialState),
+        VMSTATE_UINT32(ucr4, IMXSerialState),
         VMSTATE_END_OF_LIST()
     },
 };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
      * unfortunately.
      */
     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    /*
+     * TCEN and TXDC are both bit 3
+     */
+    mask |= s->ucr4 & UCR4_TCEN;
+
     usr2 = s->usr2 & mask;
 
     qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
         return s->ucr3;
 
     case 0x23: /* UCR4 */
+        return s->ucr4;
+
     case 0x29: /* BRM Incremental */
         return 0x0; /* TODO */
 
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
              * qemu_chr_fe_write and background I/O callbacks */
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->usr1 &= ~USR1_TRDY;
+            s->usr2 &= ~USR2_TXDC;
             imx_update(s);
             s->usr1 |= USR1_TRDY;
+            s->usr2 |= USR2_TXDC;
             imx_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
         s->ucr3 = value & 0xffff;
         break;
 
-    case 0x2d: /* UTS1 */
     case 0x23: /* UCR4 */
+        s->ucr4 = value & 0xffff;
+        imx_update(s);
+        break;
+
+    case 0x2d: /* UTS1 */
         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
         /* TODO */
-- 
2.16.2

For the rpi1 and 2 we want to boot the Linux kernel via some
custom setup code that makes sure that the SMC instruction
acts as a no-op, because it's used for cache maintenance.
The rpi3 boots AArch64 kernels, which don't need SMC for
cache maintenance and always expect to be booted non-secure.
Don't fill in the aarch32-specific parts of the binfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     binfo.board_id = raspi_boardid[version];
     binfo.ram_size = ram_size;
     binfo.nb_cpus = smp_cpus;
-    binfo.board_setup_addr = BOARDSETUP_ADDR;
-    binfo.write_board_setup = write_board_setup;
-    binfo.secure_board_setup = true;
-    binfo.secure_boot = true;
+
+    if (version <= 2) {
+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         * mode before booting a kernel (to set up the SMC vectors so
+         * that we get a no-op SMC; this is used by Linux to call the
+         * firmware for some cache maintenance operations.
+         * The rpi3 doesn't need this.
+         */
+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+        binfo.write_board_setup = write_board_setup;
+        binfo.secure_board_setup = true;
+        binfo.secure_boot = true;
+    }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-- 
2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,
the board code has not mistakenly set either secure_boot or
secure_board_setup. It doesn't make sense to set secure_boot,
because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but
we don't currently support that, because only the AArch32
bootloader[] code calls this hook; bootloader_aarch64[] does not.
Since we don't have a current need for this functionality, just
assert that we don't try to use it. If it's needed we'll add
it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     } else {
                         env->pstate = PSTATE_MODE_EL1h;
                     }
+                    /* AArch64 kernels never boot in secure mode */
+                    assert(!info->secure_boot);
+                    /* This hook is only supported for AArch32 currently:
+                     * bootloader_aarch64[] will not call the hook, and
+                     * the code above has already dropped us into EL2 or EL1.
+                     */
+                    assert(!info->secure_board_setup);
                 }
 
                 /* Set to non-secure if not a secure boot */
-- 
2.16.2

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

The TypeInfo and state struct for bcm2386 disagree about what the
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
but the BCM2386State struct only defines the parent_obj field
as DeviceState. This would have caused problems if anything
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
need any of the additional functionality TYPE_SYS_BUS_DEVICE
provides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo bcm2836_type_info = {
     .name = TYPE_BCM2836,
-    .parent = TYPE_SYS_BUS_DEVICE,
+    .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM2836State),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
-- 
2.16.2

Our BCM2836 type is really a generic one that can be any of
the bcm283x family. Rename it accordingly. We change only
the names which are visible via the header file to the
rest of the QEMU code, leaving private function names
in bcm2836.c as they are.

This is a preliminary to making bcm283x be an abstract
parent class to specific types for the bcm2836 and bcm2837.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 12 ++++++------
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           | 16 ++++++++--------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
-#define TYPE_BCM2836 "bcm2836"
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+#define TYPE_BCM283X "bcm283x"
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 
-#define BCM2836_NCPUS 4
+#define BCM283X_NCPUS 4
 
-typedef struct BCM2836State {
+typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
     char *cpu_type;
     uint32_t enabled_cpus;
 
-    ARMCPU cpus[BCM2836_NCPUS];
+    ARMCPU cpus[BCM283X_NCPUS];
     BCM2836ControlState control;
     BCM2835PeripheralState peripherals;
-} BCM2836State;
+} BCM283XState;
 
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 static void bcm2836_init(Object *obj)
 {
-    BCM2836State *s = BCM2836(obj);
+    BCM283XState *s = BCM283X(obj);
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
 
 static void bcm2836_realize(DeviceState *dev, Error **errp)
 {
-    BCM2836State *s = BCM2836(dev);
+    BCM283XState *s = BCM283X(dev);
     Object *obj;
     Error *err = NULL;
     int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     /* common peripherals from bcm2835 */
 
     obj = OBJECT(dev);
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                           s->cpu_type);
         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         /* Mirror bcm2836, which has clusterid set to 0xf
          * TODO: this should be converted to a property of ARM_CPU
          */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                       BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 }
 
 static const TypeInfo bcm2836_type_info = {
-    .name = TYPE_BCM2836,
+    .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
-    .instance_size = sizeof(BCM2836State),
+    .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
 
 typedef struct RasPiState {
-    BCM2836State soc;
+    BCM283XState soc;
     MemoryRegion ram;
 } RasPiState;
 
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
 }
 DEFINE_MACHINE("raspi3", raspi3_machine_init)
-- 
2.16.2

The bcm2837 is pretty similar to the bcm2836, but it does have
some differences. Notably, the MPIDR affinity aff1 values it
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
uses, and if this is wrong Linux will not boot.

Rather than trying to have one device with properties that
configure it differently for the two cases, create two
separate QOM devices for the two SoCs. We use the same approach
as hw/arm/aspeed_soc.c and share code and have a data table
that might differ per-SoC. For the moment the two types don't
actually have different behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
 hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
 hw/arm/raspi.c           |  3 ++-
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 
 #define BCM283X_NCPUS 4
 
+/* These type names are for specific SoCs; other than instantiating
+ * them, code using these devices should always handle them via the
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ */
+#define TYPE_BCM2836 "bcm2836"
+#define TYPE_BCM2837 "bcm2837"
+
 typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
     BCM2835PeripheralState peripherals;
 } BCM283XState;
 
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+    DeviceClass parent_class;
+    const BCM283XInfo *info;
+} BCM283XClass;
+
+#define BCM283X_CLASS(klass) \
+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
 #define BCM2836_CONTROL_BASE    0x40000000
 
+struct BCM283XInfo {
+    const char *name;
+};
+
+static const BCM283XInfo bcm283x_socs[] = {
+    {
+        .name = TYPE_BCM2836,
+    },
+    {
+        .name = TYPE_BCM2837,
+    },
+};
+
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void bcm2836_class_init(ObjectClass *oc, void *data)
+static void bcm283x_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
+    BCM283XClass *bc = BCM283X_CLASS(oc);
 
-    dc->props = bcm2836_props;
+    bc->info = data;
     dc->realize = bcm2836_realize;
+    dc->props = bcm2836_props;
 }
 
-static const TypeInfo bcm2836_type_info = {
+static const TypeInfo bcm283x_type_info = {
     .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
-    .class_init = bcm2836_class_init,
+    .class_size = sizeof(BCM283XClass),
+    .abstract = true,
 };
 
 static void bcm2836_register_types(void)
 {
-    type_register_static(&bcm2836_type_info);
+    int i;
+
+    type_register_static(&bcm283x_type_info);
+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+        TypeInfo ti = {
+            .name = bcm283x_socs[i].name,
+            .parent = TYPE_BCM283X,
+            .class_init = bcm283x_class_init,
+            .class_data = (void *) &bcm283x_socs[i],
+        };
+        type_register(&ti);
+    }
 }
 
 type_init(bcm2836_register_types)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+    object_initialize(&s->soc, sizeof(s->soc),
+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
-- 
2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
is required for Linux to boot.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Now we have separate types for BCM2386 and BCM2387, we might as well
just hard-code the CPU type they use rather than having it passed
through as an object property. This then lets us put the initialization
of the CPU object in init rather than realize.

Note that this change means that it's no longer possible on
the command line to use -cpu to ask for a different kind of
CPU than the SoC supports. This was never a supported thing to
do anyway; we were just not sanity-checking the command line.

This does require us to only build the bcm2837 object on
TARGET_AARCH64 configs, since otherwise it won't instantiate
due to the missing cortex-a53 device and "make check" will fail.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 24 +++++++++++++++---------
 hw/arm/raspi.c   |  2 --
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 struct BCM283XInfo {
     const char *name;
+    const char *cpu_type;
     int clusterid;
 };
 
 static const BCM283XInfo bcm283x_socs[] = {
     {
         .name = TYPE_BCM2836,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
         .clusterid = 0xf,
     },
+#ifdef TARGET_AARCH64
     {
         .name = TYPE_BCM2837,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
         .clusterid = 0x0,
     },
+#endif
 };
 
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+    const BCM283XInfo *info = bc->info;
+    int n;
+
+    for (n = 0; n < BCM283X_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          info->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
-    obj = OBJECT(dev);
-    for (n = 0; n < BCM283X_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          s->cpu_type);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
-
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                        BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
-                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
-- 
2.16.2

The raspi3 has AArch64 CPUs, which means that our smpboot
code for keeping the secondary CPUs in a pen needs to have
a version for A64 as well as A32. Without this, the
secondary CPUs go into an infinite loop of taking undefined
instruction exceptions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
 
 /* Table of Linux board IDs for different Pi versions */
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                        info->smp_loader_start);
 }
 
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+     * The mechanism for doing the spin-table is also entirely different.
+     * We must have four 64-bit fields at absolute addresses
+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+     * our CPUs, and which we must ensure are zero initialized before
+     * the primary CPU goes into the kernel. We put these variables inside
+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+     */
+    static const uint32_t smpboot[] = {
+        0xd2801b05, /*        mov     x5, 0xd8 */
+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+        0x924004c6, /*        and     x6, x6, #0x3 */
+        0xd503205f, /* spin:  wfe */
+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+        0xb4ffffc4, /*        cbz     x4, spin */
+        0xd2800000, /*        mov     x0, #0x0 */
+        0xd2800001, /*        mov     x1, #0x0 */
+        0xd2800002, /*        mov     x2, #0x0 */
+        0xd2800003, /*        mov     x3, #0x0 */
+        0xd61f0080, /*        br      x4 */
+    };
+
+    static const uint64_t spintables[] = {
+        0, 0, 0, 0
+    };
+
+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
+                       info->smp_loader_start);
+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+                       SPINTABLE_ADDR);
+}
+
 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
         binfo.smp_loader_start = SMPBOOT_ADDR;
-        binfo.write_secondary_boot = write_smpboot;
+        if (version == 2) {
+            binfo.write_secondary_boot = write_smpboot;
+        } else {
+            binfo.write_secondary_boot = write_smpboot64;
+        }
         binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
-- 
2.16.2

The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:

Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306

for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:

hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * allwinner-h3: Fix I2C controller model for Sun6i SoCs
 * allwinner-h3: Add missing i2c controllers
 * Expose M-profile system registers to gdbstub
 * Expose pauth information to gdbstub
 * Support direct boot for Linux/arm64 EFI zboot images
 * Fix incorrect stage 2 MMU setup validation

----------------------------------------------------------------
Ard Biesheuvel (1):
      hw: arm: Support direct boot for Linux/arm64 EFI zboot images

David Reiss (2):
      target/arm: Export arm_v7m_mrs_control
      target/arm: Export arm_v7m_get_sp_ptr

Richard Henderson (16):
      target/arm: Normalize aarch64 gdbstub get/set function names
      target/arm: Unexport arm_gen_dynamic_sysreg_xml
      target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
      target/arm: Split out output_vector_union_type
      target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
      target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
      target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
      target/arm: Add name argument to output_vector_union_type
      target/arm: Simplify iteration over bit widths
      target/arm: Create pauth_ptr_mask
      target/arm: Implement gdbstub pauth extension
      target/arm: Implement gdbstub m-profile systemreg and secext
      target/arm: Handle m-profile in arm_is_secure
      target/arm: Stub arm_hcr_el2_eff for m-profile
      target/arm: Diagnose incorrect usage of arm_is_secure subroutines
      target/arm: Rewrite check_s2_mmu_setup

qianfan Zhao (2):
      hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
      hw: arm: allwinner-h3: Fix and complete H3 i2c devices

From: Richard Henderson <richard.henderson@linaro.org>

Make the form of the function names between fp and sve the same:
  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
  - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 8 ++++----
 target/arm/gdbstub.c   | 9 +++++----
 target/arm/gdbstub64.c | 8 ++++----
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
 }
 
 #ifdef TARGET_AARCH64
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
          */
 #ifdef TARGET_AARCH64
         if (isar_feature_aa64_sve(&cpu->isar)) {
-            gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
-                                     arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
+            int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
+            gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
+                                     aarch64_gdb_set_sve_reg, nreg,
                                      "sve-registers.xml", 0);
         } else {
-            gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
-                                     aarch64_fpu_gdb_set_reg,
+            gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
+                                     aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
 #endif
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     return 0;
 }
 
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
 {
     switch (reg) {
     case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
     }
 }
 
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     switch (reg) {
     case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
     }
 }
 
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
 {
     ARMCPU *cpu = env_archcpu(env);
 
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
     return 0;
 }
 
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     ARMCPU *cpu = env_archcpu(env);
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This function is not used outside gdbstub.c.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     | 1 -
 target/arm/gdbstub.c | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  * Helpers to dynamically generates XML descriptions of the sysregs
  * and SVE registers. Returns the number of registers in each set.
  */
-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 
 /* Returns the dynamically generated XML for the gdb stub.
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
     }
 }
 
-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     GString *s = g_string_new(NULL);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The function is only used for aarch64, so move it to the
file that has the other aarch64 gdbstub stuff.  Move the
declaration to internals.h.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |   6 ---
 target/arm/internals.h |   1 +
 target/arm/gdbstub.c   | 120 -----------------------------------------
 target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 119 insertions(+), 126 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
-/*
- * Helpers to dynamically generates XML descriptions of the sysregs
- * and SVE registers. Returns the number of registers in each set.
- */
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
-
 /* Returns the dynamically generated XML for the gdb stub.
  * Returns a pointer to the XML contents for the specified XML file or NULL
  * if the XML name doesn't match the predefined one.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
 }
 
 #ifdef TARGET_AARCH64
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
-struct TypeSize {
-    const char *gdb_type;
-    int  size;
-    const char sz, suffix;
-};
-
-static const struct TypeSize vec_lanes[] = {
-    /* quads */
-    { "uint128", 128, 'q', 'u' },
-    { "int128", 128, 'q', 's' },
-    /* 64 bit */
-    { "ieee_double", 64, 'd', 'f' },
-    { "uint64", 64, 'd', 'u' },
-    { "int64", 64, 'd', 's' },
-    /* 32 bit */
-    { "ieee_single", 32, 's', 'f' },
-    { "uint32", 32, 's', 'u' },
-    { "int32", 32, 's', 's' },
-    /* 16 bit */
-    { "ieee_half", 16, 'h', 'f' },
-    { "uint16", 16, 'h', 'u' },
-    { "int16", 16, 'h', 's' },
-    /* bytes */
-    { "uint8", 8, 'b', 'u' },
-    { "int8", 8, 'b', 's' },
-};
-
-
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    GString *s = g_string_new(NULL);
-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-    g_autoptr(GString) ts = g_string_new("");
-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
-    g_string_printf(s, "<?xml version=\"1.0\"?>");
-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
-
-    /* First define types and totals in a whole VL */
-    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
-        g_string_append_printf(s,
-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-                               ts->str, vec_lanes[i].gdb_type, count);
-    }
-    /*
-     * Now define a union for each size group containing unsigned and
-     * signed and potentially float versions of each size from 128 to
-     * 8 bits.
-     */
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
-        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
-            if (vec_lanes[j].size == bits) {
-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-                                       vec_lanes[j].suffix,
-                                       vec_lanes[j].sz, vec_lanes[j].suffix);
-            }
-        }
-        g_string_append(s, "</union>");
-    }
-    /* And now the final union of unions */
-    g_string_append(s, "<union id=\"svev\">");
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
-                               suf[i], suf[i]);
-    }
-    g_string_append(s, "</union>");
-
-    /* Finally the sve prefix type */
-    g_string_append_printf(s,
-                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
-
-    /* Then define each register in parts for each vq */
-    for (i = 0; i < 32; i++) {
-        g_string_append_printf(s,
-                               "<reg name=\"z%d\" bitsize=\"%d\""
-                               " regnum=\"%d\" type=\"svev\"/>",
-                               i, reg_width, base_reg++);
-        info->num++;
-    }
-    /* fpscr & status registers */
-    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
-                           " regnum=\"%d\" group=\"float\""
-                           " type=\"int\"/>", base_reg++);
-    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
-                           " regnum=\"%d\" group=\"float\""
-                           " type=\"int\"/>", base_reg++);
-    info->num += 2;
-
-    for (i = 0; i < 16; i++) {
-        g_string_append_printf(s,
-                               "<reg name=\"p%d\" bitsize=\"%d\""
-                               " regnum=\"%d\" type=\"svep\"/>",
-                               i, cpu->sve_max_vq * 16, base_reg++);
-        info->num++;
-    }
-    g_string_append_printf(s,
-                           "<reg name=\"ffr\" bitsize=\"%d\""
-                           " regnum=\"%d\" group=\"vector\""
-                           " type=\"svep\"/>",
-                           cpu->sve_max_vq * 16, base_reg++);
-    g_string_append_printf(s,
-                           "<reg name=\"vg\" bitsize=\"64\""
-                           " regnum=\"%d\" type=\"int\"/>",
-                           base_reg++);
-    info->num += 2;
-    g_string_append_printf(s, "</feature>");
-    cpu->dyn_svereg_xml.desc = g_string_free(s, false);
-
-    return cpu->dyn_svereg_xml.num;
-}
-
-
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
     ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
 
     return 0;
 }
+
+struct TypeSize {
+    const char *gdb_type;
+    short size;
+    char sz, suffix;
+};
+
+static const struct TypeSize vec_lanes[] = {
+    /* quads */
+    { "uint128", 128, 'q', 'u' },
+    { "int128", 128, 'q', 's' },
+    /* 64 bit */
+    { "ieee_double", 64, 'd', 'f' },
+    { "uint64", 64, 'd', 'u' },
+    { "int64", 64, 'd', 's' },
+    /* 32 bit */
+    { "ieee_single", 32, 's', 'f' },
+    { "uint32", 32, 's', 'u' },
+    { "int32", 32, 's', 's' },
+    /* 16 bit */
+    { "ieee_half", 16, 'h', 'f' },
+    { "uint16", 16, 'h', 'u' },
+    { "int16", 16, 'h', 's' },
+    /* bytes */
+    { "uint8", 8, 'b', 'u' },
+    { "int8", 8, 'b', 's' },
+};
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    g_autoptr(GString) ts = g_string_new("");
+    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
+    info->num = 0;
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+
+    /* First define types and totals in a whole VL */
+    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+        int count = reg_width / vec_lanes[i].size;
+        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
+        g_string_append_printf(s,
+                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+                               ts->str, vec_lanes[i].gdb_type, count);
+    }
+    /*
+     * Now define a union for each size group containing unsigned and
+     * signed and potentially float versions of each size from 128 to
+     * 8 bits.
+     */
+    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+            if (vec_lanes[j].size == bits) {
+                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
+                                       vec_lanes[j].suffix,
+                                       vec_lanes[j].sz, vec_lanes[j].suffix);
+            }
+        }
+        g_string_append(s, "</union>");
+    }
+    /* And now the final union of unions */
+    g_string_append(s, "<union id=\"svev\">");
+    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
+                               suf[i], suf[i]);
+    }
+    g_string_append(s, "</union>");
+
+    /* Finally the sve prefix type */
+    g_string_append_printf(s,
+                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+                           reg_width / 8);
+
+    /* Then define each register in parts for each vq */
+    for (i = 0; i < 32; i++) {
+        g_string_append_printf(s,
+                               "<reg name=\"z%d\" bitsize=\"%d\""
+                               " regnum=\"%d\" type=\"svev\"/>",
+                               i, reg_width, base_reg++);
+        info->num++;
+    }
+    /* fpscr & status registers */
+    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
+                           " regnum=\"%d\" group=\"float\""
+                           " type=\"int\"/>", base_reg++);
+    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
+                           " regnum=\"%d\" group=\"float\""
+                           " type=\"int\"/>", base_reg++);
+    info->num += 2;
+
+    for (i = 0; i < 16; i++) {
+        g_string_append_printf(s,
+                               "<reg name=\"p%d\" bitsize=\"%d\""
+                               " regnum=\"%d\" type=\"svep\"/>",
+                               i, cpu->sve_max_vq * 16, base_reg++);
+        info->num++;
+    }
+    g_string_append_printf(s,
+                           "<reg name=\"ffr\" bitsize=\"%d\""
+                           " regnum=\"%d\" group=\"vector\""
+                           " type=\"svep\"/>",
+                           cpu->sve_max_vq * 16, base_reg++);
+    g_string_append_printf(s,
+                           "<reg name=\"vg\" bitsize=\"64\""
+                           " regnum=\"%d\" type=\"int\"/>",
+                           base_reg++);
+    info->num += 2;
+    g_string_append_printf(s, "</feature>");
+    info->desc = g_string_free(s, false);
+
+    return info->num;
+}
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a subroutine for creating the union of unions
of the various type sizes that a vector may contain.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 38 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
-struct TypeSize {
-    const char *gdb_type;
-    short size;
-    char sz, suffix;
-};
-
-static const struct TypeSize vec_lanes[] = {
-    /* quads */
-    { "uint128", 128, 'q', 'u' },
-    { "int128", 128, 'q', 's' },
-    /* 64 bit */
-    { "ieee_double", 64, 'd', 'f' },
-    { "uint64", 64, 'd', 'u' },
-    { "int64", 64, 'd', 's' },
-    /* 32 bit */
-    { "ieee_single", 32, 's', 'f' },
-    { "uint32", 32, 's', 'u' },
-    { "int32", 32, 's', 's' },
-    /* 16 bit */
-    { "ieee_half", 16, 'h', 'f' },
-    { "uint16", 16, 'h', 'u' },
-    { "int16", 16, 'h', 's' },
-    /* bytes */
-    { "uint8", 8, 'b', 'u' },
-    { "int8", 8, 'b', 's' },
-};
-
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+static void output_vector_union_type(GString *s, int reg_width)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    GString *s = g_string_new(NULL);
-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    struct TypeSize {
+        const char *gdb_type;
+        short size;
+        char sz, suffix;
+    };
+
+    static const struct TypeSize vec_lanes[] = {
+        /* quads */
+        { "uint128", 128, 'q', 'u' },
+        { "int128", 128, 'q', 's' },
+        /* 64 bit */
+        { "ieee_double", 64, 'd', 'f' },
+        { "uint64", 64, 'd', 'u' },
+        { "int64", 64, 'd', 's' },
+        /* 32 bit */
+        { "ieee_single", 32, 's', 'f' },
+        { "uint32", 32, 's', 'u' },
+        { "int32", 32, 's', 's' },
+        /* 16 bit */
+        { "ieee_half", 16, 'h', 'f' },
+        { "uint16", 16, 'h', 'u' },
+        { "int16", 16, 'h', 's' },
+        /* bytes */
+        { "uint8", 8, 'b', 'u' },
+        { "int8", 8, 'b', 's' },
+    };
+
+    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+
     g_autoptr(GString) ts = g_string_new("");
-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
-    g_string_printf(s, "<?xml version=\"1.0\"?>");
-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+    int i, j, bits;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
      * 8 bits.
      */
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
         g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
     /* And now the final union of unions */
     g_string_append(s, "<union id=\"svev\">");
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
         g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
                                suf[i], suf[i]);
     }
     g_string_append(s, "</union>");
+}
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    int i, reg_width = (cpu->sve_max_vq * 128);
+    info->num = 0;
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+
+    output_vector_union_type(s, reg_width);
 
     /* Finally the sve prefix type */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Rather than increment base_reg and num, compute num from the change
to base_reg at the end.  Clean up some nearby comments.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
     g_string_append(s, "</union>");
 }
 
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     GString *s = g_string_new(NULL);
     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-    int i, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
+    int reg_width = cpu->sve_max_vq * 128;
+    int base_reg = orig_base_reg;
+    int i;
+
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 
+    /* Create the vector union type. */
     output_vector_union_type(s, reg_width);
 
-    /* Finally the sve prefix type */
+    /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
                            reg_width / 8);
 
-    /* Then define each register in parts for each vq */
+    /* Define the vector registers. */
     for (i = 0; i < 32; i++) {
         g_string_append_printf(s,
                                "<reg name=\"z%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svev\"/>",
                                i, reg_width, base_reg++);
-        info->num++;
     }
+
     /* fpscr & status registers */
     g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
                            " regnum=\"%d\" group=\"float\""
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
     g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
                            " regnum=\"%d\" group=\"float\""
                            " type=\"int\"/>", base_reg++);
-    info->num += 2;
 
+    /* Define the predicate registers. */
     for (i = 0; i < 16; i++) {
         g_string_append_printf(s,
                                "<reg name=\"p%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svep\"/>",
                                i, cpu->sve_max_vq * 16, base_reg++);
-        info->num++;
     }
     g_string_append_printf(s,
                            "<reg name=\"ffr\" bitsize=\"%d\""
                            " regnum=\"%d\" group=\"vector\""
                            " type=\"svep\"/>",
                            cpu->sve_max_vq * 16, base_reg++);
+
+    /* Define the vector length pseudo-register. */
     g_string_append_printf(s,
                            "<reg name=\"vg\" bitsize=\"64\""
                            " regnum=\"%d\" type=\"int\"/>",
                            base_reg++);
-    info->num += 2;
-    g_string_append_printf(s, "</feature>");
-    info->desc = g_string_free(s, false);
 
+    g_string_append_printf(s, "</feature>");
+
+    info->desc = g_string_free(s, false);
+    info->num = base_reg - orig_base_reg;
     return info->num;
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     GString *s = g_string_new(NULL);
     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
     int reg_width = cpu->sve_max_vq * 128;
+    int pred_width = cpu->sve_max_vq * 16;
     int base_reg = orig_base_reg;
     int i;
 
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
         g_string_append_printf(s,
                                "<reg name=\"p%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svep\"/>",
-                               i, cpu->sve_max_vq * 16, base_reg++);
+                               i, pred_width, base_reg++);
     }
     g_string_append_printf(s,
                            "<reg name=\"ffr\" bitsize=\"%d\""
                            " regnum=\"%d\" group=\"vector\""
                            " type=\"svep\"/>",
-                           cpu->sve_max_vq * 16, base_reg++);
+                           pred_width, base_reg++);
 
     /* Define the vector length pseudo-register. */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Define svep based on the size of the predicates,
not the primary vector registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
+                           pred_width / 8);
 
     /* Define the vector registers. */
     for (i = 0; i < 32; i++) {
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This will make the function usable between SVE and SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
-static void output_vector_union_type(GString *s, int reg_width)
+static void output_vector_union_type(GString *s, int reg_width,
+                                     const char *name)
 {
     struct TypeSize {
         const char *gdb_type;
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
     };
 
     static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-
-    g_autoptr(GString) ts = g_string_new("");
     int i, j, bits;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
         g_string_append_printf(s,
-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-                               ts->str, vec_lanes[i].gdb_type, count);
+                               "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
+                               name, vec_lanes[i].sz, vec_lanes[i].suffix,
+                               vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
     }
+
     /*
      * Now define a union for each size group containing unsigned and
      * signed and potentially float versions of each size from 128 to
      * 8 bits.
      */
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+        g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-                                       vec_lanes[j].suffix,
+                g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
+                                       vec_lanes[j].suffix, name,
                                        vec_lanes[j].sz, vec_lanes[j].suffix);
             }
         }
         g_string_append(s, "</union>");
     }
+
     /* And now the final union of unions */
-    g_string_append(s, "<union id=\"svev\">");
+    g_string_append_printf(s, "<union id=\"%s\">", name);
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
-                               suf[i], suf[i]);
+        g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
+                               suf[i], name, suf[i]);
     }
     g_string_append(s, "</union>");
 }
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 
     /* Create the vector union type. */
-    output_vector_union_type(s, reg_width);
+    output_vector_union_type(s, reg_width, "svev");
 
     /* Create the predicate vector type. */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Order suf[] by the log8 of the width.
Use ARRAY_SIZE instead of hard-coding 128.

This changes the order of the union definitions,
but retains the order of the union-of-union members.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
         { "int8", 8, 'b', 's' },
     };
 
-    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-    int i, j, bits;
+    static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
+    int i, j;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
      * signed and potentially float versions of each size from 128 to
      * 8 bits.
      */
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+    for (i = 0; i < ARRAY_SIZE(suf); i++) {
+        int bits = 8 << i;
+
         g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
 
     /* And now the final union of unions */
     g_string_append_printf(s, "<union id=\"%s\">", name);
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+    for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
         g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
                                suf[i], name, suf[i]);
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Keep the logic for pauth within pauth_helper.c, and expose
a helper function for use with the gdbstub pac extension.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h        | 10 ++++++++++
 target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
 bool arm_singlestep_active(CPUARMState *env);
 bool arm_generate_debug_exceptions(CPUARMState *env);
 
+/**
+ * pauth_ptr_mask:
+ * @env: cpu context
+ * @ptr: selects between TTBR0 and TTBR1
+ * @data: selects between TBI and TBID
+ *
+ * Return a mask of the bits of @ptr that contain the authentication code.
+ */
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
+
 /* Add the cpreg definitions for debug related system registers */
 void define_debug_regs(ARMCPU *cpu);
 
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
     return pac | ext | ptr;
 }
 
-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
 {
-    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
-    uint64_t extfield = sextract64(ptr, 55, 1);
     int bot_pac_bit = 64 - param.tsz;
     int top_pac_bit = 64 - 8 * param.tbi;
 
-    return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
+    return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
+}
+
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
+{
+    uint64_t mask = pauth_ptr_mask_internal(param);
+
+    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+    if (extract64(ptr, 55, 1)) {
+        return ptr | mask;
+    } else {
+        return ptr & ~mask;
+    }
+}
+
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
+{
+    ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
+    ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
+
+    return pauth_ptr_mask_internal(param);
 }
 
 static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
ptrace register set.

The original gdb feature consists of two masks, data and code, which are
used to mask out the authentication code within a pointer.  Following
discussion with Luis Machado, add two more masks in order to support
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 configs/targets/aarch64-linux-user.mak    |  2 +-
 configs/targets/aarch64-softmmu.mak       |  2 +-
 configs/targets/aarch64_be-linux-user.mak |  2 +-
 target/arm/internals.h                    |  2 ++
 target/arm/gdbstub.c                      |  5 ++++
 target/arm/gdbstub64.c                    | 34 +++++++++++++++++++++++
 gdb-xml/aarch64-pauth.xml                 | 15 ++++++++++
 7 files changed, 59 insertions(+), 3 deletions(-)
 create mode 100644 gdb-xml/aarch64-pauth.xml

diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64-linux-user.mak
+++ b/configs/targets/aarch64-linux-user.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
 TARGET_HAS_BFLT=y
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64-softmmu.mak
+++ b/configs/targets/aarch64-softmmu.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
 TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
 TARGET_NEED_FDT=y
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64_be-linux-user.mak
+++ b/configs/targets/aarch64_be-linux-user.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
 TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
 TARGET_HAS_BFLT=y
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                                      aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
+        if (isar_feature_aa64_pauth(&cpu->isar)) {
+            gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
+                                     aarch64_gdb_set_pauth_reg,
+                                     4, "aarch64-pauth.xml", 0);
+        }
 #endif
     } else {
         if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    switch (reg) {
+    case 0: /* pauth_dmask */
+    case 1: /* pauth_cmask */
+    case 2: /* pauth_dmask_high */
+    case 3: /* pauth_cmask_high */
+        /*
+         * Note that older versions of this feature only contained
+         * pauth_{d,c}mask, for use with Linux user processes, and
+         * thus exclusively in the low half of the address space.
+         *
+         * To support system mode, and to debug kernels, two new regs
+         * were added to cover the high half of the address space.
+         * For the purpose of pauth_ptr_mask, we can use any well-formed
+         * address within the address space half -- here, 0 and -1.
+         */
+        {
+            bool is_data = !(reg & 1);
+            bool is_high = reg & 2;
+            uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
+            return gdb_get_reg64(buf, mask);
+        }
+    default:
+        return 0;
+    }
+}
+
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    /* All pseudo registers are read-only. */
+    return 0;
+}
+
 static void output_vector_union_type(GString *s, int reg_width,
                                      const char *name)
 {
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/gdb-xml/aarch64-pauth.xml
@@ -XXX,XX +XXX,XX @@
+<?xml version="1.0"?>
+
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.pauth">
+  <reg name="pauth_dmask" bitsize="64"/>
+  <reg name="pauth_cmask" bitsize="64"/>
+  <reg name="pauth_dmask_high" bitsize="64"/>
+  <reg name="pauth_cmask_high" bitsize="64"/>
+</feature>
+
-- 
2.34.1

From: David Reiss <dreiss@meta.com>

Allow the function to be used outside of m_helper.c.
Rename with an "arm_" prefix.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 3 +++
 target/arm/tcg/m_helper.c | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 #endif
 
+/* Read the CONTROL register as the MRS instruction would. */
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
+
 #ifdef CONFIG_USER_ONLY
 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 #else
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
     return xpsr_read(env) & mask;
 }
 
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
 {
     uint32_t value = env->v7m.control[secure];
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
     case 0 ... 7: /* xPSR sub-fields */
         return v7m_mrs_xpsr(env, reg, 0);
     case 20: /* CONTROL */
-        return v7m_mrs_control(env, 0);
+        return arm_v7m_mrs_control(env, 0);
     default:
         /* Unprivileged reads others as zero.  */
         return 0;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
     case 0 ... 7: /* xPSR sub-fields */
         return v7m_mrs_xpsr(env, reg, el);
     case 20: /* CONTROL */
-        return v7m_mrs_control(env, env->v7m.secure);
+        return arm_v7m_mrs_control(env, env->v7m.secure);
     case 0x94: /* CONTROL_NS */
         /*
          * We have to handle this here because unprivileged Secure code
-- 
2.34.1

From: David Reiss <dreiss@meta.com>

Allow the function to be used outside of m_helper.c.
Move to be outside of ifndef CONFIG_USER_ONLY block.
Rename from get_v7m_sp_ptr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 10 +++++
 target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
 2 files changed, 51 insertions(+), 43 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 /* Read the CONTROL register as the MRS instruction would. */
 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
 
+/*
+ * Return a pointer to the location where we currently store the
+ * stack pointer for the requested security state and thread mode.
+ * This pointer will become invalid if the CPU state is updated
+ * such that the stack pointers are switched around (eg changing
+ * the SPSEL control bit).
+ */
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
+                             bool threadmode, bool spsel);
+
 #ifdef CONFIG_USER_ONLY
 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 #else
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
     arm_rebuild_hflags(env);
 }
 
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
-                                bool spsel)
-{
-    /*
-     * Return a pointer to the location where we currently store the
-     * stack pointer for the requested security state and thread mode.
-     * This pointer will become invalid if the CPU state is updated
-     * such that the stack pointers are switched around (eg changing
-     * the SPSEL control bit).
-     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
-     * Unlike that pseudocode, we require the caller to pass us in the
-     * SPSEL control bit value; this is because we also use this
-     * function in handling of pushing of the callee-saves registers
-     * part of the v8M stack frame (pseudocode PushCalleeStack()),
-     * and in the tailchain codepath the SPSEL bit comes from the exception
-     * return magic LR value from the previous exception. The pseudocode
-     * opencodes the stack-selection in PushCalleeStack(), but we prefer
-     * to make this utility function generic enough to do the job.
-     */
-    bool want_psp = threadmode && spsel;
-
-    if (secure == env->v7m.secure) {
-        if (want_psp == v7m_using_psp(env)) {
-            return &env->regs[13];
-        } else {
-            return &env->v7m.other_sp;
-        }
-    } else {
-        if (want_psp) {
-            return &env->v7m.other_ss_psp;
-        } else {
-            return &env->v7m.other_ss_msp;
-        }
-    }
-}
-
 static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
                                 uint32_t *pvec)
 {
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
             !mode;
 
         mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
-        frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
-                                    lr & R_V7M_EXCRET_SPSEL_MASK);
+        frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
+                                        lr & R_V7M_EXCRET_SPSEL_MASK);
         want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
         if (want_psp) {
             limit = env->v7m.psplim[M_REG_S];
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
          * use 'frame_sp_p' after we do something that makes it invalid.
          */
         bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
-        uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
-                                              return_to_secure,
-                                              !return_to_handler,
-                                              spsel);
+        uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
+                                                  !return_to_handler, spsel);
         uint32_t frameptr = *frame_sp_p;
         bool pop_ok = true;
         ARMMMUIdx mmu_idx;
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
         threadmode = !arm_v7m_is_handler_mode(env);
         spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
 
-        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
+        frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
         frameptr = *frame_sp_p;
 
         /*
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
 }
 
 #endif /* !CONFIG_USER_ONLY */
+
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
+                             bool spsel)
+{
+    /*
+     * Return a pointer to the location where we currently store the
+     * stack pointer for the requested security state and thread mode.
+     * This pointer will become invalid if the CPU state is updated
+     * such that the stack pointers are switched around (eg changing
+     * the SPSEL control bit).
+     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
+     * Unlike that pseudocode, we require the caller to pass us in the
+     * SPSEL control bit value; this is because we also use this
+     * function in handling of pushing of the callee-saves registers
+     * part of the v8M stack frame (pseudocode PushCalleeStack()),
+     * and in the tailchain codepath the SPSEL bit comes from the exception
+     * return magic LR value from the previous exception. The pseudocode
+     * opencodes the stack-selection in PushCalleeStack(), but we prefer
+     * to make this utility function generic enough to do the job.
+     */
+    bool want_psp = threadmode && spsel;
+
+    if (secure == env->v7m.secure) {
+        if (want_psp == v7m_using_psp(env)) {
+            return &env->regs[13];
+        } else {
+            return &env->v7m.other_sp;
+        }
+    } else {
+        if (want_psp) {
+            return &env->v7m.other_ss_psp;
+        } else {
+            return &env->v7m.other_ss_msp;
+        }
+    }
+}
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
go ahead and implement the other system registers as well.

Since there is significant overlap between the two, implement
them with common code.  The only exception is the systemreg
view of CONTROL, which merges the banked bits as per MRS.

Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
[rth: Substatial rewrite using enumerator and shared code.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |   2 +
 target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 180 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     DynamicGDBXMLInfo dyn_sysreg_xml;
     DynamicGDBXMLInfo dyn_svereg_xml;
+    DynamicGDBXMLInfo dyn_m_systemreg_xml;
+    DynamicGDBXMLInfo dyn_m_secextreg_xml;
 
     /* Timers used by the generic (architected) timer */
     QEMUTimer *gt_timer[NUM_GTIMERS];
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
+typedef enum {
+    M_SYSREG_MSP,
+    M_SYSREG_PSP,
+    M_SYSREG_PRIMASK,
+    M_SYSREG_CONTROL,
+    M_SYSREG_BASEPRI,
+    M_SYSREG_FAULTMASK,
+    M_SYSREG_MSPLIM,
+    M_SYSREG_PSPLIM,
+} MProfileSysreg;
+
+static const struct {
+    const char *name;
+    int feature;
+} m_sysreg_def[] = {
+    [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
+    [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
+    [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
+    [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
+    [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
+    [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
+    [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
+    [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
+};
+
+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
+{
+    uint32_t *ptr;
+
+    switch (reg) {
+    case M_SYSREG_MSP:
+        ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
+        break;
+    case M_SYSREG_PSP:
+        ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
+        break;
+    case M_SYSREG_MSPLIM:
+        ptr = &env->v7m.msplim[sec];
+        break;
+    case M_SYSREG_PSPLIM:
+        ptr = &env->v7m.psplim[sec];
+        break;
+    case M_SYSREG_PRIMASK:
+        ptr = &env->v7m.primask[sec];
+        break;
+    case M_SYSREG_BASEPRI:
+        ptr = &env->v7m.basepri[sec];
+        break;
+    case M_SYSREG_FAULTMASK:
+        ptr = &env->v7m.faultmask[sec];
+        break;
+    case M_SYSREG_CONTROL:
+        ptr = &env->v7m.control[sec];
+        break;
+    default:
+        return NULL;
+    }
+    return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
+}
+
+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
+                        MProfileSysreg reg, bool secure)
+{
+    uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
+
+    if (ptr == NULL) {
+        return 0;
+    }
+    return gdb_get_reg32(buf, *ptr);
+}
+
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    /*
+     * Here, we emulate MRS instruction, where CONTROL has a mix of
+     * banked and non-banked bits.
+     */
+    if (reg == M_SYSREG_CONTROL) {
+        return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
+    }
+    return m_sysreg_get(env, buf, reg, env->v7m.secure);
+}
+
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    return 0; /* TODO */
+}
+
+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    GString *s = g_string_new(NULL);
+    int base_reg = orig_base_reg;
+    int i;
+
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
+
+    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
+        if (arm_feature(env, m_sysreg_def[i].feature)) {
+            g_string_append_printf(s,
+                "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+                m_sysreg_def[i].name, base_reg++);
+        }
+    }
+
+    g_string_append_printf(s, "</feature>");
+    cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
+    cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
+
+    return cpu->dyn_m_systemreg_xml.num;
+}
+
+#ifndef CONFIG_USER_ONLY
+/*
+ * For user-only, we see the non-secure registers via m_systemreg above.
+ * For secext, encode the non-secure view as even and secure view as odd.
+ */
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    return m_sysreg_get(env, buf, reg >> 1, reg & 1);
+}
+
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    return 0; /* TODO */
+}
+
+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    int base_reg = orig_base_reg;
+    int i;
+
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
+
+    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
+        g_string_append_printf(s,
+            "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
+            m_sysreg_def[i].name, base_reg++);
+        g_string_append_printf(s,
+            "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+            m_sysreg_def[i].name, base_reg++);
+    }
+
+    g_string_append_printf(s, "</feature>");
+    cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
+    cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
+
+    return cpu->dyn_m_secextreg_xml.num;
+}
+#endif
+
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
         return cpu->dyn_sysreg_xml.desc;
     } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
         return cpu->dyn_svereg_xml.desc;
+    } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
+        return cpu->dyn_m_systemreg_xml.desc;
+#ifndef CONFIG_USER_ONLY
+    } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
+        return cpu->dyn_m_secextreg_xml.desc;
+#endif
     }
     return NULL;
 }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                              "system-registers.xml", 0);
 
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        gdb_register_coprocessor(cs,
+            arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
+            arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
+            "arm-m-system.xml", 0);
+#ifndef CONFIG_USER_ONLY
+        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+            gdb_register_coprocessor(cs,
+                arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
+                arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
+                "arm-m-secext.xml", 0);
+        }
+#endif
+    }
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

M-profile doesn't have HCR_EL2.  While we could test features
before each call, zero is a generally safe return value to
disable the code in the caller.  This test is required to
avoid an assert in arm_is_secure_below_el3.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
 
 uint64_t arm_hcr_el2_eff(CPUARMState *env)
 {
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        return 0;
+    }
     return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
 }
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

In several places we use arm_is_secure_below_el3 and
arm_is_el3_or_mon separately from arm_is_secure.
These functions make no sense for m-profile, and
would indicate prior incorrect feature testing.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
 
 #if !defined(CONFIG_USER_ONLY)
-/* Return true if exception levels below EL3 are in secure state,
+/*
+ * Return true if exception levels below EL3 are in secure state,
  * or would be following an exception return to that level.
  * Unlike arm_is_secure() (which is always a question about the
  * _current_ state of the CPU) this doesn't care about the current
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
  */
 static inline bool arm_is_secure_below_el3(CPUARMState *env)
 {
+    assert(!arm_feature(env, ARM_FEATURE_M));
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         return !(env->cp15.scr_el3 & SCR_NS);
     } else {
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
 static inline bool arm_is_el3_or_mon(CPUARMState *env)
 {
+    assert(!arm_feature(env, ARM_FEATURE_M));
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
             /* CPU currently in AArch64 state and EL3 */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Integrate neighboring code from get_phys_addr_lpae which computed
starting level, as it is easier to validate when doing both at the
same time.  Mirror the checks at the start of AArch{64,32}.S2Walk,
especially S2InvalidSL and S2InconsistentSL.

This reverts 49ba115bb74, which was incorrect -- there is nothing
in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
pseudocode is consistent in referencing PAMax.

Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
 1 file changed, 97 insertions(+), 76 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
  * check_s2_mmu_setup
  * @cpu:        ARMCPU
  * @is_aa64:    True if the translation regime is in AArch64 state
- * @startlevel: Suggested starting level
- * @inputsize:  Bitsize of IPAs
+ * @tcr:        VTCR_EL2 or VSTCR_EL2
+ * @ds:         Effective value of TCR.DS.
+ * @iasize:     Bitsize of IPAs
  * @stride:     Page-table stride (See the ARM ARM)
  *
- * Returns true if the suggested S2 translation parameters are OK and
- * false otherwise.
+ * Decode the starting level of the S2 lookup, returning INT_MIN if
+ * the configuration is invalid.
  */
-static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
-                               int inputsize, int stride, int outputsize)
+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
+                              bool ds, int iasize, int stride)
 {
-    const int grainsize = stride + 3;
-    int startsizecheck;
-
-    /*
-     * Negative levels are usually not allowed...
-     * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
-     * begins with level -1.  Note that previous feature tests will have
-     * eliminated this combination if it is not enabled.
-     */
-    if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
-        return false;
-    }
-
-    startsizecheck = inputsize - ((3 - level) * stride + grainsize);
-    if (startsizecheck < 1 || startsizecheck > stride + 4) {
-        return false;
-    }
+    int sl0, sl2, startlevel, granulebits, levels;
+    int s1_min_iasize, s1_max_iasize;
 
+    sl0 = extract32(tcr, 6, 2);
     if (is_aa64) {
+        /*
+         * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
+         * get_phys_addr_lpae, that used aa64_va_parameters which apply
+         * to aarch64.  If Stage1 is aarch32, the min_txsz is larger.
+         * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
+         * inputsize is 64 - 24 = 40.
+         */
+        if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
+            goto fail;
+        }
+
+        /*
+         * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
+         * so interleave AArch64.S2StartLevel.
+         */
         switch (stride) {
-        case 13: /* 64KB Pages.  */
-            if (level == 0 || (level == 1 && outputsize <= 42)) {
-                return false;
+        case 9: /* 4KB */
+            /* SL2 is RES0 unless DS=1 & 4KB granule. */
+            sl2 = extract64(tcr, 33, 1);
+            if (ds && sl2) {
+                if (sl0 != 0) {
+                    goto fail;
+                }
+                startlevel = -1;
+            } else {
+                startlevel = 2 - sl0;
+                switch (sl0) {
+                case 2:
+                    if (arm_pamax(cpu) < 44) {
+                        goto fail;
+                    }
+                    break;
+                case 3:
+                    if (!cpu_isar_feature(aa64_st, cpu)) {
+                        goto fail;
+                    }
+                    startlevel = 3;
+                    break;
+                }
             }
             break;
-        case 11: /* 16KB Pages.  */
-            if (level == 0 || (level == 1 && outputsize <= 40)) {
-                return false;
+        case 11: /* 16KB */
+            switch (sl0) {
+            case 2:
+                if (arm_pamax(cpu) < 42) {
+                    goto fail;
+                }
+                break;
+            case 3:
+                if (!ds) {
+                    goto fail;
+                }
+                break;
             }
+            startlevel = 3 - sl0;
             break;
-        case 9: /* 4KB Pages.  */
-            if (level == 0 && outputsize <= 42) {
-                return false;
+        case 13: /* 64KB */
+            switch (sl0) {
+            case 2:
+                if (arm_pamax(cpu) < 44) {
+                    goto fail;
+                }
+                break;
+            case 3:
+                goto fail;
             }
+            startlevel = 3 - sl0;
             break;
         default:
             g_assert_not_reached();
         }
-
-        /* Inputsize checks.  */
-        if (inputsize > outputsize &&
-            (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
-            /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
-            return false;
-        }
     } else {
-        /* AArch32 only supports 4KB pages. Assert on that.  */
+        /*
+         * Things are simpler for AArch32 EL2, with only 4k pages.
+         * There is no separate S2InvalidSL function, but AArch32.S2Walk
+         * begins with walkparms.sl0 in {'1x'}.
+         */
         assert(stride == 9);
-
-        if (level == 0) {
-            return false;
+        if (sl0 >= 2) {
+            goto fail;
         }
+        startlevel = 2 - sl0;
     }
-    return true;
+
+    /* AArch{64,32}.S2InconsistentSL are functionally equivalent.  */
+    levels = 3 - startlevel;
+    granulebits = stride + 3;
+
+    s1_min_iasize = levels * stride + granulebits + 1;
+    s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
+
+    if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
+        return startlevel;
+    }
+
+ fail:
+    return INT_MIN;
 }
 
 /**
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
          */
         level = 4 - (inputsize - 4) / stride;
     } else {
-        /*
-         * For stage 2 translations the starting level is specified by the
-         * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
-         */
-        uint32_t sl0 = extract32(tcr, 6, 2);
-        uint32_t sl2 = extract64(tcr, 33, 1);
-        int32_t startlevel;
-        bool ok;
-
-        /* SL2 is RES0 unless DS=1 & 4kb granule. */
-        if (param.ds && stride == 9 && sl2) {
-            if (sl0 != 0) {
-                level = 0;
-                goto do_translation_fault;
-            }
-            startlevel = -1;
-        } else if (!aarch64 || stride == 9) {
-            /* AArch32 or 4KB pages */
-            startlevel = 2 - sl0;
-
-            if (cpu_isar_feature(aa64_st, cpu)) {
-                startlevel &= 3;
-            }
-        } else {
-            /* 16KB or 64KB pages */
-            startlevel = 3 - sl0;
-        }
-
-        /* Check that the starting level is valid. */
-        ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
-                                inputsize, stride, outputsize);
-        if (!ok) {
+        int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
+                                            inputsize, stride);
+        if (startlevel == INT_MIN) {
+            level = 0;
             goto do_translation_fault;
         }
         level = startlevel;
-- 
2.34.1

From: Ard Biesheuvel <ardb@kernel.org>

Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
format, using gzip compression for the payload.

For doing EFI boot in QEMU, this is completely transparent, as the
firmware or bootloader will take care of this. However, for direct
kernel boot without firmware, we will lose the ability to boot such
distro kernels unless we deal with the new format directly.

EFI zboot images contain metadata in the header regarding the placement
of the compressed payload inside the image, and the type of compression
used. This means we can wire up the existing gzip support without too
much hassle, by parsing the header and grabbing the payload from inside
the loaded zboot image.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20230303160109.3626966-1-ardb@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked comment formatting, fixed checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/loader.h | 19 ++++++++++
 hw/arm/boot.c       |  6 +++
 hw/core/loader.c    | 91 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+)

diff --git a/include/hw/loader.h b/include/hw/loader.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
                                   uint8_t **buffer);
 ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
 
+/**
+ * unpack_efi_zboot_image:
+ * @buffer: pointer to a variable holding the address of a buffer containing the
+ *          image
+ * @size: pointer to a variable holding the size of the buffer
+ *
+ * Check whether the buffer contains a EFI zboot image, and if it does, extract
+ * the compressed payload and decompress it into a new buffer. If successful,
+ * the old buffer is freed, and the *buffer and size variables pointed to by the
+ * function arguments are updated to refer to the newly populated buffer.
+ *
+ * Returns 0 if the image could not be identified as a EFI zboot image.
+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
+ * unpacking failed for any reason.
+ * Returns the size of the decompressed payload if decompression was performed
+ * successfully.
+ */
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
+
 #define ELF_LOAD_FAILED       -1
 #define ELF_LOAD_NOT_ELF      -2
 #define ELF_LOAD_WRONG_ARCH   -3
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
             return -1;
         }
         size = len;
+
+        /* Unpack the image if it is a EFI zboot image */
+        if (unpack_efi_zboot_image(&buffer, &size) < 0) {
+            g_free(buffer);
+            return -1;
+        }
     }
 
     /* check the arm64 magic header value -- very old kernels may not have it */
diff --git a/hw/core/loader.c b/hw/core/loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
     return bytes;
 }
 
+/* The PE/COFF MS-DOS stub magic number */
+#define EFI_PE_MSDOS_MAGIC        "MZ"
+
+/*
+ * The Linux header magic number for a EFI PE/COFF
+ * image targetting an unspecified architecture.
+ */
+#define EFI_PE_LINUX_MAGIC        "\xcd\x23\x82\x81"
+
+/*
+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
+ * self-decompressing executables when loaded via EFI. The compressed payload
+ * can also be extracted from the image and decompressed by a non-EFI loader.
+ *
+ * The de facto specification for this format is at the following URL:
+ *
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
+ *
+ * This definition is based on Linux upstream commit 29636a5ce87beba.
+ */
+struct linux_efi_zboot_header {
+    uint8_t     msdos_magic[2];         /* PE/COFF 'MZ' magic number */
+    uint8_t     reserved0[2];
+    uint8_t     zimg[4];                /* "zimg" for Linux EFI zboot images */
+    uint32_t    payload_offset;         /* LE offset to compressed payload */
+    uint32_t    payload_size;           /* LE size of the compressed payload */
+    uint8_t     reserved1[8];
+    char        compression_type[32];   /* Compression type, NUL terminated */
+    uint8_t     linux_magic[4];         /* Linux header magic */
+    uint32_t    pe_header_offset;       /* LE offset to the PE header */
+};
+
+/*
+ * Check whether *buffer points to a Linux EFI zboot image in memory.
+ *
+ * If it does, attempt to decompress it to a new buffer, and free the old one.
+ * If any of this fails, return an error to the caller.
+ *
+ * If the image is not a Linux EFI zboot image, do nothing and return success.
+ */
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
+{
+    const struct linux_efi_zboot_header *header;
+    uint8_t *data = NULL;
+    int ploff, plsize;
+    ssize_t bytes;
+
+    /* ignore if this is too small to be a EFI zboot image */
+    if (*size < sizeof(*header)) {
+        return 0;
+    }
+
+    header = (struct linux_efi_zboot_header *)*buffer;
+
+    /* ignore if this is not a Linux EFI zboot image */
+    if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
+        memcmp(&header->zimg, "zimg", 4) != 0 ||
+        memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
+        return 0;
+    }
+
+    if (strcmp(header->compression_type, "gzip") != 0) {
+        fprintf(stderr,
+                "unable to handle EFI zboot image with \"%.*s\" compression\n",
+                (int)sizeof(header->compression_type) - 1,
+                header->compression_type);
+        return -1;
+    }
+
+    ploff = ldl_le_p(&header->payload_offset);
+    plsize = ldl_le_p(&header->payload_size);
+
+    if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
+        fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
+        return -1;
+    }
+
+    data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
+    bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
+    if (bytes < 0) {
+        fprintf(stderr, "failed to decompress EFI zboot image\n");
+        g_free(data);
+        return -1;
+    }
+
+    g_free(*buffer);
+    *buffer = g_realloc(data, bytes);
+    *size = bytes;
+    return bytes;
+}
+
 /*
  * Functions for reboot-persistent memory regions.
  *  - used for vga bios and option roms.
-- 
2.34.1

From: qianfan Zhao <qianfanguijin@163.com>

TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register on SUN6i based SoCs, we should lower interrupt when the guest
set this bit.

The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:

allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
...

Fix it.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/allwinner-i2c.h |  6 ++++++
 hw/i2c/allwinner-i2c.c         | 26 ++++++++++++++++++++++++--
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/allwinner-i2c.h
+++ b/include/hw/i2c/allwinner-i2c.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_AW_I2C "allwinner.i2c"
+
+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
+
 OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
 
 #define AW_I2C_MEM_SIZE         0x24
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
     uint8_t srst;
     uint8_t efr;
     uint8_t lcr;
+
+    bool irq_clear_inverted;
 };
 
 #endif /* ALLWINNER_I2C_H */
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/allwinner-i2c.c
+++ b/hw/i2c/allwinner-i2c.c
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
                 s->stat = STAT_FROM_STA(STAT_IDLE);
                 s->cntr &= ~TWI_CNTR_M_STP;
             }
-            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
-                /* Interrupt flag cleared */
+
+            if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
+                /* Write 0 to clear this flag */
+                qemu_irq_lower(s->irq);
+            } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
+                /* Write 1 to clear this flag */
+                s->cntr &= ~TWI_CNTR_INT_FLAG;
                 qemu_irq_lower(s->irq);
             }
+
             if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
                 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
                     s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
     .class_init = allwinner_i2c_class_init,
 };
 
+static void allwinner_i2c_sun6i_init(Object *obj)
+{
+    AWI2CState *s = AW_I2C(obj);
+
+    s->irq_clear_inverted = true;
+}
+
+static const TypeInfo allwinner_i2c_sun6i_type_info = {
+    .name = TYPE_AW_I2C_SUN6I,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AWI2CState),
+    .instance_init = allwinner_i2c_sun6i_init,
+    .class_init = allwinner_i2c_class_init,
+};
+
 static void allwinner_i2c_register_types(void)
 {
     type_register_static(&allwinner_i2c_type_info);
+    type_register_static(&allwinner_i2c_sun6i_type_info);
 }
 
 type_init(allwinner_i2c_register_types)
-- 
2.34.1

From: qianfan Zhao <qianfanguijin@163.com>

Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
control register's INT_FLAG bit.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-h3.h |  6 ++++++
 hw/arm/allwinner-h3.c         | 29 +++++++++++++++++++++++++----
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_UART3,
     AW_H3_DEV_EMAC,
     AW_H3_DEV_TWI0,
+    AW_H3_DEV_TWI1,
+    AW_H3_DEV_TWI2,
     AW_H3_DEV_DRAMCOM,
     AW_H3_DEV_DRAMCTL,
     AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_GIC_VCPU,
     AW_H3_DEV_RTC,
     AW_H3_DEV_CPUCFG,
+    AW_H3_DEV_R_TWI,
     AW_H3_DEV_SDRAM
 };
 
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
     AwSidState sid;
     AwSdHostState mmc0;
     AWI2CState i2c0;
+    AWI2CState i2c1;
+    AWI2CState i2c2;
+    AWI2CState r_twi;
     AwSun8iEmacState emac;
     AwRtcState rtc;
     GICState gic;
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_UART2]      = 0x01c28800,
     [AW_H3_DEV_UART3]      = 0x01c28c00,
     [AW_H3_DEV_TWI0]       = 0x01c2ac00,
+    [AW_H3_DEV_TWI1]       = 0x01c2b000,
+    [AW_H3_DEV_TWI2]       = 0x01c2b400,
     [AW_H3_DEV_EMAC]       = 0x01c30000,
     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
     [AW_H3_DEV_RTC]        = 0x01f00000,
     [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
+    [AW_H3_DEV_R_TWI]      = 0x01f02400,
     [AW_H3_DEV_SDRAM]      = 0x40000000
 };
 
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "uart1",     0x01c28400, 1 * KiB },
     { "uart2",     0x01c28800, 1 * KiB },
     { "uart3",     0x01c28c00, 1 * KiB },
-    { "twi1",      0x01c2b000, 1 * KiB },
-    { "twi2",      0x01c2b400, 1 * KiB },
     { "scr",       0x01c2c400, 1 * KiB },
     { "gpu",       0x01c40000, 64 * KiB },
     { "hstmr",     0x01c60000, 4 * KiB },
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "r_prcm",    0x01f01400, 1 * KiB },
     { "r_twd",     0x01f01800, 1 * KiB },
     { "r_cir-rx",  0x01f02000, 1 * KiB },
-    { "r_twi",     0x01f02400, 1 * KiB },
     { "r_uart",    0x01f02800, 1 * KiB },
     { "r_pio",     0x01f02c00, 1 * KiB },
     { "r_pwm",     0x01f03800, 1 * KiB },
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_GIC_SPI_UART2     =  2,
     AW_H3_GIC_SPI_UART3     =  3,
     AW_H3_GIC_SPI_TWI0      =  6,
+    AW_H3_GIC_SPI_TWI1      =  7,
+    AW_H3_GIC_SPI_TWI2      =  8,
     AW_H3_GIC_SPI_TIMER0    = 18,
     AW_H3_GIC_SPI_TIMER1    = 19,
+    AW_H3_GIC_SPI_R_TWI     = 44,
     AW_H3_GIC_SPI_MMC0      = 60,
     AW_H3_GIC_SPI_EHCI0     = 72,
     AW_H3_GIC_SPI_OHCI0     = 73,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
 
-    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
+    object_initialize_child(obj, "twi0",  &s->i2c0,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
 }
 
 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
 
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
+
     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
         create_unimplemented_device(unimplemented[i].device_name,
-- 
2.34.1