Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[PULL 00/24] target-arm queue
-Arm patch queue -- these are all bug fix patches but we might
+Hi; here's the latest arm pullreq. This is mostly patches from
-as well put them in to rc0...
+RTH, plus a couple of other more minor things. Switching to
 PCREL is the big one, hopefully should improve performance.
 thanks
 -- PMM
-The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
+The following changes since commit 214a8da23651f2472b296b3293e619fd58d9e212:
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
+  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-10-18 11:14:31 -0400)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221020
-for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
+for you to fetch changes up to 5db899303799e49209016a93289b8694afa1449e:
-  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
+  hw/ide/microdrive: Use device_cold_reset() for self-resets (2022-10-20 12:11:53 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * fsl-imx6: Fix incorrect Ethernet interrupt defines
+ * Switch to TARGET_TB_PCREL
- * dump: Update correct kdump phys_base field for AArch64
+ * More pagetable-walk refactoring preparatory to HAFDBS
- * char: i.MX: Add support for "TX complete" interrupt
+ * update the cortex-a15 MIDR to latest rev
- * bcm2836/raspi: Fix various bugs resulting in panics trying
+ * hw/char/pl011: fix baud rate calculation
-   to boot a Debian Linux kernel on raspi3
+ * hw/ide/microdrive: Use device_cold_reset() for self-resets
 ----------------------------------------------------------------
-Andrey Smirnov (2):
+Alex Bennée (1):
-      char: i.MX: Simplify imx_update()
+      target/arm: update the cortex-a15 MIDR to latest rev
       char: i.MX: Add support for "TX complete" interrupt
-Guenter Roeck (1):
+Baruch Siach (1):
-      fsl-imx6: Swap Ethernet interrupt defines
+      hw/char/pl011: fix baud rate calculation
-Peter Maydell (9):
+Peter Maydell (1):
-      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+      hw/ide/microdrive: Use device_cold_reset() for self-resets
       hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
       hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
       hw/arm/bcm2386: Fix parent type of bcm2386
       hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
       hw/arm/bcm2836: Create proper bcm2837 device
       hw/arm/bcm2836: Use correct affinity values for BCM2837
       hw/arm/bcm2836: Hardcode correct CPU type
       hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
-Wei Huang (1):
+Richard Henderson (21):
-      dump: Update correct kdump phys_base field for AArch64
+      target/arm: Enable TARGET_PAGE_ENTRY_EXTRA
       target/arm: Use probe_access_full for MTE
       target/arm: Use probe_access_full for BTI
       target/arm: Add ARMMMUIdx_Phys_{S,NS}
       target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx
       target/arm: Restrict tlb flush from vttbr_write to vmid change
       target/arm: Split out S1Translate type
       target/arm: Plumb debug into S1Translate
       target/arm: Move be test for regime into S1TranslateResult
       target/arm: Use softmmu tlbs for page table walking
       target/arm: Split out get_phys_addr_twostage
       target/arm: Use bool consistently for get_phys_addr subroutines
       target/arm: Introduce curr_insn_len
       target/arm: Change gen_goto_tb to work on displacements
       target/arm: Change gen_*set_pc_im to gen_*update_pc
       target/arm: Change gen_exception_insn* to work on displacements
       target/arm: Remove gen_exception_internal_insn pc argument
       target/arm: Change gen_jmp* to work on displacements
       target/arm: Introduce gen_pc_plus_diff for aarch64
       target/arm: Introduce gen_pc_plus_diff for aarch32
       target/arm: Enable TARGET_TB_PCREL
- include/hw/arm/bcm2836.h     | 31 +++++++++++++---
+ target/arm/cpu-param.h         |  17 +-
- include/hw/arm/fsl-imx6.h    |  4 +-
+ target/arm/cpu.h               |  47 ++--
- include/hw/char/imx_serial.h |  3 ++
+ target/arm/internals.h         |   1 +
- dump.c                       | 14 +++++--
+ target/arm/sve_ldst_internal.h |   1 +
- hw/arm/bcm2836.c             | 87 +++++++++++++++++++++++++++++++-------------
+ target/arm/translate-a32.h     |   2 +-
- hw/arm/boot.c                | 12 ++++++
+ target/arm/translate.h         |  66 ++++-
- hw/arm/raspi.c               | 77 +++++++++++++++++++++++++++++++--------
+ hw/char/pl011.c                |   2 +-
- hw/char/imx_serial.c         | 44 ++++++++++++++++------
+ hw/ide/microdrive.c            |   8 +-
- hw/net/imx_fec.c             | 28 +++++++++++++-
+ target/arm/cpu.c               |  23 +-
-files changed, 237 insertions(+), 63 deletions(-)
+ target/arm/cpu_tcg.c           |   4 +-
  target/arm/helper.c            | 155 +++++++++---
  target/arm/mte_helper.c        |  62 ++---
  target/arm/ptw.c               | 535 +++++++++++++++++++++++++----------------
  target/arm/sve_helper.c        |  54 ++---
  target/arm/tlb_helper.c        |  24 +-
  target/arm/translate-a64.c     | 220 ++++++++++-------
  target/arm/translate-m-nocp.c  |   8 +-
  target/arm/translate-mve.c     |   2 +-
  target/arm/translate-vfp.c     |  10 +-
  target/arm/translate.c         | 284 +++++++++++++---------
 files changed, 918 insertions(+), 607 deletions(-)

-[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
+[PULL 01/24] hw/char/pl011: fix baud rate calculation
-The TypeInfo and state struct for bcm2386 disagree about what the
+From: Baruch Siach <baruch@tkos.co.il>
 parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
 but the BCM2386State struct only defines the parent_obj field
 as DeviceState. This would have caused problems if anything
 actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
 Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
 need any of the additional functionality TYPE_SYS_BUS_DEVICE
 provides.
+The PL011 TRM says that "UARTIBRD = 0 is invalid and UARTFBRD is ignored
+when this is the case". But the code looks at FBRD for the invalid case.
+Fix this.
+Signed-off-by: Baruch Siach <baruch@tkos.co.il>
+Message-id: 1408f62a2e45665816527d4845ffde650957d5ab.1665051588.git.baruchs-c@neureality.ai
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 2 +-
+ hw/char/pl011.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/char/pl011.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static unsigned int pl011_get_baudrate(const PL011State *s)
+ {
- static const TypeInfo bcm2836_type_info = {
+     uint64_t clk;
-     .name = TYPE_BCM2836,
--    .parent = TYPE_SYS_BUS_DEVICE,
+-    if (s->fbrd == 0) {
-+    .parent = TYPE_DEVICE,
++    if (s->ibrd == 0) {
-     .instance_size = sizeof(BCM2836State),
+         return 0;
-     .instance_init = bcm2836_init,
+     }
-     .class_init = bcm2836_class_init,
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
+[PULL 04/24] target/arm: Use probe_access_full for MTE
-From: Guenter Roeck <linux@roeck-us.net>
+From: Richard Henderson <richard.henderson@linaro.org>
-The sabrelite machine model used by qemu-system-arm is based on the
+The CPUTLBEntryFull structure now stores the original pte attributes, as
-Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
+well as the physical address.  Therefore, we no longer need a separate
-controller which is supported in QEMU using the imx_fec.c module
+bit in MemTxAttrs, nor do we need to walk the tree of memory regions.
 (actually called imx.enet for this model.)
-The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
-imx.enet device like this:
- #define FSL_IMX6_ENET_MAC_1588_IRQ 118
- #define FSL_IMX6_ENET_MAC_IRQ 119
-According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
-page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
-interrupts are as follows.
-ENET MAC 0 IRQ
-ENET MAC 0 1588 Timer interrupt
-where
-- 32 == 118
-- 32 == 119
-In other words, the vector definitions in the fsl-imx6.h file are reversed.
-Fixing the interrupts alone causes problems with older Linux kernels:
-The Ethernet interface will fail to probe with Linux v4.9 and earlier.
-Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
-error handling. This is a Linux kernel problem, not a qemu problem:
-the Linux kernel only worked by accident since it requested both interrupts.
-For backward compatibility, generate the Ethernet interrupt on both interrupt
-lines. This was shown to work from all Linux kernel releases starting with
-v3.16.
-Link: https://bugs.launchpad.net/qemu/+bug/1753309
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6.h |  4 ++--
+ target/arm/cpu.h               |  1 -
- hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
+ target/arm/sve_ldst_internal.h |  1 +
-files changed, 29 insertions(+), 3 deletions(-)
+ target/arm/mte_helper.c        | 62 ++++++++++------------------------
  target/arm/sve_helper.c        | 54 ++++++++++-------------------
  target/arm/tlb_helper.c        |  4 ---
 files changed, 36 insertions(+), 86 deletions(-)
-diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
+--- a/target/arm/cpu.h
-+++ b/include/hw/arm/fsl-imx6.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
+@@ -XXX,XX +XXX,XX @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
- #define FSL_IMX6_HDMI_MASTER_IRQ 115
+  * generic target bits directly.
- #define FSL_IMX6_HDMI_CEC_IRQ 116
+  */
- #define FSL_IMX6_MLB150_LOW_IRQ 117
+ #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
--#define FSL_IMX6_ENET_MAC_1588_IRQ 118
+-#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
--#define FSL_IMX6_ENET_MAC_IRQ 119
-+#define FSL_IMX6_ENET_MAC_IRQ 118
+ /*
-+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
+  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
- #define FSL_IMX6_PCIE1_IRQ 120
+diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h
- #define FSL_IMX6_PCIE2_IRQ 121
+index XXXXXXX..XXXXXXX 100644
- #define FSL_IMX6_PCIE3_IRQ 122
+--- a/target/arm/sve_ldst_internal.h
-diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
++++ b/target/arm/sve_ldst_internal.h
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ typedef struct {
---- a/hw/net/imx_fec.c
+     void *host;
-+++ b/hw/net/imx_fec.c
+     int flags;
-@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
+     MemTxAttrs attrs;
++    bool tagged;
- static void imx_eth_update(IMXFECState *s)
+ } SVEHostPage;
- {
--    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mte_helper.c
 +++ b/target/arm/mte_helper.c
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
                        TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1);
      return tags + index;
  #else
 -    uintptr_t index;
      CPUTLBEntryFull *full;
 +    MemTxAttrs attrs;
      int in_page, flags;
 -    ram_addr_t ptr_ra;
      hwaddr ptr_paddr, tag_paddr, xlat;
      MemoryRegion *mr;
      ARMASIdx tag_asi;
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
       * valid.  Indicate to probe_access_flags no-fault, then assert that
       * we received a valid page.
       */
 -    flags = probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx,
 -                               ra == 0, &host, ra);
 +    flags = probe_access_full(env, ptr, ptr_access, ptr_mmu_idx,
 +                              ra == 0, &host, &full, ra);
      assert(!(flags & TLB_INVALID_MASK));
 -    /*
 -     * Find the CPUTLBEntryFull for ptr.  This *must* be present in the TLB
 -     * because we just found the mapping.
 -     * TODO: Perhaps there should be a cputlb helper that returns a
 -     * matching tlb entry + iotlb entry.
 -     */
 -    index = tlb_index(env, ptr_mmu_idx, ptr);
 -# ifdef CONFIG_DEBUG_TCG
 -    {
 -        CPUTLBEntry *entry = tlb_entry(env, ptr_mmu_idx, ptr);
 -        target_ulong comparator = (ptr_access == MMU_DATA_LOAD
 -                                   ? entry->addr_read
 -                                   : tlb_addr_write(entry));
 -        g_assert(tlb_hit(comparator, ptr));
 -    }
 -# endif
 -    full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index];
 -
      /* If the virtual page MemAttr != Tagged, access unchecked. */
 -    if (!arm_tlb_mte_tagged(&full->attrs)) {
 +    if (full->pte_attrs != 0xf0) {
          return NULL;
      }
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
          return NULL;
      }
 +    /*
-+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
++     * Remember these values across the second lookup below,
-+     * interrupts swapped. This worked with older versions of Linux (4.14
++     * which may invalidate this pointer via tlb resize.
 +     * and older) since Linux associated both interrupt lines with Ethernet
 +     * MAC interrupts. Specifically,
 +     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
 +     *   timer interrupts. Those versions of Linux fail with versions of QEMU
 +     *   with swapped interrupt assignments.
 +     * - In linux 4.14, both interrupt lines were registered with the Ethernet
 +     *   MAC interrupt handler. As a result, all versions of qemu happen to
 +     *   work, though that is accidental.
 +     * - In Linux 4.9 and older, the timer interrupt was registered directly
 +     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
 +     *   redirected to a GPIO interrupt to work around erratum ERR006687.
 +     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
 +     *   interrupt never fired since IOMUX is currently not supported in qemu.
 +     *   Linux instead received MAC interrupts on the timer interrupt.
 +     *   As a result, qemu versions with the swapped interrupt assignment work,
 +     *   albeit accidentally, but qemu versions with the correct interrupt
 +     *   assignment fail.
 +     *
 +     * To ensure that all versions of Linux work, generate ENET_INT_MAC
 +     * interrrupts on both interrupt lines. This should be changed if and when
 +     * qemu supports IOMUX.
 +     */
-+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
++    ptr_paddr = full->phys_addr;
-+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
++    attrs = full->attrs;
-         qemu_set_irq(s->irq[1], 1);
++    full = NULL;
-     } else {
++
-         qemu_set_irq(s->irq[1], 0);
+     /*
       * The Normal memory access can extend to the next page.  E.g. a single
       * 8-byte access to the last byte of a page will check only the last
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
       */
      in_page = -(ptr | TARGET_PAGE_MASK);
      if (unlikely(ptr_size > in_page)) {
 -        void *ignore;
 -        flags |= probe_access_flags(env, ptr + in_page, ptr_access,
 -                                    ptr_mmu_idx, ra == 0, &ignore, ra);
 +        flags |= probe_access_full(env, ptr + in_page, ptr_access,
 +                                   ptr_mmu_idx, ra == 0, &host, &full, ra);
          assert(!(flags & TLB_INVALID_MASK));
      }
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      if (unlikely(flags & TLB_WATCHPOINT)) {
          int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
          assert(ra != 0);
 -        cpu_check_watchpoint(env_cpu(env), ptr, ptr_size,
 -                             full->attrs, wp, ra);
 +        cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra);
      }
 -    /*
 -     * Find the physical address within the normal mem space.
 -     * The memory region lookup must succeed because TLB_MMIO was
 -     * not set in the cputlb lookup above.
 -     */
 -    mr = memory_region_from_host(host, &ptr_ra);
 -    tcg_debug_assert(mr != NULL);
 -    tcg_debug_assert(memory_region_is_ram(mr));
 -    ptr_paddr = ptr_ra;
 -    do {
 -        ptr_paddr += mr->addr;
 -        mr = mr->container;
 -    } while (mr);
 -
      /* Convert to the physical address in tag space.  */
      tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1);
      /* Look up the address in tag space. */
 -    tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
 +    tag_asi = attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
      tag_as = cpu_get_address_space(env_cpu(env), tag_asi);
      mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL,
 -                                 tag_access == MMU_DATA_STORE,
 -                                 full->attrs);
 +                                 tag_access == MMU_DATA_STORE, attrs);
      /*
       * Note that @mr will never be NULL.  If there is nothing in the address
 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sve_helper.c
 +++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
       */
      addr = useronly_clean_ptr(addr);
 +#ifdef CONFIG_USER_ONLY
      flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
                                 &info->host, retaddr);
 +    memset(&info->attrs, 0, sizeof(info->attrs));
 +    /* Require both ANON and MTE; see allocation_tag_mem(). */
 +    info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
 +#else
 +    CPUTLBEntryFull *full;
 +    flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
 +                              &info->host, &full, retaddr);
 +    info->attrs = full->attrs;
 +    info->tagged = full->pte_attrs == 0xf0;
 +#endif
      info->flags = flags;
      if (flags & TLB_INVALID_MASK) {
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
      /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
      info->host -= mem_off;
 -
 -#ifdef CONFIG_USER_ONLY
 -    memset(&info->attrs, 0, sizeof(info->attrs));
 -    /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */
 -    arm_tlb_mte_tagged(&info->attrs) =
 -        (flags & PAGE_ANON) && (flags & PAGE_MTE);
 -#else
 -    /*
 -     * Find the iotlbentry for addr and return the transaction attributes.
 -     * This *must* be present in the TLB because we just found the mapping.
 -     */
 -    {
 -        uintptr_t index = tlb_index(env, mmu_idx, addr);
 -
 -# ifdef CONFIG_DEBUG_TCG
 -        CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
 -        target_ulong comparator = (access_type == MMU_DATA_LOAD
 -                                   ? entry->addr_read
 -                                   : tlb_addr_write(entry));
 -        g_assert(tlb_hit(comparator, addr));
 -# endif
 -
 -        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
 -        info->attrs = full->attrs;
 -    }
 -#endif
 -
      return true;
  }
@@ -XXX,XX +XXX,XX @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env,
      intptr_t mem_off, reg_off, reg_last;
      /* Process the page only if MemAttr == Tagged. */
 -    if (arm_tlb_mte_tagged(&info->page[0].attrs)) {
 +    if (info->page[0].tagged) {
          mem_off = info->mem_off_first[0];
          reg_off = info->reg_off_first[0];
          reg_last = info->reg_off_split;
@@ -XXX,XX +XXX,XX @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env,
      }
      mem_off = info->mem_off_first[1];
 -    if (mem_off >= 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) {
 +    if (mem_off >= 0 && info->page[1].tagged) {
          reg_off = info->reg_off_first[1];
          reg_last = info->reg_off_last[1];
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
       * Disable MTE checking if the Tagged bit is not set.  Since TBI must
       * be set within MTEDESC for MTE, !mtedesc => !mte_active.
       */
 -    if (!arm_tlb_mte_tagged(&info.page[0].attrs)) {
 +    if (!info.page[0].tagged) {
          mtedesc = 0;
      }
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                          cpu_check_watchpoint(env_cpu(env), addr, msize,
                                               info.attrs, BP_MEM_READ, retaddr);
                      }
 -                    if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
 +                    if (mtedesc && info.tagged) {
                          mte_check(env, mtedesc, addr, retaddr);
                      }
                      if (unlikely(info.flags & TLB_MMIO)) {
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                                               msize, info.attrs,
                                               BP_MEM_READ, retaddr);
                      }
 -                    if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
 +                    if (mtedesc && info.tagged) {
                          mte_check(env, mtedesc, addr, retaddr);
                      }
                      tlb_fn(env, &scratch, reg_off, addr, retaddr);
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                       (env_cpu(env), addr, msize) & BP_MEM_READ)) {
                      goto fault;
                  }
 -                if (mtedesc &&
 -                    arm_tlb_mte_tagged(&info.attrs) &&
 -                    !mte_probe(env, mtedesc, addr)) {
 +                if (mtedesc && info.tagged && !mte_probe(env, mtedesc, addr)) {
                      goto fault;
                  }
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                                           info.attrs, BP_MEM_WRITE, retaddr);
                  }
 -                if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
 +                if (mtedesc && info.tagged) {
                      mte_check(env, mtedesc, addr, retaddr);
                  }
              }
 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tlb_helper.c
 +++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
              res.f.phys_addr &= TARGET_PAGE_MASK;
              address &= TARGET_PAGE_MASK;
          }
 -        /* Notice and record tagged memory. */
 -        if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
 -            arm_tlb_mte_tagged(&res.f.attrs) = true;
 -        }
          res.f.pte_attrs = res.cacheattrs.attrs;
          res.f.shareability = res.cacheattrs.shareability;
 --
-.16.2
+.25.1

-New patch
+[PULL 05/24] target/arm: Use probe_access_full for BTI
+From: Richard Henderson <richard.henderson@linaro.org>
+Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit.
+In is_guarded_page, use probe_access_full instead of just guessing
+that the tlb entry is still present.  Also handles the FIXME about
+executing from device memory.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-4-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu-param.h     |  9 +++++----
+ target/arm/cpu.h           | 13 -------------
+ target/arm/internals.h     |  1 +
+ target/arm/ptw.c           |  7 ++++---
+ target/arm/translate-a64.c | 21 ++++++++++-----------
+files changed, 20 insertions(+), 31 deletions(-)
+diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu-param.h
++++ b/target/arm/cpu-param.h
+@@ -XXX,XX +XXX,XX @@
+  *
+  * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2].
+  * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format.
+- * For shareability, as in the SH field of the VMSAv8-64 PTEs.
++ * For shareability and guarded, as in the SH and GP fields respectively
++ * of the VMSAv8-64 PTEs.
+  */
+ # define TARGET_PAGE_ENTRY_EXTRA  \
+-     uint8_t pte_attrs;           \
+-     uint8_t shareability;
+-
++    uint8_t pte_attrs;            \
++    uint8_t shareability;         \
++    bool guarded;
+ #endif
+ #define NB_MMU_MODES 8
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
+ /* Shared between translate-sve.c and sve_helper.c.  */
+ extern const uint64_t pred_esz_masks[5];
+-/* Helper for the macros below, validating the argument type. */
+-static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
+-{
+-    return x;
+-}
+-
+-/*
+- * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
+- * Using these should be a bit more self-documenting than using the
+- * generic target bits directly.
+- */
+-#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
+-
+ /*
+  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
+  * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
+     unsigned int attrs:8;
+     unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
+     bool is_s2_format:1;
++    bool guarded:1;              /* guarded bit of the v8-64 PTE */
+ } ARMCacheAttrs;
+ /* Fields that are valid upon success. */
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+          */
+         result->f.attrs.secure = false;
+     }
+-    /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.  */
+-    if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
+-        arm_tlb_bti_gp(&result->f.attrs) = true;
++
++    /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB.  */
++    if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
++        result->f.guarded = guarded;
+     }
+     if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
+ #ifdef CONFIG_USER_ONLY
+     return page_get_flags(addr) & PAGE_BTI;
+ #else
++    CPUTLBEntryFull *full;
++    void *host;
+     int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
+-    unsigned int index = tlb_index(env, mmu_idx, addr);
+-    CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
++    int flags;
+     /*
+      * We test this immediately after reading an insn, which means
+-     * that any normal page must be in the TLB.  The only exception
+-     * would be for executing from flash or device memory, which
+-     * does not retain the TLB entry.
+-     *
+-     * FIXME: Assume false for those, for now.  We could use
+-     * arm_cpu_get_phys_page_attrs_debug to re-read the page
+-     * table entry even for that case.
++     * that the TLB entry must be present and valid, and thus this
++     * access will never raise an exception.
+      */
+-    return (tlb_hit(entry->addr_code, addr) &&
+-            arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs));
++    flags = probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx,
++                              false, &host, &full, 0);
++    assert(!(flags & TLB_INVALID_MASK));
++
++    return full->guarded;
+ #endif
+ }
+--
+.25.1

-New patch
+[PULL 06/24] target/arm: Add ARMMMUIdx_Phys_{S,NS}
+From: Richard Henderson <richard.henderson@linaro.org>
+Not yet used, but add mmu indexes for 1-1 mapping
+to physical addresses.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu-param.h |  2 +-
+ target/arm/cpu.h       |  7 ++++++-
+ target/arm/ptw.c       | 19 +++++++++++++++++--
+files changed, 24 insertions(+), 4 deletions(-)
+diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu-param.h
++++ b/target/arm/cpu-param.h
+@@ -XXX,XX +XXX,XX @@
+     bool guarded;
+ #endif
+-#define NB_MMU_MODES 8
++#define NB_MMU_MODES 10
+ #endif
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
+  * EL2 EL2&0 +PAN
+  * EL2 (aka NS PL2)
+  * EL3 (aka S PL1)
++ * Physical (NS & S)
+  *
+- * for a total of 8 different mmu_idx.
++ * for a total of 10 different mmu_idx.
+  *
+  * R profile CPUs have an MPU, but can use the same set of MMU indexes
+  * as A profile. They only need to distinguish EL0 and EL1 (and
+@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
+     ARMMMUIdx_E2        = 6 | ARM_MMU_IDX_A,
+     ARMMMUIdx_E3        = 7 | ARM_MMU_IDX_A,
++    /* TLBs with 1-1 mapping to the physical address spaces. */
++    ARMMMUIdx_Phys_NS   = 8 | ARM_MMU_IDX_A,
++    ARMMMUIdx_Phys_S    = 9 | ARM_MMU_IDX_A,
++
+     /*
+      * These are not allocated TLBs and are used only for AT system
+      * instructions or for the first stage of an S12 page table walk.
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
+     case ARMMMUIdx_E3:
+         break;
++    case ARMMMUIdx_Phys_NS:
++    case ARMMMUIdx_Phys_S:
++        /* No translation for physical address spaces. */
++        return true;
++
+     default:
+         g_assert_not_reached();
+     }
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+ {
+     uint8_t memattr = 0x00;    /* Device nGnRnE */
+     uint8_t shareability = 0;  /* non-sharable */
++    int r_el;
+-    if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
+-        int r_el = regime_el(env, mmu_idx);
++    switch (mmu_idx) {
++    case ARMMMUIdx_Stage2:
++    case ARMMMUIdx_Stage2_S:
++    case ARMMMUIdx_Phys_NS:
++    case ARMMMUIdx_Phys_S:
++        break;
++    default:
++        r_el = regime_el(env, mmu_idx);
+         if (arm_el_is_aa64(env, r_el)) {
+             int pamax = arm_pamax(env_archcpu(env));
+             uint64_t tcr = env->cp15.tcr_el[r_el];
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+             shareability = 2; /* outer sharable */
+         }
+         result->cacheattrs.is_s2_format = false;
++        break;
+     }
+     result->f.phys_addr = address;
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
+         is_secure = arm_is_secure_below_el3(env);
+         break;
+     case ARMMMUIdx_Stage2:
++    case ARMMMUIdx_Phys_NS:
+     case ARMMMUIdx_MPrivNegPri:
+     case ARMMMUIdx_MUserNegPri:
+     case ARMMMUIdx_MPriv:
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
+         break;
+     case ARMMMUIdx_E3:
+     case ARMMMUIdx_Stage2_S:
++    case ARMMMUIdx_Phys_S:
+     case ARMMMUIdx_MSPrivNegPri:
+     case ARMMMUIdx_MSUserNegPri:
+     case ARMMMUIdx_MSPriv:
+--
+.25.1

-New patch
+[PULL 07/24] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx
+From: Richard Henderson <richard.henderson@linaro.org>
+We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb.
+Flush the tlb when invalidating stage 1+2 translations.  Re-use
+alle1_tlbmask() for other instances of EL1&0 + Stage2.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20221011031911.2408754-6-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu-param.h |   2 +-
+ target/arm/cpu.h       |  23 ++++---
+ target/arm/helper.c    | 151 ++++++++++++++++++++++++++++++-----------
+files changed, 127 insertions(+), 49 deletions(-)
+diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu-param.h
++++ b/target/arm/cpu-param.h
+@@ -XXX,XX +XXX,XX @@
+     bool guarded;
+ #endif
+-#define NB_MMU_MODES 10
++#define NB_MMU_MODES 12
+ #endif
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
+  * EL2 (aka NS PL2)
+  * EL3 (aka S PL1)
+  * Physical (NS & S)
++ * Stage2 (NS & S)
+  *
+- * for a total of 10 different mmu_idx.
++ * for a total of 12 different mmu_idx.
+  *
+  * R profile CPUs have an MPU, but can use the same set of MMU indexes
+  * as A profile. They only need to distinguish EL0 and EL1 (and
+@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
+     ARMMMUIdx_Phys_NS   = 8 | ARM_MMU_IDX_A,
+     ARMMMUIdx_Phys_S    = 9 | ARM_MMU_IDX_A,
++    /*
++     * Used for second stage of an S12 page table walk, or for descriptor
++     * loads during first stage of an S1 page table walk.  Note that both
++     * are in use simultaneously for SecureEL2: the security state for
++     * the S2 ptw is selected by the NS bit from the S1 ptw.
++     */
++    ARMMMUIdx_Stage2    = 10 | ARM_MMU_IDX_A,
++    ARMMMUIdx_Stage2_S  = 11 | ARM_MMU_IDX_A,
++
+     /*
+      * These are not allocated TLBs and are used only for AT system
+      * instructions or for the first stage of an S12 page table walk.
+@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
+     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
+     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
+     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
+-    /*
+-     * Not allocated a TLB: used only for second stage of an S12 page
+-     * table walk, or for descriptor loads during first stage of an S1
+-     * page table walk. Note that if we ever want to have a TLB for this
+-     * then various TLB flush insns which currently are no-ops or flush
+-     * only stage 1 MMU indexes will need to change to flush stage 2.
+-     */
+-    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
+-    ARMMMUIdx_Stage2_S   = 4 | ARM_MMU_IDX_NOTLB,
+     /*
+      * M-profile.
+@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
+     TO_CORE_BIT(E20_2),
+     TO_CORE_BIT(E20_2_PAN),
+     TO_CORE_BIT(E3),
++    TO_CORE_BIT(Stage2),
++    TO_CORE_BIT(Stage2_S),
+     TO_CORE_BIT(MUser),
+     TO_CORE_BIT(MPriv),
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+     raw_write(env, ri, value);
+ }
++static int alle1_tlbmask(CPUARMState *env)
++{
++    /*
++     * Note that the 'ALL' scope must invalidate both stage 1 and
++     * stage 2 translations, whereas most other scopes only invalidate
++     * stage 1 translations.
++     */
++    return (ARMMMUIdxBit_E10_1 |
++            ARMMMUIdxBit_E10_1_PAN |
++            ARMMMUIdxBit_E10_0 |
++            ARMMMUIdxBit_Stage2 |
++            ARMMMUIdxBit_Stage2_S);
++}
++
++
+ /* IS variants of TLB operations must affect all cores */
+ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ {
+     CPUState *cs = env_cpu(env);
+-    tlb_flush_by_mmuidx(cs,
+-                        ARMMMUIdxBit_E10_1 |
+-                        ARMMMUIdxBit_E10_1_PAN |
+-                        ARMMMUIdxBit_E10_0);
++    tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
+ }
+ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ {
+     CPUState *cs = env_cpu(env);
+-    tlb_flush_by_mmuidx_all_cpus_synced(cs,
+-                                        ARMMMUIdxBit_E10_1 |
+-                                        ARMMMUIdxBit_E10_1_PAN |
+-                                        ARMMMUIdxBit_E10_0);
++    tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env));
+ }
+@@ -XXX,XX +XXX,XX @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                              ARMMMUIdxBit_E2);
+ }
++static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
++                                uint64_t value)
++{
++    CPUState *cs = env_cpu(env);
++    uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12;
++
++    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
++}
++
++static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
++                                uint64_t value)
++{
++    CPUState *cs = env_cpu(env);
++    uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12;
++
++    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2);
++}
++
+ static const ARMCPRegInfo cp_reginfo[] = {
+     /* Define the secure and non-secure FCSE identifier CP registers
+      * separately because there is no secure bank in V8 (no _EL3).  This allows
+@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+     /*
+      * A change in VMID to the stage2 page table (Stage2) invalidates
+-     * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
++     * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
+      */
+     if (raw_read(env, ri) != value) {
+-        uint16_t mask = ARMMMUIdxBit_E10_1 |
+-                        ARMMMUIdxBit_E10_1_PAN |
+-                        ARMMMUIdxBit_E10_0;
+-        tlb_flush_by_mmuidx(cs, mask);
++        tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
+         raw_write(env, ri, value);
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+     }
+ }
+-static int alle1_tlbmask(CPUARMState *env)
+-{
+-    /*
+-     * Note that the 'ALL' scope must invalidate both stage 1 and
+-     * stage 2 translations, whereas most other scopes only invalidate
+-     * stage 1 translations.
+-     */
+-    return (ARMMMUIdxBit_E10_1 |
+-            ARMMMUIdxBit_E10_1_PAN |
+-            ARMMMUIdxBit_E10_0);
+-}
+-
+ static int e2_tlbmask(CPUARMState *env)
+ {
+     return (ARMMMUIdxBit_E20_0 |
+@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                                   ARMMMUIdxBit_E3, bits);
+ }
++static int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
++{
++    /*
++     * The MSB of value is the NS field, which only applies if SEL2
++     * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
++     */
++    return (value >= 0
++            && cpu_isar_feature(aa64_sel2, env_archcpu(env))
++            && arm_is_secure_below_el3(env)
++            ? ARMMMUIdxBit_Stage2_S
++            : ARMMMUIdxBit_Stage2);
++}
++
++static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
++                                    uint64_t value)
++{
++    CPUState *cs = env_cpu(env);
++    int mask = ipas2e1_tlbmask(env, value);
++    uint64_t pageaddr = sextract64(value << 12, 0, 56);
++
++    if (tlb_force_broadcast(env)) {
++        tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
++    } else {
++        tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
++    }
++}
++
++static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
++                                      uint64_t value)
++{
++    CPUState *cs = env_cpu(env);
++    int mask = ipas2e1_tlbmask(env, value);
++    uint64_t pageaddr = sextract64(value << 12, 0, 56);
++
++    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
++}
++
+ #ifdef TARGET_AARCH64
+ typedef struct {
+     uint64_t base;
+@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
+     do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
+ }
++
++static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
++                                     uint64_t value)
++{
++    do_rvae_write(env, value, ipas2e1_tlbmask(env, value),
++                  tlb_force_broadcast(env));
++}
++
++static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
++                                       const ARMCPRegInfo *ri,
++                                       uint64_t value)
++{
++    do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true);
++}
+ #endif
+ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+       .writefn = tlbi_aa64_vae1_write },
+     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ipas2e1is_write },
+     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ipas2e1is_write },
+     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
+       .access = PL2_W, .type = ARM_CP_NO_RAW,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+       .writefn = tlbi_aa64_alle1is_write },
+     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ipas2e1_write },
+     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ipas2e1_write },
+     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
+       .access = PL2_W, .type = ARM_CP_NO_RAW,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+       .writefn = tlbimva_hyp_is_write },
+     { .name = "TLBIIPAS2",
+       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
+-      .type = ARM_CP_NOP, .access = PL2_W },
++      .type = ARM_CP_NO_RAW, .access = PL2_W,
++      .writefn = tlbiipas2_hyp_write },
+     { .name = "TLBIIPAS2IS",
+       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
+-      .type = ARM_CP_NOP, .access = PL2_W },
++      .type = ARM_CP_NO_RAW, .access = PL2_W,
++      .writefn = tlbiipas2is_hyp_write },
+     { .name = "TLBIIPAS2L",
+       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
+-      .type = ARM_CP_NOP, .access = PL2_W },
++      .type = ARM_CP_NO_RAW, .access = PL2_W,
++      .writefn = tlbiipas2_hyp_write },
+     { .name = "TLBIIPAS2LIS",
+       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
+-      .type = ARM_CP_NOP, .access = PL2_W },
++      .type = ARM_CP_NO_RAW, .access = PL2_W,
++      .writefn = tlbiipas2is_hyp_write },
+     /* 32 bit cache operations */
+     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
+       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
+       .writefn = tlbi_aa64_rvae1_write },
+     { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ripas2e1is_write },
+     { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ripas2e1is_write },
+     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
+       .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
+       .writefn = tlbi_aa64_rvae2is_write },
+     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
+-      .access = PL2_W, .type = ARM_CP_NOP },
+-   { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ripas2e1_write },
++    { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
+-      .access = PL2_W, .type = ARM_CP_NOP },
++      .access = PL2_W, .type = ARM_CP_NO_RAW,
++      .writefn = tlbi_aa64_ripas2e1_write },
+    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
+       .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+--
+.25.1

-New patch
+[PULL 08/24] target/arm: Restrict tlb flush from vttbr_write to vmid change
+From: Richard Henderson <richard.henderson@linaro.org>
+Compare only the VMID field when considering whether we need to flush.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20221011031911.2408754-7-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+      * A change in VMID to the stage2 page table (Stage2) invalidates
+      * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
+      */
+-    if (raw_read(env, ri) != value) {
++    if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
+         tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
+-        raw_write(env, ri, value);
+     }
++    raw_write(env, ri, value);
+ }
+ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
+--
+.25.1

-New patch
+[PULL 09/24] target/arm: Split out S1Translate type
+From: Richard Henderson <richard.henderson@linaro.org>
+Consolidate most of the inputs and outputs of S1_ptw_translate
+into a single structure.  Plumb this through arm_ld*_ptw from
+the controlling get_phys_addr_* routine.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20221011031911.2408754-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/ptw.c | 140 ++++++++++++++++++++++++++---------------------
+file changed, 79 insertions(+), 61 deletions(-)
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@
+ #include "idau.h"
+-static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+-                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-                               bool is_secure, bool s1_is_el0,
++typedef struct S1Translate {
++    ARMMMUIdx in_mmu_idx;
++    bool in_secure;
++    bool out_secure;
++    hwaddr out_phys;
++} S1Translate;
++
++static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
++                               uint64_t address,
++                               MMUAccessType access_type, bool s1_is_el0,
+                                GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+     __attribute__((nonnull));
+@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
+ }
+ /* Translate a S1 pagetable walk through S2 if needed.  */
+-static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
+-                               hwaddr addr, bool *is_secure_ptr,
+-                               ARMMMUFaultInfo *fi)
++static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
++                             hwaddr addr, ARMMMUFaultInfo *fi)
+ {
+-    bool is_secure = *is_secure_ptr;
++    bool is_secure = ptw->in_secure;
+     ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+-    if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
++    if (arm_mmu_idx_is_stage1_of_2(ptw->in_mmu_idx) &&
+         !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
+         GetPhysAddrResult s2 = {};
++        S1Translate s2ptw = {
++            .in_mmu_idx = s2_mmu_idx,
++            .in_secure = is_secure,
++        };
+         uint64_t hcr;
+         int ret;
+-        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
+-                                 is_secure, false, &s2, fi);
++        ret = get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
++                                 false, &s2, fi);
+         if (ret) {
+             assert(fi->type != ARMFault_None);
+             fi->s2addr = addr;
+             fi->stage2 = true;
+             fi->s1ptw = true;
+             fi->s1ns = !is_secure;
+-            return ~0;
++            return false;
+         }
+         hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
+             fi->stage2 = true;
+             fi->s1ptw = true;
+             fi->s1ns = !is_secure;
+-            return ~0;
++            return false;
+         }
+         if (arm_is_secure_below_el3(env)) {
+@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
+             } else {
+                 is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
+             }
+-            *is_secure_ptr = is_secure;
+         } else {
+             assert(!is_secure);
+         }
+         addr = s2.f.phys_addr;
+     }
+-    return addr;
++
++    ptw->out_secure = is_secure;
++    ptw->out_phys = addr;
++    return true;
+ }
+ /* All loads done in the course of a page table walk go through here. */
+-static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
+-                            ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
++static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
++                            ARMMMUFaultInfo *fi)
+ {
+     CPUState *cs = env_cpu(env);
+     MemTxAttrs attrs = {};
+@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
+     AddressSpace *as;
+     uint32_t data;
+-    addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
+-    attrs.secure = is_secure;
+-    as = arm_addressspace(cs, attrs);
+-    if (fi->s1ptw) {
++    if (!S1_ptw_translate(env, ptw, addr, fi)) {
+         return 0;
+     }
+-    if (regime_translation_big_endian(env, mmu_idx)) {
++    addr = ptw->out_phys;
++    attrs.secure = ptw->out_secure;
++    as = arm_addressspace(cs, attrs);
++    if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
+         data = address_space_ldl_be(as, addr, attrs, &result);
+     } else {
+         data = address_space_ldl_le(as, addr, attrs, &result);
+@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
+     return 0;
+ }
+-static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
+-                            ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
++static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
++                            ARMMMUFaultInfo *fi)
+ {
+     CPUState *cs = env_cpu(env);
+     MemTxAttrs attrs = {};
+@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
+     AddressSpace *as;
+     uint64_t data;
+-    addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
+-    attrs.secure = is_secure;
+-    as = arm_addressspace(cs, attrs);
+-    if (fi->s1ptw) {
++    if (!S1_ptw_translate(env, ptw, addr, fi)) {
+         return 0;
+     }
+-    if (regime_translation_big_endian(env, mmu_idx)) {
++    addr = ptw->out_phys;
++    attrs.secure = ptw->out_secure;
++    as = arm_addressspace(cs, attrs);
++    if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
+         data = address_space_ldq_be(as, addr, attrs, &result);
+     } else {
+         data = address_space_ldq_le(as, addr, attrs, &result);
+@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
+     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
+ }
+-static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
+-                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-                             bool is_secure, GetPhysAddrResult *result,
+-                             ARMMMUFaultInfo *fi)
++static bool get_phys_addr_v5(CPUARMState *env, S1Translate *ptw,
++                             uint32_t address, MMUAccessType access_type,
++                             GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+ {
+     int level = 1;
+     uint32_t table;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
+     /* Pagetable walk.  */
+     /* Lookup l1 descriptor.  */
+-    if (!get_level1_table_address(env, mmu_idx, &table, address)) {
++    if (!get_level1_table_address(env, ptw->in_mmu_idx, &table, address)) {
+         /* Section translation fault if page walk is disabled by PD0 or PD1 */
+         fi->type = ARMFault_Translation;
+         goto do_fault;
+     }
+-    desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
++    desc = arm_ldl_ptw(env, ptw, table, fi);
+     if (fi->type != ARMFault_None) {
+         goto do_fault;
+     }
+     type = (desc & 3);
+     domain = (desc >> 5) & 0x0f;
+-    if (regime_el(env, mmu_idx) == 1) {
++    if (regime_el(env, ptw->in_mmu_idx) == 1) {
+         dacr = env->cp15.dacr_ns;
+     } else {
+         dacr = env->cp15.dacr_s;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
+             /* Fine pagetable.  */
+             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
+         }
+-        desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
++        desc = arm_ldl_ptw(env, ptw, table, fi);
+         if (fi->type != ARMFault_None) {
+             goto do_fault;
+         }
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
+             g_assert_not_reached();
+         }
+     }
+-    result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
++    result->f.prot = ap_to_rw_prot(env, ptw->in_mmu_idx, ap, domain_prot);
+     result->f.prot |= result->f.prot ? PAGE_EXEC : 0;
+     if (!(result->f.prot & (1 << access_type))) {
+         /* Access permission fault.  */
+@@ -XXX,XX +XXX,XX @@ do_fault:
+     return true;
+ }
+-static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
+-                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-                             bool is_secure, GetPhysAddrResult *result,
+-                             ARMMMUFaultInfo *fi)
++static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
++                             uint32_t address, MMUAccessType access_type,
++                             GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+ {
+     ARMCPU *cpu = env_archcpu(env);
++    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
+     int level = 1;
+     uint32_t table;
+     uint32_t desc;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
+         fi->type = ARMFault_Translation;
+         goto do_fault;
+     }
+-    desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
++    desc = arm_ldl_ptw(env, ptw, table, fi);
+     if (fi->type != ARMFault_None) {
+         goto do_fault;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
+         ns = extract32(desc, 3, 1);
+         /* Lookup l2 entry.  */
+         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
+-        desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
++        desc = arm_ldl_ptw(env, ptw, table, fi);
+         if (fi->type != ARMFault_None) {
+             goto do_fault;
+         }
+@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
+  * the WnR bit is never set (the caller must do this).
+  *
+  * @env: CPUARMState
++ * @ptw: Current and next stage parameters for the walk.
+  * @address: virtual address to get physical address for
+  * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
+- * @mmu_idx: MMU index indicating required translation regime
+- * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page
+- *             table walk), must be true if this is stage 2 of a stage 1+2
++ * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
++ *             (so this is a stage 2 page table walk),
++ *             must be true if this is stage 2 of a stage 1+2
+  *             walk for an EL0 access. If @mmu_idx is anything else,
+  *             @s1_is_el0 is ignored.
+  * @result: set on translation success,
+  * @fi: set to fault info if the translation fails
+  */
+-static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+-                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-                               bool is_secure, bool s1_is_el0,
++static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
++                               uint64_t address,
++                               MMUAccessType access_type, bool s1_is_el0,
+                                GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+ {
+     ARMCPU *cpu = env_archcpu(env);
++    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
++    bool is_secure = ptw->in_secure;
+     /* Read an LPAE long-descriptor translation table. */
+     ARMFaultType fault_type = ARMFault_Translation;
+     uint32_t level;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+         descaddr |= (address >> (stride * (4 - level))) & indexmask;
+         descaddr &= ~7ULL;
+         nstable = extract32(tableattrs, 4, 1);
+-        descriptor = arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, fi);
++        ptw->in_secure = !nstable;
++        descriptor = arm_ldq_ptw(env, ptw, descaddr, fi);
+         if (fi->type != ARMFault_None) {
+             goto do_fault;
+         }
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                                ARMMMUFaultInfo *fi)
+ {
+     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
++    S1Translate ptw;
+     if (mmu_idx != s1_mmu_idx) {
+         /*
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+             int ret;
+             bool ipa_secure, s2walk_secure;
+             ARMCacheAttrs cacheattrs1;
+-            ARMMMUIdx s2_mmu_idx;
+             bool is_el0;
+             uint64_t hcr;
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                 s2walk_secure = false;
+             }
+-            s2_mmu_idx = (s2walk_secure
+-                          ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
++            ptw.in_mmu_idx =
++                s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
++            ptw.in_secure = s2walk_secure;
+             is_el0 = mmu_idx == ARMMMUIdx_E10_0;
+             /*
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+             cacheattrs1 = result->cacheattrs;
+             memset(result, 0, sizeof(*result));
+-            ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
+-                                     s2walk_secure, is_el0, result, fi);
++            ret = get_phys_addr_lpae(env, &ptw, ipa, access_type,
++                                     is_el0, result, fi);
+             fi->s2addr = ipa;
+             /* Combine the S1 and S2 perms.  */
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+         return get_phys_addr_disabled(env, address, access_type, mmu_idx,
+                                       is_secure, result, fi);
+     }
++
++    ptw.in_mmu_idx = mmu_idx;
++    ptw.in_secure = is_secure;
++
+     if (regime_using_lpae_format(env, mmu_idx)) {
+-        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
+-                                  is_secure, false, result, fi);
++        return get_phys_addr_lpae(env, &ptw, address, access_type, false,
++                                  result, fi);
+     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
+-        return get_phys_addr_v6(env, address, access_type, mmu_idx,
+-                                is_secure, result, fi);
++        return get_phys_addr_v6(env, &ptw, address, access_type, result, fi);
+     } else {
+-        return get_phys_addr_v5(env, address, access_type, mmu_idx,
+-                                is_secure, result, fi);
++        return get_phys_addr_v5(env, &ptw, address, access_type, result, fi);
+     }
+ }
+--
+.25.1

-New patch
+[PULL 10/24] target/arm: Plumb debug into S1Translate
+From: Richard Henderson <richard.henderson@linaro.org>
+Before using softmmu page tables for the ptw, plumb down
+a debug parameter so that we can query page table entries
+from gdbstub without modifying cpu state.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-9-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/ptw.c | 55 ++++++++++++++++++++++++++++++++----------------
+file changed, 37 insertions(+), 18 deletions(-)
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@
+ typedef struct S1Translate {
+     ARMMMUIdx in_mmu_idx;
+     bool in_secure;
++    bool in_debug;
+     bool out_secure;
+     hwaddr out_phys;
+ } S1Translate;
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
+         S1Translate s2ptw = {
+             .in_mmu_idx = s2_mmu_idx,
+             .in_secure = is_secure,
++            .in_debug = ptw->in_debug,
+         };
+         uint64_t hcr;
+         int ret;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+     return 0;
+ }
+-bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+-                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
+-                               bool is_secure, GetPhysAddrResult *result,
+-                               ARMMMUFaultInfo *fi)
++static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
++                                      target_ulong address,
++                                      MMUAccessType access_type,
++                                      GetPhysAddrResult *result,
++                                      ARMMMUFaultInfo *fi)
+ {
++    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
+     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
+-    S1Translate ptw;
++    bool is_secure = ptw->in_secure;
+     if (mmu_idx != s1_mmu_idx) {
+         /*
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+             bool is_el0;
+             uint64_t hcr;
+-            ret = get_phys_addr_with_secure(env, address, access_type,
+-                                            s1_mmu_idx, is_secure, result, fi);
++            ptw->in_mmu_idx = s1_mmu_idx;
++            ret = get_phys_addr_with_struct(env, ptw, address, access_type,
++                                            result, fi);
+             /* If S1 fails or S2 is disabled, return early.  */
+             if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                 s2walk_secure = false;
+             }
+-            ptw.in_mmu_idx =
++            ptw->in_mmu_idx =
+                 s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+-            ptw.in_secure = s2walk_secure;
++            ptw->in_secure = s2walk_secure;
+             is_el0 = mmu_idx == ARMMMUIdx_E10_0;
+             /*
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+             cacheattrs1 = result->cacheattrs;
+             memset(result, 0, sizeof(*result));
+-            ret = get_phys_addr_lpae(env, &ptw, ipa, access_type,
++            ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
+                                      is_el0, result, fi);
+             fi->s2addr = ipa;
+@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                                       is_secure, result, fi);
+     }
+-    ptw.in_mmu_idx = mmu_idx;
+-    ptw.in_secure = is_secure;
+-
+     if (regime_using_lpae_format(env, mmu_idx)) {
+-        return get_phys_addr_lpae(env, &ptw, address, access_type, false,
++        return get_phys_addr_lpae(env, ptw, address, access_type, false,
+                                   result, fi);
+     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
+-        return get_phys_addr_v6(env, &ptw, address, access_type, result, fi);
++        return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
+     } else {
+-        return get_phys_addr_v5(env, &ptw, address, access_type, result, fi);
++        return get_phys_addr_v5(env, ptw, address, access_type, result, fi);
+     }
+ }
++bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
++                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
++                               bool is_secure, GetPhysAddrResult *result,
++                               ARMMMUFaultInfo *fi)
++{
++    S1Translate ptw = {
++        .in_mmu_idx = mmu_idx,
++        .in_secure = is_secure,
++    };
++    return get_phys_addr_with_struct(env, &ptw, address, access_type,
++                                     result, fi);
++}
++
+ bool get_phys_addr(CPUARMState *env, target_ulong address,
+                    MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                    GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
+ {
+     ARMCPU *cpu = ARM_CPU(cs);
+     CPUARMState *env = &cpu->env;
++    S1Translate ptw = {
++        .in_mmu_idx = arm_mmu_idx(env),
++        .in_secure = arm_is_secure(env),
++        .in_debug = true,
++    };
+     GetPhysAddrResult res = {};
+     ARMMMUFaultInfo fi = {};
+-    ARMMMUIdx mmu_idx = arm_mmu_idx(env);
+     bool ret;
+-    ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
++    ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi);
+     *attrs = res.f.attrs;
+     if (ret) {
+--
+.25.1

-New patch
+[PULL 11/24] target/arm: Move be test for regime into S1TranslateResult
+From: Richard Henderson <richard.henderson@linaro.org>
+Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/ptw.c | 6 ++++--
+file changed, 4 insertions(+), 2 deletions(-)
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
+     bool in_secure;
+     bool in_debug;
+     bool out_secure;
++    bool out_be;
+     hwaddr out_phys;
+ } S1Translate;
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
+     ptw->out_secure = is_secure;
+     ptw->out_phys = addr;
++    ptw->out_be = regime_translation_big_endian(env, ptw->in_mmu_idx);
+     return true;
+ }
+@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+     addr = ptw->out_phys;
+     attrs.secure = ptw->out_secure;
+     as = arm_addressspace(cs, attrs);
+-    if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
++    if (ptw->out_be) {
+         data = address_space_ldl_be(as, addr, attrs, &result);
+     } else {
+         data = address_space_ldl_le(as, addr, attrs, &result);
+@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+     addr = ptw->out_phys;
+     attrs.secure = ptw->out_secure;
+     as = arm_addressspace(cs, attrs);
+-    if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
++    if (ptw->out_be) {
+         data = address_space_ldq_be(as, addr, attrs, &result);
+     } else {
+         data = address_space_ldq_le(as, addr, attrs, &result);
+--
+.25.1

-New patch
+[PULL 12/24] target/arm: Use softmmu tlbs for page table walking
+From: Richard Henderson <richard.henderson@linaro.org>
+So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and
+arm_ldq_ptw.  Use probe_access_full to find the host address,
+and if so use a host load.  If the probe fails, we've got our
+fault info already.  On the off chance that page tables are not
+in RAM, continue to use the address_space_ld* functions.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h        |   5 +
+ target/arm/ptw.c        | 196 +++++++++++++++++++++++++---------------
+ target/arm/tlb_helper.c |  17 +++-
+files changed, 144 insertions(+), 74 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
+     target_ulong flags2;
+ } CPUARMTBFlags;
++typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
++
+ typedef struct CPUArchState {
+     /* Regs for current mode.  */
+     uint32_t regs[16];
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     struct CPUBreakpoint *cpu_breakpoint[16];
+     struct CPUWatchpoint *cpu_watchpoint[16];
++    /* Optional fault info across tlb lookup. */
++    ARMMMUFaultInfo *tlb_fi;
++
+     /* Fields up to this point are cleared by a CPU reset */
+     struct {} end_reset_fields;
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qemu/log.h"
+ #include "qemu/range.h"
++#include "exec/exec-all.h"
+ #include "cpu.h"
+ #include "internals.h"
+ #include "idau.h"
+@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
+     bool out_secure;
+     bool out_be;
+     hwaddr out_phys;
++    void *out_host;
+ } S1Translate;
+ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
+@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
+     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
+ }
+-static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
++static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
+ {
+     /*
+      * For an S1 page table walk, the stage 1 attributes are always
+@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
+      * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
+      * when cacheattrs.attrs bit [2] is 0.
+      */
+-    assert(cacheattrs.is_s2_format);
+     if (hcr & HCR_FWB) {
+-        return (cacheattrs.attrs & 0x4) == 0;
++        return (attrs & 0x4) == 0;
+     } else {
+-        return (cacheattrs.attrs & 0xc) == 0;
++        return (attrs & 0xc) == 0;
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
+                              hwaddr addr, ARMMMUFaultInfo *fi)
+ {
+     bool is_secure = ptw->in_secure;
++    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
+     ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
++    bool s2_phys = false;
++    uint8_t pte_attrs;
++    bool pte_secure;
+-    if (arm_mmu_idx_is_stage1_of_2(ptw->in_mmu_idx) &&
+-        !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
+-        GetPhysAddrResult s2 = {};
+-        S1Translate s2ptw = {
+-            .in_mmu_idx = s2_mmu_idx,
+-            .in_secure = is_secure,
+-            .in_debug = ptw->in_debug,
+-        };
+-        uint64_t hcr;
+-        int ret;
++    if (!arm_mmu_idx_is_stage1_of_2(mmu_idx)
++        || regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
++        s2_mmu_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
++        s2_phys = true;
++    }
+-        ret = get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
+-                                 false, &s2, fi);
+-        if (ret) {
+-            assert(fi->type != ARMFault_None);
+-            fi->s2addr = addr;
+-            fi->stage2 = true;
+-            fi->s1ptw = true;
+-            fi->s1ns = !is_secure;
+-            return false;
++    if (unlikely(ptw->in_debug)) {
++        /*
++         * From gdbstub, do not use softmmu so that we don't modify the
++         * state of the cpu at all, including softmmu tlb contents.
++         */
++        if (s2_phys) {
++            ptw->out_phys = addr;
++            pte_attrs = 0;
++            pte_secure = is_secure;
++        } else {
++            S1Translate s2ptw = {
++                .in_mmu_idx = s2_mmu_idx,
++                .in_secure = is_secure,
++                .in_debug = true,
++            };
++            GetPhysAddrResult s2 = { };
++            if (!get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
++                                    false, &s2, fi)) {
++                goto fail;
++            }
++            ptw->out_phys = s2.f.phys_addr;
++            pte_attrs = s2.cacheattrs.attrs;
++            pte_secure = s2.f.attrs.secure;
+         }
++        ptw->out_host = NULL;
++    } else {
++        CPUTLBEntryFull *full;
++        int flags;
+-        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+-        if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
++        env->tlb_fi = fi;
++        flags = probe_access_full(env, addr, MMU_DATA_LOAD,
++                                  arm_to_core_mmu_idx(s2_mmu_idx),
++                                  true, &ptw->out_host, &full, 0);
++        env->tlb_fi = NULL;
++
++        if (unlikely(flags & TLB_INVALID_MASK)) {
++            goto fail;
++        }
++        ptw->out_phys = full->phys_addr;
++        pte_attrs = full->pte_attrs;
++        pte_secure = full->attrs.secure;
++    }
++
++    if (!s2_phys) {
++        uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
++
++        if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) {
+             /*
+              * PTW set and S1 walk touched S2 Device memory:
+              * generate Permission fault.
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
+             fi->s1ns = !is_secure;
+             return false;
+         }
+-
+-        if (arm_is_secure_below_el3(env)) {
+-            /* Check if page table walk is to secure or non-secure PA space. */
+-            if (is_secure) {
+-                is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
+-            } else {
+-                is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
+-            }
+-        } else {
+-            assert(!is_secure);
+-        }
+-
+-        addr = s2.f.phys_addr;
+     }
+-    ptw->out_secure = is_secure;
+-    ptw->out_phys = addr;
+-    ptw->out_be = regime_translation_big_endian(env, ptw->in_mmu_idx);
++    /* Check if page table walk is to secure or non-secure PA space. */
++    ptw->out_secure = (is_secure
++                       && !(pte_secure
++                            ? env->cp15.vstcr_el2 & VSTCR_SW
++                            : env->cp15.vtcr_el2 & VTCR_NSW));
++    ptw->out_be = regime_translation_big_endian(env, mmu_idx);
+     return true;
++
++ fail:
++    assert(fi->type != ARMFault_None);
++    fi->s2addr = addr;
++    fi->stage2 = true;
++    fi->s1ptw = true;
++    fi->s1ns = !is_secure;
++    return false;
+ }
+ /* All loads done in the course of a page table walk go through here. */
+@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+                             ARMMMUFaultInfo *fi)
+ {
+     CPUState *cs = env_cpu(env);
+-    MemTxAttrs attrs = {};
+-    MemTxResult result = MEMTX_OK;
+-    AddressSpace *as;
+     uint32_t data;
+     if (!S1_ptw_translate(env, ptw, addr, fi)) {
++        /* Failure. */
++        assert(fi->s1ptw);
+         return 0;
+     }
+-    addr = ptw->out_phys;
+-    attrs.secure = ptw->out_secure;
+-    as = arm_addressspace(cs, attrs);
+-    if (ptw->out_be) {
+-        data = address_space_ldl_be(as, addr, attrs, &result);
++
++    if (likely(ptw->out_host)) {
++        /* Page tables are in RAM, and we have the host address. */
++        if (ptw->out_be) {
++            data = ldl_be_p(ptw->out_host);
++        } else {
++            data = ldl_le_p(ptw->out_host);
++        }
+     } else {
+-        data = address_space_ldl_le(as, addr, attrs, &result);
++        /* Page tables are in MMIO. */
++        MemTxAttrs attrs = { .secure = ptw->out_secure };
++        AddressSpace *as = arm_addressspace(cs, attrs);
++        MemTxResult result = MEMTX_OK;
++
++        if (ptw->out_be) {
++            data = address_space_ldl_be(as, ptw->out_phys, attrs, &result);
++        } else {
++            data = address_space_ldl_le(as, ptw->out_phys, attrs, &result);
++        }
++        if (unlikely(result != MEMTX_OK)) {
++            fi->type = ARMFault_SyncExternalOnWalk;
++            fi->ea = arm_extabort_type(result);
++            return 0;
++        }
+     }
+-    if (result == MEMTX_OK) {
+-        return data;
+-    }
+-    fi->type = ARMFault_SyncExternalOnWalk;
+-    fi->ea = arm_extabort_type(result);
+-    return 0;
++    return data;
+ }
+ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+                             ARMMMUFaultInfo *fi)
+ {
+     CPUState *cs = env_cpu(env);
+-    MemTxAttrs attrs = {};
+-    MemTxResult result = MEMTX_OK;
+-    AddressSpace *as;
+     uint64_t data;
+     if (!S1_ptw_translate(env, ptw, addr, fi)) {
++        /* Failure. */
++        assert(fi->s1ptw);
+         return 0;
+     }
+-    addr = ptw->out_phys;
+-    attrs.secure = ptw->out_secure;
+-    as = arm_addressspace(cs, attrs);
+-    if (ptw->out_be) {
+-        data = address_space_ldq_be(as, addr, attrs, &result);
++
++    if (likely(ptw->out_host)) {
++        /* Page tables are in RAM, and we have the host address. */
++        if (ptw->out_be) {
++            data = ldq_be_p(ptw->out_host);
++        } else {
++            data = ldq_le_p(ptw->out_host);
++        }
+     } else {
+-        data = address_space_ldq_le(as, addr, attrs, &result);
++        /* Page tables are in MMIO. */
++        MemTxAttrs attrs = { .secure = ptw->out_secure };
++        AddressSpace *as = arm_addressspace(cs, attrs);
++        MemTxResult result = MEMTX_OK;
++
++        if (ptw->out_be) {
++            data = address_space_ldq_be(as, ptw->out_phys, attrs, &result);
++        } else {
++            data = address_space_ldq_le(as, ptw->out_phys, attrs, &result);
++        }
++        if (unlikely(result != MEMTX_OK)) {
++            fi->type = ARMFault_SyncExternalOnWalk;
++            fi->ea = arm_extabort_type(result);
++            return 0;
++        }
+     }
+-    if (result == MEMTX_OK) {
+-        return data;
+-    }
+-    fi->type = ARMFault_SyncExternalOnWalk;
+-    fi->ea = arm_extabort_type(result);
+-    return 0;
++    return data;
+ }
+ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
+diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tlb_helper.c
++++ b/target/arm/tlb_helper.c
+@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                       bool probe, uintptr_t retaddr)
+ {
+     ARMCPU *cpu = ARM_CPU(cs);
+-    ARMMMUFaultInfo fi = {};
+     GetPhysAddrResult res = {};
++    ARMMMUFaultInfo local_fi, *fi;
+     int ret;
++    /*
++     * Allow S1_ptw_translate to see any fault generated here.
++     * Since this may recurse, read and clear.
++     */
++    fi = cpu->env.tlb_fi;
++    if (fi) {
++        cpu->env.tlb_fi = NULL;
++    } else {
++        fi = memset(&local_fi, 0, sizeof(local_fi));
++    }
++
+     /*
+      * Walk the page table and (if the mapping exists) add the page
+      * to the TLB.  On success, return true.  Otherwise, if probing,
+@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+      */
+     ret = get_phys_addr(&cpu->env, address, access_type,
+                         core_to_arm_mmu_idx(&cpu->env, mmu_idx),
+-                        &res, &fi);
++                        &res, fi);
+     if (likely(!ret)) {
+         /*
+          * Map a single [sub]page. Regions smaller than our declared
+@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+     } else {
+         /* now we have a real cpu fault */
+         cpu_restore_state(cs, retaddr, true);
+-        arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
++        arm_deliver_fault(cpu, address, access_type, mmu_idx, fi);
+     }
+ }
+ #else
+--
+.25.1

-[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
+[PULL 13/24] target/arm: Split out get_phys_addr_twostage
-The raspi3 has AArch64 CPUs, which means that our smpboot
+From: Richard Henderson <richard.henderson@linaro.org>
 code for keeping the secondary CPUs in a pen needs to have
 a version for A64 as well as A32. Without this, the
 secondary CPUs go into an infinite loop of taking undefined
 instruction exceptions.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-12-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
+ target/arm/ptw.c | 191 +++++++++++++++++++++++++----------------------
-file changed, 40 insertions(+), 1 deletion(-)
+file changed, 100 insertions(+), 91 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/ptw.c
-+++ b/hw/arm/raspi.c
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
- #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
+                                GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
- #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
+     __attribute__((nonnull));
- #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
-+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
++static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
++                                      target_ulong address,
- /* Table of Linux board IDs for different Pi versions */
++                                      MMUAccessType access_type,
- static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
++                                      GetPhysAddrResult *result,
-@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
++                                      ARMMMUFaultInfo *fi)
-                        info->smp_loader_start);
++    __attribute__((nonnull));
 +
  /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
  static const uint8_t pamax_map[] = {
      [0] = 32,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
      return 0;
  }
-+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
++static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
 +                                   target_ulong address,
 +                                   MMUAccessType access_type,
 +                                   GetPhysAddrResult *result,
 +                                   ARMMMUFaultInfo *fi)
 +{
-+    /* Unlike the AArch32 version we don't need to call the board setup hook.
++    hwaddr ipa;
-+     * The mechanism for doing the spin-table is also entirely different.
++    int s1_prot;
-+     * We must have four 64-bit fields at absolute addresses
++    int ret;
-+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
++    bool is_secure = ptw->in_secure;
-+     * our CPUs, and which we must ensure are zero initialized before
++    bool ipa_secure, s2walk_secure;
-+     * the primary CPU goes into the kernel. We put these variables inside
++    ARMCacheAttrs cacheattrs1;
-+     * a rom blob, so that the reset for ROM contents zeroes them for us.
++    bool is_el0;
 +    uint64_t hcr;
 +
 +    ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi);
 +
 +    /* If S1 fails or S2 is disabled, return early.  */
 +    if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) {
 +        return ret;
 +    }
 +
 +    ipa = result->f.phys_addr;
 +    ipa_secure = result->f.attrs.secure;
 +    if (is_secure) {
 +        /* Select TCR based on the NS bit from the S1 walk. */
 +        s2walk_secure = !(ipa_secure
 +                          ? env->cp15.vstcr_el2 & VSTCR_SW
 +                          : env->cp15.vtcr_el2 & VTCR_NSW);
 +    } else {
 +        assert(!ipa_secure);
 +        s2walk_secure = false;
 +    }
 +
 +    is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
 +    ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
 +    ptw->in_secure = s2walk_secure;
 +
 +    /*
 +     * S1 is done, now do S2 translation.
 +     * Save the stage1 results so that we may merge prot and cacheattrs later.
 +     */
-+    static const uint32_t smpboot[] = {
++    s1_prot = result->f.prot;
-+        0xd2801b05, /*        mov     x5, 0xd8 */
++    cacheattrs1 = result->cacheattrs;
-+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
++    memset(result, 0, sizeof(*result));
-+        0x924004c6, /*        and     x6, x6, #0x3 */
++
-+        0xd503205f, /* spin:  wfe */
++    ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
-+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
++    fi->s2addr = ipa;
-+        0xb4ffffc4, /*        cbz     x4, spin */
++
-+        0xd2800000, /*        mov     x0, #0x0 */
++    /* Combine the S1 and S2 perms.  */
-+        0xd2800001, /*        mov     x1, #0x0 */
++    result->f.prot &= s1_prot;
-+        0xd2800002, /*        mov     x2, #0x0 */
++
-+        0xd2800003, /*        mov     x3, #0x0 */
++    /* If S2 fails, return early.  */
-+        0xd61f0080, /*        br      x4 */
++    if (ret) {
-+    };
++        return ret;
-+
++    }
-+    static const uint64_t spintables[] = {
++
-+        0, 0, 0, 0
++    /* Combine the S1 and S2 cache attributes. */
-+    };
++    hcr = arm_hcr_el2_eff_secstate(env, is_secure);
-+
++    if (hcr & HCR_DC) {
-+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
++        /*
-+                       info->smp_loader_start);
++         * HCR.DC forces the first stage attributes to
-+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
++         *  Normal Non-Shareable,
-+                       SPINTABLE_ADDR);
++         *  Inner Write-Back Read-Allocate Write-Allocate,
 +         *  Outer Write-Back Read-Allocate Write-Allocate.
 +         * Do not overwrite Tagged within attrs.
 +         */
 +        if (cacheattrs1.attrs != 0xf0) {
 +            cacheattrs1.attrs = 0xff;
 +        }
 +        cacheattrs1.shareability = 0;
 +    }
 +    result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
 +                                            result->cacheattrs);
 +
 +    /*
 +     * Check if IPA translates to secure or non-secure PA space.
 +     * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
 +     */
 +    result->f.attrs.secure =
 +        (is_secure
 +         && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
 +         && (ipa_secure
 +             || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
 +
 +    return 0;
 +}
 +
- static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
+ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
- {
+                                       target_ulong address,
-     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
+                                       MMUAccessType access_type,
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
-     /* Pi2 and Pi3 requires SMP setup */
+     if (mmu_idx != s1_mmu_idx) {
-     if (version >= 2) {
+         /*
-         binfo.smp_loader_start = SMPBOOT_ADDR;
+          * Call ourselves recursively to do the stage 1 and then stage 2
--        binfo.write_secondary_boot = write_smpboot;
+-         * translations if mmu_idx is a two-stage regime.
-+        if (version == 2) {
++         * translations if mmu_idx is a two-stage regime, and EL2 present.
-+            binfo.write_secondary_boot = write_smpboot;
++         * Otherwise, a stage1+stage2 translation is just stage 1.
-+        } else {
+          */
-+            binfo.write_secondary_boot = write_smpboot64;
++        ptw->in_mmu_idx = mmu_idx = s1_mmu_idx;
-+        }
+         if (arm_feature(env, ARM_FEATURE_EL2)) {
-         binfo.secondary_cpu_reset_hook = reset_secondary;
+-            hwaddr ipa;
 -            int s1_prot;
 -            int ret;
 -            bool ipa_secure, s2walk_secure;
 -            ARMCacheAttrs cacheattrs1;
 -            bool is_el0;
 -            uint64_t hcr;
 -
 -            ptw->in_mmu_idx = s1_mmu_idx;
 -            ret = get_phys_addr_with_struct(env, ptw, address, access_type,
 -                                            result, fi);
 -
 -            /* If S1 fails or S2 is disabled, return early.  */
 -            if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
 -                                                   is_secure)) {
 -                return ret;
 -            }
 -
 -            ipa = result->f.phys_addr;
 -            ipa_secure = result->f.attrs.secure;
 -            if (is_secure) {
 -                /* Select TCR based on the NS bit from the S1 walk. */
 -                s2walk_secure = !(ipa_secure
 -                                  ? env->cp15.vstcr_el2 & VSTCR_SW
 -                                  : env->cp15.vtcr_el2 & VTCR_NSW);
 -            } else {
 -                assert(!ipa_secure);
 -                s2walk_secure = false;
 -            }
 -
 -            ptw->in_mmu_idx =
 -                s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
 -            ptw->in_secure = s2walk_secure;
 -            is_el0 = mmu_idx == ARMMMUIdx_E10_0;
 -
 -            /*
 -             * S1 is done, now do S2 translation.
 -             * Save the stage1 results so that we may merge
 -             * prot and cacheattrs later.
 -             */
 -            s1_prot = result->f.prot;
 -            cacheattrs1 = result->cacheattrs;
 -            memset(result, 0, sizeof(*result));
 -
 -            ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
 -                                     is_el0, result, fi);
 -            fi->s2addr = ipa;
 -
 -            /* Combine the S1 and S2 perms.  */
 -            result->f.prot &= s1_prot;
 -
 -            /* If S2 fails, return early.  */
 -            if (ret) {
 -                return ret;
 -            }
 -
 -            /* Combine the S1 and S2 cache attributes. */
 -            hcr = arm_hcr_el2_eff_secstate(env, is_secure);
 -            if (hcr & HCR_DC) {
 -                /*
 -                 * HCR.DC forces the first stage attributes to
 -                 *  Normal Non-Shareable,
 -                 *  Inner Write-Back Read-Allocate Write-Allocate,
 -                 *  Outer Write-Back Read-Allocate Write-Allocate.
 -                 * Do not overwrite Tagged within attrs.
 -                 */
 -                if (cacheattrs1.attrs != 0xf0) {
 -                    cacheattrs1.attrs = 0xff;
 -                }
 -                cacheattrs1.shareability = 0;
 -            }
 -            result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
 -                                                    result->cacheattrs);
 -
 -            /*
 -             * Check if IPA translates to secure or non-secure PA space.
 -             * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
 -             */
 -            result->f.attrs.secure =
 -                (is_secure
 -                 && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
 -                 && (ipa_secure
 -                     || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
 -
 -            return 0;
 -        } else {
 -            /*
 -             * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
 -             */
 -            mmu_idx = stage_1_mmu_idx(mmu_idx);
 +            return get_phys_addr_twostage(env, ptw, address, access_type,
 +                                          result, fi);
          }
      }
 --
-.16.2
+.25.1

-New patch
+[PULL 14/24] target/arm: Use bool consistently for get_phys_addr subroutines
+From: Richard Henderson <richard.henderson@linaro.org>
+The return type of the functions is already bool, but in a few
+instances we used an integer type with the return statement.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221011031911.2408754-13-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/ptw.c | 7 +++----
+file changed, 3 insertions(+), 4 deletions(-)
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/ptw.c
++++ b/target/arm/ptw.c
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
+     result->f.lg_page_size = TARGET_PAGE_BITS;
+     result->cacheattrs.shareability = shareability;
+     result->cacheattrs.attrs = memattr;
+-    return 0;
++    return false;
+ }
+ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
+ {
+     hwaddr ipa;
+     int s1_prot;
+-    int ret;
+     bool is_secure = ptw->in_secure;
+-    bool ipa_secure, s2walk_secure;
++    bool ret, ipa_secure, s2walk_secure;
+     ARMCacheAttrs cacheattrs1;
+     bool is_el0;
+     uint64_t hcr;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
+          && (ipa_secure
+              || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
+-    return 0;
++    return false;
+ }
+ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
+--
+.25.1

-[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
+[PULL 15/24] target/arm: Introduce curr_insn_len
-The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
+From: Richard Henderson <richard.henderson@linaro.org>
 CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
 is required for Linux to boot.
+A simple helper to retrieve the length of the current insn.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221020030641.2066807-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 11 +++++++----
+ target/arm/translate.h     | 5 +++++
-file changed, 7 insertions(+), 4 deletions(-)
+ target/arm/translate-vfp.c | 2 +-
  target/arm/translate.c     | 5 ++---
 files changed, 8 insertions(+), 4 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/translate.h
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+     s->insn_start = NULL;
- struct BCM283XInfo {
+ }
-     const char *name;
-+    int clusterid;
++static inline int curr_insn_len(DisasContext *s)
- };
++{
++    return s->base.pc_next - s->pc_curr;
- static const BCM283XInfo bcm283x_socs[] = {
++}
-     {
++
-         .name = TYPE_BCM2836,
+ /* is_jmp field values */
-+        .clusterid = 0xf,
+ #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
-     },
+ /* CPU state was modified dynamically; exit to main loop for interrupts. */
-     {
+diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
-         .name = TYPE_BCM2837,
+index XXXXXXX..XXXXXXX 100644
-+        .clusterid = 0x0,
+--- a/target/arm/translate-vfp.c
-     },
++++ b/target/arm/translate-vfp.c
- };
+@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
+     if (s->sme_trap_nonstreaming) {
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
+         gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- static void bcm2836_realize(DeviceState *dev, Error **errp)
+                            syn_smetrap(SME_ET_Streaming,
- {
+-                                       s->base.pc_next - s->pc_curr == 2));
-     BCM283XState *s = BCM283X(dev);
++                                       curr_insn_len(s) == 2));
-+    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
+         return false;
-+    const BCM283XInfo *info = bc->info;
+     }
-     Object *obj;
-     Error *err = NULL;
+diff --git a/target/arm/translate.c b/target/arm/translate.c
-     int n;
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+--- a/target/arm/translate.c
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
-     for (n = 0; n < BCM283X_NCPUS; n++) {
+     /* ISS not valid if writeback */
--        /* Mirror bcm2836, which has clusterid set to 0xf
+     if (p && !w) {
--         * TODO: this should be converted to a property of ARM_CPU
+         ret = rd;
--         */
+-        if (s->base.pc_next - s->pc_curr == 2) {
--        s->cpus[n].mp_affinity = 0xF00 | n;
++        if (curr_insn_len(s) == 2) {
-+        /* TODO: this should be converted to a property of ARM_CPU */
+             ret |= ISSIs16Bit;
-+        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
+         }
+     } else {
-         /* set periphbase/CBAR value for CPU-local registers */
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
-         object_property_set_int(OBJECT(&s->cpus[n]),
+             /* nothing more to generate */
              break;
          case DISAS_WFI:
 -            gen_helper_wfi(cpu_env,
 -                           tcg_constant_i32(dc->base.pc_next - dc->pc_curr));
 +            gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc)));
              /*
               * The helper doesn't necessarily throw an exception, but we
               * must go back to the main loop to check for interrupts anyway.
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+[PULL 16/24] target/arm: Change gen_goto_tb to work on displacements
-If we're directly booting a Linux kernel and the CPU supports both
+From: Richard Henderson <richard.henderson@linaro.org>
 EL3 and EL2, we start the kernel in EL2, as it expects. We must also
 set the SCR_EL3.HCE bit in this situation, so that the HVC
 instruction is enabled rather than UNDEFing. Otherwise at least some
 kernels will panic when trying to initialize KVM in the guest.
+In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221020030641.2066807-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 5 +++++
+ target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------
-file changed, 5 insertions(+)
+ target/arm/translate.c     | 10 ++++++----
 files changed, 27 insertions(+), 23 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/arm/boot.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
-                     assert(!info->secure_board_setup);
+     return translator_use_goto_tb(&s->base, dest);
-                 }
+ }
-+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+-static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
-+                    /* If we have EL2 then Linux expects the HVC insn to work */
++static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
-+                    env->cp15.scr_el3 |= SCR_HCE;
+ {
-+                }
++    uint64_t dest = s->pc_curr + diff;
 +
-                 /* Set to non-secure if not a secure boot */
+     if (use_goto_tb(s, dest)) {
-                 if (!info->secure_boot &&
+         tcg_gen_goto_tb(n);
-                     (cs != first_cpu || !info->secure_board_setup)) {
+         gen_a64_set_pc_im(dest);
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
   */
  static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
  {
 -    uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
 +    int64_t diff = sextract32(insn, 0, 26) * 4;
      if (insn & (1U << 31)) {
          /* BL Branch with link */
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
      /* B Branch / BL Branch with link */
      reset_btype(s);
 -    gen_goto_tb(s, 0, addr);
 +    gen_goto_tb(s, 0, diff);
  }
  /* Compare and branch (immediate)
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
  static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
  {
      unsigned int sf, op, rt;
 -    uint64_t addr;
 +    int64_t diff;
      TCGLabel *label_match;
      TCGv_i64 tcg_cmp;
      sf = extract32(insn, 31, 1);
      op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
      rt = extract32(insn, 0, 5);
 -    addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
 +    diff = sextract32(insn, 5, 19) * 4;
      tcg_cmp = read_cpu_reg(s, rt, sf);
      label_match = gen_new_label();
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
      tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
                          tcg_cmp, 0, label_match);
 -    gen_goto_tb(s, 0, s->base.pc_next);
 +    gen_goto_tb(s, 0, 4);
      gen_set_label(label_match);
 -    gen_goto_tb(s, 1, addr);
 +    gen_goto_tb(s, 1, diff);
  }
  /* Test and branch (immediate)
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
  static void disas_test_b_imm(DisasContext *s, uint32_t insn)
  {
      unsigned int bit_pos, op, rt;
 -    uint64_t addr;
 +    int64_t diff;
      TCGLabel *label_match;
      TCGv_i64 tcg_cmp;
      bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
      op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
 -    addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
 +    diff = sextract32(insn, 5, 14) * 4;
      rt = extract32(insn, 0, 5);
      tcg_cmp = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
      tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
                          tcg_cmp, 0, label_match);
      tcg_temp_free_i64(tcg_cmp);
 -    gen_goto_tb(s, 0, s->base.pc_next);
 +    gen_goto_tb(s, 0, 4);
      gen_set_label(label_match);
 -    gen_goto_tb(s, 1, addr);
 +    gen_goto_tb(s, 1, diff);
  }
  /* Conditional branch (immediate)
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
  static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
  {
      unsigned int cond;
 -    uint64_t addr;
 +    int64_t diff;
      if ((insn & (1 << 4)) || (insn & (1 << 24))) {
          unallocated_encoding(s);
          return;
      }
 -    addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
 +    diff = sextract32(insn, 5, 19) * 4;
      cond = extract32(insn, 0, 4);
      reset_btype(s);
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
          /* genuinely conditional branches */
          TCGLabel *label_match = gen_new_label();
          arm_gen_test_cc(cond, label_match);
 -        gen_goto_tb(s, 0, s->base.pc_next);
 +        gen_goto_tb(s, 0, 4);
          gen_set_label(label_match);
 -        gen_goto_tb(s, 1, addr);
 +        gen_goto_tb(s, 1, diff);
      } else {
          /* 0xe and 0xf are both "always" conditions */
 -        gen_goto_tb(s, 0, addr);
 +        gen_goto_tb(s, 0, diff);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
           * any pending interrupts immediately.
           */
          reset_btype(s);
 -        gen_goto_tb(s, 0, s->base.pc_next);
 +        gen_goto_tb(s, 0, 4);
          return;
      case 7: /* SB */
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
           * MB and end the TB instead.
           */
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
 -        gen_goto_tb(s, 0, s->base.pc_next);
 +        gen_goto_tb(s, 0, 4);
          return;
      default:
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          switch (dc->base.is_jmp) {
          case DISAS_NEXT:
          case DISAS_TOO_MANY:
 -            gen_goto_tb(dc, 1, dc->base.pc_next);
 +            gen_goto_tb(dc, 1, 4);
              break;
          default:
          case DISAS_UPDATE_EXIT:
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_ptr(void)
   * cpu_loop_exec. Any live exit_requests will be processed as we
   * enter the next TB.
   */
 -static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
 +static void gen_goto_tb(DisasContext *s, int n, int diff)
  {
 +    target_ulong dest = s->pc_curr + diff;
 +
      if (translator_use_goto_tb(&s->base, dest)) {
          tcg_gen_goto_tb(n);
          gen_set_pc_im(s, dest);
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
           *    gen_jmp();
           * on the second call to gen_jmp().
           */
 -        gen_goto_tb(s, tbno, dest);
 +        gen_goto_tb(s, tbno, dest - s->pc_curr);
          break;
      case DISAS_UPDATE_NOCHAIN:
      case DISAS_UPDATE_EXIT:
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          switch (dc->base.is_jmp) {
          case DISAS_NEXT:
          case DISAS_TOO_MANY:
 -            gen_goto_tb(dc, 1, dc->base.pc_next);
 +            gen_goto_tb(dc, 1, curr_insn_len(dc));
              break;
          case DISAS_UPDATE_NOCHAIN:
              gen_set_pc_im(dc, dc->base.pc_next);
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
              gen_set_pc_im(dc, dc->base.pc_next);
              gen_singlestep_exception(dc);
          } else {
 -            gen_goto_tb(dc, 1, dc->base.pc_next);
 +            gen_goto_tb(dc, 1, curr_insn_len(dc));
          }
      }
  }
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+[PULL 17/24] target/arm: Change gen_*set_pc_im to gen_*update_pc
-For the rpi1 and 2 we want to boot the Linux kernel via some
+From: Richard Henderson <richard.henderson@linaro.org>
 custom setup code that makes sure that the SMC instruction
 acts as a no-op, because it's used for cache maintenance.
 The rpi3 boots AArch64 kernels, which don't need SMC for
 cache maintenance and always expect to be booted non-secure.
 Don't fill in the aarch32-specific parts of the binfo struct.
+In preparation for TARGET_TB_PCREL, reduce reliance on
+absolute values by passing in pc difference.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221020030641.2066807-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 17 +++++++++++++----
+ target/arm/translate-a32.h |  2 +-
-file changed, 13 insertions(+), 4 deletions(-)
+ target/arm/translate.h     |  6 ++--
  target/arm/translate-a64.c | 32 +++++++++---------
  target/arm/translate-vfp.c |  2 +-
  target/arm/translate.c     | 68 ++++++++++++++++++++------------------
 files changed, 56 insertions(+), 54 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/translate-a32.h
-+++ b/hw/arm/raspi.c
++++ b/target/arm/translate-a32.h
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
-     binfo.board_id = raspi_boardid[version];
+ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
-     binfo.ram_size = ram_size;
+ void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
-     binfo.nb_cpus = smp_cpus;
+ void gen_set_condexec(DisasContext *s);
--    binfo.board_setup_addr = BOARDSETUP_ADDR;
+-void gen_set_pc_im(DisasContext *s, target_ulong val);
--    binfo.write_board_setup = write_board_setup;
++void gen_update_pc(DisasContext *s, target_long diff);
--    binfo.secure_board_setup = true;
+ void gen_lookup_tb(DisasContext *s);
--    binfo.secure_boot = true;
+ long vfp_reg_offset(bool dp, unsigned reg);
  long neon_full_reg_offset(unsigned reg);
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int curr_insn_len(DisasContext *s)
   * For instructions which want an immediate exit to the main loop, as opposed
   * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
   * doesn't write the PC on exiting the translation loop so you need to ensure
 - * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
 + * something (gen_a64_update_pc or runtime helper) has done so before we reach
   * return from cpu_tb_exec.
   */
  #define DISAS_EXIT      DISAS_TARGET_9
@@ -XXX,XX +XXX,XX @@ static inline int curr_insn_len(DisasContext *s)
  #ifdef TARGET_AARCH64
  void a64_translate_init(void);
 -void gen_a64_set_pc_im(uint64_t val);
 +void gen_a64_update_pc(DisasContext *s, target_long diff);
  extern const TranslatorOps aarch64_translator_ops;
  #else
  static inline void a64_translate_init(void)
  {
  }
 -static inline void gen_a64_set_pc_im(uint64_t val)
 +static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
  {
  }
  #endif
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s)
      }
  }
 -void gen_a64_set_pc_im(uint64_t val)
 +void gen_a64_update_pc(DisasContext *s, target_long diff)
  {
 -    tcg_gen_movi_i64(cpu_pc, val);
 +    tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
  }
  /*
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
  static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
  {
 -    gen_a64_set_pc_im(pc);
 +    gen_a64_update_pc(s, pc - s->pc_curr);
      gen_exception_internal(excp);
      s->base.is_jmp = DISAS_NORETURN;
  }
  static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
  {
 -    gen_a64_set_pc_im(s->pc_curr);
 +    gen_a64_update_pc(s, 0);
      gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
      s->base.is_jmp = DISAS_NORETURN;
  }
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
      if (use_goto_tb(s, dest)) {
          tcg_gen_goto_tb(n);
 -        gen_a64_set_pc_im(dest);
 +        gen_a64_update_pc(s, diff);
          tcg_gen_exit_tb(s->base.tb, n);
          s->base.is_jmp = DISAS_NORETURN;
      } else {
 -        gen_a64_set_pc_im(dest);
 +        gen_a64_update_pc(s, diff);
          if (s->ss_active) {
              gen_step_complete_exception(s);
          } else {
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
          uint32_t syndrome;
          syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
 -        gen_a64_set_pc_im(s->pc_curr);
 +        gen_a64_update_pc(s, 0);
          gen_helper_access_check_cp_reg(cpu_env,
                                         tcg_constant_ptr(ri),
                                         tcg_constant_i32(syndrome),
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
           * The readfn or writefn might raise an exception;
           * synchronize the CPU state in case it does.
           */
 -        gen_a64_set_pc_im(s->pc_curr);
 +        gen_a64_update_pc(s, 0);
      }
      /* Handle special cases first */
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
              /* The pre HVC helper handles cases when HVC gets trapped
               * as an undefined insn by runtime configuration.
               */
 -            gen_a64_set_pc_im(s->pc_curr);
 +            gen_a64_update_pc(s, 0);
              gen_helper_pre_hvc(cpu_env);
              gen_ss_advance(s);
              gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
                  unallocated_encoding(s);
                  break;
              }
 -            gen_a64_set_pc_im(s->pc_curr);
 +            gen_a64_update_pc(s, 0);
              gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
              gen_ss_advance(s);
              gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
           */
          switch (dc->base.is_jmp) {
          default:
 -            gen_a64_set_pc_im(dc->base.pc_next);
 +            gen_a64_update_pc(dc, 4);
              /* fall through */
          case DISAS_EXIT:
          case DISAS_JUMP:
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
              break;
          default:
          case DISAS_UPDATE_EXIT:
 -            gen_a64_set_pc_im(dc->base.pc_next);
 +            gen_a64_update_pc(dc, 4);
              /* fall through */
          case DISAS_EXIT:
              tcg_gen_exit_tb(NULL, 0);
              break;
          case DISAS_UPDATE_NOCHAIN:
 -            gen_a64_set_pc_im(dc->base.pc_next);
 +            gen_a64_update_pc(dc, 4);
              /* fall through */
          case DISAS_JUMP:
              tcg_gen_lookup_and_goto_ptr();
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          case DISAS_SWI:
              break;
          case DISAS_WFE:
 -            gen_a64_set_pc_im(dc->base.pc_next);
 +            gen_a64_update_pc(dc, 4);
              gen_helper_wfe(cpu_env);
              break;
          case DISAS_YIELD:
 -            gen_a64_set_pc_im(dc->base.pc_next);
 +            gen_a64_update_pc(dc, 4);
              gen_helper_yield(cpu_env);
              break;
          case DISAS_WFI:
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
               * This is a special case because we don't want to just halt
               * the CPU if trying to debug across a WFI.
               */
 -            gen_a64_set_pc_im(dc->base.pc_next);
 +            gen_a64_update_pc(dc, 4);
              gen_helper_wfi(cpu_env, tcg_constant_i32(4));
              /*
               * The helper doesn't necessarily throw an exception, but we
 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c
 +++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
          case ARM_VFP_FPSID:
              if (s->current_el == 1) {
                  gen_set_condexec(s);
 -                gen_set_pc_im(s, s->pc_curr);
 +                gen_update_pc(s, 0);
                  gen_helper_check_hcr_el2_trap(cpu_env,
                                                tcg_constant_i32(a->rt),
                                                tcg_constant_i32(a->reg));
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_set_condexec(DisasContext *s)
      }
  }
 -void gen_set_pc_im(DisasContext *s, target_ulong val)
 +void gen_update_pc(DisasContext *s, target_long diff)
  {
 -    tcg_gen_movi_i32(cpu_R[15], val);
 +    tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff);
  }
  /* Set PC and Thumb state from var.  var is marked as dead.  */
@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)
      /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
       * we need to sync state before calling it, but:
 -     *  - we don't need to do gen_set_pc_im() because the bxns helper will
 +     *  - we don't need to do gen_update_pc() because the bxns helper will
       *    always set the PC itself
       *  - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
       *    unless it's outside an IT block or the last insn in an IT block,
@@ -XXX,XX +XXX,XX @@ static inline void gen_blxns(DisasContext *s, int rm)
       * We do however need to set the PC, because the blxns helper reads it.
       * The blxns helper may throw an exception.
       */
 -    gen_set_pc_im(s, s->base.pc_next);
 +    gen_update_pc(s, curr_insn_len(s));
      gen_helper_v7m_blxns(cpu_env, var);
      tcg_temp_free_i32(var);
      s->base.is_jmp = DISAS_EXIT;
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
       * as an undefined insn by runtime configuration (ie before
       * the insn really executes).
       */
 -    gen_set_pc_im(s, s->pc_curr);
 +    gen_update_pc(s, 0);
      gen_helper_pre_hvc(cpu_env);
      /* Otherwise we will treat this as a real exception which
       * happens after execution of the insn. (The distinction matters
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
       * for single stepping.)
       */
      s->svc_imm = imm16;
 -    gen_set_pc_im(s, s->base.pc_next);
 +    gen_update_pc(s, curr_insn_len(s));
      s->base.is_jmp = DISAS_HVC;
  }
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
      /* As with HVC, we may take an exception either before or after
       * the insn executes.
       */
 -    gen_set_pc_im(s, s->pc_curr);
 +    gen_update_pc(s, 0);
      gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
 -    gen_set_pc_im(s, s->base.pc_next);
 +    gen_update_pc(s, curr_insn_len(s));
      s->base.is_jmp = DISAS_SMC;
  }
  static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
  {
      gen_set_condexec(s);
 -    gen_set_pc_im(s, pc);
 +    gen_update_pc(s, pc - s->pc_curr);
      gen_exception_internal(excp);
      s->base.is_jmp = DISAS_NORETURN;
  }
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
                                      uint32_t syn, TCGv_i32 tcg_el)
  {
      if (s->aarch64) {
 -        gen_a64_set_pc_im(pc);
 +        gen_a64_update_pc(s, pc - s->pc_curr);
      } else {
          gen_set_condexec(s);
 -        gen_set_pc_im(s, pc);
 +        gen_update_pc(s, pc - s->pc_curr);
      }
      gen_exception_el_v(excp, syn, tcg_el);
      s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
  void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
  {
      if (s->aarch64) {
 -        gen_a64_set_pc_im(pc);
 +        gen_a64_update_pc(s, pc - s->pc_curr);
      } else {
          gen_set_condexec(s);
 -        gen_set_pc_im(s, pc);
 +        gen_update_pc(s, pc - s->pc_curr);
      }
      gen_exception(excp, syn);
      s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
  static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
  {
      gen_set_condexec(s);
 -    gen_set_pc_im(s, s->pc_curr);
 +    gen_update_pc(s, 0);
      gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
      s->base.is_jmp = DISAS_NORETURN;
  }
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
      if (translator_use_goto_tb(&s->base, dest)) {
          tcg_gen_goto_tb(n);
 -        gen_set_pc_im(s, dest);
 +        gen_update_pc(s, diff);
          tcg_gen_exit_tb(s->base.tb, n);
      } else {
 -        gen_set_pc_im(s, dest);
 +        gen_update_pc(s, diff);
          gen_goto_ptr();
      }
      s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
  /* Jump, specifying which TB number to use if we gen_goto_tb() */
  static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
  {
 +    int diff = dest - s->pc_curr;
 +
-+    if (version <= 2) {
+     if (unlikely(s->ss_active)) {
-+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         /* An indirect jump so that we still trigger the debug exception.  */
-+         * mode before booting a kernel (to set up the SMC vectors so
+-        gen_set_pc_im(s, dest);
-+         * that we get a no-op SMC; this is used by Linux to call the
++        gen_update_pc(s, diff);
-+         * firmware for some cache maintenance operations.
+         s->base.is_jmp = DISAS_JUMP;
-+         * The rpi3 doesn't need this.
+         return;
-+         */
+     }
-+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
-+        binfo.write_board_setup = write_board_setup;
+          *    gen_jmp();
-+        binfo.secure_board_setup = true;
+          * on the second call to gen_jmp().
-+        binfo.secure_boot = true;
+          */
-+    }
+-        gen_goto_tb(s, tbno, dest - s->pc_curr);
++        gen_goto_tb(s, tbno, diff);
-     /* Pi2 and Pi3 requires SMP setup */
+         break;
-     if (version >= 2) {
+     case DISAS_UPDATE_NOCHAIN:
      case DISAS_UPDATE_EXIT:
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
           * Avoid using goto_tb so we really do exit back to the main loop
           * and don't chain to another TB.
           */
 -        gen_set_pc_im(s, dest);
 +        gen_update_pc(s, diff);
          gen_goto_ptr();
          s->base.is_jmp = DISAS_NORETURN;
          break;
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
      /* Sync state because msr_banked() can raise exceptions */
      gen_set_condexec(s);
 -    gen_set_pc_im(s, s->pc_curr);
 +    gen_update_pc(s, 0);
      tcg_reg = load_reg(s, rn);
      gen_helper_msr_banked(cpu_env, tcg_reg,
                            tcg_constant_i32(tgtmode),
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
      /* Sync state because mrs_banked() can raise exceptions */
      gen_set_condexec(s);
 -    gen_set_pc_im(s, s->pc_curr);
 +    gen_update_pc(s, 0);
      tcg_reg = tcg_temp_new_i32();
      gen_helper_mrs_banked(tcg_reg, cpu_env,
                            tcg_constant_i32(tgtmode),
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
              }
              gen_set_condexec(s);
 -            gen_set_pc_im(s, s->pc_curr);
 +            gen_update_pc(s, 0);
              gen_helper_access_check_cp_reg(cpu_env,
                                             tcg_constant_ptr(ri),
                                             tcg_constant_i32(syndrome),
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
               * synchronize the CPU state in case it does.
               */
              gen_set_condexec(s);
 -            gen_set_pc_im(s, s->pc_curr);
 +            gen_update_pc(s, 0);
          }
          /* Handle special cases first */
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
                  unallocated_encoding(s);
                  return;
              }
 -            gen_set_pc_im(s, s->base.pc_next);
 +            gen_update_pc(s, curr_insn_len(s));
              s->base.is_jmp = DISAS_WFI;
              return;
          default:
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
      addr = tcg_temp_new_i32();
      /* get_r13_banked() will raise an exception if called from System mode */
      gen_set_condexec(s);
 -    gen_set_pc_im(s, s->pc_curr);
 +    gen_update_pc(s, 0);
      gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
      switch (amode) {
      case 0: /* DA */
@@ -XXX,XX +XXX,XX @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
       * scheduling of other vCPUs.
       */
      if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
 -        gen_set_pc_im(s, s->base.pc_next);
 +        gen_update_pc(s, curr_insn_len(s));
          s->base.is_jmp = DISAS_YIELD;
      }
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
       * implemented so we can't sleep like WFI does.
       */
      if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
 -        gen_set_pc_im(s, s->base.pc_next);
 +        gen_update_pc(s, curr_insn_len(s));
          s->base.is_jmp = DISAS_WFE;
      }
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
  static bool trans_WFI(DisasContext *s, arg_WFI *a)
  {
      /* For WFI, halt the vCPU until an IRQ. */
 -    gen_set_pc_im(s, s->base.pc_next);
 +    gen_update_pc(s, curr_insn_len(s));
      s->base.is_jmp = DISAS_WFI;
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
          (a->imm == semihost_imm)) {
          gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
      } else {
 -        gen_set_pc_im(s, s->base.pc_next);
 +        gen_update_pc(s, curr_insn_len(s));
          s->svc_imm = a->imm;
          s->base.is_jmp = DISAS_SWI;
      }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          case DISAS_TOO_MANY:
          case DISAS_UPDATE_EXIT:
          case DISAS_UPDATE_NOCHAIN:
 -            gen_set_pc_im(dc, dc->base.pc_next);
 +            gen_update_pc(dc, curr_insn_len(dc));
              /* fall through */
          default:
              /* FIXME: Single stepping a WFI insn will not halt the CPU. */
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
              gen_goto_tb(dc, 1, curr_insn_len(dc));
              break;
          case DISAS_UPDATE_NOCHAIN:
 -            gen_set_pc_im(dc, dc->base.pc_next);
 +            gen_update_pc(dc, curr_insn_len(dc));
              /* fall through */
          case DISAS_JUMP:
              gen_goto_ptr();
              break;
          case DISAS_UPDATE_EXIT:
 -            gen_set_pc_im(dc, dc->base.pc_next);
 +            gen_update_pc(dc, curr_insn_len(dc));
              /* fall through */
          default:
              /* indicate that the hash table must be used to find the next TB */
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          gen_set_label(dc->condlabel);
          gen_set_condexec(dc);
          if (unlikely(dc->ss_active)) {
 -            gen_set_pc_im(dc, dc->base.pc_next);
 +            gen_update_pc(dc, curr_insn_len(dc));
              gen_singlestep_exception(dc);
          } else {
              gen_goto_tb(dc, 1, curr_insn_len(dc));
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+[PULL 18/24] target/arm: Change gen_exception_insn* to work on displacements
-Add some assertions that if we're about to boot an AArch64 kernel,
+From: Richard Henderson <richard.henderson@linaro.org>
-the board code has not mistakenly set either secure_boot or
-secure_board_setup. It doesn't make sense to set secure_boot,
+In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
-because all AArch64 kernels must be booted in non-secure mode.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-It might in theory make sense to set secure_board_setup, but
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-we don't currently support that, because only the AArch32
+Message-id: 20221020030641.2066807-5-richard.henderson@linaro.org
 bootloader[] code calls this hook; bootloader_aarch64[] does not.
 Since we don't have a current need for this functionality, just
 assert that we don't try to use it. If it's needed we'll add
 it later.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 7 +++++++
+ target/arm/translate.h        |  5 +++--
-file changed, 7 insertions(+)
+ target/arm/translate-a64.c    | 28 ++++++++++-------------
+ target/arm/translate-m-nocp.c |  6 ++---
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+ target/arm/translate-mve.c    |  2 +-
-index XXXXXXX..XXXXXXX 100644
+ target/arm/translate-vfp.c    |  6 ++---
---- a/hw/arm/boot.c
+ target/arm/translate.c        | 42 +++++++++++++++++------------------
-+++ b/hw/arm/boot.c
+files changed, 43 insertions(+), 46 deletions(-)
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-                     } else {
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-                         env->pstate = PSTATE_MODE_EL1h;
+index XXXXXXX..XXXXXXX 100644
-                     }
+--- a/target/arm/translate.h
-+                    /* AArch64 kernels never boot in secure mode */
++++ b/target/arm/translate.h
-+                    assert(!info->secure_boot);
+@@ -XXX,XX +XXX,XX @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
-+                    /* This hook is only supported for AArch32 currently:
+ void arm_gen_test_cc(int cc, TCGLabel *label);
-+                     * bootloader_aarch64[] will not call the hook, and
+ MemOp pow2_align(unsigned i);
-+                     * the code above has already dropped us into EL2 or EL1.
+ void unallocated_encoding(DisasContext *s);
-+                     */
+-void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
-+                    assert(!info->secure_board_setup);
++void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
-                 }
+                            uint32_t syn, uint32_t target_el);
+-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn);
-                 /* Set to non-secure if not a secure boot */
++void gen_exception_insn(DisasContext *s, target_long pc_diff,
 +                        int excp, uint32_t syn);
  /* Return state of Alternate Half-precision flag, caller frees result */
  static inline TCGv_i32 get_ahp_flag(void)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check_only(DisasContext *s)
          assert(!s->fp_access_checked);
          s->fp_access_checked = true;
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn_el(s, 0, EXCP_UDEF,
                                syn_fp_access_trap(1, 0xe, false, 0),
                                s->fp_excp_el);
          return false;
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
          return false;
      }
      if (s->sme_trap_nonstreaming && s->is_nonstreaming) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn(s, 0, EXCP_UDEF,
                             syn_smetrap(SME_ET_Streaming, false));
          return false;
      }
@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
              goto fail_exit;
          }
      } else if (s->sve_excp_el) {
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn_el(s, 0, EXCP_UDEF,
                                syn_sve_access_trap(), s->sve_excp_el);
          goto fail_exit;
      }
@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
  static bool sme_access_check(DisasContext *s)
  {
      if (s->sme_excp_el) {
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn_el(s, 0, EXCP_UDEF,
                                syn_smetrap(SME_ET_AccessTrap, false),
                                s->sme_excp_el);
          return false;
@@ -XXX,XX +XXX,XX @@ bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
          return false;
      }
      if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn(s, 0, EXCP_UDEF,
                             syn_smetrap(SME_ET_NotStreaming, false));
          return false;
      }
      if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn(s, 0, EXCP_UDEF,
                             syn_smetrap(SME_ET_InactiveZA, false));
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
      } else {
          syndrome = syn_uncategorized();
      }
 -    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome);
 +    gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
  }
  /* MRS - move from system register
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
          switch (op2_ll) {
          case 1:                                                     /* SVC */
              gen_ss_advance(s);
 -            gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
 -                               syn_aa64_svc(imm16));
 +            gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
              break;
          case 2:                                                     /* HVC */
              if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
              gen_a64_update_pc(s, 0);
              gen_helper_pre_hvc(cpu_env);
              gen_ss_advance(s);
 -            gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
 -                                  syn_aa64_hvc(imm16), 2);
 +            gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2);
              break;
          case 3:                                                     /* SMC */
              if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
              gen_a64_update_pc(s, 0);
              gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
              gen_ss_advance(s);
 -            gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
 -                                  syn_aa64_smc(imm16), 3);
 +            gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3);
              break;
          default:
              unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
           * Illegal execution state. This has priority over BTI
           * exceptions, but comes after instruction abort exceptions.
           */
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
 +        gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate());
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
              if (s->btype != 0
                  && s->guarded_page
                  && !btype_destination_ok(insn, s->bt, s->btype)) {
 -                gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 -                                   syn_btitrap(s->btype));
 +                gen_exception_insn(s, 0, EXCP_UDEF, syn_btitrap(s->btype));
                  return;
              }
          } else {
 diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-m-nocp.c
 +++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
      tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
      if (s->fp_excp_el != 0) {
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
 +        gen_exception_insn_el(s, 0, EXCP_NOCP,
                                syn_uncategorized(), s->fp_excp_el);
          return true;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
      }
      if (a->cp != 10) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized());
 +        gen_exception_insn(s, 0, EXCP_NOCP, syn_uncategorized());
          return true;
      }
      if (s->fp_excp_el != 0) {
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
 +        gen_exception_insn_el(s, 0, EXCP_NOCP,
                                syn_uncategorized(), s->fp_excp_el);
          return true;
      }
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s)
          return true;
      default:
          /* Reserved value: INVSTATE UsageFault */
 -        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
 +        gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
          return false;
      }
  }
 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c
 +++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
          int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
          uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
 +        gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->fp_excp_el);
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
       * appear to be any insns which touch VFP which are allowed.
       */
      if (s->sme_trap_nonstreaming) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 +        gen_exception_insn(s, 0, EXCP_UDEF,
                             syn_smetrap(SME_ET_Streaming,
                                         curr_insn_len(s) == 2));
          return false;
@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
           * the encoding space handled by the patterns in m-nocp.decode,
           * and for them we may need to raise NOCP here.
           */
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
 +        gen_exception_insn_el(s, 0, EXCP_NOCP,
                                syn_uncategorized(), s->fp_excp_el);
          return false;
      }
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception(int excp, uint32_t syndrome)
                                         tcg_constant_i32(syndrome));
  }
 -static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
 -                                    uint32_t syn, TCGv_i32 tcg_el)
 +static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff,
 +                                    int excp, uint32_t syn, TCGv_i32 tcg_el)
  {
      if (s->aarch64) {
 -        gen_a64_update_pc(s, pc - s->pc_curr);
 +        gen_a64_update_pc(s, pc_diff);
      } else {
          gen_set_condexec(s);
 -        gen_update_pc(s, pc - s->pc_curr);
 +        gen_update_pc(s, pc_diff);
      }
      gen_exception_el_v(excp, syn, tcg_el);
      s->base.is_jmp = DISAS_NORETURN;
  }
 -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
 +void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
                             uint32_t syn, uint32_t target_el)
  {
 -    gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
 +    gen_exception_insn_el_v(s, pc_diff, excp, syn,
 +                            tcg_constant_i32(target_el));
  }
 -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
 +void gen_exception_insn(DisasContext *s, target_long pc_diff,
 +                        int excp, uint32_t syn)
  {
      if (s->aarch64) {
 -        gen_a64_update_pc(s, pc - s->pc_curr);
 +        gen_a64_update_pc(s, pc_diff);
      } else {
          gen_set_condexec(s);
 -        gen_update_pc(s, pc - s->pc_curr);
 +        gen_update_pc(s, pc_diff);
      }
      gen_exception(excp, syn);
      s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
  void unallocated_encoding(DisasContext *s)
  {
      /* Unallocated and reserved encodings are uncategorized */
 -    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
 +    gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized());
  }
  /* Force a TB lookup after an instruction that changes the CPU state.  */
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
                  tcg_el = tcg_constant_i32(3);
              }
 -            gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF,
 +            gen_exception_insn_el_v(s, 0, EXCP_UDEF,
                                      syn_uncategorized(), tcg_el);
              tcg_temp_free_i32(tcg_el);
              return false;
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
  undef:
      /* If we get here then some access check did not pass */
 -    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
 +    gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized());
      return false;
  }
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
       * For the UNPREDICTABLE cases we choose to UNDEF.
       */
      if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
 -        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
 -                              syn_uncategorized(), 3);
 +        gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3);
          return;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
           * Do the check-and-raise-exception by hand.
           */
          if (s->fp_excp_el) {
 -            gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
 +            gen_exception_insn_el(s, 0, EXCP_NOCP,
                                    syn_uncategorized(), s->fp_excp_el);
              return true;
          }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
          tmp = load_cpu_field(v7m.ltpsize);
          tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
          tcg_temp_free_i32(tmp);
 -        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
 +        gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
          gen_set_label(skipexc);
      }
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
       * UsageFault exception.
       */
      if (arm_dc_feature(s, ARM_FEATURE_M)) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
 +        gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
           * Illegal execution state. This has priority over BTI
           * exceptions, but comes after instruction abort exceptions.
           */
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
 +        gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate());
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
           * Illegal execution state. This has priority over BTI
           * exceptions, but comes after instruction abort exceptions.
           */
 -        gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate());
 +        gen_exception_insn(dc, 0, EXCP_UDEF, syn_illegalstate());
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
           */
          tcg_remove_ops_after(dc->insn_eci_rewind);
          dc->condjmp = 0;
 -        gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE,
 -                           syn_uncategorized());
 +        gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized());
      }
      arm_post_translate_insn(dc);
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
+[PULL 19/24] target/arm: Remove gen_exception_internal_insn pc argument
-From: Wei Huang <wei@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-For guest kernel that supports KASLR, the load address can change every
+In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
-time when guest VM runs. To find the physical base address correctly,
+Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.
 current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
 However this string pattern is only available on x86_64. AArch64 uses a
 different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
 QEMU dump uses the correct string on AArch64.
-Signed-off-by: Wei Huang <wei@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
+Message-id: 20221020030641.2066807-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- dump.c | 14 +++++++++++---
+ target/arm/translate-a64.c |  6 +++---
-file changed, 11 insertions(+), 3 deletions(-)
+ target/arm/translate.c     | 10 +++++-----
 files changed, 8 insertions(+), 8 deletions(-)
-diff --git a/dump.c b/dump.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/dump.c
+--- a/target/arm/translate-a64.c
-+++ b/dump.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
+     gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
-     lines = g_strsplit((char *)vmci, "\n", -1);
+ }
-     for (i = 0; lines[i]; i++) {
--        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
+-static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
--            if (qemu_strtou64(lines[i] + 18, NULL, 16,
++static void gen_exception_internal_insn(DisasContext *s, int excp)
-+        const char *prefix = NULL;
+ {
-+
+-    gen_a64_update_pc(s, pc - s->pc_curr);
-+        if (s->dump_info.d_machine == EM_X86_64) {
++    gen_a64_update_pc(s, 0);
-+            prefix = "NUMBER(phys_base)=";
+     gen_exception_internal(excp);
-+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+     s->base.is_jmp = DISAS_NORETURN;
-+            prefix = "NUMBER(PHYS_OFFSET)=";
+ }
-+        }
+@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
-+
+          * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
-+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+          */
-+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
+         if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) {
-                               &phys_base) < 0) {
+-            gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
--                warn_report("Failed to read NUMBER(phys_base)=");
++            gen_exception_internal_insn(s, EXCP_SEMIHOST);
-+                warn_report("Failed to read %s", prefix);
+         } else {
-             } else {
+             unallocated_encoding(s);
-                 s->dump_info.phys_base = phys_base;
+         }
-             }
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
      s->base.is_jmp = DISAS_SMC;
  }
 -static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
 +static void gen_exception_internal_insn(DisasContext *s, int excp)
  {
      gen_set_condexec(s);
 -    gen_update_pc(s, pc - s->pc_curr);
 +    gen_update_pc(s, 0);
      gen_exception_internal(excp);
      s->base.is_jmp = DISAS_NORETURN;
  }
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
       */
      if (semihosting_enabled(s->current_el != 0) &&
          (imm == (s->thumb ? 0x3c : 0xf000))) {
 -        gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
 +        gen_exception_internal_insn(s, EXCP_SEMIHOST);
          return;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
      if (arm_dc_feature(s, ARM_FEATURE_M) &&
          semihosting_enabled(s->current_el == 0) &&
          (a->imm == 0xab)) {
 -        gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
 +        gen_exception_internal_insn(s, EXCP_SEMIHOST);
      } else {
          gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
      if (!arm_dc_feature(s, ARM_FEATURE_M) &&
          semihosting_enabled(s->current_el == 0) &&
          (a->imm == semihost_imm)) {
 -        gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
 +        gen_exception_internal_insn(s, EXCP_SEMIHOST);
      } else {
          gen_update_pc(s, curr_insn_len(s));
          s->svc_imm = a->imm;
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
+[PULL 20/24] target/arm: Change gen_jmp* to work on displacements
-The bcm2837 is pretty similar to the bcm2836, but it does have
+From: Richard Henderson <richard.henderson@linaro.org>
 some differences. Notably, the MPIDR affinity aff1 values it
 sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
 uses, and if this is wrong Linux will not boot.
-Rather than trying to have one device with properties that
+In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
 configure it differently for the two cases, create two
 separate QOM devices for the two SoCs. We use the same approach
 as hw/arm/aspeed_soc.c and share code and have a data table
 that might differ per-SoC. For the moment the two types don't
 actually have different behaviour.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20221020030641.2066807-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
+ target/arm/translate.c | 37 +++++++++++++++++++++----------------
- hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
+file changed, 21 insertions(+), 16 deletions(-)
  hw/arm/raspi.c           |  3 ++-
 files changed, 53 insertions(+), 6 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/target/arm/translate.c
-+++ b/include/hw/arm/bcm2836.h
++++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint32_t read_pc(DisasContext *s)
+     return s->pc_curr + (s->thumb ? 4 : 8);
- #define BCM283X_NCPUS 4
+ }
-+/* These type names are for specific SoCs; other than instantiating
++/* The pc_curr difference for an architectural jump. */
-+ * them, code using these devices should always handle them via the
++static target_long jmp_diff(DisasContext *s, target_long diff)
-+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
++{
-+ */
++    return diff + (s->thumb ? 4 : 8);
-+#define TYPE_BCM2836 "bcm2836"
++}
 +#define TYPE_BCM2837 "bcm2837"
 +
- typedef struct BCM283XState {
+ /* Set a variable to the value of a CPU register.  */
-     /*< private >*/
+ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
      DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
      BCM2835PeripheralState peripherals;
  } BCM283XState;
 +typedef struct BCM283XInfo BCM283XInfo;
 +
 +typedef struct BCM283XClass {
 +    DeviceClass parent_class;
 +    const BCM283XInfo *info;
 +} BCM283XClass;
 +
 +#define BCM283X_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
 +#define BCM283X_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
 +
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2836.c
 +++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
  /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
  #define BCM2836_CONTROL_BASE    0x40000000
 +struct BCM283XInfo {
 +    const char *name;
 +};
 +
 +static const BCM283XInfo bcm283x_socs[] = {
 +    {
 +        .name = TYPE_BCM2836,
 +    },
 +    {
 +        .name = TYPE_BCM2837,
 +    },
 +};
 +
  static void bcm2836_init(Object *obj)
  {
-     BCM283XState *s = BCM283X(obj);
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_ptr(void)
-@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
+  * cpu_loop_exec. Any live exit_requests will be processed as we
-     DEFINE_PROP_END_OF_LIST()
+  * enter the next TB.
- };
+  */
+-static void gen_goto_tb(DisasContext *s, int n, int diff)
--static void bcm2836_class_init(ObjectClass *oc, void *data)
++static void gen_goto_tb(DisasContext *s, int n, target_long diff)
 +static void bcm283x_class_init(ObjectClass *oc, void *data)
  {
-     DeviceClass *dc = DEVICE_CLASS(oc);
+     target_ulong dest = s->pc_curr + diff;
-+    BCM283XClass *bc = BCM283X_CLASS(oc);
+@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
 -    dc->props = bcm2836_props;
 +    bc->info = data;
      dc->realize = bcm2836_realize;
 +    dc->props = bcm2836_props;
  }
--static const TypeInfo bcm2836_type_info = {
+ /* Jump, specifying which TB number to use if we gen_goto_tb() */
-+static const TypeInfo bcm283x_type_info = {
+-static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
-     .name = TYPE_BCM283X,
++static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno)
      .parent = TYPE_DEVICE,
      .instance_size = sizeof(BCM283XState),
      .instance_init = bcm2836_init,
 -    .class_init = bcm2836_class_init,
 +    .class_size = sizeof(BCM283XClass),
 +    .abstract = true,
  };
  static void bcm2836_register_types(void)
  {
--    type_register_static(&bcm2836_type_info);
+-    int diff = dest - s->pc_curr;
-+    int i;
+-
-+
+     if (unlikely(s->ss_active)) {
-+    type_register_static(&bcm283x_type_info);
+         /* An indirect jump so that we still trigger the debug exception.  */
-+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+         gen_update_pc(s, diff);
-+        TypeInfo ti = {
+@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
-+            .name = bcm283x_socs[i].name,
+     }
 +            .parent = TYPE_BCM283X,
 +            .class_init = bcm283x_class_init,
 +            .class_data = (void *) &bcm283x_socs[i],
 +        };
 +        type_register(&ti);
 +    }
  }
- type_init(bcm2836_register_types)
+-static inline void gen_jmp(DisasContext *s, uint32_t dest)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
++static inline void gen_jmp(DisasContext *s, target_long diff)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/hw/arm/raspi.c
+-    gen_jmp_tb(s, dest, 0);
-+++ b/hw/arm/raspi.c
++    gen_jmp_tb(s, diff, 0);
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+ }
-     BusState *bus;
-     DeviceState *carddev;
+ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
+@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
--    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
-+    object_initialize(&s->soc, sizeof(s->soc),
+ static bool trans_B(DisasContext *s, arg_i *a)
-+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
+ {
-     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
+-    gen_jmp(s, read_pc(s) + a->imm);
-                               &error_abort);
++    gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
          return true;
      }
      arm_skip_unless(s, a->cond);
 -    gen_jmp(s, read_pc(s) + a->imm);
 +    gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
  static bool trans_BL(DisasContext *s, arg_i *a)
  {
      tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
 -    gen_jmp(s, read_pc(s) + a->imm);
 +    gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
      }
      tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
      store_cpu_field_constant(!s->thumb, thumb);
 -    gen_jmp(s, (read_pc(s) & ~3) + a->imm);
 +    /* This jump is computed from an aligned PC: subtract off the low bits. */
 +    gen_jmp(s, jmp_diff(s, a->imm - (s->pc_curr & 3)));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
           * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
           */
      }
 -    gen_jmp_tb(s, s->base.pc_next, 1);
 +    gen_jmp_tb(s, curr_insn_len(s), 1);
      gen_set_label(nextlabel);
 -    gen_jmp(s, read_pc(s) + a->imm);
 +    gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
      if (a->f) {
          /* Loop-forever: just jump back to the loop start */
 -        gen_jmp(s, read_pc(s) - a->imm);
 +        gen_jmp(s, jmp_diff(s, -a->imm));
          return true;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
          tcg_temp_free_i32(decr);
      }
      /* Jump back to the loop start */
 -    gen_jmp(s, read_pc(s) - a->imm);
 +    gen_jmp(s, jmp_diff(s, -a->imm));
      gen_set_label(loopend);
      if (a->tp) {
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
          store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
      }
      /* End TB, continuing to following insn */
 -    gen_jmp_tb(s, s->base.pc_next, 1);
 +    gen_jmp_tb(s, curr_insn_len(s), 1);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
      tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
                          tmp, 0, s->condlabel);
      tcg_temp_free_i32(tmp);
 -    gen_jmp(s, read_pc(s) + a->imm);
 +    gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
+[PULL 21/24] target/arm: Introduce gen_pc_plus_diff for aarch64
-Now we have separate types for BCM2386 and BCM2387, we might as well
+From: Richard Henderson <richard.henderson@linaro.org>
 just hard-code the CPU type they use rather than having it passed
 through as an object property. This then lets us put the initialization
 of the CPU object in init rather than realize.
-Note that this change means that it's no longer possible on
+In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
 the command line to use -cpu to ask for a different kind of
 CPU than the SoC supports. This was never a supported thing to
 do anyway; we were just not sanity-checking the command line.
-This does require us to only build the bcm2837 object on
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-TARGET_AARCH64 configs, since otherwise it won't instantiate
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-due to the missing cortex-a53 device and "make check" will fail.
+Message-id: 20221020030641.2066807-8-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++-----------
 file changed, 29 insertions(+), 12 deletions(-)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
 ---
  hw/arm/bcm2836.c | 24 +++++++++++++++---------
  hw/arm/raspi.c   |  2 --
 files changed, 15 insertions(+), 11 deletions(-)
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s)
+     }
- struct BCM283XInfo {
+ }
-     const char *name;
-+    const char *cpu_type;
++static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
-     int clusterid;
++{
- };
++    tcg_gen_movi_i64(dest, s->pc_curr + diff);
++}
- static const BCM283XInfo bcm283x_socs[] = {
++
-     {
+ void gen_a64_update_pc(DisasContext *s, target_long diff)
          .name = TYPE_BCM2836,
 +        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
          .clusterid = 0xf,
      },
 +#ifdef TARGET_AARCH64
      {
          .name = TYPE_BCM2837,
 +        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
          .clusterid = 0x0,
      },
 +#endif
  };
  static void bcm2836_init(Object *obj)
  {
-     BCM283XState *s = BCM283X(obj);
+-    tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
-+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
++    gen_pc_plus_diff(s, cpu_pc, diff);
 +    const BCM283XInfo *info = bc->info;
 +    int n;
 +
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
 +        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 +                          info->cpu_type);
 +        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 +                                  &error_abort);
 +    }
      object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
      object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      /* common peripherals from bcm2835 */
 -    obj = OBJECT(dev);
 -    for (n = 0; n < BCM283X_NCPUS; n++) {
 -        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 -                          s->cpu_type);
 -        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 -                                  &error_abort);
 -    }
 -
      obj = object_property_get_link(OBJECT(dev), "ram", &err);
      if (obj == NULL) {
          error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
  }
- static Property bcm2836_props[] = {
+ /*
--    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
-     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
-                        BCM283X_NCPUS),
+     if (insn & (1U << 31)) {
-     DEFINE_PROP_END_OF_LIST()
+         /* BL Branch with link */
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+-        tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
-index XXXXXXX..XXXXXXX 100644
++        gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
---- a/hw/arm/raspi.c
+     }
-+++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+     /* B Branch / BL Branch with link */
-     /* Setup the SOC */
+@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
-     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
+         default:
-                                    &error_abort);
+             goto do_unallocated;
--    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+         }
--                            &error_abort);
+-        gen_a64_set_pc(s, dst);
-     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
+         /* BLR also needs to load return address */
-                             &error_abort);
+         if (opc == 1) {
-     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
+-            tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
 +            TCGv_i64 lr = cpu_reg(s, 30);
 +            if (dst == lr) {
 +                TCGv_i64 tmp = new_tmp_a64(s);
 +                tcg_gen_mov_i64(tmp, dst);
 +                dst = tmp;
 +            }
 +            gen_pc_plus_diff(s, lr, curr_insn_len(s));
          }
 +        gen_a64_set_pc(s, dst);
          break;
      case 8: /* BRAA */
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
          } else {
              dst = cpu_reg(s, rn);
          }
 -        gen_a64_set_pc(s, dst);
          /* BLRAA also needs to load return address */
          if (opc == 9) {
 -            tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
 +            TCGv_i64 lr = cpu_reg(s, 30);
 +            if (dst == lr) {
 +                TCGv_i64 tmp = new_tmp_a64(s);
 +                tcg_gen_mov_i64(tmp, dst);
 +                dst = tmp;
 +            }
 +            gen_pc_plus_diff(s, lr, curr_insn_len(s));
          }
 +        gen_a64_set_pc(s, dst);
          break;
      case 4: /* ERET */
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
      tcg_rt = cpu_reg(s, rt);
 -    clean_addr = tcg_constant_i64(s->pc_curr + imm);
 +    clean_addr = new_tmp_a64(s);
 +    gen_pc_plus_diff(s, clean_addr, imm);
      if (is_vector) {
          do_fp_ld(s, rt, clean_addr, size);
      } else {
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
  static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
  {
      unsigned int page, rd;
 -    uint64_t base;
 -    uint64_t offset;
 +    int64_t offset;
      page = extract32(insn, 31, 1);
      /* SignExtend(immhi:immlo) -> offset */
      offset = sextract64(insn, 5, 19);
      offset = offset << 2 | extract32(insn, 29, 2);
      rd = extract32(insn, 0, 5);
 -    base = s->pc_curr;
      if (page) {
          /* ADRP (page based) */
 -        base &= ~0xfff;
          offset <<= 12;
 +        /* The page offset is ok for TARGET_TB_PCREL. */
 +        offset -= s->pc_curr & 0xfff;
      }
 -    tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
 +    gen_pc_plus_diff(s, cpu_reg(s, rd), offset);
  }
  /*
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
+[PULL 22/24] target/arm: Introduce gen_pc_plus_diff for aarch32
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Code of imx_update() is slightly confusing since the "flags" variable
+In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
 doesn't really corespond to anything in real hardware and server as a
 kitchensink accumulating events normally reported via USR1 and USR2
 registers.
-Change the code to explicitly evaluate state of interrupts reported
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-via USR1 and USR2 against corresponding masking bits and use the to
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-detemine if IRQ line should be asserted or not.
+Message-id: 20221020030641.2066807-9-richard.henderson@linaro.org
 NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
 reasons:
 . Emulation code implements a single character FIFO, so this flag
        will always be set since characters are trasmitted as a part of
        the code emulating "push" into the FIFO
 . imx_update() is really just a function doing ORing and maksing
        of reported events, so checking for UTS1_TXEMPTY should happen,
        if it's ever really needed should probably happen outside of
        it.
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/imx_serial.c | 24 ++++++++++++++++--------
+ target/arm/translate.c | 38 +++++++++++++++++++++-----------------
-file changed, 16 insertions(+), 8 deletions(-)
+file changed, 21 insertions(+), 17 deletions(-)
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/target/arm/translate.c
-+++ b/hw/char/imx_serial.c
++++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
+     }
- static void imx_update(IMXSerialState *s)
+ }
 -/* The architectural value of PC.  */
 -static uint32_t read_pc(DisasContext *s)
 -{
 -    return s->pc_curr + (s->thumb ? 4 : 8);
 -}
 -
  /* The pc_curr difference for an architectural jump. */
  static target_long jmp_diff(DisasContext *s, target_long diff)
  {
--    uint32_t flags;
+     return diff + (s->thumb ? 4 : 8);
 +    uint32_t usr1;
 +    uint32_t usr2;
 +    uint32_t mask;
 -    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
 -    if (s->ucr1 & UCR1_TXMPTYEN) {
 -        flags |= (s->uts1 & UTS1_TXEMPTY);
 -    } else {
 -        flags &= ~USR1_TRDY;
 -    }
 +    /*
 +     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
 +     * UCR1, so we can get away with something as simple as the
 +     * following:
 +     */
 +    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
 +    /*
 +     * Bits that we want in USR2 are not as conveniently laid out,
 +     * unfortunately.
 +     */
 +    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    usr2 = s->usr2 & mask;
 -    qemu_set_irq(s->irq, !!flags);
 +    qemu_set_irq(s->irq, usr1 || usr2);
  }
- static void imx_serial_reset(IMXSerialState *s)
++static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)
 +{
 +    tcg_gen_movi_i32(var, s->pc_curr + diff);
 +}
 +
  /* Set a variable to the value of a CPU register.  */
  void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
  {
      if (reg == 15) {
 -        tcg_gen_movi_i32(var, read_pc(s));
 +        gen_pc_plus_diff(s, var, jmp_diff(s, 0));
      } else {
          tcg_gen_mov_i32(var, cpu_R[reg]);
      }
@@ -XXX,XX +XXX,XX @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
      TCGv_i32 tmp = tcg_temp_new_i32();
      if (reg == 15) {
 -        tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs);
 +        /*
 +         * This address is computed from an aligned PC:
 +         * subtract off the low bits.
 +         */
 +        gen_pc_plus_diff(s, tmp, jmp_diff(s, ofs - (s->pc_curr & 3)));
      } else {
          tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
      }
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
  /* Force a TB lookup after an instruction that changes the CPU state.  */
  void gen_lookup_tb(DisasContext *s)
  {
 -    tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
 +    gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s));
      s->base.is_jmp = DISAS_EXIT;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a)
          return false;
      }
      tmp = load_reg(s, a->rm);
 -    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
 +    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb);
      gen_bx(s, tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
  static bool trans_BL(DisasContext *s, arg_i *a)
  {
 -    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
 +    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb);
      gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
      if (s->thumb && (a->imm & 2)) {
          return false;
      }
 -    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
 +    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb);
      store_cpu_field_constant(!s->thumb, thumb);
      /* This jump is computed from an aligned PC: subtract off the low bits. */
      gen_jmp(s, jmp_diff(s, a->imm - (s->pc_curr & 3)));
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
  static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a)
  {
      assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
 -    tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12));
 +    gen_pc_plus_diff(s, cpu_R[14], jmp_diff(s, a->imm << 12));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a)
      assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
      tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1);
 -    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
 +    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1);
      gen_bx(s, tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a)
      tmp = tcg_temp_new_i32();
      tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1);
      tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
 -    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
 +    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1);
      gen_bx(s, tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
      tcg_gen_add_i32(addr, addr, tmp);
      gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB);
 -    tcg_temp_free_i32(addr);
      tcg_gen_add_i32(tmp, tmp, tmp);
 -    tcg_gen_addi_i32(tmp, tmp, read_pc(s));
 +    gen_pc_plus_diff(s, addr, jmp_diff(s, 0));
 +    tcg_gen_add_i32(tmp, tmp, addr);
 +    tcg_temp_free_i32(addr);
      store_reg(s, 15, tmp);
      return true;
  }
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
+[PULL 23/24] target/arm: Enable TARGET_TB_PCREL
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Add support for "TX complete"/TXDC interrupt generate by real HW since
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-it is needed to support guests other than Linux.
+Message-id: 20221020030641.2066807-10-richard.henderson@linaro.org
 Based on the patch by Bill Paul as found here:
 https://bugs.launchpad.net/qemu/+bug/1753314
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Bill Paul <wpaul@windriver.com>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/char/imx_serial.h |  3 +++
+ target/arm/cpu-param.h        |   2 +
- hw/char/imx_serial.c         | 20 +++++++++++++++++---
+ target/arm/translate.h        |  50 +++++++++++++++-
-files changed, 20 insertions(+), 3 deletions(-)
+ target/arm/cpu.c              |  23 ++++----
  target/arm/translate-a64.c    |  64 +++++++++++++-------
  target/arm/translate-m-nocp.c |   2 +-
  target/arm/translate.c        | 108 +++++++++++++++++++++++-----------
 files changed, 178 insertions(+), 71 deletions(-)
-diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
+diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/imx_serial.h
+--- a/target/arm/cpu-param.h
-+++ b/include/hw/char/imx_serial.h
++++ b/target/arm/cpu-param.h
 @@ -XXX,XX +XXX,XX @@
- #define UCR2_RXEN       (1<<1)    /* Receiver enable */
+ # define TARGET_PAGE_BITS_VARY
- #define UCR2_SRST       (1<<0)    /* Reset complete */
+ # define TARGET_PAGE_BITS_MIN  10
-+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
++# define TARGET_TB_PCREL 1
 +
- #define UTS1_TXEMPTY    (1<<6)
+ /*
- #define UTS1_RXEMPTY    (1<<5)
+  * Cache the attrs and shareability fields from the page table entry.
- #define UTS1_TXFULL     (1<<4)
+  *
-@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
+diff --git a/target/arm/translate.h b/target/arm/translate.h
      uint32_t ubmr;
      uint32_t ubrc;
      uint32_t ucr3;
 +    uint32_t ucr4;
      qemu_irq irq;
      CharBackend chr;
 diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/target/arm/translate.h
-+++ b/hw/char/imx_serial.c
++++ b/target/arm/translate.h
 @@ -XXX,XX +XXX,XX @@
- static const VMStateDescription vmstate_imx_serial = {
-     .name = TYPE_IMX_SERIAL,
+ /* internal defines */
--    .version_id = 1,
++
--    .minimum_version_id = 1,
++/*
-+    .version_id = 2,
++ * Save pc_save across a branch, so that we may restore the value from
-+    .minimum_version_id = 2,
++ * before the branch at the point the label is emitted.
-     .fields = (VMStateField[]) {
++ */
-         VMSTATE_INT32(readbuff, IMXSerialState),
++typedef struct DisasLabel {
-         VMSTATE_UINT32(usr1, IMXSerialState),
++    TCGLabel *label;
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
++    target_ulong pc_save;
-         VMSTATE_UINT32(ubmr, IMXSerialState),
++} DisasLabel;
-         VMSTATE_UINT32(ubrc, IMXSerialState),
++
-         VMSTATE_UINT32(ucr3, IMXSerialState),
+ typedef struct DisasContext {
-+        VMSTATE_UINT32(ucr4, IMXSerialState),
+     DisasContextBase base;
-         VMSTATE_END_OF_LIST()
+     const ARMISARegisters *isar;
-     },
- };
+     /* The address of the current instruction being translated. */
-@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
+     target_ulong pc_curr;
-      * unfortunately.
++    /*
 +     * For TARGET_TB_PCREL, the full value of cpu_pc is not known
 +     * (although the page offset is known).  For convenience, the
 +     * translation loop uses the full virtual address that triggered
 +     * the translation, from base.pc_start through pc_curr.
 +     * For efficiency, we do not update cpu_pc for every instruction.
 +     * Instead, pc_save has the value of pc_curr at the time of the
 +     * last update to cpu_pc, which allows us to compute the addend
 +     * needed to bring cpu_pc current: pc_curr - pc_save.
 +     * If cpu_pc now contains the destination of an indirect branch,
 +     * pc_save contains -1 to indicate that relative updates are no
 +     * longer possible.
 +     */
 +    target_ulong pc_save;
      target_ulong page_start;
      uint32_t insn;
      /* Nonzero if this instruction has been conditionally skipped.  */
      int condjmp;
      /* The label that will be jumped to when the instruction is skipped.  */
 -    TCGLabel *condlabel;
 +    DisasLabel condlabel;
      /* Thumb-2 conditional execution bits.  */
      int condexec_mask;
      int condexec_cond;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
       * after decode (ie after any UNDEF checks)
       */
-     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+     bool eci_handled;
-+    /*
+-    /* TCG op to rewind to if this turns out to be an invalid ECI state */
-+     * TCEN and TXDC are both bit 3
+-    TCGOp *insn_eci_rewind;
-+     */
+     int sctlr_b;
-+    mask |= s->ucr4 & UCR4_TCEN;
+     MemOp be_data;
  #if !defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
   */
  uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 +/*
 + * gen_disas_label:
 + * Create a label and cache a copy of pc_save.
 + */
 +static inline DisasLabel gen_disas_label(DisasContext *s)
 +{
 +    return (DisasLabel){
 +        .label = gen_new_label(),
 +        .pc_save = s->pc_save,
 +    };
 +}
 +
-     usr2 = s->usr2 & mask;
++/*
++ * set_disas_label:
-     qemu_set_irq(s->irq, usr1 || usr2);
++ * Emit a label and restore the cached copy of pc_save.
-@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
++ */
-         return s->ucr3;
++static inline void set_disas_label(DisasContext *s, DisasLabel l)
++{
-     case 0x23: /* UCR4 */
++    gen_set_label(l.label);
-+        return s->ucr4;
++    s->pc_save = l.pc_save;
 +}
 +
-     case 0x29: /* BRM Incremental */
+ /*
-         return 0x0; /* TODO */
+  * Helpers for implementing sets of trans_* functions.
+  * Defer the implementation of NAME to FUNC, with optional extra arguments.
-@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-              * qemu_chr_fe_write and background I/O callbacks */
+index XXXXXXX..XXXXXXX 100644
-             qemu_chr_fe_write_all(&s->chr, &ch, 1);
+--- a/target/arm/cpu.c
-             s->usr1 &= ~USR1_TRDY;
++++ b/target/arm/cpu.c
-+            s->usr2 &= ~USR2_TXDC;
+@@ -XXX,XX +XXX,XX @@ static vaddr arm_cpu_get_pc(CPUState *cs)
-             imx_update(s);
+ void arm_cpu_synchronize_from_tb(CPUState *cs,
-             s->usr1 |= USR1_TRDY;
+                                  const TranslationBlock *tb)
-+            s->usr2 |= USR2_TXDC;
+ {
-             imx_update(s);
+-    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 -
 -    /*
 -     * It's OK to look at env for the current mode here, because it's
 -     * never possible for an AArch64 TB to chain to an AArch32 TB.
 -     */
 -    if (is_a64(env)) {
 -        env->pc = tb_pc(tb);
 -    } else {
 -        env->regs[15] = tb_pc(tb);
 +    /* The program counter is always up to date with TARGET_TB_PCREL. */
 +    if (!TARGET_TB_PCREL) {
 +        CPUARMState *env = cs->env_ptr;
 +        /*
 +         * It's OK to look at env for the current mode here, because it's
 +         * never possible for an AArch64 TB to chain to an AArch32 TB.
 +         */
 +        if (is_a64(env)) {
 +            env->pc = tb_pc(tb);
 +        } else {
 +            env->regs[15] = tb_pc(tb);
 +        }
      }
  }
  #endif /* CONFIG_TCG */
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s)
  static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
  {
 -    tcg_gen_movi_i64(dest, s->pc_curr + diff);
 +    assert(s->pc_save != -1);
 +    if (TARGET_TB_PCREL) {
 +        tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff);
 +    } else {
 +        tcg_gen_movi_i64(dest, s->pc_curr + diff);
 +    }
  }
  void gen_a64_update_pc(DisasContext *s, target_long diff)
  {
      gen_pc_plus_diff(s, cpu_pc, diff);
 +    s->pc_save = s->pc_curr + diff;
  }
  /*
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
       * then loading an address into the PC will clear out any tag.
       */
      gen_top_byte_ignore(s, cpu_pc, src, s->tbii);
 +    s->pc_save = -1;
  }
  /*
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
  static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
  {
 -    uint64_t dest = s->pc_curr + diff;
 -
 -    if (use_goto_tb(s, dest)) {
 -        tcg_gen_goto_tb(n);
 -        gen_a64_update_pc(s, diff);
 +    if (use_goto_tb(s, s->pc_curr + diff)) {
 +        /*
 +         * For pcrel, the pc must always be up-to-date on entry to
 +         * the linked TB, so that it can use simple additions for all
 +         * further adjustments.  For !pcrel, the linked TB is compiled
 +         * to know its full virtual address, so we can delay the
 +         * update to pc to the unlinked path.  A long chain of links
 +         * can thus avoid many updates to the PC.
 +         */
 +        if (TARGET_TB_PCREL) {
 +            gen_a64_update_pc(s, diff);
 +            tcg_gen_goto_tb(n);
 +        } else {
 +            tcg_gen_goto_tb(n);
 +            gen_a64_update_pc(s, diff);
 +        }
          tcg_gen_exit_tb(s->base.tb, n);
          s->base.is_jmp = DISAS_NORETURN;
      } else {
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
  {
      unsigned int sf, op, rt;
      int64_t diff;
 -    TCGLabel *label_match;
 +    DisasLabel match;
      TCGv_i64 tcg_cmp;
      sf = extract32(insn, 31, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
      diff = sextract32(insn, 5, 19) * 4;
      tcg_cmp = read_cpu_reg(s, rt, sf);
 -    label_match = gen_new_label();
 -
      reset_btype(s);
 -    tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
 -                        tcg_cmp, 0, label_match);
 +    match = gen_disas_label(s);
 +    tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
 +                        tcg_cmp, 0, match.label);
      gen_goto_tb(s, 0, 4);
 -    gen_set_label(label_match);
 +    set_disas_label(s, match);
      gen_goto_tb(s, 1, diff);
  }
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
  {
      unsigned int bit_pos, op, rt;
      int64_t diff;
 -    TCGLabel *label_match;
 +    DisasLabel match;
      TCGv_i64 tcg_cmp;
      bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
      tcg_cmp = tcg_temp_new_i64();
      tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
 -    label_match = gen_new_label();
      reset_btype(s);
 +
 +    match = gen_disas_label(s);
      tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
 -                        tcg_cmp, 0, label_match);
 +                        tcg_cmp, 0, match.label);
      tcg_temp_free_i64(tcg_cmp);
      gen_goto_tb(s, 0, 4);
 -    gen_set_label(label_match);
 +    set_disas_label(s, match);
      gen_goto_tb(s, 1, diff);
  }
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
      reset_btype(s);
      if (cond < 0x0e) {
          /* genuinely conditional branches */
 -        TCGLabel *label_match = gen_new_label();
 -        arm_gen_test_cc(cond, label_match);
 +        DisasLabel match = gen_disas_label(s);
 +        arm_gen_test_cc(cond, match.label);
          gen_goto_tb(s, 0, 4);
 -        gen_set_label(label_match);
 +        set_disas_label(s, match);
          gen_goto_tb(s, 1, diff);
      } else {
          /* 0xe and 0xf are both "always" conditions */
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->isar = &arm_cpu->isar;
      dc->condjmp = 0;
 -
 +    dc->pc_save = dc->base.pc_first;
      dc->aarch64 = true;
      dc->thumb = false;
      dc->sctlr_b = 0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
  static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
  {
      DisasContext *dc = container_of(dcbase, DisasContext, base);
 +    target_ulong pc_arg = dc->base.pc_next;
 -    tcg_gen_insn_start(dc->base.pc_next, 0, 0);
 +    if (TARGET_TB_PCREL) {
 +        pc_arg &= ~TARGET_PAGE_MASK;
 +    }
 +    tcg_gen_insn_start(pc_arg, 0, 0);
      dc->insn_start = tcg_last_op();
  }
 diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-m-nocp.c
 +++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
      tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
      tcg_gen_or_i32(sfpa, sfpa, aspen);
      arm_gen_condlabel(s);
 -    tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
 +    tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel.label);
      if (s->fp_excp_el != 0) {
          gen_exception_insn_el(s, 0, EXCP_NOCP,
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
  void arm_gen_condlabel(DisasContext *s)
  {
      if (!s->condjmp) {
 -        s->condlabel = gen_new_label();
 +        s->condlabel = gen_disas_label(s);
          s->condjmp = 1;
      }
  }
@@ -XXX,XX +XXX,XX @@ static target_long jmp_diff(DisasContext *s, target_long diff)
  static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)
  {
 -    tcg_gen_movi_i32(var, s->pc_curr + diff);
 +    assert(s->pc_save != -1);
 +    if (TARGET_TB_PCREL) {
 +        tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff);
 +    } else {
 +        tcg_gen_movi_i32(var, s->pc_curr + diff);
 +    }
  }
  /* Set a variable to the value of a CPU register.  */
@@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var)
           */
          tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
          s->base.is_jmp = DISAS_JUMP;
 +        s->pc_save = -1;
      } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) {
          /* For M-profile SP bits [1:0] are always zero */
          tcg_gen_andi_i32(var, var, ~3);
@@ -XXX,XX +XXX,XX @@ void gen_set_condexec(DisasContext *s)
  void gen_update_pc(DisasContext *s, target_long diff)
  {
 -    tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff);
 +    gen_pc_plus_diff(s, cpu_R[15], diff);
 +    s->pc_save = s->pc_curr + diff;
  }
  /* Set PC and Thumb state from var.  var is marked as dead.  */
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
      tcg_gen_andi_i32(cpu_R[15], var, ~1);
      tcg_gen_andi_i32(var, var, 1);
      store_cpu_field(var, thumb);
 +    s->pc_save = -1;
  }
  /*
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
  static inline void gen_bx_excret_final_code(DisasContext *s)
  {
      /* Generate the code to finish possible exception return and end the TB */
 -    TCGLabel *excret_label = gen_new_label();
 +    DisasLabel excret_label = gen_disas_label(s);
      uint32_t min_magic;
      if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
      }
      /* Is the new PC value in the magic range indicating exception return? */
 -    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
 +    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label.label);
      /* No: end the TB as we would for a DISAS_JMP */
      if (s->ss_active) {
          gen_singlestep_exception(s);
      } else {
          tcg_gen_exit_tb(NULL, 0);
      }
 -    gen_set_label(excret_label);
 +    set_disas_label(s, excret_label);
      /* Yes: this is an exception return.
       * At this point in runtime env->regs[15] and env->thumb will hold
       * the exception-return magic number, which do_v7m_exception_exit()
@@ -XXX,XX +XXX,XX @@ static void gen_goto_ptr(void)
   */
  static void gen_goto_tb(DisasContext *s, int n, target_long diff)
  {
 -    target_ulong dest = s->pc_curr + diff;
 -
 -    if (translator_use_goto_tb(&s->base, dest)) {
 -        tcg_gen_goto_tb(n);
 -        gen_update_pc(s, diff);
 +    if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {
 +        /*
 +         * For pcrel, the pc must always be up-to-date on entry to
 +         * the linked TB, so that it can use simple additions for all
 +         * further adjustments.  For !pcrel, the linked TB is compiled
 +         * to know its full virtual address, so we can delay the
 +         * update to pc to the unlinked path.  A long chain of links
 +         * can thus avoid many updates to the PC.
 +         */
 +        if (TARGET_TB_PCREL) {
 +            gen_update_pc(s, diff);
 +            tcg_gen_goto_tb(n);
 +        } else {
 +            tcg_gen_goto_tb(n);
 +            gen_update_pc(s, diff);
 +        }
          tcg_gen_exit_tb(s->base.tb, n);
      } else {
          gen_update_pc(s, diff);
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
  static void arm_skip_unless(DisasContext *s, uint32_t cond)
  {
      arm_gen_condlabel(s);
 -    arm_gen_test_cc(cond ^ 1, s->condlabel);
 +    arm_gen_test_cc(cond ^ 1, s->condlabel.label);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
  {
      /* M-profile low-overhead while-loop start */
      TCGv_i32 tmp;
 -    TCGLabel *nextlabel;
 +    DisasLabel nextlabel;
      if (!dc_isar_feature(aa32_lob, s)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
          }
-         break;
+     }
-@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
-         s->ucr3 = value & 0xffff;
+-    nextlabel = gen_new_label();
-         break;
+-    tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel);
++    nextlabel = gen_disas_label(s);
--    case 0x2d: /* UTS1 */
++    tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel.label);
-     case 0x23: /* UCR4 */
+     tmp = load_reg(s, a->rn);
-+        s->ucr4 = value & 0xffff;
+     store_reg(s, 14, tmp);
-+        imx_update(s);
+     if (a->size != 4) {
-+        break;
+@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
-+
+     }
-+    case 0x2d: /* UTS1 */
+     gen_jmp_tb(s, curr_insn_len(s), 1);
-         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
-                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
+-    gen_set_label(nextlabel);
-         /* TODO */
++    set_disas_label(s, nextlabel);
      gen_jmp(s, jmp_diff(s, a->imm));
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
       * any faster.
       */
      TCGv_i32 tmp;
 -    TCGLabel *loopend;
 +    DisasLabel loopend;
      bool fpu_active;
      if (!dc_isar_feature(aa32_lob, s)) {
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
      if (!a->tp && dc_isar_feature(aa32_mve, s) && fpu_active) {
          /* Need to do a runtime check for LTPSIZE != 4 */
 -        TCGLabel *skipexc = gen_new_label();
 +        DisasLabel skipexc = gen_disas_label(s);
          tmp = load_cpu_field(v7m.ltpsize);
 -        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
 +        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc.label);
          tcg_temp_free_i32(tmp);
          gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
 -        gen_set_label(skipexc);
 +        set_disas_label(s, skipexc);
      }
      if (a->f) {
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
       * loop decrement value is 1. For LETP we need to calculate the decrement
       * value from LTPSIZE.
       */
 -    loopend = gen_new_label();
 +    loopend = gen_disas_label(s);
      if (!a->tp) {
 -        tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend);
 +        tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend.label);
          tcg_gen_addi_i32(cpu_R[14], cpu_R[14], -1);
      } else {
          /*
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
          tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr);
          tcg_temp_free_i32(ltpsize);
 -        tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend);
 +        tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend.label);
          tcg_gen_sub_i32(cpu_R[14], cpu_R[14], decr);
          tcg_temp_free_i32(decr);
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
      /* Jump back to the loop start */
      gen_jmp(s, jmp_diff(s, -a->imm));
 -    gen_set_label(loopend);
 +    set_disas_label(s, loopend);
      if (a->tp) {
          /* Exits from tail-pred loops must reset LTPSIZE to 4 */
          store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
      arm_gen_condlabel(s);
      tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
 -                        tmp, 0, s->condlabel);
 +                        tmp, 0, s->condlabel.label);
      tcg_temp_free_i32(tmp);
      gen_jmp(s, jmp_diff(s, a->imm));
      return true;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      dc->isar = &cpu->isar;
      dc->condjmp = 0;
 -
 +    dc->pc_save = dc->base.pc_first;
      dc->aarch64 = false;
      dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB);
      dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
       */
      dc->eci = dc->condexec_mask = dc->condexec_cond = 0;
      dc->eci_handled = false;
 -    dc->insn_eci_rewind = NULL;
      if (condexec & 0xf) {
          dc->condexec_mask = (condexec & 0xf) << 1;
          dc->condexec_cond = condexec >> 4;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
       * fields here.
       */
      uint32_t condexec_bits;
 +    target_ulong pc_arg = dc->base.pc_next;
 +    if (TARGET_TB_PCREL) {
 +        pc_arg &= ~TARGET_PAGE_MASK;
 +    }
      if (dc->eci) {
          condexec_bits = dc->eci << 4;
      } else {
          condexec_bits = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
      }
 -    tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0);
 +    tcg_gen_insn_start(pc_arg, condexec_bits, 0);
      dc->insn_start = tcg_last_op();
  }
@@ -XXX,XX +XXX,XX @@ static bool arm_check_ss_active(DisasContext *dc)
  static void arm_post_translate_insn(DisasContext *dc)
  {
 -    if (dc->condjmp && !dc->base.is_jmp) {
 -        gen_set_label(dc->condlabel);
 +    if (dc->condjmp && dc->base.is_jmp == DISAS_NEXT) {
 +        if (dc->pc_save != dc->condlabel.pc_save) {
 +            gen_update_pc(dc, dc->condlabel.pc_save - dc->pc_save);
 +        }
 +        gen_set_label(dc->condlabel.label);
          dc->condjmp = 0;
      }
      translator_loop_temp_check(&dc->base);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
      uint32_t pc = dc->base.pc_next;
      uint32_t insn;
      bool is_16bit;
 +    /* TCG op to rewind to if this turns out to be an invalid ECI state */
 +    TCGOp *insn_eci_rewind = NULL;
 +    target_ulong insn_eci_pc_save = -1;
      /* Misaligned thumb PC is architecturally impossible. */
      assert((dc->base.pc_next & 1) == 0);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
           *     insn" case. We will rewind to the marker (ie throwing away
           *     all the generated code) and instead emit "take exception".
           */
 -        dc->insn_eci_rewind = tcg_last_op();
 +        insn_eci_rewind = tcg_last_op();
 +        insn_eci_pc_save = dc->pc_save;
      }
      if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
           * Insn wasn't valid for ECI/ICI at all: undo what we
           * just generated and instead emit an exception
           */
 -        tcg_remove_ops_after(dc->insn_eci_rewind);
 +        tcg_remove_ops_after(insn_eci_rewind);
 +        dc->pc_save = insn_eci_pc_save;
          dc->condjmp = 0;
          gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized());
      }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
      if (dc->condjmp) {
          /* "Condition failed" instruction codepath for the branch/trap insn */
 -        gen_set_label(dc->condlabel);
 +        set_disas_label(dc, dc->condlabel);
          gen_set_condexec(dc);
          if (unlikely(dc->ss_active)) {
              gen_update_pc(dc, curr_insn_len(dc));
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
                            target_ulong *data)
  {
      if (is_a64(env)) {
 -        env->pc = data[0];
 +        if (TARGET_TB_PCREL) {
 +            env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
 +        } else {
 +            env->pc = data[0];
 +        }
          env->condexec_bits = 0;
          env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
      } else {
 -        env->regs[15] = data[0];
 +        if (TARGET_TB_PCREL) {
 +            env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
 +        } else {
 +            env->regs[15] = data[0];
 +        }
          env->condexec_bits = data[1];
          env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
      }
 --
-.16.2
+.25.1

-[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+[PULL 24/24] hw/ide/microdrive: Use device_cold_reset() for self-resets
-Our BCM2836 type is really a generic one that can be any of
+Currently the microdrive code uses device_legacy_reset() to reset
-the bcm283x family. Rename it accordingly. We change only
+itself, and has its reset method call reset on the IDE bus as the
-the names which are visible via the header file to the
+last thing it does.  Switch to using device_cold_reset().
 rest of the QEMU code, leaving private function names
 in bcm2836.c as they are.
-This is a preliminary to making bcm283x be an abstract
+The only concrete microdrive device is the TYPE_DSCM1XXXX; it is not
-parent class to specific types for the bcm2836 and bcm2837.
+command-line pluggable, so it is used only by the old pxa2xx Arm
 boards 'akita', 'borzoi', 'spitz', 'terrier' and 'tosa'.
 You might think that this would result in the IDE bus being
 reset automatically, but it does not, because the IDEBus type
 does not set the BusClass::reset method. Instead the controller
 must explicitly call ide_bus_reset(). We therefore leave that
 call in md_reset().
 Note also that because the PCMCIA card device is a direct subclass of
 TYPE_DEVICE and we don't model the PCMCIA controller-to-card
 interface as a qbus, PCMCIA cards are not on any qbus and so they
 don't get reset when the system is reset.  The reset only happens via
 the dscm1xxxx_attach() and dscm1xxxx_detach() functions during
 machine creation.
 Because our aim here is merely to try to get rid of calls to the
 device_legacy_reset() function, we leave these other dubious
 reset-related issues alone.  (They all stem from this code being
 absolutely ancient.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20221013174042.1602926-1-peter.maydell@linaro.org
 Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 12 ++++++------
+ hw/ide/microdrive.c | 8 ++++----
- hw/arm/bcm2836.c         | 17 +++++++++--------
+file changed, 4 insertions(+), 4 deletions(-)
  hw/arm/raspi.c           | 16 ++++++++--------
 files changed, 23 insertions(+), 22 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/hw/ide/microdrive.c
-+++ b/include/hw/arm/bcm2836.h
++++ b/hw/ide/microdrive.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
- #include "hw/arm/bcm2835_peripherals.h"
+     case 0x00:    /* Configuration Option Register */
- #include "hw/intc/bcm2836_control.h"
+         s->opt = value & 0xcf;
+         if (value & OPT_SRESET) {
--#define TYPE_BCM2836 "bcm2836"
+-            device_legacy_reset(DEVICE(s));
--#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
++            device_cold_reset(DEVICE(s));
-+#define TYPE_BCM283X "bcm283x"
+         }
-+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
+         md_interrupt_update(s);
+         break;
--#define BCM2836_NCPUS 4
+@@ -XXX,XX +XXX,XX @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
-+#define BCM283X_NCPUS 4
+     case 0xe:    /* Device Control */
+         s->ctrl = value;
--typedef struct BCM2836State {
+         if (value & CTRL_SRST) {
-+typedef struct BCM283XState {
+-            device_legacy_reset(DEVICE(s));
-     /*< private >*/
++            device_cold_reset(DEVICE(s));
-     DeviceState parent_obj;
+         }
-     /*< public >*/
+         md_interrupt_update(s);
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
+         break;
-     char *cpu_type;
+@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_attach(PCMCIACardState *card)
-     uint32_t enabled_cpus;
+     md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
+     md->io_base = 0x0;
--    ARMCPU cpus[BCM2836_NCPUS];
-+    ARMCPU cpus[BCM283X_NCPUS];
+-    device_legacy_reset(DEVICE(md));
-     BCM2836ControlState control;
++    device_cold_reset(DEVICE(md));
-     BCM2835PeripheralState peripherals;
+     md_interrupt_update(md);
--} BCM2836State;
-+} BCM283XState;
+     return 0;
+@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_detach(PCMCIACardState *card)
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2836.c
 +++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
  static void bcm2836_init(Object *obj)
  {
--    BCM2836State *s = BCM2836(obj);
+     MicroDriveState *md = MICRODRIVE(card);
-+    BCM283XState *s = BCM283X(obj);
+-    device_legacy_reset(DEVICE(md));
-     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
++    device_cold_reset(DEVICE(md));
-     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
+     return 0;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
  static void bcm2836_realize(DeviceState *dev, Error **errp)
  {
 -    BCM2836State *s = BCM2836(dev);
 +    BCM283XState *s = BCM283X(dev);
      Object *obj;
      Error *err = NULL;
      int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      /* common peripherals from bcm2835 */
      obj = OBJECT(dev);
 -    for (n = 0; n < BCM2836_NCPUS; n++) {
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
          object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                            s->cpu_type);
          object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
          qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 -    for (n = 0; n < BCM2836_NCPUS; n++) {
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
          /* Mirror bcm2836, which has clusterid set to 0xf
           * TODO: this should be converted to a property of ARM_CPU
           */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
  }
- static Property bcm2836_props[] = {
--    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
--    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
-+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
-+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
-+                       BCM283X_NCPUS),
-     DEFINE_PROP_END_OF_LIST()
- };
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
- }
- static const TypeInfo bcm2836_type_info = {
--    .name = TYPE_BCM2836,
-+    .name = TYPE_BCM283X,
-     .parent = TYPE_DEVICE,
--    .instance_size = sizeof(BCM2836State),
-+    .instance_size = sizeof(BCM283XState),
-     .instance_init = bcm2836_init,
-     .class_init = bcm2836_class_init,
- };
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
-+++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
- static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
- typedef struct RasPiState {
--    BCM2836State soc;
-+    BCM283XState soc;
-     MemoryRegion ram;
- } RasPiState;
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
-     BusState *bus;
-     DeviceState *carddev;
--    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
-+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
-     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
-                               &error_abort);
-@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
-     mc->no_floppy = 1;
-     mc->no_cdrom = 1;
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
--    mc->max_cpus = BCM2836_NCPUS;
--    mc->min_cpus = BCM2836_NCPUS;
--    mc->default_cpus = BCM2836_NCPUS;
-+    mc->max_cpus = BCM283X_NCPUS;
-+    mc->min_cpus = BCM283X_NCPUS;
-+    mc->default_cpus = BCM283X_NCPUS;
-     mc->default_ram_size = 1024 * 1024 * 1024;
-     mc->ignore_memory_transaction_failures = true;
- };
-@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
-     mc->no_floppy = 1;
-     mc->no_cdrom = 1;
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
--    mc->max_cpus = BCM2836_NCPUS;
--    mc->min_cpus = BCM2836_NCPUS;
--    mc->default_cpus = BCM2836_NCPUS;
-+    mc->max_cpus = BCM283X_NCPUS;
-+    mc->min_cpus = BCM283X_NCPUS;
-+    mc->default_cpus = BCM283X_NCPUS;
-     mc->default_ram_size = 1024 * 1024 * 1024;
- }
- DEFINE_MACHINE("raspi3", raspi3_machine_init)
 --
-.16.2
+.25.1

Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3

----------------------------------------------------------------
Andrey Smirnov (2):
      char: i.MX: Simplify imx_update()
      char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
      fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
      hw/arm/bcm2386: Fix parent type of bcm2386
      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
      hw/arm/bcm2836: Create proper bcm2837 device
      hw/arm/bcm2836: Use correct affinity values for BCM2837
      hw/arm/bcm2836: Hardcode correct CPU type
      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
      dump: Update correct kdump phys_base field for AArch64

From: Guenter Roeck <linux@roeck-us.net>

The sabrelite machine model used by qemu-system-arm is based on the
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
controller which is supported in QEMU using the imx_fec.c module
(actually called imx.enet for this model.)

The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
imx.enet device like this:

#define FSL_IMX6_ENET_MAC_1588_IRQ 118
 #define FSL_IMX6_ENET_MAC_IRQ 119

According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
interrupts are as follows.

150 ENET MAC 0 IRQ
151 ENET MAC 0 1588 Timer interrupt

where

150 - 32 == 118
151 - 32 == 119

In other words, the vector definitions in the fsl-imx6.h file are reversed.

Fixing the interrupts alone causes problems with older Linux kernels:
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
error handling. This is a Linux kernel problem, not a qemu problem:
the Linux kernel only worked by accident since it requested both interrupts.

For backward compatibility, generate the Ethernet interrupt on both interrupt
lines. This was shown to work from all Linux kernel releases starting with
v3.16.

Link: https://bugs.launchpad.net/qemu/+bug/1753309
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  4 ++--
 hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
 #define FSL_IMX6_HDMI_MASTER_IRQ 115
 #define FSL_IMX6_HDMI_CEC_IRQ 116
 #define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
-#define FSL_IMX6_ENET_MAC_IRQ 119
+#define FSL_IMX6_ENET_MAC_IRQ 118
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
 #define FSL_IMX6_PCIE1_IRQ 120
 #define FSL_IMX6_PCIE2_IRQ 121
 #define FSL_IMX6_PCIE3_IRQ 122
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
 
 static void imx_eth_update(IMXFECState *s)
 {
-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+    /*
+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+     * interrupts swapped. This worked with older versions of Linux (4.14
+     * and older) since Linux associated both interrupt lines with Ethernet
+     * MAC interrupts. Specifically,
+     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
+     *   timer interrupts. Those versions of Linux fail with versions of QEMU
+     *   with swapped interrupt assignments.
+     * - In linux 4.14, both interrupt lines were registered with the Ethernet
+     *   MAC interrupt handler. As a result, all versions of qemu happen to
+     *   work, though that is accidental.
+     * - In Linux 4.9 and older, the timer interrupt was registered directly
+     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
+     *   redirected to a GPIO interrupt to work around erratum ERR006687.
+     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
+     *   interrupt never fired since IOMUX is currently not supported in qemu.
+     *   Linux instead received MAC interrupts on the timer interrupt.
+     *   As a result, qemu versions with the swapped interrupt assignment work,
+     *   albeit accidentally, but qemu versions with the correct interrupt
+     *   assignment fail.
+     *
+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
+     * interrrupts on both interrupt lines. This should be changed if and when
+     * qemu supports IOMUX.
+     */
+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
         qemu_set_irq(s->irq[1], 1);
     } else {
         qemu_set_irq(s->irq[1], 0);
-- 
2.16.2

From: Wei Huang <wei@redhat.com>

For guest kernel that supports KASLR, the load address can change every
time when guest VM runs. To find the physical base address correctly,
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
However this string pattern is only available on x86_64. AArch64 uses a
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
QEMU dump uses the correct string on AArch64.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 dump.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/dump.c b/dump.c
index XXXXXXX..XXXXXXX 100644
--- a/dump.c
+++ b/dump.c
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
 
     lines = g_strsplit((char *)vmci, "\n", -1);
     for (i = 0; lines[i]; i++) {
-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+        const char *prefix = NULL;
+
+        if (s->dump_info.d_machine == EM_X86_64) {
+            prefix = "NUMBER(phys_base)=";
+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+            prefix = "NUMBER(PHYS_OFFSET)=";
+        }
+
+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
                               &phys_base) < 0) {
-                warn_report("Failed to read NUMBER(phys_base)=");
+                warn_report("Failed to read %s", prefix);
             } else {
                 s->dump_info.phys_base = phys_base;
             }
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Code of imx_update() is slightly confusing since the "flags" variable
doesn't really corespond to anything in real hardware and server as a
kitchensink accumulating events normally reported via USR1 and USR2
registers.

Change the code to explicitly evaluate state of interrupts reported
via USR1 and USR2 against corresponding masking bits and use the to
detemine if IRQ line should be asserted or not.

NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
reasons:

1. Emulation code implements a single character FIFO, so this flag
       will always be set since characters are trasmitted as a part of
       the code emulating "push" into the FIFO

2. imx_update() is really just a function doing ORing and maksing
       of reported events, so checking for UTS1_TXEMPTY should happen,
       if it's ever really needed should probably happen outside of
       it.

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/imx_serial.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
 
 static void imx_update(IMXSerialState *s)
 {
-    uint32_t flags;
+    uint32_t usr1;
+    uint32_t usr2;
+    uint32_t mask;
 
-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
-    if (s->ucr1 & UCR1_TXMPTYEN) {
-        flags |= (s->uts1 & UTS1_TXEMPTY);
-    } else {
-        flags &= ~USR1_TRDY;
-    }
+    /*
+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+     * UCR1, so we can get away with something as simple as the
+     * following:
+     */
+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+    /*
+     * Bits that we want in USR2 are not as conveniently laid out,
+     * unfortunately.
+     */
+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    usr2 = s->usr2 & mask;
 
-    qemu_set_irq(s->irq, !!flags);
+    qemu_set_irq(s->irq, usr1 || usr2);
 }
 
 static void imx_serial_reset(IMXSerialState *s)
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.

Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/imx_serial.h |  3 +++
 hw/char/imx_serial.c         | 20 +++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -XXX,XX +XXX,XX @@
 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
 #define UCR2_SRST       (1<<0)    /* Reset complete */
 
+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+
 #define UTS1_TXEMPTY    (1<<6)
 #define UTS1_RXEMPTY    (1<<5)
 #define UTS1_TXFULL     (1<<4)
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
     uint32_t ubmr;
     uint32_t ubrc;
     uint32_t ucr3;
+    uint32_t ucr4;
 
     qemu_irq irq;
     CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
 
 static const VMStateDescription vmstate_imx_serial = {
     .name = TYPE_IMX_SERIAL,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_INT32(readbuff, IMXSerialState),
         VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
         VMSTATE_UINT32(ubmr, IMXSerialState),
         VMSTATE_UINT32(ubrc, IMXSerialState),
         VMSTATE_UINT32(ucr3, IMXSerialState),
+        VMSTATE_UINT32(ucr4, IMXSerialState),
         VMSTATE_END_OF_LIST()
     },
 };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
      * unfortunately.
      */
     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    /*
+     * TCEN and TXDC are both bit 3
+     */
+    mask |= s->ucr4 & UCR4_TCEN;
+
     usr2 = s->usr2 & mask;
 
     qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
         return s->ucr3;
 
     case 0x23: /* UCR4 */
+        return s->ucr4;
+
     case 0x29: /* BRM Incremental */
         return 0x0; /* TODO */
 
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
              * qemu_chr_fe_write and background I/O callbacks */
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->usr1 &= ~USR1_TRDY;
+            s->usr2 &= ~USR2_TXDC;
             imx_update(s);
             s->usr1 |= USR1_TRDY;
+            s->usr2 |= USR2_TXDC;
             imx_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
         s->ucr3 = value & 0xffff;
         break;
 
-    case 0x2d: /* UTS1 */
     case 0x23: /* UCR4 */
+        s->ucr4 = value & 0xffff;
+        imx_update(s);
+        break;
+
+    case 0x2d: /* UTS1 */
         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
         /* TODO */
-- 
2.16.2

For the rpi1 and 2 we want to boot the Linux kernel via some
custom setup code that makes sure that the SMC instruction
acts as a no-op, because it's used for cache maintenance.
The rpi3 boots AArch64 kernels, which don't need SMC for
cache maintenance and always expect to be booted non-secure.
Don't fill in the aarch32-specific parts of the binfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     binfo.board_id = raspi_boardid[version];
     binfo.ram_size = ram_size;
     binfo.nb_cpus = smp_cpus;
-    binfo.board_setup_addr = BOARDSETUP_ADDR;
-    binfo.write_board_setup = write_board_setup;
-    binfo.secure_board_setup = true;
-    binfo.secure_boot = true;
+
+    if (version <= 2) {
+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         * mode before booting a kernel (to set up the SMC vectors so
+         * that we get a no-op SMC; this is used by Linux to call the
+         * firmware for some cache maintenance operations.
+         * The rpi3 doesn't need this.
+         */
+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+        binfo.write_board_setup = write_board_setup;
+        binfo.secure_board_setup = true;
+        binfo.secure_boot = true;
+    }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-- 
2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,
the board code has not mistakenly set either secure_boot or
secure_board_setup. It doesn't make sense to set secure_boot,
because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but
we don't currently support that, because only the AArch32
bootloader[] code calls this hook; bootloader_aarch64[] does not.
Since we don't have a current need for this functionality, just
assert that we don't try to use it. If it's needed we'll add
it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     } else {
                         env->pstate = PSTATE_MODE_EL1h;
                     }
+                    /* AArch64 kernels never boot in secure mode */
+                    assert(!info->secure_boot);
+                    /* This hook is only supported for AArch32 currently:
+                     * bootloader_aarch64[] will not call the hook, and
+                     * the code above has already dropped us into EL2 or EL1.
+                     */
+                    assert(!info->secure_board_setup);
                 }
 
                 /* Set to non-secure if not a secure boot */
-- 
2.16.2

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

The TypeInfo and state struct for bcm2386 disagree about what the
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
but the BCM2386State struct only defines the parent_obj field
as DeviceState. This would have caused problems if anything
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
need any of the additional functionality TYPE_SYS_BUS_DEVICE
provides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo bcm2836_type_info = {
     .name = TYPE_BCM2836,
-    .parent = TYPE_SYS_BUS_DEVICE,
+    .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM2836State),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
-- 
2.16.2

Our BCM2836 type is really a generic one that can be any of
the bcm283x family. Rename it accordingly. We change only
the names which are visible via the header file to the
rest of the QEMU code, leaving private function names
in bcm2836.c as they are.

This is a preliminary to making bcm283x be an abstract
parent class to specific types for the bcm2836 and bcm2837.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 12 ++++++------
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           | 16 ++++++++--------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
-#define TYPE_BCM2836 "bcm2836"
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+#define TYPE_BCM283X "bcm283x"
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 
-#define BCM2836_NCPUS 4
+#define BCM283X_NCPUS 4
 
-typedef struct BCM2836State {
+typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
     char *cpu_type;
     uint32_t enabled_cpus;
 
-    ARMCPU cpus[BCM2836_NCPUS];
+    ARMCPU cpus[BCM283X_NCPUS];
     BCM2836ControlState control;
     BCM2835PeripheralState peripherals;
-} BCM2836State;
+} BCM283XState;
 
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 static void bcm2836_init(Object *obj)
 {
-    BCM2836State *s = BCM2836(obj);
+    BCM283XState *s = BCM283X(obj);
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
 
 static void bcm2836_realize(DeviceState *dev, Error **errp)
 {
-    BCM2836State *s = BCM2836(dev);
+    BCM283XState *s = BCM283X(dev);
     Object *obj;
     Error *err = NULL;
     int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     /* common peripherals from bcm2835 */
 
     obj = OBJECT(dev);
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                           s->cpu_type);
         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         /* Mirror bcm2836, which has clusterid set to 0xf
          * TODO: this should be converted to a property of ARM_CPU
          */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                       BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 }
 
 static const TypeInfo bcm2836_type_info = {
-    .name = TYPE_BCM2836,
+    .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
-    .instance_size = sizeof(BCM2836State),
+    .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
 
 typedef struct RasPiState {
-    BCM2836State soc;
+    BCM283XState soc;
     MemoryRegion ram;
 } RasPiState;
 
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
 }
 DEFINE_MACHINE("raspi3", raspi3_machine_init)
-- 
2.16.2

The bcm2837 is pretty similar to the bcm2836, but it does have
some differences. Notably, the MPIDR affinity aff1 values it
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
uses, and if this is wrong Linux will not boot.

Rather than trying to have one device with properties that
configure it differently for the two cases, create two
separate QOM devices for the two SoCs. We use the same approach
as hw/arm/aspeed_soc.c and share code and have a data table
that might differ per-SoC. For the moment the two types don't
actually have different behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
 hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
 hw/arm/raspi.c           |  3 ++-
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 
 #define BCM283X_NCPUS 4
 
+/* These type names are for specific SoCs; other than instantiating
+ * them, code using these devices should always handle them via the
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ */
+#define TYPE_BCM2836 "bcm2836"
+#define TYPE_BCM2837 "bcm2837"
+
 typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
     BCM2835PeripheralState peripherals;
 } BCM283XState;
 
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+    DeviceClass parent_class;
+    const BCM283XInfo *info;
+} BCM283XClass;
+
+#define BCM283X_CLASS(klass) \
+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
 #define BCM2836_CONTROL_BASE    0x40000000
 
+struct BCM283XInfo {
+    const char *name;
+};
+
+static const BCM283XInfo bcm283x_socs[] = {
+    {
+        .name = TYPE_BCM2836,
+    },
+    {
+        .name = TYPE_BCM2837,
+    },
+};
+
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void bcm2836_class_init(ObjectClass *oc, void *data)
+static void bcm283x_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
+    BCM283XClass *bc = BCM283X_CLASS(oc);
 
-    dc->props = bcm2836_props;
+    bc->info = data;
     dc->realize = bcm2836_realize;
+    dc->props = bcm2836_props;
 }
 
-static const TypeInfo bcm2836_type_info = {
+static const TypeInfo bcm283x_type_info = {
     .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
-    .class_init = bcm2836_class_init,
+    .class_size = sizeof(BCM283XClass),
+    .abstract = true,
 };
 
 static void bcm2836_register_types(void)
 {
-    type_register_static(&bcm2836_type_info);
+    int i;
+
+    type_register_static(&bcm283x_type_info);
+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+        TypeInfo ti = {
+            .name = bcm283x_socs[i].name,
+            .parent = TYPE_BCM283X,
+            .class_init = bcm283x_class_init,
+            .class_data = (void *) &bcm283x_socs[i],
+        };
+        type_register(&ti);
+    }
 }
 
 type_init(bcm2836_register_types)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+    object_initialize(&s->soc, sizeof(s->soc),
+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
-- 
2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
is required for Linux to boot.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Now we have separate types for BCM2386 and BCM2387, we might as well
just hard-code the CPU type they use rather than having it passed
through as an object property. This then lets us put the initialization
of the CPU object in init rather than realize.

Note that this change means that it's no longer possible on
the command line to use -cpu to ask for a different kind of
CPU than the SoC supports. This was never a supported thing to
do anyway; we were just not sanity-checking the command line.

This does require us to only build the bcm2837 object on
TARGET_AARCH64 configs, since otherwise it won't instantiate
due to the missing cortex-a53 device and "make check" will fail.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 24 +++++++++++++++---------
 hw/arm/raspi.c   |  2 --
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 struct BCM283XInfo {
     const char *name;
+    const char *cpu_type;
     int clusterid;
 };
 
 static const BCM283XInfo bcm283x_socs[] = {
     {
         .name = TYPE_BCM2836,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
         .clusterid = 0xf,
     },
+#ifdef TARGET_AARCH64
     {
         .name = TYPE_BCM2837,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
         .clusterid = 0x0,
     },
+#endif
 };
 
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+    const BCM283XInfo *info = bc->info;
+    int n;
+
+    for (n = 0; n < BCM283X_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          info->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
-    obj = OBJECT(dev);
-    for (n = 0; n < BCM283X_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          s->cpu_type);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
-
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                        BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
-                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
-- 
2.16.2

The raspi3 has AArch64 CPUs, which means that our smpboot
code for keeping the secondary CPUs in a pen needs to have
a version for A64 as well as A32. Without this, the
secondary CPUs go into an infinite loop of taking undefined
instruction exceptions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
 
 /* Table of Linux board IDs for different Pi versions */
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                        info->smp_loader_start);
 }
 
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+     * The mechanism for doing the spin-table is also entirely different.
+     * We must have four 64-bit fields at absolute addresses
+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+     * our CPUs, and which we must ensure are zero initialized before
+     * the primary CPU goes into the kernel. We put these variables inside
+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+     */
+    static const uint32_t smpboot[] = {
+        0xd2801b05, /*        mov     x5, 0xd8 */
+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+        0x924004c6, /*        and     x6, x6, #0x3 */
+        0xd503205f, /* spin:  wfe */
+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+        0xb4ffffc4, /*        cbz     x4, spin */
+        0xd2800000, /*        mov     x0, #0x0 */
+        0xd2800001, /*        mov     x1, #0x0 */
+        0xd2800002, /*        mov     x2, #0x0 */
+        0xd2800003, /*        mov     x3, #0x0 */
+        0xd61f0080, /*        br      x4 */
+    };
+
+    static const uint64_t spintables[] = {
+        0, 0, 0, 0
+    };
+
+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
+                       info->smp_loader_start);
+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+                       SPINTABLE_ADDR);
+}
+
 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
         binfo.smp_loader_start = SMPBOOT_ADDR;
-        binfo.write_secondary_boot = write_smpboot;
+        if (version == 2) {
+            binfo.write_secondary_boot = write_smpboot;
+        } else {
+            binfo.write_secondary_boot = write_smpboot64;
+        }
         binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
-- 
2.16.2

Hi; here's the latest arm pullreq. This is mostly patches from
RTH, plus a couple of other more minor things. Switching to
PCREL is the big one, hopefully should improve performance.

thanks
-- PMM

The following changes since commit 214a8da23651f2472b296b3293e619fd58d9e212:

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-10-18 11:14:31 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221020

for you to fetch changes up to 5db899303799e49209016a93289b8694afa1449e:

hw/ide/microdrive: Use device_cold_reset() for self-resets (2022-10-20 12:11:53 +0100)

----------------------------------------------------------------
target-arm queue:
 * Switch to TARGET_TB_PCREL
 * More pagetable-walk refactoring preparatory to HAFDBS
 * update the cortex-a15 MIDR to latest rev
 * hw/char/pl011: fix baud rate calculation
 * hw/ide/microdrive: Use device_cold_reset() for self-resets

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: update the cortex-a15 MIDR to latest rev

Baruch Siach (1):
      hw/char/pl011: fix baud rate calculation

Peter Maydell (1):
      hw/ide/microdrive: Use device_cold_reset() for self-resets

Richard Henderson (21):
      target/arm: Enable TARGET_PAGE_ENTRY_EXTRA
      target/arm: Use probe_access_full for MTE
      target/arm: Use probe_access_full for BTI
      target/arm: Add ARMMMUIdx_Phys_{S,NS}
      target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx
      target/arm: Restrict tlb flush from vttbr_write to vmid change
      target/arm: Split out S1Translate type
      target/arm: Plumb debug into S1Translate
      target/arm: Move be test for regime into S1TranslateResult
      target/arm: Use softmmu tlbs for page table walking
      target/arm: Split out get_phys_addr_twostage
      target/arm: Use bool consistently for get_phys_addr subroutines
      target/arm: Introduce curr_insn_len
      target/arm: Change gen_goto_tb to work on displacements
      target/arm: Change gen_*set_pc_im to gen_*update_pc
      target/arm: Change gen_exception_insn* to work on displacements
      target/arm: Remove gen_exception_internal_insn pc argument
      target/arm: Change gen_jmp* to work on displacements
      target/arm: Introduce gen_pc_plus_diff for aarch64
      target/arm: Introduce gen_pc_plus_diff for aarch32
      target/arm: Enable TARGET_TB_PCREL

From: Richard Henderson <richard.henderson@linaro.org>

The CPUTLBEntryFull structure now stores the original pte attributes, as
well as the physical address.  Therefore, we no longer need a separate
bit in MemTxAttrs, nor do we need to walk the tree of memory regions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h               |  1 -
 target/arm/sve_ldst_internal.h |  1 +
 target/arm/mte_helper.c        | 62 ++++++++++------------------------
 target/arm/sve_helper.c        | 54 ++++++++++-------------------
 target/arm/tlb_helper.c        |  4 ---
 5 files changed, 36 insertions(+), 86 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
  * generic target bits directly.
  */
 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
-#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
 
 /*
  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_ldst_internal.h
+++ b/target/arm/sve_ldst_internal.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     void *host;
     int flags;
     MemTxAttrs attrs;
+    bool tagged;
 } SVEHostPage;
 
 bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
                       TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1);
     return tags + index;
 #else
-    uintptr_t index;
     CPUTLBEntryFull *full;
+    MemTxAttrs attrs;
     int in_page, flags;
-    ram_addr_t ptr_ra;
     hwaddr ptr_paddr, tag_paddr, xlat;
     MemoryRegion *mr;
     ARMASIdx tag_asi;
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      * valid.  Indicate to probe_access_flags no-fault, then assert that
      * we received a valid page.
      */
-    flags = probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx,
-                               ra == 0, &host, ra);
+    flags = probe_access_full(env, ptr, ptr_access, ptr_mmu_idx,
+                              ra == 0, &host, &full, ra);
     assert(!(flags & TLB_INVALID_MASK));
 
-    /*
-     * Find the CPUTLBEntryFull for ptr.  This *must* be present in the TLB
-     * because we just found the mapping.
-     * TODO: Perhaps there should be a cputlb helper that returns a
-     * matching tlb entry + iotlb entry.
-     */
-    index = tlb_index(env, ptr_mmu_idx, ptr);
-# ifdef CONFIG_DEBUG_TCG
-    {
-        CPUTLBEntry *entry = tlb_entry(env, ptr_mmu_idx, ptr);
-        target_ulong comparator = (ptr_access == MMU_DATA_LOAD
-                                   ? entry->addr_read
-                                   : tlb_addr_write(entry));
-        g_assert(tlb_hit(comparator, ptr));
-    }
-# endif
-    full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index];
-
     /* If the virtual page MemAttr != Tagged, access unchecked. */
-    if (!arm_tlb_mte_tagged(&full->attrs)) {
+    if (full->pte_attrs != 0xf0) {
         return NULL;
     }
 
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
         return NULL;
     }
 
+    /*
+     * Remember these values across the second lookup below,
+     * which may invalidate this pointer via tlb resize.
+     */
+    ptr_paddr = full->phys_addr;
+    attrs = full->attrs;
+    full = NULL;
+
     /*
      * The Normal memory access can extend to the next page.  E.g. a single
      * 8-byte access to the last byte of a page will check only the last
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
      */
     in_page = -(ptr | TARGET_PAGE_MASK);
     if (unlikely(ptr_size > in_page)) {
-        void *ignore;
-        flags |= probe_access_flags(env, ptr + in_page, ptr_access,
-                                    ptr_mmu_idx, ra == 0, &ignore, ra);
+        flags |= probe_access_full(env, ptr + in_page, ptr_access,
+                                   ptr_mmu_idx, ra == 0, &host, &full, ra);
         assert(!(flags & TLB_INVALID_MASK));
     }
 
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
     if (unlikely(flags & TLB_WATCHPOINT)) {
         int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
         assert(ra != 0);
-        cpu_check_watchpoint(env_cpu(env), ptr, ptr_size,
-                             full->attrs, wp, ra);
+        cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra);
     }
 
-    /*
-     * Find the physical address within the normal mem space.
-     * The memory region lookup must succeed because TLB_MMIO was
-     * not set in the cputlb lookup above.
-     */
-    mr = memory_region_from_host(host, &ptr_ra);
-    tcg_debug_assert(mr != NULL);
-    tcg_debug_assert(memory_region_is_ram(mr));
-    ptr_paddr = ptr_ra;
-    do {
-        ptr_paddr += mr->addr;
-        mr = mr->container;
-    } while (mr);
-
     /* Convert to the physical address in tag space.  */
     tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1);
 
     /* Look up the address in tag space. */
-    tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
+    tag_asi = attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
     tag_as = cpu_get_address_space(env_cpu(env), tag_asi);
     mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL,
-                                 tag_access == MMU_DATA_STORE,
-                                 full->attrs);
+                                 tag_access == MMU_DATA_STORE, attrs);
 
     /*
      * Note that @mr will never be NULL.  If there is nothing in the address
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
      */
     addr = useronly_clean_ptr(addr);
 
+#ifdef CONFIG_USER_ONLY
     flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
                                &info->host, retaddr);
+    memset(&info->attrs, 0, sizeof(info->attrs));
+    /* Require both ANON and MTE; see allocation_tag_mem(). */
+    info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
+#else
+    CPUTLBEntryFull *full;
+    flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
+                              &info->host, &full, retaddr);
+    info->attrs = full->attrs;
+    info->tagged = full->pte_attrs == 0xf0;
+#endif
     info->flags = flags;
 
     if (flags & TLB_INVALID_MASK) {
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
 
     /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
     info->host -= mem_off;
-
-#ifdef CONFIG_USER_ONLY
-    memset(&info->attrs, 0, sizeof(info->attrs));
-    /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */
-    arm_tlb_mte_tagged(&info->attrs) =
-        (flags & PAGE_ANON) && (flags & PAGE_MTE);
-#else
-    /*
-     * Find the iotlbentry for addr and return the transaction attributes.
-     * This *must* be present in the TLB because we just found the mapping.
-     */
-    {
-        uintptr_t index = tlb_index(env, mmu_idx, addr);
-
-# ifdef CONFIG_DEBUG_TCG
-        CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
-        target_ulong comparator = (access_type == MMU_DATA_LOAD
-                                   ? entry->addr_read
-                                   : tlb_addr_write(entry));
-        g_assert(tlb_hit(comparator, addr));
-# endif
-
-        CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
-        info->attrs = full->attrs;
-    }
-#endif
-
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env,
     intptr_t mem_off, reg_off, reg_last;
 
     /* Process the page only if MemAttr == Tagged. */
-    if (arm_tlb_mte_tagged(&info->page[0].attrs)) {
+    if (info->page[0].tagged) {
         mem_off = info->mem_off_first[0];
         reg_off = info->reg_off_first[0];
         reg_last = info->reg_off_split;
@@ -XXX,XX +XXX,XX @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env,
     }
 
     mem_off = info->mem_off_first[1];
-    if (mem_off >= 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) {
+    if (mem_off >= 0 && info->page[1].tagged) {
         reg_off = info->reg_off_first[1];
         reg_last = info->reg_off_last[1];
 
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr,
      * Disable MTE checking if the Tagged bit is not set.  Since TBI must
      * be set within MTEDESC for MTE, !mtedesc => !mte_active.
      */
-    if (!arm_tlb_mte_tagged(&info.page[0].attrs)) {
+    if (!info.page[0].tagged) {
         mtedesc = 0;
     }
 
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                         cpu_check_watchpoint(env_cpu(env), addr, msize,
                                              info.attrs, BP_MEM_READ, retaddr);
                     }
-                    if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
+                    if (mtedesc && info.tagged) {
                         mte_check(env, mtedesc, addr, retaddr);
                     }
                     if (unlikely(info.flags & TLB_MMIO)) {
@@ -XXX,XX +XXX,XX @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                                              msize, info.attrs,
                                              BP_MEM_READ, retaddr);
                     }
-                    if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
+                    if (mtedesc && info.tagged) {
                         mte_check(env, mtedesc, addr, retaddr);
                     }
                     tlb_fn(env, &scratch, reg_off, addr, retaddr);
@@ -XXX,XX +XXX,XX @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                      (env_cpu(env), addr, msize) & BP_MEM_READ)) {
                     goto fault;
                 }
-                if (mtedesc &&
-                    arm_tlb_mte_tagged(&info.attrs) &&
-                    !mte_probe(env, mtedesc, addr)) {
+                if (mtedesc && info.tagged && !mte_probe(env, mtedesc, addr)) {
                     goto fault;
                 }
 
@@ -XXX,XX +XXX,XX @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
                                          info.attrs, BP_MEM_WRITE, retaddr);
                 }
 
-                if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) {
+                if (mtedesc && info.tagged) {
                     mte_check(env, mtedesc, addr, retaddr);
                 }
             }
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             res.f.phys_addr &= TARGET_PAGE_MASK;
             address &= TARGET_PAGE_MASK;
         }
-        /* Notice and record tagged memory. */
-        if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
-            arm_tlb_mte_tagged(&res.f.attrs) = true;
-        }
 
         res.f.pte_attrs = res.cacheattrs.attrs;
         res.f.shareability = res.cacheattrs.shareability;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit.
In is_guarded_page, use probe_access_full instead of just guessing
that the tlb entry is still present.  Also handles the FIXME about
executing from device memory.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu-param.h     |  9 +++++----
 target/arm/cpu.h           | 13 -------------
 target/arm/internals.h     |  1 +
 target/arm/ptw.c           |  7 ++++---
 target/arm/translate-a64.c | 21 ++++++++++-----------
 5 files changed, 20 insertions(+), 31 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
  *
  * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2].
  * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format.
- * For shareability, as in the SH field of the VMSAv8-64 PTEs.
+ * For shareability and guarded, as in the SH and GP fields respectively
+ * of the VMSAv8-64 PTEs.
  */
 # define TARGET_PAGE_ENTRY_EXTRA  \
-     uint8_t pte_attrs;           \
-     uint8_t shareability;
-
+    uint8_t pte_attrs;            \
+    uint8_t shareability;         \
+    bool guarded;
 #endif
 
 #define NB_MMU_MODES 8
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
 /* Shared between translate-sve.c and sve_helper.c.  */
 extern const uint64_t pred_esz_masks[5];
 
-/* Helper for the macros below, validating the argument type. */
-static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
-{
-    return x;
-}
-
-/*
- * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
- * Using these should be a bit more self-documenting than using the
- * generic target bits directly.
- */
-#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
-
 /*
  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
  * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
     unsigned int attrs:8;
     unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
     bool is_s2_format:1;
+    bool guarded:1;              /* guarded bit of the v8-64 PTE */
 } ARMCacheAttrs;
 
 /* Fields that are valid upon success. */
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          */
         result->f.attrs.secure = false;
     }
-    /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.  */
-    if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
-        arm_tlb_bti_gp(&result->f.attrs) = true;
+
+    /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB.  */
+    if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
+        result->f.guarded = guarded;
     }
 
     if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
 #ifdef CONFIG_USER_ONLY
     return page_get_flags(addr) & PAGE_BTI;
 #else
+    CPUTLBEntryFull *full;
+    void *host;
     int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
-    unsigned int index = tlb_index(env, mmu_idx, addr);
-    CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
+    int flags;
 
     /*
      * We test this immediately after reading an insn, which means
-     * that any normal page must be in the TLB.  The only exception
-     * would be for executing from flash or device memory, which
-     * does not retain the TLB entry.
-     *
-     * FIXME: Assume false for those, for now.  We could use
-     * arm_cpu_get_phys_page_attrs_debug to re-read the page
-     * table entry even for that case.
+     * that the TLB entry must be present and valid, and thus this
+     * access will never raise an exception.
      */
-    return (tlb_hit(entry->addr_code, addr) &&
-            arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs));
+    flags = probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx,
+                              false, &host, &full, 0);
+    assert(!(flags & TLB_INVALID_MASK));
+
+    return full->guarded;
 #endif
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Not yet used, but add mmu indexes for 1-1 mapping
to physical addresses.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu-param.h |  2 +-
 target/arm/cpu.h       |  7 ++++++-
 target/arm/ptw.c       | 19 +++++++++++++++++--
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
     bool guarded;
 #endif
 
-#define NB_MMU_MODES 8
+#define NB_MMU_MODES 10
 
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  * EL2 EL2&0 +PAN
  * EL2 (aka NS PL2)
  * EL3 (aka S PL1)
+ * Physical (NS & S)
  *
- * for a total of 8 different mmu_idx.
+ * for a total of 10 different mmu_idx.
  *
  * R profile CPUs have an MPU, but can use the same set of MMU indexes
  * as A profile. They only need to distinguish EL0 and EL1 (and
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_E2        = 6 | ARM_MMU_IDX_A,
     ARMMMUIdx_E3        = 7 | ARM_MMU_IDX_A,
 
+    /* TLBs with 1-1 mapping to the physical address spaces. */
+    ARMMMUIdx_Phys_NS   = 8 | ARM_MMU_IDX_A,
+    ARMMMUIdx_Phys_S    = 9 | ARM_MMU_IDX_A,
+
     /*
      * These are not allocated TLBs and are used only for AT system
      * instructions or for the first stage of an S12 page table walk.
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
     case ARMMMUIdx_E3:
         break;
 
+    case ARMMMUIdx_Phys_NS:
+    case ARMMMUIdx_Phys_S:
+        /* No translation for physical address spaces. */
+        return true;
+
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
 {
     uint8_t memattr = 0x00;    /* Device nGnRnE */
     uint8_t shareability = 0;  /* non-sharable */
+    int r_el;
 
-    if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
-        int r_el = regime_el(env, mmu_idx);
+    switch (mmu_idx) {
+    case ARMMMUIdx_Stage2:
+    case ARMMMUIdx_Stage2_S:
+    case ARMMMUIdx_Phys_NS:
+    case ARMMMUIdx_Phys_S:
+        break;
 
+    default:
+        r_el = regime_el(env, mmu_idx);
         if (arm_el_is_aa64(env, r_el)) {
             int pamax = arm_pamax(env_archcpu(env));
             uint64_t tcr = env->cp15.tcr_el[r_el];
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
             shareability = 2; /* outer sharable */
         }
         result->cacheattrs.is_s2_format = false;
+        break;
     }
 
     result->f.phys_addr = address;
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
         is_secure = arm_is_secure_below_el3(env);
         break;
     case ARMMMUIdx_Stage2:
+    case ARMMMUIdx_Phys_NS:
     case ARMMMUIdx_MPrivNegPri:
     case ARMMMUIdx_MUserNegPri:
     case ARMMMUIdx_MPriv:
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
         break;
     case ARMMMUIdx_E3:
     case ARMMMUIdx_Stage2_S:
+    case ARMMMUIdx_Phys_S:
     case ARMMMUIdx_MSPrivNegPri:
     case ARMMMUIdx_MSUserNegPri:
     case ARMMMUIdx_MSPriv:
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb.
Flush the tlb when invalidating stage 1+2 translations.  Re-use
alle1_tlbmask() for other instances of EL1&0 + Stage2.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu-param.h |   2 +-
 target/arm/cpu.h       |  23 ++++---
 target/arm/helper.c    | 151 ++++++++++++++++++++++++++++++-----------
 3 files changed, 127 insertions(+), 49 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
     bool guarded;
 #endif
 
-#define NB_MMU_MODES 10
+#define NB_MMU_MODES 12
 
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  * EL2 (aka NS PL2)
  * EL3 (aka S PL1)
  * Physical (NS & S)
+ * Stage2 (NS & S)
  *
- * for a total of 10 different mmu_idx.
+ * for a total of 12 different mmu_idx.
  *
  * R profile CPUs have an MPU, but can use the same set of MMU indexes
  * as A profile. They only need to distinguish EL0 and EL1 (and
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_Phys_NS   = 8 | ARM_MMU_IDX_A,
     ARMMMUIdx_Phys_S    = 9 | ARM_MMU_IDX_A,
 
+    /*
+     * Used for second stage of an S12 page table walk, or for descriptor
+     * loads during first stage of an S1 page table walk.  Note that both
+     * are in use simultaneously for SecureEL2: the security state for
+     * the S2 ptw is selected by the NS bit from the S1 ptw.
+     */
+    ARMMMUIdx_Stage2    = 10 | ARM_MMU_IDX_A,
+    ARMMMUIdx_Stage2_S  = 11 | ARM_MMU_IDX_A,
+
     /*
      * These are not allocated TLBs and are used only for AT system
      * instructions or for the first stage of an S12 page table walk.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
-    /*
-     * Not allocated a TLB: used only for second stage of an S12 page
-     * table walk, or for descriptor loads during first stage of an S1
-     * page table walk. Note that if we ever want to have a TLB for this
-     * then various TLB flush insns which currently are no-ops or flush
-     * only stage 1 MMU indexes will need to change to flush stage 2.
-     */
-    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
-    ARMMMUIdx_Stage2_S   = 4 | ARM_MMU_IDX_NOTLB,
 
     /*
      * M-profile.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
     TO_CORE_BIT(E20_2),
     TO_CORE_BIT(E20_2_PAN),
     TO_CORE_BIT(E3),
+    TO_CORE_BIT(Stage2),
+    TO_CORE_BIT(Stage2_S),
 
     TO_CORE_BIT(MUser),
     TO_CORE_BIT(MPriv),
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     raw_write(env, ri, value);
 }
 
+static int alle1_tlbmask(CPUARMState *env)
+{
+    /*
+     * Note that the 'ALL' scope must invalidate both stage 1 and
+     * stage 2 translations, whereas most other scopes only invalidate
+     * stage 1 translations.
+     */
+    return (ARMMMUIdxBit_E10_1 |
+            ARMMMUIdxBit_E10_1_PAN |
+            ARMMMUIdxBit_E10_0 |
+            ARMMMUIdxBit_Stage2 |
+            ARMMMUIdxBit_Stage2_S);
+}
+
+
 /* IS variants of TLB operations must affect all cores */
 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t value)
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = env_cpu(env);
 
-    tlb_flush_by_mmuidx(cs,
-                        ARMMMUIdxBit_E10_1 |
-                        ARMMMUIdxBit_E10_1_PAN |
-                        ARMMMUIdxBit_E10_0);
+    tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
 }
 
 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = env_cpu(env);
 
-    tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                        ARMMMUIdxBit_E10_1 |
-                                        ARMMMUIdxBit_E10_1_PAN |
-                                        ARMMMUIdxBit_E10_0);
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env));
 }
 
 
@@ -XXX,XX +XXX,XX @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                              ARMMMUIdxBit_E2);
 }
 
+static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                uint64_t value)
+{
+    CPUState *cs = env_cpu(env);
+    uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12;
+
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
+}
+
+static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                uint64_t value)
+{
+    CPUState *cs = env_cpu(env);
+    uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12;
+
+    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2);
+}
+
 static const ARMCPRegInfo cp_reginfo[] = {
     /* Define the secure and non-secure FCSE identifier CP registers
      * separately because there is no secure bank in V8 (no _EL3).  This allows
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     /*
      * A change in VMID to the stage2 page table (Stage2) invalidates
-     * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
+     * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
      */
     if (raw_read(env, ri) != value) {
-        uint16_t mask = ARMMMUIdxBit_E10_1 |
-                        ARMMMUIdxBit_E10_1_PAN |
-                        ARMMMUIdxBit_E10_0;
-        tlb_flush_by_mmuidx(cs, mask);
+        tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
         raw_write(env, ri, value);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static int alle1_tlbmask(CPUARMState *env)
-{
-    /*
-     * Note that the 'ALL' scope must invalidate both stage 1 and
-     * stage 2 translations, whereas most other scopes only invalidate
-     * stage 1 translations.
-     */
-    return (ARMMMUIdxBit_E10_1 |
-            ARMMMUIdxBit_E10_1_PAN |
-            ARMMMUIdxBit_E10_0);
-}
-
 static int e2_tlbmask(CPUARMState *env)
 {
     return (ARMMMUIdxBit_E20_0 |
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                                   ARMMMUIdxBit_E3, bits);
 }
 
+static int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
+{
+    /*
+     * The MSB of value is the NS field, which only applies if SEL2
+     * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
+     */
+    return (value >= 0
+            && cpu_isar_feature(aa64_sel2, env_archcpu(env))
+            && arm_is_secure_below_el3(env)
+            ? ARMMMUIdxBit_Stage2_S
+            : ARMMMUIdxBit_Stage2);
+}
+
+static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                    uint64_t value)
+{
+    CPUState *cs = env_cpu(env);
+    int mask = ipas2e1_tlbmask(env, value);
+    uint64_t pageaddr = sextract64(value << 12, 0, 56);
+
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+    } else {
+        tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
+    }
+}
+
+static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                      uint64_t value)
+{
+    CPUState *cs = env_cpu(env);
+    int mask = ipas2e1_tlbmask(env, value);
+    uint64_t pageaddr = sextract64(value << 12, 0, 56);
+
+    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+}
+
 #ifdef TARGET_AARCH64
 typedef struct {
     uint64_t base;
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
 
     do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
 }
+
+static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                     uint64_t value)
+{
+    do_rvae_write(env, value, ipas2e1_tlbmask(env, value),
+                  tlb_force_broadcast(env));
+}
+
+static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
+                                       const ARMCPRegInfo *ri,
+                                       uint64_t value)
+{
+    do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true);
+}
 #endif
 
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ipas2e1is_write },
     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ipas2e1is_write },
     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
       .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ipas2e1_write },
     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ipas2e1_write },
     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
       .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBIIPAS2",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
-      .type = ARM_CP_NOP, .access = PL2_W },
+      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .writefn = tlbiipas2_hyp_write },
     { .name = "TLBIIPAS2IS",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-      .type = ARM_CP_NOP, .access = PL2_W },
+      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .writefn = tlbiipas2is_hyp_write },
     { .name = "TLBIIPAS2L",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
-      .type = ARM_CP_NOP, .access = PL2_W },
+      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .writefn = tlbiipas2_hyp_write },
     { .name = "TLBIIPAS2LIS",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
-      .type = ARM_CP_NOP, .access = PL2_W },
+      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .writefn = tlbiipas2is_hyp_write },
     /* 32 bit cache operations */
     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ripas2e1is_write },
     { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ripas2e1is_write },
     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
       .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
-      .access = PL2_W, .type = ARM_CP_NOP },
-   { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ripas2e1_write },
+    { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
-      .access = PL2_W, .type = ARM_CP_NOP },
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbi_aa64_ripas2e1_write },
    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
       .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Compare only the VMID field when considering whether we need to flush.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
      * A change in VMID to the stage2 page table (Stage2) invalidates
      * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
      */
-    if (raw_read(env, ri) != value) {
+    if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
         tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
-        raw_write(env, ri, value);
     }
+    raw_write(env, ri, value);
 }
 
 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Consolidate most of the inputs and outputs of S1_ptw_translate
into a single structure.  Plumb this through arm_ld*_ptw from
the controlling get_phys_addr_* routine.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 140 ++++++++++++++++++++++++++---------------------
 1 file changed, 79 insertions(+), 61 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@
 #include "idau.h"
 
 
-static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
-                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                               bool is_secure, bool s1_is_el0,
+typedef struct S1Translate {
+    ARMMMUIdx in_mmu_idx;
+    bool in_secure;
+    bool out_secure;
+    hwaddr out_phys;
+} S1Translate;
+
+static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
+                               uint64_t address,
+                               MMUAccessType access_type, bool s1_is_el0,
                                GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
     __attribute__((nonnull));
 
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
 }
 
 /* Translate a S1 pagetable walk through S2 if needed.  */
-static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-                               hwaddr addr, bool *is_secure_ptr,
-                               ARMMMUFaultInfo *fi)
+static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
+                             hwaddr addr, ARMMMUFaultInfo *fi)
 {
-    bool is_secure = *is_secure_ptr;
+    bool is_secure = ptw->in_secure;
     ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
 
-    if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
+    if (arm_mmu_idx_is_stage1_of_2(ptw->in_mmu_idx) &&
         !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
         GetPhysAddrResult s2 = {};
+        S1Translate s2ptw = {
+            .in_mmu_idx = s2_mmu_idx,
+            .in_secure = is_secure,
+        };
         uint64_t hcr;
         int ret;
 
-        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
-                                 is_secure, false, &s2, fi);
+        ret = get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
+                                 false, &s2, fi);
         if (ret) {
             assert(fi->type != ARMFault_None);
             fi->s2addr = addr;
             fi->stage2 = true;
             fi->s1ptw = true;
             fi->s1ns = !is_secure;
-            return ~0;
+            return false;
         }
 
         hcr = arm_hcr_el2_eff_secstate(env, is_secure);
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             fi->stage2 = true;
             fi->s1ptw = true;
             fi->s1ns = !is_secure;
-            return ~0;
+            return false;
         }
 
         if (arm_is_secure_below_el3(env)) {
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             } else {
                 is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
             }
-            *is_secure_ptr = is_secure;
         } else {
             assert(!is_secure);
         }
 
         addr = s2.f.phys_addr;
     }
-    return addr;
+
+    ptw->out_secure = is_secure;
+    ptw->out_phys = addr;
+    return true;
 }
 
 /* All loads done in the course of a page table walk go through here. */
-static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
-                            ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
+static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+                            ARMMMUFaultInfo *fi)
 {
     CPUState *cs = env_cpu(env);
     MemTxAttrs attrs = {};
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
     AddressSpace *as;
     uint32_t data;
 
-    addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
-    attrs.secure = is_secure;
-    as = arm_addressspace(cs, attrs);
-    if (fi->s1ptw) {
+    if (!S1_ptw_translate(env, ptw, addr, fi)) {
         return 0;
     }
-    if (regime_translation_big_endian(env, mmu_idx)) {
+    addr = ptw->out_phys;
+    attrs.secure = ptw->out_secure;
+    as = arm_addressspace(cs, attrs);
+    if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
         data = address_space_ldl_be(as, addr, attrs, &result);
     } else {
         data = address_space_ldl_le(as, addr, attrs, &result);
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
     return 0;
 }
 
-static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
-                            ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
+static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+                            ARMMMUFaultInfo *fi)
 {
     CPUState *cs = env_cpu(env);
     MemTxAttrs attrs = {};
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
     AddressSpace *as;
     uint64_t data;
 
-    addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
-    attrs.secure = is_secure;
-    as = arm_addressspace(cs, attrs);
-    if (fi->s1ptw) {
+    if (!S1_ptw_translate(env, ptw, addr, fi)) {
         return 0;
     }
-    if (regime_translation_big_endian(env, mmu_idx)) {
+    addr = ptw->out_phys;
+    attrs.secure = ptw->out_secure;
+    as = arm_addressspace(cs, attrs);
+    if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
         data = address_space_ldq_be(as, addr, attrs, &result);
     } else {
         data = address_space_ldq_le(as, addr, attrs, &result);
@@ -XXX,XX +XXX,XX @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
 }
 
-static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
-                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                             bool is_secure, GetPhysAddrResult *result,
-                             ARMMMUFaultInfo *fi)
+static bool get_phys_addr_v5(CPUARMState *env, S1Translate *ptw,
+                             uint32_t address, MMUAccessType access_type,
+                             GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 {
     int level = 1;
     uint32_t table;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
 
     /* Pagetable walk.  */
     /* Lookup l1 descriptor.  */
-    if (!get_level1_table_address(env, mmu_idx, &table, address)) {
+    if (!get_level1_table_address(env, ptw->in_mmu_idx, &table, address)) {
         /* Section translation fault if page walk is disabled by PD0 or PD1 */
         fi->type = ARMFault_Translation;
         goto do_fault;
     }
-    desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
+    desc = arm_ldl_ptw(env, ptw, table, fi);
     if (fi->type != ARMFault_None) {
         goto do_fault;
     }
     type = (desc & 3);
     domain = (desc >> 5) & 0x0f;
-    if (regime_el(env, mmu_idx) == 1) {
+    if (regime_el(env, ptw->in_mmu_idx) == 1) {
         dacr = env->cp15.dacr_ns;
     } else {
         dacr = env->cp15.dacr_s;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
             /* Fine pagetable.  */
             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
         }
-        desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
+        desc = arm_ldl_ptw(env, ptw, table, fi);
         if (fi->type != ARMFault_None) {
             goto do_fault;
         }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
             g_assert_not_reached();
         }
     }
-    result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+    result->f.prot = ap_to_rw_prot(env, ptw->in_mmu_idx, ap, domain_prot);
     result->f.prot |= result->f.prot ? PAGE_EXEC : 0;
     if (!(result->f.prot & (1 << access_type))) {
         /* Access permission fault.  */
@@ -XXX,XX +XXX,XX @@ do_fault:
     return true;
 }
 
-static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
-                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                             bool is_secure, GetPhysAddrResult *result,
-                             ARMMMUFaultInfo *fi)
+static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
+                             uint32_t address, MMUAccessType access_type,
+                             GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 {
     ARMCPU *cpu = env_archcpu(env);
+    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
     int level = 1;
     uint32_t table;
     uint32_t desc;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         fi->type = ARMFault_Translation;
         goto do_fault;
     }
-    desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
+    desc = arm_ldl_ptw(env, ptw, table, fi);
     if (fi->type != ARMFault_None) {
         goto do_fault;
     }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         ns = extract32(desc, 3, 1);
         /* Lookup l2 entry.  */
         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
-        desc = arm_ldl_ptw(env, table, is_secure, mmu_idx, fi);
+        desc = arm_ldl_ptw(env, ptw, table, fi);
         if (fi->type != ARMFault_None) {
             goto do_fault;
         }
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
  * the WnR bit is never set (the caller must do this).
  *
  * @env: CPUARMState
+ * @ptw: Current and next stage parameters for the walk.
  * @address: virtual address to get physical address for
  * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
- * @mmu_idx: MMU index indicating required translation regime
- * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page
- *             table walk), must be true if this is stage 2 of a stage 1+2
+ * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
+ *             (so this is a stage 2 page table walk),
+ *             must be true if this is stage 2 of a stage 1+2
  *             walk for an EL0 access. If @mmu_idx is anything else,
  *             @s1_is_el0 is ignored.
  * @result: set on translation success,
  * @fi: set to fault info if the translation fails
  */
-static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
-                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                               bool is_secure, bool s1_is_el0,
+static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
+                               uint64_t address,
+                               MMUAccessType access_type, bool s1_is_el0,
                                GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
 {
     ARMCPU *cpu = env_archcpu(env);
+    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
+    bool is_secure = ptw->in_secure;
     /* Read an LPAE long-descriptor translation table. */
     ARMFaultType fault_type = ARMFault_Translation;
     uint32_t level;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         descaddr |= (address >> (stride * (4 - level))) & indexmask;
         descaddr &= ~7ULL;
         nstable = extract32(tableattrs, 4, 1);
-        descriptor = arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, fi);
+        ptw->in_secure = !nstable;
+        descriptor = arm_ldq_ptw(env, ptw, descaddr, fi);
         if (fi->type != ARMFault_None) {
             goto do_fault;
         }
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                                ARMMMUFaultInfo *fi)
 {
     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
+    S1Translate ptw;
 
     if (mmu_idx != s1_mmu_idx) {
         /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             int ret;
             bool ipa_secure, s2walk_secure;
             ARMCacheAttrs cacheattrs1;
-            ARMMMUIdx s2_mmu_idx;
             bool is_el0;
             uint64_t hcr;
 
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                 s2walk_secure = false;
             }
 
-            s2_mmu_idx = (s2walk_secure
-                          ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
+            ptw.in_mmu_idx =
+                s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+            ptw.in_secure = s2walk_secure;
             is_el0 = mmu_idx == ARMMMUIdx_E10_0;
 
             /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             cacheattrs1 = result->cacheattrs;
             memset(result, 0, sizeof(*result));
 
-            ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
-                                     s2walk_secure, is_el0, result, fi);
+            ret = get_phys_addr_lpae(env, &ptw, ipa, access_type,
+                                     is_el0, result, fi);
             fi->s2addr = ipa;
 
             /* Combine the S1 and S2 perms.  */
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
         return get_phys_addr_disabled(env, address, access_type, mmu_idx,
                                       is_secure, result, fi);
     }
+
+    ptw.in_mmu_idx = mmu_idx;
+    ptw.in_secure = is_secure;
+
     if (regime_using_lpae_format(env, mmu_idx)) {
-        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
-                                  is_secure, false, result, fi);
+        return get_phys_addr_lpae(env, &ptw, address, access_type, false,
+                                  result, fi);
     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
-        return get_phys_addr_v6(env, address, access_type, mmu_idx,
-                                is_secure, result, fi);
+        return get_phys_addr_v6(env, &ptw, address, access_type, result, fi);
     } else {
-        return get_phys_addr_v5(env, address, access_type, mmu_idx,
-                                is_secure, result, fi);
+        return get_phys_addr_v5(env, &ptw, address, access_type, result, fi);
     }
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Before using softmmu page tables for the ptw, plumb down
a debug parameter so that we can query page table entries
from gdbstub without modifying cpu state.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 55 ++++++++++++++++++++++++++++++++----------------
 1 file changed, 37 insertions(+), 18 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@
 typedef struct S1Translate {
     ARMMMUIdx in_mmu_idx;
     bool in_secure;
+    bool in_debug;
     bool out_secure;
     hwaddr out_phys;
 } S1Translate;
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
         S1Translate s2ptw = {
             .in_mmu_idx = s2_mmu_idx,
             .in_secure = is_secure,
+            .in_debug = ptw->in_debug,
         };
         uint64_t hcr;
         int ret;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
     return 0;
 }
 
-bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
-                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                               bool is_secure, GetPhysAddrResult *result,
-                               ARMMMUFaultInfo *fi)
+static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
+                                      target_ulong address,
+                                      MMUAccessType access_type,
+                                      GetPhysAddrResult *result,
+                                      ARMMMUFaultInfo *fi)
 {
+    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
-    S1Translate ptw;
+    bool is_secure = ptw->in_secure;
 
     if (mmu_idx != s1_mmu_idx) {
         /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             bool is_el0;
             uint64_t hcr;
 
-            ret = get_phys_addr_with_secure(env, address, access_type,
-                                            s1_mmu_idx, is_secure, result, fi);
+            ptw->in_mmu_idx = s1_mmu_idx;
+            ret = get_phys_addr_with_struct(env, ptw, address, access_type,
+                                            result, fi);
 
             /* If S1 fails or S2 is disabled, return early.  */
             if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                 s2walk_secure = false;
             }
 
-            ptw.in_mmu_idx =
+            ptw->in_mmu_idx =
                 s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
-            ptw.in_secure = s2walk_secure;
+            ptw->in_secure = s2walk_secure;
             is_el0 = mmu_idx == ARMMMUIdx_E10_0;
 
             /*
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
             cacheattrs1 = result->cacheattrs;
             memset(result, 0, sizeof(*result));
 
-            ret = get_phys_addr_lpae(env, &ptw, ipa, access_type,
+            ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
                                      is_el0, result, fi);
             fi->s2addr = ipa;
 
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
                                       is_secure, result, fi);
     }
 
-    ptw.in_mmu_idx = mmu_idx;
-    ptw.in_secure = is_secure;
-
     if (regime_using_lpae_format(env, mmu_idx)) {
-        return get_phys_addr_lpae(env, &ptw, address, access_type, false,
+        return get_phys_addr_lpae(env, ptw, address, access_type, false,
                                   result, fi);
     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
-        return get_phys_addr_v6(env, &ptw, address, access_type, result, fi);
+        return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
     } else {
-        return get_phys_addr_v5(env, &ptw, address, access_type, result, fi);
+        return get_phys_addr_v5(env, ptw, address, access_type, result, fi);
     }
 }
 
+bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
+                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                               bool is_secure, GetPhysAddrResult *result,
+                               ARMMMUFaultInfo *fi)
+{
+    S1Translate ptw = {
+        .in_mmu_idx = mmu_idx,
+        .in_secure = is_secure,
+    };
+    return get_phys_addr_with_struct(env, &ptw, address, access_type,
+                                     result, fi);
+}
+
 bool get_phys_addr(CPUARMState *env, target_ulong address,
                    MMUAccessType access_type, ARMMMUIdx mmu_idx,
                    GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
+    S1Translate ptw = {
+        .in_mmu_idx = arm_mmu_idx(env),
+        .in_secure = arm_is_secure(env),
+        .in_debug = true,
+    };
     GetPhysAddrResult res = {};
     ARMMMUFaultInfo fi = {};
-    ARMMMUIdx mmu_idx = arm_mmu_idx(env);
     bool ret;
 
-    ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
+    ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi);
     *attrs = res.f.attrs;
 
     if (ret) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and
arm_ldq_ptw.  Use probe_access_full to find the host address,
and if so use a host load.  If the probe fails, we've got our
fault info already.  On the off chance that page tables are not
in RAM, continue to use the address_space_ld* functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h        |   5 +
 target/arm/ptw.c        | 196 +++++++++++++++++++++++++---------------
 target/arm/tlb_helper.c |  17 +++-
 3 files changed, 144 insertions(+), 74 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
     target_ulong flags2;
 } CPUARMTBFlags;
 
+typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
+
 typedef struct CPUArchState {
     /* Regs for current mode.  */
     uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
+    /* Optional fault info across tlb lookup. */
+    ARMMMUFaultInfo *tlb_fi;
+
     /* Fields up to this point are cleared by a CPU reset */
     struct {} end_reset_fields;
 
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qemu/log.h"
 #include "qemu/range.h"
+#include "exec/exec-all.h"
 #include "cpu.h"
 #include "internals.h"
 #include "idau.h"
@@ -XXX,XX +XXX,XX @@ typedef struct S1Translate {
     bool out_secure;
     bool out_be;
     hwaddr out_phys;
+    void *out_host;
 } S1Translate;
 
 static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
 }
 
-static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
+static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
 {
     /*
      * For an S1 page table walk, the stage 1 attributes are always
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
      * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
      * when cacheattrs.attrs bit [2] is 0.
      */
-    assert(cacheattrs.is_s2_format);
     if (hcr & HCR_FWB) {
-        return (cacheattrs.attrs & 0x4) == 0;
+        return (attrs & 0x4) == 0;
     } else {
-        return (cacheattrs.attrs & 0xc) == 0;
+        return (attrs & 0xc) == 0;
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
                              hwaddr addr, ARMMMUFaultInfo *fi)
 {
     bool is_secure = ptw->in_secure;
+    ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
     ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+    bool s2_phys = false;
+    uint8_t pte_attrs;
+    bool pte_secure;
 
-    if (arm_mmu_idx_is_stage1_of_2(ptw->in_mmu_idx) &&
-        !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
-        GetPhysAddrResult s2 = {};
-        S1Translate s2ptw = {
-            .in_mmu_idx = s2_mmu_idx,
-            .in_secure = is_secure,
-            .in_debug = ptw->in_debug,
-        };
-        uint64_t hcr;
-        int ret;
+    if (!arm_mmu_idx_is_stage1_of_2(mmu_idx)
+        || regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
+        s2_mmu_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS;
+        s2_phys = true;
+    }
 
-        ret = get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
-                                 false, &s2, fi);
-        if (ret) {
-            assert(fi->type != ARMFault_None);
-            fi->s2addr = addr;
-            fi->stage2 = true;
-            fi->s1ptw = true;
-            fi->s1ns = !is_secure;
-            return false;
+    if (unlikely(ptw->in_debug)) {
+        /*
+         * From gdbstub, do not use softmmu so that we don't modify the
+         * state of the cpu at all, including softmmu tlb contents.
+         */
+        if (s2_phys) {
+            ptw->out_phys = addr;
+            pte_attrs = 0;
+            pte_secure = is_secure;
+        } else {
+            S1Translate s2ptw = {
+                .in_mmu_idx = s2_mmu_idx,
+                .in_secure = is_secure,
+                .in_debug = true,
+            };
+            GetPhysAddrResult s2 = { };
+            if (!get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
+                                    false, &s2, fi)) {
+                goto fail;
+            }
+            ptw->out_phys = s2.f.phys_addr;
+            pte_attrs = s2.cacheattrs.attrs;
+            pte_secure = s2.f.attrs.secure;
         }
+        ptw->out_host = NULL;
+    } else {
+        CPUTLBEntryFull *full;
+        int flags;
 
-        hcr = arm_hcr_el2_eff_secstate(env, is_secure);
-        if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
+        env->tlb_fi = fi;
+        flags = probe_access_full(env, addr, MMU_DATA_LOAD,
+                                  arm_to_core_mmu_idx(s2_mmu_idx),
+                                  true, &ptw->out_host, &full, 0);
+        env->tlb_fi = NULL;
+
+        if (unlikely(flags & TLB_INVALID_MASK)) {
+            goto fail;
+        }
+        ptw->out_phys = full->phys_addr;
+        pte_attrs = full->pte_attrs;
+        pte_secure = full->attrs.secure;
+    }
+
+    if (!s2_phys) {
+        uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+
+        if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) {
             /*
              * PTW set and S1 walk touched S2 Device memory:
              * generate Permission fault.
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
             fi->s1ns = !is_secure;
             return false;
         }
-
-        if (arm_is_secure_below_el3(env)) {
-            /* Check if page table walk is to secure or non-secure PA space. */
-            if (is_secure) {
-                is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
-            } else {
-                is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
-            }
-        } else {
-            assert(!is_secure);
-        }
-
-        addr = s2.f.phys_addr;
     }
 
-    ptw->out_secure = is_secure;
-    ptw->out_phys = addr;
-    ptw->out_be = regime_translation_big_endian(env, ptw->in_mmu_idx);
+    /* Check if page table walk is to secure or non-secure PA space. */
+    ptw->out_secure = (is_secure
+                       && !(pte_secure
+                            ? env->cp15.vstcr_el2 & VSTCR_SW
+                            : env->cp15.vtcr_el2 & VTCR_NSW));
+    ptw->out_be = regime_translation_big_endian(env, mmu_idx);
     return true;
+
+ fail:
+    assert(fi->type != ARMFault_None);
+    fi->s2addr = addr;
+    fi->stage2 = true;
+    fi->s1ptw = true;
+    fi->s1ns = !is_secure;
+    return false;
 }
 
 /* All loads done in the course of a page table walk go through here. */
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
                             ARMMMUFaultInfo *fi)
 {
     CPUState *cs = env_cpu(env);
-    MemTxAttrs attrs = {};
-    MemTxResult result = MEMTX_OK;
-    AddressSpace *as;
     uint32_t data;
 
     if (!S1_ptw_translate(env, ptw, addr, fi)) {
+        /* Failure. */
+        assert(fi->s1ptw);
         return 0;
     }
-    addr = ptw->out_phys;
-    attrs.secure = ptw->out_secure;
-    as = arm_addressspace(cs, attrs);
-    if (ptw->out_be) {
-        data = address_space_ldl_be(as, addr, attrs, &result);
+
+    if (likely(ptw->out_host)) {
+        /* Page tables are in RAM, and we have the host address. */
+        if (ptw->out_be) {
+            data = ldl_be_p(ptw->out_host);
+        } else {
+            data = ldl_le_p(ptw->out_host);
+        }
     } else {
-        data = address_space_ldl_le(as, addr, attrs, &result);
+        /* Page tables are in MMIO. */
+        MemTxAttrs attrs = { .secure = ptw->out_secure };
+        AddressSpace *as = arm_addressspace(cs, attrs);
+        MemTxResult result = MEMTX_OK;
+
+        if (ptw->out_be) {
+            data = address_space_ldl_be(as, ptw->out_phys, attrs, &result);
+        } else {
+            data = address_space_ldl_le(as, ptw->out_phys, attrs, &result);
+        }
+        if (unlikely(result != MEMTX_OK)) {
+            fi->type = ARMFault_SyncExternalOnWalk;
+            fi->ea = arm_extabort_type(result);
+            return 0;
+        }
     }
-    if (result == MEMTX_OK) {
-        return data;
-    }
-    fi->type = ARMFault_SyncExternalOnWalk;
-    fi->ea = arm_extabort_type(result);
-    return 0;
+    return data;
 }
 
 static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
                             ARMMMUFaultInfo *fi)
 {
     CPUState *cs = env_cpu(env);
-    MemTxAttrs attrs = {};
-    MemTxResult result = MEMTX_OK;
-    AddressSpace *as;
     uint64_t data;
 
     if (!S1_ptw_translate(env, ptw, addr, fi)) {
+        /* Failure. */
+        assert(fi->s1ptw);
         return 0;
     }
-    addr = ptw->out_phys;
-    attrs.secure = ptw->out_secure;
-    as = arm_addressspace(cs, attrs);
-    if (ptw->out_be) {
-        data = address_space_ldq_be(as, addr, attrs, &result);
+
+    if (likely(ptw->out_host)) {
+        /* Page tables are in RAM, and we have the host address. */
+        if (ptw->out_be) {
+            data = ldq_be_p(ptw->out_host);
+        } else {
+            data = ldq_le_p(ptw->out_host);
+        }
     } else {
-        data = address_space_ldq_le(as, addr, attrs, &result);
+        /* Page tables are in MMIO. */
+        MemTxAttrs attrs = { .secure = ptw->out_secure };
+        AddressSpace *as = arm_addressspace(cs, attrs);
+        MemTxResult result = MEMTX_OK;
+
+        if (ptw->out_be) {
+            data = address_space_ldq_be(as, ptw->out_phys, attrs, &result);
+        } else {
+            data = address_space_ldq_le(as, ptw->out_phys, attrs, &result);
+        }
+        if (unlikely(result != MEMTX_OK)) {
+            fi->type = ARMFault_SyncExternalOnWalk;
+            fi->ea = arm_extabort_type(result);
+            return 0;
+        }
     }
-    if (result == MEMTX_OK) {
-        return data;
-    }
-    fi->type = ARMFault_SyncExternalOnWalk;
-    fi->ea = arm_extabort_type(result);
-    return 0;
+    return data;
 }
 
 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       bool probe, uintptr_t retaddr)
 {
     ARMCPU *cpu = ARM_CPU(cs);
-    ARMMMUFaultInfo fi = {};
     GetPhysAddrResult res = {};
+    ARMMMUFaultInfo local_fi, *fi;
     int ret;
 
+    /*
+     * Allow S1_ptw_translate to see any fault generated here.
+     * Since this may recurse, read and clear.
+     */
+    fi = cpu->env.tlb_fi;
+    if (fi) {
+        cpu->env.tlb_fi = NULL;
+    } else {
+        fi = memset(&local_fi, 0, sizeof(local_fi));
+    }
+
     /*
      * Walk the page table and (if the mapping exists) add the page
      * to the TLB.  On success, return true.  Otherwise, if probing,
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      */
     ret = get_phys_addr(&cpu->env, address, access_type,
                         core_to_arm_mmu_idx(&cpu->env, mmu_idx),
-                        &res, &fi);
+                        &res, fi);
     if (likely(!ret)) {
         /*
          * Map a single [sub]page. Regions smaller than our declared
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     } else {
         /* now we have a real cpu fault */
         cpu_restore_state(cs, retaddr, true);
-        arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
+        arm_deliver_fault(cpu, address, access_type, mmu_idx, fi);
     }
 }
 #else
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 191 +++++++++++++++++++++++++----------------------
 1 file changed, 100 insertions(+), 91 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
                                GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
     __attribute__((nonnull));
 
+static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
+                                      target_ulong address,
+                                      MMUAccessType access_type,
+                                      GetPhysAddrResult *result,
+                                      ARMMMUFaultInfo *fi)
+    __attribute__((nonnull));
+
 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
 static const uint8_t pamax_map[] = {
     [0] = 32,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
     return 0;
 }
 
+static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
+                                   target_ulong address,
+                                   MMUAccessType access_type,
+                                   GetPhysAddrResult *result,
+                                   ARMMMUFaultInfo *fi)
+{
+    hwaddr ipa;
+    int s1_prot;
+    int ret;
+    bool is_secure = ptw->in_secure;
+    bool ipa_secure, s2walk_secure;
+    ARMCacheAttrs cacheattrs1;
+    bool is_el0;
+    uint64_t hcr;
+
+    ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi);
+
+    /* If S1 fails or S2 is disabled, return early.  */
+    if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) {
+        return ret;
+    }
+
+    ipa = result->f.phys_addr;
+    ipa_secure = result->f.attrs.secure;
+    if (is_secure) {
+        /* Select TCR based on the NS bit from the S1 walk. */
+        s2walk_secure = !(ipa_secure
+                          ? env->cp15.vstcr_el2 & VSTCR_SW
+                          : env->cp15.vtcr_el2 & VTCR_NSW);
+    } else {
+        assert(!ipa_secure);
+        s2walk_secure = false;
+    }
+
+    is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
+    ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
+    ptw->in_secure = s2walk_secure;
+
+    /*
+     * S1 is done, now do S2 translation.
+     * Save the stage1 results so that we may merge prot and cacheattrs later.
+     */
+    s1_prot = result->f.prot;
+    cacheattrs1 = result->cacheattrs;
+    memset(result, 0, sizeof(*result));
+
+    ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
+    fi->s2addr = ipa;
+
+    /* Combine the S1 and S2 perms.  */
+    result->f.prot &= s1_prot;
+
+    /* If S2 fails, return early.  */
+    if (ret) {
+        return ret;
+    }
+
+    /* Combine the S1 and S2 cache attributes. */
+    hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+    if (hcr & HCR_DC) {
+        /*
+         * HCR.DC forces the first stage attributes to
+         *  Normal Non-Shareable,
+         *  Inner Write-Back Read-Allocate Write-Allocate,
+         *  Outer Write-Back Read-Allocate Write-Allocate.
+         * Do not overwrite Tagged within attrs.
+         */
+        if (cacheattrs1.attrs != 0xf0) {
+            cacheattrs1.attrs = 0xff;
+        }
+        cacheattrs1.shareability = 0;
+    }
+    result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
+                                            result->cacheattrs);
+
+    /*
+     * Check if IPA translates to secure or non-secure PA space.
+     * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
+     */
+    result->f.attrs.secure =
+        (is_secure
+         && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
+         && (ipa_secure
+             || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
+
+    return 0;
+}
+
 static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
                                       target_ulong address,
                                       MMUAccessType access_type,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
     if (mmu_idx != s1_mmu_idx) {
         /*
          * Call ourselves recursively to do the stage 1 and then stage 2
-         * translations if mmu_idx is a two-stage regime.
+         * translations if mmu_idx is a two-stage regime, and EL2 present.
+         * Otherwise, a stage1+stage2 translation is just stage 1.
          */
+        ptw->in_mmu_idx = mmu_idx = s1_mmu_idx;
         if (arm_feature(env, ARM_FEATURE_EL2)) {
-            hwaddr ipa;
-            int s1_prot;
-            int ret;
-            bool ipa_secure, s2walk_secure;
-            ARMCacheAttrs cacheattrs1;
-            bool is_el0;
-            uint64_t hcr;
-
-            ptw->in_mmu_idx = s1_mmu_idx;
-            ret = get_phys_addr_with_struct(env, ptw, address, access_type,
-                                            result, fi);
-
-            /* If S1 fails or S2 is disabled, return early.  */
-            if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
-                                                   is_secure)) {
-                return ret;
-            }
-
-            ipa = result->f.phys_addr;
-            ipa_secure = result->f.attrs.secure;
-            if (is_secure) {
-                /* Select TCR based on the NS bit from the S1 walk. */
-                s2walk_secure = !(ipa_secure
-                                  ? env->cp15.vstcr_el2 & VSTCR_SW
-                                  : env->cp15.vtcr_el2 & VTCR_NSW);
-            } else {
-                assert(!ipa_secure);
-                s2walk_secure = false;
-            }
-
-            ptw->in_mmu_idx =
-                s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
-            ptw->in_secure = s2walk_secure;
-            is_el0 = mmu_idx == ARMMMUIdx_E10_0;
-
-            /*
-             * S1 is done, now do S2 translation.
-             * Save the stage1 results so that we may merge
-             * prot and cacheattrs later.
-             */
-            s1_prot = result->f.prot;
-            cacheattrs1 = result->cacheattrs;
-            memset(result, 0, sizeof(*result));
-
-            ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
-                                     is_el0, result, fi);
-            fi->s2addr = ipa;
-
-            /* Combine the S1 and S2 perms.  */
-            result->f.prot &= s1_prot;
-
-            /* If S2 fails, return early.  */
-            if (ret) {
-                return ret;
-            }
-
-            /* Combine the S1 and S2 cache attributes. */
-            hcr = arm_hcr_el2_eff_secstate(env, is_secure);
-            if (hcr & HCR_DC) {
-                /*
-                 * HCR.DC forces the first stage attributes to
-                 *  Normal Non-Shareable,
-                 *  Inner Write-Back Read-Allocate Write-Allocate,
-                 *  Outer Write-Back Read-Allocate Write-Allocate.
-                 * Do not overwrite Tagged within attrs.
-                 */
-                if (cacheattrs1.attrs != 0xf0) {
-                    cacheattrs1.attrs = 0xff;
-                }
-                cacheattrs1.shareability = 0;
-            }
-            result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
-                                                    result->cacheattrs);
-
-            /*
-             * Check if IPA translates to secure or non-secure PA space.
-             * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
-             */
-            result->f.attrs.secure =
-                (is_secure
-                 && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
-                 && (ipa_secure
-                     || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
-
-            return 0;
-        } else {
-            /*
-             * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
-             */
-            mmu_idx = stage_1_mmu_idx(mmu_idx);
+            return get_phys_addr_twostage(env, ptw, address, access_type,
+                                          result, fi);
         }
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The return type of the functions is already bool, but in a few
instances we used an integer type with the return statement.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
     result->f.lg_page_size = TARGET_PAGE_BITS;
     result->cacheattrs.shareability = shareability;
     result->cacheattrs.attrs = memattr;
-    return 0;
+    return false;
 }
 
 static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
 {
     hwaddr ipa;
     int s1_prot;
-    int ret;
     bool is_secure = ptw->in_secure;
-    bool ipa_secure, s2walk_secure;
+    bool ret, ipa_secure, s2walk_secure;
     ARMCacheAttrs cacheattrs1;
     bool is_el0;
     uint64_t hcr;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
          && (ipa_secure
              || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
 
-    return 0;
+    return false;
 }
 
 static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

A simple helper to retrieve the length of the current insn.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h     | 5 +++++
 target/arm/translate-vfp.c | 2 +-
 target/arm/translate.c     | 5 ++---
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
     s->insn_start = NULL;
 }
 
+static inline int curr_insn_len(DisasContext *s)
+{
+    return s->base.pc_next - s->pc_curr;
+}
+
 /* is_jmp field values */
 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 /* CPU state was modified dynamically; exit to main loop for interrupts. */
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
     if (s->sme_trap_nonstreaming) {
         gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
                            syn_smetrap(SME_ET_Streaming,
-                                       s->base.pc_next - s->pc_curr == 2));
+                                       curr_insn_len(s) == 2));
         return false;
     }
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
     /* ISS not valid if writeback */
     if (p && !w) {
         ret = rd;
-        if (s->base.pc_next - s->pc_curr == 2) {
+        if (curr_insn_len(s) == 2) {
             ret |= ISSIs16Bit;
         }
     } else {
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             /* nothing more to generate */
             break;
         case DISAS_WFI:
-            gen_helper_wfi(cpu_env,
-                           tcg_constant_i32(dc->base.pc_next - dc->pc_curr));
+            gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc)));
             /*
              * The helper doesn't necessarily throw an exception, but we
              * must go back to the main loop to check for interrupts anyway.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------
 target/arm/translate.c     | 10 ++++++----
 2 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
     return translator_use_goto_tb(&s->base, dest);
 }
 
-static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
+static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
 {
+    uint64_t dest = s->pc_curr + diff;
+
     if (use_goto_tb(s, dest)) {
         tcg_gen_goto_tb(n);
         gen_a64_set_pc_im(dest);
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
  */
 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
 {
-    uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
+    int64_t diff = sextract32(insn, 0, 26) * 4;
 
     if (insn & (1U << 31)) {
         /* BL Branch with link */
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
 
     /* B Branch / BL Branch with link */
     reset_btype(s);
-    gen_goto_tb(s, 0, addr);
+    gen_goto_tb(s, 0, diff);
 }
 
 /* Compare and branch (immediate)
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
 {
     unsigned int sf, op, rt;
-    uint64_t addr;
+    int64_t diff;
     TCGLabel *label_match;
     TCGv_i64 tcg_cmp;
 
     sf = extract32(insn, 31, 1);
     op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
     rt = extract32(insn, 0, 5);
-    addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
+    diff = sextract32(insn, 5, 19) * 4;
 
     tcg_cmp = read_cpu_reg(s, rt, sf);
     label_match = gen_new_label();
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
     tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
                         tcg_cmp, 0, label_match);
 
-    gen_goto_tb(s, 0, s->base.pc_next);
+    gen_goto_tb(s, 0, 4);
     gen_set_label(label_match);
-    gen_goto_tb(s, 1, addr);
+    gen_goto_tb(s, 1, diff);
 }
 
 /* Test and branch (immediate)
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
 {
     unsigned int bit_pos, op, rt;
-    uint64_t addr;
+    int64_t diff;
     TCGLabel *label_match;
     TCGv_i64 tcg_cmp;
 
     bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
     op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
-    addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
+    diff = sextract32(insn, 5, 14) * 4;
     rt = extract32(insn, 0, 5);
 
     tcg_cmp = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
     tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
                         tcg_cmp, 0, label_match);
     tcg_temp_free_i64(tcg_cmp);
-    gen_goto_tb(s, 0, s->base.pc_next);
+    gen_goto_tb(s, 0, 4);
     gen_set_label(label_match);
-    gen_goto_tb(s, 1, addr);
+    gen_goto_tb(s, 1, diff);
 }
 
 /* Conditional branch (immediate)
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
 {
     unsigned int cond;
-    uint64_t addr;
+    int64_t diff;
 
     if ((insn & (1 << 4)) || (insn & (1 << 24))) {
         unallocated_encoding(s);
         return;
     }
-    addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
+    diff = sextract32(insn, 5, 19) * 4;
     cond = extract32(insn, 0, 4);
 
     reset_btype(s);
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
         /* genuinely conditional branches */
         TCGLabel *label_match = gen_new_label();
         arm_gen_test_cc(cond, label_match);
-        gen_goto_tb(s, 0, s->base.pc_next);
+        gen_goto_tb(s, 0, 4);
         gen_set_label(label_match);
-        gen_goto_tb(s, 1, addr);
+        gen_goto_tb(s, 1, diff);
     } else {
         /* 0xe and 0xf are both "always" conditions */
-        gen_goto_tb(s, 0, addr);
+        gen_goto_tb(s, 0, diff);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
          * any pending interrupts immediately.
          */
         reset_btype(s);
-        gen_goto_tb(s, 0, s->base.pc_next);
+        gen_goto_tb(s, 0, 4);
         return;
 
     case 7: /* SB */
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
          * MB and end the TB instead.
          */
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
-        gen_goto_tb(s, 0, s->base.pc_next);
+        gen_goto_tb(s, 0, 4);
         return;
 
     default:
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         switch (dc->base.is_jmp) {
         case DISAS_NEXT:
         case DISAS_TOO_MANY:
-            gen_goto_tb(dc, 1, dc->base.pc_next);
+            gen_goto_tb(dc, 1, 4);
             break;
         default:
         case DISAS_UPDATE_EXIT:
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_ptr(void)
  * cpu_loop_exec. Any live exit_requests will be processed as we
  * enter the next TB.
  */
-static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *s, int n, int diff)
 {
+    target_ulong dest = s->pc_curr + diff;
+
     if (translator_use_goto_tb(&s->base, dest)) {
         tcg_gen_goto_tb(n);
         gen_set_pc_im(s, dest);
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
          *    gen_jmp();
          * on the second call to gen_jmp().
          */
-        gen_goto_tb(s, tbno, dest);
+        gen_goto_tb(s, tbno, dest - s->pc_curr);
         break;
     case DISAS_UPDATE_NOCHAIN:
     case DISAS_UPDATE_EXIT:
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         switch (dc->base.is_jmp) {
         case DISAS_NEXT:
         case DISAS_TOO_MANY:
-            gen_goto_tb(dc, 1, dc->base.pc_next);
+            gen_goto_tb(dc, 1, curr_insn_len(dc));
             break;
         case DISAS_UPDATE_NOCHAIN:
             gen_set_pc_im(dc, dc->base.pc_next);
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             gen_set_pc_im(dc, dc->base.pc_next);
             gen_singlestep_exception(dc);
         } else {
-            gen_goto_tb(dc, 1, dc->base.pc_next);
+            gen_goto_tb(dc, 1, curr_insn_len(dc));
         }
     }
 }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a32.h |  2 +-
 target/arm/translate.h     |  6 ++--
 target/arm/translate-a64.c | 32 +++++++++---------
 target/arm/translate-vfp.c |  2 +-
 target/arm/translate.c     | 68 ++++++++++++++++++++------------------
 5 files changed, 56 insertions(+), 54 deletions(-)

diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -XXX,XX +XXX,XX @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
 TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
 void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
 void gen_set_condexec(DisasContext *s);
-void gen_set_pc_im(DisasContext *s, target_ulong val);
+void gen_update_pc(DisasContext *s, target_long diff);
 void gen_lookup_tb(DisasContext *s);
 long vfp_reg_offset(bool dp, unsigned reg);
 long neon_full_reg_offset(unsigned reg);
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int curr_insn_len(DisasContext *s)
  * For instructions which want an immediate exit to the main loop, as opposed
  * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
  * doesn't write the PC on exiting the translation loop so you need to ensure
- * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
+ * something (gen_a64_update_pc or runtime helper) has done so before we reach
  * return from cpu_tb_exec.
  */
 #define DISAS_EXIT      DISAS_TARGET_9
@@ -XXX,XX +XXX,XX @@ static inline int curr_insn_len(DisasContext *s)
 
 #ifdef TARGET_AARCH64
 void a64_translate_init(void);
-void gen_a64_set_pc_im(uint64_t val);
+void gen_a64_update_pc(DisasContext *s, target_long diff);
 extern const TranslatorOps aarch64_translator_ops;
 #else
 static inline void a64_translate_init(void)
 {
 }
 
-static inline void gen_a64_set_pc_im(uint64_t val)
+static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
 {
 }
 #endif
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s)
     }
 }
 
-void gen_a64_set_pc_im(uint64_t val)
+void gen_a64_update_pc(DisasContext *s, target_long diff)
 {
-    tcg_gen_movi_i64(cpu_pc, val);
+    tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
 
 static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
 {
-    gen_a64_set_pc_im(pc);
+    gen_a64_update_pc(s, pc - s->pc_curr);
     gen_exception_internal(excp);
     s->base.is_jmp = DISAS_NORETURN;
 }
 
 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
 {
-    gen_a64_set_pc_im(s->pc_curr);
+    gen_a64_update_pc(s, 0);
     gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
     s->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
 
     if (use_goto_tb(s, dest)) {
         tcg_gen_goto_tb(n);
-        gen_a64_set_pc_im(dest);
+        gen_a64_update_pc(s, diff);
         tcg_gen_exit_tb(s->base.tb, n);
         s->base.is_jmp = DISAS_NORETURN;
     } else {
-        gen_a64_set_pc_im(dest);
+        gen_a64_update_pc(s, diff);
         if (s->ss_active) {
             gen_step_complete_exception(s);
         } else {
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         uint32_t syndrome;
 
         syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
-        gen_a64_set_pc_im(s->pc_curr);
+        gen_a64_update_pc(s, 0);
         gen_helper_access_check_cp_reg(cpu_env,
                                        tcg_constant_ptr(ri),
                                        tcg_constant_i32(syndrome),
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
          * The readfn or writefn might raise an exception;
          * synchronize the CPU state in case it does.
          */
-        gen_a64_set_pc_im(s->pc_curr);
+        gen_a64_update_pc(s, 0);
     }
 
     /* Handle special cases first */
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
             /* The pre HVC helper handles cases when HVC gets trapped
              * as an undefined insn by runtime configuration.
              */
-            gen_a64_set_pc_im(s->pc_curr);
+            gen_a64_update_pc(s, 0);
             gen_helper_pre_hvc(cpu_env);
             gen_ss_advance(s);
             gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
                 unallocated_encoding(s);
                 break;
             }
-            gen_a64_set_pc_im(s->pc_curr);
+            gen_a64_update_pc(s, 0);
             gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
             gen_ss_advance(s);
             gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
          */
         switch (dc->base.is_jmp) {
         default:
-            gen_a64_set_pc_im(dc->base.pc_next);
+            gen_a64_update_pc(dc, 4);
             /* fall through */
         case DISAS_EXIT:
         case DISAS_JUMP:
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             break;
         default:
         case DISAS_UPDATE_EXIT:
-            gen_a64_set_pc_im(dc->base.pc_next);
+            gen_a64_update_pc(dc, 4);
             /* fall through */
         case DISAS_EXIT:
             tcg_gen_exit_tb(NULL, 0);
             break;
         case DISAS_UPDATE_NOCHAIN:
-            gen_a64_set_pc_im(dc->base.pc_next);
+            gen_a64_update_pc(dc, 4);
             /* fall through */
         case DISAS_JUMP:
             tcg_gen_lookup_and_goto_ptr();
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         case DISAS_SWI:
             break;
         case DISAS_WFE:
-            gen_a64_set_pc_im(dc->base.pc_next);
+            gen_a64_update_pc(dc, 4);
             gen_helper_wfe(cpu_env);
             break;
         case DISAS_YIELD:
-            gen_a64_set_pc_im(dc->base.pc_next);
+            gen_a64_update_pc(dc, 4);
             gen_helper_yield(cpu_env);
             break;
         case DISAS_WFI:
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
              * This is a special case because we don't want to just halt
              * the CPU if trying to debug across a WFI.
              */
-            gen_a64_set_pc_im(dc->base.pc_next);
+            gen_a64_update_pc(dc, 4);
             gen_helper_wfi(cpu_env, tcg_constant_i32(4));
             /*
              * The helper doesn't necessarily throw an exception, but we
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
         case ARM_VFP_FPSID:
             if (s->current_el == 1) {
                 gen_set_condexec(s);
-                gen_set_pc_im(s, s->pc_curr);
+                gen_update_pc(s, 0);
                 gen_helper_check_hcr_el2_trap(cpu_env,
                                               tcg_constant_i32(a->rt),
                                               tcg_constant_i32(a->reg));
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_set_condexec(DisasContext *s)
     }
 }
 
-void gen_set_pc_im(DisasContext *s, target_ulong val)
+void gen_update_pc(DisasContext *s, target_long diff)
 {
-    tcg_gen_movi_i32(cpu_R[15], val);
+    tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff);
 }
 
 /* Set PC and Thumb state from var.  var is marked as dead.  */
@@ -XXX,XX +XXX,XX @@ static inline void gen_bxns(DisasContext *s, int rm)
 
     /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
      * we need to sync state before calling it, but:
-     *  - we don't need to do gen_set_pc_im() because the bxns helper will
+     *  - we don't need to do gen_update_pc() because the bxns helper will
      *    always set the PC itself
      *  - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
      *    unless it's outside an IT block or the last insn in an IT block,
@@ -XXX,XX +XXX,XX @@ static inline void gen_blxns(DisasContext *s, int rm)
      * We do however need to set the PC, because the blxns helper reads it.
      * The blxns helper may throw an exception.
      */
-    gen_set_pc_im(s, s->base.pc_next);
+    gen_update_pc(s, curr_insn_len(s));
     gen_helper_v7m_blxns(cpu_env, var);
     tcg_temp_free_i32(var);
     s->base.is_jmp = DISAS_EXIT;
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
      * as an undefined insn by runtime configuration (ie before
      * the insn really executes).
      */
-    gen_set_pc_im(s, s->pc_curr);
+    gen_update_pc(s, 0);
     gen_helper_pre_hvc(cpu_env);
     /* Otherwise we will treat this as a real exception which
      * happens after execution of the insn. (The distinction matters
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
      * for single stepping.)
      */
     s->svc_imm = imm16;
-    gen_set_pc_im(s, s->base.pc_next);
+    gen_update_pc(s, curr_insn_len(s));
     s->base.is_jmp = DISAS_HVC;
 }
 
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
     /* As with HVC, we may take an exception either before or after
      * the insn executes.
      */
-    gen_set_pc_im(s, s->pc_curr);
+    gen_update_pc(s, 0);
     gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
-    gen_set_pc_im(s, s->base.pc_next);
+    gen_update_pc(s, curr_insn_len(s));
     s->base.is_jmp = DISAS_SMC;
 }
 
 static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
 {
     gen_set_condexec(s);
-    gen_set_pc_im(s, pc);
+    gen_update_pc(s, pc - s->pc_curr);
     gen_exception_internal(excp);
     s->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
                                     uint32_t syn, TCGv_i32 tcg_el)
 {
     if (s->aarch64) {
-        gen_a64_set_pc_im(pc);
+        gen_a64_update_pc(s, pc - s->pc_curr);
     } else {
         gen_set_condexec(s);
-        gen_set_pc_im(s, pc);
+        gen_update_pc(s, pc - s->pc_curr);
     }
     gen_exception_el_v(excp, syn, tcg_el);
     s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
 void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
 {
     if (s->aarch64) {
-        gen_a64_set_pc_im(pc);
+        gen_a64_update_pc(s, pc - s->pc_curr);
     } else {
         gen_set_condexec(s);
-        gen_set_pc_im(s, pc);
+        gen_update_pc(s, pc - s->pc_curr);
     }
     gen_exception(excp, syn);
     s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 {
     gen_set_condexec(s);
-    gen_set_pc_im(s, s->pc_curr);
+    gen_update_pc(s, 0);
     gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
     s->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
 
     if (translator_use_goto_tb(&s->base, dest)) {
         tcg_gen_goto_tb(n);
-        gen_set_pc_im(s, dest);
+        gen_update_pc(s, diff);
         tcg_gen_exit_tb(s->base.tb, n);
     } else {
-        gen_set_pc_im(s, dest);
+        gen_update_pc(s, diff);
         gen_goto_ptr();
     }
     s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
 /* Jump, specifying which TB number to use if we gen_goto_tb() */
 static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
 {
+    int diff = dest - s->pc_curr;
+
     if (unlikely(s->ss_active)) {
         /* An indirect jump so that we still trigger the debug exception.  */
-        gen_set_pc_im(s, dest);
+        gen_update_pc(s, diff);
         s->base.is_jmp = DISAS_JUMP;
         return;
     }
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
          *    gen_jmp();
          * on the second call to gen_jmp().
          */
-        gen_goto_tb(s, tbno, dest - s->pc_curr);
+        gen_goto_tb(s, tbno, diff);
         break;
     case DISAS_UPDATE_NOCHAIN:
     case DISAS_UPDATE_EXIT:
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
          * Avoid using goto_tb so we really do exit back to the main loop
          * and don't chain to another TB.
          */
-        gen_set_pc_im(s, dest);
+        gen_update_pc(s, diff);
         gen_goto_ptr();
         s->base.is_jmp = DISAS_NORETURN;
         break;
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
 
     /* Sync state because msr_banked() can raise exceptions */
     gen_set_condexec(s);
-    gen_set_pc_im(s, s->pc_curr);
+    gen_update_pc(s, 0);
     tcg_reg = load_reg(s, rn);
     gen_helper_msr_banked(cpu_env, tcg_reg,
                           tcg_constant_i32(tgtmode),
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
 
     /* Sync state because mrs_banked() can raise exceptions */
     gen_set_condexec(s);
-    gen_set_pc_im(s, s->pc_curr);
+    gen_update_pc(s, 0);
     tcg_reg = tcg_temp_new_i32();
     gen_helper_mrs_banked(tcg_reg, cpu_env,
                           tcg_constant_i32(tgtmode),
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
             }
 
             gen_set_condexec(s);
-            gen_set_pc_im(s, s->pc_curr);
+            gen_update_pc(s, 0);
             gen_helper_access_check_cp_reg(cpu_env,
                                            tcg_constant_ptr(ri),
                                            tcg_constant_i32(syndrome),
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
              * synchronize the CPU state in case it does.
              */
             gen_set_condexec(s);
-            gen_set_pc_im(s, s->pc_curr);
+            gen_update_pc(s, 0);
         }
 
         /* Handle special cases first */
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
                 unallocated_encoding(s);
                 return;
             }
-            gen_set_pc_im(s, s->base.pc_next);
+            gen_update_pc(s, curr_insn_len(s));
             s->base.is_jmp = DISAS_WFI;
             return;
         default:
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
     addr = tcg_temp_new_i32();
     /* get_r13_banked() will raise an exception if called from System mode */
     gen_set_condexec(s);
-    gen_set_pc_im(s, s->pc_curr);
+    gen_update_pc(s, 0);
     gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
     switch (amode) {
     case 0: /* DA */
@@ -XXX,XX +XXX,XX @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
      * scheduling of other vCPUs.
      */
     if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
-        gen_set_pc_im(s, s->base.pc_next);
+        gen_update_pc(s, curr_insn_len(s));
         s->base.is_jmp = DISAS_YIELD;
     }
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
      * implemented so we can't sleep like WFI does.
      */
     if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
-        gen_set_pc_im(s, s->base.pc_next);
+        gen_update_pc(s, curr_insn_len(s));
         s->base.is_jmp = DISAS_WFE;
     }
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
 static bool trans_WFI(DisasContext *s, arg_WFI *a)
 {
     /* For WFI, halt the vCPU until an IRQ. */
-    gen_set_pc_im(s, s->base.pc_next);
+    gen_update_pc(s, curr_insn_len(s));
     s->base.is_jmp = DISAS_WFI;
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
         (a->imm == semihost_imm)) {
         gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
     } else {
-        gen_set_pc_im(s, s->base.pc_next);
+        gen_update_pc(s, curr_insn_len(s));
         s->svc_imm = a->imm;
         s->base.is_jmp = DISAS_SWI;
     }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         case DISAS_TOO_MANY:
         case DISAS_UPDATE_EXIT:
         case DISAS_UPDATE_NOCHAIN:
-            gen_set_pc_im(dc, dc->base.pc_next);
+            gen_update_pc(dc, curr_insn_len(dc));
             /* fall through */
         default:
             /* FIXME: Single stepping a WFI insn will not halt the CPU. */
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             gen_goto_tb(dc, 1, curr_insn_len(dc));
             break;
         case DISAS_UPDATE_NOCHAIN:
-            gen_set_pc_im(dc, dc->base.pc_next);
+            gen_update_pc(dc, curr_insn_len(dc));
             /* fall through */
         case DISAS_JUMP:
             gen_goto_ptr();
             break;
         case DISAS_UPDATE_EXIT:
-            gen_set_pc_im(dc, dc->base.pc_next);
+            gen_update_pc(dc, curr_insn_len(dc));
             /* fall through */
         default:
             /* indicate that the hash table must be used to find the next TB */
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         gen_set_label(dc->condlabel);
         gen_set_condexec(dc);
         if (unlikely(dc->ss_active)) {
-            gen_set_pc_im(dc, dc->base.pc_next);
+            gen_update_pc(dc, curr_insn_len(dc));
             gen_singlestep_exception(dc);
         } else {
             gen_goto_tb(dc, 1, curr_insn_len(dc));
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h        |  5 +++--
 target/arm/translate-a64.c    | 28 ++++++++++-------------
 target/arm/translate-m-nocp.c |  6 ++---
 target/arm/translate-mve.c    |  2 +-
 target/arm/translate-vfp.c    |  6 ++---
 target/arm/translate.c        | 42 +++++++++++++++++------------------
 6 files changed, 43 insertions(+), 46 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 void arm_gen_test_cc(int cc, TCGLabel *label);
 MemOp pow2_align(unsigned i);
 void unallocated_encoding(DisasContext *s);
-void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
                            uint32_t syn, uint32_t target_el);
-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn);
+void gen_exception_insn(DisasContext *s, target_long pc_diff,
+                        int excp, uint32_t syn);
 
 /* Return state of Alternate Half-precision flag, caller frees result */
 static inline TCGv_i32 get_ahp_flag(void)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check_only(DisasContext *s)
         assert(!s->fp_access_checked);
         s->fp_access_checked = true;
 
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn_el(s, 0, EXCP_UDEF,
                               syn_fp_access_trap(1, 0xe, false, 0),
                               s->fp_excp_el);
         return false;
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
         return false;
     }
     if (s->sme_trap_nonstreaming && s->is_nonstreaming) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn(s, 0, EXCP_UDEF,
                            syn_smetrap(SME_ET_Streaming, false));
         return false;
     }
@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
             goto fail_exit;
         }
     } else if (s->sve_excp_el) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn_el(s, 0, EXCP_UDEF,
                               syn_sve_access_trap(), s->sve_excp_el);
         goto fail_exit;
     }
@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
 static bool sme_access_check(DisasContext *s)
 {
     if (s->sme_excp_el) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn_el(s, 0, EXCP_UDEF,
                               syn_smetrap(SME_ET_AccessTrap, false),
                               s->sme_excp_el);
         return false;
@@ -XXX,XX +XXX,XX @@ bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
         return false;
     }
     if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn(s, 0, EXCP_UDEF,
                            syn_smetrap(SME_ET_NotStreaming, false));
         return false;
     }
     if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn(s, 0, EXCP_UDEF,
                            syn_smetrap(SME_ET_InactiveZA, false));
         return false;
     }
@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
     } else {
         syndrome = syn_uncategorized();
     }
-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome);
+    gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
 }
 
 /* MRS - move from system register
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
         switch (op2_ll) {
         case 1:                                                     /* SVC */
             gen_ss_advance(s);
-            gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
-                               syn_aa64_svc(imm16));
+            gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
             break;
         case 2:                                                     /* HVC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
             gen_a64_update_pc(s, 0);
             gen_helper_pre_hvc(cpu_env);
             gen_ss_advance(s);
-            gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
-                                  syn_aa64_hvc(imm16), 2);
+            gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2);
             break;
         case 3:                                                     /* SMC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
             gen_a64_update_pc(s, 0);
             gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
             gen_ss_advance(s);
-            gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
-                                  syn_aa64_smc(imm16), 3);
+            gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3);
             break;
         default:
             unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
+        gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
             if (s->btype != 0
                 && s->guarded_page
                 && !btype_destination_ok(insn, s->bt, s->btype)) {
-                gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                                   syn_btitrap(s->btype));
+                gen_exception_insn(s, 0, EXCP_UDEF, syn_btitrap(s->btype));
                 return;
             }
         } else {
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-m-nocp.c
+++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
     tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
 
     if (s->fp_excp_el != 0) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+        gen_exception_insn_el(s, 0, EXCP_NOCP,
                               syn_uncategorized(), s->fp_excp_el);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
     }
 
     if (a->cp != 10) {
-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized());
+        gen_exception_insn(s, 0, EXCP_NOCP, syn_uncategorized());
         return true;
     }
 
     if (s->fp_excp_el != 0) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+        gen_exception_insn_el(s, 0, EXCP_NOCP,
                               syn_uncategorized(), s->fp_excp_el);
         return true;
     }
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s)
         return true;
     default:
         /* Reserved value: INVSTATE UsageFault */
-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
+        gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
         return false;
     }
 }
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
         int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
         uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
 
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
+        gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->fp_excp_el);
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
      * appear to be any insns which touch VFP which are allowed.
      */
     if (s->sme_trap_nonstreaming) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+        gen_exception_insn(s, 0, EXCP_UDEF,
                            syn_smetrap(SME_ET_Streaming,
                                        curr_insn_len(s) == 2));
         return false;
@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
          * the encoding space handled by the patterns in m-nocp.decode,
          * and for them we may need to raise NOCP here.
          */
-        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+        gen_exception_insn_el(s, 0, EXCP_NOCP,
                               syn_uncategorized(), s->fp_excp_el);
         return false;
     }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception(int excp, uint32_t syndrome)
                                        tcg_constant_i32(syndrome));
 }
 
-static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
-                                    uint32_t syn, TCGv_i32 tcg_el)
+static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff,
+                                    int excp, uint32_t syn, TCGv_i32 tcg_el)
 {
     if (s->aarch64) {
-        gen_a64_update_pc(s, pc - s->pc_curr);
+        gen_a64_update_pc(s, pc_diff);
     } else {
         gen_set_condexec(s);
-        gen_update_pc(s, pc - s->pc_curr);
+        gen_update_pc(s, pc_diff);
     }
     gen_exception_el_v(excp, syn, tcg_el);
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
                            uint32_t syn, uint32_t target_el)
 {
-    gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
+    gen_exception_insn_el_v(s, pc_diff, excp, syn,
+                            tcg_constant_i32(target_el));
 }
 
-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
+void gen_exception_insn(DisasContext *s, target_long pc_diff,
+                        int excp, uint32_t syn)
 {
     if (s->aarch64) {
-        gen_a64_update_pc(s, pc - s->pc_curr);
+        gen_a64_update_pc(s, pc_diff);
     } else {
         gen_set_condexec(s);
-        gen_update_pc(s, pc - s->pc_curr);
+        gen_update_pc(s, pc_diff);
     }
     gen_exception(excp, syn);
     s->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 void unallocated_encoding(DisasContext *s)
 {
     /* Unallocated and reserved encodings are uncategorized */
-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
+    gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized());
 }
 
 /* Force a TB lookup after an instruction that changes the CPU state.  */
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
                 tcg_el = tcg_constant_i32(3);
             }
 
-            gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF,
+            gen_exception_insn_el_v(s, 0, EXCP_UDEF,
                                     syn_uncategorized(), tcg_el);
             tcg_temp_free_i32(tcg_el);
             return false;
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
 
 undef:
     /* If we get here then some access check did not pass */
-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
+    gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized());
     return false;
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
      * For the UNPREDICTABLE cases we choose to UNDEF.
      */
     if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
-                              syn_uncategorized(), 3);
+        gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
          * Do the check-and-raise-exception by hand.
          */
         if (s->fp_excp_el) {
-            gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+            gen_exception_insn_el(s, 0, EXCP_NOCP,
                                   syn_uncategorized(), s->fp_excp_el);
             return true;
         }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
         tmp = load_cpu_field(v7m.ltpsize);
         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
         tcg_temp_free_i32(tmp);
-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
+        gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
         gen_set_label(skipexc);
     }
 
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
      * UsageFault exception.
      */
     if (arm_dc_feature(s, ARM_FEATURE_M)) {
-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
+        gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
+        gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate());
+        gen_exception_insn(dc, 0, EXCP_UDEF, syn_illegalstate());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          */
         tcg_remove_ops_after(dc->insn_eci_rewind);
         dc->condjmp = 0;
-        gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE,
-                           syn_uncategorized());
+        gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized());
     }
 
     arm_post_translate_insn(dc);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c |  6 +++---
 target/arm/translate.c     | 10 +++++-----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
     gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
 }
 
-static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
+static void gen_exception_internal_insn(DisasContext *s, int excp)
 {
-    gen_a64_update_pc(s, pc - s->pc_curr);
+    gen_a64_update_pc(s, 0);
     gen_exception_internal(excp);
     s->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
          * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
          */
         if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) {
-            gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+            gen_exception_internal_insn(s, EXCP_SEMIHOST);
         } else {
             unallocated_encoding(s);
         }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
     s->base.is_jmp = DISAS_SMC;
 }
 
-static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
+static void gen_exception_internal_insn(DisasContext *s, int excp)
 {
     gen_set_condexec(s);
-    gen_update_pc(s, pc - s->pc_curr);
+    gen_update_pc(s, 0);
     gen_exception_internal(excp);
     s->base.is_jmp = DISAS_NORETURN;
 }
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
      */
     if (semihosting_enabled(s->current_el != 0) &&
         (imm == (s->thumb ? 0x3c : 0xf000))) {
-        gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+        gen_exception_internal_insn(s, EXCP_SEMIHOST);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
     if (arm_dc_feature(s, ARM_FEATURE_M) &&
         semihosting_enabled(s->current_el == 0) &&
         (a->imm == 0xab)) {
-        gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+        gen_exception_internal_insn(s, EXCP_SEMIHOST);
     } else {
         gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
     if (!arm_dc_feature(s, ARM_FEATURE_M) &&
         semihosting_enabled(s->current_el == 0) &&
         (a->imm == semihost_imm)) {
-        gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
+        gen_exception_internal_insn(s, EXCP_SEMIHOST);
     } else {
         gen_update_pc(s, curr_insn_len(s));
         s->svc_imm = a->imm;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 37 +++++++++++++++++++++----------------
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t read_pc(DisasContext *s)
     return s->pc_curr + (s->thumb ? 4 : 8);
 }
 
+/* The pc_curr difference for an architectural jump. */
+static target_long jmp_diff(DisasContext *s, target_long diff)
+{
+    return diff + (s->thumb ? 4 : 8);
+}
+
 /* Set a variable to the value of a CPU register.  */
 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
 {
@@ -XXX,XX +XXX,XX @@ static void gen_goto_ptr(void)
  * cpu_loop_exec. Any live exit_requests will be processed as we
  * enter the next TB.
  */
-static void gen_goto_tb(DisasContext *s, int n, int diff)
+static void gen_goto_tb(DisasContext *s, int n, target_long diff)
 {
     target_ulong dest = s->pc_curr + diff;
 
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
 }
 
 /* Jump, specifying which TB number to use if we gen_goto_tb() */
-static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
+static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno)
 {
-    int diff = dest - s->pc_curr;
-
     if (unlikely(s->ss_active)) {
         /* An indirect jump so that we still trigger the debug exception.  */
         gen_update_pc(s, diff);
@@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
     }
 }
 
-static inline void gen_jmp(DisasContext *s, uint32_t dest)
+static inline void gen_jmp(DisasContext *s, target_long diff)
 {
-    gen_jmp_tb(s, dest, 0);
+    gen_jmp_tb(s, diff, 0);
 }
 
 static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
 
 static bool trans_B(DisasContext *s, arg_i *a)
 {
-    gen_jmp(s, read_pc(s) + a->imm);
+    gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
         return true;
     }
     arm_skip_unless(s, a->cond);
-    gen_jmp(s, read_pc(s) + a->imm);
+    gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
 
 static bool trans_BL(DisasContext *s, arg_i *a)
 {
     tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
-    gen_jmp(s, read_pc(s) + a->imm);
+    gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
     }
     tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
     store_cpu_field_constant(!s->thumb, thumb);
-    gen_jmp(s, (read_pc(s) & ~3) + a->imm);
+    /* This jump is computed from an aligned PC: subtract off the low bits. */
+    gen_jmp(s, jmp_diff(s, a->imm - (s->pc_curr & 3)));
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
          * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
          */
     }
-    gen_jmp_tb(s, s->base.pc_next, 1);
+    gen_jmp_tb(s, curr_insn_len(s), 1);
 
     gen_set_label(nextlabel);
-    gen_jmp(s, read_pc(s) + a->imm);
+    gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
 
     if (a->f) {
         /* Loop-forever: just jump back to the loop start */
-        gen_jmp(s, read_pc(s) - a->imm);
+        gen_jmp(s, jmp_diff(s, -a->imm));
         return true;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
         tcg_temp_free_i32(decr);
     }
     /* Jump back to the loop start */
-    gen_jmp(s, read_pc(s) - a->imm);
+    gen_jmp(s, jmp_diff(s, -a->imm));
 
     gen_set_label(loopend);
     if (a->tp) {
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
         store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
     }
     /* End TB, continuing to following insn */
-    gen_jmp_tb(s, s->base.pc_next, 1);
+    gen_jmp_tb(s, curr_insn_len(s), 1);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
     tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
                         tmp, 0, s->condlabel);
     tcg_temp_free_i32(tmp);
-    gen_jmp(s, read_pc(s) + a->imm);
+    gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s)
     }
 }
 
+static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
+{
+    tcg_gen_movi_i64(dest, s->pc_curr + diff);
+}
+
 void gen_a64_update_pc(DisasContext *s, target_long diff)
 {
-    tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
+    gen_pc_plus_diff(s, cpu_pc, diff);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
 
     if (insn & (1U << 31)) {
         /* BL Branch with link */
-        tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
+        gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
     }
 
     /* B Branch / BL Branch with link */
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
         default:
             goto do_unallocated;
         }
-        gen_a64_set_pc(s, dst);
         /* BLR also needs to load return address */
         if (opc == 1) {
-            tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
+            TCGv_i64 lr = cpu_reg(s, 30);
+            if (dst == lr) {
+                TCGv_i64 tmp = new_tmp_a64(s);
+                tcg_gen_mov_i64(tmp, dst);
+                dst = tmp;
+            }
+            gen_pc_plus_diff(s, lr, curr_insn_len(s));
         }
+        gen_a64_set_pc(s, dst);
         break;
 
     case 8: /* BRAA */
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
         } else {
             dst = cpu_reg(s, rn);
         }
-        gen_a64_set_pc(s, dst);
         /* BLRAA also needs to load return address */
         if (opc == 9) {
-            tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
+            TCGv_i64 lr = cpu_reg(s, 30);
+            if (dst == lr) {
+                TCGv_i64 tmp = new_tmp_a64(s);
+                tcg_gen_mov_i64(tmp, dst);
+                dst = tmp;
+            }
+            gen_pc_plus_diff(s, lr, curr_insn_len(s));
         }
+        gen_a64_set_pc(s, dst);
         break;
 
     case 4: /* ERET */
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
 
     tcg_rt = cpu_reg(s, rt);
 
-    clean_addr = tcg_constant_i64(s->pc_curr + imm);
+    clean_addr = new_tmp_a64(s);
+    gen_pc_plus_diff(s, clean_addr, imm);
     if (is_vector) {
         do_fp_ld(s, rt, clean_addr, size);
     } else {
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
 {
     unsigned int page, rd;
-    uint64_t base;
-    uint64_t offset;
+    int64_t offset;
 
     page = extract32(insn, 31, 1);
     /* SignExtend(immhi:immlo) -> offset */
     offset = sextract64(insn, 5, 19);
     offset = offset << 2 | extract32(insn, 29, 2);
     rd = extract32(insn, 0, 5);
-    base = s->pc_curr;
 
     if (page) {
         /* ADRP (page based) */
-        base &= ~0xfff;
         offset <<= 12;
+        /* The page offset is ok for TARGET_TB_PCREL. */
+        offset -= s->pc_curr & 0xfff;
     }
 
-    tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
+    gen_pc_plus_diff(s, cpu_reg(s, rd), offset);
 }
 
 /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
     }
 }
 
-/* The architectural value of PC.  */
-static uint32_t read_pc(DisasContext *s)
-{
-    return s->pc_curr + (s->thumb ? 4 : 8);
-}
-
 /* The pc_curr difference for an architectural jump. */
 static target_long jmp_diff(DisasContext *s, target_long diff)
 {
     return diff + (s->thumb ? 4 : 8);
 }
 
+static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)
+{
+    tcg_gen_movi_i32(var, s->pc_curr + diff);
+}
+
 /* Set a variable to the value of a CPU register.  */
 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
 {
     if (reg == 15) {
-        tcg_gen_movi_i32(var, read_pc(s));
+        gen_pc_plus_diff(s, var, jmp_diff(s, 0));
     } else {
         tcg_gen_mov_i32(var, cpu_R[reg]);
     }
@@ -XXX,XX +XXX,XX @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
     TCGv_i32 tmp = tcg_temp_new_i32();
 
     if (reg == 15) {
-        tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs);
+        /*
+         * This address is computed from an aligned PC:
+         * subtract off the low bits.
+         */
+        gen_pc_plus_diff(s, tmp, jmp_diff(s, ofs - (s->pc_curr & 3)));
     } else {
         tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
     }
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
 /* Force a TB lookup after an instruction that changes the CPU state.  */
 void gen_lookup_tb(DisasContext *s)
 {
-    tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
+    gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s));
     s->base.is_jmp = DISAS_EXIT;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a)
         return false;
     }
     tmp = load_reg(s, a->rm);
-    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
+    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb);
     gen_bx(s, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
 
 static bool trans_BL(DisasContext *s, arg_i *a)
 {
-    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
+    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb);
     gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
     if (s->thumb && (a->imm & 2)) {
         return false;
     }
-    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
+    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb);
     store_cpu_field_constant(!s->thumb, thumb);
     /* This jump is computed from an aligned PC: subtract off the low bits. */
     gen_jmp(s, jmp_diff(s, a->imm - (s->pc_curr & 3)));
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
 static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a)
 {
     assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
-    tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12));
+    gen_pc_plus_diff(s, cpu_R[14], jmp_diff(s, a->imm << 12));
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a)
 
     assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2));
     tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1);
-    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
+    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1);
     gen_bx(s, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a)
     tmp = tcg_temp_new_i32();
     tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1);
     tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
-    tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
+    gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1);
     gen_bx(s, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
     tcg_gen_add_i32(addr, addr, tmp);
 
     gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB);
-    tcg_temp_free_i32(addr);
 
     tcg_gen_add_i32(tmp, tmp, tmp);
-    tcg_gen_addi_i32(tmp, tmp, read_pc(s));
+    gen_pc_plus_diff(s, addr, jmp_diff(s, 0));
+    tcg_gen_add_i32(tmp, tmp, addr);
+    tcg_temp_free_i32(addr);
     store_reg(s, 15, tmp);
     return true;
 }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu-param.h        |   2 +
 target/arm/translate.h        |  50 +++++++++++++++-
 target/arm/cpu.c              |  23 ++++----
 target/arm/translate-a64.c    |  64 +++++++++++++-------
 target/arm/translate-m-nocp.c |   2 +-
 target/arm/translate.c        | 108 +++++++++++++++++++++++-----------
 6 files changed, 178 insertions(+), 71 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
 # define TARGET_PAGE_BITS_VARY
 # define TARGET_PAGE_BITS_MIN  10
 
+# define TARGET_TB_PCREL 1
+
 /*
  * Cache the attrs and shareability fields from the page table entry.
  *
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@
 
 
 /* internal defines */
+
+/*
+ * Save pc_save across a branch, so that we may restore the value from
+ * before the branch at the point the label is emitted.
+ */
+typedef struct DisasLabel {
+    TCGLabel *label;
+    target_ulong pc_save;
+} DisasLabel;
+
 typedef struct DisasContext {
     DisasContextBase base;
     const ARMISARegisters *isar;
 
     /* The address of the current instruction being translated. */
     target_ulong pc_curr;
+    /*
+     * For TARGET_TB_PCREL, the full value of cpu_pc is not known
+     * (although the page offset is known).  For convenience, the
+     * translation loop uses the full virtual address that triggered
+     * the translation, from base.pc_start through pc_curr.
+     * For efficiency, we do not update cpu_pc for every instruction.
+     * Instead, pc_save has the value of pc_curr at the time of the
+     * last update to cpu_pc, which allows us to compute the addend
+     * needed to bring cpu_pc current: pc_curr - pc_save.
+     * If cpu_pc now contains the destination of an indirect branch,
+     * pc_save contains -1 to indicate that relative updates are no
+     * longer possible.
+     */
+    target_ulong pc_save;
     target_ulong page_start;
     uint32_t insn;
     /* Nonzero if this instruction has been conditionally skipped.  */
     int condjmp;
     /* The label that will be jumped to when the instruction is skipped.  */
-    TCGLabel *condlabel;
+    DisasLabel condlabel;
     /* Thumb-2 conditional execution bits.  */
     int condexec_mask;
     int condexec_cond;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      * after decode (ie after any UNDEF checks)
      */
     bool eci_handled;
-    /* TCG op to rewind to if this turns out to be an invalid ECI state */
-    TCGOp *insn_eci_rewind;
     int sctlr_b;
     MemOp be_data;
 #if !defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  */
 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 
+/*
+ * gen_disas_label:
+ * Create a label and cache a copy of pc_save.
+ */
+static inline DisasLabel gen_disas_label(DisasContext *s)
+{
+    return (DisasLabel){
+        .label = gen_new_label(),
+        .pc_save = s->pc_save,
+    };
+}
+
+/*
+ * set_disas_label:
+ * Emit a label and restore the cached copy of pc_save.
+ */
+static inline void set_disas_label(DisasContext *s, DisasLabel l)
+{
+    gen_set_label(l.label);
+    s->pc_save = l.pc_save;
+}
+
 /*
  * Helpers for implementing sets of trans_* functions.
  * Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static vaddr arm_cpu_get_pc(CPUState *cs)
 void arm_cpu_synchronize_from_tb(CPUState *cs,
                                  const TranslationBlock *tb)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-
-    /*
-     * It's OK to look at env for the current mode here, because it's
-     * never possible for an AArch64 TB to chain to an AArch32 TB.
-     */
-    if (is_a64(env)) {
-        env->pc = tb_pc(tb);
-    } else {
-        env->regs[15] = tb_pc(tb);
+    /* The program counter is always up to date with TARGET_TB_PCREL. */
+    if (!TARGET_TB_PCREL) {
+        CPUARMState *env = cs->env_ptr;
+        /*
+         * It's OK to look at env for the current mode here, because it's
+         * never possible for an AArch64 TB to chain to an AArch32 TB.
+         */
+        if (is_a64(env)) {
+            env->pc = tb_pc(tb);
+        } else {
+            env->regs[15] = tb_pc(tb);
+        }
     }
 }
 #endif /* CONFIG_TCG */
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s)
 
 static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
 {
-    tcg_gen_movi_i64(dest, s->pc_curr + diff);
+    assert(s->pc_save != -1);
+    if (TARGET_TB_PCREL) {
+        tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff);
+    } else {
+        tcg_gen_movi_i64(dest, s->pc_curr + diff);
+    }
 }
 
 void gen_a64_update_pc(DisasContext *s, target_long diff)
 {
     gen_pc_plus_diff(s, cpu_pc, diff);
+    s->pc_save = s->pc_curr + diff;
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
      * then loading an address into the PC will clear out any tag.
      */
     gen_top_byte_ignore(s, cpu_pc, src, s->tbii);
+    s->pc_save = -1;
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
 
 static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
 {
-    uint64_t dest = s->pc_curr + diff;
-
-    if (use_goto_tb(s, dest)) {
-        tcg_gen_goto_tb(n);
-        gen_a64_update_pc(s, diff);
+    if (use_goto_tb(s, s->pc_curr + diff)) {
+        /*
+         * For pcrel, the pc must always be up-to-date on entry to
+         * the linked TB, so that it can use simple additions for all
+         * further adjustments.  For !pcrel, the linked TB is compiled
+         * to know its full virtual address, so we can delay the
+         * update to pc to the unlinked path.  A long chain of links
+         * can thus avoid many updates to the PC.
+         */
+        if (TARGET_TB_PCREL) {
+            gen_a64_update_pc(s, diff);
+            tcg_gen_goto_tb(n);
+        } else {
+            tcg_gen_goto_tb(n);
+            gen_a64_update_pc(s, diff);
+        }
         tcg_gen_exit_tb(s->base.tb, n);
         s->base.is_jmp = DISAS_NORETURN;
     } else {
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
 {
     unsigned int sf, op, rt;
     int64_t diff;
-    TCGLabel *label_match;
+    DisasLabel match;
     TCGv_i64 tcg_cmp;
 
     sf = extract32(insn, 31, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
     diff = sextract32(insn, 5, 19) * 4;
 
     tcg_cmp = read_cpu_reg(s, rt, sf);
-    label_match = gen_new_label();
-
     reset_btype(s);
-    tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
-                        tcg_cmp, 0, label_match);
 
+    match = gen_disas_label(s);
+    tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
+                        tcg_cmp, 0, match.label);
     gen_goto_tb(s, 0, 4);
-    gen_set_label(label_match);
+    set_disas_label(s, match);
     gen_goto_tb(s, 1, diff);
 }
 
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
 {
     unsigned int bit_pos, op, rt;
     int64_t diff;
-    TCGLabel *label_match;
+    DisasLabel match;
     TCGv_i64 tcg_cmp;
 
     bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
 
     tcg_cmp = tcg_temp_new_i64();
     tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
-    label_match = gen_new_label();
 
     reset_btype(s);
+
+    match = gen_disas_label(s);
     tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
-                        tcg_cmp, 0, label_match);
+                        tcg_cmp, 0, match.label);
     tcg_temp_free_i64(tcg_cmp);
     gen_goto_tb(s, 0, 4);
-    gen_set_label(label_match);
+    set_disas_label(s, match);
     gen_goto_tb(s, 1, diff);
 }
 
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
     reset_btype(s);
     if (cond < 0x0e) {
         /* genuinely conditional branches */
-        TCGLabel *label_match = gen_new_label();
-        arm_gen_test_cc(cond, label_match);
+        DisasLabel match = gen_disas_label(s);
+        arm_gen_test_cc(cond, match.label);
         gen_goto_tb(s, 0, 4);
-        gen_set_label(label_match);
+        set_disas_label(s, match);
         gen_goto_tb(s, 1, diff);
     } else {
         /* 0xe and 0xf are both "always" conditions */
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
 
     dc->isar = &arm_cpu->isar;
     dc->condjmp = 0;
-
+    dc->pc_save = dc->base.pc_first;
     dc->aarch64 = true;
     dc->thumb = false;
     dc->sctlr_b = 0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
+    target_ulong pc_arg = dc->base.pc_next;
 
-    tcg_gen_insn_start(dc->base.pc_next, 0, 0);
+    if (TARGET_TB_PCREL) {
+        pc_arg &= ~TARGET_PAGE_MASK;
+    }
+    tcg_gen_insn_start(pc_arg, 0, 0);
     dc->insn_start = tcg_last_op();
 }
 
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-m-nocp.c
+++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
     tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
     tcg_gen_or_i32(sfpa, sfpa, aspen);
     arm_gen_condlabel(s);
-    tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
+    tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel.label);
 
     if (s->fp_excp_el != 0) {
         gen_exception_insn_el(s, 0, EXCP_NOCP,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
 void arm_gen_condlabel(DisasContext *s)
 {
     if (!s->condjmp) {
-        s->condlabel = gen_new_label();
+        s->condlabel = gen_disas_label(s);
         s->condjmp = 1;
     }
 }
@@ -XXX,XX +XXX,XX @@ static target_long jmp_diff(DisasContext *s, target_long diff)
 
 static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)
 {
-    tcg_gen_movi_i32(var, s->pc_curr + diff);
+    assert(s->pc_save != -1);
+    if (TARGET_TB_PCREL) {
+        tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff);
+    } else {
+        tcg_gen_movi_i32(var, s->pc_curr + diff);
+    }
 }
 
 /* Set a variable to the value of a CPU register.  */
@@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var)
          */
         tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
         s->base.is_jmp = DISAS_JUMP;
+        s->pc_save = -1;
     } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) {
         /* For M-profile SP bits [1:0] are always zero */
         tcg_gen_andi_i32(var, var, ~3);
@@ -XXX,XX +XXX,XX @@ void gen_set_condexec(DisasContext *s)
 
 void gen_update_pc(DisasContext *s, target_long diff)
 {
-    tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff);
+    gen_pc_plus_diff(s, cpu_R[15], diff);
+    s->pc_save = s->pc_curr + diff;
 }
 
 /* Set PC and Thumb state from var.  var is marked as dead.  */
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
     tcg_gen_andi_i32(cpu_R[15], var, ~1);
     tcg_gen_andi_i32(var, var, 1);
     store_cpu_field(var, thumb);
+    s->pc_save = -1;
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
 static inline void gen_bx_excret_final_code(DisasContext *s)
 {
     /* Generate the code to finish possible exception return and end the TB */
-    TCGLabel *excret_label = gen_new_label();
+    DisasLabel excret_label = gen_disas_label(s);
     uint32_t min_magic;
 
     if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
     }
 
     /* Is the new PC value in the magic range indicating exception return? */
-    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label.label);
     /* No: end the TB as we would for a DISAS_JMP */
     if (s->ss_active) {
         gen_singlestep_exception(s);
     } else {
         tcg_gen_exit_tb(NULL, 0);
     }
-    gen_set_label(excret_label);
+    set_disas_label(s, excret_label);
     /* Yes: this is an exception return.
      * At this point in runtime env->regs[15] and env->thumb will hold
      * the exception-return magic number, which do_v7m_exception_exit()
@@ -XXX,XX +XXX,XX @@ static void gen_goto_ptr(void)
  */
 static void gen_goto_tb(DisasContext *s, int n, target_long diff)
 {
-    target_ulong dest = s->pc_curr + diff;
-
-    if (translator_use_goto_tb(&s->base, dest)) {
-        tcg_gen_goto_tb(n);
-        gen_update_pc(s, diff);
+    if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {
+        /*
+         * For pcrel, the pc must always be up-to-date on entry to
+         * the linked TB, so that it can use simple additions for all
+         * further adjustments.  For !pcrel, the linked TB is compiled
+         * to know its full virtual address, so we can delay the
+         * update to pc to the unlinked path.  A long chain of links
+         * can thus avoid many updates to the PC.
+         */
+        if (TARGET_TB_PCREL) {
+            gen_update_pc(s, diff);
+            tcg_gen_goto_tb(n);
+        } else {
+            tcg_gen_goto_tb(n);
+            gen_update_pc(s, diff);
+        }
         tcg_gen_exit_tb(s->base.tb, n);
     } else {
         gen_update_pc(s, diff);
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
 static void arm_skip_unless(DisasContext *s, uint32_t cond)
 {
     arm_gen_condlabel(s);
-    arm_gen_test_cc(cond ^ 1, s->condlabel);
+    arm_gen_test_cc(cond ^ 1, s->condlabel.label);
 }
 
 
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
 {
     /* M-profile low-overhead while-loop start */
     TCGv_i32 tmp;
-    TCGLabel *nextlabel;
+    DisasLabel nextlabel;
 
     if (!dc_isar_feature(aa32_lob, s)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
         }
     }
 
-    nextlabel = gen_new_label();
-    tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel);
+    nextlabel = gen_disas_label(s);
+    tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel.label);
     tmp = load_reg(s, a->rn);
     store_reg(s, 14, tmp);
     if (a->size != 4) {
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
     }
     gen_jmp_tb(s, curr_insn_len(s), 1);
 
-    gen_set_label(nextlabel);
+    set_disas_label(s, nextlabel);
     gen_jmp(s, jmp_diff(s, a->imm));
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
      * any faster.
      */
     TCGv_i32 tmp;
-    TCGLabel *loopend;
+    DisasLabel loopend;
     bool fpu_active;
 
     if (!dc_isar_feature(aa32_lob, s)) {
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
 
     if (!a->tp && dc_isar_feature(aa32_mve, s) && fpu_active) {
         /* Need to do a runtime check for LTPSIZE != 4 */
-        TCGLabel *skipexc = gen_new_label();
+        DisasLabel skipexc = gen_disas_label(s);
         tmp = load_cpu_field(v7m.ltpsize);
-        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
+        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc.label);
         tcg_temp_free_i32(tmp);
         gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized());
-        gen_set_label(skipexc);
+        set_disas_label(s, skipexc);
     }
 
     if (a->f) {
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
      * loop decrement value is 1. For LETP we need to calculate the decrement
      * value from LTPSIZE.
      */
-    loopend = gen_new_label();
+    loopend = gen_disas_label(s);
     if (!a->tp) {
-        tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend);
+        tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend.label);
         tcg_gen_addi_i32(cpu_R[14], cpu_R[14], -1);
     } else {
         /*
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
         tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr);
         tcg_temp_free_i32(ltpsize);
 
-        tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend);
+        tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend.label);
 
         tcg_gen_sub_i32(cpu_R[14], cpu_R[14], decr);
         tcg_temp_free_i32(decr);
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
     /* Jump back to the loop start */
     gen_jmp(s, jmp_diff(s, -a->imm));
 
-    gen_set_label(loopend);
+    set_disas_label(s, loopend);
     if (a->tp) {
         /* Exits from tail-pred loops must reset LTPSIZE to 4 */
         store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
 
     arm_gen_condlabel(s);
     tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE,
-                        tmp, 0, s->condlabel);
+                        tmp, 0, s->condlabel.label);
     tcg_temp_free_i32(tmp);
     gen_jmp(s, jmp_diff(s, a->imm));
     return true;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 
     dc->isar = &cpu->isar;
     dc->condjmp = 0;
-
+    dc->pc_save = dc->base.pc_first;
     dc->aarch64 = false;
     dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB);
     dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      */
     dc->eci = dc->condexec_mask = dc->condexec_cond = 0;
     dc->eci_handled = false;
-    dc->insn_eci_rewind = NULL;
     if (condexec & 0xf) {
         dc->condexec_mask = (condexec & 0xf) << 1;
         dc->condexec_cond = condexec >> 4;
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
      * fields here.
      */
     uint32_t condexec_bits;
+    target_ulong pc_arg = dc->base.pc_next;
 
+    if (TARGET_TB_PCREL) {
+        pc_arg &= ~TARGET_PAGE_MASK;
+    }
     if (dc->eci) {
         condexec_bits = dc->eci << 4;
     } else {
         condexec_bits = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
     }
-    tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0);
+    tcg_gen_insn_start(pc_arg, condexec_bits, 0);
     dc->insn_start = tcg_last_op();
 }
 
@@ -XXX,XX +XXX,XX @@ static bool arm_check_ss_active(DisasContext *dc)
 
 static void arm_post_translate_insn(DisasContext *dc)
 {
-    if (dc->condjmp && !dc->base.is_jmp) {
-        gen_set_label(dc->condlabel);
+    if (dc->condjmp && dc->base.is_jmp == DISAS_NEXT) {
+        if (dc->pc_save != dc->condlabel.pc_save) {
+            gen_update_pc(dc, dc->condlabel.pc_save - dc->pc_save);
+        }
+        gen_set_label(dc->condlabel.label);
         dc->condjmp = 0;
     }
     translator_loop_temp_check(&dc->base);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t pc = dc->base.pc_next;
     uint32_t insn;
     bool is_16bit;
+    /* TCG op to rewind to if this turns out to be an invalid ECI state */
+    TCGOp *insn_eci_rewind = NULL;
+    target_ulong insn_eci_pc_save = -1;
 
     /* Misaligned thumb PC is architecturally impossible. */
     assert((dc->base.pc_next & 1) == 0);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          *     insn" case. We will rewind to the marker (ie throwing away
          *     all the generated code) and instead emit "take exception".
          */
-        dc->insn_eci_rewind = tcg_last_op();
+        insn_eci_rewind = tcg_last_op();
+        insn_eci_pc_save = dc->pc_save;
     }
 
     if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Insn wasn't valid for ECI/ICI at all: undo what we
          * just generated and instead emit an exception
          */
-        tcg_remove_ops_after(dc->insn_eci_rewind);
+        tcg_remove_ops_after(insn_eci_rewind);
+        dc->pc_save = insn_eci_pc_save;
         dc->condjmp = 0;
         gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized());
     }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 
     if (dc->condjmp) {
         /* "Condition failed" instruction codepath for the branch/trap insn */
-        gen_set_label(dc->condlabel);
+        set_disas_label(dc, dc->condlabel);
         gen_set_condexec(dc);
         if (unlikely(dc->ss_active)) {
             gen_update_pc(dc, curr_insn_len(dc));
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
                           target_ulong *data)
 {
     if (is_a64(env)) {
-        env->pc = data[0];
+        if (TARGET_TB_PCREL) {
+            env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+        } else {
+            env->pc = data[0];
+        }
         env->condexec_bits = 0;
         env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
     } else {
-        env->regs[15] = data[0];
+        if (TARGET_TB_PCREL) {
+            env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
+        } else {
+            env->regs[15] = data[0];
+        }
         env->condexec_bits = data[1];
         env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
     }
-- 
2.25.1

Currently the microdrive code uses device_legacy_reset() to reset
itself, and has its reset method call reset on the IDE bus as the
last thing it does.  Switch to using device_cold_reset().

The only concrete microdrive device is the TYPE_DSCM1XXXX; it is not
command-line pluggable, so it is used only by the old pxa2xx Arm
boards 'akita', 'borzoi', 'spitz', 'terrier' and 'tosa'.

You might think that this would result in the IDE bus being
reset automatically, but it does not, because the IDEBus type
does not set the BusClass::reset method. Instead the controller
must explicitly call ide_bus_reset(). We therefore leave that
call in md_reset().

Note also that because the PCMCIA card device is a direct subclass of
TYPE_DEVICE and we don't model the PCMCIA controller-to-card
interface as a qbus, PCMCIA cards are not on any qbus and so they
don't get reset when the system is reset.  The reset only happens via
the dscm1xxxx_attach() and dscm1xxxx_detach() functions during
machine creation.

Because our aim here is merely to try to get rid of calls to the
device_legacy_reset() function, we leave these other dubious
reset-related issues alone.  (They all stem from this code being
absolutely ancient.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221013174042.1602926-1-peter.maydell@linaro.org
---
 hw/ide/microdrive.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ide/microdrive.c
+++ b/hw/ide/microdrive.c
@@ -XXX,XX +XXX,XX @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
     case 0x00:	/* Configuration Option Register */
         s->opt = value & 0xcf;
         if (value & OPT_SRESET) {
-            device_legacy_reset(DEVICE(s));
+            device_cold_reset(DEVICE(s));
         }
         md_interrupt_update(s);
         break;
@@ -XXX,XX +XXX,XX @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
     case 0xe:	/* Device Control */
         s->ctrl = value;
         if (value & CTRL_SRST) {
-            device_legacy_reset(DEVICE(s));
+            device_cold_reset(DEVICE(s));
         }
         md_interrupt_update(s);
         break;
@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_attach(PCMCIACardState *card)
     md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
     md->io_base = 0x0;
 
-    device_legacy_reset(DEVICE(md));
+    device_cold_reset(DEVICE(md));
     md_interrupt_update(md);
 
     return 0;
@@ -XXX,XX +XXX,XX @@ static int dscm1xxxx_detach(PCMCIACardState *card)
 {
     MicroDriveState *md = MICRODRIVE(card);
 
-    device_legacy_reset(DEVICE(md));
+    device_cold_reset(DEVICE(md));
     return 0;
 }
 
-- 
2.25.1