[Qemu-devel] [PULL 00/13] target-arm queue
[PULL 00/10] target-arm queue
1
Arm patch queue -- these are all bug fix patches but we might
1
Hi; not so many patches in this one, but notably it includes the
2
as well put them in to rc0...
2
fix for various Avocado CI tests failing (incorrectly reported by
3
Avocado as a timeout, but really a QEMU exit-with-error).
3
4
4
thanks
5
thanks
5
-- PMM
6
-- PMM
6
7
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
8
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
8
9
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
10
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
10
11
11
are available in the Git repository at:
12
are available in the Git repository at:
12
13
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
14
15
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
16
for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
16
17
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
18
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
18
19
19
----------------------------------------------------------------
20
----------------------------------------------------------------
20
target-arm queue:
21
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
22
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
22
* dump: Update correct kdump phys_base field for AArch64
23
PMCNTENSET_EL0 or PMCNTENCLR_EL0
23
* char: i.MX: Add support for "TX complete" interrupt
24
* Make writes to MDCR_EL3 use PMU start/finish calls
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
25
* Let AArch32 write to SDCR.SCCD
25
to boot a Debian Linux kernel on raspi3
26
* Rearrange cpu64.c so all the CPU initfns are together
27
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
28
* hw/arm/virt: fix some minor issues with generated device tree
29
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
26
30
27
----------------------------------------------------------------
31
----------------------------------------------------------------
28
Andrey Smirnov (2):
32
Francisco Iglesias (1):
29
char: i.MX: Simplify imx_update()
33
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
30
char: i.MX: Add support for "TX complete" interrupt
31
34
32
Guenter Roeck (1):
35
Jean-Philippe Brucker (4):
33
fsl-imx6: Swap Ethernet interrupt defines
36
hw/arm/virt: Fix devicetree warning about the root node
37
hw/arm/virt: Fix devicetree warning about the GIC node
38
hw/arm/virt: Use "msi-map" devicetree property for PCI
39
hw/arm/virt: Fix devicetree warning about the SMMU node
34
40
35
Peter Maydell (9):
41
Jerome Forissier (1):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
42
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
39
hw/arm/bcm2386: Fix parent type of bcm2386
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
41
hw/arm/bcm2836: Create proper bcm2837 device
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
43
hw/arm/bcm2836: Hardcode correct CPU type
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
43
46
Wei Huang (1):
44
Peter Maydell (4):
47
dump: Update correct kdump phys_base field for AArch64
45
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
46
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
47
target/arm: Update SDCR_VALID_MASK to include SCCD
48
target/arm: Rearrange cpu64.c so all the CPU initfns are together
48
49
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
50
include/hw/arm/xlnx-zynqmp.h | 3 +
50
include/hw/arm/fsl-imx6.h | 4 +-
51
target/arm/cpu.h | 8 +-
51
include/hw/char/imx_serial.h | 3 ++
52
hw/arm/virt.c | 8 +-
52
dump.c | 14 +++++--
53
hw/arm/xlnx-zynqmp.c | 36 +++
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
54
target/arm/cpu64.c | 712 +++++++++++++++++++++----------------------
54
hw/arm/boot.c | 12 ++++++
55
target/arm/helper.c | 32 +-
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
56
6 files changed, 427 insertions(+), 372 deletions(-)
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
57
hw/net/imx_fec.c | 28 +++++++++++++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
59
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
[PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
In commit 01765386a888 we made some system register write functions
2
just hard-code the CPU type they use rather than having it passed
2
call pmu_op_start()/pmu_op_finish(). This means that they now touch
3
through as an object property. This then lets us put the initialization
3
timers, so for icount to work these registers must have the ARM_CP_IO
4
of the CPU object in init rather than realize.
4
flag set.
5
5
6
Note that this change means that it's no longer possible on
6
This fixes a bug where when icount is enabled a guest that touches
7
the command line to use -cpu to ask for a different kind of
7
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
8
CPU than the SoC supports. This was never a supported thing to
8
QEMU to print an error message and exit, for example:
9
do anyway; we were just not sanity-checking the command line.
10
9
11
This does require us to only build the bcm2837 object on
10
[ 2.495971] TCP: Hash tables configured (established 1024 bind 1024)
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
11
[ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
13
due to the missing cortex-a53 device and "make check" will fail.
12
[ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
13
[ 2.496917] NET: Registered protocol family 1
14
qemu-system-aarch64: Bad icount read
14
15
16
Reported-by: Thomas Huth <thuth@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
20
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
21
target/arm/helper.c | 12 ++++++------
21
hw/arm/raspi.c | 2 --
22
1 file changed, 6 insertions(+), 6 deletions(-)
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
23
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
24
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
26
--- a/target/arm/helper.c
27
+++ b/hw/arm/bcm2836.c
27
+++ b/target/arm/helper.c
28
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
29
29
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
30
struct BCM283XInfo {
30
*/
31
const char *name;
31
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
32
+ const char *cpu_type;
32
- .access = PL0_RW, .type = ARM_CP_ALIAS,
33
int clusterid;
33
+ .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
34
};
34
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
35
35
.writefn = pmcntenset_write,
36
static const BCM283XInfo bcm283x_socs[] = {
36
.accessfn = pmreg_access,
37
{
37
.raw_writefn = raw_write },
38
.name = TYPE_BCM2836,
38
- { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
39
+ { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
40
.clusterid = 0xf,
40
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
41
},
41
.access = PL0_RW, .accessfn = pmreg_access,
42
+#ifdef TARGET_AARCH64
42
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
43
{
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
44
.name = TYPE_BCM2837,
44
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
45
.accessfn = pmreg_access,
46
.clusterid = 0x0,
46
.writefn = pmcntenclr_write,
47
},
47
- .type = ARM_CP_ALIAS },
48
+#endif
48
+ .type = ARM_CP_ALIAS | ARM_CP_IO },
49
};
49
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
50
50
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
51
static void bcm2836_init(Object *obj)
51
.access = PL0_RW, .accessfn = pmreg_access,
52
{
52
- .type = ARM_CP_ALIAS,
53
BCM283XState *s = BCM283X(obj);
53
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
54
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
55
+ const BCM283XInfo *info = bc->info;
55
.writefn = pmcntenclr_write },
56
+ int n;
56
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
57
+
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
58
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
59
.resetvalue = 0,
60
+ info->cpu_type);
60
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
61
- { .name = "SDCR", .type = ARM_CP_ALIAS,
62
+ &error_abort);
62
+ { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
63
+ }
63
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
64
64
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
.writefn = sdcr_write,
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
67
* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
68
68
*/
69
/* common peripherals from bcm2835 */
69
ARMCPRegInfo mdcr_el2 = {
70
70
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
71
- obj = OBJECT(dev);
71
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
72
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
73
.writefn = mdcr_el2_write,
74
- s->cpu_type);
74
.access = PL2_RW, .resetvalue = pmu_num_counters(env),
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
84
85
static Property bcm2836_props[] = {
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
75
--
104
2.16.2
76
2.25.1
105
106
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
In commit 01765386a88868 we fixed a bug where we weren't correctly
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
2
bracketing changes to some registers with pmu_op_start() and
3
is required for Linux to boot.
3
pmu_op_finish() calls for changes which affect whether the PMU
4
counters might be enabled. However, we missed the case of writes to
5
the AArch64 MDCR_EL3 register, because (unlike its AArch32
6
counterpart) they are currently done directly to the CPU state struct
7
without going through the sdcr_write() function.
8
9
Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
10
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
11
masking off the bits which don't exist in the AArch32 register".
4
12
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
9
---
16
---
10
hw/arm/bcm2836.c | 11 +++++++----
17
target/arm/helper.c | 18 ++++++++++++++----
11
1 file changed, 7 insertions(+), 4 deletions(-)
18
1 file changed, 14 insertions(+), 4 deletions(-)
12
19
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
22
--- a/target/arm/helper.c
16
+++ b/hw/arm/bcm2836.c
23
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
25
}
19
struct BCM283XInfo {
26
}
20
const char *name;
27
21
+ int clusterid;
28
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
22
};
29
- uint64_t value)
23
30
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
24
static const BCM283XInfo bcm283x_socs[] = {
31
+ uint64_t value)
25
{
26
.name = TYPE_BCM2836,
27
+ .clusterid = 0xf,
28
},
29
{
30
.name = TYPE_BCM2837,
31
+ .clusterid = 0x0,
32
},
33
};
34
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
37
{
32
{
38
BCM283XState *s = BCM283X(dev);
33
/*
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
34
* Some MDCR_EL3 bits affect whether PMU counters are running:
40
+ const BCM283XInfo *info = bc->info;
35
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
41
Object *obj;
36
if (pmu_op) {
42
Error *err = NULL;
37
pmu_op_start(env);
43
int n;
38
}
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
39
- env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
40
+ env->cp15.mdcr_el3 = value;
46
41
if (pmu_op) {
47
for (n = 0; n < BCM283X_NCPUS; n++) {
42
pmu_op_finish(env);
48
- /* Mirror bcm2836, which has clusterid set to 0xf
43
}
49
- * TODO: this should be converted to a property of ARM_CPU
44
}
50
- */
45
51
- s->cpus[n].mp_affinity = 0xF00 | n;
46
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
52
+ /* TODO: this should be converted to a property of ARM_CPU */
47
+ uint64_t value)
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
48
+{
54
49
+ /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
55
/* set periphbase/CBAR value for CPU-local registers */
50
+ mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
56
object_property_set_int(OBJECT(&s->cpus[n]),
51
+}
52
+
53
static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
54
uint64_t value)
55
{
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
57
.access = PL2_RW,
58
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
59
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
60
+ .type = ARM_CP_IO,
61
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
62
.resetvalue = 0,
63
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
64
+ .access = PL3_RW,
65
+ .writefn = mdcr_el3_write,
66
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
67
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
68
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
69
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
57
--
70
--
58
2.16.2
71
2.25.1
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
1
Our BCM2836 type is really a generic one that can be any of
1
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
2
the bcm283x family. Rename it accordingly. We change only
2
by the current architecture. In particular in commit 0b42f4fab9d3 we
3
the names which are visible via the header file to the
3
forgot to add SCCD, which meant that an AArch32 guest couldn't
4
rest of the QEMU code, leaving private function names
4
actually use the SCCD bit to disable counting in Secure state.
5
in bcm2836.c as they are.
6
5
7
This is a preliminary to making bcm283x be an abstract
6
Add all the currently defined bits; we don't implement all of them,
8
parent class to specific types for the bcm2836 and bcm2837.
7
but this makes them be reads-as-written, which is architecturally
8
valid and matches how we currently handle most of the others in the
9
mask.
9
10
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
14
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
15
target/arm/cpu.h | 8 +++++++-
16
hw/arm/bcm2836.c | 17 +++++++++--------
16
1 file changed, 7 insertions(+), 1 deletion(-)
17
hw/arm/raspi.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
17
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
20
--- a/target/arm/cpu.h
23
+++ b/include/hw/arm/bcm2836.h
21
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
25
#include "hw/arm/bcm2835_peripherals.h"
23
FIELD(CPTR_EL3, TAM, 30, 1)
26
#include "hw/intc/bcm2836_control.h"
24
FIELD(CPTR_EL3, TCPAC, 31, 1)
27
25
28
-#define TYPE_BCM2836 "bcm2836"
26
+#define MDCR_MTPME (1U << 28)
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
27
+#define MDCR_TDCC (1U << 27)
30
+#define TYPE_BCM283X "bcm283x"
28
#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
29
#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
32
30
#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
33
-#define BCM2836_NCPUS 4
31
#define MDCR_EPMAD (1U << 21)
34
+#define BCM283X_NCPUS 4
32
#define MDCR_EDAD (1U << 20)
35
33
+#define MDCR_TTRF (1U << 19)
36
-typedef struct BCM2836State {
34
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
37
+typedef struct BCM283XState {
35
#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
38
/*< private >*/
36
#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
39
DeviceState parent_obj;
37
#define MDCR_SDD (1U << 16)
40
/*< public >*/
38
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
39
#define MDCR_HPMN (0x1fU)
42
char *cpu_type;
40
43
uint32_t enabled_cpus;
41
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
44
42
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
45
- ARMCPU cpus[BCM2836_NCPUS];
43
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
46
+ ARMCPU cpus[BCM283X_NCPUS];
44
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
47
BCM2836ControlState control;
45
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
48
BCM2835PeripheralState peripherals;
46
49
-} BCM2836State;
47
#define CPSR_M (0x1fU)
50
+} BCM283XState;
48
#define CPSR_T (1U << 5)
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
56
+++ b/hw/arm/bcm2836.c
57
@@ -XXX,XX +XXX,XX @@
58
59
static void bcm2836_init(Object *obj)
60
{
61
- BCM2836State *s = BCM2836(obj);
62
+ BCM283XState *s = BCM283X(obj);
63
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
67
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
69
{
70
- BCM2836State *s = BCM2836(dev);
71
+ BCM283XState *s = BCM283X(dev);
72
Object *obj;
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
95
96
static Property bcm2836_props[] = {
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
101
+ BCM283X_NCPUS),
102
DEFINE_PROP_END_OF_LIST()
103
};
104
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
106
}
107
108
static const TypeInfo bcm2836_type_info = {
109
- .name = TYPE_BCM2836,
110
+ .name = TYPE_BCM283X,
111
.parent = TYPE_DEVICE,
112
- .instance_size = sizeof(BCM2836State),
113
+ .instance_size = sizeof(BCM283XState),
114
.instance_init = bcm2836_init,
115
.class_init = bcm2836_class_init,
116
};
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/arm/raspi.c
120
+++ b/hw/arm/raspi.c
121
@@ -XXX,XX +XXX,XX @@
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
123
124
typedef struct RasPiState {
125
- BCM2836State soc;
126
+ BCM283XState soc;
127
MemoryRegion ram;
128
} RasPiState;
129
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
165
--
49
--
166
2.16.2
50
2.25.1
167
168
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
[PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
cpu64.c has ended up in a slightly odd order -- it starts with the
2
code for keeping the secondary CPUs in a pen needs to have
2
initfns for most of the models-real-hardware CPUs; after that comes a
3
a version for A64 as well as A32. Without this, the
3
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
4
secondary CPUs go into an infinite loop of taking undefined
4
come the initfns for the 'host' and 'max' CPU types, and then after
5
instruction exceptions.
5
that one more models-real-hardware CPU initfn, for a64fx. (This
6
ordering is partly historical and partly required because a64fx needs
7
the SVE properties.)
8
9
Reorder the file into:
10
* CPU property support functions
11
* initfns for real hardware CPUs
12
* initfns for host and max
13
* class boilerplate
6
14
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
---
18
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
19
target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
12
1 file changed, 40 insertions(+), 1 deletion(-)
20
1 file changed, 356 insertions(+), 356 deletions(-)
13
21
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
22
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
24
--- a/target/arm/cpu64.c
17
+++ b/hw/arm/raspi.c
25
+++ b/target/arm/cpu64.c
18
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
27
define_cortex_a72_a57_a53_cp_reginfo(cpu);
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
23
24
/* Table of Linux board IDs for different Pi versions */
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
27
info->smp_loader_start);
28
}
28
}
29
29
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
30
-static void aarch64_a57_initfn(Object *obj)
31
-{
32
- ARMCPU *cpu = ARM_CPU(obj);
33
-
34
- cpu->dtb_compatible = "arm,cortex-a57";
35
- set_feature(&cpu->env, ARM_FEATURE_V8);
36
- set_feature(&cpu->env, ARM_FEATURE_NEON);
37
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40
- set_feature(&cpu->env, ARM_FEATURE_EL2);
41
- set_feature(&cpu->env, ARM_FEATURE_EL3);
42
- set_feature(&cpu->env, ARM_FEATURE_PMU);
43
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
44
- cpu->midr = 0x411fd070;
45
- cpu->revidr = 0x00000000;
46
- cpu->reset_fpsid = 0x41034070;
47
- cpu->isar.mvfr0 = 0x10110222;
48
- cpu->isar.mvfr1 = 0x12111111;
49
- cpu->isar.mvfr2 = 0x00000043;
50
- cpu->ctr = 0x8444c004;
51
- cpu->reset_sctlr = 0x00c50838;
52
- cpu->isar.id_pfr0 = 0x00000131;
53
- cpu->isar.id_pfr1 = 0x00011011;
54
- cpu->isar.id_dfr0 = 0x03010066;
55
- cpu->id_afr0 = 0x00000000;
56
- cpu->isar.id_mmfr0 = 0x10101105;
57
- cpu->isar.id_mmfr1 = 0x40000000;
58
- cpu->isar.id_mmfr2 = 0x01260000;
59
- cpu->isar.id_mmfr3 = 0x02102211;
60
- cpu->isar.id_isar0 = 0x02101110;
61
- cpu->isar.id_isar1 = 0x13112111;
62
- cpu->isar.id_isar2 = 0x21232042;
63
- cpu->isar.id_isar3 = 0x01112131;
64
- cpu->isar.id_isar4 = 0x00011142;
65
- cpu->isar.id_isar5 = 0x00011121;
66
- cpu->isar.id_isar6 = 0;
67
- cpu->isar.id_aa64pfr0 = 0x00002222;
68
- cpu->isar.id_aa64dfr0 = 0x10305106;
69
- cpu->isar.id_aa64isar0 = 0x00011120;
70
- cpu->isar.id_aa64mmfr0 = 0x00001124;
71
- cpu->isar.dbgdidr = 0x3516d000;
72
- cpu->isar.dbgdevid = 0x01110f13;
73
- cpu->isar.dbgdevid1 = 0x2;
74
- cpu->isar.reset_pmcr_el0 = 0x41013000;
75
- cpu->clidr = 0x0a200023;
76
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
77
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
78
- cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
79
- cpu->dcz_blocksize = 4; /* 64 bytes */
80
- cpu->gic_num_lrs = 4;
81
- cpu->gic_vpribits = 5;
82
- cpu->gic_vprebits = 5;
83
- cpu->gic_pribits = 5;
84
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
85
-}
86
-
87
-static void aarch64_a53_initfn(Object *obj)
88
-{
89
- ARMCPU *cpu = ARM_CPU(obj);
90
-
91
- cpu->dtb_compatible = "arm,cortex-a53";
92
- set_feature(&cpu->env, ARM_FEATURE_V8);
93
- set_feature(&cpu->env, ARM_FEATURE_NEON);
94
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
95
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
96
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
97
- set_feature(&cpu->env, ARM_FEATURE_EL2);
98
- set_feature(&cpu->env, ARM_FEATURE_EL3);
99
- set_feature(&cpu->env, ARM_FEATURE_PMU);
100
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
101
- cpu->midr = 0x410fd034;
102
- cpu->revidr = 0x00000000;
103
- cpu->reset_fpsid = 0x41034070;
104
- cpu->isar.mvfr0 = 0x10110222;
105
- cpu->isar.mvfr1 = 0x12111111;
106
- cpu->isar.mvfr2 = 0x00000043;
107
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
108
- cpu->reset_sctlr = 0x00c50838;
109
- cpu->isar.id_pfr0 = 0x00000131;
110
- cpu->isar.id_pfr1 = 0x00011011;
111
- cpu->isar.id_dfr0 = 0x03010066;
112
- cpu->id_afr0 = 0x00000000;
113
- cpu->isar.id_mmfr0 = 0x10101105;
114
- cpu->isar.id_mmfr1 = 0x40000000;
115
- cpu->isar.id_mmfr2 = 0x01260000;
116
- cpu->isar.id_mmfr3 = 0x02102211;
117
- cpu->isar.id_isar0 = 0x02101110;
118
- cpu->isar.id_isar1 = 0x13112111;
119
- cpu->isar.id_isar2 = 0x21232042;
120
- cpu->isar.id_isar3 = 0x01112131;
121
- cpu->isar.id_isar4 = 0x00011142;
122
- cpu->isar.id_isar5 = 0x00011121;
123
- cpu->isar.id_isar6 = 0;
124
- cpu->isar.id_aa64pfr0 = 0x00002222;
125
- cpu->isar.id_aa64dfr0 = 0x10305106;
126
- cpu->isar.id_aa64isar0 = 0x00011120;
127
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
128
- cpu->isar.dbgdidr = 0x3516d000;
129
- cpu->isar.dbgdevid = 0x00110f13;
130
- cpu->isar.dbgdevid1 = 0x1;
131
- cpu->isar.reset_pmcr_el0 = 0x41033000;
132
- cpu->clidr = 0x0a200023;
133
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
134
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
135
- cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
136
- cpu->dcz_blocksize = 4; /* 64 bytes */
137
- cpu->gic_num_lrs = 4;
138
- cpu->gic_vpribits = 5;
139
- cpu->gic_vprebits = 5;
140
- cpu->gic_pribits = 5;
141
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
142
-}
143
-
144
-static void aarch64_a72_initfn(Object *obj)
145
-{
146
- ARMCPU *cpu = ARM_CPU(obj);
147
-
148
- cpu->dtb_compatible = "arm,cortex-a72";
149
- set_feature(&cpu->env, ARM_FEATURE_V8);
150
- set_feature(&cpu->env, ARM_FEATURE_NEON);
151
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
152
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
153
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
154
- set_feature(&cpu->env, ARM_FEATURE_EL2);
155
- set_feature(&cpu->env, ARM_FEATURE_EL3);
156
- set_feature(&cpu->env, ARM_FEATURE_PMU);
157
- cpu->midr = 0x410fd083;
158
- cpu->revidr = 0x00000000;
159
- cpu->reset_fpsid = 0x41034080;
160
- cpu->isar.mvfr0 = 0x10110222;
161
- cpu->isar.mvfr1 = 0x12111111;
162
- cpu->isar.mvfr2 = 0x00000043;
163
- cpu->ctr = 0x8444c004;
164
- cpu->reset_sctlr = 0x00c50838;
165
- cpu->isar.id_pfr0 = 0x00000131;
166
- cpu->isar.id_pfr1 = 0x00011011;
167
- cpu->isar.id_dfr0 = 0x03010066;
168
- cpu->id_afr0 = 0x00000000;
169
- cpu->isar.id_mmfr0 = 0x10201105;
170
- cpu->isar.id_mmfr1 = 0x40000000;
171
- cpu->isar.id_mmfr2 = 0x01260000;
172
- cpu->isar.id_mmfr3 = 0x02102211;
173
- cpu->isar.id_isar0 = 0x02101110;
174
- cpu->isar.id_isar1 = 0x13112111;
175
- cpu->isar.id_isar2 = 0x21232042;
176
- cpu->isar.id_isar3 = 0x01112131;
177
- cpu->isar.id_isar4 = 0x00011142;
178
- cpu->isar.id_isar5 = 0x00011121;
179
- cpu->isar.id_aa64pfr0 = 0x00002222;
180
- cpu->isar.id_aa64dfr0 = 0x10305106;
181
- cpu->isar.id_aa64isar0 = 0x00011120;
182
- cpu->isar.id_aa64mmfr0 = 0x00001124;
183
- cpu->isar.dbgdidr = 0x3516d000;
184
- cpu->isar.dbgdevid = 0x01110f13;
185
- cpu->isar.dbgdevid1 = 0x2;
186
- cpu->isar.reset_pmcr_el0 = 0x41023000;
187
- cpu->clidr = 0x0a200023;
188
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
189
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
190
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
191
- cpu->dcz_blocksize = 4; /* 64 bytes */
192
- cpu->gic_num_lrs = 4;
193
- cpu->gic_vpribits = 5;
194
- cpu->gic_vprebits = 5;
195
- cpu->gic_pribits = 5;
196
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
197
-}
198
-
199
-static void aarch64_a76_initfn(Object *obj)
200
-{
201
- ARMCPU *cpu = ARM_CPU(obj);
202
-
203
- cpu->dtb_compatible = "arm,cortex-a76";
204
- set_feature(&cpu->env, ARM_FEATURE_V8);
205
- set_feature(&cpu->env, ARM_FEATURE_NEON);
206
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
207
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
208
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
209
- set_feature(&cpu->env, ARM_FEATURE_EL2);
210
- set_feature(&cpu->env, ARM_FEATURE_EL3);
211
- set_feature(&cpu->env, ARM_FEATURE_PMU);
212
-
213
- /* Ordered by B2.4 AArch64 registers by functional group */
214
- cpu->clidr = 0x82000023;
215
- cpu->ctr = 0x8444C004;
216
- cpu->dcz_blocksize = 4;
217
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
218
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
219
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
220
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
221
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
222
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
223
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
224
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
225
- cpu->id_afr0 = 0x00000000;
226
- cpu->isar.id_dfr0 = 0x04010088;
227
- cpu->isar.id_isar0 = 0x02101110;
228
- cpu->isar.id_isar1 = 0x13112111;
229
- cpu->isar.id_isar2 = 0x21232042;
230
- cpu->isar.id_isar3 = 0x01112131;
231
- cpu->isar.id_isar4 = 0x00010142;
232
- cpu->isar.id_isar5 = 0x01011121;
233
- cpu->isar.id_isar6 = 0x00000010;
234
- cpu->isar.id_mmfr0 = 0x10201105;
235
- cpu->isar.id_mmfr1 = 0x40000000;
236
- cpu->isar.id_mmfr2 = 0x01260000;
237
- cpu->isar.id_mmfr3 = 0x02122211;
238
- cpu->isar.id_mmfr4 = 0x00021110;
239
- cpu->isar.id_pfr0 = 0x10010131;
240
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
241
- cpu->isar.id_pfr2 = 0x00000011;
242
- cpu->midr = 0x414fd0b1; /* r4p1 */
243
- cpu->revidr = 0;
244
-
245
- /* From B2.18 CCSIDR_EL1 */
246
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
247
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
248
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
249
-
250
- /* From B2.93 SCTLR_EL3 */
251
- cpu->reset_sctlr = 0x30c50838;
252
-
253
- /* From B4.23 ICH_VTR_EL2 */
254
- cpu->gic_num_lrs = 4;
255
- cpu->gic_vpribits = 5;
256
- cpu->gic_vprebits = 5;
257
- cpu->gic_pribits = 5;
258
-
259
- /* From B5.1 AdvSIMD AArch64 register summary */
260
- cpu->isar.mvfr0 = 0x10110222;
261
- cpu->isar.mvfr1 = 0x13211111;
262
- cpu->isar.mvfr2 = 0x00000043;
263
-
264
- /* From D5.1 AArch64 PMU register summary */
265
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
266
-}
267
-
268
-static void aarch64_neoverse_n1_initfn(Object *obj)
269
-{
270
- ARMCPU *cpu = ARM_CPU(obj);
271
-
272
- cpu->dtb_compatible = "arm,neoverse-n1";
273
- set_feature(&cpu->env, ARM_FEATURE_V8);
274
- set_feature(&cpu->env, ARM_FEATURE_NEON);
275
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
277
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
278
- set_feature(&cpu->env, ARM_FEATURE_EL2);
279
- set_feature(&cpu->env, ARM_FEATURE_EL3);
280
- set_feature(&cpu->env, ARM_FEATURE_PMU);
281
-
282
- /* Ordered by B2.4 AArch64 registers by functional group */
283
- cpu->clidr = 0x82000023;
284
- cpu->ctr = 0x8444c004;
285
- cpu->dcz_blocksize = 4;
286
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
287
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
288
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
289
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
290
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
291
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
292
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
293
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
294
- cpu->id_afr0 = 0x00000000;
295
- cpu->isar.id_dfr0 = 0x04010088;
296
- cpu->isar.id_isar0 = 0x02101110;
297
- cpu->isar.id_isar1 = 0x13112111;
298
- cpu->isar.id_isar2 = 0x21232042;
299
- cpu->isar.id_isar3 = 0x01112131;
300
- cpu->isar.id_isar4 = 0x00010142;
301
- cpu->isar.id_isar5 = 0x01011121;
302
- cpu->isar.id_isar6 = 0x00000010;
303
- cpu->isar.id_mmfr0 = 0x10201105;
304
- cpu->isar.id_mmfr1 = 0x40000000;
305
- cpu->isar.id_mmfr2 = 0x01260000;
306
- cpu->isar.id_mmfr3 = 0x02122211;
307
- cpu->isar.id_mmfr4 = 0x00021110;
308
- cpu->isar.id_pfr0 = 0x10010131;
309
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
310
- cpu->isar.id_pfr2 = 0x00000011;
311
- cpu->midr = 0x414fd0c1; /* r4p1 */
312
- cpu->revidr = 0;
313
-
314
- /* From B2.23 CCSIDR_EL1 */
315
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
316
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
317
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
318
-
319
- /* From B2.98 SCTLR_EL3 */
320
- cpu->reset_sctlr = 0x30c50838;
321
-
322
- /* From B4.23 ICH_VTR_EL2 */
323
- cpu->gic_num_lrs = 4;
324
- cpu->gic_vpribits = 5;
325
- cpu->gic_vprebits = 5;
326
- cpu->gic_pribits = 5;
327
-
328
- /* From B5.1 AdvSIMD AArch64 register summary */
329
- cpu->isar.mvfr0 = 0x10110222;
330
- cpu->isar.mvfr1 = 0x13211111;
331
- cpu->isar.mvfr2 = 0x00000043;
332
-
333
- /* From D5.1 AArch64 PMU register summary */
334
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
335
-}
336
-
337
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
338
{
339
/*
340
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
341
cpu->isar.id_aa64mmfr0 = t;
342
}
343
344
+static void aarch64_a57_initfn(Object *obj)
31
+{
345
+{
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
346
+ ARMCPU *cpu = ARM_CPU(obj);
33
+ * The mechanism for doing the spin-table is also entirely different.
347
+
34
+ * We must have four 64-bit fields at absolute addresses
348
+ cpu->dtb_compatible = "arm,cortex-a57";
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
349
+ set_feature(&cpu->env, ARM_FEATURE_V8);
36
+ * our CPUs, and which we must ensure are zero initialized before
350
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
37
+ * the primary CPU goes into the kernel. We put these variables inside
351
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
352
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39
+ */
353
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40
+ static const uint32_t smpboot[] = {
354
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
41
+ 0xd2801b05, /* mov x5, 0xd8 */
355
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
356
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
43
+ 0x924004c6, /* and x6, x6, #0x3 */
357
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
44
+ 0xd503205f, /* spin: wfe */
358
+ cpu->midr = 0x411fd070;
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
359
+ cpu->revidr = 0x00000000;
46
+ 0xb4ffffc4, /* cbz x4, spin */
360
+ cpu->reset_fpsid = 0x41034070;
47
+ 0xd2800000, /* mov x0, #0x0 */
361
+ cpu->isar.mvfr0 = 0x10110222;
48
+ 0xd2800001, /* mov x1, #0x0 */
362
+ cpu->isar.mvfr1 = 0x12111111;
49
+ 0xd2800002, /* mov x2, #0x0 */
363
+ cpu->isar.mvfr2 = 0x00000043;
50
+ 0xd2800003, /* mov x3, #0x0 */
364
+ cpu->ctr = 0x8444c004;
51
+ 0xd61f0080, /* br x4 */
365
+ cpu->reset_sctlr = 0x00c50838;
52
+ };
366
+ cpu->isar.id_pfr0 = 0x00000131;
53
+
367
+ cpu->isar.id_pfr1 = 0x00011011;
54
+ static const uint64_t spintables[] = {
368
+ cpu->isar.id_dfr0 = 0x03010066;
55
+ 0, 0, 0, 0
369
+ cpu->id_afr0 = 0x00000000;
56
+ };
370
+ cpu->isar.id_mmfr0 = 0x10101105;
57
+
371
+ cpu->isar.id_mmfr1 = 0x40000000;
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
372
+ cpu->isar.id_mmfr2 = 0x01260000;
59
+ info->smp_loader_start);
373
+ cpu->isar.id_mmfr3 = 0x02102211;
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
374
+ cpu->isar.id_isar0 = 0x02101110;
61
+ SPINTABLE_ADDR);
375
+ cpu->isar.id_isar1 = 0x13112111;
376
+ cpu->isar.id_isar2 = 0x21232042;
377
+ cpu->isar.id_isar3 = 0x01112131;
378
+ cpu->isar.id_isar4 = 0x00011142;
379
+ cpu->isar.id_isar5 = 0x00011121;
380
+ cpu->isar.id_isar6 = 0;
381
+ cpu->isar.id_aa64pfr0 = 0x00002222;
382
+ cpu->isar.id_aa64dfr0 = 0x10305106;
383
+ cpu->isar.id_aa64isar0 = 0x00011120;
384
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
385
+ cpu->isar.dbgdidr = 0x3516d000;
386
+ cpu->isar.dbgdevid = 0x01110f13;
387
+ cpu->isar.dbgdevid1 = 0x2;
388
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
389
+ cpu->clidr = 0x0a200023;
390
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
391
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
392
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
393
+ cpu->dcz_blocksize = 4; /* 64 bytes */
394
+ cpu->gic_num_lrs = 4;
395
+ cpu->gic_vpribits = 5;
396
+ cpu->gic_vprebits = 5;
397
+ cpu->gic_pribits = 5;
398
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
62
+}
399
+}
63
+
400
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
401
+static void aarch64_a53_initfn(Object *obj)
402
+{
403
+ ARMCPU *cpu = ARM_CPU(obj);
404
+
405
+ cpu->dtb_compatible = "arm,cortex-a53";
406
+ set_feature(&cpu->env, ARM_FEATURE_V8);
407
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
408
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
409
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
410
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
411
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
412
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
413
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
414
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
415
+ cpu->midr = 0x410fd034;
416
+ cpu->revidr = 0x00000000;
417
+ cpu->reset_fpsid = 0x41034070;
418
+ cpu->isar.mvfr0 = 0x10110222;
419
+ cpu->isar.mvfr1 = 0x12111111;
420
+ cpu->isar.mvfr2 = 0x00000043;
421
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
422
+ cpu->reset_sctlr = 0x00c50838;
423
+ cpu->isar.id_pfr0 = 0x00000131;
424
+ cpu->isar.id_pfr1 = 0x00011011;
425
+ cpu->isar.id_dfr0 = 0x03010066;
426
+ cpu->id_afr0 = 0x00000000;
427
+ cpu->isar.id_mmfr0 = 0x10101105;
428
+ cpu->isar.id_mmfr1 = 0x40000000;
429
+ cpu->isar.id_mmfr2 = 0x01260000;
430
+ cpu->isar.id_mmfr3 = 0x02102211;
431
+ cpu->isar.id_isar0 = 0x02101110;
432
+ cpu->isar.id_isar1 = 0x13112111;
433
+ cpu->isar.id_isar2 = 0x21232042;
434
+ cpu->isar.id_isar3 = 0x01112131;
435
+ cpu->isar.id_isar4 = 0x00011142;
436
+ cpu->isar.id_isar5 = 0x00011121;
437
+ cpu->isar.id_isar6 = 0;
438
+ cpu->isar.id_aa64pfr0 = 0x00002222;
439
+ cpu->isar.id_aa64dfr0 = 0x10305106;
440
+ cpu->isar.id_aa64isar0 = 0x00011120;
441
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
442
+ cpu->isar.dbgdidr = 0x3516d000;
443
+ cpu->isar.dbgdevid = 0x00110f13;
444
+ cpu->isar.dbgdevid1 = 0x1;
445
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
446
+ cpu->clidr = 0x0a200023;
447
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
448
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
449
+ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
450
+ cpu->dcz_blocksize = 4; /* 64 bytes */
451
+ cpu->gic_num_lrs = 4;
452
+ cpu->gic_vpribits = 5;
453
+ cpu->gic_vprebits = 5;
454
+ cpu->gic_pribits = 5;
455
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
456
+}
457
+
458
+static void aarch64_a72_initfn(Object *obj)
459
+{
460
+ ARMCPU *cpu = ARM_CPU(obj);
461
+
462
+ cpu->dtb_compatible = "arm,cortex-a72";
463
+ set_feature(&cpu->env, ARM_FEATURE_V8);
464
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
465
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
466
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
467
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
468
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
469
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
470
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
471
+ cpu->midr = 0x410fd083;
472
+ cpu->revidr = 0x00000000;
473
+ cpu->reset_fpsid = 0x41034080;
474
+ cpu->isar.mvfr0 = 0x10110222;
475
+ cpu->isar.mvfr1 = 0x12111111;
476
+ cpu->isar.mvfr2 = 0x00000043;
477
+ cpu->ctr = 0x8444c004;
478
+ cpu->reset_sctlr = 0x00c50838;
479
+ cpu->isar.id_pfr0 = 0x00000131;
480
+ cpu->isar.id_pfr1 = 0x00011011;
481
+ cpu->isar.id_dfr0 = 0x03010066;
482
+ cpu->id_afr0 = 0x00000000;
483
+ cpu->isar.id_mmfr0 = 0x10201105;
484
+ cpu->isar.id_mmfr1 = 0x40000000;
485
+ cpu->isar.id_mmfr2 = 0x01260000;
486
+ cpu->isar.id_mmfr3 = 0x02102211;
487
+ cpu->isar.id_isar0 = 0x02101110;
488
+ cpu->isar.id_isar1 = 0x13112111;
489
+ cpu->isar.id_isar2 = 0x21232042;
490
+ cpu->isar.id_isar3 = 0x01112131;
491
+ cpu->isar.id_isar4 = 0x00011142;
492
+ cpu->isar.id_isar5 = 0x00011121;
493
+ cpu->isar.id_aa64pfr0 = 0x00002222;
494
+ cpu->isar.id_aa64dfr0 = 0x10305106;
495
+ cpu->isar.id_aa64isar0 = 0x00011120;
496
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
497
+ cpu->isar.dbgdidr = 0x3516d000;
498
+ cpu->isar.dbgdevid = 0x01110f13;
499
+ cpu->isar.dbgdevid1 = 0x2;
500
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
501
+ cpu->clidr = 0x0a200023;
502
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
503
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
504
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
505
+ cpu->dcz_blocksize = 4; /* 64 bytes */
506
+ cpu->gic_num_lrs = 4;
507
+ cpu->gic_vpribits = 5;
508
+ cpu->gic_vprebits = 5;
509
+ cpu->gic_pribits = 5;
510
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
511
+}
512
+
513
+static void aarch64_a76_initfn(Object *obj)
514
+{
515
+ ARMCPU *cpu = ARM_CPU(obj);
516
+
517
+ cpu->dtb_compatible = "arm,cortex-a76";
518
+ set_feature(&cpu->env, ARM_FEATURE_V8);
519
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
520
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
521
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
522
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
523
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
524
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
525
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
526
+
527
+ /* Ordered by B2.4 AArch64 registers by functional group */
528
+ cpu->clidr = 0x82000023;
529
+ cpu->ctr = 0x8444C004;
530
+ cpu->dcz_blocksize = 4;
531
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
532
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
533
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
534
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
535
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
536
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
537
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
538
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
539
+ cpu->id_afr0 = 0x00000000;
540
+ cpu->isar.id_dfr0 = 0x04010088;
541
+ cpu->isar.id_isar0 = 0x02101110;
542
+ cpu->isar.id_isar1 = 0x13112111;
543
+ cpu->isar.id_isar2 = 0x21232042;
544
+ cpu->isar.id_isar3 = 0x01112131;
545
+ cpu->isar.id_isar4 = 0x00010142;
546
+ cpu->isar.id_isar5 = 0x01011121;
547
+ cpu->isar.id_isar6 = 0x00000010;
548
+ cpu->isar.id_mmfr0 = 0x10201105;
549
+ cpu->isar.id_mmfr1 = 0x40000000;
550
+ cpu->isar.id_mmfr2 = 0x01260000;
551
+ cpu->isar.id_mmfr3 = 0x02122211;
552
+ cpu->isar.id_mmfr4 = 0x00021110;
553
+ cpu->isar.id_pfr0 = 0x10010131;
554
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
555
+ cpu->isar.id_pfr2 = 0x00000011;
556
+ cpu->midr = 0x414fd0b1; /* r4p1 */
557
+ cpu->revidr = 0;
558
+
559
+ /* From B2.18 CCSIDR_EL1 */
560
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
561
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
562
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
563
+
564
+ /* From B2.93 SCTLR_EL3 */
565
+ cpu->reset_sctlr = 0x30c50838;
566
+
567
+ /* From B4.23 ICH_VTR_EL2 */
568
+ cpu->gic_num_lrs = 4;
569
+ cpu->gic_vpribits = 5;
570
+ cpu->gic_vprebits = 5;
571
+ cpu->gic_pribits = 5;
572
+
573
+ /* From B5.1 AdvSIMD AArch64 register summary */
574
+ cpu->isar.mvfr0 = 0x10110222;
575
+ cpu->isar.mvfr1 = 0x13211111;
576
+ cpu->isar.mvfr2 = 0x00000043;
577
+
578
+ /* From D5.1 AArch64 PMU register summary */
579
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
580
+}
581
+
582
+static void aarch64_a64fx_initfn(Object *obj)
583
+{
584
+ ARMCPU *cpu = ARM_CPU(obj);
585
+
586
+ cpu->dtb_compatible = "arm,a64fx";
587
+ set_feature(&cpu->env, ARM_FEATURE_V8);
588
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
589
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
590
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
591
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
592
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
593
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
594
+ cpu->midr = 0x461f0010;
595
+ cpu->revidr = 0x00000000;
596
+ cpu->ctr = 0x86668006;
597
+ cpu->reset_sctlr = 0x30000180;
598
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
599
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
600
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
601
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
602
+ cpu->id_aa64afr0 = 0x0000000000000000;
603
+ cpu->id_aa64afr1 = 0x0000000000000000;
604
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
605
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
606
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
607
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
608
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
609
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
610
+ cpu->clidr = 0x0000000080000023;
611
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
612
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
613
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
614
+ cpu->dcz_blocksize = 6; /* 256 bytes */
615
+ cpu->gic_num_lrs = 4;
616
+ cpu->gic_vpribits = 5;
617
+ cpu->gic_vprebits = 5;
618
+ cpu->gic_pribits = 5;
619
+
620
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
621
+ aarch64_add_sve_properties(obj);
622
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
623
+ | (1 << 1) /* 256bit */
624
+ | (1 << 3); /* 512bit */
625
+
626
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
627
+
628
+ /* TODO: Add A64FX specific HPC extension registers */
629
+}
630
+
631
+static void aarch64_neoverse_n1_initfn(Object *obj)
632
+{
633
+ ARMCPU *cpu = ARM_CPU(obj);
634
+
635
+ cpu->dtb_compatible = "arm,neoverse-n1";
636
+ set_feature(&cpu->env, ARM_FEATURE_V8);
637
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
638
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
639
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
640
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
641
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
642
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
643
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
644
+
645
+ /* Ordered by B2.4 AArch64 registers by functional group */
646
+ cpu->clidr = 0x82000023;
647
+ cpu->ctr = 0x8444c004;
648
+ cpu->dcz_blocksize = 4;
649
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
650
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
651
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
652
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
653
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
654
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
655
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
656
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
657
+ cpu->id_afr0 = 0x00000000;
658
+ cpu->isar.id_dfr0 = 0x04010088;
659
+ cpu->isar.id_isar0 = 0x02101110;
660
+ cpu->isar.id_isar1 = 0x13112111;
661
+ cpu->isar.id_isar2 = 0x21232042;
662
+ cpu->isar.id_isar3 = 0x01112131;
663
+ cpu->isar.id_isar4 = 0x00010142;
664
+ cpu->isar.id_isar5 = 0x01011121;
665
+ cpu->isar.id_isar6 = 0x00000010;
666
+ cpu->isar.id_mmfr0 = 0x10201105;
667
+ cpu->isar.id_mmfr1 = 0x40000000;
668
+ cpu->isar.id_mmfr2 = 0x01260000;
669
+ cpu->isar.id_mmfr3 = 0x02122211;
670
+ cpu->isar.id_mmfr4 = 0x00021110;
671
+ cpu->isar.id_pfr0 = 0x10010131;
672
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
673
+ cpu->isar.id_pfr2 = 0x00000011;
674
+ cpu->midr = 0x414fd0c1; /* r4p1 */
675
+ cpu->revidr = 0;
676
+
677
+ /* From B2.23 CCSIDR_EL1 */
678
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
679
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
680
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
681
+
682
+ /* From B2.98 SCTLR_EL3 */
683
+ cpu->reset_sctlr = 0x30c50838;
684
+
685
+ /* From B4.23 ICH_VTR_EL2 */
686
+ cpu->gic_num_lrs = 4;
687
+ cpu->gic_vpribits = 5;
688
+ cpu->gic_vprebits = 5;
689
+ cpu->gic_pribits = 5;
690
+
691
+ /* From B5.1 AdvSIMD AArch64 register summary */
692
+ cpu->isar.mvfr0 = 0x10110222;
693
+ cpu->isar.mvfr1 = 0x13211111;
694
+ cpu->isar.mvfr2 = 0x00000043;
695
+
696
+ /* From D5.1 AArch64 PMU register summary */
697
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
698
+}
699
+
700
static void aarch64_host_initfn(Object *obj)
65
{
701
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
702
#if defined(CONFIG_KVM)
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
703
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
68
/* Pi2 and Pi3 requires SMP setup */
704
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
69
if (version >= 2) {
705
}
70
binfo.smp_loader_start = SMPBOOT_ADDR;
706
71
- binfo.write_secondary_boot = write_smpboot;
707
-static void aarch64_a64fx_initfn(Object *obj)
72
+ if (version == 2) {
708
-{
73
+ binfo.write_secondary_boot = write_smpboot;
709
- ARMCPU *cpu = ARM_CPU(obj);
74
+ } else {
710
-
75
+ binfo.write_secondary_boot = write_smpboot64;
711
- cpu->dtb_compatible = "arm,a64fx";
76
+ }
712
- set_feature(&cpu->env, ARM_FEATURE_V8);
77
binfo.secondary_cpu_reset_hook = reset_secondary;
713
- set_feature(&cpu->env, ARM_FEATURE_NEON);
78
}
714
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
79
715
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
716
- set_feature(&cpu->env, ARM_FEATURE_EL2);
717
- set_feature(&cpu->env, ARM_FEATURE_EL3);
718
- set_feature(&cpu->env, ARM_FEATURE_PMU);
719
- cpu->midr = 0x461f0010;
720
- cpu->revidr = 0x00000000;
721
- cpu->ctr = 0x86668006;
722
- cpu->reset_sctlr = 0x30000180;
723
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
724
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
725
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
726
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
727
- cpu->id_aa64afr0 = 0x0000000000000000;
728
- cpu->id_aa64afr1 = 0x0000000000000000;
729
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
730
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
731
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
732
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
733
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
734
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
735
- cpu->clidr = 0x0000000080000023;
736
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
737
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
738
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
739
- cpu->dcz_blocksize = 6; /* 256 bytes */
740
- cpu->gic_num_lrs = 4;
741
- cpu->gic_vpribits = 5;
742
- cpu->gic_vprebits = 5;
743
- cpu->gic_pribits = 5;
744
-
745
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
746
- aarch64_add_sve_properties(obj);
747
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
748
- | (1 << 1) /* 256bit */
749
- | (1 << 3); /* 512bit */
750
-
751
- cpu->isar.reset_pmcr_el0 = 0x46014040;
752
-
753
- /* TODO: Add A64FX specific HPC extension registers */
754
-}
755
-
756
static const ARMCPUInfo aarch64_cpus[] = {
757
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
758
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
80
--
759
--
81
2.16.2
760
2.25.1
82
761
83
762
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
From: Francisco Iglesias <francisco.iglesias@amd.com>
2
some differences. Notably, the MPIDR affinity aff1 values it
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
2
6
Rather than trying to have one device with properties that
3
Connect ZynqMP's USB controllers.
7
configure it differently for the two cases, create two
8
separate QOM devices for the two SoCs. We use the same approach
9
as hw/arm/aspeed_soc.c and share code and have a data table
10
that might differ per-SoC. For the moment the two types don't
11
actually have different behaviour.
12
4
5
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
---
10
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
11
include/hw/arm/xlnx-zynqmp.h | 3 +++
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
12
hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++
19
hw/arm/raspi.c | 3 ++-
13
2 files changed, 39 insertions(+)
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
14
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
17
--- a/include/hw/arm/xlnx-zynqmp.h
25
+++ b/include/hw/arm/bcm2836.h
18
+++ b/include/hw/arm/xlnx-zynqmp.h
26
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
27
20
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
28
#define BCM283X_NCPUS 4
21
#include "hw/misc/xlnx-zynqmp-crf.h"
29
22
#include "hw/timer/cadence_ttc.h"
30
+/* These type names are for specific SoCs; other than instantiating
23
+#include "hw/usb/hcd-dwc3.h"
31
+ * them, code using these devices should always handle them via the
24
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
25
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
33
+ */
26
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
34
+#define TYPE_BCM2836 "bcm2836"
27
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
35
+#define TYPE_BCM2837 "bcm2837"
28
#define XLNX_ZYNQMP_NUM_SPIS 2
36
+
29
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
37
typedef struct BCM283XState {
30
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
38
/*< private >*/
31
+#define XLNX_ZYNQMP_NUM_USB 2
39
DeviceState parent_obj;
32
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
33
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
41
BCM2835PeripheralState peripherals;
34
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
42
} BCM283XState;
35
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
43
36
XlnxZynqMPAPUCtrl apu_ctrl;
44
+typedef struct BCM283XInfo BCM283XInfo;
37
XlnxZynqMPCRF crf;
45
+
38
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
46
+typedef struct BCM283XClass {
39
+ USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
47
+ DeviceClass parent_class;
40
48
+ const BCM283XInfo *info;
41
char *boot_cpu;
49
+} BCM283XClass;
42
ARMCPU *boot_cpu_ptr;
50
+
43
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
51
+#define BCM283X_CLASS(klass) \
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
53
+#define BCM283X_GET_CLASS(obj) \
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
55
+
56
#endif /* BCM2836_H */
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
58
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/bcm2836.c
45
--- a/hw/arm/xlnx-zynqmp.c
60
+++ b/hw/arm/bcm2836.c
46
+++ b/hw/arm/xlnx-zynqmp.c
61
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
48
77, 78, 79, 80, 81, 82, 83, 84
63
#define BCM2836_CONTROL_BASE 0x40000000
49
};
64
50
65
+struct BCM283XInfo {
51
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
66
+ const char *name;
52
+ 0xFE200000, 0xFE300000
67
+};
53
+};
68
+
54
+
69
+static const BCM283XInfo bcm283x_socs[] = {
55
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
70
+ {
56
+ 65, 70
71
+ .name = TYPE_BCM2836,
72
+ },
73
+ {
74
+ .name = TYPE_BCM2837,
75
+ },
76
+};
57
+};
77
+
58
+
78
static void bcm2836_init(Object *obj)
59
typedef struct XlnxZynqMPGICRegion {
79
{
60
int region_index;
80
BCM283XState *s = BCM283X(obj);
61
uint32_t address;
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
82
DEFINE_PROP_END_OF_LIST()
63
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
83
};
64
object_initialize_child(obj, "qspi-irq-orgate",
84
65
&s->qspi_irq_orgate, TYPE_OR_IRQ);
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
96
97
-static const TypeInfo bcm2836_type_info = {
98
+static const TypeInfo bcm283x_type_info = {
99
.name = TYPE_BCM283X,
100
.parent = TYPE_DEVICE,
101
.instance_size = sizeof(BCM283XState),
102
.instance_init = bcm2836_init,
103
- .class_init = bcm2836_class_init,
104
+ .class_size = sizeof(BCM283XClass),
105
+ .abstract = true,
106
};
107
108
static void bcm2836_register_types(void)
109
{
110
- type_register_static(&bcm2836_type_info);
111
+ int i;
112
+
66
+
113
+ type_register_static(&bcm283x_type_info);
67
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
68
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
115
+ TypeInfo ti = {
116
+ .name = bcm283x_socs[i].name,
117
+ .parent = TYPE_BCM283X,
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
69
+ }
123
}
70
}
124
71
125
type_init(bcm2836_register_types)
72
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
127
index XXXXXXX..XXXXXXX 100644
74
object_property_add_alias(OBJECT(s), bus_name,
128
--- a/hw/arm/raspi.c
75
OBJECT(&s->qspi), target_bus);
129
+++ b/hw/arm/raspi.c
76
}
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
77
+
131
BusState *bus;
78
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
132
DeviceState *carddev;
79
+ if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
133
80
+ OBJECT(system_memory), errp)) {
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
81
+ return;
135
+ object_initialize(&s->soc, sizeof(s->soc),
82
+ }
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
83
+
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
84
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
138
&error_abort);
85
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
139
86
+
87
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
88
+ return;
89
+ }
90
+
91
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
92
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
93
+ gic_spi[usb_intr[i]]);
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
95
+ gic_spi[usb_intr[i] + 1]);
96
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
97
+ gic_spi[usb_intr[i] + 2]);
98
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
99
+ gic_spi[usb_intr[i] + 3]);
100
+ }
101
}
102
103
static Property xlnx_zynqmp_props[] = {
140
--
104
--
141
2.16.2
105
2.25.1
142
143
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
[PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
The devicetree specification requires a 'model' property in the root
4
it is needed to support guests other than Linux.
4
node. Fix the corresponding dt-validate warning:
5
5
6
Based on the patch by Bill Paul as found here:
6
/: 'model' is a required property
7
https://bugs.launchpad.net/qemu/+bug/1753314
7
From schema: dtschema/schemas/root-node.yaml
8
8
9
Cc: qemu-devel@nongnu.org
9
Use the same name for model as for compatible. The specification
10
Cc: qemu-arm@nongnu.org
10
recommends that 'compatible' follows the format 'manufacturer,model' and
11
Cc: Bill Paul <wpaul@windriver.com>
11
'model' follows the format 'manufacturer,model-number'. Since our
12
Cc: Peter Maydell <peter.maydell@linaro.org>
12
'compatible' doesn't observe this, 'model' doesn't really need to
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
13
either.
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
14
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
15
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
20
---
19
include/hw/char/imx_serial.h | 3 +++
21
hw/arm/virt.c | 1 +
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
22
1 file changed, 1 insertion(+)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
23
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
24
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
26
--- a/hw/arm/virt.c
26
+++ b/include/hw/char/imx_serial.h
27
+++ b/hw/arm/virt.c
27
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
29
qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
29
#define UCR2_SRST (1<<0) /* Reset complete */
30
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
30
31
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
32
+ qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
32
+
33
33
#define UTS1_TXEMPTY (1<<6)
34
/* /chosen must exist for load_dtb to fill in necessary properties later */
34
#define UTS1_RXEMPTY (1<<5)
35
qemu_fdt_add_subnode(fdt, "/chosen");
35
#define UTS1_TXFULL (1<<4)
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
37
uint32_t ubmr;
38
uint32_t ubrc;
39
uint32_t ucr3;
40
+ uint32_t ucr4;
41
42
qemu_irq irq;
43
CharBackend chr;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
98
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
36
--
114
2.16.2
37
2.25.1
115
116
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
[PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
4
doesn't really corespond to anything in real hardware and server as a
4
the corresponding dt-validate warning:
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
5
8
Change the code to explicitly evaluate state of interrupts reported
6
interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
9
via USR1 and USR2 against corresponding masking bits and use the to
7
From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
10
detemine if IRQ line should be asserted or not.
11
8
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
13
reasons:
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
14
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
15
hw/arm/virt.c | 1 +
34
1 file changed, 16 insertions(+), 8 deletions(-)
16
1 file changed, 1 insertion(+)
35
17
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
37
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
20
--- a/hw/arm/virt.c
39
+++ b/hw/char/imx_serial.c
21
+++ b/hw/arm/virt.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
22
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
41
23
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
42
static void imx_update(IMXSerialState *s)
24
"arm,gic-v3-its");
43
{
25
qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
44
- uint32_t flags;
26
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
45
+ uint32_t usr1;
27
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
46
+ uint32_t usr2;
28
2, vms->memmap[VIRT_GIC_ITS].base,
47
+ uint32_t mask;
29
2, vms->memmap[VIRT_GIC_ITS].size);
48
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
52
- } else {
53
- flags &= ~USR1_TRDY;
54
- }
55
+ /*
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
57
+ * UCR1, so we can get away with something as simple as the
58
+ * following:
59
+ */
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
71
72
static void imx_serial_reset(IMXSerialState *s)
73
--
30
--
74
2.16.2
31
2.25.1
75
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
[PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI
1
From: Wei Huang <wei@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
The "msi-parent" property can be used on the PCI node when MSIs do not
4
time when guest VM runs. To find the physical base address correctly,
4
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
5
contain the requester ID, so the PCI node should use the "msi-map"
6
However this string pattern is only available on x86_64. AArch64 uses a
6
property instead of "msi-parent". In our case the property describes an
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
7
identity map between requester ID and sideband data.
8
QEMU dump uses the correct string on AArch64.
9
8
10
Signed-off-by: Wei Huang <wei@redhat.com>
9
This fixes a warning when passing the DTB generated by QEMU to dtc,
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
10
following a recent change to the GICv3 node:
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
11
12
Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
13
14
[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
15
16
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
21
---
15
dump.c | 14 +++++++++++---
22
hw/arm/virt.c | 4 ++--
16
1 file changed, 11 insertions(+), 3 deletions(-)
23
1 file changed, 2 insertions(+), 2 deletions(-)
17
24
18
diff --git a/dump.c b/dump.c
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
19
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
27
--- a/hw/arm/virt.c
21
+++ b/dump.c
28
+++ b/hw/arm/virt.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
29
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
23
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
24
lines = g_strsplit((char *)vmci, "\n", -1);
31
25
for (i = 0; lines[i]; i++) {
32
if (vms->msi_phandle) {
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
33
- qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
34
- vms->msi_phandle);
28
+ const char *prefix = NULL;
35
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
29
+
36
+ 0, vms->msi_phandle, 0, 0x10000);
30
+ if (s->dump_info.d_machine == EM_X86_64) {
37
}
31
+ prefix = "NUMBER(phys_base)=";
38
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
39
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
34
+ }
35
+
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
38
&phys_base) < 0) {
39
- warn_report("Failed to read NUMBER(phys_base)=");
40
+ warn_report("Failed to read %s", prefix);
41
} else {
42
s->dump_info.phys_base = phys_base;
43
}
44
--
40
--
45
2.16.2
41
2.25.1
46
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
[PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
The SMMUv3 node isn't expected to have clock properties
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
4
(unlike the SMMUv2). Fix the corresponding dt-validate warning:
5
controller which is supported in QEMU using the imx_fec.c module
6
(actually called imx.enet for this model.)
7
5
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
6
smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
9
imx.enet device like this:
7
From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
10
8
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
12
#define FSL_IMX6_ENET_MAC_IRQ 119
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: tweaked commit message as suggested by Eric]
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
15
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
16
hw/arm/virt.c | 2 --
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
17
1 file changed, 2 deletions(-)
46
2 files changed, 29 insertions(+), 3 deletions(-)
47
18
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
49
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
21
--- a/hw/arm/virt.c
51
+++ b/include/hw/arm/fsl-imx6.h
22
+++ b/hw/arm/virt.c
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
23
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
24
qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
25
sizeof(irq_names));
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
26
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
27
- qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
28
- qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
29
qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
30
60
#define FSL_IMX6_PCIE1_IRQ 120
31
qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
61
#define FSL_IMX6_PCIE2_IRQ 121
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
66
+++ b/hw/net/imx_fec.c
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
68
69
static void imx_eth_update(IMXFECState *s)
70
{
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
72
+ /*
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
75
+ * and older) since Linux associated both interrupt lines with Ethernet
76
+ * MAC interrupts. Specifically,
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
79
+ * with swapped interrupt assignments.
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
82
+ * work, though that is accidental.
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
88
+ * Linux instead received MAC interrupts on the timer interrupt.
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
90
+ * albeit accidentally, but qemu versions with the correct interrupt
91
+ * assignment fail.
92
+ *
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
94
+ * interrrupts on both interrupt lines. This should be changed if and when
95
+ * qemu supports IOMUX.
96
+ */
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
99
qemu_set_irq(s->irq[1], 1);
100
} else {
101
qemu_set_irq(s->irq[1], 0);
102
--
32
--
103
2.16.2
33
2.25.1
104
105
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
Deleted patch
1
For the rpi1 and 2 we want to boot the Linux kernel via some
2
custom setup code that makes sure that the SMC instruction
3
acts as a no-op, because it's used for cache maintenance.
4
The rpi3 boots AArch64 kernels, which don't need SMC for
5
cache maintenance and always expect to be booted non-secure.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
13
hw/arm/raspi.c | 17 +++++++++++++----
14
1 file changed, 13 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
21
binfo.board_id = raspi_boardid[version];
22
binfo.ram_size = ram_size;
23
binfo.nb_cpus = smp_cpus;
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
25
- binfo.write_board_setup = write_board_setup;
26
- binfo.secure_board_setup = true;
27
- binfo.secure_boot = true;
28
+
29
+ if (version <= 2) {
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
31
+ * mode before booting a kernel (to set up the SMC vectors so
32
+ * that we get a no-op SMC; this is used by Linux to call the
33
+ * firmware for some cache maintenance operations.
34
+ * The rpi3 doesn't need this.
35
+ */
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
37
+ binfo.write_board_setup = write_board_setup;
38
+ binfo.secure_board_setup = true;
39
+ binfo.secure_boot = true;
40
+ }
41
42
/* Pi2 and Pi3 requires SMP setup */
43
if (version >= 2) {
44
--
45
2.16.2
46
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
Deleted patch
1
Add some assertions that if we're about to boot an AArch64 kernel,
2
the board code has not mistakenly set either secure_boot or
3
secure_board_setup. It doesn't make sense to set secure_boot,
4
because all AArch64 kernels must be booted in non-secure mode.
5
1
6
It might in theory make sense to set secure_board_setup, but
7
we don't currently support that, because only the AArch32
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
9
Since we don't have a current need for this functionality, just
10
assert that we don't try to use it. If it's needed we'll add
11
it later.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
16
---
17
hw/arm/boot.c | 7 +++++++
18
1 file changed, 7 insertions(+)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
+++ b/hw/arm/boot.c
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
25
} else {
26
env->pstate = PSTATE_MODE_EL1h;
27
}
28
+ /* AArch64 kernels never boot in secure mode */
29
+ assert(!info->secure_boot);
30
+ /* This hook is only supported for AArch32 currently:
31
+ * bootloader_aarch64[] will not call the hook, and
32
+ * the code above has already dropped us into EL2 or EL1.
33
+ */
34
+ assert(!info->secure_board_setup);
35
}
36
37
/* Set to non-secure if not a secure boot */
38
--
39
2.16.2
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
Deleted patch
1
If we're directly booting a Linux kernel and the CPU supports both
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
4
instruction is enabled rather than UNDEFing. Otherwise at least some
5
kernels will panic when trying to initialize KVM in the guest.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
9
---
10
hw/arm/boot.c | 5 +++++
11
1 file changed, 5 insertions(+)
12
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
16
+++ b/hw/arm/boot.c
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
18
assert(!info->secure_board_setup);
19
}
20
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
23
+ env->cp15.scr_el3 |= SCR_HCE;
24
+ }
25
+
26
/* Set to non-secure if not a secure boot */
27
if (!info->secure_boot &&
28
(cs != first_cpu || !info->secure_board_setup)) {
29
--
30
2.16.2
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
[PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
From: Jerome Forissier <jerome.forissier@linaro.org>
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
3
but the BCM2386State struct only defines the parent_obj field
4
as DeviceState. This would have caused problems if anything
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
8
provides.
9
2
3
SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
4
it with ARM_CP_EL3_NO_EL2_KEEP.
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
8
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
14
---
12
---
15
hw/arm/bcm2836.c | 2 +-
13
target/arm/helper.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
17
15
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
18
--- a/target/arm/helper.c
21
+++ b/hw/arm/bcm2836.c
19
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
23
21
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
24
static const TypeInfo bcm2836_type_info = {
22
{ .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
25
.name = TYPE_BCM2836,
23
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
26
- .parent = TYPE_SYS_BUS_DEVICE,
24
- .access = PL2_RW, .type = ARM_CP_ALIAS,
27
+ .parent = TYPE_DEVICE,
25
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
28
.instance_size = sizeof(BCM2836State),
26
.fieldoffset = offsetof(CPUARMState, sp_el[1]) },
29
.instance_init = bcm2836_init,
27
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
30
.class_init = bcm2836_class_init,
28
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
31
--
29
--
32
2.16.2
30
2.25.1
33
34
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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