1
Arm patch queue -- these are all bug fix patches but we might
1
This is mostly RTH's tcg_constant refactoring work, plus a few
2
as well put them in to rc0...
2
other things.
3
3
4
thanks
4
thanks
5
-- PMM
5
-- PMM
6
6
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
7
The following changes since commit cf6f26d6f9b2015ee12b4604b79359e76784163a:
8
8
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
9
Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into staging (2022-04-27 10:49:28 -0700)
10
10
11
are available in the Git repository at:
11
are available in the Git repository at:
12
12
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220428
14
14
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
15
for you to fetch changes up to f8e7163d9e6740b5cef02bf73a17a59d0bef8bdb:
16
16
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
17
hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 (2022-04-28 13:59:23 +0100)
18
18
19
----------------------------------------------------------------
19
----------------------------------------------------------------
20
target-arm queue:
20
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
21
* refactor to use tcg_constant where appropriate
22
* dump: Update correct kdump phys_base field for AArch64
22
* Advertise support for FEAT_TTL and FEAT_BBM level 2
23
* char: i.MX: Add support for "TX complete" interrupt
23
* smmuv3: Cache event fault record
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
24
* smmuv3: Add space in guest error message
25
to boot a Debian Linux kernel on raspi3
25
* smmuv3: Advertise support for SMMUv3.2-BBML2
26
26
27
----------------------------------------------------------------
27
----------------------------------------------------------------
28
Andrey Smirnov (2):
28
Damien Hedde (1):
29
char: i.MX: Simplify imx_update()
29
target/arm: Disable cryptographic instructions when neon is disabled
30
char: i.MX: Add support for "TX complete" interrupt
31
30
32
Guenter Roeck (1):
31
Jean-Philippe Brucker (2):
33
fsl-imx6: Swap Ethernet interrupt defines
32
hw/arm/smmuv3: Cache event fault record
33
hw/arm/smmuv3: Add space in guest error message
34
34
35
Peter Maydell (9):
35
Peter Maydell (3):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
36
target/arm: Advertise support for FEAT_TTL
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
37
target/arm: Advertise support for FEAT_BBM level 2
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
38
hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2
39
hw/arm/bcm2386: Fix parent type of bcm2386
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
41
hw/arm/bcm2836: Create proper bcm2837 device
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
43
hw/arm/bcm2836: Hardcode correct CPU type
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
39
46
Wei Huang (1):
40
Richard Henderson (48):
47
dump: Update correct kdump phys_base field for AArch64
41
target/arm: Use tcg_constant in gen_probe_access
42
target/arm: Use tcg_constant in gen_mte_check*
43
target/arm: Use tcg_constant in gen_exception*
44
target/arm: Use tcg_constant in gen_adc_CC
45
target/arm: Use tcg_constant in handle_msr_i
46
target/arm: Use tcg_constant in handle_sys
47
target/arm: Use tcg_constant in disas_exc
48
target/arm: Use tcg_constant in gen_compare_and_swap_pair
49
target/arm: Use tcg_constant in disas_ld_lit
50
target/arm: Use tcg_constant in disas_ldst_*
51
target/arm: Use tcg_constant in disas_add_sum_imm*
52
target/arm: Use tcg_constant in disas_movw_imm
53
target/arm: Use tcg_constant in shift_reg_imm
54
target/arm: Use tcg_constant in disas_cond_select
55
target/arm: Use tcg_constant in handle_{rev16,crc32}
56
target/arm: Use tcg_constant in disas_data_proc_2src
57
target/arm: Use tcg_constant in disas_fp*
58
target/arm: Use tcg_constant in simd shift expanders
59
target/arm: Use tcg_constant in simd fp/int conversion
60
target/arm: Use tcg_constant in 2misc expanders
61
target/arm: Use tcg_constant in balance of translate-a64.c
62
target/arm: Use tcg_constant for aa32 exceptions
63
target/arm: Use tcg_constant for disas_iwmmxt_insn
64
target/arm: Use tcg_constant for gen_{msr,mrs}
65
target/arm: Use tcg_constant for vector shift expanders
66
target/arm: Use tcg_constant for do_coproc_insn
67
target/arm: Use tcg_constant for gen_srs
68
target/arm: Use tcg_constant for op_s_{rri,rxi}_rot
69
target/arm: Use tcg_constant for MOVW, UMAAL, CRC32
70
target/arm: Use tcg_constant for v7m MRS, MSR
71
target/arm: Use tcg_constant for TT, SAT, SMMLA
72
target/arm: Use tcg_constant in LDM, STM
73
target/arm: Use tcg_constant in CLRM, DLS, WLS, LE
74
target/arm: Use tcg_constant in trans_CPS_v7m
75
target/arm: Use tcg_constant in trans_CSEL
76
target/arm: Use tcg_constant for trans_INDEX_*
77
target/arm: Use tcg_constant in SINCDEC, INCDEC
78
target/arm: Use tcg_constant in FCPY, CPY
79
target/arm: Use tcg_constant in {incr, wrap}_last_active
80
target/arm: Use tcg_constant in do_clast_scalar
81
target/arm: Use tcg_constant in WHILE
82
target/arm: Use tcg_constant in LD1, ST1
83
target/arm: Use tcg_constant in SUBR
84
target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm
85
target/arm: Use tcg_constant for predicate descriptors
86
target/arm: Use tcg_constant for do_brk{2,3}
87
target/arm: Use tcg_constant for vector descriptor
88
target/arm: Use field names for accessing DBGWCRn
48
89
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
90
docs/system/arm/emulation.rst | 2 +
50
include/hw/arm/fsl-imx6.h | 4 +-
91
hw/arm/smmuv3-internal.h | 2 +-
51
include/hw/char/imx_serial.h | 3 ++
92
include/hw/arm/smmu-common.h | 1 +
52
dump.c | 14 +++++--
93
target/arm/internals.h | 12 ++
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
94
hw/arm/smmuv3.c | 17 +--
54
hw/arm/boot.c | 12 ++++++
95
target/arm/cpu.c | 9 ++
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
96
target/arm/cpu64.c | 2 +
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
97
target/arm/debug_helper.c | 10 +-
57
hw/net/imx_fec.c | 28 +++++++++++++-
98
target/arm/helper.c | 8 +-
58
9 files changed, 237 insertions(+), 63 deletions(-)
99
target/arm/kvm64.c | 14 +-
59
100
target/arm/translate-a64.c | 301 +++++++++++++-----------------------------
101
target/arm/translate-sve.c | 202 ++++++++++------------------
102
target/arm/translate.c | 244 ++++++++++++----------------------
103
13 files changed, 293 insertions(+), 531 deletions(-)
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src)
16
static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
17
MMUAccessType acc, int log2_size)
18
{
19
- TCGv_i32 t_acc = tcg_const_i32(acc);
20
- TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s));
21
- TCGv_i32 t_size = tcg_const_i32(1 << log2_size);
22
-
23
- gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size);
24
- tcg_temp_free_i32(t_acc);
25
- tcg_temp_free_i32(t_idx);
26
- tcg_temp_free_i32(t_size);
27
+ gen_helper_probe_access(cpu_env, ptr,
28
+ tcg_constant_i32(acc),
29
+ tcg_constant_i32(get_mem_index(s)),
30
+ tcg_constant_i32(1 << log2_size));
31
}
32
33
/*
34
--
35
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-3-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 10 ++--------
9
1 file changed, 2 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
16
int core_idx)
17
{
18
if (tag_checked && s->mte_active[is_unpriv]) {
19
- TCGv_i32 tcg_desc;
20
TCGv_i64 ret;
21
int desc = 0;
22
23
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
24
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
25
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
26
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
27
- tcg_desc = tcg_const_i32(desc);
28
29
ret = new_tmp_a64(s);
30
- gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
31
- tcg_temp_free_i32(tcg_desc);
32
+ gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
33
34
return ret;
35
}
36
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
37
bool tag_checked, int size)
38
{
39
if (tag_checked && s->mte_active[0]) {
40
- TCGv_i32 tcg_desc;
41
TCGv_i64 ret;
42
int desc = 0;
43
44
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
45
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
46
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
47
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
48
- tcg_desc = tcg_const_i32(desc);
49
50
ret = new_tmp_a64(s);
51
- gen_helper_mte_check(ret, cpu_env, tcg_desc, addr);
52
- tcg_temp_free_i32(tcg_desc);
53
+ gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
54
55
return ret;
56
}
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-4-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s)
16
17
static void gen_exception_internal(int excp)
18
{
19
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
20
-
21
assert(excp_is_internal(excp));
22
- gen_helper_exception_internal(cpu_env, tcg_excp);
23
- tcg_temp_free_i32(tcg_excp);
24
+ gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
25
}
26
27
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
28
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
29
30
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
31
{
32
- TCGv_i32 tcg_syn;
33
-
34
gen_a64_set_pc_im(s->pc_curr);
35
- tcg_syn = tcg_const_i32(syndrome);
36
- gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
37
- tcg_temp_free_i32(tcg_syn);
38
+ gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
39
s->base.is_jmp = DISAS_NORETURN;
40
}
41
42
--
43
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Note that tmp was doing double-duty as zero
4
and then later as a temporary in its own right.
5
Split the use of 0 to a new variable 'zero'.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 26 +++++++++++++-------------
13
1 file changed, 13 insertions(+), 13 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
20
static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
21
{
22
if (sf) {
23
- TCGv_i64 result, cf_64, vf_64, tmp;
24
- result = tcg_temp_new_i64();
25
- cf_64 = tcg_temp_new_i64();
26
- vf_64 = tcg_temp_new_i64();
27
- tmp = tcg_const_i64(0);
28
+ TCGv_i64 result = tcg_temp_new_i64();
29
+ TCGv_i64 cf_64 = tcg_temp_new_i64();
30
+ TCGv_i64 vf_64 = tcg_temp_new_i64();
31
+ TCGv_i64 tmp = tcg_temp_new_i64();
32
+ TCGv_i64 zero = tcg_constant_i64(0);
33
34
tcg_gen_extu_i32_i64(cf_64, cpu_CF);
35
- tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
36
- tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
37
+ tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
38
+ tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
39
tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
40
gen_set_NZ64(result);
41
42
@@ -XXX,XX +XXX,XX @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
43
tcg_temp_free_i64(cf_64);
44
tcg_temp_free_i64(result);
45
} else {
46
- TCGv_i32 t0_32, t1_32, tmp;
47
- t0_32 = tcg_temp_new_i32();
48
- t1_32 = tcg_temp_new_i32();
49
- tmp = tcg_const_i32(0);
50
+ TCGv_i32 t0_32 = tcg_temp_new_i32();
51
+ TCGv_i32 t1_32 = tcg_temp_new_i32();
52
+ TCGv_i32 tmp = tcg_temp_new_i32();
53
+ TCGv_i32 zero = tcg_constant_i32(0);
54
55
tcg_gen_extrl_i64_i32(t0_32, t0);
56
tcg_gen_extrl_i64_i32(t1_32, t1);
57
- tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
58
- tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
59
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
60
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
61
62
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
63
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
64
--
65
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-6-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 13 +++----------
9
1 file changed, 3 insertions(+), 10 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_axflag(void)
16
static void handle_msr_i(DisasContext *s, uint32_t insn,
17
unsigned int op1, unsigned int op2, unsigned int crm)
18
{
19
- TCGv_i32 t1;
20
int op = op1 << 3 | op2;
21
22
/* End the TB by default, chaining is ok. */
23
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
24
if (s->current_el == 0) {
25
goto do_unallocated;
26
}
27
- t1 = tcg_const_i32(crm & PSTATE_SP);
28
- gen_helper_msr_i_spsel(cpu_env, t1);
29
- tcg_temp_free_i32(t1);
30
+ gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP));
31
break;
32
33
case 0x19: /* SSBS */
34
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
35
break;
36
37
case 0x1e: /* DAIFSet */
38
- t1 = tcg_const_i32(crm);
39
- gen_helper_msr_i_daifset(cpu_env, t1);
40
- tcg_temp_free_i32(t1);
41
+ gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm));
42
break;
43
44
case 0x1f: /* DAIFClear */
45
- t1 = tcg_const_i32(crm);
46
- gen_helper_msr_i_daifclear(cpu_env, t1);
47
- tcg_temp_free_i32(t1);
48
+ gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm));
49
/* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
50
s->base.is_jmp = DISAS_UPDATE_EXIT;
51
break;
52
--
53
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-7-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 31 +++++++++----------------------
9
1 file changed, 9 insertions(+), 22 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
16
/* Emit code to perform further access permissions checks at
17
* runtime; this may result in an exception.
18
*/
19
- TCGv_ptr tmpptr;
20
- TCGv_i32 tcg_syn, tcg_isread;
21
uint32_t syndrome;
22
23
- gen_a64_set_pc_im(s->pc_curr);
24
- tmpptr = tcg_const_ptr(ri);
25
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
26
- tcg_syn = tcg_const_i32(syndrome);
27
- tcg_isread = tcg_const_i32(isread);
28
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
29
- tcg_temp_free_ptr(tmpptr);
30
- tcg_temp_free_i32(tcg_syn);
31
- tcg_temp_free_i32(tcg_isread);
32
+ gen_a64_set_pc_im(s->pc_curr);
33
+ gen_helper_access_check_cp_reg(cpu_env,
34
+ tcg_constant_ptr(ri),
35
+ tcg_constant_i32(syndrome),
36
+ tcg_constant_i32(isread));
37
} else if (ri->type & ARM_CP_RAISES_EXC) {
38
/*
39
* The readfn or writefn might raise an exception;
40
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
41
case ARM_CP_DC_ZVA:
42
/* Writes clear the aligned block of memory which rt points into. */
43
if (s->mte_active[0]) {
44
- TCGv_i32 t_desc;
45
int desc = 0;
46
47
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
48
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
49
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
50
- t_desc = tcg_const_i32(desc);
51
52
tcg_rt = new_tmp_a64(s);
53
- gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt));
54
- tcg_temp_free_i32(t_desc);
55
+ gen_helper_mte_check_zva(tcg_rt, cpu_env,
56
+ tcg_constant_i32(desc), cpu_reg(s, rt));
57
} else {
58
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
59
}
60
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
61
if (ri->type & ARM_CP_CONST) {
62
tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
63
} else if (ri->readfn) {
64
- TCGv_ptr tmpptr;
65
- tmpptr = tcg_const_ptr(ri);
66
- gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
67
- tcg_temp_free_ptr(tmpptr);
68
+ gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri));
69
} else {
70
tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
71
}
72
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
73
/* If not forbidden by access permissions, treat as WI */
74
return;
75
} else if (ri->writefn) {
76
- TCGv_ptr tmpptr;
77
- tmpptr = tcg_const_ptr(ri);
78
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
79
- tcg_temp_free_ptr(tmpptr);
80
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt);
81
} else {
82
tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
83
}
84
--
85
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-8-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
16
int opc = extract32(insn, 21, 3);
17
int op2_ll = extract32(insn, 0, 5);
18
int imm16 = extract32(insn, 5, 16);
19
- TCGv_i32 tmp;
20
21
switch (opc) {
22
case 0:
23
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
24
break;
25
}
26
gen_a64_set_pc_im(s->pc_curr);
27
- tmp = tcg_const_i32(syn_aa64_smc(imm16));
28
- gen_helper_pre_smc(cpu_env, tmp);
29
- tcg_temp_free_i32(tmp);
30
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
31
gen_ss_advance(s);
32
gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
33
syn_aa64_smc(imm16), 3);
34
--
35
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-9-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 6 ++----
9
1 file changed, 2 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
16
tcg_temp_free_i64(cmp);
17
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
18
if (HAVE_CMPXCHG128) {
19
- TCGv_i32 tcg_rs = tcg_const_i32(rs);
20
+ TCGv_i32 tcg_rs = tcg_constant_i32(rs);
21
if (s->be_data == MO_LE) {
22
gen_helper_casp_le_parallel(cpu_env, tcg_rs,
23
clean_addr, t1, t2);
24
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
25
gen_helper_casp_be_parallel(cpu_env, tcg_rs,
26
clean_addr, t1, t2);
27
}
28
- tcg_temp_free_i32(tcg_rs);
29
} else {
30
gen_helper_exit_atomic(cpu_env);
31
s->base.is_jmp = DISAS_NORETURN;
32
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
33
TCGv_i64 a2 = tcg_temp_new_i64();
34
TCGv_i64 c1 = tcg_temp_new_i64();
35
TCGv_i64 c2 = tcg_temp_new_i64();
36
- TCGv_i64 zero = tcg_const_i64(0);
37
+ TCGv_i64 zero = tcg_constant_i64(0);
38
39
/* Load the two words, in memory order. */
40
tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,
41
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
42
tcg_temp_free_i64(a2);
43
tcg_temp_free_i64(c1);
44
tcg_temp_free_i64(c2);
45
- tcg_temp_free_i64(zero);
46
47
/* Write back the data from memory to Rs. */
48
tcg_gen_mov_i64(s1, d1);
49
--
50
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 3 +--
9
1 file changed, 1 insertion(+), 2 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
16
17
tcg_rt = cpu_reg(s, rt);
18
19
- clean_addr = tcg_const_i64(s->pc_curr + imm);
20
+ clean_addr = tcg_constant_i64(s->pc_curr + imm);
21
if (is_vector) {
22
do_fp_ld(s, rt, clean_addr, size);
23
} else {
24
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
25
do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
26
false, true, rt, iss_sf, false);
27
}
28
- tcg_temp_free_i64(clean_addr);
29
}
30
31
/*
32
--
33
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-11-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 9 +++------
9
1 file changed, 3 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
16
mop = endian | size | align;
17
18
elements = (is_q ? 16 : 8) >> size;
19
- tcg_ebytes = tcg_const_i64(1 << size);
20
+ tcg_ebytes = tcg_constant_i64(1 << size);
21
for (r = 0; r < rpt; r++) {
22
int e;
23
for (e = 0; e < elements; e++) {
24
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
25
}
26
}
27
}
28
- tcg_temp_free_i64(tcg_ebytes);
29
30
if (!is_store) {
31
/* For non-quad operations, setting a slice of the low
32
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
33
total);
34
mop = finalize_memop(s, scale);
35
36
- tcg_ebytes = tcg_const_i64(1 << scale);
37
+ tcg_ebytes = tcg_constant_i64(1 << scale);
38
for (xs = 0; xs < selem; xs++) {
39
if (replicate) {
40
/* Load and replicate to all elements */
41
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
42
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
43
rt = (rt + 1) % 32;
44
}
45
- tcg_temp_free_i64(tcg_ebytes);
46
47
if (is_postidx) {
48
if (rm == 31) {
49
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
50
51
if (is_zero) {
52
TCGv_i64 clean_addr = clean_data_tbi(s, addr);
53
- TCGv_i64 tcg_zero = tcg_const_i64(0);
54
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
55
int mem_index = get_mem_index(s);
56
int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
57
58
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
59
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
60
tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ);
61
}
62
- tcg_temp_free_i64(tcg_zero);
63
}
64
65
if (index != 0) {
66
--
67
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
16
tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
17
}
18
} else {
19
- TCGv_i64 tcg_imm = tcg_const_i64(imm);
20
+ TCGv_i64 tcg_imm = tcg_constant_i64(imm);
21
if (sub_op) {
22
gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
23
} else {
24
gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
25
}
26
- tcg_temp_free_i64(tcg_imm);
27
}
28
29
if (is_64bit) {
30
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn)
31
tcg_rd = cpu_reg_sp(s, rd);
32
33
if (s->ata) {
34
- TCGv_i32 offset = tcg_const_i32(imm);
35
- TCGv_i32 tag_offset = tcg_const_i32(uimm4);
36
-
37
- gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset);
38
- tcg_temp_free_i32(tag_offset);
39
- tcg_temp_free_i32(offset);
40
+ gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn,
41
+ tcg_constant_i32(imm),
42
+ tcg_constant_i32(uimm4));
43
} else {
44
tcg_gen_addi_i64(tcg_rd, tcg_rn, imm);
45
gen_address_with_allocation_tag0(tcg_rd, tcg_rd);
46
--
47
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-13-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
16
int opc = extract32(insn, 29, 2);
17
int pos = extract32(insn, 21, 2) << 4;
18
TCGv_i64 tcg_rd = cpu_reg(s, rd);
19
- TCGv_i64 tcg_imm;
20
21
if (!sf && (pos >= 32)) {
22
unallocated_encoding(s);
23
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
24
tcg_gen_movi_i64(tcg_rd, imm);
25
break;
26
case 3: /* MOVK */
27
- tcg_imm = tcg_const_i64(imm);
28
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
29
- tcg_temp_free_i64(tcg_imm);
30
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16);
31
if (!sf) {
32
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
33
}
34
--
35
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-14-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 6 +-----
9
1 file changed, 1 insertion(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
16
if (shift_i == 0) {
17
tcg_gen_mov_i64(dst, src);
18
} else {
19
- TCGv_i64 shift_const;
20
-
21
- shift_const = tcg_const_i64(shift_i);
22
- shift_reg(dst, src, sf, shift_type, shift_const);
23
- tcg_temp_free_i64(shift_const);
24
+ shift_reg(dst, src, sf, shift_type, tcg_constant_i64(shift_i));
25
}
26
}
27
28
--
29
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-15-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 3 +--
9
1 file changed, 1 insertion(+), 2 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
16
tcg_rd = cpu_reg(s, rd);
17
18
a64_test_cc(&c, cond);
19
- zero = tcg_const_i64(0);
20
+ zero = tcg_constant_i64(0);
21
22
if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
23
/* CSET & CSETM. */
24
@@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
25
tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
26
}
27
28
- tcg_temp_free_i64(zero);
29
a64_free_cc(&c);
30
31
if (!sf) {
32
--
33
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-16-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 7 ++-----
9
1 file changed, 2 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
16
TCGv_i64 tcg_rd = cpu_reg(s, rd);
17
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
18
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
19
- TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
20
+ TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
21
22
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
23
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
24
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
25
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
26
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
27
28
- tcg_temp_free_i64(mask);
29
tcg_temp_free_i64(tcg_tmp);
30
}
31
32
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
33
}
34
35
tcg_acc = cpu_reg(s, rn);
36
- tcg_bytes = tcg_const_i32(1 << sz);
37
+ tcg_bytes = tcg_constant_i32(1 << sz);
38
39
if (crc32c) {
40
gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
41
} else {
42
gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
43
}
44
-
45
- tcg_temp_free_i32(tcg_bytes);
46
}
47
48
/* Data-processing (2 source)
49
--
50
2.25.1
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
Existing temp usage treats t1 as both zero and as a
4
it is needed to support guests other than Linux.
4
temporary. Rearrange to only require one temporary,
5
so remove t1 and rename t2.
5
6
6
Based on the patch by Bill Paul as found here:
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
https://bugs.launchpad.net/qemu/+bug/1753314
8
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Cc: Bill Paul <wpaul@windriver.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-17-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/char/imx_serial.h | 3 +++
12
target/arm/translate-a64.c | 12 +++++-------
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
13
1 file changed, 5 insertions(+), 7 deletions(-)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
14
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
17
--- a/target/arm/translate-a64.c
26
+++ b/include/hw/char/imx_serial.h
18
+++ b/target/arm/translate-a64.c
27
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
20
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
29
#define UCR2_SRST (1<<0) /* Reset complete */
21
goto do_unallocated;
30
22
} else {
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
23
- TCGv_i64 t1 = tcg_const_i64(1);
32
+
24
- TCGv_i64 t2 = tcg_temp_new_i64();
33
#define UTS1_TXEMPTY (1<<6)
25
+ TCGv_i64 t = tcg_temp_new_i64();
34
#define UTS1_RXEMPTY (1<<5)
26
35
#define UTS1_TXFULL (1<<4)
27
- tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4);
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
28
- tcg_gen_shl_i64(t1, t1, t2);
37
uint32_t ubmr;
29
- tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1);
38
uint32_t ubrc;
30
+ tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4);
39
uint32_t ucr3;
31
+ tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
40
+ uint32_t ucr4;
32
+ tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
41
33
42
qemu_irq irq;
34
- tcg_temp_free_i64(t1);
43
CharBackend chr;
35
- tcg_temp_free_i64(t2);
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
36
+ tcg_temp_free_i64(t);
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
37
}
98
break;
38
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
39
case 8: /* LSLV */
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
40
--
114
2.16.2
41
2.25.1
115
116
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-18-richard.henderson@linaro.org
6
[PMM: Restore incorrectly removed free of t_false in disas_fp_csel()]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/translate-a64.c | 23 +++++++----------------
10
1 file changed, 7 insertions(+), 16 deletions(-)
11
12
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-a64.c
15
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, int size,
17
18
tcg_vn = read_fp_dreg(s, rn);
19
if (cmp_with_zero) {
20
- tcg_vm = tcg_const_i64(0);
21
+ tcg_vm = tcg_constant_i64(0);
22
} else {
23
tcg_vm = read_fp_dreg(s, rm);
24
}
25
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
26
static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
27
{
28
unsigned int mos, type, rm, cond, rn, op, nzcv;
29
- TCGv_i64 tcg_flags;
30
TCGLabel *label_continue = NULL;
31
int size;
32
33
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
34
label_continue = gen_new_label();
35
arm_gen_test_cc(cond, label_match);
36
/* nomatch: */
37
- tcg_flags = tcg_const_i64(nzcv << 28);
38
- gen_set_nzcv(tcg_flags);
39
- tcg_temp_free_i64(tcg_flags);
40
+ gen_set_nzcv(tcg_constant_i64(nzcv << 28));
41
tcg_gen_br(label_continue);
42
gen_set_label(label_match);
43
}
44
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
45
static void disas_fp_csel(DisasContext *s, uint32_t insn)
46
{
47
unsigned int mos, type, rm, cond, rn, rd;
48
- TCGv_i64 t_true, t_false, t_zero;
49
+ TCGv_i64 t_true, t_false;
50
DisasCompare64 c;
51
MemOp sz;
52
53
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
54
read_vec_element(s, t_false, rm, 0, sz);
55
56
a64_test_cc(&c, cond);
57
- t_zero = tcg_const_i64(0);
58
- tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
59
- tcg_temp_free_i64(t_zero);
60
+ tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0),
61
+ t_true, t_false);
62
tcg_temp_free_i64(t_false);
63
a64_free_cc(&c);
64
65
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
66
int type = extract32(insn, 22, 2);
67
int mos = extract32(insn, 29, 3);
68
uint64_t imm;
69
- TCGv_i64 tcg_res;
70
MemOp sz;
71
72
if (mos || imm5) {
73
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
74
}
75
76
imm = vfp_expand_imm(sz, imm8);
77
-
78
- tcg_res = tcg_const_i64(imm);
79
- write_fp_dreg(s, rd, tcg_res);
80
- tcg_temp_free_i64(tcg_res);
81
+ write_fp_dreg(s, rd, tcg_constant_i64(imm));
82
}
83
84
/* Handle floating point <=> fixed point conversions. Note that we can
85
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
86
87
tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR);
88
89
- tcg_shift = tcg_const_i32(64 - scale);
90
+ tcg_shift = tcg_constant_i32(64 - scale);
91
92
if (itof) {
93
TCGv_i64 tcg_int = cpu_reg(s, rn);
94
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
95
}
96
97
tcg_temp_free_ptr(tcg_fpstatus);
98
- tcg_temp_free_i32(tcg_shift);
99
}
100
101
/* Floating point <-> fixed point conversions
102
--
103
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 21 +++++----------------
9
1 file changed, 5 insertions(+), 16 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
16
/* Deal with the rounding step */
17
if (round) {
18
if (extended_result) {
19
- TCGv_i64 tcg_zero = tcg_const_i64(0);
20
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
21
if (!is_u) {
22
/* take care of sign extending tcg_res */
23
tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
24
@@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
25
tcg_src, tcg_zero,
26
tcg_rnd, tcg_zero);
27
}
28
- tcg_temp_free_i64(tcg_zero);
29
} else {
30
tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
31
}
32
@@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s,
33
}
34
35
if (round) {
36
- uint64_t round_const = 1ULL << (shift - 1);
37
- tcg_round = tcg_const_i64(round_const);
38
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
39
} else {
40
tcg_round = NULL;
41
}
42
@@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s,
43
44
tcg_temp_free_i64(tcg_rn);
45
tcg_temp_free_i64(tcg_rd);
46
- if (round) {
47
- tcg_temp_free_i64(tcg_round);
48
- }
49
}
50
51
/* SHL/SLI - Scalar shift left */
52
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
53
tcg_final = tcg_const_i64(0);
54
55
if (round) {
56
- uint64_t round_const = 1ULL << (shift - 1);
57
- tcg_round = tcg_const_i64(round_const);
58
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
59
} else {
60
tcg_round = NULL;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
63
write_vec_element(s, tcg_final, rd, 1, MO_64);
64
}
65
66
- if (round) {
67
- tcg_temp_free_i64(tcg_round);
68
- }
69
tcg_temp_free_i64(tcg_rn);
70
tcg_temp_free_i64(tcg_rd);
71
tcg_temp_free_i32(tcg_rd_narrowed);
72
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
73
}
74
75
if (size == 3) {
76
- TCGv_i64 tcg_shift = tcg_const_i64(shift);
77
+ TCGv_i64 tcg_shift = tcg_constant_i64(shift);
78
static NeonGenTwo64OpEnvFn * const fns[2][2] = {
79
{ gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
80
{ NULL, gen_helper_neon_qshl_u64 },
81
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
82
83
tcg_temp_free_i64(tcg_op);
84
}
85
- tcg_temp_free_i64(tcg_shift);
86
clear_vec_high(s, is_q, rd);
87
} else {
88
- TCGv_i32 tcg_shift = tcg_const_i32(shift);
89
+ TCGv_i32 tcg_shift = tcg_constant_i32(shift);
90
static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
91
{
92
{ gen_helper_neon_qshl_s8,
93
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
94
95
tcg_temp_free_i32(tcg_op);
96
}
97
- tcg_temp_free_i32(tcg_shift);
98
99
if (!scalar) {
100
clear_vec_high(s, is_q, rd);
101
--
102
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-20-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 26 ++++++--------------------
9
1 file changed, 6 insertions(+), 20 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
16
int pass;
17
18
if (fracbits || size == MO_64) {
19
- tcg_shift = tcg_const_i32(fracbits);
20
+ tcg_shift = tcg_constant_i32(fracbits);
21
}
22
23
if (size == MO_64) {
24
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
25
}
26
27
tcg_temp_free_ptr(tcg_fpst);
28
- if (tcg_shift) {
29
- tcg_temp_free_i32(tcg_shift);
30
- }
31
32
clear_vec_high(s, elements << size == 16, rd);
33
}
34
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
35
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
36
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
37
fracbits = (16 << size) - immhb;
38
- tcg_shift = tcg_const_i32(fracbits);
39
+ tcg_shift = tcg_constant_i32(fracbits);
40
41
if (size == MO_64) {
42
int maxpass = is_scalar ? 1 : 2;
43
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
44
}
45
}
46
47
- tcg_temp_free_i32(tcg_shift);
48
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
49
tcg_temp_free_ptr(tcg_fpstatus);
50
tcg_temp_free_i32(tcg_rmode);
51
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
52
case 0x1c: /* FCVTAS */
53
case 0x3a: /* FCVTPS */
54
case 0x3b: /* FCVTZS */
55
- {
56
- TCGv_i32 tcg_shift = tcg_const_i32(0);
57
- gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
58
- tcg_temp_free_i32(tcg_shift);
59
+ gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
60
break;
61
- }
62
case 0x5a: /* FCVTNU */
63
case 0x5b: /* FCVTMU */
64
case 0x5c: /* FCVTAU */
65
case 0x7a: /* FCVTPU */
66
case 0x7b: /* FCVTZU */
67
- {
68
- TCGv_i32 tcg_shift = tcg_const_i32(0);
69
- gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
70
- tcg_temp_free_i32(tcg_shift);
71
+ gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
72
break;
73
- }
74
case 0x18: /* FRINTN */
75
case 0x19: /* FRINTM */
76
case 0x38: /* FRINTP */
77
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
78
79
if (is_double) {
80
TCGv_i64 tcg_op = tcg_temp_new_i64();
81
- TCGv_i64 tcg_zero = tcg_const_i64(0);
82
+ TCGv_i64 tcg_zero = tcg_constant_i64(0);
83
TCGv_i64 tcg_res = tcg_temp_new_i64();
84
NeonGenTwoDoubleOpFn *genfn;
85
bool swap = false;
86
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
87
write_vec_element(s, tcg_res, rd, pass, MO_64);
88
}
89
tcg_temp_free_i64(tcg_res);
90
- tcg_temp_free_i64(tcg_zero);
91
tcg_temp_free_i64(tcg_op);
92
93
clear_vec_high(s, !is_scalar, rd);
94
} else {
95
TCGv_i32 tcg_op = tcg_temp_new_i32();
96
- TCGv_i32 tcg_zero = tcg_const_i32(0);
97
+ TCGv_i32 tcg_zero = tcg_constant_i32(0);
98
TCGv_i32 tcg_res = tcg_temp_new_i32();
99
NeonGenTwoSingleOpFn *genfn;
100
bool swap = false;
101
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
102
}
103
}
104
tcg_temp_free_i32(tcg_res);
105
- tcg_temp_free_i32(tcg_zero);
106
tcg_temp_free_i32(tcg_op);
107
if (!is_scalar) {
108
clear_vec_high(s, is_q, rd);
109
--
110
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-21-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 40 ++++++++++----------------------------
9
1 file changed, 10 insertions(+), 30 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
16
int passes = scalar ? 1 : 2;
17
18
if (scalar) {
19
- tcg_res[1] = tcg_const_i32(0);
20
+ tcg_res[1] = tcg_constant_i32(0);
21
}
22
23
for (pass = 0; pass < passes; pass++) {
24
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
25
}
26
27
if (is_scalar) {
28
- TCGv_i64 tcg_zero = tcg_const_i64(0);
29
- write_vec_element(s, tcg_zero, rd, 0, MO_64);
30
- tcg_temp_free_i64(tcg_zero);
31
+ write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
32
}
33
write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
34
}
35
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
36
case 0x1c: /* FCVTAS */
37
case 0x3a: /* FCVTPS */
38
case 0x3b: /* FCVTZS */
39
- {
40
- TCGv_i32 tcg_shift = tcg_const_i32(0);
41
- gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
42
- tcg_temp_free_i32(tcg_shift);
43
+ gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
44
+ tcg_fpstatus);
45
break;
46
- }
47
case 0x5a: /* FCVTNU */
48
case 0x5b: /* FCVTMU */
49
case 0x5c: /* FCVTAU */
50
case 0x7a: /* FCVTPU */
51
case 0x7b: /* FCVTZU */
52
- {
53
- TCGv_i32 tcg_shift = tcg_const_i32(0);
54
- gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
55
- tcg_temp_free_i32(tcg_shift);
56
+ gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
57
+ tcg_fpstatus);
58
break;
59
- }
60
default:
61
g_assert_not_reached();
62
}
63
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
64
read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
65
66
if (round) {
67
- uint64_t round_const = 1ULL << (shift - 1);
68
- tcg_round = tcg_const_i64(round_const);
69
+ tcg_round = tcg_constant_i64(1ULL << (shift - 1));
70
} else {
71
tcg_round = NULL;
72
}
73
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
74
} else {
75
write_vec_element(s, tcg_final, rd, 1, MO_64);
76
}
77
- if (round) {
78
- tcg_temp_free_i64(tcg_round);
79
- }
80
tcg_temp_free_i64(tcg_rn);
81
tcg_temp_free_i64(tcg_rd);
82
tcg_temp_free_i64(tcg_final);
83
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
84
}
85
}
86
if (!is_q) {
87
- tcg_res[1] = tcg_const_i64(0);
88
+ tcg_res[1] = tcg_constant_i64(0);
89
}
90
for (pass = 0; pass < 2; pass++) {
91
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
92
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
93
case 0x1c: /* FCVTAS */
94
case 0x3a: /* FCVTPS */
95
case 0x3b: /* FCVTZS */
96
- {
97
- TCGv_i32 tcg_shift = tcg_const_i32(0);
98
gen_helper_vfp_tosls(tcg_res, tcg_op,
99
- tcg_shift, tcg_fpstatus);
100
- tcg_temp_free_i32(tcg_shift);
101
+ tcg_constant_i32(0), tcg_fpstatus);
102
break;
103
- }
104
case 0x5a: /* FCVTNU */
105
case 0x5b: /* FCVTMU */
106
case 0x5c: /* FCVTAU */
107
case 0x7a: /* FCVTPU */
108
case 0x7b: /* FCVTZU */
109
- {
110
- TCGv_i32 tcg_shift = tcg_const_i32(0);
111
gen_helper_vfp_touls(tcg_res, tcg_op,
112
- tcg_shift, tcg_fpstatus);
113
- tcg_temp_free_i32(tcg_shift);
114
+ tcg_constant_i32(0), tcg_fpstatus);
115
break;
116
- }
117
case 0x18: /* FRINTN */
118
case 0x19: /* FRINTM */
119
case 0x38: /* FRINTP */
120
--
121
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Finish conversion of the file to tcg_constant_*.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20220426163043.100432-22-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 20 ++++++++------------
11
1 file changed, 8 insertions(+), 12 deletions(-)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
18
}
19
20
if (is_scalar) {
21
- tcg_res[1] = tcg_const_i64(0);
22
+ tcg_res[1] = tcg_constant_i64(0);
23
}
24
25
for (pass = 0; pass < 2; pass++) {
26
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
27
tcg_op2 = tcg_temp_new_i32();
28
tcg_op3 = tcg_temp_new_i32();
29
tcg_res = tcg_temp_new_i32();
30
- tcg_zero = tcg_const_i32(0);
31
+ tcg_zero = tcg_constant_i32(0);
32
33
read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);
34
read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);
35
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
36
tcg_temp_free_i32(tcg_op2);
37
tcg_temp_free_i32(tcg_op3);
38
tcg_temp_free_i32(tcg_res);
39
- tcg_temp_free_i32(tcg_zero);
40
}
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
44
gen_helper_yield(cpu_env);
45
break;
46
case DISAS_WFI:
47
- {
48
- /* This is a special case because we don't want to just halt the CPU
49
- * if trying to debug across a WFI.
50
+ /*
51
+ * This is a special case because we don't want to just halt
52
+ * the CPU if trying to debug across a WFI.
53
*/
54
- TCGv_i32 tmp = tcg_const_i32(4);
55
-
56
gen_a64_set_pc_im(dc->base.pc_next);
57
- gen_helper_wfi(cpu_env, tmp);
58
- tcg_temp_free_i32(tmp);
59
- /* The helper doesn't necessarily throw an exception, but we
60
+ gen_helper_wfi(cpu_env, tcg_constant_i32(4));
61
+ /*
62
+ * The helper doesn't necessarily throw an exception, but we
63
* must go back to the main loop to check for interrupts anyway.
64
*/
65
tcg_gen_exit_tb(NULL, 0);
66
break;
67
}
68
- }
69
}
70
}
71
72
--
73
2.25.1
diff view generated by jsdifflib
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
From: Richard Henderson <richard.henderson@linaro.org>
2
some differences. Notably, the MPIDR affinity aff1 values it
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
2
6
Rather than trying to have one device with properties that
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
configure it differently for the two cases, create two
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
separate QOM devices for the two SoCs. We use the same approach
5
Message-id: 20220426163043.100432-23-richard.henderson@linaro.org
9
as hw/arm/aspeed_soc.c and share code and have a data table
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
that might differ per-SoC. For the moment the two types don't
7
---
11
actually have different behaviour.
8
target/arm/translate.c | 32 +++++++-------------------------
9
1 file changed, 7 insertions(+), 25 deletions(-)
12
10
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
19
hw/arm/raspi.c | 3 ++-
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
23
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
13
--- a/target/arm/translate.c
25
+++ b/include/hw/arm/bcm2836.h
14
+++ b/target/arm/translate.c
26
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
27
16
28
#define BCM283X_NCPUS 4
17
void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
29
30
+/* These type names are for specific SoCs; other than instantiating
31
+ * them, code using these devices should always handle them via the
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
33
+ */
34
+#define TYPE_BCM2836 "bcm2836"
35
+#define TYPE_BCM2837 "bcm2837"
36
+
37
typedef struct BCM283XState {
38
/*< private >*/
39
DeviceState parent_obj;
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
41
BCM2835PeripheralState peripherals;
42
} BCM283XState;
43
44
+typedef struct BCM283XInfo BCM283XInfo;
45
+
46
+typedef struct BCM283XClass {
47
+ DeviceClass parent_class;
48
+ const BCM283XInfo *info;
49
+} BCM283XClass;
50
+
51
+#define BCM283X_CLASS(klass) \
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
53
+#define BCM283X_GET_CLASS(obj) \
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
55
+
56
#endif /* BCM2836_H */
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/bcm2836.c
60
+++ b/hw/arm/bcm2836.c
61
@@ -XXX,XX +XXX,XX @@
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
63
#define BCM2836_CONTROL_BASE 0x40000000
64
65
+struct BCM283XInfo {
66
+ const char *name;
67
+};
68
+
69
+static const BCM283XInfo bcm283x_socs[] = {
70
+ {
71
+ .name = TYPE_BCM2836,
72
+ },
73
+ {
74
+ .name = TYPE_BCM2837,
75
+ },
76
+};
77
+
78
static void bcm2836_init(Object *obj)
79
{
18
{
80
BCM283XState *s = BCM283X(obj);
19
- TCGv_i32 tmp_mask = tcg_const_i32(mask);
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
20
- gen_helper_cpsr_write(cpu_env, var, tmp_mask);
82
DEFINE_PROP_END_OF_LIST()
21
- tcg_temp_free_i32(tmp_mask);
83
};
22
+ gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask));
84
23
}
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
24
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
25
static void gen_rebuild_hflags(DisasContext *s, bool new_el)
26
@@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el)
27
28
static void gen_exception_internal(int excp)
87
{
29
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
30
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
31
-
90
32
assert(excp_is_internal(excp));
91
- dc->props = bcm2836_props;
33
- gen_helper_exception_internal(cpu_env, tcg_excp);
92
+ bc->info = data;
34
- tcg_temp_free_i32(tcg_excp);
93
dc->realize = bcm2836_realize;
35
+ gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
94
+ dc->props = bcm2836_props;
95
}
36
}
96
37
97
-static const TypeInfo bcm2836_type_info = {
38
static void gen_singlestep_exception(DisasContext *s)
98
+static const TypeInfo bcm283x_type_info = {
39
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
99
.name = TYPE_BCM283X,
40
/* As with HVC, we may take an exception either before or after
100
.parent = TYPE_DEVICE,
41
* the insn executes.
101
.instance_size = sizeof(BCM283XState),
42
*/
102
.instance_init = bcm2836_init,
43
- TCGv_i32 tmp;
103
- .class_init = bcm2836_class_init,
44
-
104
+ .class_size = sizeof(BCM283XClass),
45
gen_set_pc_im(s, s->pc_curr);
105
+ .abstract = true,
46
- tmp = tcg_const_i32(syn_aa32_smc());
106
};
47
- gen_helper_pre_smc(cpu_env, tmp);
107
48
- tcg_temp_free_i32(tmp);
108
static void bcm2836_register_types(void)
49
+ gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
50
gen_set_pc_im(s, s->base.pc_next);
51
s->base.is_jmp = DISAS_SMC;
52
}
53
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
54
55
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
109
{
56
{
110
- type_register_static(&bcm2836_type_info);
57
- TCGv_i32 tcg_syn;
111
+ int i;
58
-
112
+
59
gen_set_condexec(s);
113
+ type_register_static(&bcm283x_type_info);
60
gen_set_pc_im(s, s->pc_curr);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
61
- tcg_syn = tcg_const_i32(syn);
115
+ TypeInfo ti = {
62
- gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
116
+ .name = bcm283x_socs[i].name,
63
- tcg_temp_free_i32(tcg_syn);
117
+ .parent = TYPE_BCM283X,
64
+ gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
118
+ .class_init = bcm283x_class_init,
65
s->base.is_jmp = DISAS_NORETURN;
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
123
}
66
}
124
67
125
type_init(bcm2836_register_types)
68
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
69
static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
127
index XXXXXXX..XXXXXXX 100644
70
TCGv_i32 tcg_el)
128
--- a/hw/arm/raspi.c
71
{
129
+++ b/hw/arm/raspi.c
72
- TCGv_i32 tcg_excp;
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
73
- TCGv_i32 tcg_syn;
131
BusState *bus;
74
-
132
DeviceState *carddev;
75
gen_set_condexec(s);
133
76
gen_set_pc_im(s, s->pc_curr);
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
77
- tcg_excp = tcg_const_i32(excp);
135
+ object_initialize(&s->soc, sizeof(s->soc),
78
- tcg_syn = tcg_const_i32(syn);
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
79
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
80
- tcg_temp_free_i32(tcg_syn);
138
&error_abort);
81
- tcg_temp_free_i32(tcg_excp);
82
+ gen_helper_exception_with_syndrome(cpu_env,
83
+ tcg_constant_i32(excp),
84
+ tcg_constant_i32(syn), tcg_el);
85
s->base.is_jmp = DISAS_NORETURN;
86
}
139
87
140
--
88
--
141
2.16.2
89
2.25.1
142
143
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-24-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 25 ++++++++++---------------
9
1 file changed, 10 insertions(+), 15 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
16
gen_op_iwmmxt_movq_M0_wRn(wrd);
17
switch ((insn >> 6) & 3) {
18
case 0:
19
- tmp2 = tcg_const_i32(0xff);
20
- tmp3 = tcg_const_i32((insn & 7) << 3);
21
+ tmp2 = tcg_constant_i32(0xff);
22
+ tmp3 = tcg_constant_i32((insn & 7) << 3);
23
break;
24
case 1:
25
- tmp2 = tcg_const_i32(0xffff);
26
- tmp3 = tcg_const_i32((insn & 3) << 4);
27
+ tmp2 = tcg_constant_i32(0xffff);
28
+ tmp3 = tcg_constant_i32((insn & 3) << 4);
29
break;
30
case 2:
31
- tmp2 = tcg_const_i32(0xffffffff);
32
- tmp3 = tcg_const_i32((insn & 1) << 5);
33
+ tmp2 = tcg_constant_i32(0xffffffff);
34
+ tmp3 = tcg_constant_i32((insn & 1) << 5);
35
break;
36
default:
37
- tmp2 = NULL;
38
- tmp3 = NULL;
39
+ g_assert_not_reached();
40
}
41
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
42
- tcg_temp_free_i32(tmp3);
43
- tcg_temp_free_i32(tmp2);
44
tcg_temp_free_i32(tmp);
45
gen_op_iwmmxt_movq_wRn_M0(wrd);
46
gen_op_iwmmxt_set_mup();
47
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
48
rd0 = (insn >> 16) & 0xf;
49
rd1 = (insn >> 0) & 0xf;
50
gen_op_iwmmxt_movq_M0_wRn(rd0);
51
- tmp = tcg_const_i32((insn >> 20) & 3);
52
iwmmxt_load_reg(cpu_V1, rd1);
53
- gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
54
- tcg_temp_free_i32(tmp);
55
+ gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1,
56
+ tcg_constant_i32((insn >> 20) & 3));
57
gen_op_iwmmxt_movq_wRn_M0(wrd);
58
gen_op_iwmmxt_set_mup();
59
break;
60
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
61
wrd = (insn >> 12) & 0xf;
62
rd0 = (insn >> 16) & 0xf;
63
gen_op_iwmmxt_movq_M0_wRn(rd0);
64
- tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
65
+ tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
66
gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
67
- tcg_temp_free_i32(tmp);
68
gen_op_iwmmxt_movq_wRn_M0(wrd);
69
gen_op_iwmmxt_set_mup();
70
gen_op_iwmmxt_set_cup();
71
--
72
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-25-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 22 +++++++++-------------
9
1 file changed, 9 insertions(+), 13 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
16
tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
17
tcg_gen_addi_i32(tcg_el, tcg_el, 3);
18
} else {
19
- tcg_el = tcg_const_i32(3);
20
+ tcg_el = tcg_constant_i32(3);
21
}
22
23
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
24
@@ -XXX,XX +XXX,XX @@ undef:
25
26
static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
27
{
28
- TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
29
+ TCGv_i32 tcg_reg;
30
int tgtmode = 0, regno = 0;
31
32
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
33
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
34
gen_set_condexec(s);
35
gen_set_pc_im(s, s->pc_curr);
36
tcg_reg = load_reg(s, rn);
37
- tcg_tgtmode = tcg_const_i32(tgtmode);
38
- tcg_regno = tcg_const_i32(regno);
39
- gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
40
- tcg_temp_free_i32(tcg_tgtmode);
41
- tcg_temp_free_i32(tcg_regno);
42
+ gen_helper_msr_banked(cpu_env, tcg_reg,
43
+ tcg_constant_i32(tgtmode),
44
+ tcg_constant_i32(regno));
45
tcg_temp_free_i32(tcg_reg);
46
s->base.is_jmp = DISAS_UPDATE_EXIT;
47
}
48
49
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
50
{
51
- TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
52
+ TCGv_i32 tcg_reg;
53
int tgtmode = 0, regno = 0;
54
55
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
56
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
57
gen_set_condexec(s);
58
gen_set_pc_im(s, s->pc_curr);
59
tcg_reg = tcg_temp_new_i32();
60
- tcg_tgtmode = tcg_const_i32(tgtmode);
61
- tcg_regno = tcg_const_i32(regno);
62
- gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno);
63
- tcg_temp_free_i32(tcg_tgtmode);
64
- tcg_temp_free_i32(tcg_regno);
65
+ gen_helper_mrs_banked(tcg_reg, cpu_env,
66
+ tcg_constant_i32(tgtmode),
67
+ tcg_constant_i32(regno));
68
store_reg(s, rn, tcg_reg);
69
s->base.is_jmp = DISAS_UPDATE_EXIT;
70
}
71
--
72
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-26-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 27 +++++++++------------------
9
1 file changed, 9 insertions(+), 18 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
16
} \
17
static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \
18
{ \
19
- TCGv_vec zero = tcg_const_zeros_vec_matching(d); \
20
+ TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \
21
tcg_gen_cmp_vec(COND, vece, d, a, zero); \
22
- tcg_temp_free_vec(zero); \
23
} \
24
void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \
25
uint32_t opr_sz, uint32_t max_sz) \
26
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
27
TCGv_i32 rval = tcg_temp_new_i32();
28
TCGv_i32 lsh = tcg_temp_new_i32();
29
TCGv_i32 rsh = tcg_temp_new_i32();
30
- TCGv_i32 zero = tcg_const_i32(0);
31
- TCGv_i32 max = tcg_const_i32(32);
32
+ TCGv_i32 zero = tcg_constant_i32(0);
33
+ TCGv_i32 max = tcg_constant_i32(32);
34
35
/*
36
* Rely on the TCG guarantee that out of range shifts produce
37
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
38
tcg_temp_free_i32(rval);
39
tcg_temp_free_i32(lsh);
40
tcg_temp_free_i32(rsh);
41
- tcg_temp_free_i32(zero);
42
- tcg_temp_free_i32(max);
43
}
44
45
void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
46
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
47
TCGv_i64 rval = tcg_temp_new_i64();
48
TCGv_i64 lsh = tcg_temp_new_i64();
49
TCGv_i64 rsh = tcg_temp_new_i64();
50
- TCGv_i64 zero = tcg_const_i64(0);
51
- TCGv_i64 max = tcg_const_i64(64);
52
+ TCGv_i64 zero = tcg_constant_i64(0);
53
+ TCGv_i64 max = tcg_constant_i64(64);
54
55
/*
56
* Rely on the TCG guarantee that out of range shifts produce
57
@@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
58
tcg_temp_free_i64(rval);
59
tcg_temp_free_i64(lsh);
60
tcg_temp_free_i64(rsh);
61
- tcg_temp_free_i64(zero);
62
- tcg_temp_free_i64(max);
63
}
64
65
static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
66
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
67
TCGv_i32 rval = tcg_temp_new_i32();
68
TCGv_i32 lsh = tcg_temp_new_i32();
69
TCGv_i32 rsh = tcg_temp_new_i32();
70
- TCGv_i32 zero = tcg_const_i32(0);
71
- TCGv_i32 max = tcg_const_i32(31);
72
+ TCGv_i32 zero = tcg_constant_i32(0);
73
+ TCGv_i32 max = tcg_constant_i32(31);
74
75
/*
76
* Rely on the TCG guarantee that out of range shifts produce
77
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
78
tcg_temp_free_i32(rval);
79
tcg_temp_free_i32(lsh);
80
tcg_temp_free_i32(rsh);
81
- tcg_temp_free_i32(zero);
82
- tcg_temp_free_i32(max);
83
}
84
85
void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
86
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
87
TCGv_i64 rval = tcg_temp_new_i64();
88
TCGv_i64 lsh = tcg_temp_new_i64();
89
TCGv_i64 rsh = tcg_temp_new_i64();
90
- TCGv_i64 zero = tcg_const_i64(0);
91
- TCGv_i64 max = tcg_const_i64(63);
92
+ TCGv_i64 zero = tcg_constant_i64(0);
93
+ TCGv_i64 max = tcg_constant_i64(63);
94
95
/*
96
* Rely on the TCG guarantee that out of range shifts produce
97
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
98
tcg_temp_free_i64(rval);
99
tcg_temp_free_i64(lsh);
100
tcg_temp_free_i64(rsh);
101
- tcg_temp_free_i64(zero);
102
- tcg_temp_free_i64(max);
103
}
104
105
static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
106
--
107
2.25.1
diff view generated by jsdifflib
1
From: Wei Huang <wei@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
time when guest VM runs. To find the physical base address correctly,
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
5
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
10
Signed-off-by: Wei Huang <wei@redhat.com>
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
7
---
15
dump.c | 14 +++++++++++---
8
target/arm/translate.c | 43 +++++++++++++-----------------------------
16
1 file changed, 11 insertions(+), 3 deletions(-)
9
1 file changed, 13 insertions(+), 30 deletions(-)
17
10
18
diff --git a/dump.c b/dump.c
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
13
--- a/target/arm/translate.c
21
+++ b/dump.c
14
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
15
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
23
16
* Note that on XScale all cp0..c13 registers do an access check
24
lines = g_strsplit((char *)vmci, "\n", -1);
17
* call in order to handle c15_cpar.
25
for (i = 0; lines[i]; i++) {
18
*/
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
19
- TCGv_ptr tmpptr;
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
20
- TCGv_i32 tcg_syn, tcg_isread;
28
+ const char *prefix = NULL;
21
uint32_t syndrome;
29
+
22
30
+ if (s->dump_info.d_machine == EM_X86_64) {
23
/* Note that since we are an implementation which takes an
31
+ prefix = "NUMBER(phys_base)=";
24
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
25
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
26
gen_set_condexec(s);
34
+ }
27
gen_set_pc_im(s, s->pc_curr);
35
+
28
- tmpptr = tcg_const_ptr(ri);
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
29
- tcg_syn = tcg_const_i32(syndrome);
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
30
- tcg_isread = tcg_const_i32(isread);
38
&phys_base) < 0) {
31
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
39
- warn_report("Failed to read NUMBER(phys_base)=");
32
- tcg_isread);
40
+ warn_report("Failed to read %s", prefix);
33
- tcg_temp_free_ptr(tmpptr);
34
- tcg_temp_free_i32(tcg_syn);
35
- tcg_temp_free_i32(tcg_isread);
36
+ gen_helper_access_check_cp_reg(cpu_env,
37
+ tcg_constant_ptr(ri),
38
+ tcg_constant_i32(syndrome),
39
+ tcg_constant_i32(isread));
40
} else if (ri->type & ARM_CP_RAISES_EXC) {
41
/*
42
* The readfn or writefn might raise an exception;
43
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
44
TCGv_i64 tmp64;
45
TCGv_i32 tmp;
46
if (ri->type & ARM_CP_CONST) {
47
- tmp64 = tcg_const_i64(ri->resetvalue);
48
+ tmp64 = tcg_constant_i64(ri->resetvalue);
49
} else if (ri->readfn) {
50
- TCGv_ptr tmpptr;
51
tmp64 = tcg_temp_new_i64();
52
- tmpptr = tcg_const_ptr(ri);
53
- gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
54
- tcg_temp_free_ptr(tmpptr);
55
+ gen_helper_get_cp_reg64(tmp64, cpu_env,
56
+ tcg_constant_ptr(ri));
57
} else {
58
tmp64 = tcg_temp_new_i64();
59
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
60
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
41
} else {
61
} else {
42
s->dump_info.phys_base = phys_base;
62
TCGv_i32 tmp;
63
if (ri->type & ARM_CP_CONST) {
64
- tmp = tcg_const_i32(ri->resetvalue);
65
+ tmp = tcg_constant_i32(ri->resetvalue);
66
} else if (ri->readfn) {
67
- TCGv_ptr tmpptr;
68
tmp = tcg_temp_new_i32();
69
- tmpptr = tcg_const_ptr(ri);
70
- gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
71
- tcg_temp_free_ptr(tmpptr);
72
+ gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
73
} else {
74
tmp = load_cpu_offset(ri->fieldoffset);
75
}
76
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
77
tcg_temp_free_i32(tmplo);
78
tcg_temp_free_i32(tmphi);
79
if (ri->writefn) {
80
- TCGv_ptr tmpptr = tcg_const_ptr(ri);
81
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
82
- tcg_temp_free_ptr(tmpptr);
83
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
84
+ tmp64);
85
} else {
86
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
87
}
88
tcg_temp_free_i64(tmp64);
89
} else {
90
+ TCGv_i32 tmp = load_reg(s, rt);
91
if (ri->writefn) {
92
- TCGv_i32 tmp;
93
- TCGv_ptr tmpptr;
94
- tmp = load_reg(s, rt);
95
- tmpptr = tcg_const_ptr(ri);
96
- gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
97
- tcg_temp_free_ptr(tmpptr);
98
+ gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
99
tcg_temp_free_i32(tmp);
100
} else {
101
- TCGv_i32 tmp = load_reg(s, rt);
102
store_cpu_offset(tmp, ri->fieldoffset, 4);
103
}
43
}
104
}
44
--
105
--
45
2.16.2
106
2.25.1
46
47
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-28-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 8 ++------
9
1 file changed, 2 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
16
}
17
18
addr = tcg_temp_new_i32();
19
- tmp = tcg_const_i32(mode);
20
/* get_r13_banked() will raise an exception if called from System mode */
21
gen_set_condexec(s);
22
gen_set_pc_im(s, s->pc_curr);
23
- gen_helper_get_r13_banked(addr, cpu_env, tmp);
24
- tcg_temp_free_i32(tmp);
25
+ gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
26
switch (amode) {
27
case 0: /* DA */
28
offset = -4;
29
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
30
abort();
31
}
32
tcg_gen_addi_i32(addr, addr, offset);
33
- tmp = tcg_const_i32(mode);
34
- gen_helper_set_r13_banked(cpu_env, tmp, addr);
35
- tcg_temp_free_i32(tmp);
36
+ gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
37
}
38
tcg_temp_free_i32(addr);
39
s->base.is_jmp = DISAS_UPDATE_EXIT;
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-29-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 11 +++++------
9
1 file changed, 5 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a,
16
void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32),
17
int logic_cc, StoreRegKind kind)
18
{
19
- TCGv_i32 tmp1, tmp2;
20
+ TCGv_i32 tmp1;
21
uint32_t imm;
22
23
imm = ror32(a->imm, a->rot);
24
if (logic_cc && a->rot) {
25
tcg_gen_movi_i32(cpu_CF, imm >> 31);
26
}
27
- tmp2 = tcg_const_i32(imm);
28
tmp1 = load_reg(s, a->rn);
29
30
- gen(tmp1, tmp1, tmp2);
31
- tcg_temp_free_i32(tmp2);
32
+ gen(tmp1, tmp1, tcg_constant_i32(imm));
33
34
if (logic_cc) {
35
gen_logic_CC(tmp1);
36
@@ -XXX,XX +XXX,XX @@ static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a,
37
if (logic_cc && a->rot) {
38
tcg_gen_movi_i32(cpu_CF, imm >> 31);
39
}
40
- tmp = tcg_const_i32(imm);
41
42
- gen(tmp, tmp);
43
+ tmp = tcg_temp_new_i32();
44
+ gen(tmp, tcg_constant_i32(imm));
45
+
46
if (logic_cc) {
47
gen_logic_CC(tmp);
48
}
49
--
50
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-30-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 11 +++--------
9
1 file changed, 3 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_ADR(DisasContext *s, arg_ri *a)
16
17
static bool trans_MOVW(DisasContext *s, arg_MOVW *a)
18
{
19
- TCGv_i32 tmp;
20
-
21
if (!ENABLE_ARCH_6T2) {
22
return false;
23
}
24
25
- tmp = tcg_const_i32(a->imm);
26
- store_reg(s, a->rd, tmp);
27
+ store_reg(s, a->rd, tcg_constant_i32(a->imm));
28
return true;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a)
32
t0 = load_reg(s, a->rm);
33
t1 = load_reg(s, a->rn);
34
tcg_gen_mulu2_i32(t0, t1, t0, t1);
35
- zero = tcg_const_i32(0);
36
+ zero = tcg_constant_i32(0);
37
t2 = load_reg(s, a->ra);
38
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
39
tcg_temp_free_i32(t2);
40
t2 = load_reg(s, a->rd);
41
tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero);
42
tcg_temp_free_i32(t2);
43
- tcg_temp_free_i32(zero);
44
store_reg(s, a->ra, t0);
45
store_reg(s, a->rd, t1);
46
return true;
47
@@ -XXX,XX +XXX,XX @@ static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz)
48
default:
49
g_assert_not_reached();
50
}
51
- t3 = tcg_const_i32(1 << sz);
52
+ t3 = tcg_constant_i32(1 << sz);
53
if (c) {
54
gen_helper_crc32c(t1, t1, t2, t3);
55
} else {
56
gen_helper_crc32(t1, t1, t2, t3);
57
}
58
tcg_temp_free_i32(t2);
59
- tcg_temp_free_i32(t3);
60
store_reg(s, a->rd, t1);
61
return true;
62
}
63
--
64
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-31-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 7 +++----
9
1 file changed, 3 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a)
16
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
17
return false;
18
}
19
- tmp = tcg_const_i32(a->sysm);
20
- gen_helper_v7m_mrs(tmp, cpu_env, tmp);
21
+ tmp = tcg_temp_new_i32();
22
+ gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm));
23
store_reg(s, a->rd, tmp);
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
27
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
28
return false;
29
}
30
- addr = tcg_const_i32((a->mask << 10) | a->sysm);
31
+ addr = tcg_constant_i32((a->mask << 10) | a->sysm);
32
reg = load_reg(s, a->rn);
33
gen_helper_v7m_msr(cpu_env, addr, reg);
34
- tcg_temp_free_i32(addr);
35
tcg_temp_free_i32(reg);
36
/* If we wrote to CONTROL, the EL might have changed */
37
gen_rebuild_hflags(s, true);
38
--
39
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-32-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 14 +++++---------
9
1 file changed, 5 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_TT(DisasContext *s, arg_TT *a)
16
}
17
18
addr = load_reg(s, a->rn);
19
- tmp = tcg_const_i32((a->A << 1) | a->T);
20
- gen_helper_v7m_tt(tmp, cpu_env, addr, tmp);
21
+ tmp = tcg_temp_new_i32();
22
+ gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T));
23
tcg_temp_free_i32(addr);
24
store_reg(s, a->rd, tmp);
25
return true;
26
@@ -XXX,XX +XXX,XX @@ static bool trans_PKH(DisasContext *s, arg_PKH *a)
27
static bool op_sat(DisasContext *s, arg_sat *a,
28
void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
29
{
30
- TCGv_i32 tmp, satimm;
31
+ TCGv_i32 tmp;
32
int shift = a->imm;
33
34
if (!ENABLE_ARCH_6) {
35
@@ -XXX,XX +XXX,XX @@ static bool op_sat(DisasContext *s, arg_sat *a,
36
tcg_gen_shli_i32(tmp, tmp, shift);
37
}
38
39
- satimm = tcg_const_i32(a->satimm);
40
- gen(tmp, cpu_env, tmp, satimm);
41
- tcg_temp_free_i32(satimm);
42
+ gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm));
43
44
store_reg(s, a->rd, tmp);
45
return true;
46
@@ -XXX,XX +XXX,XX @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub)
47
* a non-zero multiplicand lowpart, and the correct result
48
* lowpart for rounding.
49
*/
50
- TCGv_i32 zero = tcg_const_i32(0);
51
- tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1);
52
- tcg_temp_free_i32(zero);
53
+ tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1);
54
} else {
55
tcg_gen_add_i32(t1, t1, t3);
56
}
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-33-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
16
{
17
int i, j, n, list, mem_idx;
18
bool user = a->u;
19
- TCGv_i32 addr, tmp, tmp2;
20
+ TCGv_i32 addr, tmp;
21
22
if (user) {
23
/* STM (user) */
24
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
25
26
if (user && i != 15) {
27
tmp = tcg_temp_new_i32();
28
- tmp2 = tcg_const_i32(i);
29
- gen_helper_get_user_reg(tmp, cpu_env, tmp2);
30
- tcg_temp_free_i32(tmp2);
31
+ gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i));
32
} else {
33
tmp = load_reg(s, i);
34
}
35
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
36
bool loaded_base;
37
bool user = a->u;
38
bool exc_return = false;
39
- TCGv_i32 addr, tmp, tmp2, loaded_var;
40
+ TCGv_i32 addr, tmp, loaded_var;
41
42
if (user) {
43
/* LDM (user), LDM (exception return) */
44
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
45
tmp = tcg_temp_new_i32();
46
gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
47
if (user) {
48
- tmp2 = tcg_const_i32(i);
49
- gen_helper_set_user_reg(cpu_env, tmp2, tmp);
50
- tcg_temp_free_i32(tmp2);
51
+ gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp);
52
tcg_temp_free_i32(tmp);
53
} else if (i == a->rn) {
54
loaded_var = tmp;
55
--
56
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-34-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 16 +++++-----------
9
1 file changed, 5 insertions(+), 11 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
16
17
s->eci_handled = true;
18
19
- zero = tcg_const_i32(0);
20
+ zero = tcg_constant_i32(0);
21
for (i = 0; i < 15; i++) {
22
if (extract32(a->list, i, 1)) {
23
/* Clear R[i] */
24
@@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
25
* Clear APSR (by calling the MSR helper with the same argument
26
* as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
27
*/
28
- TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
29
- gen_helper_v7m_msr(cpu_env, maskreg, zero);
30
- tcg_temp_free_i32(maskreg);
31
+ gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero);
32
}
33
- tcg_temp_free_i32(zero);
34
clear_eci_state(s);
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
38
store_reg(s, 14, tmp);
39
if (a->size != 4) {
40
/* DLSTP: set FPSCR.LTPSIZE */
41
- tmp = tcg_const_i32(a->size);
42
- store_cpu_field(tmp, v7m.ltpsize);
43
+ store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
44
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
45
}
46
return true;
47
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
48
*/
49
bool ok = vfp_access_check(s);
50
assert(ok);
51
- tmp = tcg_const_i32(a->size);
52
- store_cpu_field(tmp, v7m.ltpsize);
53
+ store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize);
54
/*
55
* LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)
56
* when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.
57
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
58
gen_set_label(loopend);
59
if (a->tp) {
60
/* Exits from tail-pred loops must reset LTPSIZE to 4 */
61
- tmp = tcg_const_i32(4);
62
- store_cpu_field(tmp, v7m.ltpsize);
63
+ store_cpu_field(tcg_constant_i32(4), v7m.ltpsize);
64
}
65
/* End TB, continuing to following insn */
66
gen_jmp_tb(s, s->base.pc_next, 1);
67
--
68
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-35-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 9 +++------
9
1 file changed, 3 insertions(+), 6 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
16
return true;
17
}
18
19
- tmp = tcg_const_i32(a->im);
20
+ tmp = tcg_constant_i32(a->im);
21
/* FAULTMASK */
22
if (a->F) {
23
- addr = tcg_const_i32(19);
24
+ addr = tcg_constant_i32(19);
25
gen_helper_v7m_msr(cpu_env, addr, tmp);
26
- tcg_temp_free_i32(addr);
27
}
28
/* PRIMASK */
29
if (a->I) {
30
- addr = tcg_const_i32(16);
31
+ addr = tcg_constant_i32(16);
32
gen_helper_v7m_msr(cpu_env, addr, tmp);
33
- tcg_temp_free_i32(addr);
34
}
35
gen_rebuild_hflags(s, false);
36
- tcg_temp_free_i32(tmp);
37
gen_lookup_tb(s);
38
return true;
39
}
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-36-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 7 +++----
9
1 file changed, 3 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
16
}
17
18
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
19
+ zero = tcg_constant_i32(0);
20
if (a->rn == 15) {
21
- rn = tcg_const_i32(0);
22
+ rn = zero;
23
} else {
24
rn = load_reg(s, a->rn);
25
}
26
if (a->rm == 15) {
27
- rm = tcg_const_i32(0);
28
+ rm = zero;
29
} else {
30
rm = load_reg(s, a->rm);
31
}
32
@@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
33
}
34
35
arm_test_cc(&c, a->fcond);
36
- zero = tcg_const_i32(0);
37
tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
38
arm_free_cc(&c);
39
- tcg_temp_free_i32(zero);
40
41
store_reg(s, a->rd, rn);
42
tcg_temp_free_i32(rm);
43
--
44
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-37-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 12 ++++--------
9
1 file changed, 4 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
16
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
17
{
18
if (sve_access_check(s)) {
19
- TCGv_i64 start = tcg_const_i64(a->imm1);
20
- TCGv_i64 incr = tcg_const_i64(a->imm2);
21
+ TCGv_i64 start = tcg_constant_i64(a->imm1);
22
+ TCGv_i64 incr = tcg_constant_i64(a->imm2);
23
do_index(s, a->esz, a->rd, start, incr);
24
- tcg_temp_free_i64(start);
25
- tcg_temp_free_i64(incr);
26
}
27
return true;
28
}
29
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
30
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
31
{
32
if (sve_access_check(s)) {
33
- TCGv_i64 start = tcg_const_i64(a->imm);
34
+ TCGv_i64 start = tcg_constant_i64(a->imm);
35
TCGv_i64 incr = cpu_reg(s, a->rm);
36
do_index(s, a->esz, a->rd, start, incr);
37
- tcg_temp_free_i64(start);
38
}
39
return true;
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
42
{
43
if (sve_access_check(s)) {
44
TCGv_i64 start = cpu_reg(s, a->rn);
45
- TCGv_i64 incr = tcg_const_i64(a->imm);
46
+ TCGv_i64 incr = tcg_constant_i64(a->imm);
47
do_index(s, a->esz, a->rd, start, incr);
48
- tcg_temp_free_i64(incr);
49
}
50
return true;
51
}
52
--
53
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-38-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 18 ++++++------------
9
1 file changed, 6 insertions(+), 12 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a)
16
tcg_gen_ext32s_i64(reg, reg);
17
}
18
} else {
19
- TCGv_i64 t = tcg_const_i64(inc);
20
- do_sat_addsub_32(reg, t, a->u, a->d);
21
- tcg_temp_free_i64(t);
22
+ do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d);
23
}
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a)
27
TCGv_i64 reg = cpu_reg(s, a->rd);
28
29
if (inc != 0) {
30
- TCGv_i64 t = tcg_const_i64(inc);
31
- do_sat_addsub_64(reg, t, a->u, a->d);
32
- tcg_temp_free_i64(t);
33
+ do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d);
34
}
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
38
39
if (inc != 0) {
40
if (sve_access_check(s)) {
41
- TCGv_i64 t = tcg_const_i64(a->d ? -inc : inc);
42
tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd),
43
vec_full_reg_offset(s, a->rn),
44
- t, fullsz, fullsz);
45
- tcg_temp_free_i64(t);
46
+ tcg_constant_i64(a->d ? -inc : inc),
47
+ fullsz, fullsz);
48
}
49
} else {
50
do_mov_z(s, a->rd, a->rn);
51
@@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a)
52
53
if (inc != 0) {
54
if (sve_access_check(s)) {
55
- TCGv_i64 t = tcg_const_i64(inc);
56
- do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d);
57
- tcg_temp_free_i64(t);
58
+ do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
59
+ tcg_constant_i64(inc), a->u, a->d);
60
}
61
} else {
62
do_mov_z(s, a->rd, a->rn);
63
--
64
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-39-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 13 ++++---------
9
1 file changed, 4 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
16
if (sve_access_check(s)) {
17
/* Decode the VFP immediate. */
18
uint64_t imm = vfp_expand_imm(a->esz, a->imm);
19
- TCGv_i64 t_imm = tcg_const_i64(imm);
20
- do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
21
- tcg_temp_free_i64(t_imm);
22
+ do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm));
23
}
24
return true;
25
}
26
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
27
return false;
28
}
29
if (sve_access_check(s)) {
30
- TCGv_i64 t_imm = tcg_const_i64(a->imm);
31
- do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
32
- tcg_temp_free_i64(t_imm);
33
+ do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
34
}
35
return true;
36
}
37
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
38
}
39
if (sve_access_check(s)) {
40
unsigned vsz = vec_full_reg_size(s);
41
- TCGv_i64 t_imm = tcg_const_i64(a->imm);
42
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
43
pred_full_reg_offset(s, a->pg),
44
- t_imm, vsz, vsz, 0, fns[a->esz]);
45
- tcg_temp_free_i64(t_imm);
46
+ tcg_constant_i64(a->imm),
47
+ vsz, vsz, 0, fns[a->esz]);
48
}
49
return true;
50
}
51
--
52
2.25.1
diff view generated by jsdifflib
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
From: Richard Henderson <richard.henderson@linaro.org>
2
code for keeping the secondary CPUs in a pen needs to have
3
a version for A64 as well as A32. Without this, the
4
secondary CPUs go into an infinite loop of taking undefined
5
instruction exceptions.
6
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-40-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
10
---
7
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
8
target/arm/translate-sve.c | 12 ++++--------
12
1 file changed, 40 insertions(+), 1 deletion(-)
9
1 file changed, 4 insertions(+), 8 deletions(-)
13
10
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
13
--- a/target/arm/translate-sve.c
17
+++ b/hw/arm/raspi.c
14
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
16
if (is_power_of_2(vsz)) {
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
17
tcg_gen_andi_i32(last, last, vsz - 1);
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
18
} else {
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
19
- TCGv_i32 max = tcg_const_i32(vsz);
23
20
- TCGv_i32 zero = tcg_const_i32(0);
24
/* Table of Linux board IDs for different Pi versions */
21
+ TCGv_i32 max = tcg_constant_i32(vsz);
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
22
+ TCGv_i32 zero = tcg_constant_i32(0);
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
23
tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last);
27
info->smp_loader_start);
24
- tcg_temp_free_i32(max);
25
- tcg_temp_free_i32(zero);
26
}
28
}
27
}
29
28
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
29
@@ -XXX,XX +XXX,XX @@ static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz)
31
+{
30
if (is_power_of_2(vsz)) {
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
31
tcg_gen_andi_i32(last, last, vsz - 1);
33
+ * The mechanism for doing the spin-table is also entirely different.
32
} else {
34
+ * We must have four 64-bit fields at absolute addresses
33
- TCGv_i32 max = tcg_const_i32(vsz - (1 << esz));
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
34
- TCGv_i32 zero = tcg_const_i32(0);
36
+ * our CPUs, and which we must ensure are zero initialized before
35
+ TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz));
37
+ * the primary CPU goes into the kernel. We put these variables inside
36
+ TCGv_i32 zero = tcg_constant_i32(0);
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
37
tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last);
39
+ */
38
- tcg_temp_free_i32(max);
40
+ static const uint32_t smpboot[] = {
39
- tcg_temp_free_i32(zero);
41
+ 0xd2801b05, /* mov x5, 0xd8 */
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
43
+ 0x924004c6, /* and x6, x6, #0x3 */
44
+ 0xd503205f, /* spin: wfe */
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
46
+ 0xb4ffffc4, /* cbz x4, spin */
47
+ 0xd2800000, /* mov x0, #0x0 */
48
+ 0xd2800001, /* mov x1, #0x0 */
49
+ 0xd2800002, /* mov x2, #0x0 */
50
+ 0xd2800003, /* mov x3, #0x0 */
51
+ 0xd61f0080, /* br x4 */
52
+ };
53
+
54
+ static const uint64_t spintables[] = {
55
+ 0, 0, 0, 0
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
63
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
65
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
68
/* Pi2 and Pi3 requires SMP setup */
69
if (version >= 2) {
70
binfo.smp_loader_start = SMPBOOT_ADDR;
71
- binfo.write_secondary_boot = write_smpboot;
72
+ if (version == 2) {
73
+ binfo.write_secondary_boot = write_smpboot;
74
+ } else {
75
+ binfo.write_secondary_boot = write_smpboot64;
76
+ }
77
binfo.secondary_cpu_reset_hook = reset_secondary;
78
}
40
}
41
}
79
42
80
--
43
--
81
2.16.2
44
2.25.1
82
83
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-41-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 7 +++----
9
1 file changed, 3 insertions(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
16
bool before, TCGv_i64 reg_val)
17
{
18
TCGv_i32 last = tcg_temp_new_i32();
19
- TCGv_i64 ele, cmp, zero;
20
+ TCGv_i64 ele, cmp;
21
22
find_last_active(s, last, esz, pg);
23
24
@@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
25
ele = load_last_active(s, last, rm, esz);
26
tcg_temp_free_i32(last);
27
28
- zero = tcg_const_i64(0);
29
- tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val);
30
+ tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0),
31
+ ele, reg_val);
32
33
- tcg_temp_free_i64(zero);
34
tcg_temp_free_i64(cmp);
35
tcg_temp_free_i64(ele);
36
}
37
--
38
2.25.1
diff view generated by jsdifflib
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
From: Richard Henderson <richard.henderson@linaro.org>
2
just hard-code the CPU type they use rather than having it passed
3
through as an object property. This then lets us put the initialization
4
of the CPU object in init rather than realize.
5
2
6
Note that this change means that it's no longer possible on
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
the command line to use -cpu to ask for a different kind of
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
CPU than the SoC supports. This was never a supported thing to
5
Message-id: 20220426163043.100432-42-richard.henderson@linaro.org
9
do anyway; we were just not sanity-checking the command line.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 20 +++++++-------------
9
1 file changed, 7 insertions(+), 13 deletions(-)
10
10
11
This does require us to only build the bcm2837 object on
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
13
due to the missing cortex-a53 device and "make check" will fail.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
21
hw/arm/raspi.c | 2 --
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
13
--- a/target/arm/translate-sve.c
27
+++ b/hw/arm/bcm2836.c
14
+++ b/target/arm/translate-sve.c
28
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a)
29
16
static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
30
struct BCM283XInfo {
31
const char *name;
32
+ const char *cpu_type;
33
int clusterid;
34
};
35
36
static const BCM283XInfo bcm283x_socs[] = {
37
{
38
.name = TYPE_BCM2836,
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
40
.clusterid = 0xf,
41
},
42
+#ifdef TARGET_AARCH64
43
{
44
.name = TYPE_BCM2837,
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
46
.clusterid = 0x0,
47
},
48
+#endif
49
};
50
51
static void bcm2836_init(Object *obj)
52
{
17
{
53
BCM283XState *s = BCM283X(obj);
18
TCGv_i64 op0, op1, t0, t1, tmax;
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
19
- TCGv_i32 t2, t3;
55
+ const BCM283XInfo *info = bc->info;
20
+ TCGv_i32 t2;
56
+ int n;
21
TCGv_ptr ptr;
57
+
22
unsigned vsz = vec_full_reg_size(s);
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
23
unsigned desc = 0;
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
24
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
60
+ info->cpu_type);
25
}
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
26
}
62
+ &error_abort);
27
63
+ }
28
- tmax = tcg_const_i64(vsz >> a->esz);
64
29
+ tmax = tcg_constant_i64(vsz >> a->esz);
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
30
if (eq) {
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
31
/* Equality means one more iteration. */
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
32
tcg_gen_addi_i64(t0, t0, 1);
68
33
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
69
/* common peripherals from bcm2835 */
34
70
35
/* Bound to the maximum. */
71
- obj = OBJECT(dev);
36
tcg_gen_umin_i64(t0, t0, tmax);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
37
- tcg_temp_free_i64(tmax);
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
38
74
- s->cpu_type);
39
/* Set the count to zero if the condition is false. */
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
40
tcg_gen_movi_i64(t1, 0);
76
- &error_abort);
41
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
77
- }
42
78
-
43
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
44
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
80
if (obj == NULL) {
45
- t3 = tcg_const_i32(desc);
81
error_setg(errp, "%s: required ram link not found: %s",
46
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
47
ptr = tcg_temp_new_ptr();
48
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
49
50
if (a->lt) {
51
- gen_helper_sve_whilel(t2, ptr, t2, t3);
52
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
53
} else {
54
- gen_helper_sve_whileg(t2, ptr, t2, t3);
55
+ gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc));
56
}
57
do_pred_flags(t2);
58
59
tcg_temp_free_ptr(ptr);
60
tcg_temp_free_i32(t2);
61
- tcg_temp_free_i32(t3);
62
return true;
83
}
63
}
84
64
85
static Property bcm2836_props[] = {
65
static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
66
{
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
67
TCGv_i64 op0, op1, diff, t1, tmax;
88
BCM283X_NCPUS),
68
- TCGv_i32 t2, t3;
89
DEFINE_PROP_END_OF_LIST()
69
+ TCGv_i32 t2;
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
70
TCGv_ptr ptr;
91
index XXXXXXX..XXXXXXX 100644
71
unsigned vsz = vec_full_reg_size(s);
92
--- a/hw/arm/raspi.c
72
unsigned desc = 0;
93
+++ b/hw/arm/raspi.c
73
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
74
op0 = read_cpu_reg(s, a->rn, 1);
95
/* Setup the SOC */
75
op1 = read_cpu_reg(s, a->rm, 1);
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
76
97
&error_abort);
77
- tmax = tcg_const_i64(vsz);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
78
+ tmax = tcg_constant_i64(vsz);
99
- &error_abort);
79
diff = tcg_temp_new_i64();
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
80
101
&error_abort);
81
if (a->rw) {
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
82
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
83
84
/* Bound to the maximum. */
85
tcg_gen_umin_i64(diff, diff, tmax);
86
- tcg_temp_free_i64(tmax);
87
88
/* Since we're bounded, pass as a 32-bit type. */
89
t2 = tcg_temp_new_i32();
90
@@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a)
91
92
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
93
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
94
- t3 = tcg_const_i32(desc);
95
96
ptr = tcg_temp_new_ptr();
97
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
98
99
- gen_helper_sve_whilel(t2, ptr, t2, t3);
100
+ gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
101
do_pred_flags(t2);
102
103
tcg_temp_free_ptr(ptr);
104
tcg_temp_free_i32(t2);
105
- tcg_temp_free_i32(t3);
106
return true;
107
}
108
103
--
109
--
104
2.16.2
110
2.25.1
105
106
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
doesn't really corespond to anything in real hardware and server as a
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
8
Change the code to explicitly evaluate state of interrupts reported
9
via USR1 and USR2 against corresponding masking bits and use the to
10
detemine if IRQ line should be asserted or not.
11
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
13
reasons:
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-43-richard.henderson@linaro.org
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
7
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
8
target/arm/translate-sve.c | 12 ++++--------
34
1 file changed, 16 insertions(+), 8 deletions(-)
9
1 file changed, 4 insertions(+), 8 deletions(-)
35
10
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
37
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
13
--- a/target/arm/translate-sve.c
39
+++ b/hw/char/imx_serial.c
14
+++ b/target/arm/translate-sve.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
15
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
41
16
gen_helper_gvec_mem_scatter *fn = NULL;
42
static void imx_update(IMXSerialState *s)
17
bool be = s->be_data == MO_BE;
43
{
18
bool mte = s->mte_active[0];
44
- uint32_t flags;
19
- TCGv_i64 imm;
45
+ uint32_t usr1;
20
46
+ uint32_t usr2;
21
if (a->esz < a->msz || (a->esz == a->msz && !a->u)) {
47
+ uint32_t mask;
22
return false;
48
23
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
24
/* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x])
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
25
* by loading the immediate into the scalar parameter.
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
26
*/
52
- } else {
27
- imm = tcg_const_i64(a->imm << a->msz);
53
- flags &= ~USR1_TRDY;
28
- do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn);
54
- }
29
- tcg_temp_free_i64(imm);
55
+ /*
30
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
31
+ tcg_constant_i64(a->imm << a->msz), a->msz, false, fn);
57
+ * UCR1, so we can get away with something as simple as the
32
return true;
58
+ * following:
59
+ */
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
33
}
71
34
72
static void imx_serial_reset(IMXSerialState *s)
35
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
36
gen_helper_gvec_mem_scatter *fn = NULL;
37
bool be = s->be_data == MO_BE;
38
bool mte = s->mte_active[0];
39
- TCGv_i64 imm;
40
41
if (a->esz < a->msz) {
42
return false;
43
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
44
/* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
45
* by loading the immediate into the scalar parameter.
46
*/
47
- imm = tcg_const_i64(a->imm << a->msz);
48
- do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn);
49
- tcg_temp_free_i64(imm);
50
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
51
+ tcg_constant_i64(a->imm << a->msz), a->msz, true, fn);
52
return true;
53
}
54
73
--
55
--
74
2.16.2
56
2.25.1
75
76
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-44-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 4 +---
9
1 file changed, 1 insertion(+), 3 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
16
}
17
if (sve_access_check(s)) {
18
unsigned vsz = vec_full_reg_size(s);
19
- TCGv_i64 c = tcg_const_i64(a->imm);
20
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
21
vec_full_reg_offset(s, a->rn),
22
- vsz, vsz, c, &op[a->esz]);
23
- tcg_temp_free_i64(c);
24
+ vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]);
25
}
26
return true;
27
}
28
--
29
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-45-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 15 +++++----------
9
1 file changed, 5 insertions(+), 10 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
16
return false;
17
}
18
if (sve_access_check(s)) {
19
- TCGv_i64 val = tcg_const_i64(a->imm);
20
- do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d);
21
- tcg_temp_free_i64(val);
22
+ do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
23
+ tcg_constant_i64(a->imm), u, d);
24
}
25
return true;
26
}
27
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
28
{
29
if (sve_access_check(s)) {
30
unsigned vsz = vec_full_reg_size(s);
31
- TCGv_i64 c = tcg_const_i64(a->imm);
32
-
33
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
34
vec_full_reg_offset(s, a->rn),
35
- c, vsz, vsz, 0, fn);
36
- tcg_temp_free_i64(c);
37
+ tcg_constant_i64(a->imm), vsz, vsz, 0, fn);
38
}
39
return true;
40
}
41
@@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
42
static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,
43
gen_helper_sve_fp2scalar *fn)
44
{
45
- TCGv_i64 temp = tcg_const_i64(imm);
46
- do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);
47
- tcg_temp_free_i64(temp);
48
+ do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16,
49
+ tcg_constant_i64(imm), fn);
50
}
51
52
#define DO_FP_IMM(NAME, name, const0, const1) \
53
--
54
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
In these cases, 't' did double-duty as zero source and
4
temporary destination. Split the two uses.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20220426163043.100432-46-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 17 ++++++++---------
12
1 file changed, 8 insertions(+), 9 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
19
{
20
TCGv_ptr dptr = tcg_temp_new_ptr();
21
TCGv_ptr gptr = tcg_temp_new_ptr();
22
- TCGv_i32 t;
23
+ TCGv_i32 t = tcg_temp_new_i32();
24
25
tcg_gen_addi_ptr(dptr, cpu_env, dofs);
26
tcg_gen_addi_ptr(gptr, cpu_env, gofs);
27
- t = tcg_const_i32(words);
28
29
- gen_helper_sve_predtest(t, dptr, gptr, t);
30
+ gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
31
tcg_temp_free_ptr(dptr);
32
tcg_temp_free_ptr(gptr);
33
34
@@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
35
36
tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
37
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
38
- t = tcg_const_i32(desc);
39
+ t = tcg_temp_new_i32();
40
41
- gen_fn(t, t_pd, t_pg, t);
42
+ gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
43
tcg_temp_free_ptr(t_pd);
44
tcg_temp_free_ptr(t_pg);
45
46
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
47
}
48
49
vsz = vec_full_reg_size(s);
50
- t = tcg_const_i32(simd_desc(vsz, vsz, 0));
51
+ t = tcg_temp_new_i32();
52
pd = tcg_temp_new_ptr();
53
zn = tcg_temp_new_ptr();
54
zm = tcg_temp_new_ptr();
55
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
56
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
57
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
58
59
- gen_fn(t, pd, zn, zm, pg, t);
60
+ gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
61
62
tcg_temp_free_ptr(pd);
63
tcg_temp_free_ptr(zn);
64
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
65
}
66
67
vsz = vec_full_reg_size(s);
68
- t = tcg_const_i32(simd_desc(vsz, vsz, a->imm));
69
+ t = tcg_temp_new_i32();
70
pd = tcg_temp_new_ptr();
71
zn = tcg_temp_new_ptr();
72
pg = tcg_temp_new_ptr();
73
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
74
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
75
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
76
77
- gen_fn(t, pd, zn, pg, t);
78
+ gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
79
80
tcg_temp_free_ptr(pd);
81
tcg_temp_free_ptr(zn);
82
--
83
2.25.1
diff view generated by jsdifflib
1
Our BCM2836 type is really a generic one that can be any of
1
From: Richard Henderson <richard.henderson@linaro.org>
2
the bcm283x family. Rename it accordingly. We change only
3
the names which are visible via the header file to the
4
rest of the QEMU code, leaving private function names
5
in bcm2836.c as they are.
6
2
7
This is a preliminary to making bcm283x be an abstract
3
In these cases, 't' did double-duty as zero source and
8
parent class to specific types for the bcm2836 and bcm2837.
4
temporary destination. Split the two uses and narrow
5
the scope of the temp.
9
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20220426163043.100432-47-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
11
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
12
target/arm/translate-sve.c | 18 ++++++++++--------
16
hw/arm/bcm2836.c | 17 +++++++++--------
13
1 file changed, 10 insertions(+), 8 deletions(-)
17
hw/arm/raspi.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
14
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
17
--- a/target/arm/translate-sve.c
23
+++ b/include/hw/arm/bcm2836.h
18
+++ b/target/arm/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
25
#include "hw/arm/bcm2835_peripherals.h"
20
TCGv_ptr n = tcg_temp_new_ptr();
26
#include "hw/intc/bcm2836_control.h"
21
TCGv_ptr m = tcg_temp_new_ptr();
27
22
TCGv_ptr g = tcg_temp_new_ptr();
28
-#define TYPE_BCM2836 "bcm2836"
23
- TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
24
+ TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
30
+#define TYPE_BCM283X "bcm283x"
25
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
26
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
32
27
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
33
-#define BCM2836_NCPUS 4
28
@@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a,
34
+#define BCM283X_NCPUS 4
29
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
35
30
36
-typedef struct BCM2836State {
31
if (a->s) {
37
+typedef struct BCM283XState {
32
- fn_s(t, d, n, m, g, t);
38
/*< private >*/
33
+ TCGv_i32 t = tcg_temp_new_i32();
39
DeviceState parent_obj;
34
+ fn_s(t, d, n, m, g, desc);
40
/*< public >*/
35
do_pred_flags(t);
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
36
+ tcg_temp_free_i32(t);
42
char *cpu_type;
37
} else {
43
uint32_t enabled_cpus;
38
- fn(d, n, m, g, t);
44
39
+ fn(d, n, m, g, desc);
45
- ARMCPU cpus[BCM2836_NCPUS];
40
}
46
+ ARMCPU cpus[BCM283X_NCPUS];
41
tcg_temp_free_ptr(d);
47
BCM2836ControlState control;
42
tcg_temp_free_ptr(n);
48
BCM2835PeripheralState peripherals;
43
tcg_temp_free_ptr(m);
49
-} BCM2836State;
44
tcg_temp_free_ptr(g);
50
+} BCM283XState;
45
- tcg_temp_free_i32(t);
51
46
return true;
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
56
+++ b/hw/arm/bcm2836.c
57
@@ -XXX,XX +XXX,XX @@
58
59
static void bcm2836_init(Object *obj)
60
{
61
- BCM2836State *s = BCM2836(obj);
62
+ BCM283XState *s = BCM283X(obj);
63
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
67
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
69
{
70
- BCM2836State *s = BCM2836(dev);
71
+ BCM283XState *s = BCM283X(dev);
72
Object *obj;
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
47
}
95
48
96
static Property bcm2836_props[] = {
49
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
50
TCGv_ptr d = tcg_temp_new_ptr();
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
51
TCGv_ptr n = tcg_temp_new_ptr();
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
52
TCGv_ptr g = tcg_temp_new_ptr();
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
53
- TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
101
+ BCM283X_NCPUS),
54
+ TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
102
DEFINE_PROP_END_OF_LIST()
55
103
};
56
tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
104
57
tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
58
tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
59
60
if (a->s) {
61
- fn_s(t, d, n, g, t);
62
+ TCGv_i32 t = tcg_temp_new_i32();
63
+ fn_s(t, d, n, g, desc);
64
do_pred_flags(t);
65
+ tcg_temp_free_i32(t);
66
} else {
67
- fn(d, n, g, t);
68
+ fn(d, n, g, desc);
69
}
70
tcg_temp_free_ptr(d);
71
tcg_temp_free_ptr(n);
72
tcg_temp_free_ptr(g);
73
- tcg_temp_free_i32(t);
74
return true;
106
}
75
}
107
76
108
static const TypeInfo bcm2836_type_info = {
109
- .name = TYPE_BCM2836,
110
+ .name = TYPE_BCM283X,
111
.parent = TYPE_DEVICE,
112
- .instance_size = sizeof(BCM2836State),
113
+ .instance_size = sizeof(BCM283XState),
114
.instance_init = bcm2836_init,
115
.class_init = bcm2836_class_init,
116
};
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/arm/raspi.c
120
+++ b/hw/arm/raspi.c
121
@@ -XXX,XX +XXX,XX @@
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
123
124
typedef struct RasPiState {
125
- BCM2836State soc;
126
+ BCM283XState soc;
127
MemoryRegion ram;
128
} RasPiState;
129
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
165
--
77
--
166
2.16.2
78
2.25.1
167
168
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220426163043.100432-48-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 54 ++++++++++----------------------------
9
1 file changed, 14 insertions(+), 40 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
16
return true;
17
}
18
19
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
20
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
21
temp = tcg_temp_new_i64();
22
t_zn = tcg_temp_new_ptr();
23
t_pg = tcg_temp_new_ptr();
24
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
25
fn(temp, t_zn, t_pg, desc);
26
tcg_temp_free_ptr(t_zn);
27
tcg_temp_free_ptr(t_pg);
28
- tcg_temp_free_i32(desc);
29
30
write_fp_dreg(s, a->rd, temp);
31
tcg_temp_free_i64(temp);
32
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
33
TCGv_i64 start, TCGv_i64 incr)
34
{
35
unsigned vsz = vec_full_reg_size(s);
36
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
37
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
38
TCGv_ptr t_zd = tcg_temp_new_ptr();
39
40
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
41
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
42
tcg_temp_free_i32(i32);
43
}
44
tcg_temp_free_ptr(t_zd);
45
- tcg_temp_free_i32(desc);
46
}
47
48
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
49
@@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
50
nptr = tcg_temp_new_ptr();
51
tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd));
52
tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn));
53
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
54
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
55
56
switch (esz) {
57
case MO_8:
58
@@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn,
59
60
tcg_temp_free_ptr(dptr);
61
tcg_temp_free_ptr(nptr);
62
- tcg_temp_free_i32(desc);
63
}
64
65
static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a)
66
@@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
67
gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d,
68
};
69
unsigned vsz = vec_full_reg_size(s);
70
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
71
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
72
TCGv_ptr t_zd = tcg_temp_new_ptr();
73
TCGv_ptr t_zn = tcg_temp_new_ptr();
74
TCGv_ptr t_pg = tcg_temp_new_ptr();
75
@@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
76
tcg_temp_free_ptr(t_zd);
77
tcg_temp_free_ptr(t_zn);
78
tcg_temp_free_ptr(t_pg);
79
- tcg_temp_free_i32(desc);
80
}
81
82
static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
83
@@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
84
gen_helper_sve_insr_s, gen_helper_sve_insr_d,
85
};
86
unsigned vsz = vec_full_reg_size(s);
87
- TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
88
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
89
TCGv_ptr t_zd = tcg_temp_new_ptr();
90
TCGv_ptr t_zn = tcg_temp_new_ptr();
91
92
@@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
93
94
tcg_temp_free_ptr(t_zd);
95
tcg_temp_free_ptr(t_zn);
96
- tcg_temp_free_i32(desc);
97
}
98
99
static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a)
100
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
101
TCGv_ptr t_d = tcg_temp_new_ptr();
102
TCGv_ptr t_n = tcg_temp_new_ptr();
103
TCGv_ptr t_m = tcg_temp_new_ptr();
104
- TCGv_i32 t_desc;
105
uint32_t desc = 0;
106
107
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
108
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
109
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
110
tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
111
tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm));
112
- t_desc = tcg_const_i32(desc);
113
114
- fn(t_d, t_n, t_m, t_desc);
115
+ fn(t_d, t_n, t_m, tcg_constant_i32(desc));
116
117
tcg_temp_free_ptr(t_d);
118
tcg_temp_free_ptr(t_n);
119
tcg_temp_free_ptr(t_m);
120
- tcg_temp_free_i32(t_desc);
121
return true;
122
}
123
124
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
125
unsigned vsz = pred_full_reg_size(s);
126
TCGv_ptr t_d = tcg_temp_new_ptr();
127
TCGv_ptr t_n = tcg_temp_new_ptr();
128
- TCGv_i32 t_desc;
129
uint32_t desc = 0;
130
131
tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
132
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
133
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
134
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
135
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
136
- t_desc = tcg_const_i32(desc);
137
138
- fn(t_d, t_n, t_desc);
139
+ fn(t_d, t_n, tcg_constant_i32(desc));
140
141
- tcg_temp_free_i32(t_desc);
142
tcg_temp_free_ptr(t_d);
143
tcg_temp_free_ptr(t_n);
144
return true;
145
@@ -XXX,XX +XXX,XX @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
146
* round up, as we do elsewhere, because we need the exact size.
147
*/
148
TCGv_ptr t_p = tcg_temp_new_ptr();
149
- TCGv_i32 t_desc;
150
unsigned desc = 0;
151
152
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
153
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
154
155
tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
156
- t_desc = tcg_const_i32(desc);
157
158
- gen_helper_sve_last_active_element(ret, t_p, t_desc);
159
+ gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
160
161
- tcg_temp_free_i32(t_desc);
162
tcg_temp_free_ptr(t_p);
163
}
164
165
@@ -XXX,XX +XXX,XX @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
166
TCGv_ptr t_pn = tcg_temp_new_ptr();
167
TCGv_ptr t_pg = tcg_temp_new_ptr();
168
unsigned desc = 0;
169
- TCGv_i32 t_desc;
170
171
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
172
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
173
174
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
175
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
176
- t_desc = tcg_const_i32(desc);
177
178
- gen_helper_sve_cntp(val, t_pn, t_pg, t_desc);
179
+ gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
180
tcg_temp_free_ptr(t_pn);
181
tcg_temp_free_ptr(t_pg);
182
- tcg_temp_free_i32(t_desc);
183
}
184
}
185
186
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
187
{
188
unsigned vsz = vec_full_reg_size(s);
189
unsigned p2vsz = pow2ceil(vsz);
190
- TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
191
+ TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
192
TCGv_ptr t_zn, t_pg, status;
193
TCGv_i64 temp;
194
195
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
196
tcg_temp_free_ptr(t_zn);
197
tcg_temp_free_ptr(t_pg);
198
tcg_temp_free_ptr(status);
199
- tcg_temp_free_i32(t_desc);
200
201
write_fp_dreg(s, a->rd, temp);
202
tcg_temp_free_i64(temp);
203
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
204
tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
205
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
206
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
207
- t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
208
+ t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
209
210
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
211
212
- tcg_temp_free_i32(t_desc);
213
tcg_temp_free_ptr(t_fpst);
214
tcg_temp_free_ptr(t_pg);
215
tcg_temp_free_ptr(t_rm);
216
@@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
217
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
218
219
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
220
- desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
221
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
222
fn(t_zd, t_zn, t_pg, scalar, status, desc);
223
224
- tcg_temp_free_i32(desc);
225
tcg_temp_free_ptr(status);
226
tcg_temp_free_ptr(t_pg);
227
tcg_temp_free_ptr(t_zn);
228
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
229
{
230
unsigned vsz = vec_full_reg_size(s);
231
TCGv_ptr t_pg;
232
- TCGv_i32 t_desc;
233
int desc = 0;
234
235
/*
236
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
237
}
238
239
desc = simd_desc(vsz, vsz, zt | desc);
240
- t_desc = tcg_const_i32(desc);
241
t_pg = tcg_temp_new_ptr();
242
243
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
244
- fn(cpu_env, t_pg, addr, t_desc);
245
+ fn(cpu_env, t_pg, addr, tcg_constant_i32(desc));
246
247
tcg_temp_free_ptr(t_pg);
248
- tcg_temp_free_i32(t_desc);
249
}
250
251
/* Indexed by [mte][be][dtype][nreg] */
252
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
253
TCGv_ptr t_zm = tcg_temp_new_ptr();
254
TCGv_ptr t_pg = tcg_temp_new_ptr();
255
TCGv_ptr t_zt = tcg_temp_new_ptr();
256
- TCGv_i32 t_desc;
257
int desc = 0;
258
259
if (s->mte_active[0]) {
260
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
261
desc <<= SVE_MTEDESC_SHIFT;
262
}
263
desc = simd_desc(vsz, vsz, desc | scale);
264
- t_desc = tcg_const_i32(desc);
265
266
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
267
tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
268
tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
269
- fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc);
270
+ fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
271
272
tcg_temp_free_ptr(t_zt);
273
tcg_temp_free_ptr(t_zm);
274
tcg_temp_free_ptr(t_pg);
275
- tcg_temp_free_i32(t_desc);
276
}
277
278
/* Indexed by [mte][be][ff][xs][u][msz]. */
279
--
280
2.25.1
diff view generated by jsdifflib
New patch
1
From: Damien Hedde <damien.hedde@greensocs.com>
1
2
3
As of now, cryptographic instructions ISAR fields are never cleared so
4
we can end up with a cpu with cryptographic instructions but no
5
floating-point/neon instructions which is not a possible configuration
6
according to Arm specifications.
7
8
In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
9
+ no support
10
+ cortex-a57/a72: cryptographic extension is optional,
11
floating-point/neon is not.
12
+ cortex-a53: crytographic extension is optional as well as
13
floating-point/neon. But cryptographic requires
14
floating-point/neon support.
15
16
Therefore we can safely clear the ISAR fields when neon is disabled.
17
18
Note that other Arm cpus seem to follow this. For example cortex-a55 is
19
like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
20
21
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20220427090117.6954-1-damien.hedde@greensocs.com
24
[PMM: fixed commit message typos]
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
target/arm/cpu.c | 9 +++++++++
28
1 file changed, 9 insertions(+)
29
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
35
unset_feature(env, ARM_FEATURE_NEON);
36
37
t = cpu->isar.id_aa64isar0;
38
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
39
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
40
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
44
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
45
cpu->isar.id_aa64isar0 = t;
46
47
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
48
cpu->isar.id_aa64pfr0 = t;
49
50
u = cpu->isar.id_isar5;
51
+ u = FIELD_DP32(u, ID_ISAR5, AES, 0);
52
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
53
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
54
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
55
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
56
cpu->isar.id_isar5 = u;
57
--
58
2.25.1
diff view generated by jsdifflib
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
From: Richard Henderson <richard.henderson@linaro.org>
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
3
is required for Linux to boot.
4
2
3
While defining these names, use the correct field width of 5 not 4 for
4
DBGWCR.MASK. This typo prevented setting a watchpoint larger than 32k.
5
6
Reported-by: Chris Howard <cvz185@web.de>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20220427051926.295223-1-richard.henderson@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
9
---
11
---
10
hw/arm/bcm2836.c | 11 +++++++----
12
target/arm/internals.h | 12 ++++++++++++
11
1 file changed, 7 insertions(+), 4 deletions(-)
13
target/arm/debug_helper.c | 10 +++++-----
14
target/arm/helper.c | 8 ++++----
15
target/arm/kvm64.c | 14 +++++++-------
16
4 files changed, 28 insertions(+), 16 deletions(-)
12
17
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
20
--- a/target/arm/internals.h
16
+++ b/hw/arm/bcm2836.c
21
+++ b/target/arm/internals.h
17
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
18
23
*/
19
struct BCM283XInfo {
24
#define FNC_RETURN_MIN_MAGIC 0xfefffffe
20
const char *name;
25
21
+ int clusterid;
26
+/* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
22
};
27
+FIELD(DBGWCR, E, 0, 1)
23
28
+FIELD(DBGWCR, PAC, 1, 2)
24
static const BCM283XInfo bcm283x_socs[] = {
29
+FIELD(DBGWCR, LSC, 3, 2)
25
{
30
+FIELD(DBGWCR, BAS, 5, 8)
26
.name = TYPE_BCM2836,
31
+FIELD(DBGWCR, HMC, 13, 1)
27
+ .clusterid = 0xf,
32
+FIELD(DBGWCR, SSC, 14, 2)
28
},
33
+FIELD(DBGWCR, LBN, 16, 4)
29
{
34
+FIELD(DBGWCR, WT, 20, 1)
30
.name = TYPE_BCM2837,
35
+FIELD(DBGWCR, MASK, 24, 5)
31
+ .clusterid = 0x0,
36
+FIELD(DBGWCR, SSCE, 29, 1)
32
},
37
+
33
};
38
/* We use a few fake FSR values for internal purposes in M profile.
34
39
* M profile cores don't have A/R format FSRs, but currently our
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
40
* get_phys_addr() code assumes A/R profile and reports failures via
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
41
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/debug_helper.c
44
+++ b/target/arm/debug_helper.c
45
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
46
* Non-Secure to simplify the code slightly compared to the full
47
* table in the ARM ARM.
48
*/
49
- pac = extract64(cr, 1, 2);
50
- hmc = extract64(cr, 13, 1);
51
- ssc = extract64(cr, 14, 2);
52
+ pac = FIELD_EX64(cr, DBGWCR, PAC);
53
+ hmc = FIELD_EX64(cr, DBGWCR, HMC);
54
+ ssc = FIELD_EX64(cr, DBGWCR, SSC);
55
56
switch (ssc) {
57
case 0:
58
@@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
59
g_assert_not_reached();
60
}
61
62
- wt = extract64(cr, 20, 1);
63
- lbn = extract64(cr, 16, 4);
64
+ wt = FIELD_EX64(cr, DBGWCR, WT);
65
+ lbn = FIELD_EX64(cr, DBGWCR, LBN);
66
67
if (wt && !linked_bp_matches(cpu, lbn)) {
68
return false;
69
diff --git a/target/arm/helper.c b/target/arm/helper.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/helper.c
72
+++ b/target/arm/helper.c
73
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
74
env->cpu_watchpoint[n] = NULL;
75
}
76
77
- if (!extract64(wcr, 0, 1)) {
78
+ if (!FIELD_EX64(wcr, DBGWCR, E)) {
79
/* E bit clear : watchpoint disabled */
80
return;
81
}
82
83
- switch (extract64(wcr, 3, 2)) {
84
+ switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
85
case 0:
86
/* LSC 00 is reserved and must behave as if the wp is disabled */
87
return;
88
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
89
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
90
* thus generating a watchpoint for every byte in the masked region.
91
*/
92
- mask = extract64(wcr, 24, 4);
93
+ mask = FIELD_EX64(wcr, DBGWCR, MASK);
94
if (mask == 1 || mask == 2) {
95
/* Reserved values of MASK; we must act as if the mask value was
96
* some non-reserved value, or as if the watchpoint were disabled.
97
@@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n)
98
wvr &= ~(len - 1);
99
} else {
100
/* Watchpoint covers bytes defined by the byte address select bits */
101
- int bas = extract64(wcr, 5, 8);
102
+ int bas = FIELD_EX64(wcr, DBGWCR, BAS);
103
int basstart;
104
105
if (extract64(wvr, 2, 1)) {
106
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/kvm64.c
109
+++ b/target/arm/kvm64.c
110
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
111
target_ulong len, int type)
37
{
112
{
38
BCM283XState *s = BCM283X(dev);
113
HWWatchpoint wp = {
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
114
- .wcr = 1, /* E=1, enable */
40
+ const BCM283XInfo *info = bc->info;
115
+ .wcr = R_DBGWCR_E_MASK, /* E=1, enable */
41
Object *obj;
116
.wvr = addr & (~0x7ULL),
42
Error *err = NULL;
117
.details = { .vaddr = addr, .len = len }
43
int n;
118
};
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
119
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
120
* HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
46
121
* valid whether EL3 is implemented or not
47
for (n = 0; n < BCM283X_NCPUS; n++) {
122
*/
48
- /* Mirror bcm2836, which has clusterid set to 0xf
123
- wp.wcr = deposit32(wp.wcr, 1, 2, 3);
49
- * TODO: this should be converted to a property of ARM_CPU
124
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3);
50
- */
125
51
- s->cpus[n].mp_affinity = 0xF00 | n;
126
switch (type) {
52
+ /* TODO: this should be converted to a property of ARM_CPU */
127
case GDB_WATCHPOINT_READ:
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
128
- wp.wcr = deposit32(wp.wcr, 3, 2, 1);
54
129
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1);
55
/* set periphbase/CBAR value for CPU-local registers */
130
wp.details.flags = BP_MEM_READ;
56
object_property_set_int(OBJECT(&s->cpus[n]),
131
break;
132
case GDB_WATCHPOINT_WRITE:
133
- wp.wcr = deposit32(wp.wcr, 3, 2, 2);
134
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2);
135
wp.details.flags = BP_MEM_WRITE;
136
break;
137
case GDB_WATCHPOINT_ACCESS:
138
- wp.wcr = deposit32(wp.wcr, 3, 2, 3);
139
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3);
140
wp.details.flags = BP_MEM_ACCESS;
141
break;
142
default:
143
@@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr,
144
int bits = ctz64(len);
145
146
wp.wvr &= ~((1 << bits) - 1);
147
- wp.wcr = deposit32(wp.wcr, 24, 4, bits);
148
- wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
149
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits);
150
+ wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff);
151
} else {
152
return -ENOBUFS;
153
}
57
--
154
--
58
2.16.2
155
2.25.1
59
156
60
157
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
The Record bit in the Context Descriptor tells the SMMU to report fault
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
4
events to the event queue. Since we don't cache the Record bit at the
5
controller which is supported in QEMU using the imx_fec.c module
5
moment, access faults from a cached Context Descriptor are never
6
(actually called imx.enet for this model.)
6
reported. Store the Record bit in the cached SMMUTransCfg.
7
7
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
8
Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback")
9
imx.enet device like this:
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
#define FSL_IMX6_ENET_MAC_IRQ 119
12
Message-id: 20220427111543.124620-1-jean-philippe@linaro.org
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
14
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
15
hw/arm/smmuv3-internal.h | 1 -
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
16
include/hw/arm/smmu-common.h | 1 +
46
2 files changed, 29 insertions(+), 3 deletions(-)
17
hw/arm/smmuv3.c | 14 +++++++-------
18
3 files changed, 8 insertions(+), 8 deletions(-)
47
19
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
20
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
49
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
22
--- a/hw/arm/smmuv3-internal.h
51
+++ b/include/hw/arm/fsl-imx6.h
23
+++ b/hw/arm/smmuv3-internal.h
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
24
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo {
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
25
SMMUEventType type;
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
26
uint32_t sid;
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
27
bool recorded;
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
28
- bool record_trans_faults;
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
29
bool inval_ste_allowed;
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
30
union {
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
31
struct {
60
#define FSL_IMX6_PCIE1_IRQ 120
32
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
61
#define FSL_IMX6_PCIE2_IRQ 121
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
34
--- a/include/hw/arm/smmu-common.h
66
+++ b/hw/net/imx_fec.c
35
+++ b/include/hw/arm/smmu-common.h
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
36
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
68
37
bool disabled; /* smmu is disabled */
69
static void imx_eth_update(IMXFECState *s)
38
bool bypassed; /* translation is bypassed */
70
{
39
bool aborted; /* translation is aborted */
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
40
+ bool record_faults; /* record fault events */
72
+ /*
41
uint64_t ttb; /* TT base address */
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
42
uint8_t oas; /* output address width */
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
43
uint8_t tbi; /* Top Byte Ignore */
75
+ * and older) since Linux associated both interrupt lines with Ethernet
44
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
76
+ * MAC interrupts. Specifically,
45
index XXXXXXX..XXXXXXX 100644
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
46
--- a/hw/arm/smmuv3.c
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
47
+++ b/hw/arm/smmuv3.c
79
+ * with swapped interrupt assignments.
48
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
49
trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had);
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
50
}
82
+ * work, though that is accidental.
51
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
52
- event->record_trans_faults = CD_R(cd);
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
53
+ cfg->record_faults = CD_R(cd);
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
54
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
55
return 0;
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
56
88
+ * Linux instead received MAC interrupts on the timer interrupt.
57
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
58
90
+ * albeit accidentally, but qemu versions with the correct interrupt
59
tt = select_tt(cfg, addr);
91
+ * assignment fail.
60
if (!tt) {
92
+ *
61
- if (event.record_trans_faults) {
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
62
+ if (cfg->record_faults) {
94
+ * interrrupts on both interrupt lines. This should be changed if and when
63
event.type = SMMU_EVT_F_TRANSLATION;
95
+ * qemu supports IOMUX.
64
event.u.f_translation.addr = addr;
96
+ */
65
event.u.f_translation.rnw = flag & 0x1;
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
66
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
67
if (cached_entry) {
99
qemu_set_irq(s->irq[1], 1);
68
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
100
} else {
69
status = SMMU_TRANS_ERROR;
101
qemu_set_irq(s->irq[1], 0);
70
- if (event.record_trans_faults) {
71
+ if (cfg->record_faults) {
72
event.type = SMMU_EVT_F_PERMISSION;
73
event.u.f_permission.addr = addr;
74
event.u.f_permission.rnw = flag & 0x1;
75
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
76
event.u.f_walk_eabt.addr2 = ptw_info.addr;
77
break;
78
case SMMU_PTW_ERR_TRANSLATION:
79
- if (event.record_trans_faults) {
80
+ if (cfg->record_faults) {
81
event.type = SMMU_EVT_F_TRANSLATION;
82
event.u.f_translation.addr = addr;
83
event.u.f_translation.rnw = flag & 0x1;
84
}
85
break;
86
case SMMU_PTW_ERR_ADDR_SIZE:
87
- if (event.record_trans_faults) {
88
+ if (cfg->record_faults) {
89
event.type = SMMU_EVT_F_ADDR_SIZE;
90
event.u.f_addr_size.addr = addr;
91
event.u.f_addr_size.rnw = flag & 0x1;
92
}
93
break;
94
case SMMU_PTW_ERR_ACCESS:
95
- if (event.record_trans_faults) {
96
+ if (cfg->record_faults) {
97
event.type = SMMU_EVT_F_ACCESS;
98
event.u.f_access.addr = addr;
99
event.u.f_access.rnw = flag & 0x1;
100
}
101
break;
102
case SMMU_PTW_ERR_PERMISSION:
103
- if (event.record_trans_faults) {
104
+ if (cfg->record_faults) {
105
event.type = SMMU_EVT_F_PERMISSION;
106
event.u.f_permission.addr = addr;
107
event.u.f_permission.rnw = flag & 0x1;
102
--
108
--
103
2.16.2
109
2.25.1
104
105
diff view generated by jsdifflib
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
3
but the BCM2386State struct only defines the parent_obj field
4
as DeviceState. This would have caused problems if anything
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
8
provides.
9
2
3
Make the translation error message prettier by adding a missing space
4
before the parenthesis.
5
6
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20220427111543.124620-2-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
14
---
11
---
15
hw/arm/bcm2836.c | 2 +-
12
hw/arm/smmuv3.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
17
14
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
15
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
17
--- a/hw/arm/smmuv3.c
21
+++ b/hw/arm/bcm2836.c
18
+++ b/hw/arm/smmuv3.c
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
19
@@ -XXX,XX +XXX,XX @@ epilogue:
23
20
break;
24
static const TypeInfo bcm2836_type_info = {
21
case SMMU_TRANS_ERROR:
25
.name = TYPE_BCM2836,
22
qemu_log_mask(LOG_GUEST_ERROR,
26
- .parent = TYPE_SYS_BUS_DEVICE,
23
- "%s translation failed for iova=0x%"PRIx64"(%s)\n",
27
+ .parent = TYPE_DEVICE,
24
+ "%s translation failed for iova=0x%"PRIx64" (%s)\n",
28
.instance_size = sizeof(BCM2836State),
25
mr->parent_obj.name, addr, smmu_event_string(event.type));
29
.instance_init = bcm2836_init,
26
smmuv3_record_event(s, &event);
30
.class_init = bcm2836_class_init,
27
break;
31
--
28
--
32
2.16.2
29
2.25.1
33
34
diff view generated by jsdifflib
1
If we're directly booting a Linux kernel and the CPU supports both
1
The Arm FEAT_TTL architectural feature allows the guest to provide an
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
2
optional hint in an AArch64 TLB invalidate operation about which
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
3
translation table level holds the leaf entry for the address being
4
instruction is enabled rather than UNDEFing. Otherwise at least some
4
invalidated. QEMU's TLB implementation doesn't need that hint, and
5
kernels will panic when trying to initialize KVM in the guest.
5
we correctly ignore the (previously RES0) bits in TLB invalidate
6
operation values that are now used for the TTL field. So we can
7
simply advertise support for it in our 'max' CPU.
6
8
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
9
---
12
---
10
hw/arm/boot.c | 5 +++++
13
docs/system/arm/emulation.rst | 1 +
11
1 file changed, 5 insertions(+)
14
target/arm/cpu64.c | 1 +
15
2 files changed, 2 insertions(+)
12
16
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
19
--- a/docs/system/arm/emulation.rst
16
+++ b/hw/arm/boot.c
20
+++ b/docs/system/arm/emulation.rst
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
assert(!info->secure_board_setup);
22
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
19
}
23
- FEAT_TLBIRANGE (TLB invalidate range instructions)
20
24
- FEAT_TTCNP (Translation table Common not private translations)
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
25
+- FEAT_TTL (Translation Table Level)
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
26
- FEAT_TTST (Small translation tables)
23
+ env->cp15.scr_el3 |= SCR_HCE;
27
- FEAT_UAO (Unprivileged Access Override control)
24
+ }
28
- FEAT_VHE (Virtualization Host Extensions)
25
+
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
/* Set to non-secure if not a secure boot */
30
index XXXXXXX..XXXXXXX 100644
27
if (!info->secure_boot &&
31
--- a/target/arm/cpu64.c
28
(cs != first_cpu || !info->secure_board_setup)) {
32
+++ b/target/arm/cpu64.c
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
34
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
35
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
37
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
38
cpu->isar.id_aa64mmfr2 = t;
39
40
t = cpu->isar.id_aa64zfr0;
29
--
41
--
30
2.16.2
42
2.25.1
31
32
diff view generated by jsdifflib
1
Add some assertions that if we're about to boot an AArch64 kernel,
1
The description in the Arm ARM of the requirements of FEAT_BBM is
2
the board code has not mistakenly set either secure_boot or
2
admirably clear on the guarantees it provides software, but slightly
3
secure_board_setup. It doesn't make sense to set secure_boot,
3
more obscure on what that means for implementations. The description
4
because all AArch64 kernels must be booted in non-secure mode.
4
of the equivalent SMMU feature in the SMMU specification (IHI0070D.b
5
section 3.21.1) is perhaps a bit more detailed and includes some
6
example valid implementation choices. (The SMMU version of this
7
feature is slightly tighter than the CPU version: the CPU is permitted
8
to raise TLB Conflict aborts in some situations that the SMMU may
9
not. This doesn't matter for QEMU because we don't want to do TLB
10
Conflict aborts anyway.)
5
11
6
It might in theory make sense to set secure_board_setup, but
12
The informal summary of FEAT_BBM is that it is about permitting an OS
7
we don't currently support that, because only the AArch32
13
to switch a range of memory between "covered by a huge page" and
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
14
"covered by a sequence of normal pages" without having to engage in
9
Since we don't have a current need for this functionality, just
15
the 'break-before-make' dance that has traditionally been
10
assert that we don't try to use it. If it's needed we'll add
16
necessary. The 'break-before-make' sequence is:
11
it later.
17
18
* replace the old translation table entry with an invalid entry
19
* execute a DSB insn
20
* execute a broadcast TLB invalidate insn
21
* execute a DSB insn
22
* write the new translation table entry
23
* execute a DSB insn
24
25
The point of this is to ensure that no TLB can simultaneously contain
26
TLB entries for the old and the new entry, which would traditionally
27
be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault
28
or to use a random mishmash of values from the old and the new
29
entry). FEAT_BBM level 2 says "for the specific case where the only
30
thing that changed is the size of the block, the TLB is guaranteed
31
not to do weird things even if there are multiple entries for an
32
address", which means that software can now do:
33
34
* replace old translation table entry with new entry
35
* DSB
36
* broadcast TLB invalidate
37
* DSB
38
39
As the SMMU spec notes, valid ways to do this include:
40
41
* if there are multiple entries in the TLB for an address,
42
choose one of them and use it, ignoring the others
43
* if there are multiple entries in the TLB for an address,
44
throw them all out and do a page table walk to get a new one
45
46
QEMU's page table walk implementation for Arm CPUs already meets the
47
requirements for FEAT_BBM level 2. When we cache an entry in our TCG
48
TLB, we do so only for the specific (non-huge) page that the address
49
is in, and there is no way for the TLB data structure to ever have
50
more than one TLB entry for that page. (We handle huge pages only in
51
that we track what part of the address space is covered by huge pages
52
so that a TLB invalidate operation for an address in a huge page
53
results in an invalidation of the whole TLB.) We ignore the Contiguous
54
bit in page table entries, so we don't have to do anything for the
55
parts of FEAT_BBM that deal with changis to the Contiguous bit.
56
57
FEAT_BBM level 2 also requires that the nT bit in block descriptors
58
must be ignored; since commit 39a1fd25287f5dece5 we do this.
59
60
It's therefore safe for QEMU to advertise FEAT_BBM level 2 by
61
setting ID_AA64MMFR2_EL1.BBM to 2.
12
62
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
63
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
64
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
65
Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org
16
---
66
---
17
hw/arm/boot.c | 7 +++++++
67
docs/system/arm/emulation.rst | 1 +
18
1 file changed, 7 insertions(+)
68
target/arm/cpu64.c | 1 +
69
2 files changed, 2 insertions(+)
19
70
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
71
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
72
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
73
--- a/docs/system/arm/emulation.rst
23
+++ b/hw/arm/boot.c
74
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
75
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
} else {
76
- FEAT_AA32HPD (AArch32 hierarchical permission disables)
26
env->pstate = PSTATE_MODE_EL1h;
77
- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
27
}
78
- FEAT_AES (AESD and AESE instructions)
28
+ /* AArch64 kernels never boot in secure mode */
79
+- FEAT_BBM at level 2 (Translation table break-before-make levels)
29
+ assert(!info->secure_boot);
80
- FEAT_BF16 (AArch64 BFloat16 instructions)
30
+ /* This hook is only supported for AArch32 currently:
81
- FEAT_BTI (Branch Target Identification)
31
+ * bootloader_aarch64[] will not call the hook, and
82
- FEAT_DIT (Data Independent Timing instructions)
32
+ * the code above has already dropped us into EL2 or EL1.
83
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
33
+ */
84
index XXXXXXX..XXXXXXX 100644
34
+ assert(!info->secure_board_setup);
85
--- a/target/arm/cpu64.c
35
}
86
+++ b/target/arm/cpu64.c
36
87
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
37
/* Set to non-secure if not a secure boot */
88
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
89
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
90
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
91
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
92
cpu->isar.id_aa64mmfr2 = t;
93
94
t = cpu->isar.id_aa64zfr0;
38
--
95
--
39
2.16.2
96
2.25.1
40
41
diff view generated by jsdifflib
1
For the rpi1 and 2 we want to boot the Linux kernel via some
1
The Arm SMMUv3 includes an optional feature equivalent to the CPU
2
custom setup code that makes sure that the SMC instruction
2
FEAT_BBM, which permits an OS to switch a range of memory between
3
acts as a no-op, because it's used for cache maintenance.
3
"covered by a huge page" and "covered by a sequence of normal pages"
4
The rpi3 boots AArch64 kernels, which don't need SMC for
4
without having to engage in the traditional 'break-before-make'
5
cache maintenance and always expect to be booted non-secure.
5
dance. (This is particularly important for the SMMU, because devices
6
Don't fill in the aarch32-specific parts of the binfo struct.
6
performing I/O through an SMMU are less likely to be able to cope with
7
the window in the sequence where an access results in a translation
8
fault.) The SMMU spec explicitly notes that one of the valid ways to
9
be a BBM level 2 compliant implementation is:
10
* if there are multiple entries in the TLB for an address,
11
choose one of them and use it, ignoring the others
12
13
Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple
14
TLB entries for an address, because the translation table level is
15
part of the SMMUIOTLBKey, and so our IOTLB hashtable can include
16
entries for the same address where the leaf was at different levels
17
(i.e. both hugepage and normal page). Our TLB lookup implementation in
18
smmu_iotlb_lookup() will always find the entry with the lowest level
19
(i.e. it prefers the hugepage over the normal page) and ignore any
20
others. TLB invalidation correctly removes all TLB entries matching
21
the specified address or address range (unless the guest specifies the
22
leaf level explicitly, in which case it gets what it asked for). So we
23
can validly advertise support for BBML level 2.
24
25
Note that we still can't yet advertise ourselves as an SMMU v3.2,
26
because v3.2 requires support for the S2FWB feature, which we don't
27
yet implement.
7
28
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
31
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
32
Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
12
---
33
---
13
hw/arm/raspi.c | 17 +++++++++++++----
34
hw/arm/smmuv3-internal.h | 1 +
14
1 file changed, 13 insertions(+), 4 deletions(-)
35
hw/arm/smmuv3.c | 1 +
36
2 files changed, 2 insertions(+)
15
37
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
38
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
17
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
40
--- a/hw/arm/smmuv3-internal.h
19
+++ b/hw/arm/raspi.c
41
+++ b/hw/arm/smmuv3-internal.h
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
42
@@ -XXX,XX +XXX,XX @@ REG32(IDR2, 0x8)
21
binfo.board_id = raspi_boardid[version];
43
REG32(IDR3, 0xc)
22
binfo.ram_size = ram_size;
44
FIELD(IDR3, HAD, 2, 1);
23
binfo.nb_cpus = smp_cpus;
45
FIELD(IDR3, RIL, 10, 1);
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
46
+ FIELD(IDR3, BBML, 11, 2);
25
- binfo.write_board_setup = write_board_setup;
47
REG32(IDR4, 0x10)
26
- binfo.secure_board_setup = true;
48
REG32(IDR5, 0x14)
27
- binfo.secure_boot = true;
49
FIELD(IDR5, OAS, 0, 3);
28
+
50
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
29
+ if (version <= 2) {
51
index XXXXXXX..XXXXXXX 100644
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
52
--- a/hw/arm/smmuv3.c
31
+ * mode before booting a kernel (to set up the SMC vectors so
53
+++ b/hw/arm/smmuv3.c
32
+ * that we get a no-op SMC; this is used by Linux to call the
54
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
33
+ * firmware for some cache maintenance operations.
55
34
+ * The rpi3 doesn't need this.
56
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
35
+ */
57
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
58
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
37
+ binfo.write_board_setup = write_board_setup;
59
38
+ binfo.secure_board_setup = true;
60
/* 4K, 16K and 64K granule support */
39
+ binfo.secure_boot = true;
61
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
40
+ }
41
42
/* Pi2 and Pi3 requires SMP setup */
43
if (version >= 2) {
44
--
62
--
45
2.16.2
63
2.25.1
46
47
diff view generated by jsdifflib