The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913

for you to fetch changes up to 9a2b2ecf4d25a3943918c95d2db4508b304161b5:

hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 17:09:28 +0100)

* mark MPS2/MPS3 board-internal i2c buses as 'full' so that command

line user-created devices are not plugged into them

* Take an exception if PSTATE.IL is set

* Support an emulated ITS in the virt board

* Add support for kudo-bmc board

* Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM

* cadence_uart: Fix clock handling issues that prevented

u-boot from running

Bin Meng (6):

hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase

hw/char: cadence_uart: Disable transmit when input clock is disabled

hw/char: cadence_uart: Move clock/reset check to uart_can_receive()

hw/char: cadence_uart: Convert to memop_with_attrs() ops

hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}()

hw/char: cadence_uart: Log a guest error when device is unclocked or in reset

Chris Rauer (1):

hw/arm: Add support for kudo-bmc board.

Marc Zyngier (1):

hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM

Peter Maydell (5):

target/arm: Take an exception if PSTATE.IL is set

qdev: Support marking individual buses as 'full'

hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn

hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'

hw/arm/mps2.c: Mark internal-only I2C buses as 'full'

Richard Henderson (1):

target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn

From: Bin Meng <bmeng.cn@gmail.com>

As of today, when booting upstream U-Boot for Xilinx Zynq, the UART

does not receive anything. Debugging shows that the UART input clock

frequency is zero which prevents the UART from receiving anything as

per the logic in uart_receive().

hw/misc/zynq_slcr.c | 31 ++++++++++++++++++-------------

1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c

--- a/hw/misc/zynq_slcr.c

+++ b/hw/misc/zynq_slcr.c

@@ -XXX,XX +XXX,XX @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],

zynq_slcr_compute_clock((plls), (state)->regs[reg], \

reg ## _ ## enable_field ## _SHIFT)

+static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk)

+{

+ uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);

+ uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);

+ uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);

+ uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};

+ /* compute uartX reference clocks */

+ clock_set(s->uart0_ref_clk,

+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));

+ clock_set(s->uart1_ref_clk,

+ ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));

+}

/**

* Compute and set the ouputs clocks periods.

* But do not propagate them further. Connected clocks

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s)

ps_clk = 0;

}

- uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);

- uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);

- uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);

-

- uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};

-

- /* compute uartX reference clocks */

- clock_set(s->uart0_ref_clk,

- ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));

- clock_set(s->uart1_ref_clk,

- ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));

+ zynq_slcr_compute_clocks_internal(s, ps_clk);

/**

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset_hold(Object *obj)

ZynqSLCRState *s = ZYNQ_SLCR(obj);

/* will disable all output clocks */

- zynq_slcr_compute_clocks(s);

+ zynq_slcr_compute_clocks_internal(s, 0);

zynq_slcr_propagate_clocks(s);

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset_exit(Object *obj)

ZynqSLCRState *s = ZYNQ_SLCR(obj);

/* will compute output clocks according to ps_clk and registers */

- zynq_slcr_compute_clocks(s);

+ zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk));

zynq_slcr_propagate_clocks(s);

}

2.20.1

From: Bin Meng <bmeng.cn@gmail.com>

This converts uart_read() and uart_write() to memop_with_attrs() ops.

hw/char/cadence_uart.c | 26 +++++++++++++++-----------

1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c

--- a/hw/char/cadence_uart.c

+++ b/hw/char/cadence_uart.c

@@ -XXX,XX +XXX,XX @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)

uart_update_status(s);

}

-static void uart_write(void *opaque, hwaddr offset,

- uint64_t value, unsigned size)

+static MemTxResult uart_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size, MemTxAttrs attrs)

CadenceUARTState *s = opaque;

DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);

offset >>= 2;

if (offset >= CADENCE_UART_R_MAX) {

- return;

+ return MEMTX_DECODE_ERROR;

}

switch (offset) {

case R_IER: /* ier (wts imr) */

@@ -XXX,XX +XXX,XX @@ static void uart_write(void *opaque, hwaddr offset,

break;

}

uart_update_status(s);

+

+ return MEMTX_OK;

}

-static uint64_t uart_read(void *opaque, hwaddr offset,

- unsigned size)

+static MemTxResult uart_read(void *opaque, hwaddr offset,

+ uint64_t *value, unsigned size, MemTxAttrs attrs)

CadenceUARTState *s = opaque;

uint32_t c = 0;

offset >>= 2;

if (offset >= CADENCE_UART_R_MAX) {

- c = 0;

- } else if (offset == R_TX_RX) {

+ return MEMTX_DECODE_ERROR;

+ }

+ if (offset == R_TX_RX) {

uart_read_rx_fifo(s, &c);

} else {

- c = s->r[offset];

+ c = s->r[offset];

}

DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);

- return c;

+ *value = c;

+ return MEMTX_OK;

static const MemoryRegionOps uart_ops = {

- .read = uart_read,

- .write = uart_write,

+ .read_with_attrs = uart_read,

+ .write_with_attrs = uart_write,

.endianness = DEVICE_NATIVE_ENDIAN,

2.20.1

From: Chris Rauer <crauer@google.com>

docs/system/arm/nuvoton.rst | 1 +

hw/arm/npcm7xx_boards.c | 34 ++++++++++++++++++++++++++++++++++

2 files changed, 35 insertions(+)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst

--- a/docs/system/arm/nuvoton.rst

+++ b/docs/system/arm/nuvoton.rst

@@ -XXX,XX +XXX,XX @@ Hyperscale applications. The following machines are based on this chip :

- ``quanta-gbs-bmc`` Quanta GBS server BMC

- ``quanta-gsj`` Quanta GSJ server BMC

+- ``kudo-bmc`` Fii USA Kudo server BMC

There are also two more SoCs, NPCM710 and NPCM705, which are single-core

variants of NPCM750 and NPCM730, respectively. These are currently not

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/npcm7xx_boards.c

+++ b/hw/arm/npcm7xx_boards.c

#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7

#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff

#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff

+#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff

static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";

@@ -XXX,XX +XXX,XX @@ static void quanta_gbs_init(MachineState *machine)

npcm7xx_load_kernel(machine, soc);

}

+static void kudo_bmc_init(MachineState *machine)

+{

+ NPCM7xxState *soc;

+

+ soc = npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS);

+ npcm7xx_connect_dram(soc, machine->ram);

+ qdev_realize(DEVICE(soc), NULL, &error_fatal);

+

+ npcm7xx_load_bootrom(machine, soc);

+ npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",

+ drive_get(IF_MTD, 0, 0));

+ npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",

+ drive_get(IF_MTD, 3, 0));

+

+ npcm7xx_load_kernel(machine, soc);

+}

+

static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)

{

NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));

@@ -XXX,XX +XXX,XX @@ static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data)

mc->default_ram_size = 1 * GiB;

}

+static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data)

+{

+ NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);

+ MachineClass *mc = MACHINE_CLASS(oc);

+

+ npcm7xx_set_soc_type(nmc, TYPE_NPCM730);

+

+ mc->desc = "Kudo BMC (Cortex-A9)";

+ mc->init = kudo_bmc_init;

+ mc->default_ram_size = 1 * GiB;

+};

+

static const TypeInfo npcm7xx_machine_types[] = {

.name = TYPE_NPCM7XX_MACHINE,

@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_machine_types[] = {

.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),

.parent = TYPE_NPCM7XX_MACHINE,

.class_init = gbs_bmc_machine_class_init,

+ }, {

+ .name = MACHINE_TYPE_NAME("kudo-bmc"),

+ .parent = TYPE_NPCM7XX_MACHINE,

+ .class_init = kudo_bmc_machine_class_init,

2.20.1