Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[PULL 00/17] target-arm queue
-Arm patch queue -- these are all bug fix patches but we might
+Arm changes for before softfreeze: mostly my PL061/GPIO patches,
-as well put them in to rc0...
+but also a new M-profile board and various other things.
 thanks
 -- PMM
-The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
+The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
+  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709
-for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
+for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:
-  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
+  hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * fsl-imx6: Fix incorrect Ethernet interrupt defines
+ * New machine type: stm32vldiscovery
- * dump: Update correct kdump phys_base field for AArch64
+ * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
- * char: i.MX: Add support for "TX complete" interrupt
+ * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
- * bcm2836/raspi: Fix various bugs resulting in panics trying
+ * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
-   to boot a Debian Linux kernel on raspi3
+ * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  * hw/intc: Improve formatting of MEMTX_ERROR guest error message
 ----------------------------------------------------------------
-Andrey Smirnov (2):
+Alexandre Iooss (4):
-      char: i.MX: Simplify imx_update()
+      stm32f100: Add the stm32f100 SoC
-      char: i.MX: Add support for "TX complete" interrupt
+      stm32vldiscovery: Add the STM32VLDISCOVERY Machine
       docs/system: arm: Add stm32 boards description
       tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
-Guenter Roeck (1):
+Peter Maydell (10):
-      fsl-imx6: Swap Ethernet interrupt defines
+      hw/gpio/pl061: Convert DPRINTF to tracepoints
       hw/gpio/pl061: Clean up read/write offset handling logic
       hw/gpio/pl061: Add tracepoints for register read and write
       hw/gpio/pl061: Document the interface of this device
       hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
       hw/gpio/pl061: Make pullup/pulldown of outputs configurable
       hw/arm/virt: Make PL061 GPIO lines pulled low, not high
       hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
       hw/gpio/pl061: Document a shortcoming in our implementation
       hw/arm/stellaris: Expand comment about handling of OLED chipselect
-Peter Maydell (9):
+Rebecca Cran (1):
-      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+      hw/intc: Improve formatting of MEMTX_ERROR guest error message
       hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
       hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
       hw/arm/bcm2386: Fix parent type of bcm2386
       hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
       hw/arm/bcm2836: Create proper bcm2837 device
       hw/arm/bcm2836: Use correct affinity values for BCM2837
       hw/arm/bcm2836: Hardcode correct CPU type
       hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
-Wei Huang (1):
+Ricardo Koller (1):
-      dump: Update correct kdump phys_base field for AArch64
+      hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
- include/hw/arm/bcm2836.h     | 31 +++++++++++++---
+hnick@vmware.com (1):
- include/hw/arm/fsl-imx6.h    |  4 +-
+      target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  include/hw/char/imx_serial.h |  3 ++
  dump.c                       | 14 +++++--
  hw/arm/bcm2836.c             | 87 +++++++++++++++++++++++++++++++-------------
  hw/arm/boot.c                | 12 ++++++
  hw/arm/raspi.c               | 77 +++++++++++++++++++++++++++++++--------
  hw/char/imx_serial.c         | 44 ++++++++++++++++------
  hw/net/imx_fec.c             | 28 +++++++++++++-
 files changed, 237 insertions(+), 63 deletions(-)
+ docs/system/arm/stm32.rst               |  66 +++++++
+ docs/system/target-arm.rst              |   1 +
+ default-configs/devices/arm-softmmu.mak |   1 +
+ include/hw/arm/stm32f100_soc.h          |  57 ++++++
+ hw/arm/stellaris.c                      |  56 +++++-
+ hw/arm/stm32f100_soc.c                  | 182 +++++++++++++++++
+ hw/arm/stm32vldiscovery.c               |  66 +++++++
+ hw/arm/virt.c                           |   3 +
+ hw/gpio/pl061.c                         | 341 +++++++++++++++++++++++++-------
+ hw/intc/arm_gicv3_cpuif.c               |   4 +-
+ hw/intc/arm_gicv3_redist.c              |   4 +-
+ target/arm/helper.c                     |  16 +-
+ tests/qtest/boot-serial-test.c          |  37 ++++
+ MAINTAINERS                             |  13 ++
+ hw/arm/Kconfig                          |  10 +
+ hw/arm/meson.build                      |   2 +
+ hw/gpio/trace-events                    |   9 +
+files changed, 790 insertions(+), 78 deletions(-)
+ create mode 100644 docs/system/arm/stm32.rst
+ create mode 100644 include/hw/arm/stm32f100_soc.h
+ create mode 100644 hw/arm/stm32f100_soc.c
+ create mode 100644 hw/arm/stm32vldiscovery.c

-New patch
+[PULL 01/17] stm32f100: Add the stm32f100 SoC
+From: Alexandre Iooss <erdnaxe@crans.org>
 This SoC is similar to stm32f205 SoC.
 This will be used by the STM32VLDISCOVERY to create a machine.
 Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/stm32f100_soc.h |  57 +++++++++++
  hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
  MAINTAINERS                    |   6 ++
  hw/arm/Kconfig                 |   6 ++
  hw/arm/meson.build             |   1 +
 files changed, 252 insertions(+)
  create mode 100644 include/hw/arm/stm32f100_soc.h
  create mode 100644 hw/arm/stm32f100_soc.c
 diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/arm/stm32f100_soc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * STM32F100 SoC
 + *
 + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_ARM_STM32F100_SOC_H
 +#define HW_ARM_STM32F100_SOC_H
 +
 +#include "hw/char/stm32f2xx_usart.h"
 +#include "hw/ssi/stm32f2xx_spi.h"
 +#include "hw/arm/armv7m.h"
 +#include "qom/object.h"
 +
 +#define TYPE_STM32F100_SOC "stm32f100-soc"
 +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
 +
 +#define STM_NUM_USARTS 3
 +#define STM_NUM_SPIS 2
 +
 +#define FLASH_BASE_ADDRESS 0x08000000
 +#define FLASH_SIZE (128 * 1024)
 +#define SRAM_BASE_ADDRESS 0x20000000
 +#define SRAM_SIZE (8 * 1024)
 +
 +struct STM32F100State {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +
 +    /*< public >*/
 +    char *cpu_type;
 +
 +    ARMv7MState armv7m;
 +
 +    STM32F2XXUsartState usart[STM_NUM_USARTS];
 +    STM32F2XXSPIState spi[STM_NUM_SPIS];
 +};
 +
 +#endif
 diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/stm32f100_soc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * STM32F100 SoC
 + *
 + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
 + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "qemu/module.h"
 +#include "hw/arm/boot.h"
 +#include "exec/address-spaces.h"
 +#include "hw/arm/stm32f100_soc.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/misc/unimp.h"
 +#include "sysemu/sysemu.h"
 +
 +/* stm32f100_soc implementation is derived from stm32f205_soc */
 +
 +static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
 +    0x40004800 };
 +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
 +
 +static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
 +static const int spi_irq[STM_NUM_SPIS] = {35, 36};
 +
 +static void stm32f100_soc_initfn(Object *obj)
 +{
 +    STM32F100State *s = STM32F100_SOC(obj);
 +    int i;
 +
 +    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
 +
 +    for (i = 0; i < STM_NUM_USARTS; i++) {
 +        object_initialize_child(obj, "usart[*]", &s->usart[i],
 +                                TYPE_STM32F2XX_USART);
 +    }
 +
 +    for (i = 0; i < STM_NUM_SPIS; i++) {
 +        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
 +    }
 +}
 +
 +static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
 +{
 +    STM32F100State *s = STM32F100_SOC(dev_soc);
 +    DeviceState *dev, *armv7m;
 +    SysBusDevice *busdev;
 +    int i;
 +
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *sram = g_new(MemoryRegion, 1);
 +    MemoryRegion *flash = g_new(MemoryRegion, 1);
 +    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
 +
 +    /*
 +     * Init flash region
 +     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
 +     */
 +    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
 +                           FLASH_SIZE, &error_fatal);
 +    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
 +                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
 +    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
 +    memory_region_add_subregion(system_memory, 0, flash_alias);
 +
 +    /* Init SRAM region */
 +    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
 +                           &error_fatal);
 +    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 +
 +    /* Init ARMv7m */
 +    armv7m = DEVICE(&s->armv7m);
 +    qdev_prop_set_uint32(armv7m, "num-irq", 61);
 +    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 +    qdev_prop_set_bit(armv7m, "enable-bitband", true);
 +    object_property_set_link(OBJECT(&s->armv7m), "memory",
 +                             OBJECT(get_system_memory()), &error_abort);
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
 +        return;
 +    }
 +
 +    /* Attach UART (uses USART registers) and USART controllers */
 +    for (i = 0; i < STM_NUM_USARTS; i++) {
 +        dev = DEVICE(&(s->usart[i]));
 +        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
 +            return;
 +        }
 +        busdev = SYS_BUS_DEVICE(dev);
 +        sysbus_mmio_map(busdev, 0, usart_addr[i]);
 +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
 +    }
 +
 +    /* SPI 1 and 2 */
 +    for (i = 0; i < STM_NUM_SPIS; i++) {
 +        dev = DEVICE(&(s->spi[i]));
 +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 +            return;
 +        }
 +        busdev = SYS_BUS_DEVICE(dev);
 +        sysbus_mmio_map(busdev, 0, spi_addr[i]);
 +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
 +    }
 +
 +    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
 +    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
 +    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
 +    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
 +    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
 +    create_unimplemented_device("RTC",       0x40002800, 0x400);
 +    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
 +    create_unimplemented_device("IWDG",      0x40003000, 0x400);
 +    create_unimplemented_device("I2C1",      0x40005400, 0x400);
 +    create_unimplemented_device("I2C2",      0x40005800, 0x400);
 +    create_unimplemented_device("BKP",       0x40006C00, 0x400);
 +    create_unimplemented_device("PWR",       0x40007000, 0x400);
 +    create_unimplemented_device("DAC",       0x40007400, 0x400);
 +    create_unimplemented_device("CEC",       0x40007800, 0x400);
 +    create_unimplemented_device("AFIO",      0x40010000, 0x400);
 +    create_unimplemented_device("EXTI",      0x40010400, 0x400);
 +    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
 +    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
 +    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
 +    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
 +    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
 +    create_unimplemented_device("ADC1",      0x40012400, 0x400);
 +    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
 +    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
 +    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
 +    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
 +    create_unimplemented_device("DMA",       0x40020000, 0x400);
 +    create_unimplemented_device("RCC",       0x40021000, 0x400);
 +    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
 +    create_unimplemented_device("CRC",       0x40023000, 0x400);
 +}
 +
 +static Property stm32f100_soc_properties[] = {
 +    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = stm32f100_soc_realize;
 +    device_class_set_props(dc, stm32f100_soc_properties);
 +}
 +
 +static const TypeInfo stm32f100_soc_info = {
 +    .name          = TYPE_STM32F100_SOC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(STM32F100State),
 +    .instance_init = stm32f100_soc_initfn,
 +    .class_init    = stm32f100_soc_class_init,
 +};
 +
 +static void stm32f100_soc_types(void)
 +{
 +    type_register_static(&stm32f100_soc_info);
 +}
 +
 +type_init(stm32f100_soc_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/arm/virt-acpi-build.c
 +STM32F100
 +M: Alexandre Iooss <erdnaxe@crans.org>
 +L: qemu-arm@nongnu.org
 +S: Maintained
 +F: hw/arm/stm32f100_soc.c
 +
  STM32F205
  M: Alistair Francis <alistair@alistair23.me>
  M: Peter Maydell <peter.maydell@linaro.org>
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config RASPI
      select SDHCI
      select USB_DWC2
 +config STM32F100_SOC
 +    bool
 +    select ARM_V7M
 +    select STM32F2XX_USART
 +    select STM32F2XX_SPI
 +
  config STM32F205_SOC
      bool
      select ARM_V7M
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
  arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
  arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
  arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
 +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
  arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
  arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
  arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 --
 .20.1

-New patch
+[PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine
+From: Alexandre Iooss <erdnaxe@crans.org>
+This is a Cortex-M3 based machine. Information can be found at:
+https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ default-configs/devices/arm-softmmu.mak |  1 +
+ hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
+ MAINTAINERS                             |  6 +++
+ hw/arm/Kconfig                          |  4 ++
+ hw/arm/meson.build                      |  1 +
+files changed, 78 insertions(+)
+ create mode 100644 hw/arm/stm32vldiscovery.c
+diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/default-configs/devices/arm-softmmu.mak
++++ b/default-configs/devices/arm-softmmu.mak
+@@ -XXX,XX +XXX,XX @@ CONFIG_CHEETAH=y
+ CONFIG_SX1=y
+ CONFIG_NSERIES=y
+ CONFIG_STELLARIS=y
++CONFIG_STM32VLDISCOVERY=y
+ CONFIG_REALVIEW=y
+ CONFIG_VERSATILE=y
+ CONFIG_VEXPRESS=y
+diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/arm/stm32vldiscovery.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * ST STM32VLDISCOVERY machine
++ *
++ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * of this software and associated documentation files (the "Software"), to deal
++ * in the Software without restriction, including without limitation the rights
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
++ * copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
++ * THE SOFTWARE.
++ */
++
++#include "qemu/osdep.h"
++#include "qapi/error.h"
++#include "hw/boards.h"
++#include "hw/qdev-properties.h"
++#include "qemu/error-report.h"
++#include "hw/arm/stm32f100_soc.h"
++#include "hw/arm/boot.h"
++
++/* stm32vldiscovery implementation is derived from netduinoplus2 */
++
++/* Main SYSCLK frequency in Hz (24MHz) */
++#define SYSCLK_FRQ 24000000ULL
++
++static void stm32vldiscovery_init(MachineState *machine)
++{
++    DeviceState *dev;
++
++    /*
++     * TODO: ideally we would model the SoC RCC and let it handle
++     * system_clock_scale, including its ability to define different
++     * possible SYSCLK sources.
++     */
++    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
++
++    dev = qdev_new(TYPE_STM32F100_SOC);
++    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++
++    armv7m_load_kernel(ARM_CPU(first_cpu),
++                       machine->kernel_filename,
++                       FLASH_SIZE);
++}
++
++static void stm32vldiscovery_machine_init(MachineClass *mc)
++{
++    mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
++    mc->init = stm32vldiscovery_init;
++}
++
++DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
++
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: hw/*/stellaris*
+ F: include/hw/input/gamepad.h
+ F: docs/system/arm/stellaris.rst
++STM32VLDISCOVERY
++M: Alexandre Iooss <erdnaxe@crans.org>
++L: qemu-arm@nongnu.org
++S: Maintained
++F: hw/arm/stm32vldiscovery.c
++
+ Versatile Express
+ M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config STELLARIS
+     select STELLARIS_ENET # ethernet
+     select UNIMP
++config STM32VLDISCOVERY
++    bool
++    select STM32F100_SOC
++
+ config STRONGARM
+     bool
+     select PXA2XX
+diff --git a/hw/arm/meson.build b/hw/arm/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/meson.build
++++ b/hw/arm/meson.build
+@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
+ arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
+ arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
+ arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
++arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
+ arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
+ arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
+ arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
+--
+.20.1

-New patch
+[PULL 03/17] docs/system: arm: Add stm32 boards description
+From: Alexandre Iooss <erdnaxe@crans.org>
+This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/stm32.rst  | 66 ++++++++++++++++++++++++++++++++++++++
+ docs/system/target-arm.rst |  1 +
+ MAINTAINERS                |  1 +
+files changed, 68 insertions(+)
+ create mode 100644 docs/system/arm/stm32.rst
+diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/docs/system/arm/stm32.rst
+@@ -XXX,XX +XXX,XX @@
++STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
++========================================================================================
++
++The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
++STMicroelectronics.
++
++.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
++
++The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
++based on this chip :
++
++- ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
++
++The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
++based on this chip :
++
++- ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller
++
++The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
++compatible with STM32F2 series. The following machines are based on this chip :
++
++- ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
++
++There are many other STM32 series that are currently not supported by QEMU.
++
++Supported devices
++-----------------
++
++ * ARM Cortex-M3, Cortex M4F
++ * Analog to Digital Converter (ADC)
++ * EXTI interrupt
++ * Serial ports (USART)
++ * SPI controller
++ * System configuration (SYSCFG)
++ * Timer controller (TIMER)
++
++Missing devices
++---------------
++
++ * Camera interface (DCMI)
++ * Controller Area Network (CAN)
++ * Cycle Redundancy Check (CRC) calculation unit
++ * Digital to Analog Converter (DAC)
++ * DMA controller
++ * Ethernet controller
++ * Flash Interface Unit
++ * GPIO controller
++ * I2C controller
++ * Inter-Integrated Sound (I2S) controller
++ * Power supply configuration (PWR)
++ * Random Number Generator (RNG)
++ * Real-Time Clock (RTC) controller
++ * Reset and Clock Controller (RCC)
++ * Secure Digital Input/Output (SDIO) interface
++ * USB OTG
++ * Watchdog controller (IWDG, WWDG)
++
++Boot options
++------------
++
++The STM32 machines can be started using the ``-kernel`` option to load a
++firmware. Example:
++
++.. code-block:: bash
++
++  $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin
+diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/target-arm.rst
++++ b/docs/system/target-arm.rst
+@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+    arm/collie
+    arm/sx1
+    arm/stellaris
++   arm/stm32
+    arm/virt
+    arm/xlnx-versal-virt
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ M: Alexandre Iooss <erdnaxe@crans.org>
+ L: qemu-arm@nongnu.org
+ S: Maintained
+ F: hw/arm/stm32vldiscovery.c
++F: docs/system/arm/stm32.rst
+ Versatile Express
+ M: Peter Maydell <peter.maydell@linaro.org>
+--
+.20.1

-[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
+[PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Alexandre Iooss <erdnaxe@crans.org>
-Code of imx_update() is slightly confusing since the "flags" variable
+New mini-kernel test for STM32VLDISCOVERY USART1.
 doesn't really corespond to anything in real hardware and server as a
 kitchensink accumulating events normally reported via USR1 and USR2
 registers.
-Change the code to explicitly evaluate state of interrupts reported
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
-via USR1 and USR2 against corresponding masking bits and use the to
+Acked-by: Thomas Huth <thuth@redhat.com>
-detemine if IRQ line should be asserted or not.
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
 NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
 reasons:
 . Emulation code implements a single character FIFO, so this flag
        will always be set since characters are trasmitted as a part of
        the code emulating "push" into the FIFO
 . imx_update() is really just a function doing ORing and maksing
        of reported events, so checking for UTS1_TXEMPTY should happen,
        if it's ever really needed should probably happen outside of
        it.
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/imx_serial.c | 24 ++++++++++++++++--------
+ tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
-file changed, 16 insertions(+), 8 deletions(-)
+file changed, 37 insertions(+)
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/tests/qtest/boot-serial-test.c
-+++ b/hw/char/imx_serial.c
++++ b/tests/qtest/boot-serial-test.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_nrf51[] = {
+x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
- static void imx_update(IMXSerialState *s)
+ };
- {
--    uint32_t flags;
++static const uint8_t kernel_stm32vldiscovery[] = {
-+    uint32_t usr1;
++    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
-+    uint32_t usr2;
++    0x1d, 0x00, 0x00, 0x00,                 /* Reset handler address */
-+    uint32_t mask;
++    0x00, 0x00, 0x00, 0x00,                 /* NMI */
++    0x00, 0x00, 0x00, 0x00,                 /* Hard fault */
--    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
++    0x00, 0x00, 0x00, 0x00,                 /* Memory management fault */
--    if (s->ucr1 & UCR1_TXMPTYEN) {
++    0x00, 0x00, 0x00, 0x00,                 /* Bus fault */
--        flags |= (s->uts1 & UTS1_TXEMPTY);
++    0x00, 0x00, 0x00, 0x00,                 /* Usage fault */
--    } else {
++    0x0b, 0x4b,                             /* ldr  r3, [pc, #44] Get RCC */
--        flags &= ~USR1_TRDY;
++    0x44, 0xf2, 0x04, 0x02,                 /* movw r2, #16388 */
--    }
++    0x1a, 0x60,                             /* str  r2, [r3] */
-+    /*
++    0x0a, 0x4b,                             /* ldr  r3, [pc, #40] Get GPIOA */
-+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
++    0x1a, 0x68,                             /* ldr  r2, [r3] */
-+     * UCR1, so we can get away with something as simple as the
++    0x22, 0xf0, 0xf0, 0x02,                 /* bic  r2, r2, #240 */
-+     * following:
++    0x1a, 0x60,                             /* str  r2, [r3] */
-+     */
++    0x1a, 0x68,                             /* ldr  r2, [r3] */
-+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
++    0x42, 0xf0, 0xb0, 0x02,                 /* orr  r2, r2, #176 */
-+    /*
++    0x1a, 0x60,                             /* str  r2, [r3] */
-+     * Bits that we want in USR2 are not as conveniently laid out,
++    0x07, 0x4b,                             /* ldr  r3, [pc, #26] Get BAUD */
-+     * unfortunately.
++    0x45, 0x22,                             /* movs r2, #69 */
-+     */
++    0x1a, 0x60,                             /* str  r2, [r3] */
-+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
++    0x06, 0x4b,                             /* ldr  r3, [pc, #24] Get ENABLE */
-+    usr2 = s->usr2 & mask;
++    0x42, 0xf2, 0x08, 0x02,                 /* movw r2, #8200 */
++    0x1a, 0x60,                             /* str  r2, [r3] */
--    qemu_set_irq(s->irq, !!flags);
++    0x05, 0x4b,                             /* ldr  r3, [pc, #20] Get TXD */
-+    qemu_set_irq(s->irq, usr1 || usr2);
++    0x54, 0x22,                             /* movs r2, 'T' */
- }
++    0x1a, 0x60,                             /* str  r2, [r3] */
++    0xfe, 0xe7,                             /* b    . */
- static void imx_serial_reset(IMXSerialState *s)
++    0x18, 0x10, 0x02, 0x40,                 /* 0x40021018 = RCC */
 +    0x04, 0x08, 0x01, 0x40,                 /* 0x40010804 = GPIOA */
 +    0x08, 0x38, 0x01, 0x40,                 /* 0x40013808 = USART1 BAUD */
 +    0x0c, 0x38, 0x01, 0x40,                 /* 0x4001380c = USART1 ENABLE */
 +    0x04, 0x38, 0x01, 0x40                  /* 0x40013804 = USART1 TXD */
 +};
 +
  typedef struct testdef {
      const char *arch;       /* Target architecture */
      const char *machine;    /* Name of the machine */
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
      { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
        kernel_aarch64 },
      { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
 +    { "arm", "stm32vldiscovery", "", "T",
 +      sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
      { NULL }
  };
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
+[PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Ricardo Koller <ricarkol@google.com>
-Add support for "TX complete"/TXDC interrupt generate by real HW since
+icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
-it is needed to support guests other than Linux.
+(like LPIs).  The issue is that these functions check against the number
 of implemented IRQs (QEMU's default is num_irq=288) which can be lower
 than the maximum virtual IRQ number (1020 - 1).  The consequence is that
 if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
 guest is unable to deactivate the resulting IRQ. Note that other
 functions that deal with large IRQ numbers, like icv_iar_read, check
 against 1020 and not against num_irq.
-Based on the patch by Bill Paul as found here:
+Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
-https://bugs.launchpad.net/qemu/+bug/1753314
+implemented IRQs.
-Cc: qemu-devel@nongnu.org
+Signed-off-by: Ricardo Koller <ricarkol@google.com>
-Cc: qemu-arm@nongnu.org
+Message-id: 20210702233701.3369-1-ricarkol@google.com
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Bill Paul <wpaul@windriver.com>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/char/imx_serial.h |  3 +++
+ hw/intc/arm_gicv3_cpuif.c | 4 ++--
- hw/char/imx_serial.c         | 20 +++++++++++++++++---
+file changed, 2 insertions(+), 2 deletions(-)
 files changed, 20 insertions(+), 3 deletions(-)
-diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/imx_serial.h
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/include/hw/char/imx_serial.h
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
- #define UCR2_RXEN       (1<<1)    /* Receiver enable */
- #define UCR2_SRST       (1<<0)    /* Reset complete */
+     trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
-+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+-    if (irq >= cs->gic->num_irq) {
-+
++    if (irq >= GICV3_MAXIRQ) {
- #define UTS1_TXEMPTY    (1<<6)
+         /* Also catches special interrupt numbers and LPIs */
- #define UTS1_RXEMPTY    (1<<5)
+         return;
- #define UTS1_TXFULL     (1<<4)
+     }
-@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
+@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     uint32_t ubmr;
+     trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
-     uint32_t ubrc;
+                                gicv3_redist_affid(cs), value);
-     uint32_t ucr3;
-+    uint32_t ucr4;
+-    if (irq >= cs->gic->num_irq) {
++    if (irq >= GICV3_MAXIRQ) {
-     qemu_irq irq;
+         /* Also catches special interrupt numbers and LPIs */
-     CharBackend chr;
+         return;
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+     }
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/imx_serial.c
 +++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
  static const VMStateDescription vmstate_imx_serial = {
      .name = TYPE_IMX_SERIAL,
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_INT32(readbuff, IMXSerialState),
          VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
          VMSTATE_UINT32(ubmr, IMXSerialState),
          VMSTATE_UINT32(ubrc, IMXSerialState),
          VMSTATE_UINT32(ucr3, IMXSerialState),
 +        VMSTATE_UINT32(ucr4, IMXSerialState),
          VMSTATE_END_OF_LIST()
      },
  };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
       * unfortunately.
       */
      mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    /*
 +     * TCEN and TXDC are both bit 3
 +     */
 +    mask |= s->ucr4 & UCR4_TCEN;
 +
      usr2 = s->usr2 & mask;
      qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
          return s->ucr3;
      case 0x23: /* UCR4 */
 +        return s->ucr4;
 +
      case 0x29: /* BRM Incremental */
          return 0x0; /* TODO */
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
               * qemu_chr_fe_write and background I/O callbacks */
              qemu_chr_fe_write_all(&s->chr, &ch, 1);
              s->usr1 &= ~USR1_TRDY;
 +            s->usr2 &= ~USR2_TXDC;
              imx_update(s);
              s->usr1 |= USR1_TRDY;
 +            s->usr2 |= USR2_TXDC;
              imx_update(s);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
          s->ucr3 = value & 0xffff;
          break;
 -    case 0x2d: /* UTS1 */
      case 0x23: /* UCR4 */
 +        s->ucr4 = value & 0xffff;
 +        imx_update(s);
 +        break;
 +
 +    case 0x2d: /* UTS1 */
          qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                        HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
          /* TODO */
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
+[PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints
-The TypeInfo and state struct for bcm2386 disagree about what the
+Convert the use of the DPRINTF debug macro in the PL061 model to
-parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
+use tracepoints.
 but the BCM2386State struct only defines the parent_obj field
 as DeviceState. This would have caused problems if anything
 actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
 Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
 need any of the additional functionality TYPE_SYS_BUS_DEVICE
 provides.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/arm/bcm2836.c | 2 +-
+ hw/gpio/pl061.c      | 27 +++++++++------------------
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/gpio/trace-events |  6 ++++++
 files changed, 15 insertions(+), 18 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/log.h"
- static const TypeInfo bcm2836_type_info = {
+ #include "qemu/module.h"
-     .name = TYPE_BCM2836,
+ #include "qom/object.h"
--    .parent = TYPE_SYS_BUS_DEVICE,
+-
-+    .parent = TYPE_DEVICE,
+-//#define DEBUG_PL061 1
-     .instance_size = sizeof(BCM2836State),
+-
-     .instance_init = bcm2836_init,
+-#ifdef DEBUG_PL061
-     .class_init = bcm2836_class_init,
+-#define DPRINTF(fmt, ...) \
 -do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
 -#define BADF(fmt, ...) \
 -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
 -#else
 -#define DPRINTF(fmt, ...) do {} while(0)
 -#define BADF(fmt, ...) \
 -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
 -#endif
 +#include "trace.h"
  static const uint8_t pl061_id[12] =
    { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
      uint8_t out;
      int i;
 -    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
 +    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
      /* Outputs float high.  */
      /* FIXME: This is board dependent.  */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
          for (i = 0; i < N_GPIOS; i++) {
              mask = 1 << i;
              if (changed & mask) {
 -                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 -                qemu_set_irq(s->out[i], (out & mask) != 0);
 +                int level = (out & mask) != 0;
 +                trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
 +                qemu_set_irq(s->out[i], level);
              }
          }
      }
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
          for (i = 0; i < N_GPIOS; i++) {
              mask = 1 << i;
              if (changed & mask) {
 -                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
 +                trace_pl061_input_change(DEVICE(s)->canonical_path, i,
 +                                         (s->data & mask) != 0);
                  if (!(s->isense & mask)) {
                      /* Edge interrupt */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
      /* Level interrupt */
      s->istate |= ~(s->data ^ s->iev) & s->isense;
 -    DPRINTF("istate = %02X\n", s->istate);
 +    trace_pl061_update_istate(DEVICE(s)->canonical_path,
 +                              s->istate, s->im, (s->istate & s->im) != 0);
      qemu_set_irq(s->irq, (s->istate & s->im) != 0);
  }
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x
  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +# pl061.c
 +pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
 +pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 +pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 +pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 +
  # sifive_gpio.c
  sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
  sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+[PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic
-Our BCM2836 type is really a generic one that can be any of
+Currently the pl061_read() and pl061_write() functions handle offsets
-the bcm283x family. Rename it accordingly. We change only
+using a combination of three if() statements and a switch().  Clean
-the names which are visible via the header file to the
+this up to use just a switch, using case ranges.
-rest of the QEMU code, leaving private function names
-in bcm2836.c as they are.
+This requires that instead of catching accesses to the luminary-only
+registers on a stock PL061 via a check on s->rsvd_start we use
-This is a preliminary to making bcm283x be an abstract
+an "is this luminary?" check in the cases for each luminary-only
-parent class to specific types for the bcm2836 and bcm2837.
+register.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 12 ++++++------
+ hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------
- hw/arm/bcm2836.c         | 17 +++++++++--------
+file changed, 79 insertions(+), 25 deletions(-)
- hw/arm/raspi.c           | 16 ++++++++--------
-files changed, 23 insertions(+), 22 deletions(-)
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/hw/gpio/pl061.c
-+++ b/include/hw/arm/bcm2836.h
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct PL061State {
- #include "hw/arm/bcm2835_peripherals.h"
+     qemu_irq irq;
- #include "hw/intc/bcm2836_control.h"
+     qemu_irq out[N_GPIOS];
+     const unsigned char *id;
--#define TYPE_BCM2836 "bcm2836"
+-    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
--#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+ };
-+#define TYPE_BCM283X "bcm283x"
-+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
+ static const VMStateDescription vmstate_pl061 = {
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
 -#define BCM2836_NCPUS 4
 +#define BCM283X_NCPUS 4
 -typedef struct BCM2836State {
 +typedef struct BCM283XState {
      /*< private >*/
      DeviceState parent_obj;
      /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
      char *cpu_type;
      uint32_t enabled_cpus;
 -    ARMCPU cpus[BCM2836_NCPUS];
 +    ARMCPU cpus[BCM283X_NCPUS];
      BCM2836ControlState control;
      BCM2835PeripheralState peripherals;
 -} BCM2836State;
 +} BCM283XState;
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2836.c
 +++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
  static void bcm2836_init(Object *obj)
  {
--    BCM2836State *s = BCM2836(obj);
+     PL061State *s = (PL061State *)opaque;
-+    BCM283XState *s = BCM283X(obj);
+-    if (offset < 0x400) {
-     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
+-        return s->data & (offset >> 2);
-     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
+-    }
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
+-    if (offset >= s->rsvd_start && offset <= 0xfcc) {
+-        goto err_out;
- static void bcm2836_realize(DeviceState *dev, Error **errp)
+-    }
- {
+-    if (offset >= 0xfd0 && offset < 0x1000) {
--    BCM2836State *s = BCM2836(dev);
+-        return s->id[(offset - 0xfd0) >> 2];
-+    BCM283XState *s = BCM283X(dev);
+-    }
-     Object *obj;
+     switch (offset) {
-     Error *err = NULL;
++    case 0x0 ... 0x3ff: /* Data */
-     int n;
++        return s->data & (offset >> 2);
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+     case 0x400: /* Direction */
-     /* common peripherals from bcm2835 */
+         return s->dir;
+     case 0x404: /* Interrupt sense */
-     obj = OBJECT(dev);
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
--    for (n = 0; n < BCM2836_NCPUS; n++) {
+     case 0x420: /* Alternate function select */
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
+         return s->afsel;
-         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+     case 0x500: /* 2mA drive */
-                           s->cpu_type);
++        if (s->id != pl061_id_luminary) {
-         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
++            goto bad_offset;
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
++        }
-     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+         return s->dr2r;
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
+     case 0x504: /* 4mA drive */
++        if (s->id != pl061_id_luminary) {
--    for (n = 0; n < BCM2836_NCPUS; n++) {
++            goto bad_offset;
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
++        }
-         /* Mirror bcm2836, which has clusterid set to 0xf
+         return s->dr4r;
-          * TODO: this should be converted to a property of ARM_CPU
+     case 0x508: /* 8mA drive */
-          */
++        if (s->id != pl061_id_luminary) {
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
++            goto bad_offset;
 +        }
          return s->dr8r;
      case 0x50c: /* Open drain */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->odr;
      case 0x510: /* Pull-up */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->pur;
      case 0x514: /* Pull-down */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->pdr;
      case 0x518: /* Slew rate control */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->slr;
      case 0x51c: /* Digital enable */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->den;
      case 0x520: /* Lock */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->locked;
      case 0x524: /* Commit */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->cr;
      case 0x528: /* Analog mode select */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->amsel;
 +    case 0xfd0 ... 0xfff: /* ID registers */
 +        return s->id[(offset - 0xfd0) >> 2];
      default:
 +    bad_offset:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "pl061_read: Bad offset %x\n", (int)offset);
          break;
      }
 -err_out:
 -    qemu_log_mask(LOG_GUEST_ERROR,
 -                  "pl061_read: Bad offset %x\n", (int)offset);
      return 0;
  }
- static Property bcm2836_props[] = {
+@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
--    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
+     PL061State *s = (PL061State *)opaque;
--    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+     uint8_t mask;
-+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
-+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+-    if (offset < 0x400) {
-+                       BCM283X_NCPUS),
++    switch (offset) {
-     DEFINE_PROP_END_OF_LIST()
++    case 0 ... 0x3ff:
- };
+         mask = (offset >> 2) & s->dir;
+         s->data = (s->data & ~mask) | (value & mask);
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+         pl061_update(s);
          return;
 -    }
 -    if (offset >= s->rsvd_start) {
 -        goto err_out;
 -    }
 -    switch (offset) {
      case 0x400: /* Direction */
          s->dir = value & 0xff;
          break;
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
          s->afsel = (s->afsel & ~mask) | (value & mask);
          break;
      case 0x500: /* 2mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->dr2r = value & 0xff;
          break;
      case 0x504: /* 4mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->dr4r = value & 0xff;
          break;
      case 0x508: /* 8mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->dr8r = value & 0xff;
          break;
      case 0x50c: /* Open drain */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->odr = value & 0xff;
          break;
      case 0x510: /* Pull-up */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->pur = value & 0xff;
          break;
      case 0x514: /* Pull-down */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->pdr = value & 0xff;
          break;
      case 0x518: /* Slew rate control */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->slr = value & 0xff;
          break;
      case 0x51c: /* Digital enable */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->den = value & 0xff;
          break;
      case 0x520: /* Lock */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->locked = (value != 0xacce551);
          break;
      case 0x524: /* Commit */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          if (!s->locked)
              s->cr = value & 0xff;
          break;
      case 0x528:
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->amsel = value & 0xff;
          break;
      default:
 -        goto err_out;
 +    bad_offset:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "pl061_write: Bad offset %x\n", (int)offset);
 +        return;
      }
      pl061_update(s);
      return;
 -err_out:
 -    qemu_log_mask(LOG_GUEST_ERROR,
 -                  "pl061_write: Bad offset %x\n", (int)offset);
  }
- static const TypeInfo bcm2836_type_info = {
+ static void pl061_reset(DeviceState *dev)
--    .name = TYPE_BCM2836,
+@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)
-+    .name = TYPE_BCM283X,
+     PL061State *s = PL061(obj);
-     .parent = TYPE_DEVICE,
--    .instance_size = sizeof(BCM2836State),
+     s->id = pl061_id_luminary;
-+    .instance_size = sizeof(BCM283XState),
+-    s->rsvd_start = 0x52c;
      .instance_init = bcm2836_init,
      .class_init = bcm2836_class_init,
  };
 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/raspi.c
 +++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
  static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
  typedef struct RasPiState {
 -    BCM2836State soc;
 +    BCM283XState soc;
      MemoryRegion ram;
  } RasPiState;
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
      BusState *bus;
      DeviceState *carddev;
 -    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
 +    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
      object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                                &error_abort);
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
      mc->no_floppy = 1;
      mc->no_cdrom = 1;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 -    mc->max_cpus = BCM2836_NCPUS;
 -    mc->min_cpus = BCM2836_NCPUS;
 -    mc->default_cpus = BCM2836_NCPUS;
 +    mc->max_cpus = BCM283X_NCPUS;
 +    mc->min_cpus = BCM283X_NCPUS;
 +    mc->default_cpus = BCM283X_NCPUS;
      mc->default_ram_size = 1024 * 1024 * 1024;
      mc->ignore_memory_transaction_failures = true;
  };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
      mc->no_floppy = 1;
      mc->no_cdrom = 1;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
 -    mc->max_cpus = BCM2836_NCPUS;
 -    mc->min_cpus = BCM2836_NCPUS;
 -    mc->default_cpus = BCM2836_NCPUS;
 +    mc->max_cpus = BCM283X_NCPUS;
 +    mc->min_cpus = BCM283X_NCPUS;
 +    mc->default_cpus = BCM283X_NCPUS;
      mc->default_ram_size = 1024 * 1024 * 1024;
  }
- DEFINE_MACHINE("raspi3", raspi3_machine_init)
  static void pl061_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
      SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      s->id = pl061_id;
 -    s->rsvd_start = 0x424;
      memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
      sysbus_init_mmio(sbd, &s->iomem);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+[PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write
-If we're directly booting a Linux kernel and the CPU supports both
+Add tracepoints for reads and writes to the PL061 registers. This requires
-EL3 and EL2, we start the kernel in EL2, as it expects. We must also
+restructuring pl061_read() to only return after the tracepoint, rather
-set the SCR_EL3.HCE bit in this situation, so that the HVC
+than having lots of early-returns.
 instruction is enabled rather than UNDEFing. Otherwise at least some
 kernels will panic when trying to initialize KVM in the guest.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/arm/boot.c | 5 +++++
+ hw/gpio/pl061.c      | 70 ++++++++++++++++++++++++++++++--------------
-file changed, 5 insertions(+)
+ hw/gpio/trace-events |  2 ++
 files changed, 50 insertions(+), 22 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/boot.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
-                     assert(!info->secure_board_setup);
+                            unsigned size)
-                 }
+ {
+     PL061State *s = (PL061State *)opaque;
-+                if (arm_feature(env, ARM_FEATURE_EL2)) {
++    uint64_t r = 0;
-+                    /* If we have EL2 then Linux expects the HVC insn to work */
-+                    env->cp15.scr_el3 |= SCR_HCE;
+     switch (offset) {
-+                }
+     case 0x0 ... 0x3ff: /* Data */
 -        return s->data & (offset >> 2);
 +        r = s->data & (offset >> 2);
 +        break;
      case 0x400: /* Direction */
 -        return s->dir;
 +        r = s->dir;
 +        break;
      case 0x404: /* Interrupt sense */
 -        return s->isense;
 +        r = s->isense;
 +        break;
      case 0x408: /* Interrupt both edges */
 -        return s->ibe;
 +        r = s->ibe;
 +        break;
      case 0x40c: /* Interrupt event */
 -        return s->iev;
 +        r = s->iev;
 +        break;
      case 0x410: /* Interrupt mask */
 -        return s->im;
 +        r = s->im;
 +        break;
      case 0x414: /* Raw interrupt status */
 -        return s->istate;
 +        r = s->istate;
 +        break;
      case 0x418: /* Masked interrupt status */
 -        return s->istate & s->im;
 +        r = s->istate & s->im;
 +        break;
      case 0x420: /* Alternate function select */
 -        return s->afsel;
 +        r = s->afsel;
 +        break;
      case 0x500: /* 2mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr2r;
 +        r = s->dr2r;
 +        break;
      case 0x504: /* 4mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr4r;
 +        r = s->dr4r;
 +        break;
      case 0x508: /* 8mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr8r;
 +        r = s->dr8r;
 +        break;
      case 0x50c: /* Open drain */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->odr;
 +        r = s->odr;
 +        break;
      case 0x510: /* Pull-up */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->pur;
 +        r = s->pur;
 +        break;
      case 0x514: /* Pull-down */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->pdr;
 +        r = s->pdr;
 +        break;
      case 0x518: /* Slew rate control */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->slr;
 +        r = s->slr;
 +        break;
      case 0x51c: /* Digital enable */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->den;
 +        r = s->den;
 +        break;
      case 0x520: /* Lock */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->locked;
 +        r = s->locked;
 +        break;
      case 0x524: /* Commit */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->cr;
 +        r = s->cr;
 +        break;
      case 0x528: /* Analog mode select */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->amsel;
 +        r = s->amsel;
 +        break;
      case 0xfd0 ... 0xfff: /* ID registers */
 -        return s->id[(offset - 0xfd0) >> 2];
 +        r = s->id[(offset - 0xfd0) >> 2];
 +        break;
      default:
      bad_offset:
          qemu_log_mask(LOG_GUEST_ERROR,
                        "pl061_read: Bad offset %x\n", (int)offset);
          break;
      }
 -    return 0;
 +
-                 /* Set to non-secure if not a secure boot */
++    trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
-                 if (!info->secure_boot &&
++    return r;
-                     (cs != first_cpu || !info->secure_board_setup)) {
+ }
  static void pl061_write(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
      PL061State *s = (PL061State *)opaque;
      uint8_t mask;
 +    trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
 +
      switch (offset) {
      case 0 ... 0x3ff:
          mask = (offset >> 2) & s->dir;
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
  pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
  pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
  pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 +pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 +pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
  # sifive_gpio.c
  sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+[PULL 09/17] hw/gpio/pl061: Document the interface of this device
-Add some assertions that if we're about to boot an AArch64 kernel,
+Add a comment documenting the "QEMU interface" of this device:
-the board code has not mistakenly set either secure_boot or
+which MMIO regions, IRQ lines, GPIO lines, etc it exposes.
 secure_board_setup. It doesn't make sense to set secure_boot,
 because all AArch64 kernels must be booted in non-secure mode.
 It might in theory make sense to set secure_board_setup, but
 we don't currently support that, because only the AArch32
 bootloader[] code calls this hook; bootloader_aarch64[] does not.
 Since we don't have a current need for this functionality, just
 assert that we don't try to use it. If it's needed we'll add
 it later.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 7 +++++++
+ hw/gpio/pl061.c | 7 +++++++
 file changed, 7 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/boot.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@
-                     } else {
+  * Written by Paul Brook
-                         env->pstate = PSTATE_MODE_EL1h;
+  *
-                     }
+  * This code is licensed under the GPL.
-+                    /* AArch64 kernels never boot in secure mode */
++ *
-+                    assert(!info->secure_boot);
++ * QEMU interface:
-+                    /* This hook is only supported for AArch32 currently:
++ *  + sysbus MMIO region 0: the device registers
-+                     * bootloader_aarch64[] will not call the hook, and
++ *  + sysbus IRQ: the GPIOINTR interrupt line
-+                     * the code above has already dropped us into EL2 or EL1.
++ *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
-+                     */
++ *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
-+                    assert(!info->secure_board_setup);
++ *    outputs
-                 }
+  */
-                 /* Set to non-secure if not a secure boot */
+ #include "qemu/osdep.h"
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
+[PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
-The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
+The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
-CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
+which lets the guest configure whether the GPIO lines are pull-up,
-is required for Linux to boot.
+pull-down, or truly floating. Instead of assuming all lines are pulled
 high, honour the PUR and PDR registers.
 For the plain PL061, continue to assume that lines have an external
 pull-up resistor, as we did before.
 The stellaris board actually relies on this behaviour -- the CD line
 of the ssd0323 display device is connected to GPIO output C7, and it
 is only because of a different bug which we're about to fix that we
 weren't incorrectly driving this line high on reset and putting the
 ssd0323 into data mode.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 11 +++++++----
+ hw/gpio/pl061.c      | 58 +++++++++++++++++++++++++++++++++++++++++---
-file changed, 7 insertions(+), 4 deletions(-)
+ hw/gpio/trace-events |  2 +-
 files changed, 55 insertions(+), 5 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {
+     }
  struct BCM283XInfo {
      const char *name;
 +    int clusterid;
  };
- static const BCM283XInfo bcm283x_socs[] = {
++static uint8_t pl061_floating(PL061State *s)
-     {
++{
-         .name = TYPE_BCM2836,
++    /*
-+        .clusterid = 0xf,
++     * Return mask of bits which correspond to pins configured as inputs
-     },
++     * and which are floating (neither pulled up to 1 nor down to 0).
-     {
++     */
-         .name = TYPE_BCM2837,
++    uint8_t floating;
-+        .clusterid = 0x0,
++
-     },
++    if (s->id == pl061_id_luminary) {
- };
++        /*
++         * If both PUR and PDR bits are clear, there is neither a pullup
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
++         * nor a pulldown in place, and the output truly floats.
- static void bcm2836_realize(DeviceState *dev, Error **errp)
++         */
 +        floating = ~(s->pur | s->pdr);
 +    } else {
 +        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 +        floating = 0;
 +    }
 +    return floating & ~s->dir;
 +}
 +
 +static uint8_t pl061_pullups(PL061State *s)
 +{
 +    /*
 +     * Return mask of bits which correspond to pins configured as inputs
 +     * and which are pulled up to 1.
 +     */
 +    uint8_t pullups;
 +
 +    if (s->id == pl061_id_luminary) {
 +        /*
 +         * The Luminary variant of the PL061 has an extra registers which
 +         * the guest can use to configure whether lines should be pullup
 +         * or pulldown.
 +         */
 +        pullups = s->pur;
 +    } else {
 +        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 +        pullups = 0xff;
 +    }
 +    return pullups & ~s->dir;
 +}
 +
  static void pl061_update(PL061State *s)
  {
-     BCM283XState *s = BCM283X(dev);
+     uint8_t changed;
-+    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
+     uint8_t mask;
-+    const BCM283XInfo *info = bc->info;
+     uint8_t out;
-     Object *obj;
+     int i;
-     Error *err = NULL;
++    uint8_t pullups = pl061_pullups(s);
-     int n;
++    uint8_t floating = pl061_floating(s);
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
+-    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
++    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,
-     for (n = 0; n < BCM283X_NCPUS; n++) {
++                       pullups, floating);
--        /* Mirror bcm2836, which has clusterid set to 0xf
--         * TODO: this should be converted to a property of ARM_CPU
+-    /* Outputs float high.  */
--         */
+-    /* FIXME: This is board dependent.  */
--        s->cpus[n].mp_affinity = 0xF00 | n;
+-    out = (s->data & s->dir) | ~s->dir;
-+        /* TODO: this should be converted to a property of ARM_CPU */
++    /*
-+        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
++     * Pins configured as output are driven from the data register;
++     * otherwise if they're pulled up they're 1, and if they're floating
-         /* set periphbase/CBAR value for CPU-local registers */
++     * then we give them the same value they had previously, so we don't
-         object_property_set_int(OBJECT(&s->cpus[n]),
++     * report any change to the other end.
 +     */
 +    out = (s->data & s->dir) | pullups | (s->old_out_data & floating);
      changed = s->old_out_data ^ out;
      if (changed) {
          s->old_out_data = out;
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  # pl061.c
 -pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
 +pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"
  pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
  pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
  pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
+[PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable
-Now we have separate types for BCM2386 and BCM2387, we might as well
+The PL061 GPIO does not itself include pullup or pulldown resistors
-just hard-code the CPU type they use rather than having it passed
+to set the value of a GPIO line treated as an output when it is
-through as an object property. This then lets us put the initialization
+configured as an input (ie when the PL061 itself is not driving it).
-of the CPU object in init rather than realize.
+In real hardware it is up to the board to add suitable pullups or
 pulldowns.  Currently our implementation hardwires this to "outputs
 pulled high", which is correct for some boards (eg the realview ones:
 see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
 User Guide" DUI0224I), but wrong for others.
-Note that this change means that it's no longer possible on
+In particular, the wiring in the 'virt' board and the gpio-pwr device
-the command line to use -cpu to ask for a different kind of
+assumes that wires should be pulled low, because otherwise the
-CPU than the SoC supports. This was never a supported thing to
+pull-to-high will trigger a shutdown or reset action.  (The only
-do anyway; we were just not sanity-checking the command line.
+reason this doesn't happen immediately on startup is due to another
 bug in the PL061, where we don't assert the GPIOs to the correct
 value on reset, but will do so as soon as the guest touches a
 register and pl061_update() gets called.)
-This does require us to only build the bcm2837 object on
+Add properties to the pl061 so the board can configure whether it
-TARGET_AARCH64 configs, since otherwise it won't instantiate
+wants GPIO lines to have pullup, pulldown, or neither.
 due to the missing cortex-a53 device and "make check" will fail.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 24 +++++++++++++++---------
+ hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----
- hw/arm/raspi.c   |  2 --
+file changed, 47 insertions(+), 4 deletions(-)
 files changed, 15 insertions(+), 11 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/gpio/pl061.c
 @@ -XXX,XX +XXX,XX @@
+  *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
- struct BCM283XInfo {
+  *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
-     const char *name;
+  *    outputs
-+    const char *cpu_type;
++ *  + QOM property "pullups": an integer defining whether non-floating lines
-     int clusterid;
++ *    configured as inputs should be pulled up to logical 1 (ie whether in
 + *    real hardware they have a pullup resistor on the line out of the PL061).
 + *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
 + *    be pulled high, bit 1 configures line 1, and so on. The default is 0xff,
 + *    indicating that all GPIO lines are pulled up to logical 1.
 + *  + QOM property "pulldowns": an integer defining whether non-floating lines
 + *    configured as inputs should be pulled down to logical 0 (ie whether in
 + *    real hardware they have a pulldown resistor on the line out of the PL061).
 + *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
 + *    be pulled low, bit 1 configures line 1, and so on. The default is 0x0.
 + *    It is an error to set a bit in both "pullups" and "pulldowns". If a bit
 + *    is 0 in both, then the line is considered to be floating, and it will
 + *    not have qemu_set_irq() called on it when it is configured as an input.
   */
  #include "qemu/osdep.h"
  #include "hw/irq.h"
  #include "hw/sysbus.h"
 +#include "hw/qdev-properties.h"
  #include "migration/vmstate.h"
 +#include "qapi/error.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
  #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct PL061State {
      qemu_irq irq;
      qemu_irq out[N_GPIOS];
      const unsigned char *id;
 +    /* Properties, for non-Luminary PL061 */
 +    uint32_t pullups;
 +    uint32_t pulldowns;
  };
- static const BCM283XInfo bcm283x_socs[] = {
+ static const VMStateDescription vmstate_pl061 = {
-     {
+@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)
-         .name = TYPE_BCM2836,
+          */
-+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
+         floating = ~(s->pur | s->pdr);
-         .clusterid = 0xf,
+     } else {
-     },
+-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-+#ifdef TARGET_AARCH64
+-        floating = 0;
-     {
++        floating = ~(s->pullups | s->pulldowns);
-         .name = TYPE_BCM2837,
+     }
-+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
+     return floating & ~s->dir;
-         .clusterid = 0x0,
+ }
-     },
+@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_pullups(PL061State *s)
-+#endif
+          */
- };
+         pullups = s->pur;
+     } else {
- static void bcm2836_init(Object *obj)
+-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 -        pullups = 0xff;
 +        pullups = s->pullups;
      }
      return pullups & ~s->dir;
  }
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
      qdev_init_gpio_out(dev, s->out, N_GPIOS);
  }
 +static void pl061_realize(DeviceState *dev, Error **errp)
 +{
 +    PL061State *s = PL061(dev);
 +
 +    if (s->pullups > 0xff) {
 +        error_setg(errp, "pullups property must be between 0 and 0xff");
 +        return;
 +    }
 +    if (s->pulldowns > 0xff) {
 +        error_setg(errp, "pulldowns property must be between 0 and 0xff");
 +        return;
 +    }
 +    if (s->pullups & s->pulldowns) {
 +        error_setg(errp, "no bit may be set both in pullups and pulldowns");
 +        return;
 +    }
 +}
 +
 +static Property pl061_props[] = {
 +    DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff),
 +    DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0),
 +    DEFINE_PROP_END_OF_LIST()
 +};
 +
  static void pl061_class_init(ObjectClass *klass, void *data)
  {
-     BCM283XState *s = BCM283X(obj);
+     DeviceClass *dc = DEVICE_CLASS(klass);
-+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
-+    const BCM283XInfo *info = bc->info;
+     dc->vmsd = &vmstate_pl061;
-+    int n;
+     dc->reset = &pl061_reset;
-+
++    dc->realize = pl061_realize;
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
++    device_class_set_props(dc, pl061_props);
 +        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 +                          info->cpu_type);
 +        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 +                                  &error_abort);
 +    }
      object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
      object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      /* common peripherals from bcm2835 */
 -    obj = OBJECT(dev);
 -    for (n = 0; n < BCM283X_NCPUS; n++) {
 -        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 -                          s->cpu_type);
 -        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 -                                  &error_abort);
 -    }
 -
      obj = object_property_get_link(OBJECT(dev), "ram", &err);
      if (obj == NULL) {
          error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
  }
- static Property bcm2836_props[] = {
+ static const TypeInfo pl061_info = {
 -    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
      DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                         BCM283X_NCPUS),
      DEFINE_PROP_END_OF_LIST()
 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/raspi.c
 +++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
      /* Setup the SOC */
      object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                     &error_abort);
 -    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
 -                            &error_abort);
      object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                              &error_abort);
      int board_rev = version == 3 ? 0xa02082 : 0xa21041;
 --
-.16.2
+.20.1

-New patch
+[PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high
+For the virt board we have two PL061 devices -- one for NonSecure which
+is inputs only, and one for Secure which is outputs only. For the former,
+we don't care whether its outputs are pulled low or high when the line is
+configured as an input, because we don't connect them. For the latter,
+we do care, because we wire the lines up to the gpio-pwr device, which
+assumes that level 1 means "do the action" and 1 means "do nothing".
+For consistency in case we add more outputs in future, configure both
+PL061s to pull GPIO lines down to 0.
+Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ hw/arm/virt.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
+     MachineState *ms = MACHINE(vms);
+     pl061_dev = qdev_new("pl061");
++    /* Pull lines down to 0 if not driven by the PL061 */
++    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
++    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
+     s = SYS_BUS_DEVICE(pl061_dev);
+     sysbus_realize_and_unref(s, &error_fatal);
+     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
+--
+.20.1

-[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
+[PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
-The raspi3 has AArch64 CPUs, which means that our smpboot
+The PL061 comes out of reset with all its lines configured as input,
-code for keeping the secondary CPUs in a pen needs to have
+which means they might need to be pulled to 0 or 1 depending on the
-a version for A64 as well as A32. Without this, the
+'pullups' and 'pulldowns' properties.  Currently we do not assert
-secondary CPUs go into an infinite loop of taking undefined
+these lines on reset; they will only be set whenever the guest first
-instruction exceptions.
+touches a register that triggers a call to pl061_update().
 Convert the device to three-phase reset so we have a place where we
 can safely call qemu_set_irq() to set the floating lines to their
 correct values.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
+ hw/gpio/pl061.c      | 29 +++++++++++++++++++++++++----
-file changed, 40 insertions(+), 1 deletion(-)
+ hw/gpio/trace-events |  1 +
 files changed, 26 insertions(+), 4 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/raspi.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
- #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
+     return;
  #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
  #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
 +#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
  /* Table of Linux board IDs for different Pi versions */
  static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                         info->smp_loader_start);
  }
-+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+-static void pl061_reset(DeviceState *dev)
 +static void pl061_enter_reset(Object *obj, ResetType type)
  {
 -    PL061State *s = PL061(dev);
 +    PL061State *s = PL061(obj);
 +
 +    trace_pl061_reset(DEVICE(s)->canonical_path);
      /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
      s->data = 0;
 -    s->old_out_data = 0;
      s->old_in_data = 0;
      s->dir = 0;
      s->isense = 0;
@@ -XXX,XX +XXX,XX @@ static void pl061_reset(DeviceState *dev)
      s->amsel = 0;
  }
 +static void pl061_hold_reset(Object *obj)
 +{
-+    /* Unlike the AArch32 version we don't need to call the board setup hook.
++    PL061State *s = PL061(obj);
-+     * The mechanism for doing the spin-table is also entirely different.
++    int i, level;
-+     * We must have four 64-bit fields at absolute addresses
++    uint8_t floating = pl061_floating(s);
-+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
++    uint8_t pullups = pl061_pullups(s);
 +     * our CPUs, and which we must ensure are zero initialized before
 +     * the primary CPU goes into the kernel. We put these variables inside
 +     * a rom blob, so that the reset for ROM contents zeroes them for us.
 +     */
 +    static const uint32_t smpboot[] = {
 +        0xd2801b05, /*        mov     x5, 0xd8 */
 +        0xd53800a6, /*        mrs     x6, mpidr_el1 */
 +        0x924004c6, /*        and     x6, x6, #0x3 */
 +        0xd503205f, /* spin:  wfe */
 +        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
 +        0xb4ffffc4, /*        cbz     x4, spin */
 +        0xd2800000, /*        mov     x0, #0x0 */
 +        0xd2800001, /*        mov     x1, #0x0 */
 +        0xd2800002, /*        mov     x2, #0x0 */
 +        0xd2800003, /*        mov     x3, #0x0 */
 +        0xd61f0080, /*        br      x4 */
 +    };
 +
-+    static const uint64_t spintables[] = {
++    for (i = 0; i < N_GPIOS; i++) {
-+        0, 0, 0, 0
++        if (extract32(floating, i, 1)) {
-+    };
++            continue;
-+
++        }
-+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
++        level = extract32(pullups, i, 1);
-+                       info->smp_loader_start);
++        trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
-+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
++        qemu_set_irq(s->out[i], level);
-+                       SPINTABLE_ADDR);
++    }
 +    s->old_out_data = pullups;
 +}
 +
- static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
+ static void pl061_set_irq(void * opaque, int irq, int level)
  {
-     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
+     PL061State *s = (PL061State *)opaque;
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ static Property pl061_props[] = {
-     /* Pi2 and Pi3 requires SMP setup */
+ static void pl061_class_init(ObjectClass *klass, void *data)
-     if (version >= 2) {
+ {
-         binfo.smp_loader_start = SMPBOOT_ADDR;
+     DeviceClass *dc = DEVICE_CLASS(klass);
--        binfo.write_secondary_boot = write_smpboot;
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+        if (version == 2) {
-+            binfo.write_secondary_boot = write_smpboot;
+     dc->vmsd = &vmstate_pl061;
-+        } else {
+-    dc->reset = &pl061_reset;
-+            binfo.write_secondary_boot = write_smpboot64;
+     dc->realize = pl061_realize;
-+        }
+     device_class_set_props(dc, pl061_props);
-         binfo.secondary_cpu_reset_hook = reset_secondary;
++    rc->phases.enter = pl061_enter_reset;
-     }
++    rc->phases.hold = pl061_hold_reset;
+ }
  static const TypeInfo pl061_info = {
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to
  pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
  pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
  pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 +pl061_reset(const char *id) "%s reset"
  # sifive_gpio.c
  sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+[PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation
-For the rpi1 and 2 we want to boot the Linux kernel via some
+The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
-custom setup code that makes sure that the SMC instruction
+reset value for GPIOPUR.  We can get away with not letting the board
-acts as a no-op, because it's used for cache maintenance.
+configure the PUR reset value because we don't actually wire anything
-The rpi3 boots AArch64 kernels, which don't need SMC for
+up to the lines which should reset to pull-up.  Add a comment noting
-cache maintenance and always expect to be booted non-secure.
+this omission.
 Don't fill in the aarch32-specific parts of the binfo struct.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 17 +++++++++++++----
+ hw/gpio/pl061.c | 9 +++++++++
-file changed, 13 insertions(+), 4 deletions(-)
+file changed, 9 insertions(+)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/hw/gpio/pl061.c
-+++ b/hw/arm/raspi.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
-     binfo.board_id = raspi_boardid[version];
+     trace_pl061_reset(DEVICE(s)->canonical_path);
-     binfo.ram_size = ram_size;
-     binfo.nb_cpus = smp_cpus;
+     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
 -    binfo.board_setup_addr = BOARDSETUP_ADDR;
 -    binfo.write_board_setup = write_board_setup;
 -    binfo.secure_board_setup = true;
 -    binfo.secure_boot = true;
 +
-+    if (version <= 2) {
++    /*
-+        /* The rpi1 and 2 require some custom setup code to run in Secure
++     * FIXME: For the LM3S6965, not all of the PL061 instances have the
-+         * mode before booting a kernel (to set up the SMC vectors so
++     * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory
-+         * that we get a no-op SMC; this is used by Linux to call the
++     * we should allow the board to configure these via properties.
-+         * firmware for some cache maintenance operations.
++     * In practice, we don't wire anything up to the affected GPIO lines
-+         * The rpi3 doesn't need this.
++     * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can
-+         */
++     * get away with this inaccuracy.
-+        binfo.board_setup_addr = BOARDSETUP_ADDR;
++     */
-+        binfo.write_board_setup = write_board_setup;
+     s->data = 0;
-+        binfo.secure_board_setup = true;
+     s->old_in_data = 0;
-+        binfo.secure_boot = true;
+     s->dir = 0;
 +    }
      /* Pi2 and Pi3 requires SMP setup */
      if (version >= 2) {
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
+[PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect
-The bcm2837 is pretty similar to the bcm2836, but it does have
+The stellaris board doesn't emulate the handling of the OLED
-some differences. Notably, the MPIDR affinity aff1 values it
+chipselect line correctly.  Expand the comment describing this,
-sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
+including a sketch of the theoretical correct way to do it.
 uses, and if this is wrong Linux will not boot.
 Rather than trying to have one device with properties that
 configure it differently for the two cases, create two
 separate QOM devices for the two SoCs. We use the same approach
 as hw/arm/aspeed_soc.c and share code and have a data table
 that might differ per-SoC. For the moment the two types don't
 actually have different behaviour.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
+ hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
- hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
+file changed, 55 insertions(+), 1 deletion(-)
  hw/arm/raspi.c           |  3 ++-
 files changed, 53 insertions(+), 6 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/hw/arm/stellaris.c
-+++ b/include/hw/arm/bcm2836.h
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
+             DeviceState *sddev;
- #define BCM283X_NCPUS 4
+             DeviceState *ssddev;
-+/* These type names are for specific SoCs; other than instantiating
+-            /* Some boards have both an OLED controller and SD card connected to
-+ * them, code using these devices should always handle them via the
++            /*
-+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
++             * Some boards have both an OLED controller and SD card connected to
-+ */
+              * the same SSI port, with the SD card chip select connected to a
-+#define TYPE_BCM2836 "bcm2836"
+              * GPIO pin.  Technically the OLED chip select is connected to the
-+#define TYPE_BCM2837 "bcm2837"
+              * SSI Fss pin.  We do not bother emulating that as both devices
-+
+              * should never be selected simultaneously, and our OLED controller
- typedef struct BCM283XState {
+              * ignores stray 0xff commands that occur when deselecting the SD
-     /*< private >*/
+              * card.
-     DeviceState parent_obj;
++             *
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
++             * The h/w wiring is:
-     BCM2835PeripheralState peripherals;
++             *  - GPIO pin D0 is wired to the active-low SD card chip select
- } BCM283XState;
++             *  - GPIO pin A3 is wired to the active-low OLED chip select
++             *  - The SoC wiring of the PL061 "auxiliary function" for A3 is
-+typedef struct BCM283XInfo BCM283XInfo;
++             *    SSI0Fss ("frame signal"), which is an output from the SoC's
-+
++             *    SSI controller. The SSI controller takes SSI0Fss low when it
-+typedef struct BCM283XClass {
++             *    transmits a frame, so it can work as a chip-select signal.
-+    DeviceClass parent_class;
++             *  - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
-+    const BCM283XInfo *info;
++             *    (the OLED never sends data to the CPU, so no wiring needed)
-+} BCM283XClass;
++             *  - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
-+
++             *    and the OLED display-data-in
-+#define BCM283X_CLASS(klass) \
++             *  - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
-+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
++             *    serial-clock input
-+#define BCM283X_GET_CLASS(obj) \
++             * So a guest that wants to use the OLED can configure the PL061
-+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
++             * to make pins A2, A3, A5 aux-function, so they are connected
-+
++             * directly to the SSI controller. When the SSI controller sends
- #endif /* BCM2836_H */
++             * data it asserts SSI0Fss which selects the OLED.
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
++             * A guest that wants to use the SD card configures A2, A4 and A5
-index XXXXXXX..XXXXXXX 100644
++             * as aux-function, but leaves A3 as a software-controlled GPIO
---- a/hw/arm/bcm2836.c
++             * line. It asserts the SD card chip-select by using the PL061
-+++ b/hw/arm/bcm2836.c
++             * to control pin D0, and lets the SSI controller handle Clk, Tx
-@@ -XXX,XX +XXX,XX @@
++             * and Rx. (The SSI controller asserts Fss during tx cycles as
- /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
++             * usual, but because A3 is not set to aux-function this is not
- #define BCM2836_CONTROL_BASE    0x40000000
++             * forwarded to the OLED, and so the OLED stays unselected.)
++             *
-+struct BCM283XInfo {
++             * The QEMU implementation instead is:
-+    const char *name;
++             *  - GPIO pin D0 is wired to the active-low SD card chip select,
-+};
++             *    and also to the OLED chip-select which is implemented
-+
++             *    as *active-high*
-+static const BCM283XInfo bcm283x_socs[] = {
++             *  - SSI controller signals go to the devices regardless of
-+    {
++             *    whether the guest programs A2, A4, A5 as aux-function or not
-+        .name = TYPE_BCM2836,
++             *
-+    },
++             * The problem with this implementation is if the guest doesn't
-+    {
++             * care about the SD card and only uses the OLED. In that case it
-+        .name = TYPE_BCM2837,
++             * may choose never to do anything with D0 (leaving it in its
-+    },
++             * default floating state, which reliably leaves the card disabled
-+};
++             * because an SD card has a pullup on CS within the card itself),
-+
++             * and only set up A2, A3, A5. This for us would mean the OLED
- static void bcm2836_init(Object *obj)
++             * never gets the chip-select assert it needs. We work around
- {
++             * this with a manual raise of D0 here (despite board creation
-     BCM283XState *s = BCM283X(obj);
++             * code being the wrong place to raise IRQ lines) to put the OLED
-@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
++             * into an initially selected state.
-     DEFINE_PROP_END_OF_LIST()
++             *
- };
++             * In theory the right way to model this would be:
++             *  - Implement aux-function support in the PL061, with an
--static void bcm2836_class_init(ObjectClass *oc, void *data)
++             *    extra set of AFIN and AFOUT GPIO lines (set up so that
-+static void bcm283x_class_init(ObjectClass *oc, void *data)
++             *    if a GPIO line is in auxfn mode the main GPIO in and out
- {
++             *    track the AFIN and AFOUT lines)
-     DeviceClass *dc = DEVICE_CLASS(oc);
++             *  - Wire the AFOUT for D0 up to either a line from the
-+    BCM283XClass *bc = BCM283X_CLASS(oc);
++             *    SSI controller that's pulled low around every transmit,
++             *    or at least to an always-0 line here on the board
--    dc->props = bcm2836_props;
++             *  - Make the ssd0323 OLED controller chipselect active-low
-+    bc->info = data;
+              */
-     dc->realize = bcm2836_realize;
+             bus = qdev_get_child_bus(dev, "ssi");
 +    dc->props = bcm2836_props;
  }
 -static const TypeInfo bcm2836_type_info = {
 +static const TypeInfo bcm283x_type_info = {
      .name = TYPE_BCM283X,
      .parent = TYPE_DEVICE,
      .instance_size = sizeof(BCM283XState),
      .instance_init = bcm2836_init,
 -    .class_init = bcm2836_class_init,
 +    .class_size = sizeof(BCM283XClass),
 +    .abstract = true,
  };
  static void bcm2836_register_types(void)
  {
 -    type_register_static(&bcm2836_type_info);
 +    int i;
 +
 +    type_register_static(&bcm283x_type_info);
 +    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
 +        TypeInfo ti = {
 +            .name = bcm283x_socs[i].name,
 +            .parent = TYPE_BCM283X,
 +            .class_init = bcm283x_class_init,
 +            .class_data = (void *) &bcm283x_socs[i],
 +        };
 +        type_register(&ti);
 +    }
  }
  type_init(bcm2836_register_types)
 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/raspi.c
 +++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
      BusState *bus;
      DeviceState *carddev;
 -    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
 +    object_initialize(&s->soc, sizeof(s->soc),
 +                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
      object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                                &error_abort);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
+[PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
-From: Guenter Roeck <linux@roeck-us.net>
+From: "hnick@vmware.com" <hnick@vmware.com>
-The sabrelite machine model used by qemu-system-arm is based on the
+Signed-off-by: Nick Hudson <hnick@vmware.com>
 Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
 controller which is supported in QEMU using the imx_fec.c module
 (actually called imx.enet for this model.)
 The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
 imx.enet device like this:
  #define FSL_IMX6_ENET_MAC_1588_IRQ 118
  #define FSL_IMX6_ENET_MAC_IRQ 119
 According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
 page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
 interrupts are as follows.
 ENET MAC 0 IRQ
 ENET MAC 0 1588 Timer interrupt
 where
 - 32 == 118
 - 32 == 119
 In other words, the vector definitions in the fsl-imx6.h file are reversed.
 Fixing the interrupts alone causes problems with older Linux kernels:
 The Ethernet interface will fail to probe with Linux v4.9 and earlier.
 Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
 error handling. This is a Linux kernel problem, not a qemu problem:
 the Linux kernel only worked by accident since it requested both interrupts.
 For backward compatibility, generate the Ethernet interrupt on both interrupt
 lines. This was shown to work from all Linux kernel releases starting with
 v3.16.
 Link: https://bugs.launchpad.net/qemu/+bug/1753309
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6.h |  4 ++--
+ target/arm/helper.c | 16 +++++++++++++---
- hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
+file changed, 13 insertions(+), 3 deletions(-)
 files changed, 29 insertions(+), 3 deletions(-)
-diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
+--- a/target/arm/helper.c
-+++ b/include/hw/arm/fsl-imx6.h
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
- #define FSL_IMX6_HDMI_MASTER_IRQ 115
+       .access = PL1_RW, .accessfn = access_tda,
- #define FSL_IMX6_HDMI_CEC_IRQ 116
+       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
- #define FSL_IMX6_MLB150_LOW_IRQ 117
+       .resetvalue = 0 },
--#define FSL_IMX6_ENET_MAC_1588_IRQ 118
+-    /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
 -#define FSL_IMX6_ENET_MAC_IRQ 119
 +#define FSL_IMX6_ENET_MAC_IRQ 118
 +#define FSL_IMX6_ENET_MAC_1588_IRQ 119
  #define FSL_IMX6_PCIE1_IRQ 120
  #define FSL_IMX6_PCIE2_IRQ 121
  #define FSL_IMX6_PCIE3_IRQ 122
 diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/imx_fec.c
 +++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
  static void imx_eth_update(IMXFECState *s)
  {
 -    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
 +    /*
-+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
++     * MDCCSR_EL0[30:29] map to EDSCR[30:29].  Simply RAZ as the external
-+     * interrupts swapped. This worked with older versions of Linux (4.14
++     * Debug Communication Channel is not implemented.
 +     * and older) since Linux associated both interrupt lines with Ethernet
 +     * MAC interrupts. Specifically,
 +     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
 +     *   timer interrupts. Those versions of Linux fail with versions of QEMU
 +     *   with swapped interrupt assignments.
 +     * - In linux 4.14, both interrupt lines were registered with the Ethernet
 +     *   MAC interrupt handler. As a result, all versions of qemu happen to
 +     *   work, though that is accidental.
 +     * - In Linux 4.9 and older, the timer interrupt was registered directly
 +     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
 +     *   redirected to a GPIO interrupt to work around erratum ERR006687.
 +     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
 +     *   interrupt never fired since IOMUX is currently not supported in qemu.
 +     *   Linux instead received MAC interrupts on the timer interrupt.
 +     *   As a result, qemu versions with the swapped interrupt assignment work,
 +     *   albeit accidentally, but qemu versions with the correct interrupt
 +     *   assignment fail.
 +     *
 +     * To ensure that all versions of Linux work, generate ENET_INT_MAC
 +     * interrrupts on both interrupt lines. This should be changed if and when
 +     * qemu supports IOMUX.
 +     */
-+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
++    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
-+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
++      .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
-         qemu_set_irq(s->irq[1], 1);
++      .access = PL0_R, .accessfn = access_tda,
-     } else {
++      .type = ARM_CP_CONST, .resetvalue = 0 },
-         qemu_set_irq(s->irq[1], 0);
++    /*
 +     * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
 +     * it is unlikely a guest will care.
       * We don't implement the configurable EL0 access.
       */
 -    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
 -      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
 +    { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
 +      .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
        .type = ARM_CP_ALIAS,
        .access = PL1_R, .accessfn = access_tda,
        .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
+[PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message
-From: Wei Huang <wei@redhat.com>
+From: Rebecca Cran <rebecca@nuviainc.com>
-For guest kernel that supports KASLR, the load address can change every
+Add a space in the message printed when gicr_read*/gicr_write* returns
-time when guest VM runs. To find the physical base address correctly,
+MEMTX_ERROR in arm_gicv3_redist.c.
 current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
 However this string pattern is only available on x86_64. AArch64 uses a
 different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
 QEMU dump uses the correct string on AArch64.
-Signed-off-by: Wei Huang <wei@redhat.com>
+Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
-Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
+Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- dump.c | 14 +++++++++++---
+ hw/intc/arm_gicv3_redist.c | 4 ++--
-file changed, 11 insertions(+), 3 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/dump.c b/dump.c
+diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
 index XXXXXXX..XXXXXXX 100644
---- a/dump.c
+--- a/hw/intc/arm_gicv3_redist.c
-+++ b/dump.c
++++ b/hw/intc/arm_gicv3_redist.c
-@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
+@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
+     if (r == MEMTX_ERROR) {
-     lines = g_strsplit((char *)vmci, "\n", -1);
+         qemu_log_mask(LOG_GUEST_ERROR,
-     for (i = 0; lines[i]; i++) {
+                       "%s: invalid guest read at offset " TARGET_FMT_plx
--        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
+-                      "size %u\n", __func__, offset, size);
--            if (qemu_strtou64(lines[i] + 18, NULL, 16,
++                      " size %u\n", __func__, offset, size);
-+        const char *prefix = NULL;
+         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
-+
+                                    size, attrs.secure);
-+        if (s->dump_info.d_machine == EM_X86_64) {
+         /* The spec requires that reserved registers are RAZ/WI;
-+            prefix = "NUMBER(phys_base)=";
+@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
-+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+     if (r == MEMTX_ERROR) {
-+            prefix = "NUMBER(PHYS_OFFSET)=";
+         qemu_log_mask(LOG_GUEST_ERROR,
-+        }
+                       "%s: invalid guest write at offset " TARGET_FMT_plx
-+
+-                      "size %u\n", __func__, offset, size);
-+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
++                      " size %u\n", __func__, offset, size);
-+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
+         trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
-                               &phys_base) < 0) {
+                                     size, attrs.secure);
--                warn_report("Failed to read NUMBER(phys_base)=");
+         /* The spec requires that reserved registers are RAZ/WI;
 +                warn_report("Failed to read %s", prefix);
              } else {
                  s->dump_info.phys_base = phys_base;
              }
 --
-.16.2
+.20.1

Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3

----------------------------------------------------------------
Andrey Smirnov (2):
      char: i.MX: Simplify imx_update()
      char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
      fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
      hw/arm/bcm2386: Fix parent type of bcm2386
      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
      hw/arm/bcm2836: Create proper bcm2837 device
      hw/arm/bcm2836: Use correct affinity values for BCM2837
      hw/arm/bcm2836: Hardcode correct CPU type
      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
      dump: Update correct kdump phys_base field for AArch64

From: Guenter Roeck <linux@roeck-us.net>

The sabrelite machine model used by qemu-system-arm is based on the
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
controller which is supported in QEMU using the imx_fec.c module
(actually called imx.enet for this model.)

The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
imx.enet device like this:

#define FSL_IMX6_ENET_MAC_1588_IRQ 118
 #define FSL_IMX6_ENET_MAC_IRQ 119

According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
interrupts are as follows.

150 ENET MAC 0 IRQ
151 ENET MAC 0 1588 Timer interrupt

where

150 - 32 == 118
151 - 32 == 119

In other words, the vector definitions in the fsl-imx6.h file are reversed.

Fixing the interrupts alone causes problems with older Linux kernels:
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
error handling. This is a Linux kernel problem, not a qemu problem:
the Linux kernel only worked by accident since it requested both interrupts.

For backward compatibility, generate the Ethernet interrupt on both interrupt
lines. This was shown to work from all Linux kernel releases starting with
v3.16.

Link: https://bugs.launchpad.net/qemu/+bug/1753309
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  4 ++--
 hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
 #define FSL_IMX6_HDMI_MASTER_IRQ 115
 #define FSL_IMX6_HDMI_CEC_IRQ 116
 #define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
-#define FSL_IMX6_ENET_MAC_IRQ 119
+#define FSL_IMX6_ENET_MAC_IRQ 118
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
 #define FSL_IMX6_PCIE1_IRQ 120
 #define FSL_IMX6_PCIE2_IRQ 121
 #define FSL_IMX6_PCIE3_IRQ 122
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
 
 static void imx_eth_update(IMXFECState *s)
 {
-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+    /*
+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+     * interrupts swapped. This worked with older versions of Linux (4.14
+     * and older) since Linux associated both interrupt lines with Ethernet
+     * MAC interrupts. Specifically,
+     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
+     *   timer interrupts. Those versions of Linux fail with versions of QEMU
+     *   with swapped interrupt assignments.
+     * - In linux 4.14, both interrupt lines were registered with the Ethernet
+     *   MAC interrupt handler. As a result, all versions of qemu happen to
+     *   work, though that is accidental.
+     * - In Linux 4.9 and older, the timer interrupt was registered directly
+     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
+     *   redirected to a GPIO interrupt to work around erratum ERR006687.
+     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
+     *   interrupt never fired since IOMUX is currently not supported in qemu.
+     *   Linux instead received MAC interrupts on the timer interrupt.
+     *   As a result, qemu versions with the swapped interrupt assignment work,
+     *   albeit accidentally, but qemu versions with the correct interrupt
+     *   assignment fail.
+     *
+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
+     * interrrupts on both interrupt lines. This should be changed if and when
+     * qemu supports IOMUX.
+     */
+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
         qemu_set_irq(s->irq[1], 1);
     } else {
         qemu_set_irq(s->irq[1], 0);
-- 
2.16.2

From: Wei Huang <wei@redhat.com>

For guest kernel that supports KASLR, the load address can change every
time when guest VM runs. To find the physical base address correctly,
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
However this string pattern is only available on x86_64. AArch64 uses a
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
QEMU dump uses the correct string on AArch64.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 dump.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/dump.c b/dump.c
index XXXXXXX..XXXXXXX 100644
--- a/dump.c
+++ b/dump.c
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
 
     lines = g_strsplit((char *)vmci, "\n", -1);
     for (i = 0; lines[i]; i++) {
-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+        const char *prefix = NULL;
+
+        if (s->dump_info.d_machine == EM_X86_64) {
+            prefix = "NUMBER(phys_base)=";
+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+            prefix = "NUMBER(PHYS_OFFSET)=";
+        }
+
+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
                               &phys_base) < 0) {
-                warn_report("Failed to read NUMBER(phys_base)=");
+                warn_report("Failed to read %s", prefix);
             } else {
                 s->dump_info.phys_base = phys_base;
             }
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Code of imx_update() is slightly confusing since the "flags" variable
doesn't really corespond to anything in real hardware and server as a
kitchensink accumulating events normally reported via USR1 and USR2
registers.

Change the code to explicitly evaluate state of interrupts reported
via USR1 and USR2 against corresponding masking bits and use the to
detemine if IRQ line should be asserted or not.

NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
reasons:

1. Emulation code implements a single character FIFO, so this flag
       will always be set since characters are trasmitted as a part of
       the code emulating "push" into the FIFO

2. imx_update() is really just a function doing ORing and maksing
       of reported events, so checking for UTS1_TXEMPTY should happen,
       if it's ever really needed should probably happen outside of
       it.

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/imx_serial.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
 
 static void imx_update(IMXSerialState *s)
 {
-    uint32_t flags;
+    uint32_t usr1;
+    uint32_t usr2;
+    uint32_t mask;
 
-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
-    if (s->ucr1 & UCR1_TXMPTYEN) {
-        flags |= (s->uts1 & UTS1_TXEMPTY);
-    } else {
-        flags &= ~USR1_TRDY;
-    }
+    /*
+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+     * UCR1, so we can get away with something as simple as the
+     * following:
+     */
+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+    /*
+     * Bits that we want in USR2 are not as conveniently laid out,
+     * unfortunately.
+     */
+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    usr2 = s->usr2 & mask;
 
-    qemu_set_irq(s->irq, !!flags);
+    qemu_set_irq(s->irq, usr1 || usr2);
 }
 
 static void imx_serial_reset(IMXSerialState *s)
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.

Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/imx_serial.h |  3 +++
 hw/char/imx_serial.c         | 20 +++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -XXX,XX +XXX,XX @@
 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
 #define UCR2_SRST       (1<<0)    /* Reset complete */
 
+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+
 #define UTS1_TXEMPTY    (1<<6)
 #define UTS1_RXEMPTY    (1<<5)
 #define UTS1_TXFULL     (1<<4)
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
     uint32_t ubmr;
     uint32_t ubrc;
     uint32_t ucr3;
+    uint32_t ucr4;
 
     qemu_irq irq;
     CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
 
 static const VMStateDescription vmstate_imx_serial = {
     .name = TYPE_IMX_SERIAL,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_INT32(readbuff, IMXSerialState),
         VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
         VMSTATE_UINT32(ubmr, IMXSerialState),
         VMSTATE_UINT32(ubrc, IMXSerialState),
         VMSTATE_UINT32(ucr3, IMXSerialState),
+        VMSTATE_UINT32(ucr4, IMXSerialState),
         VMSTATE_END_OF_LIST()
     },
 };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
      * unfortunately.
      */
     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    /*
+     * TCEN and TXDC are both bit 3
+     */
+    mask |= s->ucr4 & UCR4_TCEN;
+
     usr2 = s->usr2 & mask;
 
     qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
         return s->ucr3;
 
     case 0x23: /* UCR4 */
+        return s->ucr4;
+
     case 0x29: /* BRM Incremental */
         return 0x0; /* TODO */
 
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
              * qemu_chr_fe_write and background I/O callbacks */
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->usr1 &= ~USR1_TRDY;
+            s->usr2 &= ~USR2_TXDC;
             imx_update(s);
             s->usr1 |= USR1_TRDY;
+            s->usr2 |= USR2_TXDC;
             imx_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
         s->ucr3 = value & 0xffff;
         break;
 
-    case 0x2d: /* UTS1 */
     case 0x23: /* UCR4 */
+        s->ucr4 = value & 0xffff;
+        imx_update(s);
+        break;
+
+    case 0x2d: /* UTS1 */
         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
         /* TODO */
-- 
2.16.2

For the rpi1 and 2 we want to boot the Linux kernel via some
custom setup code that makes sure that the SMC instruction
acts as a no-op, because it's used for cache maintenance.
The rpi3 boots AArch64 kernels, which don't need SMC for
cache maintenance and always expect to be booted non-secure.
Don't fill in the aarch32-specific parts of the binfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     binfo.board_id = raspi_boardid[version];
     binfo.ram_size = ram_size;
     binfo.nb_cpus = smp_cpus;
-    binfo.board_setup_addr = BOARDSETUP_ADDR;
-    binfo.write_board_setup = write_board_setup;
-    binfo.secure_board_setup = true;
-    binfo.secure_boot = true;
+
+    if (version <= 2) {
+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         * mode before booting a kernel (to set up the SMC vectors so
+         * that we get a no-op SMC; this is used by Linux to call the
+         * firmware for some cache maintenance operations.
+         * The rpi3 doesn't need this.
+         */
+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+        binfo.write_board_setup = write_board_setup;
+        binfo.secure_board_setup = true;
+        binfo.secure_boot = true;
+    }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-- 
2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,
the board code has not mistakenly set either secure_boot or
secure_board_setup. It doesn't make sense to set secure_boot,
because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but
we don't currently support that, because only the AArch32
bootloader[] code calls this hook; bootloader_aarch64[] does not.
Since we don't have a current need for this functionality, just
assert that we don't try to use it. If it's needed we'll add
it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     } else {
                         env->pstate = PSTATE_MODE_EL1h;
                     }
+                    /* AArch64 kernels never boot in secure mode */
+                    assert(!info->secure_boot);
+                    /* This hook is only supported for AArch32 currently:
+                     * bootloader_aarch64[] will not call the hook, and
+                     * the code above has already dropped us into EL2 or EL1.
+                     */
+                    assert(!info->secure_board_setup);
                 }
 
                 /* Set to non-secure if not a secure boot */
-- 
2.16.2

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

The TypeInfo and state struct for bcm2386 disagree about what the
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
but the BCM2386State struct only defines the parent_obj field
as DeviceState. This would have caused problems if anything
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
need any of the additional functionality TYPE_SYS_BUS_DEVICE
provides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo bcm2836_type_info = {
     .name = TYPE_BCM2836,
-    .parent = TYPE_SYS_BUS_DEVICE,
+    .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM2836State),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
-- 
2.16.2

Our BCM2836 type is really a generic one that can be any of
the bcm283x family. Rename it accordingly. We change only
the names which are visible via the header file to the
rest of the QEMU code, leaving private function names
in bcm2836.c as they are.

This is a preliminary to making bcm283x be an abstract
parent class to specific types for the bcm2836 and bcm2837.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 12 ++++++------
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           | 16 ++++++++--------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
-#define TYPE_BCM2836 "bcm2836"
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+#define TYPE_BCM283X "bcm283x"
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 
-#define BCM2836_NCPUS 4
+#define BCM283X_NCPUS 4
 
-typedef struct BCM2836State {
+typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
     char *cpu_type;
     uint32_t enabled_cpus;
 
-    ARMCPU cpus[BCM2836_NCPUS];
+    ARMCPU cpus[BCM283X_NCPUS];
     BCM2836ControlState control;
     BCM2835PeripheralState peripherals;
-} BCM2836State;
+} BCM283XState;
 
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 static void bcm2836_init(Object *obj)
 {
-    BCM2836State *s = BCM2836(obj);
+    BCM283XState *s = BCM283X(obj);
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
 
 static void bcm2836_realize(DeviceState *dev, Error **errp)
 {
-    BCM2836State *s = BCM2836(dev);
+    BCM283XState *s = BCM283X(dev);
     Object *obj;
     Error *err = NULL;
     int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     /* common peripherals from bcm2835 */
 
     obj = OBJECT(dev);
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                           s->cpu_type);
         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         /* Mirror bcm2836, which has clusterid set to 0xf
          * TODO: this should be converted to a property of ARM_CPU
          */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                       BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 }
 
 static const TypeInfo bcm2836_type_info = {
-    .name = TYPE_BCM2836,
+    .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
-    .instance_size = sizeof(BCM2836State),
+    .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
 
 typedef struct RasPiState {
-    BCM2836State soc;
+    BCM283XState soc;
     MemoryRegion ram;
 } RasPiState;
 
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
 }
 DEFINE_MACHINE("raspi3", raspi3_machine_init)
-- 
2.16.2

The bcm2837 is pretty similar to the bcm2836, but it does have
some differences. Notably, the MPIDR affinity aff1 values it
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
uses, and if this is wrong Linux will not boot.

Rather than trying to have one device with properties that
configure it differently for the two cases, create two
separate QOM devices for the two SoCs. We use the same approach
as hw/arm/aspeed_soc.c and share code and have a data table
that might differ per-SoC. For the moment the two types don't
actually have different behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
 hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
 hw/arm/raspi.c           |  3 ++-
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 
 #define BCM283X_NCPUS 4
 
+/* These type names are for specific SoCs; other than instantiating
+ * them, code using these devices should always handle them via the
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ */
+#define TYPE_BCM2836 "bcm2836"
+#define TYPE_BCM2837 "bcm2837"
+
 typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
     BCM2835PeripheralState peripherals;
 } BCM283XState;
 
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+    DeviceClass parent_class;
+    const BCM283XInfo *info;
+} BCM283XClass;
+
+#define BCM283X_CLASS(klass) \
+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
 #define BCM2836_CONTROL_BASE    0x40000000
 
+struct BCM283XInfo {
+    const char *name;
+};
+
+static const BCM283XInfo bcm283x_socs[] = {
+    {
+        .name = TYPE_BCM2836,
+    },
+    {
+        .name = TYPE_BCM2837,
+    },
+};
+
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void bcm2836_class_init(ObjectClass *oc, void *data)
+static void bcm283x_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
+    BCM283XClass *bc = BCM283X_CLASS(oc);
 
-    dc->props = bcm2836_props;
+    bc->info = data;
     dc->realize = bcm2836_realize;
+    dc->props = bcm2836_props;
 }
 
-static const TypeInfo bcm2836_type_info = {
+static const TypeInfo bcm283x_type_info = {
     .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
-    .class_init = bcm2836_class_init,
+    .class_size = sizeof(BCM283XClass),
+    .abstract = true,
 };
 
 static void bcm2836_register_types(void)
 {
-    type_register_static(&bcm2836_type_info);
+    int i;
+
+    type_register_static(&bcm283x_type_info);
+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+        TypeInfo ti = {
+            .name = bcm283x_socs[i].name,
+            .parent = TYPE_BCM283X,
+            .class_init = bcm283x_class_init,
+            .class_data = (void *) &bcm283x_socs[i],
+        };
+        type_register(&ti);
+    }
 }
 
 type_init(bcm2836_register_types)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+    object_initialize(&s->soc, sizeof(s->soc),
+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
-- 
2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
is required for Linux to boot.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Now we have separate types for BCM2386 and BCM2387, we might as well
just hard-code the CPU type they use rather than having it passed
through as an object property. This then lets us put the initialization
of the CPU object in init rather than realize.

Note that this change means that it's no longer possible on
the command line to use -cpu to ask for a different kind of
CPU than the SoC supports. This was never a supported thing to
do anyway; we were just not sanity-checking the command line.

This does require us to only build the bcm2837 object on
TARGET_AARCH64 configs, since otherwise it won't instantiate
due to the missing cortex-a53 device and "make check" will fail.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 24 +++++++++++++++---------
 hw/arm/raspi.c   |  2 --
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 struct BCM283XInfo {
     const char *name;
+    const char *cpu_type;
     int clusterid;
 };
 
 static const BCM283XInfo bcm283x_socs[] = {
     {
         .name = TYPE_BCM2836,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
         .clusterid = 0xf,
     },
+#ifdef TARGET_AARCH64
     {
         .name = TYPE_BCM2837,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
         .clusterid = 0x0,
     },
+#endif
 };
 
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+    const BCM283XInfo *info = bc->info;
+    int n;
+
+    for (n = 0; n < BCM283X_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          info->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
-    obj = OBJECT(dev);
-    for (n = 0; n < BCM283X_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          s->cpu_type);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
-
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                        BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
-                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
-- 
2.16.2

The raspi3 has AArch64 CPUs, which means that our smpboot
code for keeping the secondary CPUs in a pen needs to have
a version for A64 as well as A32. Without this, the
secondary CPUs go into an infinite loop of taking undefined
instruction exceptions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
 
 /* Table of Linux board IDs for different Pi versions */
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                        info->smp_loader_start);
 }
 
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+     * The mechanism for doing the spin-table is also entirely different.
+     * We must have four 64-bit fields at absolute addresses
+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+     * our CPUs, and which we must ensure are zero initialized before
+     * the primary CPU goes into the kernel. We put these variables inside
+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+     */
+    static const uint32_t smpboot[] = {
+        0xd2801b05, /*        mov     x5, 0xd8 */
+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+        0x924004c6, /*        and     x6, x6, #0x3 */
+        0xd503205f, /* spin:  wfe */
+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+        0xb4ffffc4, /*        cbz     x4, spin */
+        0xd2800000, /*        mov     x0, #0x0 */
+        0xd2800001, /*        mov     x1, #0x0 */
+        0xd2800002, /*        mov     x2, #0x0 */
+        0xd2800003, /*        mov     x3, #0x0 */
+        0xd61f0080, /*        br      x4 */
+    };
+
+    static const uint64_t spintables[] = {
+        0, 0, 0, 0
+    };
+
+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
+                       info->smp_loader_start);
+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+                       SPINTABLE_ADDR);
+}
+
 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
         binfo.smp_loader_start = SMPBOOT_ADDR;
-        binfo.write_secondary_boot = write_smpboot;
+        if (version == 2) {
+            binfo.write_secondary_boot = write_smpboot;
+        } else {
+            binfo.write_secondary_boot = write_smpboot64;
+        }
         binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
-- 
2.16.2

Arm changes for before softfreeze: mostly my PL061/GPIO patches,
but also a new M-profile board and various other things.

thanks
-- PMM

The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709

for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:

hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)

----------------------------------------------------------------
target-arm queue:
 * New machine type: stm32vldiscovery
 * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
 * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
 * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
 * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
 * hw/intc: Improve formatting of MEMTX_ERROR guest error message

----------------------------------------------------------------
Alexandre Iooss (4):
      stm32f100: Add the stm32f100 SoC
      stm32vldiscovery: Add the STM32VLDISCOVERY Machine
      docs/system: arm: Add stm32 boards description
      tests/boot-serial-test: Add STM32VLDISCOVERY board testcase

Peter Maydell (10):
      hw/gpio/pl061: Convert DPRINTF to tracepoints
      hw/gpio/pl061: Clean up read/write offset handling logic
      hw/gpio/pl061: Add tracepoints for register read and write
      hw/gpio/pl061: Document the interface of this device
      hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
      hw/gpio/pl061: Make pullup/pulldown of outputs configurable
      hw/arm/virt: Make PL061 GPIO lines pulled low, not high
      hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
      hw/gpio/pl061: Document a shortcoming in our implementation
      hw/arm/stellaris: Expand comment about handling of OLED chipselect

Rebecca Cran (1):
      hw/intc: Improve formatting of MEMTX_ERROR guest error message

Ricardo Koller (1):
      hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

hnick@vmware.com (1):
      target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint

docs/system/arm/stm32.rst               |  66 +++++++
 docs/system/target-arm.rst              |   1 +
 default-configs/devices/arm-softmmu.mak |   1 +
 include/hw/arm/stm32f100_soc.h          |  57 ++++++
 hw/arm/stellaris.c                      |  56 +++++-
 hw/arm/stm32f100_soc.c                  | 182 +++++++++++++++++
 hw/arm/stm32vldiscovery.c               |  66 +++++++
 hw/arm/virt.c                           |   3 +
 hw/gpio/pl061.c                         | 341 +++++++++++++++++++++++++-------
 hw/intc/arm_gicv3_cpuif.c               |   4 +-
 hw/intc/arm_gicv3_redist.c              |   4 +-
 target/arm/helper.c                     |  16 +-
 tests/qtest/boot-serial-test.c          |  37 ++++
 MAINTAINERS                             |  13 ++
 hw/arm/Kconfig                          |  10 +
 hw/arm/meson.build                      |   2 +
 hw/gpio/trace-events                    |   9 +
 17 files changed, 790 insertions(+), 78 deletions(-)
 create mode 100644 docs/system/arm/stm32.rst
 create mode 100644 include/hw/arm/stm32f100_soc.h
 create mode 100644 hw/arm/stm32f100_soc.c
 create mode 100644 hw/arm/stm32vldiscovery.c

From: Alexandre Iooss <erdnaxe@crans.org>

This SoC is similar to stm32f205 SoC.
This will be used by the STM32VLDISCOVERY to create a machine.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/stm32f100_soc.h |  57 +++++++++++
 hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
 MAINTAINERS                    |   6 ++
 hw/arm/Kconfig                 |   6 ++
 hw/arm/meson.build             |   1 +
 5 files changed, 252 insertions(+)
 create mode 100644 include/hw/arm/stm32f100_soc.h
 create mode 100644 hw/arm/stm32f100_soc.c

diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/stm32f100_soc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_STM32F100_SOC_H
+#define HW_ARM_STM32F100_SOC_H
+
+#include "hw/char/stm32f2xx_usart.h"
+#include "hw/ssi/stm32f2xx_spi.h"
+#include "hw/arm/armv7m.h"
+#include "qom/object.h"
+
+#define TYPE_STM32F100_SOC "stm32f100-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
+
+#define STM_NUM_USARTS 3
+#define STM_NUM_SPIS 2
+
+#define FLASH_BASE_ADDRESS 0x08000000
+#define FLASH_SIZE (128 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (8 * 1024)
+
+struct STM32F100State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    char *cpu_type;
+
+    ARMv7MState armv7m;
+
+    STM32F2XXUsartState usart[STM_NUM_USARTS];
+    STM32F2XXSPIState spi[STM_NUM_SPIS];
+};
+
+#endif
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32f100_soc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+
+/* stm32f100_soc implementation is derived from stm32f205_soc */
+
+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
+    0x40004800 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
+
+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
+static const int spi_irq[STM_NUM_SPIS] = {35, 36};
+
+static void stm32f100_soc_initfn(Object *obj)
+{
+    STM32F100State *s = STM32F100_SOC(obj);
+    int i;
+
+    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        object_initialize_child(obj, "usart[*]", &s->usart[i],
+                                TYPE_STM32F2XX_USART);
+    }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
+    }
+}
+
+static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    STM32F100State *s = STM32F100_SOC(dev_soc);
+    DeviceState *dev, *armv7m;
+    SysBusDevice *busdev;
+    int i;
+
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *sram = g_new(MemoryRegion, 1);
+    MemoryRegion *flash = g_new(MemoryRegion, 1);
+    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+    /*
+     * Init flash region
+     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
+     */
+    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
+                           FLASH_SIZE, &error_fatal);
+    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
+                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
+    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+    memory_region_add_subregion(system_memory, 0, flash_alias);
+
+    /* Init SRAM region */
+    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+    /* Init ARMv7m */
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 61);
+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+    qdev_prop_set_bit(armv7m, "enable-bitband", true);
+    object_property_set_link(OBJECT(&s->armv7m), "memory",
+                             OBJECT(get_system_memory()), &error_abort);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
+        return;
+    }
+
+    /* Attach UART (uses USART registers) and USART controllers */
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        dev = DEVICE(&(s->usart[i]));
+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+    }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
+    }
+
+    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
+    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
+    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
+    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
+    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
+    create_unimplemented_device("RTC",       0x40002800, 0x400);
+    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
+    create_unimplemented_device("IWDG",      0x40003000, 0x400);
+    create_unimplemented_device("I2C1",      0x40005400, 0x400);
+    create_unimplemented_device("I2C2",      0x40005800, 0x400);
+    create_unimplemented_device("BKP",       0x40006C00, 0x400);
+    create_unimplemented_device("PWR",       0x40007000, 0x400);
+    create_unimplemented_device("DAC",       0x40007400, 0x400);
+    create_unimplemented_device("CEC",       0x40007800, 0x400);
+    create_unimplemented_device("AFIO",      0x40010000, 0x400);
+    create_unimplemented_device("EXTI",      0x40010400, 0x400);
+    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
+    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
+    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
+    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
+    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
+    create_unimplemented_device("ADC1",      0x40012400, 0x400);
+    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
+    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
+    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
+    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
+    create_unimplemented_device("DMA",       0x40020000, 0x400);
+    create_unimplemented_device("RCC",       0x40021000, 0x400);
+    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
+    create_unimplemented_device("CRC",       0x40023000, 0x400);
+}
+
+static Property stm32f100_soc_properties[] = {
+    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = stm32f100_soc_realize;
+    device_class_set_props(dc, stm32f100_soc_properties);
+}
+
+static const TypeInfo stm32f100_soc_info = {
+    .name          = TYPE_STM32F100_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F100State),
+    .instance_init = stm32f100_soc_initfn,
+    .class_init    = stm32f100_soc_class_init,
+};
+
+static void stm32f100_soc_types(void)
+{
+    type_register_static(&stm32f100_soc_info);
+}
+
+type_init(stm32f100_soc_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/virt-acpi-build.c
 
+STM32F100
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32f100_soc.c
+
 STM32F205
 M: Alistair Francis <alistair@alistair23.me>
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config RASPI
     select SDHCI
     select USB_DWC2
 
+config STM32F100_SOC
+    bool
+    select ARM_V7M
+    select STM32F2XX_USART
+    select STM32F2XX_SPI
+
 config STM32F205_SOC
     bool
     select ARM_V7M
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
+arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This is a Cortex-M3 based machine. Information can be found at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 default-configs/devices/arm-softmmu.mak |  1 +
 hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
 MAINTAINERS                             |  6 +++
 hw/arm/Kconfig                          |  4 ++
 hw/arm/meson.build                      |  1 +
 5 files changed, 78 insertions(+)
 create mode 100644 hw/arm/stm32vldiscovery.c

diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_CHEETAH=y
 CONFIG_SX1=y
 CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
+CONFIG_STM32VLDISCOVERY=y
 CONFIG_REALVIEW=y
 CONFIG_VERSATILE=y
 CONFIG_VEXPRESS=y
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32vldiscovery.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ST STM32VLDISCOVERY machine
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/arm/boot.h"
+
+/* stm32vldiscovery implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (24MHz) */
+#define SYSCLK_FRQ 24000000ULL
+
+static void stm32vldiscovery_init(MachineState *machine)
+{
+    DeviceState *dev;
+
+    /*
+     * TODO: ideally we would model the SoC RCC and let it handle
+     * system_clock_scale, including its ability to define different
+     * possible SYSCLK sources.
+     */
+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+
+    dev = qdev_new(TYPE_STM32F100_SOC);
+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    armv7m_load_kernel(ARM_CPU(first_cpu),
+                       machine->kernel_filename,
+                       FLASH_SIZE);
+}
+
+static void stm32vldiscovery_machine_init(MachineClass *mc)
+{
+    mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
+    mc->init = stm32vldiscovery_init;
+}
+
+DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/*/stellaris*
 F: include/hw/input/gamepad.h
 F: docs/system/arm/stellaris.rst
 
+STM32VLDISCOVERY
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32vldiscovery.c
+
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config STELLARIS
     select STELLARIS_ENET # ethernet
     select UNIMP
 
+config STM32VLDISCOVERY
+    bool
+    select STM32F100_SOC
+
 config STRONGARM
     bool
     select PXA2XX
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
+arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/stm32.rst  | 66 ++++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst |  1 +
 MAINTAINERS                |  1 +
 3 files changed, 68 insertions(+)
 create mode 100644 docs/system/arm/stm32.rst

diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/stm32.rst
@@ -XXX,XX +XXX,XX @@
+STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
+========================================================================================
+
+The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
+STMicroelectronics.
+
+.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
+
+The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
+based on this chip :
+
+- ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
+
+The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
+based on this chip :
+
+- ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller
+
+The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
+compatible with STM32F2 series. The following machines are based on this chip :
+
+- ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
+
+There are many other STM32 series that are currently not supported by QEMU.
+
+Supported devices
+-----------------
+
+ * ARM Cortex-M3, Cortex M4F
+ * Analog to Digital Converter (ADC)
+ * EXTI interrupt
+ * Serial ports (USART)
+ * SPI controller
+ * System configuration (SYSCFG)
+ * Timer controller (TIMER)
+
+Missing devices
+---------------
+
+ * Camera interface (DCMI)
+ * Controller Area Network (CAN)
+ * Cycle Redundancy Check (CRC) calculation unit
+ * Digital to Analog Converter (DAC)
+ * DMA controller
+ * Ethernet controller
+ * Flash Interface Unit
+ * GPIO controller
+ * I2C controller
+ * Inter-Integrated Sound (I2S) controller
+ * Power supply configuration (PWR)
+ * Random Number Generator (RNG)
+ * Real-Time Clock (RTC) controller
+ * Reset and Clock Controller (RCC)
+ * Secure Digital Input/Output (SDIO) interface
+ * USB OTG
+ * Watchdog controller (IWDG, WWDG)
+
+Boot options
+------------
+
+The STM32 machines can be started using the ``-kernel`` option to load a
+firmware. Example:
+
+.. code-block:: bash
+
+  $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/collie
    arm/sx1
    arm/stellaris
+   arm/stm32
    arm/virt
    arm/xlnx-versal-virt
 
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Alexandre Iooss <erdnaxe@crans.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/stm32vldiscovery.c
+F: docs/system/arm/stm32.rst
 
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

New mini-kernel test for STM32VLDISCOVERY USART1.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_nrf51[] = {
     0x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
 };
 
+static const uint8_t kernel_stm32vldiscovery[] = {
+    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
+    0x1d, 0x00, 0x00, 0x00,                 /* Reset handler address */
+    0x00, 0x00, 0x00, 0x00,                 /* NMI */
+    0x00, 0x00, 0x00, 0x00,                 /* Hard fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Memory management fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Bus fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Usage fault */
+    0x0b, 0x4b,                             /* ldr  r3, [pc, #44] Get RCC */
+    0x44, 0xf2, 0x04, 0x02,                 /* movw r2, #16388 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x0a, 0x4b,                             /* ldr  r3, [pc, #40] Get GPIOA */
+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+    0x22, 0xf0, 0xf0, 0x02,                 /* bic  r2, r2, #240 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+    0x42, 0xf0, 0xb0, 0x02,                 /* orr  r2, r2, #176 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x07, 0x4b,                             /* ldr  r3, [pc, #26] Get BAUD */
+    0x45, 0x22,                             /* movs r2, #69 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x06, 0x4b,                             /* ldr  r3, [pc, #24] Get ENABLE */
+    0x42, 0xf2, 0x08, 0x02,                 /* movw r2, #8200 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x05, 0x4b,                             /* ldr  r3, [pc, #20] Get TXD */
+    0x54, 0x22,                             /* movs r2, 'T' */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0xfe, 0xe7,                             /* b    . */
+    0x18, 0x10, 0x02, 0x40,                 /* 0x40021018 = RCC */
+    0x04, 0x08, 0x01, 0x40,                 /* 0x40010804 = GPIOA */
+    0x08, 0x38, 0x01, 0x40,                 /* 0x40013808 = USART1 BAUD */
+    0x0c, 0x38, 0x01, 0x40,                 /* 0x4001380c = USART1 ENABLE */
+    0x04, 0x38, 0x01, 0x40                  /* 0x40013804 = USART1 TXD */
+};
+
 typedef struct testdef {
     const char *arch;       /* Target architecture */
     const char *machine;    /* Name of the machine */
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
     { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
       kernel_aarch64 },
     { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
+    { "arm", "stm32vldiscovery", "", "T",
+      sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
 
     { NULL }
 };
-- 
2.20.1

From: Ricardo Koller <ricarkol@google.com>

icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs).  The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1).  The consequence is that
if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
guest is unable to deactivate the resulting IRQ. Note that other
functions that deal with large IRQ numbers, like icv_iar_read, check
against 1020 and not against num_irq.

Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
implemented IRQs.

Signed-off-by: Ricardo Koller <ricarkol@google.com>
Message-id: 20210702233701.3369-1-ricarkol@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
 
-    if (irq >= cs->gic->num_irq) {
+    if (irq >= GICV3_MAXIRQ) {
         /* Also catches special interrupt numbers and LPIs */
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
                                gicv3_redist_affid(cs), value);
 
-    if (irq >= cs->gic->num_irq) {
+    if (irq >= GICV3_MAXIRQ) {
         /* Also catches special interrupt numbers and LPIs */
         return;
     }
-- 
2.20.1

Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 27 +++++++++------------------
 hw/gpio/trace-events |  6 ++++++
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
-
-//#define DEBUG_PL061 1
-
-#ifdef DEBUG_PL061
-#define DPRINTF(fmt, ...) \
-do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while(0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
-#endif
+#include "trace.h"
 
 static const uint8_t pl061_id[12] =
   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
     uint8_t out;
     int i;
 
-    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
 
     /* Outputs float high.  */
     /* FIXME: This is board dependent.  */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
         for (i = 0; i < N_GPIOS; i++) {
             mask = 1 << i;
             if (changed & mask) {
-                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
-                qemu_set_irq(s->out[i], (out & mask) != 0);
+                int level = (out & mask) != 0;
+                trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+                qemu_set_irq(s->out[i], level);
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
         for (i = 0; i < N_GPIOS; i++) {
             mask = 1 << i;
             if (changed & mask) {
-                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
+                trace_pl061_input_change(DEVICE(s)->canonical_path, i,
+                                         (s->data & mask) != 0);
 
                 if (!(s->isense & mask)) {
                     /* Edge interrupt */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
     /* Level interrupt */
     s->istate |= ~(s->data ^ s->iev) & s->isense;
 
-    DPRINTF("istate = %02X\n", s->istate);
+    trace_pl061_update_istate(DEVICE(s)->canonical_path,
+                              s->istate, s->im, (s->istate & s->im) != 0);
 
     qemu_set_irq(s->irq, (s->istate & s->im) != 0);
 }
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x
 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 
+# pl061.c
+pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
+pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
+pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
+pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

Currently the pl061_read() and pl061_write() functions handle offsets
using a combination of three if() statements and a switch().  Clean
this up to use just a switch, using case ranges.

This requires that instead of catching accesses to the luminary-only
registers on a stock PL061 via a check on s->rsvd_start we use
an "is this luminary?" check in the cases for each luminary-only
register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------
 1 file changed, 79 insertions(+), 25 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ struct PL061State {
     qemu_irq irq;
     qemu_irq out[N_GPIOS];
     const unsigned char *id;
-    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
 };
 
 static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
 {
     PL061State *s = (PL061State *)opaque;
 
-    if (offset < 0x400) {
-        return s->data & (offset >> 2);
-    }
-    if (offset >= s->rsvd_start && offset <= 0xfcc) {
-        goto err_out;
-    }
-    if (offset >= 0xfd0 && offset < 0x1000) {
-        return s->id[(offset - 0xfd0) >> 2];
-    }
     switch (offset) {
+    case 0x0 ... 0x3ff: /* Data */
+        return s->data & (offset >> 2);
     case 0x400: /* Direction */
         return s->dir;
     case 0x404: /* Interrupt sense */
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
     case 0x420: /* Alternate function select */
         return s->afsel;
     case 0x500: /* 2mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr2r;
     case 0x504: /* 4mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr4r;
     case 0x508: /* 8mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr8r;
     case 0x50c: /* Open drain */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->odr;
     case 0x510: /* Pull-up */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->pur;
     case 0x514: /* Pull-down */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->pdr;
     case 0x518: /* Slew rate control */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->slr;
     case 0x51c: /* Digital enable */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->den;
     case 0x520: /* Lock */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->locked;
     case 0x524: /* Commit */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->cr;
     case 0x528: /* Analog mode select */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->amsel;
+    case 0xfd0 ... 0xfff: /* ID registers */
+        return s->id[(offset - 0xfd0) >> 2];
     default:
+    bad_offset:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pl061_read: Bad offset %x\n", (int)offset);
         break;
     }
-err_out:
-    qemu_log_mask(LOG_GUEST_ERROR,
-                  "pl061_read: Bad offset %x\n", (int)offset);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     PL061State *s = (PL061State *)opaque;
     uint8_t mask;
 
-    if (offset < 0x400) {
+    switch (offset) {
+    case 0 ... 0x3ff:
         mask = (offset >> 2) & s->dir;
         s->data = (s->data & ~mask) | (value & mask);
         pl061_update(s);
         return;
-    }
-    if (offset >= s->rsvd_start) {
-        goto err_out;
-    }
-    switch (offset) {
     case 0x400: /* Direction */
         s->dir = value & 0xff;
         break;
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
         s->afsel = (s->afsel & ~mask) | (value & mask);
         break;
     case 0x500: /* 2mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr2r = value & 0xff;
         break;
     case 0x504: /* 4mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr4r = value & 0xff;
         break;
     case 0x508: /* 8mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr8r = value & 0xff;
         break;
     case 0x50c: /* Open drain */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->odr = value & 0xff;
         break;
     case 0x510: /* Pull-up */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->pur = value & 0xff;
         break;
     case 0x514: /* Pull-down */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->pdr = value & 0xff;
         break;
     case 0x518: /* Slew rate control */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->slr = value & 0xff;
         break;
     case 0x51c: /* Digital enable */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->den = value & 0xff;
         break;
     case 0x520: /* Lock */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->locked = (value != 0xacce551);
         break;
     case 0x524: /* Commit */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         if (!s->locked)
             s->cr = value & 0xff;
         break;
     case 0x528:
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->amsel = value & 0xff;
         break;
     default:
-        goto err_out;
+    bad_offset:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pl061_write: Bad offset %x\n", (int)offset);
+        return;
     }
     pl061_update(s);
     return;
-err_out:
-    qemu_log_mask(LOG_GUEST_ERROR,
-                  "pl061_write: Bad offset %x\n", (int)offset);
 }
 
 static void pl061_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)
     PL061State *s = PL061(obj);
 
     s->id = pl061_id_luminary;
-    s->rsvd_start = 0x52c;
 }
 
 static void pl061_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     s->id = pl061_id;
-    s->rsvd_start = 0x424;
 
     memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
-- 
2.20.1

Add tracepoints for reads and writes to the PL061 registers. This requires
restructuring pl061_read() to only return after the tracepoint, rather
than having lots of early-returns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 70 ++++++++++++++++++++++++++++++--------------
 hw/gpio/trace-events |  2 ++
 2 files changed, 50 insertions(+), 22 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
     PL061State *s = (PL061State *)opaque;
+    uint64_t r = 0;
 
     switch (offset) {
     case 0x0 ... 0x3ff: /* Data */
-        return s->data & (offset >> 2);
+        r = s->data & (offset >> 2);
+        break;
     case 0x400: /* Direction */
-        return s->dir;
+        r = s->dir;
+        break;
     case 0x404: /* Interrupt sense */
-        return s->isense;
+        r = s->isense;
+        break;
     case 0x408: /* Interrupt both edges */
-        return s->ibe;
+        r = s->ibe;
+        break;
     case 0x40c: /* Interrupt event */
-        return s->iev;
+        r = s->iev;
+        break;
     case 0x410: /* Interrupt mask */
-        return s->im;
+        r = s->im;
+        break;
     case 0x414: /* Raw interrupt status */
-        return s->istate;
+        r = s->istate;
+        break;
     case 0x418: /* Masked interrupt status */
-        return s->istate & s->im;
+        r = s->istate & s->im;
+        break;
     case 0x420: /* Alternate function select */
-        return s->afsel;
+        r = s->afsel;
+        break;
     case 0x500: /* 2mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr2r;
+        r = s->dr2r;
+        break;
     case 0x504: /* 4mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr4r;
+        r = s->dr4r;
+        break;
     case 0x508: /* 8mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr8r;
+        r = s->dr8r;
+        break;
     case 0x50c: /* Open drain */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->odr;
+        r = s->odr;
+        break;
     case 0x510: /* Pull-up */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->pur;
+        r = s->pur;
+        break;
     case 0x514: /* Pull-down */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->pdr;
+        r = s->pdr;
+        break;
     case 0x518: /* Slew rate control */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->slr;
+        r = s->slr;
+        break;
     case 0x51c: /* Digital enable */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->den;
+        r = s->den;
+        break;
     case 0x520: /* Lock */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->locked;
+        r = s->locked;
+        break;
     case 0x524: /* Commit */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->cr;
+        r = s->cr;
+        break;
     case 0x528: /* Analog mode select */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->amsel;
+        r = s->amsel;
+        break;
     case 0xfd0 ... 0xfff: /* ID registers */
-        return s->id[(offset - 0xfd0) >> 2];
+        r = s->id[(offset - 0xfd0) >> 2];
+        break;
     default:
     bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "pl061_read: Bad offset %x\n", (int)offset);
         break;
     }
-    return 0;
+
+    trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
+    return r;
 }
 
 static void pl061_write(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     PL061State *s = (PL061State *)opaque;
     uint8_t mask;
 
+    trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
+
     switch (offset) {
     case 0 ... 0x3ff:
         mask = (offset >> 2) & s->dir;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
which lets the guest configure whether the GPIO lines are pull-up,
pull-down, or truly floating. Instead of assuming all lines are pulled
high, honour the PUR and PDR registers.

For the plain PL061, continue to assume that lines have an external
pull-up resistor, as we did before.

The stellaris board actually relies on this behaviour -- the CD line
of the ssd0323 display device is connected to GPIO output C7, and it
is only because of a different bug which we're about to fix that we
weren't incorrectly driving this line high on reset and putting the
ssd0323 into data mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 58 +++++++++++++++++++++++++++++++++++++++++---
 hw/gpio/trace-events |  2 +-
 2 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {
     }
 };
 
+static uint8_t pl061_floating(PL061State *s)
+{
+    /*
+     * Return mask of bits which correspond to pins configured as inputs
+     * and which are floating (neither pulled up to 1 nor down to 0).
+     */
+    uint8_t floating;
+
+    if (s->id == pl061_id_luminary) {
+        /*
+         * If both PUR and PDR bits are clear, there is neither a pullup
+         * nor a pulldown in place, and the output truly floats.
+         */
+        floating = ~(s->pur | s->pdr);
+    } else {
+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
+        floating = 0;
+    }
+    return floating & ~s->dir;
+}
+
+static uint8_t pl061_pullups(PL061State *s)
+{
+    /*
+     * Return mask of bits which correspond to pins configured as inputs
+     * and which are pulled up to 1.
+     */
+    uint8_t pullups;
+
+    if (s->id == pl061_id_luminary) {
+        /*
+         * The Luminary variant of the PL061 has an extra registers which
+         * the guest can use to configure whether lines should be pullup
+         * or pulldown.
+         */
+        pullups = s->pur;
+    } else {
+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
+        pullups = 0xff;
+    }
+    return pullups & ~s->dir;
+}
+
 static void pl061_update(PL061State *s)
 {
     uint8_t changed;
     uint8_t mask;
     uint8_t out;
     int i;
+    uint8_t pullups = pl061_pullups(s);
+    uint8_t floating = pl061_floating(s);
 
-    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,
+                       pullups, floating);
 
-    /* Outputs float high.  */
-    /* FIXME: This is board dependent.  */
-    out = (s->data & s->dir) | ~s->dir;
+    /*
+     * Pins configured as output are driven from the data register;
+     * otherwise if they're pulled up they're 1, and if they're floating
+     * then we give them the same value they had previously, so we don't
+     * report any change to the other end.
+     */
+    out = (s->data & s->dir) | pullups | (s->old_out_data & floating);
     changed = s->old_out_data ^ out;
     if (changed) {
         s->old_out_data = out;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 
 # pl061.c
-pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
+pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"
 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
-- 
2.20.1

The PL061 GPIO does not itself include pullup or pulldown resistors
to set the value of a GPIO line treated as an output when it is
configured as an input (ie when the PL061 itself is not driving it).
In real hardware it is up to the board to add suitable pullups or
pulldowns.  Currently our implementation hardwires this to "outputs
pulled high", which is correct for some boards (eg the realview ones:
see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
User Guide" DUI0224I), but wrong for others.

In particular, the wiring in the 'virt' board and the gpio-pwr device
assumes that wires should be pulled low, because otherwise the
pull-to-high will trigger a shutdown or reset action.  (The only
reason this doesn't happen immediately on startup is due to another
bug in the PL061, where we don't assert the GPIOs to the correct
value on reset, but will do so as soon as the guest touches a
register and pl061_update() gets called.)

Add properties to the pl061 so the board can configure whether it
wants GPIO lines to have pullup, pulldown, or neither.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@
  *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
  *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
  *    outputs
+ *  + QOM property "pullups": an integer defining whether non-floating lines
+ *    configured as inputs should be pulled up to logical 1 (ie whether in
+ *    real hardware they have a pullup resistor on the line out of the PL061).
+ *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
+ *    be pulled high, bit 1 configures line 1, and so on. The default is 0xff,
+ *    indicating that all GPIO lines are pulled up to logical 1.
+ *  + QOM property "pulldowns": an integer defining whether non-floating lines
+ *    configured as inputs should be pulled down to logical 0 (ie whether in
+ *    real hardware they have a pulldown resistor on the line out of the PL061).
+ *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
+ *    be pulled low, bit 1 configures line 1, and so on. The default is 0x0.
+ *    It is an error to set a bit in both "pullups" and "pulldowns". If a bit
+ *    is 0 in both, then the line is considered to be floating, and it will
+ *    not have qemu_set_irq() called on it when it is configured as an input.
  */
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
 #include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
+#include "qapi/error.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct PL061State {
     qemu_irq irq;
     qemu_irq out[N_GPIOS];
     const unsigned char *id;
+    /* Properties, for non-Luminary PL061 */
+    uint32_t pullups;
+    uint32_t pulldowns;
 };
 
 static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)
          */
         floating = ~(s->pur | s->pdr);
     } else {
-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-        floating = 0;
+        floating = ~(s->pullups | s->pulldowns);
     }
     return floating & ~s->dir;
 }
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_pullups(PL061State *s)
          */
         pullups = s->pur;
     } else {
-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-        pullups = 0xff;
+        pullups = s->pullups;
     }
     return pullups & ~s->dir;
 }
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
     qdev_init_gpio_out(dev, s->out, N_GPIOS);
 }
 
+static void pl061_realize(DeviceState *dev, Error **errp)
+{
+    PL061State *s = PL061(dev);
+
+    if (s->pullups > 0xff) {
+        error_setg(errp, "pullups property must be between 0 and 0xff");
+        return;
+    }
+    if (s->pulldowns > 0xff) {
+        error_setg(errp, "pulldowns property must be between 0 and 0xff");
+        return;
+    }
+    if (s->pullups & s->pulldowns) {
+        error_setg(errp, "no bit may be set both in pullups and pulldowns");
+        return;
+    }
+}
+
+static Property pl061_props[] = {
+    DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff),
+    DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void pl061_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl061;
     dc->reset = &pl061_reset;
+    dc->realize = pl061_realize;
+    device_class_set_props(dc, pl061_props);
 }
 
 static const TypeInfo pl061_info = {
-- 
2.20.1

For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do care, because we wire the lines up to the gpio-pwr device, which
assumes that level 1 means "do the action" and 1 means "do nothing".
For consistency in case we add more outputs in future, configure both
PL061s to pull GPIO lines down to 0.

Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
     MachineState *ms = MACHINE(vms);
 
     pl061_dev = qdev_new("pl061");
+    /* Pull lines down to 0 if not driven by the PL061 */
+    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
+    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
     s = SYS_BUS_DEVICE(pl061_dev);
     sysbus_realize_and_unref(s, &error_fatal);
     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
-- 
2.20.1

The PL061 comes out of reset with all its lines configured as input,
which means they might need to be pulled to 0 or 1 depending on the
'pullups' and 'pulldowns' properties.  Currently we do not assert
these lines on reset; they will only be set whenever the guest first
touches a register that triggers a call to pl061_update().

Convert the device to three-phase reset so we have a place where we
can safely call qemu_set_irq() to set the floating lines to their
correct values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 29 +++++++++++++++++++++++++----
 hw/gpio/trace-events |  1 +
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     return;
 }
 
-static void pl061_reset(DeviceState *dev)
+static void pl061_enter_reset(Object *obj, ResetType type)
 {
-    PL061State *s = PL061(dev);
+    PL061State *s = PL061(obj);
+
+    trace_pl061_reset(DEVICE(s)->canonical_path);
 
     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
     s->data = 0;
-    s->old_out_data = 0;
     s->old_in_data = 0;
     s->dir = 0;
     s->isense = 0;
@@ -XXX,XX +XXX,XX @@ static void pl061_reset(DeviceState *dev)
     s->amsel = 0;
 }
 
+static void pl061_hold_reset(Object *obj)
+{
+    PL061State *s = PL061(obj);
+    int i, level;
+    uint8_t floating = pl061_floating(s);
+    uint8_t pullups = pl061_pullups(s);
+
+    for (i = 0; i < N_GPIOS; i++) {
+        if (extract32(floating, i, 1)) {
+            continue;
+        }
+        level = extract32(pullups, i, 1);
+        trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+        qemu_set_irq(s->out[i], level);
+    }
+    s->old_out_data = pullups;
+}
+
 static void pl061_set_irq(void * opaque, int irq, int level)
 {
     PL061State *s = (PL061State *)opaque;
@@ -XXX,XX +XXX,XX @@ static Property pl061_props[] = {
 static void pl061_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl061;
-    dc->reset = &pl061_reset;
     dc->realize = pl061_realize;
     device_class_set_props(dc, pl061_props);
+    rc->phases.enter = pl061_enter_reset;
+    rc->phases.hold = pl061_hold_reset;
 }
 
 static const TypeInfo pl061_info = {
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+pl061_reset(const char *id) "%s reset"
 
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
reset value for GPIOPUR.  We can get away with not letting the board
configure the PUR reset value because we don't actually wire anything
up to the lines which should reset to pull-up.  Add a comment noting
this omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/gpio/pl061.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
     trace_pl061_reset(DEVICE(s)->canonical_path);
 
     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
+
+    /*
+     * FIXME: For the LM3S6965, not all of the PL061 instances have the
+     * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory
+     * we should allow the board to configure these via properties.
+     * In practice, we don't wire anything up to the affected GPIO lines
+     * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can
+     * get away with this inaccuracy.
+     */
     s->data = 0;
     s->old_in_data = 0;
     s->dir = 0;
-- 
2.20.1

The stellaris board doesn't emulate the handling of the OLED
chipselect line correctly.  Expand the comment describing this,
including a sketch of the theoretical correct way to do it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
             DeviceState *sddev;
             DeviceState *ssddev;
 
-            /* Some boards have both an OLED controller and SD card connected to
+            /*
+             * Some boards have both an OLED controller and SD card connected to
              * the same SSI port, with the SD card chip select connected to a
              * GPIO pin.  Technically the OLED chip select is connected to the
              * SSI Fss pin.  We do not bother emulating that as both devices
              * should never be selected simultaneously, and our OLED controller
              * ignores stray 0xff commands that occur when deselecting the SD
              * card.
+             *
+             * The h/w wiring is:
+             *  - GPIO pin D0 is wired to the active-low SD card chip select
+             *  - GPIO pin A3 is wired to the active-low OLED chip select
+             *  - The SoC wiring of the PL061 "auxiliary function" for A3 is
+             *    SSI0Fss ("frame signal"), which is an output from the SoC's
+             *    SSI controller. The SSI controller takes SSI0Fss low when it
+             *    transmits a frame, so it can work as a chip-select signal.
+             *  - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
+             *    (the OLED never sends data to the CPU, so no wiring needed)
+             *  - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
+             *    and the OLED display-data-in
+             *  - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
+             *    serial-clock input
+             * So a guest that wants to use the OLED can configure the PL061
+             * to make pins A2, A3, A5 aux-function, so they are connected
+             * directly to the SSI controller. When the SSI controller sends
+             * data it asserts SSI0Fss which selects the OLED.
+             * A guest that wants to use the SD card configures A2, A4 and A5
+             * as aux-function, but leaves A3 as a software-controlled GPIO
+             * line. It asserts the SD card chip-select by using the PL061
+             * to control pin D0, and lets the SSI controller handle Clk, Tx
+             * and Rx. (The SSI controller asserts Fss during tx cycles as
+             * usual, but because A3 is not set to aux-function this is not
+             * forwarded to the OLED, and so the OLED stays unselected.)
+             *
+             * The QEMU implementation instead is:
+             *  - GPIO pin D0 is wired to the active-low SD card chip select,
+             *    and also to the OLED chip-select which is implemented
+             *    as *active-high*
+             *  - SSI controller signals go to the devices regardless of
+             *    whether the guest programs A2, A4, A5 as aux-function or not
+             *
+             * The problem with this implementation is if the guest doesn't
+             * care about the SD card and only uses the OLED. In that case it
+             * may choose never to do anything with D0 (leaving it in its
+             * default floating state, which reliably leaves the card disabled
+             * because an SD card has a pullup on CS within the card itself),
+             * and only set up A2, A3, A5. This for us would mean the OLED
+             * never gets the chip-select assert it needs. We work around
+             * this with a manual raise of D0 here (despite board creation
+             * code being the wrong place to raise IRQ lines) to put the OLED
+             * into an initially selected state.
+             *
+             * In theory the right way to model this would be:
+             *  - Implement aux-function support in the PL061, with an
+             *    extra set of AFIN and AFOUT GPIO lines (set up so that
+             *    if a GPIO line is in auxfn mode the main GPIO in and out
+             *    track the AFIN and AFOUT lines)
+             *  - Wire the AFOUT for D0 up to either a line from the
+             *    SSI controller that's pulled low around every transmit,
+             *    or at least to an always-0 line here on the board
+             *  - Make the ssd0323 OLED controller chipselect active-low
              */
             bus = qdev_get_child_bus(dev, "ssi");
 
-- 
2.20.1

From: "hnick@vmware.com" <hnick@vmware.com>

Signed-off-by: Nick Hudson <hnick@vmware.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_tda,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
       .resetvalue = 0 },
-    /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
+    /*
+     * MDCCSR_EL0[30:29] map to EDSCR[30:29].  Simply RAZ as the external
+     * Debug Communication Channel is not implemented.
+     */
+    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
+      .access = PL0_R, .accessfn = access_tda,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    /*
+     * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
+     * it is unlikely a guest will care.
      * We don't implement the configurable EL0 access.
      */
-    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
-      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
+    { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
+      .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
       .type = ARM_CP_ALIAS,
       .access = PL1_R, .accessfn = access_tda,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
-- 
2.20.1

From: Rebecca Cran <rebecca@nuviainc.com>

Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_redist.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
     if (r == MEMTX_ERROR) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid guest read at offset " TARGET_FMT_plx
-                      "size %u\n", __func__, offset, size);
+                      " size %u\n", __func__, offset, size);
         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
                                    size, attrs.secure);
         /* The spec requires that reserved registers are RAZ/WI;
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
     if (r == MEMTX_ERROR) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid guest write at offset " TARGET_FMT_plx
-                      "size %u\n", __func__, offset, size);
+                      " size %u\n", __func__, offset, size);
         trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
                                     size, attrs.secure);
         /* The spec requires that reserved registers are RAZ/WI;
-- 
2.20.1