Arm patch queue -- these are all bug fix patches but we might as well put them in to rc0... thanks -- PMM The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000) are available in the Git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319 for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6: hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000) ---------------------------------------------------------------- target-arm queue: * fsl-imx6: Fix incorrect Ethernet interrupt defines * dump: Update correct kdump phys_base field for AArch64 * char: i.MX: Add support for "TX complete" interrupt * bcm2836/raspi: Fix various bugs resulting in panics trying to boot a Debian Linux kernel on raspi3 ---------------------------------------------------------------- Andrey Smirnov (2): char: i.MX: Simplify imx_update() char: i.MX: Add support for "TX complete" interrupt Guenter Roeck (1): fsl-imx6: Swap Ethernet interrupt defines Peter Maydell (9): hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE hw/arm/bcm2386: Fix parent type of bcm2386 hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x hw/arm/bcm2836: Create proper bcm2837 device hw/arm/bcm2836: Use correct affinity values for BCM2837 hw/arm/bcm2836: Hardcode correct CPU type hw/arm/raspi: Provide spin-loop code for AArch64 CPUs Wei Huang (1): dump: Update correct kdump phys_base field for AArch64 include/hw/arm/bcm2836.h | 31 +++++++++++++--- include/hw/arm/fsl-imx6.h | 4 +- include/hw/char/imx_serial.h | 3 ++ dump.c | 14 +++++-- hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++------------- hw/arm/boot.c | 12 ++++++ hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++-------- hw/char/imx_serial.c | 44 ++++++++++++++++------ hw/net/imx_fec.c | 28 +++++++++++++- 9 files changed, 237 insertions(+), 63 deletions(-) From: Guenter Roeck <linux@roeck-us.net> The sabrelite machine model used by qemu-system-arm is based on the Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet controller which is supported in QEMU using the imx_fec.c module (actually called imx.enet for this model.) The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the imx.enet device like this: #define FSL_IMX6_ENET_MAC_1588_IRQ 118 #define FSL_IMX6_ENET_MAC_IRQ 119 According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf, page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary, interrupts are as follows. 150 ENET MAC 0 IRQ 151 ENET MAC 0 1588 Timer interrupt where 150 - 32 == 118 151 - 32 == 119 In other words, the vector definitions in the fsl-imx6.h file are reversed. Fixing the interrupts alone causes problems with older Linux kernels: The Ethernet interface will fail to probe with Linux v4.9 and earlier. Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe error handling. This is a Linux kernel problem, not a qemu problem: the Linux kernel only worked by accident since it requested both interrupts. For backward compatibility, generate the Ethernet interrupt on both interrupt lines. This was shown to work from all Linux kernel releases starting with v3.16. Link: https://bugs.launchpad.net/qemu/+bug/1753309 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/fsl-imx6.h | 4 ++-- hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State { #define FSL_IMX6_HDMI_MASTER_IRQ 115 #define FSL_IMX6_HDMI_CEC_IRQ 116 #define FSL_IMX6_MLB150_LOW_IRQ 117 -#define FSL_IMX6_ENET_MAC_1588_IRQ 118 -#define FSL_IMX6_ENET_MAC_IRQ 119 +#define FSL_IMX6_ENET_MAC_IRQ 118 +#define FSL_IMX6_ENET_MAC_1588_IRQ 119 #define FSL_IMX6_PCIE1_IRQ 120 #define FSL_IMX6_PCIE2_IRQ 121 #define FSL_IMX6_PCIE3_IRQ 122 diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index XXXXXXX..XXXXXXX 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) static void imx_eth_update(IMXFECState *s) { - if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) { + /* + * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER + * interrupts swapped. This worked with older versions of Linux (4.14 + * and older) since Linux associated both interrupt lines with Ethernet + * MAC interrupts. Specifically, + * - Linux 4.15 and later have separate interrupt handlers for the MAC and + * timer interrupts. Those versions of Linux fail with versions of QEMU + * with swapped interrupt assignments. + * - In linux 4.14, both interrupt lines were registered with the Ethernet + * MAC interrupt handler. As a result, all versions of qemu happen to + * work, though that is accidental. + * - In Linux 4.9 and older, the timer interrupt was registered directly + * with the Ethernet MAC interrupt handler. The MAC interrupt was + * redirected to a GPIO interrupt to work around erratum ERR006687. + * This was implemented using the SOC's IOMUX block. In qemu, this GPIO + * interrupt never fired since IOMUX is currently not supported in qemu. + * Linux instead received MAC interrupts on the timer interrupt. + * As a result, qemu versions with the swapped interrupt assignment work, + * albeit accidentally, but qemu versions with the correct interrupt + * assignment fail. + * + * To ensure that all versions of Linux work, generate ENET_INT_MAC + * interrrupts on both interrupt lines. This should be changed if and when + * qemu supports IOMUX. + */ + if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & + (ENET_INT_MAC | ENET_INT_TS_TIMER)) { qemu_set_irq(s->irq[1], 1); } else { qemu_set_irq(s->irq[1], 0); -- 2.16.2 From: Wei Huang <wei@redhat.com> For guest kernel that supports KASLR, the load address can change every time when guest VM runs. To find the physical base address correctly, current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=". However this string pattern is only available on x86_64. AArch64 uses a different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure QEMU dump uses the correct string on AArch64. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- dump.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/dump.c b/dump.c index XXXXXXX..XXXXXXX 100644 --- a/dump.c +++ b/dump.c @@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s) lines = g_strsplit((char *)vmci, "\n", -1); for (i = 0; lines[i]; i++) { - if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) { - if (qemu_strtou64(lines[i] + 18, NULL, 16, + const char *prefix = NULL; + + if (s->dump_info.d_machine == EM_X86_64) { + prefix = "NUMBER(phys_base)="; + } else if (s->dump_info.d_machine == EM_AARCH64) { + prefix = "NUMBER(PHYS_OFFSET)="; + } + + if (prefix && g_str_has_prefix(lines[i], prefix)) { + if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16, &phys_base) < 0) { - warn_report("Failed to read NUMBER(phys_base)="); + warn_report("Failed to read %s", prefix); } else { s->dump_info.phys_base = phys_base; } -- 2.16.2 From: Andrey Smirnov <andrew.smirnov@gmail.com> Code of imx_update() is slightly confusing since the "flags" variable doesn't really corespond to anything in real hardware and server as a kitchensink accumulating events normally reported via USR1 and USR2 registers. Change the code to explicitly evaluate state of interrupts reported via USR1 and USR2 against corresponding masking bits and use the to detemine if IRQ line should be asserted or not. NOTE: Check for UTS1_TXEMPTY being set has been dropped for two reasons: 1. Emulation code implements a single character FIFO, so this flag will always be set since characters are trasmitted as a part of the code emulating "push" into the FIFO 2. imx_update() is really just a function doing ORing and maksing of reported events, so checking for UTS1_TXEMPTY should happen, if it's ever really needed should probably happen outside of it. Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: Bill Paul <wpaul@windriver.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/char/imx_serial.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index XXXXXXX..XXXXXXX 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { static void imx_update(IMXSerialState *s) { - uint32_t flags; + uint32_t usr1; + uint32_t usr2; + uint32_t mask; - flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); - if (s->ucr1 & UCR1_TXMPTYEN) { - flags |= (s->uts1 & UTS1_TXEMPTY); - } else { - flags &= ~USR1_TRDY; - } + /* + * Lucky for us TRDY and RRDY has the same offset in both USR1 and + * UCR1, so we can get away with something as simple as the + * following: + */ + usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); + /* + * Bits that we want in USR2 are not as conveniently laid out, + * unfortunately. + */ + mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; + usr2 = s->usr2 & mask; - qemu_set_irq(s->irq, !!flags); + qemu_set_irq(s->irq, usr1 || usr2); } static void imx_serial_reset(IMXSerialState *s) -- 2.16.2 From: Andrey Smirnov <andrew.smirnov@gmail.com> Add support for "TX complete"/TXDC interrupt generate by real HW since it is needed to support guests other than Linux. Based on the patch by Bill Paul as found here: https://bugs.launchpad.net/qemu/+bug/1753314 Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: Bill Paul <wpaul@windriver.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bill Paul <wpaul@windriver.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/char/imx_serial.h | 3 +++ hw/char/imx_serial.c | 20 +++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -XXX,XX +XXX,XX @@ #define UCR2_RXEN (1<<1) /* Receiver enable */ #define UCR2_SRST (1<<0) /* Reset complete */ +#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ + #define UTS1_TXEMPTY (1<<6) #define UTS1_RXEMPTY (1<<5) #define UTS1_TXFULL (1<<4) @@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState { uint32_t ubmr; uint32_t ubrc; uint32_t ucr3; + uint32_t ucr4; qemu_irq irq; CharBackend chr; diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index XXXXXXX..XXXXXXX 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { .name = TYPE_IMX_SERIAL, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_INT32(readbuff, IMXSerialState), VMSTATE_UINT32(usr1, IMXSerialState), @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { VMSTATE_UINT32(ubmr, IMXSerialState), VMSTATE_UINT32(ubrc, IMXSerialState), VMSTATE_UINT32(ucr3, IMXSerialState), + VMSTATE_UINT32(ucr4, IMXSerialState), VMSTATE_END_OF_LIST() }, }; @@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s) * unfortunately. */ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; + /* + * TCEN and TXDC are both bit 3 + */ + mask |= s->ucr4 & UCR4_TCEN; + usr2 = s->usr2 & mask; qemu_set_irq(s->irq, usr1 || usr2); @@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, return s->ucr3; case 0x23: /* UCR4 */ + return s->ucr4; + case 0x29: /* BRM Incremental */ return 0x0; /* TODO */ @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); s->usr1 &= ~USR1_TRDY; + s->usr2 &= ~USR2_TXDC; imx_update(s); s->usr1 |= USR1_TRDY; + s->usr2 |= USR2_TXDC; imx_update(s); } break; @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, s->ucr3 = value & 0xffff; break; - case 0x2d: /* UTS1 */ case 0x23: /* UCR4 */ + s->ucr4 = value & 0xffff; + imx_update(s); + break; + + case 0x2d: /* UTS1 */ qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); /* TODO */ -- 2.16.2 For the rpi1 and 2 we want to boot the Linux kernel via some custom setup code that makes sure that the SMC instruction acts as a no-op, because it's used for cache maintenance. The rpi3 boots AArch64 kernels, which don't need SMC for cache maintenance and always expect to be booted non-secure. Don't fill in the aarch32-specific parts of the binfo struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-2-peter.maydell@linaro.org --- hw/arm/raspi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) binfo.board_id = raspi_boardid[version]; binfo.ram_size = ram_size; binfo.nb_cpus = smp_cpus; - binfo.board_setup_addr = BOARDSETUP_ADDR; - binfo.write_board_setup = write_board_setup; - binfo.secure_board_setup = true; - binfo.secure_boot = true; + + if (version <= 2) { + /* The rpi1 and 2 require some custom setup code to run in Secure + * mode before booting a kernel (to set up the SMC vectors so + * that we get a no-op SMC; this is used by Linux to call the + * firmware for some cache maintenance operations. + * The rpi3 doesn't need this. + */ + binfo.board_setup_addr = BOARDSETUP_ADDR; + binfo.write_board_setup = write_board_setup; + binfo.secure_board_setup = true; + binfo.secure_boot = true; + } /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { -- 2.16.2 Add some assertions that if we're about to boot an AArch64 kernel, the board code has not mistakenly set either secure_boot or secure_board_setup. It doesn't make sense to set secure_boot, because all AArch64 kernels must be booted in non-secure mode. It might in theory make sense to set secure_board_setup, but we don't currently support that, because only the AArch32 bootloader[] code calls this hook; bootloader_aarch64[] does not. Since we don't have a current need for this functionality, just assert that we don't try to use it. If it's needed we'll add it later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-3-peter.maydell@linaro.org --- hw/arm/boot.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) } else { env->pstate = PSTATE_MODE_EL1h; } + /* AArch64 kernels never boot in secure mode */ + assert(!info->secure_boot); + /* This hook is only supported for AArch32 currently: + * bootloader_aarch64[] will not call the hook, and + * the code above has already dropped us into EL2 or EL1. + */ + assert(!info->secure_board_setup); } /* Set to non-secure if not a secure boot */ -- 2.16.2 If we're directly booting a Linux kernel and the CPU supports both EL3 and EL2, we start the kernel in EL2, as it expects. We must also set the SCR_EL3.HCE bit in this situation, so that the HVC instruction is enabled rather than UNDEFing. Otherwise at least some kernels will panic when trying to initialize KVM in the guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180313153458.26822-4-peter.maydell@linaro.org --- hw/arm/boot.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) assert(!info->secure_board_setup); } + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* If we have EL2 then Linux expects the HVC insn to work */ + env->cp15.scr_el3 |= SCR_HCE; + } + /* Set to non-secure if not a secure boot */ if (!info->secure_boot && (cs != first_cpu || !info->secure_board_setup)) { -- 2.16.2 The TypeInfo and state struct for bcm2386 disagree about what the parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, but the BCM2386State struct only defines the parent_obj field as DeviceState. This would have caused problems if anything actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't need any of the additional functionality TYPE_SYS_BUS_DEVICE provides. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-5-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) static const TypeInfo bcm2836_type_info = { .name = TYPE_BCM2836, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_DEVICE, .instance_size = sizeof(BCM2836State), .instance_init = bcm2836_init, .class_init = bcm2836_class_init, -- 2.16.2 Our BCM2836 type is really a generic one that can be any of the bcm283x family. Rename it accordingly. We change only the names which are visible via the header file to the rest of the QEMU code, leaving private function names in bcm2836.c as they are. This is a preliminary to making bcm283x be an abstract parent class to specific types for the bcm2836 and bcm2837. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-6-peter.maydell@linaro.org --- include/hw/arm/bcm2836.h | 12 ++++++------ hw/arm/bcm2836.c | 17 +++++++++-------- hw/arm/raspi.c | 16 ++++++++-------- 3 files changed, 23 insertions(+), 22 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -XXX,XX +XXX,XX @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" -#define TYPE_BCM2836 "bcm2836" -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) +#define TYPE_BCM283X "bcm283x" +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) -#define BCM2836_NCPUS 4 +#define BCM283X_NCPUS 4 -typedef struct BCM2836State { +typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State { char *cpu_type; uint32_t enabled_cpus; - ARMCPU cpus[BCM2836_NCPUS]; + ARMCPU cpus[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; -} BCM2836State; +} BCM283XState; #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) { - BCM2836State *s = BCM2836(obj); + BCM283XState *s = BCM283X(obj); object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { - BCM2836State *s = BCM2836(dev); + BCM283XState *s = BCM283X(dev); Object *obj; Error *err = NULL; int n; @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ obj = OBJECT(dev); - for (n = 0; n < BCM2836_NCPUS; n++) { + for (n = 0; n < BCM283X_NCPUS; n++) { object_initialize(&s->cpus[n], sizeof(s->cpus[n]), s->cpu_type); object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); - for (n = 0; n < BCM2836_NCPUS; n++) { + for (n = 0; n < BCM283X_NCPUS; n++) { /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, + BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() }; @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) } static const TypeInfo bcm2836_type_info = { - .name = TYPE_BCM2836, + .name = TYPE_BCM283X, .parent = TYPE_DEVICE, - .instance_size = sizeof(BCM2836State), + .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, .class_init = bcm2836_class_init, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; typedef struct RasPiState { - BCM2836State soc; + BCM283XState soc; MemoryRegion ram; } RasPiState; @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); - mc->max_cpus = BCM2836_NCPUS; - mc->min_cpus = BCM2836_NCPUS; - mc->default_cpus = BCM2836_NCPUS; + mc->max_cpus = BCM283X_NCPUS; + mc->min_cpus = BCM283X_NCPUS; + mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; mc->ignore_memory_transaction_failures = true; }; @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); - mc->max_cpus = BCM2836_NCPUS; - mc->min_cpus = BCM2836_NCPUS; - mc->default_cpus = BCM2836_NCPUS; + mc->max_cpus = BCM283X_NCPUS; + mc->min_cpus = BCM283X_NCPUS; + mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; } DEFINE_MACHINE("raspi3", raspi3_machine_init) -- 2.16.2 The bcm2837 is pretty similar to the bcm2836, but it does have some differences. Notably, the MPIDR affinity aff1 values it sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 uses, and if this is wrong Linux will not boot. Rather than trying to have one device with properties that configure it differently for the two cases, create two separate QOM devices for the two SoCs. We use the same approach as hw/arm/aspeed_soc.c and share code and have a data table that might differ per-SoC. For the moment the two types don't actually have different behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-7-peter.maydell@linaro.org --- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- hw/arm/raspi.c | 3 ++- 3 files changed, 53 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -XXX,XX +XXX,XX @@ #define BCM283X_NCPUS 4 +/* These type names are for specific SoCs; other than instantiating + * them, code using these devices should always handle them via the + * BCM283x base class, so they have no BCM2836(obj) etc macros. + */ +#define TYPE_BCM2836 "bcm2836" +#define TYPE_BCM2837 "bcm2837" + typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; @@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState { BCM2835PeripheralState peripherals; } BCM283XState; +typedef struct BCM283XInfo BCM283XInfo; + +typedef struct BCM283XClass { + DeviceClass parent_class; + const BCM283XInfo *info; +} BCM283XClass; + +#define BCM283X_CLASS(klass) \ + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) +#define BCM283X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) + #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -XXX,XX +XXX,XX @@ /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ #define BCM2836_CONTROL_BASE 0x40000000 +struct BCM283XInfo { + const char *name; +}; + +static const BCM283XInfo bcm283x_socs[] = { + { + .name = TYPE_BCM2836, + }, + { + .name = TYPE_BCM2837, + }, +}; + static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); @@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = { DEFINE_PROP_END_OF_LIST() }; -static void bcm2836_class_init(ObjectClass *oc, void *data) +static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); - dc->props = bcm2836_props; + bc->info = data; dc->realize = bcm2836_realize; + dc->props = bcm2836_props; } -static const TypeInfo bcm2836_type_info = { +static const TypeInfo bcm283x_type_info = { .name = TYPE_BCM283X, .parent = TYPE_DEVICE, .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, - .class_init = bcm2836_class_init, + .class_size = sizeof(BCM283XClass), + .abstract = true, }; static void bcm2836_register_types(void) { - type_register_static(&bcm2836_type_info); + int i; + + type_register_static(&bcm283x_type_info); + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { + TypeInfo ti = { + .name = bcm283x_socs[i].name, + .parent = TYPE_BCM283X, + .class_init = bcm283x_class_init, + .class_data = (void *) &bcm283x_socs[i], + }; + type_register(&ti); + } } type_init(bcm2836_register_types) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); + object_initialize(&s->soc, sizeof(s->soc), + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); -- 2.16.2 The BCM2837 sets the Aff1 field of the MPIDR affinity values for the CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it is required for Linux to boot. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-8-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -XXX,XX +XXX,XX @@ struct BCM283XInfo { const char *name; + int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .clusterid = 0xf, }, { .name = TYPE_BCM2837, + .clusterid = 0x0, }, }; @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); + BCM283XClass *bc = BCM283X_GET_CLASS(dev); + const BCM283XInfo *info = bc->info; Object *obj; Error *err = NULL; int n; @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); for (n = 0; n < BCM283X_NCPUS; n++) { - /* Mirror bcm2836, which has clusterid set to 0xf - * TODO: this should be converted to a property of ARM_CPU - */ - s->cpus[n].mp_affinity = 0xF00 | n; + /* TODO: this should be converted to a property of ARM_CPU */ + s->cpus[n].mp_affinity = (info->clusterid << 8) | n; /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), -- 2.16.2 Now we have separate types for BCM2386 and BCM2387, we might as well just hard-code the CPU type they use rather than having it passed through as an object property. This then lets us put the initialization of the CPU object in init rather than realize. Note that this change means that it's no longer possible on the command line to use -cpu to ask for a different kind of CPU than the SoC supports. This was never a supported thing to do anyway; we were just not sanity-checking the command line. This does require us to only build the bcm2837 object on TARGET_AARCH64 configs, since otherwise it won't instantiate due to the missing cortex-a53 device and "make check" will fail. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-9-peter.maydell@linaro.org --- hw/arm/bcm2836.c | 24 +++++++++++++++--------- hw/arm/raspi.c | 2 -- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -XXX,XX +XXX,XX @@ struct BCM283XInfo { const char *name; + const char *cpu_type; int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), .clusterid = 0xf, }, +#ifdef TARGET_AARCH64 { .name = TYPE_BCM2837, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), .clusterid = 0x0, }, +#endif }; static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); + BCM283XClass *bc = BCM283X_GET_CLASS(obj); + const BCM283XInfo *info = bc->info; + int n; + + for (n = 0; n < BCM283X_NCPUS; n++) { + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), + info->cpu_type); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), + &error_abort); + } object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ - obj = OBJECT(dev); - for (n = 0; n < BCM283X_NCPUS; n++) { - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), - s->cpu_type); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), - &error_abort); - } - obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", &error_abort); int board_rev = version == 3 ? 0xa02082 : 0xa21041; -- 2.16.2 The raspi3 has AArch64 CPUs, which means that our smpboot code for keeping the secondary CPUs in a pen needs to have a version for A64 as well as A32. Without this, the secondary CPUs go into an infinite loop of taking undefined instruction exceptions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180313153458.26822-10-peter.maydell@linaro.org --- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ /* Table of Linux board IDs for different Pi versions */ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; @@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) info->smp_loader_start); } +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) +{ + /* Unlike the AArch32 version we don't need to call the board setup hook. + * The mechanism for doing the spin-table is also entirely different. + * We must have four 64-bit fields at absolute addresses + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for + * our CPUs, and which we must ensure are zero initialized before + * the primary CPU goes into the kernel. We put these variables inside + * a rom blob, so that the reset for ROM contents zeroes them for us. + */ + static const uint32_t smpboot[] = { + 0xd2801b05, /* mov x5, 0xd8 */ + 0xd53800a6, /* mrs x6, mpidr_el1 */ + 0x924004c6, /* and x6, x6, #0x3 */ + 0xd503205f, /* spin: wfe */ + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ + 0xb4ffffc4, /* cbz x4, spin */ + 0xd2800000, /* mov x0, #0x0 */ + 0xd2800001, /* mov x1, #0x0 */ + 0xd2800002, /* mov x2, #0x0 */ + 0xd2800003, /* mov x3, #0x0 */ + 0xd61f0080, /* br x4 */ + }; + + static const uint64_t spintables[] = { + 0, 0, 0, 0 + }; + + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start); + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), + SPINTABLE_ADDR); +} + static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { binfo.smp_loader_start = SMPBOOT_ADDR; - binfo.write_secondary_boot = write_smpboot; + if (version == 2) { + binfo.write_secondary_boot = write_smpboot; + } else { + binfo.write_secondary_boot = write_smpboot64; + } binfo.secondary_cpu_reset_hook = reset_secondary; } -- 2.16.2 target-arm queue: I have a lot more still in my to-review queue, but my rule of thumb is when I get to 50 patches or so to send out what I have. thanks -- PMM The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312: Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210305 for you to fetch changes up to 2c669ff88ec6733420a000103a2b8b9e93df4945: hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-05 15:17:38 +0000) ---------------------------------------------------------------- * sbsa-ref: remove cortex-a53 from list of supported cpus * sbsa-ref: add 'max' to list of allowed cpus * target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe * npcm7xx: add EMC model * xlnx-zynqmp: Remove obsolete 'has_rpu' property * target/arm: Speed up aarch64 TBL/TBX * virtio-mmio: improve virtio-mmio get_dev_path alog * target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks * target/arm: Restrict v8M IDAU to TCG * target/arm/cpu: Update coding style to make checkpatch.pl happy * musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces * Add new board: mps3-an524 ---------------------------------------------------------------- Doug Evans (3): hw/net: Add npcm7xx emc model hw/arm: Add npcm7xx emc model tests/qtests: Add npcm7xx emc model test Marcin Juszkiewicz (2): sbsa-ref: remove cortex-a53 from list of supported cpus sbsa-ref: add 'max' to list of allowed cpus Peter Collingbourne (1): target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks Peter Maydell (34): hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces hw/display/tc6393xb: Expand out macros in template header hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite hw/display/omap_lcdc: Expand out macros in template header hw/display/omap_lcdc: Drop broken bigendian ifdef hw/display/omap_lcdc: Fix coding style issues in template header hw/display/omap_lcdc: Inline template header into C file hw/display/omap_lcdc: Delete unnecessary macro hw/display/tcx: Drop unnecessary code for handling BGR format outputs hw/arm/mps2-tz: Make SYSCLK frequency board-specific hw/misc/mps2-scc: Support configurable number of OSCCLK values hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board hw/misc/mps2-fpgaio: Make number of LEDs configurable by board hw/misc/mps2-fpgaio: Support SWITCH register hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type hw/arm/mps2-tz: Make number of IRQs board-specific hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts hw/arm/mps2-tz: Move device IRQ info to data structures hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs hw/arm/mps2-tz: Allow boards to have different PPCInfo data hw/arm/mps2-tz: Make RAM arrangement board-specific hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data hw/arm/mps2-tz: Support ROMs as well as RAMs hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo hw/arm/mps2-tz: Add new mps3-an524 board hw/arm/mps2-tz: Stub out USB controller for mps3-an524 hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 docs/system/arm/mps2.rst: Document the new mps3-an524 board hw/arm/mps2: Update old infocenter.arm.com URLs Philippe Mathieu-Daudé (4): hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() target/arm: Restrict v8M IDAU to TCG target/arm/cpu: Update coding style to make checkpatch.pl happy Rebecca Cran (3): target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Richard Henderson (1): target/arm: Speed up aarch64 TBL/TBX schspa (1): virtio-mmio: improve virtio-mmio get_dev_path alog docs/system/arm/mps2.rst | 24 +- docs/system/arm/nuvoton.rst | 3 +- hw/display/omap_lcd_template.h | 169 -------- hw/display/tc6393xb_template.h | 72 ---- include/hw/arm/armsse.h | 4 +- include/hw/arm/npcm7xx.h | 2 + include/hw/arm/xlnx-zynqmp.h | 2 - include/hw/misc/armsse-cpuid.h | 2 +- include/hw/misc/armsse-mhu.h | 2 +- include/hw/misc/iotkit-secctl.h | 2 +- include/hw/misc/iotkit-sysctl.h | 2 +- include/hw/misc/iotkit-sysinfo.h | 2 +- include/hw/misc/mps2-fpgaio.h | 8 +- include/hw/misc/mps2-scc.h | 10 +- include/hw/net/npcm7xx_emc.h | 286 +++++++++++++ include/ui/console.h | 10 - target/arm/cpu.h | 15 +- target/arm/helper-a64.h | 2 +- target/arm/internals.h | 6 + hw/arm/mps2-tz.c | 632 +++++++++++++++++++++++----- hw/arm/mps2.c | 5 + hw/arm/musicpal.c | 64 ++- hw/arm/npcm7xx.c | 50 ++- hw/arm/sbsa-ref.c | 2 +- hw/arm/xlnx-zynqmp.c | 6 - hw/display/omap_lcdc.c | 129 +++++- hw/display/tc6393xb.c | 48 +-- hw/display/tcx.c | 31 +- hw/i2c/npcm7xx_smbus.c | 1 - hw/misc/armsse-cpuid.c | 2 +- hw/misc/armsse-mhu.c | 2 +- hw/misc/iotkit-sysctl.c | 2 +- hw/misc/iotkit-sysinfo.c | 2 +- hw/misc/mps2-fpgaio.c | 43 +- hw/misc/mps2-scc.c | 93 ++++- hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++ hw/virtio/virtio-mmio.c | 13 +- target/arm/cpu.c | 23 +- target/arm/cpu64.c | 5 + target/arm/cpu_tcg.c | 8 + target/arm/helper-a64.c | 32 -- target/arm/helper.c | 39 +- target/arm/mte_helper.c | 13 +- target/arm/translate-a64.c | 70 +--- target/arm/vec_helper.c | 48 +++ tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++ hw/net/meson.build | 1 + hw/net/trace-events | 17 + tests/qtest/meson.build | 3 +- 49 files changed, 3098 insertions(+), 628 deletions(-) delete mode 100644 hw/display/omap_lcd_template.h delete mode 100644 hw/display/tc6393xb_template.h create mode 100644 include/hw/net/npcm7xx_emc.h create mode 100644 hw/net/npcm7xx_emc.c create mode 100644 tests/qtest/npcm7xx_emc-test.c From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts above this limit. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/sbsa-ref.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { }; static const char * const valid_cpus[] = { - ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), }; -- 2.20.1 From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Let add 'max' cpu while work goes on adding newer CPU types than Cortex-A72. This allows us to check SVE etc support. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/sbsa-ref.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("max"), }; static bool cpu_type_valid(const char *cpu) -- 2.20.1 From: Rebecca Cran <rebecca@nuviainc.com> Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an optional feature in ARMv8.0, and mandatory in ARMv8.5. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 15 ++++++++++++++- target/arm/internals.h | 6 ++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 ++++++++++++ 4 files changed, 69 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define SCTLR_TE (1U << 30) /* AArch32 only */ #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ +#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ -#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ +#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define CPSR_IL (1U << 20) #define CPSR_DIT (1U << 21) #define CPSR_PAN (1U << 22) +#define CPSR_SSBS (1U << 23) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define PSTATE_A (1U << 8) #define PSTATE_D (1U << 9) #define PSTATE_BTYPE (3U << 10) +#define PSTATE_SSBS (1U << 12) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; } +static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; +} + /* * 64-bit feature tests via id registers. */ @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; } +static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if (isar_feature_aa32_dit(id)) { valid |= CPSR_DIT; } + if (isar_feature_aa32_ssbs(id)) { + valid |= CPSR_SSBS; + } return valid; } @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) if (isar_feature_aa64_dit(id)) { valid |= PSTATE_DIT; } + if (isar_feature_aa64_ssbs(id)) { + valid |= PSTATE_SSBS; + } if (isar_feature_aa64_mte(id)) { valid |= PSTATE_TCO; } diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dit_reginfo = { .readfn = aa64_dit_read, .writefn = aa64_dit_write }; +static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_SSBS; +} + +static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); +} + +static const ARMCPRegInfo ssbs_reginfo = { + .name = "SSBS", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, + .type = ARM_CP_NO_RAW, .access = PL0_RW, + .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write +}; + static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_dit, cpu)) { define_one_arm_cp_reg(cpu, &dit_reginfo); } + if (cpu_isar_feature(aa64_ssbs, cpu)) { + define_one_arm_cp_reg(cpu, &ssbs_reginfo); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); @@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); env->daif |= mask; + if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { + env->uncached_cpsr |= CPSR_SSBS; + } else { + env->uncached_cpsr &= ~CPSR_SSBS; + } + } + if (new_mode == ARM_CPU_MODE_HYP) { env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; env->elr_el[2] = env->regs[15]; @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) new_mode |= PSTATE_TCO; } + if (cpu_isar_feature(aa64_ssbs, cpu)) { + if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { + new_mode |= PSTATE_SSBS; + } else { + new_mode &= ~PSTATE_SSBS; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, tcg_temp_free_i32(t1); break; + case 0x19: /* SSBS */ + if (!dc_isar_feature(aa64_ssbs, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_SSBS); + } else { + clear_pstate_bits(PSTATE_SSBS); + } + /* Don't need to rebuild hflags since SSBS is a nop */ + break; + case 0x1a: /* DIT */ if (!dc_isar_feature(aa64_dit, s)) { goto do_unallocated; -- 2.20.1 From: Rebecca Cran <rebecca@nuviainc.com> Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* * Begin with full support for MTE. This will be downgraded to MTE=0 * during realize if the board provides no tag memory, much like @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 = u; + u = cpu->isar.id_pfr2; + u = FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 = u; + u = cpu->isar.id_mmfr3; u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 = u; -- 2.20.1 From: Rebecca Cran <rebecca@nuviainc.com> Enable FEAT_SSBS for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-4-rebecca@nuviainc.com [PMM: fix typo causing compilation failure] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) t = cpu->isar.id_pfr0; t = FIELD_DP32(t, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 = t; + + t = cpu->isar.id_pfr2; + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 = t; } #endif } -- 2.20.1 From: Doug Evans <dje@google.com> This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-2-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/net/npcm7xx_emc.h | 286 ++++++++++++ hw/net/npcm7xx_emc.c | 857 +++++++++++++++++++++++++++++++++++ hw/net/meson.build | 1 + hw/net/trace-events | 17 + 4 files changed, 1161 insertions(+) create mode 100644 include/hw/net/npcm7xx_emc.h create mode 100644 hw/net/npcm7xx_emc.c diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/net/npcm7xx_emc.h @@ -XXX,XX +XXX,XX @@ +/* + * Nuvoton NPCM7xx EMC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef NPCM7XX_EMC_H +#define NPCM7XX_EMC_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "net/net.h" + +/* 32-bit register indices. */ +enum NPCM7xxPWMRegister { + /* Control registers. */ + REG_CAMCMR, + REG_CAMEN, + + /* There are 16 CAMn[ML] registers. */ + REG_CAMM_BASE, + REG_CAML_BASE, + REG_CAMML_LAST = 0x21, + + REG_TXDLSA = 0x22, + REG_RXDLSA, + REG_MCMDR, + REG_MIID, + REG_MIIDA, + REG_FFTCR, + REG_TSDR, + REG_RSDR, + REG_DMARFC, + REG_MIEN, + + /* Status registers. */ + REG_MISTA, + REG_MGSTA, + REG_MPCNT, + REG_MRPC, + REG_MRPCC, + REG_MREPC, + REG_DMARFS, + REG_CTXDSA, + REG_CTXBSA, + REG_CRXDSA, + REG_CRXBSA, + + NPCM7XX_NUM_EMC_REGS, +}; + +/* REG_CAMCMR fields */ +/* Enable CAM Compare */ +#define REG_CAMCMR_ECMP (1 << 4) +/* Complement CAM Compare */ +#define REG_CAMCMR_CCAM (1 << 3) +/* Accept Broadcast Packet */ +#define REG_CAMCMR_ABP (1 << 2) +/* Accept Multicast Packet */ +#define REG_CAMCMR_AMP (1 << 1) +/* Accept Unicast Packet */ +#define REG_CAMCMR_AUP (1 << 0) + +/* REG_MCMDR fields */ +/* Software Reset */ +#define REG_MCMDR_SWR (1 << 24) +/* Internal Loopback Select */ +#define REG_MCMDR_LBK (1 << 21) +/* Operation Mode Select */ +#define REG_MCMDR_OPMOD (1 << 20) +/* Enable MDC Clock Generation */ +#define REG_MCMDR_ENMDC (1 << 19) +/* Full-Duplex Mode Select */ +#define REG_MCMDR_FDUP (1 << 18) +/* Enable SQE Checking */ +#define REG_MCMDR_ENSEQ (1 << 17) +/* Send PAUSE Frame */ +#define REG_MCMDR_SDPZ (1 << 16) +/* No Defer */ +#define REG_MCMDR_NDEF (1 << 9) +/* Frame Transmission On */ +#define REG_MCMDR_TXON (1 << 8) +/* Strip CRC Checksum */ +#define REG_MCMDR_SPCRC (1 << 5) +/* Accept CRC Error Packet */ +#define REG_MCMDR_AEP (1 << 4) +/* Accept Control Packet */ +#define REG_MCMDR_ACP (1 << 3) +/* Accept Runt Packet */ +#define REG_MCMDR_ARP (1 << 2) +/* Accept Long Packet */ +#define REG_MCMDR_ALP (1 << 1) +/* Frame Reception On */ +#define REG_MCMDR_RXON (1 << 0) + +/* REG_MIEN fields */ +/* Enable Transmit Descriptor Unavailable Interrupt */ +#define REG_MIEN_ENTDU (1 << 23) +/* Enable Transmit Completion Interrupt */ +#define REG_MIEN_ENTXCP (1 << 18) +/* Enable Transmit Interrupt */ +#define REG_MIEN_ENTXINTR (1 << 16) +/* Enable Receive Descriptor Unavailable Interrupt */ +#define REG_MIEN_ENRDU (1 << 10) +/* Enable Receive Good Interrupt */ +#define REG_MIEN_ENRXGD (1 << 4) +/* Enable Receive Interrupt */ +#define REG_MIEN_ENRXINTR (1 << 0) + +/* REG_MISTA fields */ +/* TODO: Add error fields and support simulated errors? */ +/* Transmit Bus Error Interrupt */ +#define REG_MISTA_TXBERR (1 << 24) +/* Transmit Descriptor Unavailable Interrupt */ +#define REG_MISTA_TDU (1 << 23) +/* Transmit Completion Interrupt */ +#define REG_MISTA_TXCP (1 << 18) +/* Transmit Interrupt */ +#define REG_MISTA_TXINTR (1 << 16) +/* Receive Bus Error Interrupt */ +#define REG_MISTA_RXBERR (1 << 11) +/* Receive Descriptor Unavailable Interrupt */ +#define REG_MISTA_RDU (1 << 10) +/* DMA Early Notification Interrupt */ +#define REG_MISTA_DENI (1 << 9) +/* Maximum Frame Length Interrupt */ +#define REG_MISTA_DFOI (1 << 8) +/* Receive Good Interrupt */ +#define REG_MISTA_RXGD (1 << 4) +/* Packet Too Long Interrupt */ +#define REG_MISTA_PTLE (1 << 3) +/* Receive Interrupt */ +#define REG_MISTA_RXINTR (1 << 0) + +/* REG_MGSTA fields */ +/* Transmission Halted */ +#define REG_MGSTA_TXHA (1 << 11) +/* Receive Halted */ +#define REG_MGSTA_RXHA (1 << 11) + +/* REG_DMARFC fields */ +/* Maximum Receive Frame Length */ +#define REG_DMARFC_RXMS(word) extract32((word), 0, 16) + +/* REG MIIDA fields */ +/* Busy Bit */ +#define REG_MIIDA_BUSY (1 << 17) + +/* Transmit and receive descriptors */ +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; + +struct NPCM7xxEMCTxDesc { + uint32_t flags; + uint32_t txbsa; + uint32_t status_and_length; + uint32_t ntxdsa; +}; + +struct NPCM7xxEMCRxDesc { + uint32_t status_and_length; + uint32_t rxbsa; + uint32_t reserved; + uint32_t nrxdsa; +}; + +/* NPCM7xxEMCTxDesc.flags values */ +/* Owner: 0 = cpu, 1 = emc */ +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) +/* Transmit interrupt enable */ +#define TX_DESC_FLAG_INTEN (1 << 2) +/* CRC append */ +#define TX_DESC_FLAG_CRCAPP (1 << 1) +/* Padding enable */ +#define TX_DESC_FLAG_PADEN (1 << 0) + +/* NPCM7xxEMCTxDesc.status_and_length values */ +/* Collision count */ +#define TX_DESC_STATUS_CCNT_SHIFT 28 +#define TX_DESC_STATUS_CCNT_BITSIZE 4 +/* SQE error */ +#define TX_DESC_STATUS_SQE (1 << 26) +/* Transmission paused */ +#define TX_DESC_STATUS_PAU (1 << 25) +/* P transmission halted */ +#define TX_DESC_STATUS_TXHA (1 << 24) +/* Late collision */ +#define TX_DESC_STATUS_LC (1 << 23) +/* Transmission abort */ +#define TX_DESC_STATUS_TXABT (1 << 22) +/* No carrier sense */ +#define TX_DESC_STATUS_NCS (1 << 21) +/* Defer exceed */ +#define TX_DESC_STATUS_EXDEF (1 << 20) +/* Transmission complete */ +#define TX_DESC_STATUS_TXCP (1 << 19) +/* Transmission deferred */ +#define TX_DESC_STATUS_DEF (1 << 17) +/* Transmit interrupt */ +#define TX_DESC_STATUS_TXINTR (1 << 16) + +#define TX_DESC_PKT_LEN(word) extract32((word), 0, 16) + +/* Transmit buffer start address */ +#define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u) + +/* Next transmit descriptor start address */ +#define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u) + +/* NPCM7xxEMCRxDesc.status_and_length values */ +/* Owner: 0b00 = cpu, 0b01 = undefined, 0b10 = emc, 0b11 = undefined */ +#define RX_DESC_STATUS_OWNER_SHIFT 30 +#define RX_DESC_STATUS_OWNER_BITSIZE 2 +#define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT) +/* Runt packet */ +#define RX_DESC_STATUS_RP (1 << 22) +/* Alignment error */ +#define RX_DESC_STATUS_ALIE (1 << 21) +/* Frame reception complete */ +#define RX_DESC_STATUS_RXGD (1 << 20) +/* Packet too long */ +#define RX_DESC_STATUS_PTLE (1 << 19) +/* CRC error */ +#define RX_DESC_STATUS_CRCE (1 << 17) +/* Receive interrupt */ +#define RX_DESC_STATUS_RXINTR (1 << 16) + +#define RX_DESC_PKT_LEN(word) extract32((word), 0, 16) + +/* Receive buffer start address */ +#define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u) + +/* Next receive descriptor start address */ +#define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u) + +/* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */ +#define MIN_PACKET_LENGTH 64 + +struct NPCM7xxEMCState { + /*< private >*/ + SysBusDevice parent; + /*< public >*/ + + MemoryRegion iomem; + + qemu_irq tx_irq; + qemu_irq rx_irq; + + NICState *nic; + NICConf conf; + + /* 0 or 1, for log messages */ + uint8_t emc_num; + + uint32_t regs[NPCM7XX_NUM_EMC_REGS]; + + /* + * tx is active. Set to true by TSDR and then switches off when out of + * descriptors. If the TXON bit in REG_MCMDR is off then this is off. + */ + bool tx_active; + + /* + * rx is active. Set to true by RSDR and then switches off when out of + * descriptors. If the RXON bit in REG_MCMDR is off then this is off. + */ + bool rx_active; +}; + +typedef struct NPCM7xxEMCState NPCM7xxEMCState; + +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" +#define NPCM7XX_EMC(obj) \ + OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC) + +#endif /* NPCM7XX_EMC_H */ diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/net/npcm7xx_emc.c @@ -XXX,XX +XXX,XX @@ +/* + * Nuvoton NPCM7xx EMC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * Unsupported/unimplemented features: + * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported + * - Only CAM0 is supported, CAM[1-15] are not + * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes + * - MII is not implemented, MIIDA.BUSY and MIID always return zero + * - MCMDR.LBK is not implemented + * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported + * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored + * - MGSTA.SQE is not supported + * - pause and control frames are not implemented + * - MGSTA.CCNT is not supported + * - MPCNT, DMARFS are not implemented + */ + +#include "qemu/osdep.h" + +/* For crc32 */ +#include <zlib.h> + +#include "qemu-common.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/net/npcm7xx_emc.h" +#include "net/eth.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "sysemu/dma.h" +#include "trace.h" + +#define CRC_LENGTH 4 + +/* + * The maximum size of a (layer 2) ethernet frame as defined by 802.3. + * 1518 = 6(dest macaddr) + 6(src macaddr) + 2(proto) + 4(crc) + 1500(payload) + * This does not include an additional 4 for the vlan field (802.1q). + */ +#define MAX_ETH_FRAME_SIZE 1518 + +static const char *emc_reg_name(int regno) +{ +#define REG(name) case REG_ ## name: return #name; + switch (regno) { + REG(CAMCMR) + REG(CAMEN) + REG(TXDLSA) + REG(RXDLSA) + REG(MCMDR) + REG(MIID) + REG(MIIDA) + REG(FFTCR) + REG(TSDR) + REG(RSDR) + REG(DMARFC) + REG(MIEN) + REG(MISTA) + REG(MGSTA) + REG(MPCNT) + REG(MRPC) + REG(MRPCC) + REG(MREPC) + REG(DMARFS) + REG(CTXDSA) + REG(CTXBSA) + REG(CRXDSA) + REG(CRXBSA) + case REG_CAMM_BASE + 0: return "CAM0M"; + case REG_CAML_BASE + 0: return "CAM0L"; + case REG_CAMM_BASE + 2 ... REG_CAMML_LAST: + /* Only CAM0 is supported, fold the others into something simple. */ + if (regno & 1) { + return "CAM<n>L"; + } else { + return "CAM<n>M"; + } + default: return "UNKNOWN"; + } +#undef REG +} + +static void emc_reset(NPCM7xxEMCState *emc) +{ + trace_npcm7xx_emc_reset(emc->emc_num); + + memset(&emc->regs[0], 0, sizeof(emc->regs)); + + /* These regs have non-zero reset values. */ + emc->regs[REG_TXDLSA] = 0xfffffffc; + emc->regs[REG_RXDLSA] = 0xfffffffc; + emc->regs[REG_MIIDA] = 0x00900000; + emc->regs[REG_FFTCR] = 0x0101; + emc->regs[REG_DMARFC] = 0x0800; + emc->regs[REG_MPCNT] = 0x7fff; + + emc->tx_active = false; + emc->rx_active = false; +} + +static void npcm7xx_emc_reset(DeviceState *dev) +{ + NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); + emc_reset(emc); +} + +static void emc_soft_reset(NPCM7xxEMCState *emc) +{ + /* + * The docs say at least MCMDR.{LBK,OPMOD} bits are not changed during a + * soft reset, but does not go into further detail. For now, KISS. + */ + uint32_t mcmdr = emc->regs[REG_MCMDR]; + emc_reset(emc); + emc->regs[REG_MCMDR] = mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); + + qemu_set_irq(emc->tx_irq, 0); + qemu_set_irq(emc->rx_irq, 0); +} + +static void emc_set_link(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +/* MISTA.TXINTR is the union of the individual bits with their enables. */ +static void emc_update_mista_txintr(NPCM7xxEMCState *emc) +{ + /* Only look at the bits we support. */ + uint32_t mask = (REG_MISTA_TXBERR | + REG_MISTA_TDU | + REG_MISTA_TXCP); + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { + emc->regs[REG_MISTA] |= REG_MISTA_TXINTR; + } else { + emc->regs[REG_MISTA] &= ~REG_MISTA_TXINTR; + } +} + +/* MISTA.RXINTR is the union of the individual bits with their enables. */ +static void emc_update_mista_rxintr(NPCM7xxEMCState *emc) +{ + /* Only look at the bits we support. */ + uint32_t mask = (REG_MISTA_RXBERR | + REG_MISTA_RDU | + REG_MISTA_RXGD); + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { + emc->regs[REG_MISTA] |= REG_MISTA_RXINTR; + } else { + emc->regs[REG_MISTA] &= ~REG_MISTA_RXINTR; + } +} + +/* N.B. emc_update_mista_txintr must have already been called. */ +static void emc_update_tx_irq(NPCM7xxEMCState *emc) +{ + int level = !!(emc->regs[REG_MISTA] & + emc->regs[REG_MIEN] & + REG_MISTA_TXINTR); + trace_npcm7xx_emc_update_tx_irq(level); + qemu_set_irq(emc->tx_irq, level); +} + +/* N.B. emc_update_mista_rxintr must have already been called. */ +static void emc_update_rx_irq(NPCM7xxEMCState *emc) +{ + int level = !!(emc->regs[REG_MISTA] & + emc->regs[REG_MIEN] & + REG_MISTA_RXINTR); + trace_npcm7xx_emc_update_rx_irq(level); + qemu_set_irq(emc->rx_irq, level); +} + +/* Update IRQ states due to changes in MIEN,MISTA. */ +static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc) +{ + emc_update_mista_txintr(emc); + emc_update_tx_irq(emc); + + emc_update_mista_rxintr(emc); + emc_update_rx_irq(emc); +} + +static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->flags = le32_to_cpu(desc->flags); + desc->txbsa = le32_to_cpu(desc->txbsa); + desc->status_and_length = le32_to_cpu(desc->status_and_length); + desc->ntxdsa = le32_to_cpu(desc->ntxdsa); + return 0; +} + +static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr) +{ + NPCM7xxEMCTxDesc le_desc; + + le_desc.flags = cpu_to_le32(desc->flags); + le_desc.txbsa = cpu_to_le32(desc->txbsa); + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); + le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->status_and_length = le32_to_cpu(desc->status_and_length); + desc->rxbsa = le32_to_cpu(desc->rxbsa); + desc->reserved = le32_to_cpu(desc->reserved); + desc->nrxdsa = le32_to_cpu(desc->nrxdsa); + return 0; +} + +static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr) +{ + NPCM7xxEMCRxDesc le_desc; + + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); + le_desc.rxbsa = cpu_to_le32(desc->rxbsa); + le_desc.reserved = cpu_to_le32(desc->reserved); + le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static void emc_set_mista(NPCM7xxEMCState *emc, uint32_t flags) +{ + trace_npcm7xx_emc_set_mista(flags); + emc->regs[REG_MISTA] |= flags; + if (extract32(flags, 16, 16)) { + emc_update_mista_txintr(emc); + } + if (extract32(flags, 0, 16)) { + emc_update_mista_rxintr(emc); + } +} + +static void emc_halt_tx(NPCM7xxEMCState *emc, uint32_t mista_flag) +{ + emc->tx_active = false; + emc_set_mista(emc, mista_flag); +} + +static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) +{ + emc->rx_active = false; + emc_set_mista(emc, mista_flag); +} + +static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, + const NPCM7xxEMCTxDesc *tx_desc, + uint32_t desc_addr) +{ + /* Update the current descriptor, if only to reset the owner flag. */ + if (emc_write_tx_desc(tx_desc, desc_addr)) { + /* + * We just read it so this shouldn't generally happen. + * Error already reported. + */ + emc_set_mista(emc, REG_MISTA_TXBERR); + } + emc->regs[REG_CTXDSA] = TX_DESC_NTXDSA(tx_desc->ntxdsa); +} + +static void emc_set_next_rx_descriptor(NPCM7xxEMCState *emc, + const NPCM7xxEMCRxDesc *rx_desc, + uint32_t desc_addr) +{ + /* Update the current descriptor, if only to reset the owner flag. */ + if (emc_write_rx_desc(rx_desc, desc_addr)) { + /* + * We just read it so this shouldn't generally happen. + * Error already reported. + */ + emc_set_mista(emc, REG_MISTA_RXBERR); + } + emc->regs[REG_CRXDSA] = RX_DESC_NRXDSA(rx_desc->nrxdsa); +} + +static void emc_try_send_next_packet(NPCM7xxEMCState *emc) +{ + /* Working buffer for sending out packets. Most packets fit in this. */ +#define TX_BUFFER_SIZE 2048 + uint8_t tx_send_buffer[TX_BUFFER_SIZE]; + uint32_t desc_addr = TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]); + NPCM7xxEMCTxDesc tx_desc; + uint32_t next_buf_addr, length; + uint8_t *buf; + g_autofree uint8_t *malloced_buf = NULL; + + if (emc_read_tx_desc(desc_addr, &tx_desc)) { + /* Error reading descriptor, already reported. */ + emc_halt_tx(emc, REG_MISTA_TXBERR); + emc_update_tx_irq(emc); + return; + } + + /* Nothing we can do if we don't own the descriptor. */ + if (!(tx_desc.flags & TX_DESC_FLAG_OWNER_MASK)) { + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); + emc_halt_tx(emc, REG_MISTA_TDU); + emc_update_tx_irq(emc); + return; + } + + /* Give the descriptor back regardless of what happens. */ + tx_desc.flags &= ~TX_DESC_FLAG_OWNER_MASK; + tx_desc.status_and_length &= 0xffff; + + /* + * Despite the h/w documentation saying the tx buffer is word aligned, + * the linux driver does not word align the buffer. There is value in not + * aligning the buffer: See the description of NET_IP_ALIGN in linux + * kernel sources. + */ + next_buf_addr = tx_desc.txbsa; + emc->regs[REG_CTXBSA] = next_buf_addr; + length = TX_DESC_PKT_LEN(tx_desc.status_and_length); + buf = &tx_send_buffer[0]; + + if (length > sizeof(tx_send_buffer)) { + malloced_buf = g_malloc(length); + buf = malloced_buf; + } + + if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n", + __func__, next_buf_addr); + emc_set_mista(emc, REG_MISTA_TXBERR); + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); + emc_update_tx_irq(emc); + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); + return; + } + + if ((tx_desc.flags & TX_DESC_FLAG_PADEN) && (length < MIN_PACKET_LENGTH)) { + memset(buf + length, 0, MIN_PACKET_LENGTH - length); + length = MIN_PACKET_LENGTH; + } + + /* N.B. emc_receive can get called here. */ + qemu_send_packet(qemu_get_queue(emc->nic), buf, length); + trace_npcm7xx_emc_sent_packet(length); + + tx_desc.status_and_length |= TX_DESC_STATUS_TXCP; + if (tx_desc.flags & TX_DESC_FLAG_INTEN) { + emc_set_mista(emc, REG_MISTA_TXCP); + } + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) { + tx_desc.status_and_length |= TX_DESC_STATUS_TXINTR; + } + + emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr); + emc_update_tx_irq(emc); + trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); +} + +static bool emc_can_receive(NetClientState *nc) +{ + NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc)); + + bool can_receive = emc->rx_active; + trace_npcm7xx_emc_can_receive(can_receive); + return can_receive; +} + +/* If result is false then *fail_reason contains the reason. */ +static bool emc_receive_filter1(NPCM7xxEMCState *emc, const uint8_t *buf, + size_t len, const char **fail_reason) +{ + eth_pkt_types_e pkt_type = get_eth_packet_type(PKT_GET_ETH_HDR(buf)); + + switch (pkt_type) { + case ETH_PKT_BCAST: + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + return true; + } else { + *fail_reason = "Broadcast packet disabled"; + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP); + } + case ETH_PKT_MCAST: + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + return true; + } else { + *fail_reason = "Multicast packet disabled"; + return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP); + } + case ETH_PKT_UCAST: { + bool matches; + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) { + return true; + } + matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) && + /* We only support one CAM register, CAM0. */ + (emc->regs[REG_CAMEN] & (1 << 0)) && + memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) == 0); + if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { + *fail_reason = "MACADDR matched, comparison complemented"; + return !matches; + } else { + *fail_reason = "MACADDR didn't match"; + return matches; + } + } + default: + g_assert_not_reached(); + } +} + +static bool emc_receive_filter(NPCM7xxEMCState *emc, const uint8_t *buf, + size_t len) +{ + const char *fail_reason = NULL; + bool ok = emc_receive_filter1(emc, buf, len, &fail_reason); + if (!ok) { + trace_npcm7xx_emc_packet_filtered_out(fail_reason); + } + return ok; +} + +static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) +{ + NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc)); + const uint32_t len = len1; + size_t max_frame_len; + bool long_frame; + uint32_t desc_addr; + NPCM7xxEMCRxDesc rx_desc; + uint32_t crc; + uint8_t *crc_ptr; + uint32_t buf_addr; + + trace_npcm7xx_emc_receiving_packet(len); + + if (!emc_can_receive(nc)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__); + return -1; + } + + if (len < ETH_HLEN || + /* Defensive programming: drop unsupportable large packets. */ + len > 0xffff - CRC_LENGTH) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Dropped frame of %u bytes\n", + __func__, len); + return len; + } + + /* + * DENI is set if EMC received the Length/Type field of the incoming + * packet, so it will be set regardless of what happens next. + */ + emc_set_mista(emc, REG_MISTA_DENI); + + if (!emc_receive_filter(emc, buf, len)) { + emc_update_rx_irq(emc); + return len; + } + + /* Huge frames (> DMARFC) are dropped. */ + max_frame_len = REG_DMARFC_RXMS(emc->regs[REG_DMARFC]); + if (len + CRC_LENGTH > max_frame_len) { + trace_npcm7xx_emc_packet_dropped(len); + emc_set_mista(emc, REG_MISTA_DFOI); + emc_update_rx_irq(emc); + return len; + } + + /* + * Long Frames (> MAX_ETH_FRAME_SIZE) are also dropped, unless MCMDR.ALP + * is set. + */ + long_frame = false; + if (len + CRC_LENGTH > MAX_ETH_FRAME_SIZE) { + if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { + long_frame = true; + } else { + trace_npcm7xx_emc_packet_dropped(len); + emc_set_mista(emc, REG_MISTA_PTLE); + emc_update_rx_irq(emc); + return len; + } + } + + desc_addr = RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]); + if (emc_read_rx_desc(desc_addr, &rx_desc)) { + /* Error reading descriptor, already reported. */ + emc_halt_rx(emc, REG_MISTA_RXBERR); + emc_update_rx_irq(emc); + return len; + } + + /* Nothing we can do if we don't own the descriptor. */ + if (!(rx_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK)) { + trace_npcm7xx_emc_cpu_owned_desc(desc_addr); + emc_halt_rx(emc, REG_MISTA_RDU); + emc_update_rx_irq(emc); + return len; + } + + crc = 0; + crc_ptr = (uint8_t *) &crc; + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { + crc = cpu_to_be32(crc32(~0, buf, len)); + } + + /* Give the descriptor back regardless of what happens. */ + rx_desc.status_and_length &= ~RX_DESC_STATUS_OWNER_MASK; + + buf_addr = rx_desc.rxbsa; + emc->regs[REG_CRXBSA] = buf_addr; + if (dma_memory_write(&address_space_memory, buf_addr, buf, len) || + (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && + dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr, + 4))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n", + __func__); + emc_set_mista(emc, REG_MISTA_RXBERR); + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); + emc_update_rx_irq(emc); + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); + return len; + } + + trace_npcm7xx_emc_received_packet(len); + + /* Note: We've already verified len+4 <= 0xffff. */ + rx_desc.status_and_length = len; + if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { + rx_desc.status_and_length += 4; + } + rx_desc.status_and_length |= RX_DESC_STATUS_RXGD; + emc_set_mista(emc, REG_MISTA_RXGD); + + if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) { + rx_desc.status_and_length |= RX_DESC_STATUS_RXINTR; + } + if (long_frame) { + rx_desc.status_and_length |= RX_DESC_STATUS_PTLE; + } + + emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr); + emc_update_rx_irq(emc); + trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); + return len; +} + +static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) +{ + if (emc_can_receive(qemu_get_queue(emc->nic))) { + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); + } +} + +static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCM7xxEMCState *emc = opaque; + uint32_t reg = offset / sizeof(uint32_t); + uint32_t result; + + if (reg >= NPCM7XX_NUM_EMC_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + return 0; + } + + switch (reg) { + case REG_MIID: + /* + * We don't implement MII. For determinism, always return zero as + * writes record the last value written for debugging purposes. + */ + qemu_log_mask(LOG_UNIMP, "%s: Read of MIID, returning 0\n", __func__); + result = 0; + break; + case REG_TSDR: + case REG_RSDR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Read of write-only reg, %s/%d\n", + __func__, emc_reg_name(reg), reg); + return 0; + default: + result = emc->regs[reg]; + break; + } + + trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), reg); + return result; +} + +static void npcm7xx_emc_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCM7xxEMCState *emc = opaque; + uint32_t reg = offset / sizeof(uint32_t); + uint32_t value = v; + + g_assert(size == sizeof(uint32_t)); + + if (reg >= NPCM7XX_NUM_EMC_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, value); + + switch (reg) { + case REG_CAMCMR: + emc->regs[reg] = value; + break; + case REG_CAMEN: + /* Only CAM0 is supported, don't pretend otherwise. */ + if (value & ~1) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Only CAM0 is supported, cannot enable others" + ": 0x%x\n", + __func__, value); + } + emc->regs[reg] = value & 1; + break; + case REG_CAMM_BASE + 0: + emc->regs[reg] = value; + emc->conf.macaddr.a[0] = value >> 24; + emc->conf.macaddr.a[1] = value >> 16; + emc->conf.macaddr.a[2] = value >> 8; + emc->conf.macaddr.a[3] = value >> 0; + break; + case REG_CAML_BASE + 0: + emc->regs[reg] = value; + emc->conf.macaddr.a[4] = value >> 24; + emc->conf.macaddr.a[5] = value >> 16; + break; + case REG_MCMDR: { + uint32_t prev; + if (value & REG_MCMDR_SWR) { + emc_soft_reset(emc); + /* On h/w the reset happens over multiple cycles. For now KISS. */ + break; + } + prev = emc->regs[reg]; + emc->regs[reg] = value; + /* Update tx state. */ + if (!(prev & REG_MCMDR_TXON) && + (value & REG_MCMDR_TXON)) { + emc->regs[REG_CTXDSA] = emc->regs[REG_TXDLSA]; + /* + * Linux kernel turns TX on with CPU still holding descriptor, + * which suggests we should wait for a write to TSDR before trying + * to send a packet: so we don't send one here. + */ + } else if ((prev & REG_MCMDR_TXON) && + !(value & REG_MCMDR_TXON)) { + emc->regs[REG_MGSTA] |= REG_MGSTA_TXHA; + } + if (!(value & REG_MCMDR_TXON)) { + emc_halt_tx(emc, 0); + } + /* Update rx state. */ + if (!(prev & REG_MCMDR_RXON) && + (value & REG_MCMDR_RXON)) { + emc->regs[REG_CRXDSA] = emc->regs[REG_RXDLSA]; + } else if ((prev & REG_MCMDR_RXON) && + !(value & REG_MCMDR_RXON)) { + emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; + } + if (!(value & REG_MCMDR_RXON)) { + emc_halt_rx(emc, 0); + } + break; + } + case REG_TXDLSA: + case REG_RXDLSA: + case REG_DMARFC: + case REG_MIID: + emc->regs[reg] = value; + break; + case REG_MIEN: + emc->regs[reg] = value; + emc_update_irq_from_reg_change(emc); + break; + case REG_MISTA: + /* Clear the bits that have 1 in "value". */ + emc->regs[reg] &= ~value; + emc_update_irq_from_reg_change(emc); + break; + case REG_MGSTA: + /* Clear the bits that have 1 in "value". */ + emc->regs[reg] &= ~value; + break; + case REG_TSDR: + if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { + emc->tx_active = true; + /* Keep trying to send packets until we run out. */ + while (emc->tx_active) { + emc_try_send_next_packet(emc); + } + } + break; + case REG_RSDR: + if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { + emc->rx_active = true; + emc_try_receive_next_packet(emc); + } + break; + case REG_MIIDA: + emc->regs[reg] = value & ~REG_MIIDA_BUSY; + break; + case REG_MRPC: + case REG_MRPCC: + case REG_MREPC: + case REG_CTXDSA: + case REG_CTXBSA: + case REG_CRXDSA: + case REG_CRXBSA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only reg %s/%d\n", + __func__, emc_reg_name(reg), reg); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Write to unimplemented reg %s/%d\n", + __func__, emc_reg_name(reg), reg); + break; + } +} + +static const struct MemoryRegionOps npcm7xx_emc_ops = { + .read = npcm7xx_emc_read, + .write = npcm7xx_emc_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void emc_cleanup(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +static NetClientInfo net_npcm7xx_emc_info = { + .type = NET_CLIENT_DRIVER_NIC, + .size = sizeof(NICState), + .can_receive = emc_can_receive, + .receive = emc_receive, + .cleanup = emc_cleanup, + .link_status_changed = emc_set_link, +}; + +static void npcm7xx_emc_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(emc); + + memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc, + TYPE_NPCM7XX_EMC, 4 * KiB); + sysbus_init_mmio(sbd, &emc->iomem); + sysbus_init_irq(sbd, &emc->tx_irq); + sysbus_init_irq(sbd, &emc->rx_irq); + + qemu_macaddr_default_if_unset(&emc->conf.macaddr); + emc->nic = qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf, + object_get_typename(OBJECT(dev)), dev->id, emc); + qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a); +} + +static void npcm7xx_emc_unrealize(DeviceState *dev) +{ + NPCM7xxEMCState *emc = NPCM7XX_EMC(dev); + + qemu_del_nic(emc->nic); +} + +static const VMStateDescription vmstate_npcm7xx_emc = { + .name = TYPE_NPCM7XX_EMC, + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8(emc_num, NPCM7xxEMCState), + VMSTATE_UINT32_ARRAY(regs, NPCM7xxEMCState, NPCM7XX_NUM_EMC_REGS), + VMSTATE_BOOL(tx_active, NPCM7xxEMCState), + VMSTATE_BOOL(rx_active, NPCM7xxEMCState), + VMSTATE_END_OF_LIST(), + }, +}; + +static Property npcm7xx_emc_properties[] = { + DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); + dc->desc = "NPCM7xx EMC Controller"; + dc->realize = npcm7xx_emc_realize; + dc->unrealize = npcm7xx_emc_unrealize; + dc->reset = npcm7xx_emc_reset; + dc->vmsd = &vmstate_npcm7xx_emc; + device_class_set_props(dc, npcm7xx_emc_properties); +} + +static const TypeInfo npcm7xx_emc_info = { + .name = TYPE_NPCM7XX_EMC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxEMCState), + .class_init = npcm7xx_emc_class_init, +}; + +static void npcm7xx_emc_register_type(void) +{ + type_register_static(&npcm7xx_emc_info); +} + +type_init(npcm7xx_emc_register_type) diff --git a/hw/net/meson.build b/hw/net/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_I82596_COMMON', if_true: files('i82596.c')) softmmu_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c')) softmmu_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) softmmu_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c')) softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c')) softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) diff --git a/hw/net/trace-events b/hw/net/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -XXX,XX +XXX,XX @@ imx_fec_receive_last(int last) "rx frame flags 0x%04x" imx_enet_receive(size_t size) "len %zu" imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" imx_enet_receive_last(int last) "rx frame flags 0x%04x" + +# npcm7xx_emc.c +npcm7xx_emc_reset(int emc_num) "Resetting emc%d" +npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" +npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" +npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" +npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descriptor @0x%x" +npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" +npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=0x%x" +npcm7xx_emc_can_receive(int can_receive) "Can receive: %d" +npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered out: %s" +npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" +npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" +npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" +npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=0x%x" +npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno) "emc%d: 0x%x = reg[%s/%d]" +npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value) "emc%d: reg[%s/%d] = 0x%x" -- 2.20.1 From: Doug Evans <dje@google.com> This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-3-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- docs/system/arm/nuvoton.rst | 3 ++- include/hw/arm/npcm7xx.h | 2 ++ hw/arm/npcm7xx.c | 50 +++++++++++++++++++++++++++++++++++-- 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -XXX,XX +XXX,XX @@ Supported devices * Analog to Digital Converter (ADC) * Pulse Width Modulation (PWM) * SMBus controller (SMBF) + * Ethernet controller (EMC) Missing devices --------------- @@ -XXX,XX +XXX,XX @@ Missing devices * Shared memory (SHM) * eSPI slave interface - * Ethernet controllers (GMAC and EMC) + * Ethernet controller (GMAC) * USB device (USBD) * Peripheral SPI controller (PSPI) * SD/MMC host diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/npcm7xx_gcr.h" #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" +#include "hw/net/npcm7xx_emc.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; + NPCM7xxEMCState emc[2]; } NPCM7xxState; #define TYPE_NPCM7XX "npcm7xx" diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, NPCM7XX_UART3_IRQ, + NPCM7XX_EMC1RX_IRQ = 15, + NPCM7XX_EMC1TX_IRQ, NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ NPCM7XX_TIMER1_IRQ, NPCM7XX_TIMER2_IRQ, @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { NPCM7XX_SMBUS15_IRQ, NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ NPCM7XX_PWM1_IRQ, /* PWM module 1 */ + NPCM7XX_EMC2RX_IRQ = 114, + NPCM7XX_EMC2TX_IRQ, NPCM7XX_GPIO0_IRQ = 116, NPCM7XX_GPIO1_IRQ, NPCM7XX_GPIO2_IRQ, @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_smbus_addr[] = { 0xf008f000, }; +/* Register base address for each EMC Module */ +static const hwaddr npcm7xx_emc_addr[] = { + 0xf0825000, + 0xf0826000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); } + + for (i = 0; i < ARRAY_SIZE(s->emc); i++) { + object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); + } } static void npcm7xx_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); } + /* + * EMC Modules. Cannot fail. + * The mapping of the device to its netdev backend works as follows: + * emc[i] = nd_table[i] + * This works around the inability to specify the netdev property for the + * emc device: it's not pluggable and thus the -device option can't be + * used. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc)); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2); + for (i = 0; i < ARRAY_SIZE(s->emc); i++) { + s->emc[i].emc_num = i; + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]); + if (nd_table[i].used) { + qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC); + qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); + } + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]); + int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ; + int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ; + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq)); + sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects * specified, but this is a programming error. @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); - create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB); - create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB); create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB); create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB); create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB); -- 2.20.1 From: Doug Evans <dje@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-4-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 2 files changed, 864 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/npcm7xx_emc-test.c diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/qtest/npcm7xx_emc-test.c @@ -XXX,XX +XXX,XX @@ +/* + * QTests for Nuvoton NPCM7xx EMC Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "libqos/libqos.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" +#include "qemu/bitops.h" +#include "qemu/iov.h" + +/* Name of the emc device. */ +#define TYPE_NPCM7XX_EMC "npcm7xx-emc" + +/* Timeout for various operations, in seconds. */ +#define TIMEOUT_SECONDS 10 + +/* Address in memory of the descriptor. */ +#define DESC_ADDR (1 << 20) /* 1 MiB */ + +/* Address in memory of the data packet. */ +#define DATA_ADDR (DESC_ADDR + 4096) + +#define CRC_LENGTH 4 + +#define NUM_TX_DESCRIPTORS 3 +#define NUM_RX_DESCRIPTORS 2 + +/* Size of tx,rx test buffers. */ +#define TX_DATA_LEN 64 +#define RX_DATA_LEN 64 + +#define TX_STEP_COUNT 10000 +#define RX_STEP_COUNT 10000 + +/* 32-bit register indices. */ +typedef enum NPCM7xxPWMRegister { + /* Control registers. */ + REG_CAMCMR, + REG_CAMEN, + + /* There are 16 CAMn[ML] registers. */ + REG_CAMM_BASE, + REG_CAML_BASE, + + REG_TXDLSA = 0x22, + REG_RXDLSA, + REG_MCMDR, + REG_MIID, + REG_MIIDA, + REG_FFTCR, + REG_TSDR, + REG_RSDR, + REG_DMARFC, + REG_MIEN, + + /* Status registers. */ + REG_MISTA, + REG_MGSTA, + REG_MPCNT, + REG_MRPC, + REG_MRPCC, + REG_MREPC, + REG_DMARFS, + REG_CTXDSA, + REG_CTXBSA, + REG_CRXDSA, + REG_CRXBSA, + + NPCM7XX_NUM_EMC_REGS, +} NPCM7xxPWMRegister; + +enum { NUM_CAMML_REGS = 16 }; + +/* REG_CAMCMR fields */ +/* Enable CAM Compare */ +#define REG_CAMCMR_ECMP (1 << 4) +/* Accept Unicast Packet */ +#define REG_CAMCMR_AUP (1 << 0) + +/* REG_MCMDR fields */ +/* Software Reset */ +#define REG_MCMDR_SWR (1 << 24) +/* Frame Transmission On */ +#define REG_MCMDR_TXON (1 << 8) +/* Accept Long Packet */ +#define REG_MCMDR_ALP (1 << 1) +/* Frame Reception On */ +#define REG_MCMDR_RXON (1 << 0) + +/* REG_MIEN fields */ +/* Enable Transmit Completion Interrupt */ +#define REG_MIEN_ENTXCP (1 << 18) +/* Enable Transmit Interrupt */ +#define REG_MIEN_ENTXINTR (1 << 16) +/* Enable Receive Good Interrupt */ +#define REG_MIEN_ENRXGD (1 << 4) +/* ENable Receive Interrupt */ +#define REG_MIEN_ENRXINTR (1 << 0) + +/* REG_MISTA fields */ +/* Transmit Bus Error Interrupt */ +#define REG_MISTA_TXBERR (1 << 24) +/* Transmit Descriptor Unavailable Interrupt */ +#define REG_MISTA_TDU (1 << 23) +/* Transmit Completion Interrupt */ +#define REG_MISTA_TXCP (1 << 18) +/* Transmit Interrupt */ +#define REG_MISTA_TXINTR (1 << 16) +/* Receive Bus Error Interrupt */ +#define REG_MISTA_RXBERR (1 << 11) +/* Receive Descriptor Unavailable Interrupt */ +#define REG_MISTA_RDU (1 << 10) +/* DMA Early Notification Interrupt */ +#define REG_MISTA_DENI (1 << 9) +/* Maximum Frame Length Interrupt */ +#define REG_MISTA_DFOI (1 << 8) +/* Receive Good Interrupt */ +#define REG_MISTA_RXGD (1 << 4) +/* Packet Too Long Interrupt */ +#define REG_MISTA_PTLE (1 << 3) +/* Receive Interrupt */ +#define REG_MISTA_RXINTR (1 << 0) + +typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; +typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; + +struct NPCM7xxEMCTxDesc { + uint32_t flags; + uint32_t txbsa; + uint32_t status_and_length; + uint32_t ntxdsa; +}; + +struct NPCM7xxEMCRxDesc { + uint32_t status_and_length; + uint32_t rxbsa; + uint32_t reserved; + uint32_t nrxdsa; +}; + +/* NPCM7xxEMCTxDesc.flags values */ +/* Owner: 0 = cpu, 1 = emc */ +#define TX_DESC_FLAG_OWNER_MASK (1 << 31) +/* Transmit interrupt enable */ +#define TX_DESC_FLAG_INTEN (1 << 2) + +/* NPCM7xxEMCTxDesc.status_and_length values */ +/* Transmission complete */ +#define TX_DESC_STATUS_TXCP (1 << 19) +/* Transmit interrupt */ +#define TX_DESC_STATUS_TXINTR (1 << 16) + +/* NPCM7xxEMCRxDesc.status_and_length values */ +/* Owner: 0b00 = cpu, 0b10 = emc */ +#define RX_DESC_STATUS_OWNER_SHIFT 30 +#define RX_DESC_STATUS_OWNER_MASK 0xc0000000 +/* Frame Reception Complete */ +#define RX_DESC_STATUS_RXGD (1 << 20) +/* Packet too long */ +#define RX_DESC_STATUS_PTLE (1 << 19) +/* Receive Interrupt */ +#define RX_DESC_STATUS_RXINTR (1 << 16) + +#define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff) + +typedef struct EMCModule { + int rx_irq; + int tx_irq; + uint64_t base_addr; +} EMCModule; + +typedef struct TestData { + const EMCModule *module; +} TestData; + +static const EMCModule emc_module_list[] = { + { + .rx_irq = 15, + .tx_irq = 16, + .base_addr = 0xf0825000 + }, + { + .rx_irq = 114, + .tx_irq = 115, + .base_addr = 0xf0826000 + } +}; + +/* Returns the index of the EMC module. */ +static int emc_module_index(const EMCModule *mod) +{ + ptrdiff_t diff = mod - emc_module_list; + + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list)); + + return diff; +} + +static void packet_test_clear(void *sockets) +{ + int *test_sockets = sockets; + + close(test_sockets[0]); + g_free(test_sockets); +} + +static int *packet_test_init(int module_num, GString *cmd_line) +{ + int *test_sockets = g_new(int, 2); + int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets); + g_assert_cmpint(ret, != , -1); + + /* + * KISS and use -nic. We specify two nics (both emc{0,1}) because there's + * currently no way to specify only emc1: The driver implicitly relies on + * emc[i] == nd_table[i]. + */ + if (module_num == 0) { + g_string_append_printf(cmd_line, + " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " " + " -nic user,model=" TYPE_NPCM7XX_EMC " ", + test_sockets[1]); + } else { + g_string_append_printf(cmd_line, + " -nic user,model=" TYPE_NPCM7XX_EMC " " + " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ", + test_sockets[1]); + } + + g_test_queue_destroy(packet_test_clear, test_sockets); + return test_sockets; +} + +static uint32_t emc_read(QTestState *qts, const EMCModule *mod, + NPCM7xxPWMRegister regno) +{ + return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); +} + +static void emc_write(QTestState *qts, const EMCModule *mod, + NPCM7xxPWMRegister regno, uint32_t value) +{ + qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); +} + +static void emc_read_tx_desc(QTestState *qts, uint32_t addr, + NPCM7xxEMCTxDesc *desc) +{ + qtest_memread(qts, addr, desc, sizeof(*desc)); + desc->flags = le32_to_cpu(desc->flags); + desc->txbsa = le32_to_cpu(desc->txbsa); + desc->status_and_length = le32_to_cpu(desc->status_and_length); + desc->ntxdsa = le32_to_cpu(desc->ntxdsa); +} + +static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc, + uint32_t addr) +{ + NPCM7xxEMCTxDesc le_desc; + + le_desc.flags = cpu_to_le32(desc->flags); + le_desc.txbsa = cpu_to_le32(desc->txbsa); + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); + le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); + qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); +} + +static void emc_read_rx_desc(QTestState *qts, uint32_t addr, + NPCM7xxEMCRxDesc *desc) +{ + qtest_memread(qts, addr, desc, sizeof(*desc)); + desc->status_and_length = le32_to_cpu(desc->status_and_length); + desc->rxbsa = le32_to_cpu(desc->rxbsa); + desc->reserved = le32_to_cpu(desc->reserved); + desc->nrxdsa = le32_to_cpu(desc->nrxdsa); +} + +static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc, + uint32_t addr) +{ + NPCM7xxEMCRxDesc le_desc; + + le_desc.status_and_length = cpu_to_le32(desc->status_and_length); + le_desc.rxbsa = cpu_to_le32(desc->rxbsa); + le_desc.reserved = cpu_to_le32(desc->reserved); + le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); + qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); +} + +/* + * Reset the EMC module. + * The module must be reset before, e.g., TXDLSA,RXDLSA are changed. + */ +static bool emc_soft_reset(QTestState *qts, const EMCModule *mod) +{ + uint32_t val; + uint64_t end_time; + + emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); + + /* + * Wait for device to reset as the linux driver does. + * During reset the AHB reads 0 for all registers. So first wait for + * something that resets to non-zero, and then wait for SWR becoming 0. + */ + end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + qtest_clock_step(qts, 100); + val = emc_read(qts, mod, REG_FFTCR); + } while (val == 0 && g_get_monotonic_time() < end_time); + if (val != 0) { + do { + qtest_clock_step(qts, 100); + val = emc_read(qts, mod, REG_MCMDR); + if ((val & REG_MCMDR_SWR) == 0) { + /* + * N.B. The CAMs have been reset here, so macaddr matching of + * incoming packets will not work. + */ + return true; + } + } while (g_get_monotonic_time() < end_time); + } + + g_message("%s: Timeout expired", __func__); + return false; +} + +/* Check emc registers are reset to default value. */ +static void test_init(gconstpointer test_data) +{ + const TestData *td = test_data; + const EMCModule *mod = td->module; + QTestState *qts = qtest_init("-machine quanta-gsj"); + int i; + +#define CHECK_REG(regno, value) \ + do { \ + g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \ + } while (0) + + CHECK_REG(REG_CAMCMR, 0); + CHECK_REG(REG_CAMEN, 0); + CHECK_REG(REG_TXDLSA, 0xfffffffc); + CHECK_REG(REG_RXDLSA, 0xfffffffc); + CHECK_REG(REG_MCMDR, 0); + CHECK_REG(REG_MIID, 0); + CHECK_REG(REG_MIIDA, 0x00900000); + CHECK_REG(REG_FFTCR, 0x0101); + CHECK_REG(REG_DMARFC, 0x0800); + CHECK_REG(REG_MIEN, 0); + CHECK_REG(REG_MISTA, 0); + CHECK_REG(REG_MGSTA, 0); + CHECK_REG(REG_MPCNT, 0x7fff); + CHECK_REG(REG_MRPC, 0); + CHECK_REG(REG_MRPCC, 0); + CHECK_REG(REG_MREPC, 0); + CHECK_REG(REG_DMARFS, 0); + CHECK_REG(REG_CTXDSA, 0); + CHECK_REG(REG_CTXBSA, 0); + CHECK_REG(REG_CRXDSA, 0); + CHECK_REG(REG_CRXBSA, 0); + +#undef CHECK_REG + + for (i = 0; i < NUM_CAMML_REGS; ++i) { + g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==, + 0); + g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==, + 0); + } + + qtest_quit(qts); +} + +static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step, + bool is_tx) +{ + uint64_t end_time = + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) { + return true; + } + qtest_clock_step(qts, step); + } while (g_get_monotonic_time() < end_time); + + g_message("%s: Timeout expired", __func__); + return false; +} + +static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step, + uint32_t flag) +{ + uint64_t end_time = + g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; + + do { + uint32_t mista = emc_read(qts, mod, REG_MISTA); + if (mista & flag) { + return true; + } + qtest_clock_step(qts, step); + } while (g_get_monotonic_time() < end_time); + + g_message("%s: Timeout expired", __func__); + return false; +} + +static bool wait_socket_readable(int fd) +{ + fd_set read_fds; + struct timeval tv; + int rv; + + FD_ZERO(&read_fds); + FD_SET(fd, &read_fds); + tv.tv_sec = TIMEOUT_SECONDS; + tv.tv_usec = 0; + rv = select(fd + 1, &read_fds, NULL, NULL, &tv); + if (rv == -1) { + perror("select"); + } else if (rv == 0) { + g_message("%s: Timeout expired", __func__); + } + return rv == 1; +} + +/* Initialize *desc (in host endian format). */ +static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count, + uint32_t desc_addr) +{ + g_assert(count >= 2); + memset(&desc[0], 0, sizeof(*desc) * count); + /* Leave the last one alone, owned by the cpu -> stops transmission. */ + for (size_t i = 0; i < count - 1; ++i) { + desc[i].flags = + (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */ + TX_DESC_FLAG_INTEN | + 0 | /* crc append = 0 */ + 0 /* padding enable = 0 */); + desc[i].status_and_length = + (0 | /* collision count = 0 */ + 0 | /* SQE = 0 */ + 0 | /* PAU = 0 */ + 0 | /* TXHA = 0 */ + 0 | /* LC = 0 */ + 0 | /* TXABT = 0 */ + 0 | /* NCS = 0 */ + 0 | /* EXDEF = 0 */ + 0 | /* TXCP = 0 */ + 0 | /* DEF = 0 */ + 0 | /* TXINTR = 0 */ + 0 /* length filled in later */); + desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc); + } +} + +static void enable_tx(QTestState *qts, const EMCModule *mod, + const NPCM7xxEMCTxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t mien_flags) +{ + /* Write the descriptors to guest memory. */ + for (size_t i = 0; i < count; ++i) { + emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); + } + + /* Trigger sending the packet. */ + /* The module must be reset before changing TXDLSA. */ + g_assert(emc_soft_reset(qts, mod)); + emc_write(qts, mod, REG_TXDLSA, desc_addr); + emc_write(qts, mod, REG_CTXDSA, ~0); + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags); + { + uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); + mcmdr |= REG_MCMDR_TXON; + emc_write(qts, mod, REG_MCMDR, mcmdr); + } + + /* Prod the device to send the packet. */ + emc_write(qts, mod, REG_TSDR, 1); +} + +static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq, uint32_t desc_addr, + uint32_t next_desc_addr, + const char *test_data, int test_size) +{ + NPCM7xxEMCTxDesc result_desc; + uint32_t expected_mask, expected_value, recv_len; + int ret; + char buffer[TX_DATA_LEN]; + + g_assert(wait_socket_readable(fd)); + + /* Read the descriptor back. */ + emc_read_tx_desc(qts, desc_addr, &result_desc); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0); + /* Test the status bits, ignoring the length field. */ + expected_mask = 0xffff << 16; + expected_value = TX_DESC_STATUS_TXCP; + if (with_irq) { + expected_value |= TX_DESC_STATUS_TXINTR; + } + g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, + expected_value); + + /* Check data sent to the backend. */ + recv_len = ~0; + ret = qemu_recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT); + g_assert_cmpint(ret, == , sizeof(recv_len)); + + g_assert(wait_socket_readable(fd)); + memset(buffer, 0xff, sizeof(buffer)); + ret = qemu_recv(fd, buffer, test_size, MSG_DONTWAIT); + g_assert_cmpmem(buffer, ret, test_data, test_size); +} + +static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq) +{ + NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS]; + uint32_t desc_addr = DESC_ADDR; + static const char test1_data[] = "TEST1"; + static const char test2_data[] = "Testing 1 2 3 ..."; + uint32_t data1_addr = DATA_ADDR; + uint32_t data2_addr = data1_addr + sizeof(test1_data); + bool got_tdu; + uint32_t end_desc_addr; + + /* Prepare test data buffer. */ + qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data)); + qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data)); + + init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr); + desc[0].txbsa = data1_addr; + desc[0].status_and_length |= sizeof(test1_data); + desc[1].txbsa = data2_addr; + desc[1].status_and_length |= sizeof(test2_data); + + enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, + with_irq ? REG_MIEN_ENTXINTR : 0); + + /* + * It's problematic to observe the interrupt for each packet. + * Instead just wait until all the packets go out. + */ + got_tdu = false; + while (!got_tdu) { + if (with_irq) { + g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT, + /*is_tx=*/true)); + } else { + g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT, + REG_MISTA_TXINTR)); + } + got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU); + /* If we don't have TDU yet, reset the interrupt. */ + if (!got_tdu) { + emc_write(qts, mod, REG_MISTA, + emc_read(qts, mod, REG_MISTA) & 0xffff0000); + } + } + + end_desc_addr = desc_addr + 2 * sizeof(desc[0]); + g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr); + g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==, + REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU); + + emc_send_verify1(qts, mod, fd, with_irq, + desc_addr, end_desc_addr, + test1_data, sizeof(test1_data)); + emc_send_verify1(qts, mod, fd, with_irq, + desc_addr + sizeof(desc[0]), end_desc_addr, + test2_data, sizeof(test2_data)); +} + +/* Initialize *desc (in host endian format). */ +static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t data_addr) +{ + g_assert_true(count >= 2); + memset(desc, 0, sizeof(*desc) * count); + desc[0].rxbsa = data_addr; + desc[0].status_and_length = + (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */ + 0 | /* RP = 0 */ + 0 | /* ALIE = 0 */ + 0 | /* RXGD = 0 */ + 0 | /* PTLE = 0 */ + 0 | /* CRCE = 0 */ + 0 | /* RXINTR = 0 */ + 0 /* length (filled in later) */); + /* Leave the last one alone, owned by the cpu -> stops transmission. */ + desc[0].nrxdsa = desc_addr + sizeof(*desc); +} + +static void enable_rx(QTestState *qts, const EMCModule *mod, + const NPCM7xxEMCRxDesc *desc, size_t count, + uint32_t desc_addr, uint32_t mien_flags, + uint32_t mcmdr_flags) +{ + /* + * Write the descriptor to guest memory. + * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC + * bytes. + */ + for (size_t i = 0; i < count; ++i) { + emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); + } + + /* Trigger receiving the packet. */ + /* The module must be reset before changing RXDLSA. */ + g_assert(emc_soft_reset(qts, mod)); + emc_write(qts, mod, REG_RXDLSA, desc_addr); + emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags); + + /* + * We don't know what the device's macaddr is, so just accept all + * unicast packets (AUP). + */ + emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP); + emc_write(qts, mod, REG_CAMEN, 1 << 0); + { + uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); + mcmdr |= REG_MCMDR_RXON | mcmdr_flags; + emc_write(qts, mod, REG_MCMDR, mcmdr); + } + + /* Prod the device to accept a packet. */ + emc_write(qts, mod, REG_RSDR, 1); +} + +static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, + bool with_irq) +{ + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; + uint32_t desc_addr = DESC_ADDR; + uint32_t data_addr = DATA_ADDR; + int ret; + uint32_t expected_mask, expected_value; + NPCM7xxEMCRxDesc result_desc; + + /* Prepare test data buffer. */ + const char test[RX_DATA_LEN] = "TEST"; + int len = htonl(sizeof(test)); + const struct iovec iov[] = { + { + .iov_base = &len, + .iov_len = sizeof(len), + },{ + .iov_base = (char *) test, + .iov_len = sizeof(test), + }, + }; + + /* + * Reset the device BEFORE sending a test packet, otherwise the packet + * may get swallowed by an active device of an earlier test. + */ + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, + with_irq ? REG_MIEN_ENRXINTR : 0, 0); + + /* Send test packet to device's socket. */ + ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); + g_assert_cmpint(ret, == , sizeof(test) + sizeof(len)); + + /* Wait for RX interrupt. */ + if (with_irq) { + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); + } else { + g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD)); + } + + g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==, + desc_addr + sizeof(desc[0])); + + expected_mask = 0xffff; + expected_value = (REG_MISTA_DENI | + REG_MISTA_RXGD | + REG_MISTA_RXINTR); + g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask), + ==, expected_value); + + /* Read the descriptor back. */ + emc_read_rx_desc(qts, desc_addr, &result_desc); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); + /* Test the status bits, ignoring the length field. */ + expected_mask = 0xffff << 16; + expected_value = RX_DESC_STATUS_RXGD; + if (with_irq) { + expected_value |= RX_DESC_STATUS_RXINTR; + } + g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, + expected_value); + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, + RX_DATA_LEN + CRC_LENGTH); + + { + char buffer[RX_DATA_LEN]; + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); + g_assert_cmpstr(buffer, == , "TEST"); + } +} + +static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd) +{ + NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; + uint32_t desc_addr = DESC_ADDR; + uint32_t data_addr = DATA_ADDR; + int ret; + NPCM7xxEMCRxDesc result_desc; + uint32_t expected_mask, expected_value; + + /* Prepare test data buffer. */ +#define PTLE_DATA_LEN 1600 + char test_data[PTLE_DATA_LEN]; + int len = htonl(sizeof(test_data)); + const struct iovec iov[] = { + { + .iov_base = &len, + .iov_len = sizeof(len), + },{ + .iov_base = (char *) test_data, + .iov_len = sizeof(test_data), + }, + }; + memset(test_data, 42, sizeof(test_data)); + + /* + * Reset the device BEFORE sending a test packet, otherwise the packet + * may get swallowed by an active device of an earlier test. + */ + init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); + enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, + REG_MIEN_ENRXINTR, REG_MCMDR_ALP); + + /* Send test packet to device's socket. */ + ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data)); + g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len)); + + /* Wait for RX interrupt. */ + g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); + + /* Read the descriptor back. */ + emc_read_rx_desc(qts, desc_addr, &result_desc); + /* Descriptor should be owned by cpu now. */ + g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); + /* Test the status bits, ignoring the length field. */ + expected_mask = 0xffff << 16; + expected_value = (RX_DESC_STATUS_RXGD | + RX_DESC_STATUS_PTLE | + RX_DESC_STATUS_RXINTR); + g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, + expected_value); + g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, + PTLE_DATA_LEN + CRC_LENGTH); + + { + char buffer[PTLE_DATA_LEN]; + qtest_memread(qts, data_addr, buffer, sizeof(buffer)); + g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0); + } +} + +static void test_tx(gconstpointer test_data) +{ + const TestData *td = test_data; + GString *cmd_line = g_string_new("-machine quanta-gsj"); + int *test_sockets = packet_test_init(emc_module_index(td->module), + cmd_line); + QTestState *qts = qtest_init(cmd_line->str); + + /* + * TODO: For pedantic correctness test_sockets[0] should be closed after + * the fork and before the exec, but that will require some harness + * improvements. + */ + close(test_sockets[1]); + /* Defensive programming */ + test_sockets[1] = -1; + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false); + emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true); + + qtest_quit(qts); +} + +static void test_rx(gconstpointer test_data) +{ + const TestData *td = test_data; + GString *cmd_line = g_string_new("-machine quanta-gsj"); + int *test_sockets = packet_test_init(emc_module_index(td->module), + cmd_line); + QTestState *qts = qtest_init(cmd_line->str); + + /* + * TODO: For pedantic correctness test_sockets[0] should be closed after + * the fork and before the exec, but that will require some harness + * improvements. + */ + close(test_sockets[1]); + /* Defensive programming */ + test_sockets[1] = -1; + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false); + emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true); + emc_test_ptle(qts, td->module, test_sockets[0]); + + qtest_quit(qts); +} + +static void emc_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name = g_strdup_printf( + "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name); + qtest_add_data_func(full_name, td, fn); +} +#define add_test(name, td) emc_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(emc_module_list)]; + + g_test_init(&argc, &argv, NULL); + + for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) { + TestData *td = &test_data_list[i]; + + td->module = &emc_module_list[i]; + + add_test(init, td); + add_test(tx, td); + add_test(rx, td); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \ 'npcm7xx_rng-test', 'npcm7xx_smbus-test', 'npcm7xx_timer-test', - 'npcm7xx_watchdog_timer-test'] + 'npcm7xx_watchdog_timer-test'] + \ + (slirp.found() ? ['npcm7xx_emc-test'] : []) qtests_arm = \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> We hint the 'has_rpu' property is no longer required since commit 6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line option") which was released in QEMU v2.11.0. Beside, this device is marked 'user_creatable = false', so the only thing that could be setting the property is the board code that creates the device. Since the property is not user-facing, we can remove it without going through the deprecation process. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219144350.1979905-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/xlnx-zynqmp.h | 2 -- hw/arm/xlnx-zynqmp.c | 6 ------ 2 files changed, 8 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { bool secure; /* Has the ARM Virtualization extensions? */ bool virt; - /* Has the RPU subsystem? */ - bool has_rpu; /* CAN bus. */ CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } } - if (s->has_rpu) { - info_report("The 'has_rpu' property is no longer required, to use the " - "RPUs just use -smp 6."); - } - xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); if (err) { error_propagate(errp, err); @@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = { DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), - DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Always perform one call instead of two for 16-byte operands. Use byte loads/stores directly into the vector register file instead of extractions and deposits to a 64-bit local variable. In order to easily receive pointers into the vector register file, convert the helper to the gvec out-of-line signature. Move the helper into vec_helper.c, where it can make use of H1 and clear_tail. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210224230532.276878-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper-a64.h | 2 +- target/arm/helper-a64.c | 32 --------------------- target/arm/translate-a64.c | 58 +++++--------------------------------- target/arm/vec_helper.c | 48 +++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 84 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) -DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32) +DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp) return float64_mul(a, b, fpst); } -uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices, - uint32_t rn, uint32_t numregs) -{ - /* Helper function for SIMD TBL and TBX. We have to do the table - * lookup part for the 64 bits worth of indices we're passed in. - * result is the initial results vector (either zeroes for TBL - * or some guest values for TBX), rn the register number where - * the table starts, and numregs the number of registers in the table. - * We return the results of the lookups. - */ - int shift; - - for (shift = 0; shift < 64; shift += 8) { - int index = extract64(indices, shift, 8); - if (index < 16 * numregs) { - /* Convert index (a byte offset into the virtual table - * which is a series of 128-bit vectors concatenated) - * into the correct register element plus a bit offset - * into that element, bearing in mind that the table - * can wrap around from V31 to V0. - */ - int elt = (rn * 2 + (index >> 3)) % 64; - int bitidx = (index & 7) * 8; - uint64_t *q = aa64_vfp_qreg(env, elt >> 1); - uint64_t val = extract64(q[elt & 1], bitidx, 8); - - result = deposit64(result, shift, 8, val); - } - } - return result; -} - /* 64bit/double versions of the neon float compare functions */ uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) int rm = extract32(insn, 16, 5); int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); - int is_tblx = extract32(insn, 12, 1); - int len = extract32(insn, 13, 2); - TCGv_i64 tcg_resl, tcg_resh, tcg_idx; - TCGv_i32 tcg_regno, tcg_numregs; + int is_tbx = extract32(insn, 12, 1); + int len = (extract32(insn, 13, 2) + 1) * 16; if (op2 != 0) { unallocated_encoding(s); @@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) return; } - /* This does a table lookup: for every byte element in the input - * we index into a table formed from up to four vector registers, - * and then the output is the result of the lookups. Our helper - * function does the lookup operation for a single 64 bit part of - * the input. - */ - tcg_resl = tcg_temp_new_i64(); - tcg_resh = NULL; - - if (is_tblx) { - read_vec_element(s, tcg_resl, rd, 0, MO_64); - } else { - tcg_gen_movi_i64(tcg_resl, 0); - } - - if (is_q) { - tcg_resh = tcg_temp_new_i64(); - if (is_tblx) { - read_vec_element(s, tcg_resh, rd, 1, MO_64); - } else { - tcg_gen_movi_i64(tcg_resh, 0); - } - } - - tcg_idx = tcg_temp_new_i64(); - tcg_regno = tcg_const_i32(rn); - tcg_numregs = tcg_const_i32(len + 1); - read_vec_element(s, tcg_idx, rm, 0, MO_64); - gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, - tcg_regno, tcg_numregs); - if (is_q) { - read_vec_element(s, tcg_idx, rm, 1, MO_64); - gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, - tcg_regno, tcg_numregs); - } - tcg_temp_free_i64(tcg_idx); - tcg_temp_free_i32(tcg_regno); - tcg_temp_free_i32(tcg_numregs); - - write_vec_element(s, tcg_resl, rd, 0, MO_64); - tcg_temp_free_i64(tcg_resl); - - if (is_q) { - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - } - clear_vec_high(s, is_q, rd); + tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rm), cpu_env, + is_q ? 16 : 8, vec_full_reg_size(s), + (len << 6) | (is_tbx << 5) | rn, + gen_helper_simd_tblx); } /* ZIP/UZP/TRN diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -XXX,XX +XXX,XX @@ DO_VRINT_RMODE(gvec_vrint_rm_h, helper_rinth, uint16_t) DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t) #undef DO_VRINT_RMODE + +#ifdef TARGET_AARCH64 +void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc) +{ + const uint8_t *indices = vm; + CPUARMState *env = venv; + size_t oprsz = simd_oprsz(desc); + uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5); + bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1); + uint32_t table_len = desc >> (SIMD_DATA_SHIFT + 6); + union { + uint8_t b[16]; + uint64_t d[2]; + } result; + + /* + * We must construct the final result in a temp, lest the output + * overlaps the input table. For TBL, begin with zero; for TBX, + * begin with the original register contents. Note that we always + * copy 16 bytes here to avoid an extra branch; clearing the high + * bits of the register for oprsz == 8 is handled below. + */ + if (is_tbx) { + memcpy(&result, vd, 16); + } else { + memset(&result, 0, 16); + } + + for (size_t i = 0; i < oprsz; ++i) { + uint32_t index = indices[H1(i)]; + + if (index < table_len) { + /* + * Convert index (a byte offset into the virtual table + * which is a series of 128-bit vectors concatenated) + * into the correct register element, bearing in mind + * that the table can wrap around from V31 to V0. + */ + const uint8_t *table = (const uint8_t *) + aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); + result.b[H1(i)] = table[H1(index % 16)]; + } + } + + memcpy(vd, &result, 16); + clear_tail(vd, oprsz, simd_maxsz(desc)); +} +#endif -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The STATUS register will be reset to IDLE in cnpcm7xx_smbus_enter_reset(), no need to preset it in instance_init(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210228224813.312532-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/i2c/npcm7xx_smbus.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i2c/npcm7xx_smbus.c +++ b/hw/i2c/npcm7xx_smbus.c @@ -XXX,XX +XXX,XX @@ static void npcm7xx_smbus_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); - s->status = NPCM7XX_SMBUS_STATUS_IDLE; } static const VMStateDescription vmstate_npcm7xx_smbus = { -- 2.20.1 From: schspa <schspa@gmail.com> At the moment the following QEMU command line triggers an assertion failure On xlnx-versal SOC: qemu-system-aarch64 \ -machine xlnx-versal-virt -nographic -smp 2 -m 128 \ -fsdev local,id=shareid,path=${HOME}/work,security_model=none \ -device virtio-9p-device,fsdev=shareid,mount_tag=share \ -fsdev local,id=shareid1,path=${HOME}/Music,security_model=none \ -device virtio-9p-device,fsdev=shareid1,mount_tag=share1 qemu-system-aarch64: ../migration/savevm.c:860: vmstate_register_with_alias_id: Assertion `!se->compat || se->instance_id == 0' failed. This problem was fixed on arm virt platform in commit f58b39d2d5b ("virtio-mmio: format transport base address in BusClass.get_dev_path") It works perfectly on arm virt platform. but there is still there on xlnx-versal SOC. The main difference between arm virt and xlnx-versal is they use different way to create virtio-mmio qdev. on arm virt, it calls sysbus_create_simple("virtio-mmio", base, pic[irq]); which will call sysbus_mmio_map internally and assign base address to subsys device mmio correctly. but xlnx-versal's implements won't do this. However, xlnx-versal can't switch to sysbus_create_simple() to create virtio-mmio device. It's because xlnx-versal's cpu use VersalVirt.soc.fpd.apu.mr as it's memory. which is subregion of system_memory. sysbus_create_simple will add virtio to system_memory, which can't be accessed by cpu. Besides, xlnx-versal can't add sysbus_mmio_map api call too, because this will add memory region to system_memory, and it can't be added to VersalVirt.soc.fpd.apu.mr again. We can solve this by assign correct base address offset on dev_path. This path was test on aarch64 virt & xlnx-versal platform. Signed-off-by: schspa <schspa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/virtio/virtio-mmio.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index XXXXXXX..XXXXXXX 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -XXX,XX +XXX,XX @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) BusState *virtio_mmio_bus; VirtIOMMIOProxy *virtio_mmio_proxy; char *proxy_path; - SysBusDevice *proxy_sbd; char *path; + MemoryRegionSection section; virtio_mmio_bus = qdev_get_parent_bus(dev); virtio_mmio_proxy = VIRTIO_MMIO(virtio_mmio_bus->parent); @@ -XXX,XX +XXX,XX @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) } /* Otherwise, we append the base address of the transport. */ - proxy_sbd = SYS_BUS_DEVICE(virtio_mmio_proxy); - assert(proxy_sbd->num_mmio == 1); - assert(proxy_sbd->mmio[0].memory == &virtio_mmio_proxy->iomem); + section = memory_region_find(&virtio_mmio_proxy->iomem, 0, 0x200); + assert(section.mr); if (proxy_path) { path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path, - proxy_sbd->mmio[0].addr); + section.offset_within_address_space); } else { path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx, - proxy_sbd->mmio[0].addr); + section.offset_within_address_space); } + memory_region_unref(section.mr); + g_free(proxy_path); return path; } -- 2.20.1 From: Peter Collingbourne <pcc@google.com> Section D6.7 of the ARM ARM states: For the purpose of determining Tag Check Fault handling, unprivileged load and store instructions are treated as if executed at EL0 when executed at either: - EL1, when the Effective value of PSTATE.UAO is 0. - EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1} and the Effective value of PSTATE.UAO is 0. ARM has confirmed a defect in the pseudocode function AArch64.TagCheckFault that makes it inconsistent with the above wording. The remedy is to adjust references to PSTATE.EL in that function to instead refer to AArch64.AccessUsesEL(acctype), so that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1. The exception type for synchronous tag check faults remains unchanged. This patch implements the described change by partially reverting commits 50244cc76abc and cc97b0019bb5. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219201820.2672077-1-pcc@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 2 +- target/arm/mte_helper.c | 13 +++++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) && tbid && !(env->pstate & PSTATE_TCO) - && (sctlr & SCTLR_TCF) + && (sctlr & SCTLR_TCF0) && allocation_tag_access_enabled(env, 0, sctlr)) { flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); } diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, reg_el = regime_el(env, arm_mmu_idx); sctlr = env->cp15.sctlr_el[reg_el]; - el = arm_current_el(env); - if (el == 0) { + switch (arm_mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E20_0: + el = 0; tcf = extract64(sctlr, 38, 2); - } else { + break; + default: + el = reg_el; tcf = extract64(sctlr, 40, 2); } @@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, env->exception.vaddress = dirty_ptr; is_write = FIELD_EX32(desc, MTEDESC, WRITE); - syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11); + syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, + is_write, 0x11); raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env)); /* noreturn, but fall through to the assert anyway */ -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210221222617.2579610-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 7 ------- target/arm/cpu_tcg.c | 8 ++++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { .class_init = arm_cpu_class_init, }; -static const TypeInfo idau_interface_type_info = { - .name = TYPE_IDAU_INTERFACE, - .parent = TYPE_INTERFACE, - .class_size = sizeof(IDAUInterfaceClass), -}; - static void arm_cpu_register_types(void) { const size_t cpu_count = ARRAY_SIZE(arm_cpus); @@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void) if (cpu_count) { size_t i; - type_register_static(&idau_interface_type_info); for (i = 0; i < cpu_count; ++i) { arm_cpu_register(&arm_cpus[i]); } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -XXX,XX +XXX,XX @@ #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" +#include "target/arm/idau.h" /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, }; +static const TypeInfo idau_interface_type_info = { + .name = TYPE_IDAU_INTERFACE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(IDAUInterfaceClass), +}; + static void arm_tcg_cpu_register_types(void) { size_t i; + type_register_static(&idau_interface_type_info); for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210221222617.2579610-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj) } static const ARMCPRegInfo cortexa9_cp_reginfo[] = { - /* power_control should be set to maximum latency. Again, + /* + * power_control should be set to maximum latency. Again, * default to 0 and set by private hook */ { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, @@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); - /* Note that A9 supports the MP extensions even for + /* + * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). */ @@ -XXX,XX +XXX,XX @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { MachineState *ms = MACHINE(qdev_get_machine()); - /* Linux wants the number of processors from here. + /* + * Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ return ((ms->smp.cpus - 1) << 24) | (1 << 23); @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_mmfr1 = 0x40000000; cpu->isar.id_mmfr2 = 0x01240000; cpu->isar.id_mmfr3 = 0x02102211; - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ cpu->isar.id_isar0 = 0x02101110; -- 2.20.1 For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the milkymist display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-2-peter.maydell@linaro.org --- hw/arm/musicpal.c | 64 ++++++++++++++++++----------------------------- 1 file changed, 24 insertions(+), 40 deletions(-) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -XXX,XX +XXX,XX @@ static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) } } -#define SET_LCD_PIXEL(depth, type) \ -static inline void glue(set_lcd_pixel, depth) \ - (musicpal_lcd_state *s, int x, int y, type col) \ -{ \ - int dx, dy; \ - DisplaySurface *surface = qemu_console_surface(s->con); \ - type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ -\ - for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ - for (dx = 0; dx < 3; dx++, pixel++) \ - *pixel = col; \ +static inline void set_lcd_pixel32(musicpal_lcd_state *s, + int x, int y, uint32_t col) +{ + int dx, dy; + DisplaySurface *surface = qemu_console_surface(s->con); + uint32_t *pixel = + &((uint32_t *) surface_data(surface))[(y * 128 * 3 + x) * 3]; + + for (dy = 0; dy < 3; dy++, pixel += 127 * 3) { + for (dx = 0; dx < 3; dx++, pixel++) { + *pixel = col; + } + } } -SET_LCD_PIXEL(8, uint8_t) -SET_LCD_PIXEL(16, uint16_t) -SET_LCD_PIXEL(32, uint32_t) static void lcd_refresh(void *opaque) { musicpal_lcd_state *s = opaque; - DisplaySurface *surface = qemu_console_surface(s->con); int x, y, col; - switch (surface_bits_per_pixel(surface)) { - case 0: - return; -#define LCD_REFRESH(depth, func) \ - case depth: \ - col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ - scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ - scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ - for (x = 0; x < 128; x++) { \ - for (y = 0; y < 64; y++) { \ - if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ - glue(set_lcd_pixel, depth)(s, x, y, col); \ - } else { \ - glue(set_lcd_pixel, depth)(s, x, y, 0); \ - } \ - } \ - } \ - break; - LCD_REFRESH(8, rgb_to_pixel8) - LCD_REFRESH(16, rgb_to_pixel16) - LCD_REFRESH(32, (is_surface_bgr(surface) ? - rgb_to_pixel32bgr : rgb_to_pixel32)) - default: - hw_error("unsupported colour depth %i\n", - surface_bits_per_pixel(surface)); + col = rgb_to_pixel32(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), + scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), + scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); + for (x = 0; x < 128; x++) { + for (y = 0; y < 64; y++) { + if (s->video_ram[x + (y / 8) * 128] & (1 << (y % 8))) { + set_lcd_pixel32(s, x, y, col); + } else { + set_lcd_pixel32(s, x, y, 0); + } + } } dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); -- 2.20.1 For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the tc6393xb display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-3-peter.maydell@linaro.org --- include/ui/console.h | 10 ---------- hw/display/tc6393xb.c | 33 +-------------------------------- 2 files changed, 1 insertion(+), 42 deletions(-) diff --git a/include/ui/console.h b/include/ui/console.h index XXXXXXX..XXXXXXX 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -XXX,XX +XXX,XX @@ PixelFormat qemu_default_pixelformat(int bpp); DisplaySurface *qemu_create_displaysurface(int width, int height); void qemu_free_displaysurface(DisplaySurface *surface); -static inline int is_surface_bgr(DisplaySurface *surface) -{ - if (PIXMAN_FORMAT_BPP(surface->format) == 32 && - PIXMAN_FORMAT_TYPE(surface->format) == PIXMAN_TYPE_ABGR) { - return 1; - } else { - return 0; - } -} - static inline int is_buffer_shared(DisplaySurface *surface) { return !(surface->flags & QEMU_ALLOCATED_FLAG); diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c index XXXXXXX..XXXXXXX 100644 --- a/hw/display/tc6393xb.c +++ b/hw/display/tc6393xb.c @@ -XXX,XX +XXX,XX @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) (uint32_t) addr, value & 0xff); } -#define BITS 8 -#include "tc6393xb_template.h" -#define BITS 15 -#include "tc6393xb_template.h" -#define BITS 16 -#include "tc6393xb_template.h" -#define BITS 24 -#include "tc6393xb_template.h" #define BITS 32 #include "tc6393xb_template.h" static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) { - DisplaySurface *surface = qemu_console_surface(s->con); - - switch (surface_bits_per_pixel(surface)) { - case 8: - tc6393xb_draw_graphic8(s); - break; - case 15: - tc6393xb_draw_graphic15(s); - break; - case 16: - tc6393xb_draw_graphic16(s); - break; - case 24: - tc6393xb_draw_graphic24(s); - break; - case 32: - tc6393xb_draw_graphic32(s); - break; - default: - printf("tc6393xb: unknown depth %d\n", - surface_bits_per_pixel(surface)); - return; - } - + tc6393xb_draw_graphic32(s); dpy_gfx_update_full(s->con); } -- 2.20.1 Now the template header is included only for BITS==32, expand out all the macros that depended on the BITS setting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-4-peter.maydell@linaro.org --- hw/display/tc6393xb_template.h | 35 ++++------------------------------ 1 file changed, 4 insertions(+), 31 deletions(-) diff --git a/hw/display/tc6393xb_template.h b/hw/display/tc6393xb_template.h index XXXXXXX..XXXXXXX 100644 --- a/hw/display/tc6393xb_template.h +++ b/hw/display/tc6393xb_template.h @@ -XXX,XX +XXX,XX @@ * with this program; if not, see <http://www.gnu.org/licenses/>. */ -#if BITS == 8 -# define SET_PIXEL(addr, color) (*(uint8_t *)addr = color) -#elif BITS == 15 || BITS == 16 -# define SET_PIXEL(addr, color) (*(uint16_t *)addr = color) -#elif BITS == 24 -# define SET_PIXEL(addr, color) \ - do { \ - addr[0] = color; \ - addr[1] = (color) >> 8; \ - addr[2] = (color) >> 16; \ - } while (0) -#elif BITS == 32 -# define SET_PIXEL(addr, color) (*(uint32_t *)addr = color) -#else -# error unknown bit depth -#endif - - -static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s) +static void tc6393xb_draw_graphic32(TC6393xbState *s) { DisplaySurface *surface = qemu_console_surface(s->con); int i; @@ -XXX,XX +XXX,XX @@ static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s) data_buffer = s->vram_ptr; data_display = surface_data(surface); for(i = 0; i < s->scr_height; i++) { -#if (BITS == 16) - memcpy(data_display, data_buffer, s->scr_width * 2); - data_buffer += s->scr_width; - data_display += surface_stride(surface); -#else int j; - for (j = 0; j < s->scr_width; j++, data_display += BITS / 8, data_buffer++) { + for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) { uint16_t color = *data_buffer; - uint32_t dest_color = glue(rgb_to_pixel, BITS)( + uint32_t dest_color = rgb_to_pixel32( ((color & 0xf800) * 0x108) >> 11, ((color & 0x7e0) * 0x41) >> 9, ((color & 0x1f) * 0x21) >> 2 ); - SET_PIXEL(data_display, dest_color); + *(uint32_t *)data_display = dest_color; } -#endif } } - -#undef BITS -#undef SET_PIXEL -- 2.20.1 The function tc6393xb_draw_graphic32() is called in exactly one place, so just inline the function body at its callsite. This allows us to drop the template header entirely. The code move includes a single added space after 'for' to fix the coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-5-peter.maydell@linaro.org --- hw/display/tc6393xb_template.h | 45 ---------------------------------- hw/display/tc6393xb.c | 23 ++++++++++++++--- 2 files changed, 19 insertions(+), 49 deletions(-) delete mode 100644 hw/display/tc6393xb_template.h diff --git a/hw/display/tc6393xb_template.h b/hw/display/tc6393xb_template.h deleted file mode 100644 index XXXXXXX..XXXXXXX --- a/hw/display/tc6393xb_template.h +++ /dev/null @@ -XXX,XX +XXX,XX @@ -/* - * Toshiba TC6393XB I/O Controller. - * Found in Sharp Zaurus SL-6000 (tosa) or some - * Toshiba e-Series PDAs. - * - * FB support code. Based on G364 fb emulator - * - * Copyright (c) 2007 Hervé Poussineau - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -static void tc6393xb_draw_graphic32(TC6393xbState *s) -{ - DisplaySurface *surface = qemu_console_surface(s->con); - int i; - uint16_t *data_buffer; - uint8_t *data_display; - - data_buffer = s->vram_ptr; - data_display = surface_data(surface); - for(i = 0; i < s->scr_height; i++) { - int j; - for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) { - uint16_t color = *data_buffer; - uint32_t dest_color = rgb_to_pixel32( - ((color & 0xf800) * 0x108) >> 11, - ((color & 0x7e0) * 0x41) >> 9, - ((color & 0x1f) * 0x21) >> 2 - ); - *(uint32_t *)data_display = dest_color; - } - } -} diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c index XXXXXXX..XXXXXXX 100644 --- a/hw/display/tc6393xb.c +++ b/hw/display/tc6393xb.c @@ -XXX,XX +XXX,XX @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) (uint32_t) addr, value & 0xff); } -#define BITS 32 -#include "tc6393xb_template.h" - static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) { - tc6393xb_draw_graphic32(s); + DisplaySurface *surface = qemu_console_surface(s->con); + int i; + uint16_t *data_buffer; + uint8_t *data_display; + + data_buffer = s->vram_ptr; + data_display = surface_data(surface); + for (i = 0; i < s->scr_height; i++) { + int j; + for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) { + uint16_t color = *data_buffer; + uint32_t dest_color = rgb_to_pixel32( + ((color & 0xf800) * 0x108) >> 11, + ((color & 0x7e0) * 0x41) >> 9, + ((color & 0x1f) * 0x21) >> 2 + ); + *(uint32_t *)data_display = dest_color; + } + } dpy_gfx_update_full(s->con); } -- 2.20.1 The omap_lcdc template header is already only included once, for DEPTH==32, but it still has all the macro-driven parameterization for other depths. Expand out all the macros in the header. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-6-peter.maydell@linaro.org --- hw/display/omap_lcd_template.h | 67 ++++++++++++++-------------------- 1 file changed, 28 insertions(+), 39 deletions(-) diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h index XXXXXXX..XXXXXXX 100644 --- a/hw/display/omap_lcd_template.h +++ b/hw/display/omap_lcd_template.h @@ -XXX,XX +XXX,XX @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#if DEPTH == 32 -# define BPP 4 -# define PIXEL_TYPE uint32_t -#else -# error unsupport depth -#endif - /* * 2-bit colour */ -static void glue(draw_line2_, DEPTH)(void *opaque, - uint8_t *d, const uint8_t *s, int width, int deststep) +static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) { uint16_t *pal = opaque; uint8_t v, r, g, b; @@ -XXX,XX +XXX,XX @@ static void glue(draw_line2_, DEPTH)(void *opaque, r = (pal[v & 3] >> 4) & 0xf0; g = pal[v & 3] & 0xf0; b = (pal[v & 3] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); - d += BPP; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; v >>= 2; r = (pal[v & 3] >> 4) & 0xf0; g = pal[v & 3] & 0xf0; b = (pal[v & 3] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); - d += BPP; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; v >>= 2; r = (pal[v & 3] >> 4) & 0xf0; g = pal[v & 3] & 0xf0; b = (pal[v & 3] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); - d += BPP; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; v >>= 2; r = (pal[v & 3] >> 4) & 0xf0; g = pal[v & 3] & 0xf0; b = (pal[v & 3] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); - d += BPP; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; s ++; width -= 4; } while (width > 0); @@ -XXX,XX +XXX,XX @@ static void glue(draw_line2_, DEPTH)(void *opaque, /* * 4-bit colour */ -static void glue(draw_line4_, DEPTH)(void *opaque, - uint8_t *d, const uint8_t *s, int width, int deststep) +static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) { uint16_t *pal = opaque; uint8_t v, r, g, b; @@ -XXX,XX +XXX,XX @@ static void glue(draw_line4_, DEPTH)(void *opaque, r = (pal[v & 0xf] >> 4) & 0xf0; g = pal[v & 0xf] & 0xf0; b = (pal[v & 0xf] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); - d += BPP; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; v >>= 4; r = (pal[v & 0xf] >> 4) & 0xf0; g = pal[v & 0xf] & 0xf0; b = (pal[v & 0xf] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); - d += BPP; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; s ++; width -= 2; } while (width > 0); @@ -XXX,XX +XXX,XX @@ static void glue(draw_line4_, DEPTH)(void *opaque, /* * 8-bit colour */ -static void glue(draw_line8_, DEPTH)(void *opaque, - uint8_t *d, const uint8_t *s, int width, int deststep) +static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) { uint16_t *pal = opaque; uint8_t v, r, g, b; @@ -XXX,XX +XXX,XX @@ static void glue(draw_line8_, DEPTH)(void *opaque, r = (pal[v] >> 4) & 0xf0; g = pal[v] & 0xf0; b = (pal[v] << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); s ++; - d += BPP; + d += 4; } while (-- width != 0); } /* * 12-bit colour */ -static void glue(draw_line12_, DEPTH)(void *opaque, - uint8_t *d, const uint8_t *s, int width, int deststep) +static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) { uint16_t v; uint8_t r, g, b; @@ -XXX,XX +XXX,XX @@ static void glue(draw_line12_, DEPTH)(void *opaque, r = (v >> 4) & 0xf0; g = v & 0xf0; b = (v << 4) & 0xf0; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); s += 2; - d += BPP; + d += 4; } while (-- width != 0); } /* * 16-bit colour */ -static void glue(draw_line16_, DEPTH)(void *opaque, - uint8_t *d, const uint8_t *s, int width, int deststep) +static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) { #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) memcpy(d, s, width * 2); @@ -XXX,XX +XXX,XX @@ static void glue(draw_line16_, DEPTH)(void *opaque, r = (v >> 8) & 0xf8; g = (v >> 3) & 0xfc; b = (v << 3) & 0xf8; - ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b); + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); s += 2; - d += BPP; + d += 4; } while (-- width != 0); #endif } - -#undef DEPTH -#undef BPP -#undef PIXEL_TYPE -- 2.20.1 The draw_line16_32() function in the omap_lcdc template header includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source bitmap and destination bitmap format match", but it is broken, because in this function the formats don't match: the source is 16-bit colour and the destination is 32-bit colour, so a memcpy() will produce corrupted graphics output. Drop the bogus ifdef. This bug was introduced in commit ea644cf343129, when we dropped support for DEPTH values other than 32 from the template header. The old #if line was #if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) and this was mistakenly changed to #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) rather than deleting the #if as now having an always-false condition. Fixes: ea644cf343129 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-7-peter.maydell@linaro.org --- hw/display/omap_lcd_template.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h index XXXXXXX..XXXXXXX 100644 --- a/hw/display/omap_lcd_template.h +++ b/hw/display/omap_lcd_template.h @@ -XXX,XX +XXX,XX @@ static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, int width, int deststep) { -#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) - memcpy(d, s, width * 2); -#else uint16_t v; uint8_t r, g, b; @@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, s += 2; d += 4; } while (-- width != 0); -#endif } -- 2.20.1 Fix some minor coding style issues in the template header, so checkpatch doesn't complain when we move the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-8-peter.maydell@linaro.org --- hw/display/omap_lcd_template.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h index XXXXXXX..XXXXXXX 100644 --- a/hw/display/omap_lcd_template.h +++ b/hw/display/omap_lcd_template.h @@ -XXX,XX +XXX,XX @@ static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, b = (pal[v & 3] << 4) & 0xf0; ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); d += 4; - s ++; + s++; width -= 4; } while (width > 0); } @@ -XXX,XX +XXX,XX @@ static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, b = (pal[v & 0xf] << 4) & 0xf0; ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); d += 4; - s ++; + s++; width -= 2; } while (width > 0); } @@ -XXX,XX +XXX,XX @@ static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, g = pal[v] & 0xf0; b = (pal[v] << 4) & 0xf0; ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - s ++; + s++; d += 4; } while (-- width != 0); } -- 2.20.1 We only include the template header once, so just inline it into the source file for the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-9-peter.maydell@linaro.org --- hw/display/omap_lcd_template.h | 154 --------------------------------- hw/display/omap_lcdc.c | 127 ++++++++++++++++++++++++++- 2 files changed, 125 insertions(+), 156 deletions(-) delete mode 100644 hw/display/omap_lcd_template.h diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h deleted file mode 100644 index XXXXXXX..XXXXXXX --- a/hw/display/omap_lcd_template.h +++ /dev/null @@ -XXX,XX +XXX,XX @@ -/* - * QEMU OMAP LCD Emulator templates - * - * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * 2-bit colour - */ -static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, - int width, int deststep) -{ - uint16_t *pal = opaque; - uint8_t v, r, g, b; - - do { - v = ldub_p((void *) s); - r = (pal[v & 3] >> 4) & 0xf0; - g = pal[v & 3] & 0xf0; - b = (pal[v & 3] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - d += 4; - v >>= 2; - r = (pal[v & 3] >> 4) & 0xf0; - g = pal[v & 3] & 0xf0; - b = (pal[v & 3] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - d += 4; - v >>= 2; - r = (pal[v & 3] >> 4) & 0xf0; - g = pal[v & 3] & 0xf0; - b = (pal[v & 3] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - d += 4; - v >>= 2; - r = (pal[v & 3] >> 4) & 0xf0; - g = pal[v & 3] & 0xf0; - b = (pal[v & 3] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - d += 4; - s++; - width -= 4; - } while (width > 0); -} - -/* - * 4-bit colour - */ -static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, - int width, int deststep) -{ - uint16_t *pal = opaque; - uint8_t v, r, g, b; - - do { - v = ldub_p((void *) s); - r = (pal[v & 0xf] >> 4) & 0xf0; - g = pal[v & 0xf] & 0xf0; - b = (pal[v & 0xf] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - d += 4; - v >>= 4; - r = (pal[v & 0xf] >> 4) & 0xf0; - g = pal[v & 0xf] & 0xf0; - b = (pal[v & 0xf] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - d += 4; - s++; - width -= 2; - } while (width > 0); -} - -/* - * 8-bit colour - */ -static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, - int width, int deststep) -{ - uint16_t *pal = opaque; - uint8_t v, r, g, b; - - do { - v = ldub_p((void *) s); - r = (pal[v] >> 4) & 0xf0; - g = pal[v] & 0xf0; - b = (pal[v] << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - s++; - d += 4; - } while (-- width != 0); -} - -/* - * 12-bit colour - */ -static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, - int width, int deststep) -{ - uint16_t v; - uint8_t r, g, b; - - do { - v = lduw_le_p((void *) s); - r = (v >> 4) & 0xf0; - g = v & 0xf0; - b = (v << 4) & 0xf0; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - s += 2; - d += 4; - } while (-- width != 0); -} - -/* - * 16-bit colour - */ -static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, - int width, int deststep) -{ - uint16_t v; - uint8_t r, g, b; - - do { - v = lduw_le_p((void *) s); - r = (v >> 8) & 0xf8; - g = (v >> 3) & 0xfc; - b = (v << 3) & 0xf8; - ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); - s += 2; - d += 4; - } while (-- width != 0); -} diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) #define draw_line_func drawfn -#define DEPTH 32 -#include "omap_lcd_template.h" +/* + * 2-bit colour + */ +static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) +{ + uint16_t *pal = opaque; + uint8_t v, r, g, b; + + do { + v = ldub_p((void *) s); + r = (pal[v & 3] >> 4) & 0xf0; + g = pal[v & 3] & 0xf0; + b = (pal[v & 3] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; + v >>= 2; + r = (pal[v & 3] >> 4) & 0xf0; + g = pal[v & 3] & 0xf0; + b = (pal[v & 3] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; + v >>= 2; + r = (pal[v & 3] >> 4) & 0xf0; + g = pal[v & 3] & 0xf0; + b = (pal[v & 3] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; + v >>= 2; + r = (pal[v & 3] >> 4) & 0xf0; + g = pal[v & 3] & 0xf0; + b = (pal[v & 3] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; + s++; + width -= 4; + } while (width > 0); +} + +/* + * 4-bit colour + */ +static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) +{ + uint16_t *pal = opaque; + uint8_t v, r, g, b; + + do { + v = ldub_p((void *) s); + r = (pal[v & 0xf] >> 4) & 0xf0; + g = pal[v & 0xf] & 0xf0; + b = (pal[v & 0xf] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; + v >>= 4; + r = (pal[v & 0xf] >> 4) & 0xf0; + g = pal[v & 0xf] & 0xf0; + b = (pal[v & 0xf] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + d += 4; + s++; + width -= 2; + } while (width > 0); +} + +/* + * 8-bit colour + */ +static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) +{ + uint16_t *pal = opaque; + uint8_t v, r, g, b; + + do { + v = ldub_p((void *) s); + r = (pal[v] >> 4) & 0xf0; + g = pal[v] & 0xf0; + b = (pal[v] << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + s++; + d += 4; + } while (-- width != 0); +} + +/* + * 12-bit colour + */ +static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) +{ + uint16_t v; + uint8_t r, g, b; + + do { + v = lduw_le_p((void *) s); + r = (v >> 4) & 0xf0; + g = v & 0xf0; + b = (v << 4) & 0xf0; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + s += 2; + d += 4; + } while (-- width != 0); +} + +/* + * 16-bit colour + */ +static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, + int width, int deststep) +{ + uint16_t v; + uint8_t r, g, b; + + do { + v = lduw_le_p((void *) s); + r = (v >> 8) & 0xf8; + g = (v >> 3) & 0xfc; + b = (v << 3) & 0xf8; + ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b); + s += 2; + d += 4; + } while (-- width != 0); +} static void omap_update_display(void *opaque) { -- 2.20.1 The macro draw_line_func is used only once; just expand it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-10-peter.maydell@linaro.org --- hw/display/omap_lcdc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) qemu_irq_lower(s->irq); } -#define draw_line_func drawfn - /* * 2-bit colour */ @@ -XXX,XX +XXX,XX @@ static void omap_update_display(void *opaque) { struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; DisplaySurface *surface; - draw_line_func draw_line; + drawfn draw_line; int size, height, first, last; int width, linesize, step, bpp, frame_offset; hwaddr frame_base; -- 2.20.1 For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel, RGB. The TCX code already assumes 32bpp, but it still has some checks of is_surface_bgr() in an attempt to support 32bpp BGR. is_surface_bgr() will always return false for the qemu_console_surface(), unless the display device itself has deliberately created an alternate-format surface via a function like qemu_create_displaysurface_from(). Drop the never-used BGR-handling code, and assert that we have a 32-bit surface rather than just doing nothing if it isn't. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215102149.20513-1-peter.maydell@linaro.org --- hw/display/tcx.c | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/hw/display/tcx.c b/hw/display/tcx.c index XXXXXXX..XXXXXXX 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -XXX,XX +XXX,XX @@ static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, static void update_palette_entries(TCXState *s, int start, int end) { - DisplaySurface *surface = qemu_console_surface(s->con); int i; for (i = start; i < end; i++) { - if (is_surface_bgr(surface)) { - s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); - } else { - s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); - } + s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); } tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); } @@ -XXX,XX +XXX,XX @@ static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, } /* - XXX Could be much more optimal: - * detect if line/page/whole screen is in 24 bit mode - * if destination is also BGR, use memcpy - */ + * XXX Could be much more optimal: + * detect if line/page/whole screen is in 24 bit mode + */ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, const uint8_t *s, int width, const uint32_t *cplane, const uint32_t *s24) { - DisplaySurface *surface = qemu_console_surface(s1->con); - int x, bgr, r, g, b; + int x, r, g, b; uint8_t val, *p8; uint32_t *p = (uint32_t *)d; uint32_t dval; - bgr = is_surface_bgr(surface); for(x = 0; x < width; x++, s++, s24++) { if (be32_to_cpu(*cplane) & 0x03000000) { /* 24-bit direct, BGR order */ @@ -XXX,XX +XXX,XX @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, b = *p8++; g = *p8++; r = *p8; - if (bgr) - dval = rgb_to_pixel32bgr(r, g, b); - else - dval = rgb_to_pixel32(r, g, b); + dval = rgb_to_pixel32(r, g, b); } else { /* 8-bit pseudocolor */ val = *s; @@ -XXX,XX +XXX,XX @@ static void tcx_update_display(void *opaque) int y, y_start, dd, ds; uint8_t *d, *s; - if (surface_bits_per_pixel(surface) != 32) { - return; - } + assert(surface_bits_per_pixel(surface) == 32); page = 0; y_start = -1; @@ -XXX,XX +XXX,XX @@ static void tcx24_update_display(void *opaque) uint8_t *d, *s; uint32_t *cptr, *s24; - if (surface_bits_per_pixel(surface) != 32) { - return; - } + assert(surface_bits_per_pixel(surface) == 32); page = 0; y_start = -1; -- 2.20.1 The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-2-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; uint32_t scc_id; + uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ const char *armsse_type; }; @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) -/* Main SYSCLK frequency in Hz */ -#define SYSCLK_FRQ 20000000 /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; int rxirqno = i * 2; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); - qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s = SYS_BUS_DEVICE(uart); sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) /* These clocks don't need migration because they are fixed-frequency */ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, SYSCLK_FRQ); + clock_set_hz(mms->sysclk, mmc->sysclk_frq); mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); clock_set_hz(mms->s32kclk, S32KCLK_FRQ); @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->fpga_type = FPGA_AN505; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045050; + mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type = TYPE_IOTKIT; } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->fpga_type = FPGA_AN521; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045210; + mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type = TYPE_SSE200; } -- 2.20.1 Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-3-peter.maydell@linaro.org --- include/hw/misc/mps2-scc.h | 7 +++---- hw/arm/mps2-tz.c | 5 +++++ hw/arm/mps2.c | 5 +++++ hw/misc/mps2-scc.c | 24 +++++++++++++----------- 4 files changed, 26 insertions(+), 15 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -XXX,XX +XXX,XX @@ #define TYPE_MPS2_SCC "mps2-scc" OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC) -#define NUM_OSCCLK 3 - struct MPS2SCC { /*< private >*/ SysBusDevice parent_obj; @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { uint32_t dll; uint32_t aid; uint32_t id; - uint32_t oscclk[NUM_OSCCLK]; - uint32_t oscclk_reset[NUM_OSCCLK]; + uint32_t num_oscclk; + uint32_t *oscclk; + uint32_t *oscclk_reset; }; #endif diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* This will need to be per-FPGA image eventually */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* All these FPGA images have the same OSCCLK configuration */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); object_initialize_child(OBJECT(mms), "fpgaio", diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -XXX,XX +XXX,XX @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, { trace_mps2_scc_cfg_write(function, device, value); - if (function != 1 || device >= NUM_OSCCLK) { + if (function != 1 || device >= s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config write: bad function %d device %d\n", function, device); @@ -XXX,XX +XXX,XX @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, static bool scc_cfg_read(MPS2SCC *s, unsigned function, unsigned device, uint32_t *value) { - if (function != 1 || device >= NUM_OSCCLK) { + if (function != 1 || device >= s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config read: bad function %d device %d\n", function, device); @@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev) s->cfgctrl = 0x100000; s->cfgstat = 0; s->dll = 0xffff0001; - for (i = 0; i < NUM_OSCCLK; i++) { + for (i = 0; i < s->num_oscclk; i++) { s->oscclk[i] = s->oscclk_reset[i]; } for (i = 0; i < ARRAY_SIZE(s->led); i++) { @@ -XXX,XX +XXX,XX @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) LED_COLOR_GREEN, name); g_free(name); } + + s->oscclk = g_new0(uint32_t, s->num_oscclk); } static const VMStateDescription mps2_scc_vmstate = { .name = "mps2-scc", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), @@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = { VMSTATE_UINT32(cfgctrl, MPS2SCC), VMSTATE_UINT32(cfgstat, MPS2SCC), VMSTATE_UINT32(dll, MPS2SCC), - VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), + VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; @@ -XXX,XX +XXX,XX @@ static Property mps2_scc_properties[] = { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), - /* These are the initial settings for the source clocks on the board. + /* + * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the * motherboard configuration controller to suit the FPGA image. - * These default values are used by most of the standard FPGA images. */ - DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), - DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), - DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), + DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, + qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), }; -- 2.20.1 We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-4-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); /* This will need to be per-FPGA image eventually */ qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); -- 2.20.1 The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-5-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { MPS2TZFPGAType fpga_type; uint32_t scc_id; uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ + uint32_t len_oscclk; + const uint32_t *oscclk; const char *armsse_type; }; @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) +static const uint32_t an505_oscclk[] = { + 40000000, + 24580000, + 25000000, +}; + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, MPS2SCC *scc = opaque; DeviceState *sccdev; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + uint32_t i; object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev = DEVICE(scc); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); - /* This will need to be per-FPGA image eventually */ - qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); - qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); + qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); + for (i = 0; i < mmc->len_oscclk; i++) { + g_autofree char *propname = g_strdup_printf("oscclk[%u]", i); + qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); + } sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045050; mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk = an505_oscclk; + mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->armsse_type = TYPE_IOTKIT; } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045210; mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ + mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->armsse_type = TYPE_SSE200; } -- 2.20.1 The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-6-peter.maydell@linaro.org --- include/hw/misc/mps2-fpgaio.h | 5 ++++- hw/misc/mps2-fpgaio.c | 31 +++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -XXX,XX +XXX,XX @@ #define TYPE_MPS2_FPGAIO "mps2-fpgaio" OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO) +#define MPS2FPGAIO_MAX_LEDS 32 + struct MPS2FPGAIO { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ MemoryRegion iomem; - LEDState *led[2]; + LEDState *led[MPS2FPGAIO_MAX_LEDS]; + uint32_t num_leds; uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case A_LED0: - s->led0 = value & 0x3; - led_set_state(s->led[0], value & 0x01); - led_set_state(s->led[1], value & 0x02); + if (s->num_leds != 0) { + uint32_t i; + + s->led0 = value & MAKE_64BIT_MASK(0, s->num_leds); + for (i = 0; i < s->num_leds; i++) { + led_set_state(s->led[i], value & (1 << i)); + } + } break; case A_PRESCALE: resync_counter(s); @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_reset(DeviceState *dev) s->pscntr = 0; s->pscntr_sync_ticks = now; - for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { + for (size_t i = 0; i < s->num_leds; i++) { device_cold_reset(DEVICE(s->led[i])); } } @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_init(Object *obj) static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) { MPS2FPGAIO *s = MPS2_FPGAIO(dev); + uint32_t i; - s->led[0] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED0"); - s->led[1] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED1"); + if (s->num_leds > MPS2FPGAIO_MAX_LEDS) { + error_setg(errp, "num-leds cannot be greater than %d", + MPS2FPGAIO_MAX_LEDS); + return; + } + + for (i = 0; i < s->num_leds; i++) { + g_autofree char *ledname = g_strdup_printf("USERLED%d", i); + s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, + LED_COLOR_GREEN, ledname); + } } static bool mps2_fpgaio_counters_needed(void *opaque) @@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_fpgaio_vmstate = { static Property mps2_fpgaio_properties[] = { /* Frequency of the prescale counter */ DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), + /* Number of LEDs controlled by LED0 register */ + DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_END_OF_LIST(), }; -- 2.20.1 MPS3 boards have an extra SWITCH register in the FPGAIO block which reports the value of some switches. Implement this, governed by a property the board code can use to specify whether whether it exists. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-7-peter.maydell@linaro.org --- include/hw/misc/mps2-fpgaio.h | 1 + hw/misc/mps2-fpgaio.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -XXX,XX +XXX,XX @@ struct MPS2FPGAIO { MemoryRegion iomem; LEDState *led[MPS2FPGAIO_MAX_LEDS]; uint32_t num_leds; + bool has_switches; uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -XXX,XX +XXX,XX @@ REG32(CLK100HZ, 0x14) REG32(COUNTER, 0x18) REG32(PRESCALE, 0x1c) REG32(PSCNTR, 0x20) +REG32(SWITCH, 0x28) REG32(MISC, 0x4c) static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) resync_counter(s); r = s->pscntr; break; + case A_SWITCH: + if (!s->has_switches) { + goto bad_offset; + } + /* User-togglable board switches. We don't model that, so report 0. */ + r = 0; + break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 FPGAIO read: bad offset %x\n", (int) offset); r = 0; @@ -XXX,XX +XXX,XX @@ static Property mps2_fpgaio_properties[] = { DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), /* Number of LEDs controlled by LED0 register */ DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), + DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), DEFINE_PROP_END_OF_LIST(), }; -- 2.20.1 Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-8-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ uint32_t len_oscclk; const uint32_t *oscclk; + uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ + bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ const char *armsse_type; }; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio = opaque; + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); + qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); + qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk = an505_oscclk; mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds = 2; + mmc->fpgaio_has_switches = false; mmc->armsse_type = TYPE_IOTKIT; } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds = 2; + mmc->fpgaio_has_switches = false; mmc->armsse_type = TYPE_SSE200; } -- 2.20.1 In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-9-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ - MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + MachineClass *mc = MACHINE_GET_CLASS(mms); assert(irqno < MPS2TZ_NUMIRQ); - switch (mmc->fpga_type) { - case FPGA_AN505: - return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); - case FPGA_AN521: + if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); - default: - g_assert_not_reached(); + } else { + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); } } @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* - * The AN521 needs us to create splitters to feed the IRQ inputs - * for each CPU in the SSE-200 from each device in the board. + * If this board has more than one CPU, then we need to create splitters + * to feed the IRQ inputs for each CPU in the SSE from each device in the + * board. If there is only one CPU, we can just wire the device IRQ + * directly to the SSE's IRQ input. */ - if (mmc->fpga_type == FPGA_AN521) { + if (mc->max_cpus > 1) { for (i = 0; i < MPS2TZ_NUMIRQ; i++) { char *name = g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; -- 2.20.1 The AN524 has more interrupt lines than the AN505 and AN521; make numirq board-specific rather than a compile-time constant. Since the difference is small (92 on the current boards and 95 on the new one) we don't dynamically allocate the cpu_irq_splitter[] array but leave it as a fixed length array whose size is the maximum needed for any of the boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-10-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ #include "hw/qdev-clock.h" #include "qom/object.h" -#define MPS2TZ_NUMIRQ 92 +#define MPS2TZ_NUMIRQ_MAX 92 typedef enum MPS2TZFPGAType { FPGA_AN505, @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ + int numirq; /* Number of external interrupts */ const char *armsse_type; }; @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; - SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; }; @@ -XXX,XX +XXX,XX @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ MachineClass *mc = MACHINE_GET_CLASS(mms); + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); - assert(irqno < MPS2TZ_NUMIRQ); + assert(irqno < mmc->numirq); if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) iotkitdev = DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) * board. If there is only one CPU, we can just wire the device IRQ * directly to the SSE's IRQ input. */ + assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); if (mc->max_cpus > 1) { - for (i = 0; i < MPS2TZ_NUMIRQ; i++) { + for (i = 0; i < mmc->numirq; i++) { char *name = g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds = 2; mmc->fpgaio_has_switches = false; + mmc->numirq = 92; mmc->armsse_type = TYPE_IOTKIT; } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds = 2; mmc->fpgaio_has_switches = false; + mmc->numirq = 92; mmc->armsse_type = TYPE_SSE200; } -- 2.20.1 The AN524 version of the SCC interface has different behaviour for some of the CFG registers; implement it. Each board in this family can have minor differences in the meaning of the CFG registers, so rather than trying to specify all the possible semantics via individual device properties, we make the behaviour conditional on the part-number field of the SCC_ID register which the board code already passes us. For the AN524, the differences are: * CFG3 is reserved rather than being board switches * CFG5 is a new register ("ACLK Frequency in Hz") * CFG6 is a new register ("Clock divider for BRAM") We implement both of the new registers as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-11-peter.maydell@linaro.org --- include/hw/misc/mps2-scc.h | 3 ++ hw/misc/mps2-scc.c | 71 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { uint32_t cfg0; uint32_t cfg1; + uint32_t cfg2; uint32_t cfg4; + uint32_t cfg5; + uint32_t cfg6; uint32_t cfgdata_rtn; uint32_t cfgdata_out; uint32_t cfgctrl; diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -XXX,XX +XXX,XX @@ REG32(CFG0, 0) REG32(CFG1, 4) +REG32(CFG2, 8) REG32(CFG3, 0xc) REG32(CFG4, 0x10) +REG32(CFG5, 0x14) +REG32(CFG6, 0x18) REG32(CFGDATA_RTN, 0xa0) REG32(CFGDATA_OUT, 0xa4) REG32(CFGCTRL, 0xa8) @@ -XXX,XX +XXX,XX @@ REG32(DLL, 0x100) REG32(AID, 0xFF8) REG32(ID, 0xFFC) +static int scc_partno(MPS2SCC *s) +{ + /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ + return extract32(s->id, 4, 8); +} + /* Handle a write via the SYS_CFG channel to the specified function/device. * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). */ @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) case A_CFG1: r = s->cfg1; break; + case A_CFG2: + if (scc_partno(s) != 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + r = s->cfg2; + break; case A_CFG3: + if (scc_partno(s) == 0x524) { + /* CFG3 reserved on AN524 */ + goto bad_offset; + } /* These are user-settable DIP switches on the board. We don't * model that, so just return zeroes. */ @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) case A_CFG4: r = s->cfg4; break; + case A_CFG5: + if (scc_partno(s) != 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + r = s->cfg5; + break; + case A_CFG6: + if (scc_partno(s) != 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + r = s->cfg6; + break; case A_CFGDATA_RTN: r = s->cfgdata_rtn; break; @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) r = s->id; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC read: bad offset %x\n", (int) offset); r = 0; @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, led_set_state(s->led[i], extract32(value, i, 1)); } break; + case A_CFG2: + if (scc_partno(s) != 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + /* AN524: QSPI Select signal */ + s->cfg2 = value; + break; + case A_CFG5: + if (scc_partno(s) != 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + /* AN524: ACLK frequency in Hz */ + s->cfg5 = value; + break; + case A_CFG6: + if (scc_partno(s) != 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + /* AN524: Clock divider for BRAM */ + s->cfg6 = value; + break; case A_CFGDATA_OUT: s->cfgdata_out = value; break; @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8)); break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC write: bad offset 0x%x\n", (int) offset); break; @@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev) trace_mps2_scc_reset(); s->cfg0 = 0; s->cfg1 = 0; + s->cfg2 = 0; + s->cfg5 = 0; + s->cfg6 = 0; s->cfgdata_rtn = 0; s->cfgdata_out = 0; s->cfgctrl = 0x100000; @@ -XXX,XX +XXX,XX @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) static const VMStateDescription mps2_scc_vmstate = { .name = "mps2-scc", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), + VMSTATE_UINT32(cfg2, MPS2SCC), + /* cfg3, cfg4 are read-only so need not be migrated */ + VMSTATE_UINT32(cfg5, MPS2SCC), + VMSTATE_UINT32(cfg6, MPS2SCC), VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), VMSTATE_UINT32(cfgdata_out, MPS2SCC), VMSTATE_UINT32(cfgctrl, MPS2SCC), -- 2.20.1 On the MPS2 boards, the first 32 interrupt lines are entirely internal to the SSE; interrupt lines for devices outside the SSE start at 32. In the application notes that document each FPGA image, the interrupt wiring is documented from the point of view of the CPU, so '0' is the first of the SSE's interrupts and the devices in the FPGA image itself are '32' and up: so the UART 0 Receive interrupt is 32, the SPI #0 interrupt is 51, and so on. Within our implementation, because the external interrupts must be connected to the EXP_IRQ[0...n] lines of the SSE object, we made the get_sse_irq_in() function take an irqno whose values start at 0 for the first FPGA device interrupt. In this numbering scheme the UART 0 Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. The result of these two different numbering schemes has been that half of the devices were wired up to the wrong IRQs: the UART IRQs are wired up correctly, but the DMA and SPI devices were passing start-at-32 values to get_sse_irq_in() and so being mis-connected. Fix the bug by making get_sse_irq_in() take values specified with the same scheme that the hardware manuals use, to avoid confusion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-12-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { - /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + /* + * Return a qemu_irq which will signal IRQ n to all CPUs in the + * SSE. The irqno should be as the CPU sees it, so the first + * external-to-the-SSE interrupt is 32. + */ MachineClass *mc = MACHINE_GET_CLASS(mms); MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); - assert(irqno < mmc->numirq); + assert(irqno >= 32 && irqno < (mmc->numirq + 32)); + + /* + * Convert from "CPU irq number" (as listed in the FPGA image + * documentation) to the SSE external-interrupt number. + */ + irqno -= 32; if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; - int rxirqno = i * 2; - int txirqno = i * 2 + 1; - int combirqno = i + 10; + int rxirqno = i * 2 + 32; + int txirqno = i * 2 + 33; + int combirqno = i + 42; SysBusDevice *s; DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, s = SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); return sysbus_mmio_get_region(s, 0); } @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - get_sse_irq_in(mms, 15)); + get_sse_irq_in(mms, 47)); /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: -- 2.20.1 The mps2-tz code uses PPCPortInfo data structures to define what devices are present and how they are wired up. Currently we use these to specify device types and addresses, but hard-code the interrupt line wiring in each make_* helper function. This works for the two boards we have at the moment, but the AN524 has some devices with different interrupt assignments. This commit adds the framework to allow PPCPortInfo structures to specify interrupt numbers. We add an array of interrupt numbers to the PPCPortInfo struct, and pass it through to the make_* helpers. The following commit will change the make_* helpers over to using the framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-13-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) * needs to be plugged into the downstream end of the PPC port. */ typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size); + const char *name, hwaddr size, + const int *irqs); typedef struct PPCPortInfo { const char *name; @@ -XXX,XX +XXX,XX @@ typedef struct PPCPortInfo { void *opaque; hwaddr addr; hwaddr size; + int irqs[3]; /* currently no device needs more IRQ lines than this */ } PPCPortInfo; typedef struct PPCInfo { @@ -XXX,XX +XXX,XX @@ typedef struct PPCInfo { } PPCInfo; static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, - void *opaque, - const char *name, hwaddr size) + void *opaque, + const char *name, hwaddr size, + const int *irqs) { /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, * and return a pointer to its MemoryRegion. @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, } static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2SCC *scc = opaque; DeviceState *sccdev; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2FPGAIO *fpgaio = opaque; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { SysBusDevice *s; NICInfo *nd = &nd_table[0]; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { TZMPC *mpc = opaque; int i = mpc - &mms->ssram_mpc[0]; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { PL080State *dma = opaque; int i = dma - &mms->dma[0]; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { /* * The AN505 has five PL022 SPI controllers. @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { ArmSbconI2CState *i2c = opaque; SysBusDevice *s; @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) continue; } - mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, + pinfo->irqs); portname = g_strdup_printf("port[%d]", port); object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), &error_fatal); -- 2.20.1 Move the specification of the IRQ information for the uart, ethernet, dma and spi devices to the data structures. (The other devices handled by the PPCPortInfo structures don't have any interrupt lines we need to wire up.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-14-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; - int rxirqno = i * 2 + 32; - int txirqno = i * 2 + 33; - int combirqno = i + 42; SysBusDevice *s; DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s = SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, s = SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma = opaque; int i = dma - &mms->dma[0]; SysBusDevice *s; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, s = SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); - sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, * lines are set via the "MISC" register in the MPS2 FPGAIO device. */ PL022State *spi = opaque; - int i = spi - &mms->spi[0]; SysBusDevice *s; object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); s = SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) }, { .name = "apb_ppcexp1", .ports = { - { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, - { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, - { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, - { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, - { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, - { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, - { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, - { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, - { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, - { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, + { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, + { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, + { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, + { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, - { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, }, }, { .name = "ahb_ppcexp1", .ports = { - { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, - { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, - { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, - { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, + { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, + { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, + { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, + { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, }, }, }; -- 2.20.1 We create an OR gate to wire together the overflow IRQs for all the UARTs on the board; this has to have twice the number of inputs as there are UARTs, since each UART feeds it a TX overflow and an RX overflow interrupt line. Replace the hardcoded '10' with a calculation based on the size of the uart[] array in the MPS2TZMachineState. (We rely on OR gate inputs that are never wired up or asserted being treated as always-zero.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-15-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) */ memory_region_add_subregion(system_memory, 0x80000000, machine->ram); - /* The overflow IRQs for all UARTs are ORed together. + /* + * The overflow IRQs for all UARTs are ORed together. * Tx, Rx and "combined" IRQs are sent to the NVIC separately. - * Create the OR gate for this. + * Create the OR gate for this: it has one input for the TX overflow + * and one for the RX overflow for each UART we might have. + * (If the board has fewer than the maximum possible number of UARTs + * those inputs are never wired up and are treated as always-zero.) */ object_initialize_child(OBJECT(mms), "uart-irq-orgate", &mms->uart_irq_orgate, TYPE_OR_IRQ); - object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, + object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", + 2 * ARRAY_SIZE(mms->uart), &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, -- 2.20.1 The AN505 and AN521 have the same device layout, but the AN524 is somewhat different. Allow for more than one PPCInfo array, which can be selected based on the board type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-16-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) MemoryRegion *system_memory = get_system_memory(); DeviceState *iotkitdev; DeviceState *dev_splitter; + const PPCInfo *ppcs; + int num_ppcs; int i; if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) * + wire up the PPC's control lines to the IoTKit object */ - const PPCInfo ppcs[] = { { + const PPCInfo an505_ppcs[] = { { .name = "apb_ppcexp0", .ports = { { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) }, }; - for (i = 0; i < ARRAY_SIZE(ppcs); i++) { + switch (mmc->fpga_type) { + case FPGA_AN505: + case FPGA_AN521: + ppcs = an505_ppcs; + num_ppcs = ARRAY_SIZE(an505_ppcs); + break; + default: + g_assert_not_reached(); + } + + for (i = 0; i < num_ppcs; i++) { const PPCInfo *ppcinfo = &ppcs[i]; TZPPC *ppc = &mms->ppc[i]; DeviceState *ppcdev; -- 2.20.1 The AN505 and AN521 have the same layout of RAM; the AN524 does not. Replace the current hard-coding of where the RAM is and which parts of it are behind which MPCs with a data-driven approach. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-17-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 138 insertions(+), 37 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ #include "qom/object.h" #define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_RAM_MAX 4 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, } MPS2TZFPGAType; +/* + * Define the layout of RAM in a board, including which parts are + * behind which MPCs. + * mrindex specifies the index into mms->ram[] to use for the backing RAM; + * -1 means "use the system RAM". + */ +typedef struct RAMInfo { + const char *name; + uint32_t base; + uint32_t size; + int mpc; /* MPC number, -1 for "not behind an MPC" */ + int mrindex; + int flags; +} RAMInfo; + +/* + * Flag values: + * IS_ALIAS: this RAM area is an alias to the upstream end of the + * MPC specified by its .mpc value + */ +#define IS_ALIAS 1 + struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ int numirq; /* Number of external interrupts */ + const RAMInfo *raminfo; const char *armsse_type; }; @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { MachineState parent; ARMSSE iotkit; - MemoryRegion ssram[3]; - MemoryRegion ssram1_m; + MemoryRegion ram[MPS2TZ_RAM_MAX]; MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; - TZMPC ssram_mpc[3]; + TZMPC mpc[3]; PL022State spi[5]; ArmSbconI2CState i2c[4]; UnimplementedDeviceState i2s_audio; @@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = { 25000000, }; +static const RAMInfo an505_raminfo[] = { { + .name = "ssram-0", + .base = 0x00000000, + .size = 0x00400000, + .mpc = 0, + .mrindex = 0, + }, { + .name = "ssram-1", + .base = 0x28000000, + .size = 0x00200000, + .mpc = 1, + .mrindex = 1, + }, { + .name = "ssram-2", + .base = 0x28200000, + .size = 0x00200000, + .mpc = 2, + .mrindex = 2, + }, { + .name = "ssram-0-alias", + .base = 0x00400000, + .size = 0x00400000, + .mpc = 0, + .mrindex = 3, + .flags = IS_ALIAS, + }, { + /* Use the largest bit of contiguous RAM as our "system memory" */ + .name = "mps.ram", + .base = 0x80000000, + .size = 16 * MiB, + .mpc = -1, + .mrindex = -1, + }, { + .name = NULL, + }, +}; + +static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) +{ + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + const RAMInfo *p; + + for (p = mmc->raminfo; p->name; p++) { + if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { + return p; + } + } + /* if raminfo array doesn't have an entry for each MPC this is a bug */ + g_assert_not_reached(); +} + +static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, + const RAMInfo *raminfo) +{ + /* Return an initialized MemoryRegion for the RAMInfo. */ + MemoryRegion *ram; + + if (raminfo->mrindex < 0) { + /* Means this RAMInfo is for QEMU's "system memory" */ + MachineState *machine = MACHINE(mms); + return machine->ram; + } + + assert(raminfo->mrindex < MPS2TZ_RAM_MAX); + ram = &mms->ram[raminfo->mrindex]; + + memory_region_init_ram(ram, NULL, raminfo->name, + raminfo->size, &error_fatal); + return ram; +} + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const int *irqs) { TZMPC *mpc = opaque; - int i = mpc - &mms->ssram_mpc[0]; - MemoryRegion *ssram = &mms->ssram[i]; + int i = mpc - &mms->mpc[0]; MemoryRegion *upstream; - char *mpcname = g_strdup_printf("%s-mpc", name); - static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; - static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; + const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); + MemoryRegion *ram = mr_for_raminfo(mms, raminfo); - memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); - - object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); - object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), + object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); /* Map the upstream end of the MPC into system memory */ upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); - memory_region_add_subregion(get_system_memory(), rambase[i], upstream); + memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); /* and connect its interrupt to the IoTKit */ qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "mpcexp_status", i)); - /* The first SSRAM is a special case as it has an alias; accesses to - * the alias region at 0x00400000 must also go to the MPC upstream. - */ - if (i == 0) { - make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); - } - - g_free(mpcname); /* Return the register interface MR for our caller to map behind the PPC */ return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(s, 0); } +static void create_non_mpc_ram(MPS2TZMachineState *mms) +{ + /* + * Handle the RAMs which are either not behind MPCs or which are + * aliases to another MPC. + */ + const RAMInfo *p; + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p = mmc->raminfo; p->name; p++) { + if (p->flags & IS_ALIAS) { + SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); + MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); + make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); + } else if (p->mpc == -1) { + /* RAM not behind an MPC */ + MemoryRegion *mr = mr_for_raminfo(mms, p); + memory_region_add_subregion(get_system_memory(), p->base, mr); + } + } +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, qdev_get_gpio_in(dev_splitter, 0)); - /* The IoTKit sets up much of the memory layout, including + /* + * The IoTKit sets up much of the memory layout, including * the aliases between secure and non-secure regions in the - * address space. The FPGA itself contains: - * - * 0x00000000..0x003fffff SSRAM1 - * 0x00400000..0x007fffff alias of SSRAM1 - * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 - * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices - * 0x80000000..0x80ffffff 16MB PSRAM - */ - - /* The FPGA images have an odd combination of different RAMs, + * address space, and also most of the devices in the system. + * The FPGA itself contains various RAMs and some additional devices. + * The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily - * call the 16MB our "system memory", as it's the largest lump. + * call the largest lump our "system memory". */ - memory_region_add_subregion(system_memory, 0x80000000, machine->ram); /* * The overflow IRQs for all UARTs are ORed together. @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) const PPCInfo an505_ppcs[] = { { .name = "apb_ppcexp0", .ports = { - { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, - { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, - { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, + { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, + { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, + { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, }, }, { .name = "apb_ppcexp1", @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); + create_non_mpc_ram(mms); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 2; mmc->fpgaio_has_switches = false; mmc->numirq = 92; + mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 2; mmc->fpgaio_has_switches = false; mmc->numirq = 92; + mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; } -- 2.20.1 Instead of hardcoding the MachineClass default_ram_size and default_ram_id fields, set them on class creation by finding the entry in the RAMInfo array which is marked as being the QEMU system RAM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-18-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data) mc->init = mps2tz_common_init; iic->check = mps2_tz_idau_check; - mc->default_ram_size = 16 * MiB; - mc->default_ram_id = "mps.ram"; +} + +static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) +{ + /* + * Set mc->default_ram_size and default_ram_id from the + * information in mmc->raminfo. + */ + MachineClass *mc = MACHINE_CLASS(mmc); + const RAMInfo *p; + + for (p = mmc->raminfo; p->name; p++) { + if (p->mrindex < 0) { + /* Found the entry for "system memory" */ + mc->default_ram_size = p->size; + mc->default_ram_id = p->name; + return; + } + } + g_assert_not_reached(); } static void mps2tz_an505_class_init(ObjectClass *oc, void *data) @@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->numirq = 92; mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; + mps2tz_set_default_ram_info(mmc); } static void mps2tz_an521_class_init(ObjectClass *oc, void *data) @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->numirq = 92; mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); } static const TypeInfo mps2tz_info = { -- 2.20.1 The AN505 and AN521 don't have any read-only memory, but the AN524 does; add a flag to ROMInfo to mark a region as ROM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-19-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo { * Flag values: * IS_ALIAS: this RAM area is an alias to the upstream end of the * MPC specified by its .mpc value + * IS_ROM: this RAM area is read-only */ #define IS_ALIAS 1 +#define IS_ROM 2 struct MPS2TZMachineClass { MachineClass parent; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, if (raminfo->mrindex < 0) { /* Means this RAMInfo is for QEMU's "system memory" */ MachineState *machine = MACHINE(mms); + assert(!(raminfo->flags & IS_ROM)); return machine->ram; } @@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, memory_region_init_ram(ram, NULL, raminfo->name, raminfo->size, &error_fatal); + if (raminfo->flags & IS_ROM) { + memory_region_set_readonly(ram, true); + } return ram; } -- 2.20.1 The armv7m_load_kernel() function takes a mem_size argument which it expects to be the size of the memory region at guest address 0. (It uses this argument only as a limit on how large a raw image file it can load at address zero). Instead of hardcoding this value, find the RAMInfo corresponding to the 0 address and extract its size. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-20-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ static void create_non_mpc_ram(MPS2TZMachineState *mms) } } +static uint32_t boot_ram_size(MPS2TZMachineState *mms) +{ + /* Return the size of the RAM block at guest address zero */ + const RAMInfo *p; + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p = mmc->raminfo; p->name; p++) { + if (p->base == 0) { + return p->size; + } + } + g_assert_not_reached(); +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) create_non_mpc_ram(mms); - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + boot_ram_size(mms)); } static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, -- 2.20.1 Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-21-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 139 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 135 insertions(+), 4 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ * This source file covers the following FPGA images, for TrustZone cores: * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 + * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: @@ -XXX,XX +XXX,XX @@ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html * Application Note AN521: * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * Application Note AN524: + * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide * (ARM ECM0601256) for the details of some of the device layout: * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html - * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines + * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines * most of the device layout: * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf * @@ -XXX,XX +XXX,XX @@ #include "hw/qdev-clock.h" #include "qom/object.h" -#define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_NUMIRQ_MAX 95 #define MPS2TZ_RAM_MAX 4 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, + FPGA_AN524, } MPS2TZFPGAType; /* @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { TZPPC ppc[5]; TZMPC mpc[3]; PL022State spi[5]; - ArmSbconI2CState i2c[4]; + ArmSbconI2CState i2c[5]; UnimplementedDeviceState i2s_audio; UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; + UnimplementedDeviceState cldc; + UnimplementedDeviceState rtc; PL080State dma[4]; TZMSC msc[4]; - CMSDKAPBUART uart[5]; + CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_MACHINE "mps2tz" #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") +#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) @@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = { 25000000, }; +static const uint32_t an524_oscclk[] = { + 24000000, + 32000000, + 50000000, + 50000000, + 24576000, + 23750000, +}; + static const RAMInfo an505_raminfo[] = { { .name = "ssram-0", .base = 0x00000000, @@ -XXX,XX +XXX,XX @@ static const RAMInfo an505_raminfo[] = { { }, }; +static const RAMInfo an524_raminfo[] = { { + .name = "bram", + .base = 0x00000000, + .size = 512 * KiB, + .mpc = 0, + .mrindex = 0, + }, { + .name = "sram", + .base = 0x20000000, + .size = 32 * 4 * KiB, + .mpc = 1, + .mrindex = 1, + }, { + /* We don't model QSPI flash yet; for now expose it as simple ROM */ + .name = "QSPI", + .base = 0x28000000, + .size = 8 * MiB, + .mpc = 1, + .mrindex = 2, + .flags = IS_ROM, + }, { + .name = "DDR", + .base = 0x60000000, + .size = 2 * GiB, + .mpc = 2, + .mrindex = -1, + }, { + .name = NULL, + }, +}; + static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) { MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) }, }; + const PPCInfo an524_ppcs[] = { { + .name = "apb_ppcexp0", + .ports = { + { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, + }, + }, { + .name = "apb_ppcexp1", + .ports = { + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, + { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, + { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, + }, + }, { + .name = "apb_ppcexp2", + .ports = { + { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, + 0x41301000, 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, + { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, + { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, + + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, + { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + }, + }, { + .name = "ahb_ppcexp0", + .ports = { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, + { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: ppcs = an505_ppcs; num_ppcs = ARRAY_SIZE(an505_ppcs); break; + case FPGA_AN524: + ppcs = an524_ppcs; + num_ppcs = ARRAY_SIZE(an524_ppcs); + break; default: g_assert_not_reached(); } @@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mps2tz_set_default_ram_info(mmc); } +static void mps3tz_an524_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); + + mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; + mc->default_cpus = 2; + mc->min_cpus = mc->default_cpus; + mc->max_cpus = mc->default_cpus; + mmc->fpga_type = FPGA_AN524; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mmc->scc_id = 0x41045240; + mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ + mmc->oscclk = an524_oscclk; + mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); + mmc->fpgaio_num_leds = 10; + mmc->fpgaio_has_switches = true; + mmc->numirq = 95; + mmc->raminfo = an524_raminfo; + mmc->armsse_type = TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info = { .name = TYPE_MPS2TZ_MACHINE, .parent = TYPE_MACHINE, @@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2tz_an521_info = { .class_init = mps2tz_an521_class_init, }; +static const TypeInfo mps3tz_an524_info = { + .name = TYPE_MPS3TZ_AN524_MACHINE, + .parent = TYPE_MPS2TZ_MACHINE, + .class_init = mps3tz_an524_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); type_register_static(&mps2tz_an521_info); + type_register_static(&mps3tz_an524_info); } type_init(mps2tz_machine_init); -- 2.20.1 The AN524 has a USB controller (an ISP1763); we don't have a model of it but we should provide a stub "unimplemented-device" for it. This is slightly complicated because the USB controller shares a PPC port with the ethernet controller. Implement a make_* function which provides creates a container MemoryRegion with both the ethernet controller and an unimplemented-device stub for the USB controller. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-22-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { ARMSSE iotkit; MemoryRegion ram[MPS2TZ_RAM_MAX]; + MemoryRegion eth_usb_container; + MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; UnimplementedDeviceState rtc; + UnimplementedDeviceState usb; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(s, 0); } +static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + /* + * The AN524 makes the ethernet and USB share a PPC port. + * irqs[] is the ethernet IRQ. + */ + SysBusDevice *s; + NICInfo *nd = &nd_table[0]; + + memory_region_init(&mms->eth_usb_container, OBJECT(mms), + "mps2-tz-eth-usb-container", 0x200000); + + /* + * In hardware this is a LAN9220; the LAN9118 is software compatible + * except that it doesn't support the checksum-offload feature. + */ + qemu_check_nic_model(nd, "lan9118"); + mms->lan9118 = qdev_new(TYPE_LAN9118); + qdev_set_nic_properties(mms->lan9118, nd); + + s = SYS_BUS_DEVICE(mms->lan9118); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + + memory_region_add_subregion(&mms->eth_usb_container, + 0, sysbus_mmio_get_region(s, 0)); + + /* The USB OTG controller is an ISP1763; we don't have a model of it. */ + object_initialize_child(OBJECT(mms), "usb-otg", + &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); + qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); + s = SYS_BUS_DEVICE(&mms->usb); + sysbus_realize(s, &error_fatal); + + memory_region_add_subregion(&mms->eth_usb_container, + 0x100000, sysbus_mmio_get_region(s, 0)); + + return &mms->eth_usb_container; +} + static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, - { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, }, }, }; -- 2.20.1 The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-23-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ #include "hw/misc/tz-msc.h" #include "hw/arm/armsse.h" #include "hw/dma/pl080.h" +#include "hw/rtc/pl031.h" #include "hw/ssi/pl022.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/net/lan9118.h" @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; - UnimplementedDeviceState rtc; UnimplementedDeviceState usb; + PL031State rtc; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(s, 0); } +static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + PL031State *pl031 = opaque; + SysBusDevice *s; + + object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); + s = SYS_BUS_DEVICE(pl031); + sysbus_realize(s, &error_fatal); + /* + * The board docs don't give an IRQ number for the PL031, so + * presumably it is not connected. + */ + return sysbus_mmio_get_region(s, 0); +} + static void create_non_mpc_ram(MPS2TZMachineState *mms) { /* @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, - { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, }, }, { .name = "ahb_ppcexp0", -- 2.20.1 Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-24-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -XXX,XX +XXX,XX @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) -================================================================================================================ +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) +========================================================================================================================================= These board models all use Arm M-profile CPUs. -The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger -FPGA but is otherwise the same as the 2). Since the CPU itself -and most of the devices are in the FPGA, the details of the board -as seen by the guest depend significantly on the FPGA image. +The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a +bigger FPGA but is otherwise the same as the 2; the 3 has a bigger +FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). + +Since the CPU itself and most of the devices are in the FPGA, the +details of the board as seen by the guest depend significantly on the +FPGA image. QEMU models the following FPGA images: @@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images: Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` Dual Cortex-M33 as documented in Arm Application Note AN521 +``mps3-an524`` + Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 Differences between QEMU and real hardware: - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) +- AN524 remapping of low memory to either BRAM or to QSPI flash is + unimplemented (QEMU always maps this to BRAM, ignoring the + SCC CFG_REG0 memory-remap bit) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest visible difference is that the LAN9118 doesn't support checksum offloading +- QEMU does not model the QSPI flash in MPS3 boards as real QSPI + flash, but only as simple ROM, so attempting to rewrite the flash + from the guest will fail +- QEMU does not model the USB controller in MPS3 boards -- 2.20.1 Update old infocenter.arm.com URLs to the equivalent developer.arm.com ones (the old URLs should redirect, but we might as well avoid the redirection notice, and the new URLs are pleasantly shorter). This commit covers the links to the MPS2 board TRM, the various Application Notes, the IoTKit and SSE-200 documents. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-25-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 4 ++-- include/hw/misc/armsse-cpuid.h | 2 +- include/hw/misc/armsse-mhu.h | 2 +- include/hw/misc/iotkit-secctl.h | 2 +- include/hw/misc/iotkit-sysctl.h | 2 +- include/hw/misc/iotkit-sysinfo.h | 2 +- include/hw/misc/mps2-fpgaio.h | 2 +- hw/arm/mps2-tz.c | 11 +++++------ hw/misc/armsse-cpuid.c | 2 +- hw/misc/armsse-mhu.c | 2 +- hw/misc/iotkit-sysctl.c | 2 +- hw/misc/iotkit-sysinfo.c | 2 +- hw/misc/mps2-fpgaio.c | 2 +- hw/misc/mps2-scc.c | 2 +- 14 files changed, 19 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -XXX,XX +XXX,XX @@ * hardware, which include the IoT Kit and the SSE-050, SSE-100 and * SSE-200. Currently we model: * - the Arm IoT Kit which is documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * - the SSE-200 which is documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * The IoTKit contains: * a Cortex-M33 diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/armsse-cpuid.h +++ b/include/hw/misc/armsse-cpuid.h @@ -XXX,XX +XXX,XX @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + QOM property "CPUID": the value to use for the CPUID register diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/armsse-mhu.h +++ b/include/hw/misc/armsse-mhu.h @@ -XXX,XX +XXX,XX @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + sysbus MMIO region 0: the system information register bank diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -XXX,XX +XXX,XX @@ /* This is a model of the security controller which is part of the * Arm IoT Kit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * * QEMU interface: * + sysbus MMIO region 0 is the "secure privilege control block" registers diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -XXX,XX +XXX,XX @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system information block" and * "system control register" blocks. * diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysinfo.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -XXX,XX +XXX,XX @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * QEMU interface: * + QOM property "SYS_VERSION": value to use for SYS_VERSION register * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -XXX,XX +XXX,XX @@ /* This is a model of the FPGAIO register block in the AN505 * FPGA image for the MPS2 dev board; it is documented in the * application note: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * * QEMU interface: * + sysbus MMIO region 0: the register bank diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -XXX,XX +XXX,XX @@ * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 * * Board TRM: - * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf + * https://developer.arm.com/documentation/100112/latest/ * Application Note AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * Application Note AN521: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * https://developer.arm.com/documentation/dai0521/latest/ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide * (ARM ECM0601256) for the details of some of the device layout: - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines * most of the device layout: - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf - * + * https://developer.arm.com/documentation/101104/latest/ */ #include "qemu/osdep.h" diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -XXX,XX +XXX,XX @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * It consists of one read-only CPUID register (set by QOM property), plus the * usual ID registers. diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/armsse-mhu.c +++ b/hw/misc/armsse-mhu.c @@ -XXX,XX +XXX,XX @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ */ #include "qemu/osdep.h" diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -XXX,XX +XXX,XX @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system control register" blocks. */ diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -XXX,XX +XXX,XX @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * It consists of 2 read-only version/config registers, plus the * usual ID registers. */ diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -XXX,XX +XXX,XX @@ /* This is a model of the "FPGA system control and I/O" block found * in the AN505 FPGA image for the MPS2 devboard. * It is documented in AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ */ #include "qemu/osdep.h" diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -XXX,XX +XXX,XX @@ * found in the FPGA images of MPS2 development boards. * * Documentation of it can be found in the MPS2 TRM: - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html + * https://developer.arm.com/documentation/100112/latest/ * and also in the Application Notes documenting individual FPGA images. */ -- 2.20.1