1
Arm patch queue -- these are all bug fix patches but we might
1
Arm queue; bugfixes only.
2
as well put them in to rc0...
3
2
4
thanks
3
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
6
The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:
8
7
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117
14
13
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
14
for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:
16
15
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
16
tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
20
* hw/arm/virt: ARM_VIRT must select ARM_GIC
22
* dump: Update correct kdump phys_base field for AArch64
21
* exynos: Fix bad printf format specifiers
23
* char: i.MX: Add support for "TX complete" interrupt
22
* hw/input/ps2.c: Remove remnants of printf debug
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
23
* target/openrisc: Remove dead code attempting to check "is timer disabled"
25
to boot a Debian Linux kernel on raspi3
24
* register: Remove unnecessary NULL check
25
* util/cutils: Fix Coverity array overrun in freq_to_str()
26
* configure: Make "does libgio work" test pull in some actual functions
27
* tmp105: reset the T_low and T_High registers
28
* tmp105: Correct handling of temperature limit checks
26
29
27
----------------------------------------------------------------
30
----------------------------------------------------------------
28
Andrey Smirnov (2):
31
Alex Chen (1):
29
char: i.MX: Simplify imx_update()
32
exynos: Fix bad printf format specifiers
30
char: i.MX: Add support for "TX complete" interrupt
31
33
32
Guenter Roeck (1):
34
Alistair Francis (1):
33
fsl-imx6: Swap Ethernet interrupt defines
35
register: Remove unnecessary NULL check
34
36
35
Peter Maydell (9):
37
Andrew Jones (1):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
38
hw/arm/virt: ARM_VIRT must select ARM_GIC
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
39
hw/arm/bcm2386: Fix parent type of bcm2386
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
41
hw/arm/bcm2836: Create proper bcm2837 device
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
43
hw/arm/bcm2836: Hardcode correct CPU type
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
39
46
Wei Huang (1):
40
Peter Maydell (5):
47
dump: Update correct kdump phys_base field for AArch64
41
hw/input/ps2.c: Remove remnants of printf debug
42
target/openrisc: Remove dead code attempting to check "is timer disabled"
43
configure: Make "does libgio work" test pull in some actual functions
44
hw/misc/tmp105: reset the T_low and T_High registers
45
tmp105: Correct handling of temperature limit checks
48
46
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
47
Philippe Mathieu-Daudé (1):
50
include/hw/arm/fsl-imx6.h | 4 +-
48
util/cutils: Fix Coverity array overrun in freq_to_str()
51
include/hw/char/imx_serial.h | 3 ++
52
dump.c | 14 +++++--
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
54
hw/arm/boot.c | 12 ++++++
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
57
hw/net/imx_fec.c | 28 +++++++++++++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
59
49
50
configure | 11 +++++--
51
hw/misc/tmp105.h | 7 +++++
52
hw/core/register.c | 4 ---
53
hw/input/ps2.c | 9 ------
54
hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------
55
hw/timer/exynos4210_mct.c | 4 +--
56
hw/timer/exynos4210_pwm.c | 8 ++---
57
target/openrisc/sys_helper.c | 3 --
58
util/cutils.c | 3 +-
59
hw/arm/Kconfig | 1 +
60
10 files changed, 89 insertions(+), 34 deletions(-)
61
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
The removal of the selection of A15MPCORE from ARM_VIRT also
4
it is needed to support guests other than Linux.
4
removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
5
5
6
Based on the patch by Bill Paul as found here:
6
Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals")
7
https://bugs.launchpad.net/qemu/+bug/1753314
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Cc: qemu-devel@nongnu.org
9
Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
10
Cc: qemu-arm@nongnu.org
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Cc: Bill Paul <wpaul@windriver.com>
11
Message-id: 20201111143440.112763-1-drjones@redhat.com
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
13
---
19
include/hw/char/imx_serial.h | 3 +++
14
hw/arm/Kconfig | 1 +
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
15
1 file changed, 1 insertion(+)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
16
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
17
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
24
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
19
--- a/hw/arm/Kconfig
26
+++ b/include/hw/char/imx_serial.h
20
+++ b/hw/arm/Kconfig
27
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
22
imply VFIO_PLATFORM
29
#define UCR2_SRST (1<<0) /* Reset complete */
23
imply VFIO_XGMAC
30
24
imply TPM_TIS_SYSBUS
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
25
+ select ARM_GIC
32
+
26
select ACPI
33
#define UTS1_TXEMPTY (1<<6)
27
select ARM_SMMUV3
34
#define UTS1_RXEMPTY (1<<5)
28
select GPIO_KEY
35
#define UTS1_TXFULL (1<<4)
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
37
uint32_t ubmr;
38
uint32_t ubrc;
39
uint32_t ucr3;
40
+ uint32_t ucr4;
41
42
qemu_irq irq;
43
CharBackend chr;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
98
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
29
--
114
2.16.2
30
2.20.1
115
31
116
32
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Alex Chen <alex.chen@huawei.com>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
We should use printf format specifier "%u" instead of "%d" for
4
doesn't really corespond to anything in real hardware and server as a
4
argument of type "unsigned int".
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
5
8
Change the code to explicitly evaluate state of interrupts reported
6
Reported-by: Euler Robot <euler.robot@huawei.com>
9
via USR1 and USR2 against corresponding masking bits and use the to
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
10
detemine if IRQ line should be asserted or not.
8
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
11
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
13
reasons:
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
11
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
12
hw/timer/exynos4210_mct.c | 4 ++--
34
1 file changed, 16 insertions(+), 8 deletions(-)
13
hw/timer/exynos4210_pwm.c | 8 ++++----
14
2 files changed, 6 insertions(+), 6 deletions(-)
35
15
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
16
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
37
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
18
--- a/hw/timer/exynos4210_mct.c
39
+++ b/hw/char/imx_serial.c
19
+++ b/hw/timer/exynos4210_mct.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
41
21
/* If CSTAT is pending and IRQ is enabled */
42
static void imx_update(IMXSerialState *s)
22
if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
43
{
23
(s->reg.int_enb & G_INT_ENABLE(id))) {
44
- uint32_t flags;
24
- DPRINTF("gcmp timer[%d] IRQ\n", id);
45
+ uint32_t usr1;
25
+ DPRINTF("gcmp timer[%u] IRQ\n", id);
46
+ uint32_t usr2;
26
qemu_irq_raise(s->irq[id]);
47
+ uint32_t mask;
27
}
48
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
52
- } else {
53
- flags &= ~USR1_TRDY;
54
- }
55
+ /*
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
57
+ * UCR1, so we can get away with something as simple as the
58
+ * following:
59
+ */
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
28
}
71
29
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
72
static void imx_serial_reset(IMXSerialState *s)
30
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
31
32
if (freq != s->freq) {
33
- DPRINTF("freq=%dHz\n", s->freq);
34
+ DPRINTF("freq=%uHz\n", s->freq);
35
36
/* global timer */
37
tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
38
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/timer/exynos4210_pwm.c
41
+++ b/hw/timer/exynos4210_pwm.c
42
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
43
44
if (freq != s->timer[id].freq) {
45
ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
46
- DPRINTF("freq=%dHz\n", s->timer[id].freq);
47
+ DPRINTF("freq=%uHz\n", s->timer[id].freq);
48
}
49
}
50
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
52
uint32_t id = s->id;
53
bool cmp;
54
55
- DPRINTF("timer %d tick\n", id);
56
+ DPRINTF("timer %u tick\n", id);
57
58
/* set irq status */
59
p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
60
61
/* raise IRQ */
62
if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
63
- DPRINTF("timer %d IRQ\n", id);
64
+ DPRINTF("timer %u IRQ\n", id);
65
qemu_irq_raise(p->timer[id].irq);
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
69
}
70
71
if (cmp) {
72
- DPRINTF("auto reload timer %d count to %x\n", id,
73
+ DPRINTF("auto reload timer %u count to %x\n", id,
74
p->timer[id].reg_tcntb);
75
ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
76
ptimer_run(p->timer[id].ptimer, 1);
73
--
77
--
74
2.16.2
78
2.20.1
75
79
76
80
diff view generated by jsdifflib
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
2
just hard-code the CPU type they use rather than having it passed
2
and mouse emulation. However we didn't remove all the debug-by-printf
3
through as an object property. This then lets us put the initialization
3
support. In fact there is only one printf() remaining, and it is
4
of the CPU object in init rather than realize.
4
redundant with the trace_ps2_write_mouse() event next to it.
5
5
Remove the printf() and the now-unused DEBUG* macros.
6
Note that this change means that it's no longer possible on
7
the command line to use -cpu to ask for a different kind of
8
CPU than the SoC supports. This was never a supported thing to
9
do anyway; we were just not sanity-checking the command line.
10
11
This does require us to only build the bcm2837 object on
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
13
due to the missing cortex-a53 device and "make check" will fail.
14
6
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
10
Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
19
---
11
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
12
hw/input/ps2.c | 9 ---------
21
hw/arm/raspi.c | 2 --
13
1 file changed, 9 deletions(-)
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
14
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
15
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
17
--- a/hw/input/ps2.c
27
+++ b/hw/arm/bcm2836.c
18
+++ b/hw/input/ps2.c
28
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
29
20
30
struct BCM283XInfo {
21
#include "trace.h"
31
const char *name;
22
32
+ const char *cpu_type;
23
-/* debug PC keyboard */
33
int clusterid;
24
-//#define DEBUG_KBD
34
};
35
36
static const BCM283XInfo bcm283x_socs[] = {
37
{
38
.name = TYPE_BCM2836,
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
40
.clusterid = 0xf,
41
},
42
+#ifdef TARGET_AARCH64
43
{
44
.name = TYPE_BCM2837,
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
46
.clusterid = 0x0,
47
},
48
+#endif
49
};
50
51
static void bcm2836_init(Object *obj)
52
{
53
BCM283XState *s = BCM283X(obj);
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
55
+ const BCM283XInfo *info = bc->info;
56
+ int n;
57
+
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
60
+ info->cpu_type);
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
62
+ &error_abort);
63
+ }
64
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
68
69
/* common peripherals from bcm2835 */
70
71
- obj = OBJECT(dev);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
74
- s->cpu_type);
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
25
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
26
-/* debug PC keyboard : only mouse */
80
if (obj == NULL) {
27
-//#define DEBUG_MOUSE
81
error_setg(errp, "%s: required ram link not found: %s",
28
-
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
29
/* Keyboard Commands */
83
}
30
#define KBD_CMD_SET_LEDS    0xED    /* Set keyboard leds */
84
31
#define KBD_CMD_ECHO     0xEE
85
static Property bcm2836_props[] = {
32
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
33
PS2MouseState *s = (PS2MouseState *)opaque;
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
34
88
BCM283X_NCPUS),
35
trace_ps2_write_mouse(opaque, val);
89
DEFINE_PROP_END_OF_LIST()
36
-#ifdef DEBUG_MOUSE
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
37
- printf("kbd: write mouse 0x%02x\n", val);
91
index XXXXXXX..XXXXXXX 100644
38
-#endif
92
--- a/hw/arm/raspi.c
39
switch(s->common.write_cmd) {
93
+++ b/hw/arm/raspi.c
40
default:
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
41
case -1:
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
42
--
104
2.16.2
43
2.20.1
105
44
106
45
diff view generated by jsdifflib
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
In the mtspr helper we attempt to check for "is the timer disabled"
2
code for keeping the secondary CPUs in a pen needs to have
2
with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE
3
a version for A64 as well as A32. Without this, the
3
is zero and the condition is always false (Coverity complains about
4
secondary CPUs go into an infinite loop of taking undefined
4
the dead code.)
5
instruction exceptions.
6
5
6
The correct check would be to test whether the TTMR_M field in the
7
register is equal to TIMER_NONE instead. However, the
8
cpu_openrisc_timer_update() function checks whether the timer is
9
enabled (it looks at cpu->env.is_counting, which is set to 0 via
10
cpu_openrisc_count_stop() when the TTMR_M field is set to
11
TIMER_NONE), so there's no need to check for "timer disabled" in the
12
target/openrisc code. Instead, simply remove the dead code.
13
14
Fixes: Coverity CID 1005812
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Acked-by: Stafford Horne <shorne@gmail.com>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
17
Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
10
---
18
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
19
target/openrisc/sys_helper.c | 3 ---
12
1 file changed, 40 insertions(+), 1 deletion(-)
20
1 file changed, 3 deletions(-)
13
21
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
22
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
24
--- a/target/openrisc/sys_helper.c
17
+++ b/hw/arm/raspi.c
25
+++ b/target/openrisc/sys_helper.c
18
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
27
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
28
case TO_SPR(10, 1): /* TTCR */
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
29
cpu_openrisc_count_set(cpu, rb);
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
30
- if (env->ttmr & TIMER_NONE) {
23
31
- return;
24
/* Table of Linux board IDs for different Pi versions */
32
- }
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
33
cpu_openrisc_timer_update(cpu);
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
34
break;
27
info->smp_loader_start);
35
#endif
28
}
29
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
31
+{
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
33
+ * The mechanism for doing the spin-table is also entirely different.
34
+ * We must have four 64-bit fields at absolute addresses
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
36
+ * our CPUs, and which we must ensure are zero initialized before
37
+ * the primary CPU goes into the kernel. We put these variables inside
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
39
+ */
40
+ static const uint32_t smpboot[] = {
41
+ 0xd2801b05, /* mov x5, 0xd8 */
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
43
+ 0x924004c6, /* and x6, x6, #0x3 */
44
+ 0xd503205f, /* spin: wfe */
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
46
+ 0xb4ffffc4, /* cbz x4, spin */
47
+ 0xd2800000, /* mov x0, #0x0 */
48
+ 0xd2800001, /* mov x1, #0x0 */
49
+ 0xd2800002, /* mov x2, #0x0 */
50
+ 0xd2800003, /* mov x3, #0x0 */
51
+ 0xd61f0080, /* br x4 */
52
+ };
53
+
54
+ static const uint64_t spintables[] = {
55
+ 0, 0, 0, 0
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
63
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
65
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
68
/* Pi2 and Pi3 requires SMP setup */
69
if (version >= 2) {
70
binfo.smp_loader_start = SMPBOOT_ADDR;
71
- binfo.write_secondary_boot = write_smpboot;
72
+ if (version == 2) {
73
+ binfo.write_secondary_boot = write_smpboot;
74
+ } else {
75
+ binfo.write_secondary_boot = write_smpboot64;
76
+ }
77
binfo.secondary_cpu_reset_hook = reset_secondary;
78
}
79
80
--
36
--
81
2.16.2
37
2.20.1
82
38
83
39
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
This patch fixes CID 1432800 by removing an unnecessary check.
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
5
controller which is supported in QEMU using the imx_fec.c module
6
(actually called imx.enet for this model.)
7
4
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
imx.enet device like this:
10
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
12
#define FSL_IMX6_ENET_MAC_IRQ 119
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
8
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
9
hw/core/register.c | 4 ----
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
10
1 file changed, 4 deletions(-)
46
2 files changed, 29 insertions(+), 3 deletions(-)
47
11
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
12
diff --git a/hw/core/register.c b/hw/core/register.c
49
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
14
--- a/hw/core/register.c
51
+++ b/include/hw/arm/fsl-imx6.h
15
+++ b/hw/core/register.c
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
16
@@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner,
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
17
int index = rae[i].addr / data_size;
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
18
RegisterInfo *r = &ri[index];
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
19
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
20
- if (data + data_size * index == 0 || !&rae[i]) {
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
21
- continue;
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
22
- }
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
23
-
60
#define FSL_IMX6_PCIE1_IRQ 120
24
/* Init the register, this will zero it. */
61
#define FSL_IMX6_PCIE2_IRQ 121
25
object_initialize((void *)r, sizeof(*r), TYPE_REGISTER);
62
#define FSL_IMX6_PCIE3_IRQ 122
26
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
66
+++ b/hw/net/imx_fec.c
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
68
69
static void imx_eth_update(IMXFECState *s)
70
{
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
72
+ /*
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
75
+ * and older) since Linux associated both interrupt lines with Ethernet
76
+ * MAC interrupts. Specifically,
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
79
+ * with swapped interrupt assignments.
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
82
+ * work, though that is accidental.
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
88
+ * Linux instead received MAC interrupts on the timer interrupt.
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
90
+ * albeit accidentally, but qemu versions with the correct interrupt
91
+ * assignment fail.
92
+ *
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
94
+ * interrrupts on both interrupt lines. This should be changed if and when
95
+ * qemu supports IOMUX.
96
+ */
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
99
qemu_set_irq(s->irq[1], 1);
100
} else {
101
qemu_set_irq(s->irq[1], 0);
102
--
27
--
103
2.16.2
28
2.20.1
104
29
105
30
diff view generated by jsdifflib
1
From: Wei Huang <wei@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN):
4
time when guest VM runs. To find the physical base address correctly,
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
4
10
Signed-off-by: Wei Huang <wei@redhat.com>
5
>>> Overrunning array "suffixes" of 7 8-byte elements at element
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
6
index 7 (byte offset 63) using index "idx" (which evaluates to 7).
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
7
8
Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
9
which is ~18.446 EHz, less than 1000 EHz.
10
11
Reported-by: Eduardo Habkost <ehabkost@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
16
Message-id: 20201101215755.2021421-1-f4bug@amsat.org
17
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
20
---
15
dump.c | 14 +++++++++++---
21
util/cutils.c | 3 ++-
16
1 file changed, 11 insertions(+), 3 deletions(-)
22
1 file changed, 2 insertions(+), 1 deletion(-)
17
23
18
diff --git a/dump.c b/dump.c
24
diff --git a/util/cutils.c b/util/cutils.c
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
26
--- a/util/cutils.c
21
+++ b/dump.c
27
+++ b/util/cutils.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
28
@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
23
29
double freq = freq_hz;
24
lines = g_strsplit((char *)vmci, "\n", -1);
30
size_t idx = 0;
25
for (i = 0; lines[i]; i++) {
31
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
32
- while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
33
+ while (freq >= 1000.0) {
28
+ const char *prefix = NULL;
34
freq /= 1000.0;
29
+
35
idx++;
30
+ if (s->dump_info.d_machine == EM_X86_64) {
36
}
31
+ prefix = "NUMBER(phys_base)=";
37
+ assert(idx < ARRAY_SIZE(suffixes));
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
38
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
39
return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
34
+ }
40
}
35
+
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
38
&phys_base) < 0) {
39
- warn_report("Failed to read NUMBER(phys_base)=");
40
+ warn_report("Failed to read %s", prefix);
41
} else {
42
s->dump_info.phys_base = phys_base;
43
}
44
--
41
--
45
2.16.2
42
2.20.1
46
43
47
44
diff view generated by jsdifflib
Deleted patch
1
For the rpi1 and 2 we want to boot the Linux kernel via some
2
custom setup code that makes sure that the SMC instruction
3
acts as a no-op, because it's used for cache maintenance.
4
The rpi3 boots AArch64 kernels, which don't need SMC for
5
cache maintenance and always expect to be booted non-secure.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
13
hw/arm/raspi.c | 17 +++++++++++++----
14
1 file changed, 13 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
21
binfo.board_id = raspi_boardid[version];
22
binfo.ram_size = ram_size;
23
binfo.nb_cpus = smp_cpus;
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
25
- binfo.write_board_setup = write_board_setup;
26
- binfo.secure_board_setup = true;
27
- binfo.secure_boot = true;
28
+
29
+ if (version <= 2) {
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
31
+ * mode before booting a kernel (to set up the SMC vectors so
32
+ * that we get a no-op SMC; this is used by Linux to call the
33
+ * firmware for some cache maintenance operations.
34
+ * The rpi3 doesn't need this.
35
+ */
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
37
+ binfo.write_board_setup = write_board_setup;
38
+ binfo.secure_board_setup = true;
39
+ binfo.secure_boot = true;
40
+ }
41
42
/* Pi2 and Pi3 requires SMP setup */
43
if (version >= 2) {
44
--
45
2.16.2
46
47
diff view generated by jsdifflib
Deleted patch
1
Add some assertions that if we're about to boot an AArch64 kernel,
2
the board code has not mistakenly set either secure_boot or
3
secure_board_setup. It doesn't make sense to set secure_boot,
4
because all AArch64 kernels must be booted in non-secure mode.
5
1
6
It might in theory make sense to set secure_board_setup, but
7
we don't currently support that, because only the AArch32
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
9
Since we don't have a current need for this functionality, just
10
assert that we don't try to use it. If it's needed we'll add
11
it later.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
16
---
17
hw/arm/boot.c | 7 +++++++
18
1 file changed, 7 insertions(+)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
+++ b/hw/arm/boot.c
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
25
} else {
26
env->pstate = PSTATE_MODE_EL1h;
27
}
28
+ /* AArch64 kernels never boot in secure mode */
29
+ assert(!info->secure_boot);
30
+ /* This hook is only supported for AArch32 currently:
31
+ * bootloader_aarch64[] will not call the hook, and
32
+ * the code above has already dropped us into EL2 or EL1.
33
+ */
34
+ assert(!info->secure_board_setup);
35
}
36
37
/* Set to non-secure if not a secure boot */
38
--
39
2.16.2
40
41
diff view generated by jsdifflib
Deleted patch
1
If we're directly booting a Linux kernel and the CPU supports both
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
4
instruction is enabled rather than UNDEFing. Otherwise at least some
5
kernels will panic when trying to initialize KVM in the guest.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
9
---
10
hw/arm/boot.c | 5 +++++
11
1 file changed, 5 insertions(+)
12
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
16
+++ b/hw/arm/boot.c
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
18
assert(!info->secure_board_setup);
19
}
20
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
23
+ env->cp15.scr_el3 |= SCR_HCE;
24
+ }
25
+
26
/* Set to non-secure if not a secure boot */
27
if (!info->secure_boot &&
28
(cs != first_cpu || !info->secure_board_setup)) {
29
--
30
2.16.2
31
32
diff view generated by jsdifflib
Deleted patch
1
The TypeInfo and state struct for bcm2386 disagree about what the
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
3
but the BCM2386State struct only defines the parent_obj field
4
as DeviceState. This would have caused problems if anything
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
8
provides.
9
1
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
14
---
15
hw/arm/bcm2836.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
21
+++ b/hw/arm/bcm2836.c
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
23
24
static const TypeInfo bcm2836_type_info = {
25
.name = TYPE_BCM2836,
26
- .parent = TYPE_SYS_BUS_DEVICE,
27
+ .parent = TYPE_DEVICE,
28
.instance_size = sizeof(BCM2836State),
29
.instance_init = bcm2836_init,
30
.class_init = bcm2836_class_init,
31
--
32
2.16.2
33
34
diff view generated by jsdifflib
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
In commit 76346b6264a9b01979 we tried to add a configure check that
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
2
the libgio pkg-config data was correct, which builds an executable
3
is required for Linux to boot.
3
linked against it. Unfortunately this doesn't catch the problem
4
(missing static library dependency info), because a "do nothing" test
5
source file doesn't have any symbol references that cause the linker
6
to pull in .o files from libgio.a, and so we don't see the "missing
7
symbols from libmount" error that a full QEMU link triggers.
8
9
(The ineffective test went unnoticed because of a typo that
10
effectively disabled libgio unconditionally, but after commit
11
3569a5dfc11f2 fixed that, a static link of the system emulator on
12
Ubuntu stopped working again.)
13
14
Improve the gio test by having the test source fragment reference a
15
g_dbus function (which is what is indirectly causing us to end up
16
wanting functions from libmount).
4
17
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
19
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
9
---
21
---
10
hw/arm/bcm2836.c | 11 +++++++----
22
configure | 11 +++++++++--
11
1 file changed, 7 insertions(+), 4 deletions(-)
23
1 file changed, 9 insertions(+), 2 deletions(-)
12
24
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
25
diff --git a/configure b/configure
14
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100755
15
--- a/hw/arm/bcm2836.c
27
--- a/configure
16
+++ b/hw/arm/bcm2836.c
28
+++ b/configure
17
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
18
30
# Check that the libraries actually work -- Ubuntu 18.04 ships
19
struct BCM283XInfo {
31
# with pkg-config --static --libs data for gio-2.0 that is missing
20
const char *name;
32
# -lblkid and will give a link error.
21
+ int clusterid;
33
- write_c_skeleton
22
};
34
- if compile_prog "" "$gio_libs" ; then
23
35
+ cat > $TMPC <<EOF
24
static const BCM283XInfo bcm283x_socs[] = {
36
+#include <gio/gio.h>
25
{
37
+int main(void)
26
.name = TYPE_BCM2836,
38
+{
27
+ .clusterid = 0xf,
39
+ g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
28
},
40
+ return 0;
29
{
41
+}
30
.name = TYPE_BCM2837,
42
+EOF
31
+ .clusterid = 0x0,
43
+ if compile_prog "$gio_cflags" "$gio_libs" ; then
32
},
44
gio=yes
33
};
45
else
34
46
gio=no
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
37
{
38
BCM283XState *s = BCM283X(dev);
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
40
+ const BCM283XInfo *info = bc->info;
41
Object *obj;
42
Error *err = NULL;
43
int n;
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
46
47
for (n = 0; n < BCM283X_NCPUS; n++) {
48
- /* Mirror bcm2836, which has clusterid set to 0xf
49
- * TODO: this should be converted to a property of ARM_CPU
50
- */
51
- s->cpus[n].mp_affinity = 0xF00 | n;
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
47
--
58
2.16.2
48
2.20.1
59
49
60
50
diff view generated by jsdifflib
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
2
some differences. Notably, the MPIDR affinity aff1 values it
2
power-up reset values for the T_low and T_high registers are 80 degrees C
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
3
and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These
4
uses, and if this is wrong Linux will not boot.
4
values are then shifted right by four bits to give the register reset
5
values, since both registers store the 12 bits of temperature data in bits
6
[15..4] of a 16 bit register.
5
7
6
Rather than trying to have one device with properties that
8
We were resetting these registers to zero, which is problematic for Linux
7
configure it differently for the two cases, create two
9
guests which enable the alert interrupt and then immediately take an
8
separate QOM devices for the two SoCs. We use the same approach
10
unexpected overtemperature alert because the current temperature is above
9
as hw/arm/aspeed_soc.c and share code and have a data table
11
freezing...
10
that might differ per-SoC. For the moment the two types don't
11
actually have different behaviour.
12
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
15
Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
16
---
16
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
17
hw/misc/tmp105.c | 3 +++
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
18
1 file changed, 3 insertions(+)
19
hw/arm/raspi.c | 3 ++-
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
19
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
20
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
23
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
22
--- a/hw/misc/tmp105.c
25
+++ b/include/hw/arm/bcm2836.h
23
+++ b/hw/misc/tmp105.c
26
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
27
25
s->faults = tmp105_faultq[(s->config >> 3) & 3];
28
#define BCM283X_NCPUS 4
26
s->alarm = 0;
29
27
30
+/* These type names are for specific SoCs; other than instantiating
28
+ s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
31
+ * them, code using these devices should always handle them via the
29
+ s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
33
+ */
34
+#define TYPE_BCM2836 "bcm2836"
35
+#define TYPE_BCM2837 "bcm2837"
36
+
30
+
37
typedef struct BCM283XState {
31
tmp105_interrupt_update(s);
38
/*< private >*/
39
DeviceState parent_obj;
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
41
BCM2835PeripheralState peripherals;
42
} BCM283XState;
43
44
+typedef struct BCM283XInfo BCM283XInfo;
45
+
46
+typedef struct BCM283XClass {
47
+ DeviceClass parent_class;
48
+ const BCM283XInfo *info;
49
+} BCM283XClass;
50
+
51
+#define BCM283X_CLASS(klass) \
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
53
+#define BCM283X_GET_CLASS(obj) \
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
55
+
56
#endif /* BCM2836_H */
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/bcm2836.c
60
+++ b/hw/arm/bcm2836.c
61
@@ -XXX,XX +XXX,XX @@
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
63
#define BCM2836_CONTROL_BASE 0x40000000
64
65
+struct BCM283XInfo {
66
+ const char *name;
67
+};
68
+
69
+static const BCM283XInfo bcm283x_socs[] = {
70
+ {
71
+ .name = TYPE_BCM2836,
72
+ },
73
+ {
74
+ .name = TYPE_BCM2837,
75
+ },
76
+};
77
+
78
static void bcm2836_init(Object *obj)
79
{
80
BCM283XState *s = BCM283X(obj);
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
82
DEFINE_PROP_END_OF_LIST()
83
};
84
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
32
}
96
33
97
-static const TypeInfo bcm2836_type_info = {
98
+static const TypeInfo bcm283x_type_info = {
99
.name = TYPE_BCM283X,
100
.parent = TYPE_DEVICE,
101
.instance_size = sizeof(BCM283XState),
102
.instance_init = bcm2836_init,
103
- .class_init = bcm2836_class_init,
104
+ .class_size = sizeof(BCM283XClass),
105
+ .abstract = true,
106
};
107
108
static void bcm2836_register_types(void)
109
{
110
- type_register_static(&bcm2836_type_info);
111
+ int i;
112
+
113
+ type_register_static(&bcm283x_type_info);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
115
+ TypeInfo ti = {
116
+ .name = bcm283x_socs[i].name,
117
+ .parent = TYPE_BCM283X,
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
123
}
124
125
type_init(bcm2836_register_types)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/raspi.c
129
+++ b/hw/arm/raspi.c
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
135
+ object_initialize(&s->soc, sizeof(s->soc),
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
138
&error_abort);
139
140
--
34
--
141
2.16.2
35
2.20.1
142
36
143
37
diff view generated by jsdifflib
1
Our BCM2836 type is really a generic one that can be any of
1
The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
2
the bcm283x family. Rename it accordingly. We change only
2
signals an alert when the temperature equals or exceeds the T_high value and
3
the names which are visible via the header file to the
3
then remains high until a device register is read or the device responds to
4
rest of the QEMU code, leaving private function names
4
the SMBUS Alert Response address, or the device is put into Shutdown Mode.
5
in bcm2836.c as they are.
5
Thereafter the Alert pin will only be re-signalled when temperature falls
6
below T_low; alert can then be cleared in the same set of ways, and the
7
device returns to its initial "alert when temperature goes above T_high"
8
mode. (If this textual description is confusing, see figure 3 in the
9
TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)
6
10
7
This is a preliminary to making bcm283x be an abstract
11
We were misimplementing this as a simple "always alert if temperature is
8
parent class to specific types for the bcm2836 and bcm2837.
12
above T_high or below T_low" condition, which gives a spurious alert on
13
startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
14
limit values.
15
16
Implement the correct (hysteresis) behaviour by tracking whether we
17
are currently looking for the temperature to rise over T_high or
18
for it to fall below T_low. Our implementation of the comparator
19
mode (TM==0) wasn't wrong, but rephrase it to match the way that
20
interrupt mode is now handled for clarity.
9
21
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
23
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
24
Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
25
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
26
hw/misc/tmp105.h | 7 +++++
16
hw/arm/bcm2836.c | 17 +++++++++--------
27
hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
17
hw/arm/raspi.c | 16 ++++++++--------
28
2 files changed, 68 insertions(+), 9 deletions(-)
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
29
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
30
diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
21
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
32
--- a/hw/misc/tmp105.h
23
+++ b/include/hw/arm/bcm2836.h
33
+++ b/hw/misc/tmp105.h
24
@@ -XXX,XX +XXX,XX @@
34
@@ -XXX,XX +XXX,XX @@ struct TMP105State {
25
#include "hw/arm/bcm2835_peripherals.h"
35
int16_t limit[2];
26
#include "hw/intc/bcm2836_control.h"
36
int faults;
27
37
uint8_t alarm;
28
-#define TYPE_BCM2836 "bcm2836"
38
+ /*
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
39
+ * The TMP105 initially looks for a temperature rising above T_high;
30
+#define TYPE_BCM283X "bcm283x"
40
+ * once this is detected, the condition it looks for next is the
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
41
+ * temperature falling below T_low. This flag is false when initially
32
42
+ * looking for T_high, true when looking for T_low.
33
-#define BCM2836_NCPUS 4
43
+ */
34
+#define BCM283X_NCPUS 4
44
+ bool detect_falling;
35
45
};
36
-typedef struct BCM2836State {
46
37
+typedef struct BCM283XState {
47
#endif
38
/*< private >*/
48
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
39
DeviceState parent_obj;
40
/*< public >*/
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
42
char *cpu_type;
43
uint32_t enabled_cpus;
44
45
- ARMCPU cpus[BCM2836_NCPUS];
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
BCM2836ControlState control;
48
BCM2835PeripheralState peripherals;
49
-} BCM2836State;
50
+} BCM283XState;
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
50
--- a/hw/misc/tmp105.c
56
+++ b/hw/arm/bcm2836.c
51
+++ b/hw/misc/tmp105.c
57
@@ -XXX,XX +XXX,XX @@
52
@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
58
53
return;
59
static void bcm2836_init(Object *obj)
54
}
60
{
55
61
- BCM2836State *s = BCM2836(obj);
56
- if ((s->config >> 1) & 1) {                    /* TM */
62
+ BCM283XState *s = BCM283X(obj);
57
- if (s->temperature >= s->limit[1])
63
58
- s->alarm = 1;
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
59
- else if (s->temperature < s->limit[0])
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
60
- s->alarm = 1;
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
61
+ if (s->config >> 1 & 1) {
67
62
+ /*
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
63
+ * TM == 1 : Interrupt mode. We signal Alert when the
69
{
64
+ * temperature rises above T_high, and expect the guest to clear
70
- BCM2836State *s = BCM2836(dev);
65
+ * it (eg by reading a device register).
71
+ BCM283XState *s = BCM283X(dev);
66
+ */
72
Object *obj;
67
+ if (s->detect_falling) {
73
Error *err = NULL;
68
+ if (s->temperature < s->limit[0]) {
74
int n;
69
+ s->alarm = 1;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
70
+ s->detect_falling = false;
76
/* common peripherals from bcm2835 */
71
+ }
77
72
+ } else {
78
obj = OBJECT(dev);
73
+ if (s->temperature >= s->limit[1]) {
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
74
+ s->alarm = 1;
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
75
+ s->detect_falling = true;
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
76
+ }
82
s->cpu_type);
77
+ }
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
78
} else {
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
79
- if (s->temperature >= s->limit[1])
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
80
- s->alarm = 1;
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
81
- else if (s->temperature < s->limit[0])
87
82
- s->alarm = 0;
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
83
+ /*
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
84
+ * TM == 0 : Comparator mode. We signal Alert when the temperature
90
/* Mirror bcm2836, which has clusterid set to 0xf
85
+ * rises above T_high, and stop signalling it when the temperature
91
* TODO: this should be converted to a property of ARM_CPU
86
+ * falls below T_low.
92
*/
87
+ */
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
88
+ if (s->detect_falling) {
89
+ if (s->temperature < s->limit[0]) {
90
+ s->alarm = 0;
91
+ s->detect_falling = false;
92
+ }
93
+ } else {
94
+ if (s->temperature >= s->limit[1]) {
95
+ s->alarm = 1;
96
+ s->detect_falling = true;
97
+ }
98
+ }
99
}
100
101
tmp105_interrupt_update(s);
102
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
103
return 0;
94
}
104
}
95
105
96
static Property bcm2836_props[] = {
106
+static bool detect_falling_needed(void *opaque)
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
107
+{
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
108
+ TMP105State *s = opaque;
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
109
+
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
110
+ /*
101
+ BCM283X_NCPUS),
111
+ * We only need to migrate the detect_falling bool if it's set;
102
DEFINE_PROP_END_OF_LIST()
112
+ * for migration from older machines we assume that it is false
113
+ * (ie temperature is not out of range).
114
+ */
115
+ return s->detect_falling;
116
+}
117
+
118
+static const VMStateDescription vmstate_tmp105_detect_falling = {
119
+ .name = "TMP105/detect-falling",
120
+ .version_id = 1,
121
+ .minimum_version_id = 1,
122
+ .needed = detect_falling_needed,
123
+ .fields = (VMStateField[]) {
124
+ VMSTATE_BOOL(detect_falling, TMP105State),
125
+ VMSTATE_END_OF_LIST()
126
+ }
127
+};
128
+
129
static const VMStateDescription vmstate_tmp105 = {
130
.name = "TMP105",
131
.version_id = 0,
132
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
133
VMSTATE_UINT8(alarm, TMP105State),
134
VMSTATE_I2C_SLAVE(i2c, TMP105State),
135
VMSTATE_END_OF_LIST()
136
+ },
137
+ .subsections = (const VMStateDescription*[]) {
138
+ &vmstate_tmp105_detect_falling,
139
+ NULL
140
}
103
};
141
};
104
142
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
143
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
106
}
144
s->config = 0;
107
145
s->faults = tmp105_faultq[(s->config >> 3) & 3];
108
static const TypeInfo bcm2836_type_info = {
146
s->alarm = 0;
109
- .name = TYPE_BCM2836,
147
+ s->detect_falling = false;
110
+ .name = TYPE_BCM283X,
148
111
.parent = TYPE_DEVICE,
149
s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
112
- .instance_size = sizeof(BCM2836State),
150
s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
113
+ .instance_size = sizeof(BCM283XState),
114
.instance_init = bcm2836_init,
115
.class_init = bcm2836_class_init,
116
};
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/arm/raspi.c
120
+++ b/hw/arm/raspi.c
121
@@ -XXX,XX +XXX,XX @@
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
123
124
typedef struct RasPiState {
125
- BCM2836State soc;
126
+ BCM283XState soc;
127
MemoryRegion ram;
128
} RasPiState;
129
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
165
--
151
--
166
2.16.2
152
2.20.1
167
153
168
154
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