1
Arm patch queue -- these are all bug fix patches but we might
1
Nothing earth-shaking in here, just a lot of refactoring and cleanup
2
as well put them in to rc0...
2
and a few bugfixes. I suspect I'll have another pullreq to come in
3
the early part of next week...
3
4
4
thanks
5
The following changes since commit 19591e9e0938ea5066984553c256a043bd5d822f:
5
-- PMM
6
6
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
7
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-08-27 16:59:02 +0100)
8
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
10
8
11
are available in the Git repository at:
9
are available in the Git repository at:
12
10
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200828
14
12
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
13
for you to fetch changes up to ed78849d9711805bda37ee026018d6ee7a606d0e:
16
14
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
15
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd (2020-08-28 10:02:50 +0100)
18
16
19
----------------------------------------------------------------
17
----------------------------------------------------------------
20
target-arm queue:
18
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
19
* target/arm: Cleanup and refactoring preparatory to SVE2
22
* dump: Update correct kdump phys_base field for AArch64
20
* armsse: Define ARMSSEClass correctly
23
* char: i.MX: Add support for "TX complete" interrupt
21
* hw/misc/unimp: Improve information provided in log messages
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
22
* hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
25
to boot a Debian Linux kernel on raspi3
23
* hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
24
* hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
25
* hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
26
* target/arm: Fill in the WnR syndrome bit in mte_check_fail
27
* target/arm: Clarify HCR_EL2 ARMCPRegInfo type
28
* hw/arm/musicpal: Use AddressSpace for DMA transfers
29
* hw/clock: Minor cleanups
30
* hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
26
31
27
----------------------------------------------------------------
32
----------------------------------------------------------------
28
Andrey Smirnov (2):
33
Eduardo Habkost (1):
29
char: i.MX: Simplify imx_update()
34
armsse: Define ARMSSEClass correctly
30
char: i.MX: Add support for "TX complete" interrupt
31
35
32
Guenter Roeck (1):
36
Graeme Gregory (1):
33
fsl-imx6: Swap Ethernet interrupt defines
37
hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
34
38
35
Peter Maydell (9):
39
Philippe Mathieu-Daudé (14):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
40
hw/clock: Remove unused clock_init*() functions
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
41
hw/clock: Let clock_set() return boolean value
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
42
hw/clock: Only propagate clock changes if the clock is changed
39
hw/arm/bcm2386: Fix parent type of bcm2386
43
hw/arm/musicpal: Use AddressSpace for DMA transfers
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
44
target/arm: Clarify HCR_EL2 ARMCPRegInfo type
41
hw/arm/bcm2836: Create proper bcm2837 device
45
hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
46
hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
43
hw/arm/bcm2836: Hardcode correct CPU type
47
hw/arm/xilinx_zynq: Uninline cadence_uart_create()
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
48
hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
49
hw/qdev-clock: Uninline qdev_connect_clock_in()
50
hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
51
hw/misc/unimp: Display value after offset
52
hw/misc/unimp: Display the value with width of the access size
53
hw/misc/unimp: Display the offset with width of the region size
45
54
46
Wei Huang (1):
55
Richard Henderson (19):
47
dump: Update correct kdump phys_base field for AArch64
56
target/arm: Pass the entire mte descriptor to mte_check_fail
57
target/arm: Fill in the WnR syndrome bit in mte_check_fail
58
qemu/int128: Add int128_lshift
59
target/arm: Split out gen_gvec_fn_zz
60
target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
61
target/arm: Rearrange {sve,fp}_check_access assert
62
target/arm: Merge do_vector2_p into do_mov_p
63
target/arm: Clean up 4-operand predicate expansion
64
target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
65
target/arm: Split out gen_gvec_ool_zzzp
66
target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
67
target/arm: Split out gen_gvec_ool_zzp
68
target/arm: Split out gen_gvec_ool_zzz
69
target/arm: Split out gen_gvec_ool_zz
70
target/arm: Tidy SVE tszimm shift formats
71
target/arm: Generalize inl_qrdmlah_* helper functions
72
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
73
target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
74
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
48
75
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
76
include/hw/arm/armsse.h | 2 +-
50
include/hw/arm/fsl-imx6.h | 4 +-
77
include/hw/char/cadence_uart.h | 17 --
51
include/hw/char/imx_serial.h | 3 ++
78
include/hw/clock.h | 30 +--
52
dump.c | 14 +++++--
79
include/hw/misc/unimp.h | 1 +
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
80
include/hw/net/allwinner-sun8i-emac.h | 6 +
54
hw/arm/boot.c | 12 ++++++
81
include/hw/qdev-clock.h | 8 +-
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
82
include/hw/sd/allwinner-sdhost.h | 6 +
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
83
include/qemu/int128.h | 16 ++
57
hw/net/imx_fec.c | 28 +++++++++++++-
84
target/arm/helper-sve.h | 5 -
58
9 files changed, 237 insertions(+), 63 deletions(-)
85
target/arm/helper.h | 28 +++
86
target/arm/translate.h | 1 +
87
target/arm/sve.decode | 35 ++-
88
hw/arm/allwinner-a10.c | 2 +
89
hw/arm/allwinner-h3.c | 4 +
90
hw/arm/armsse.c | 1 +
91
hw/arm/musicpal.c | 45 ++--
92
hw/arm/sbsa-ref.c | 2 +-
93
hw/arm/xilinx_zynq.c | 24 +-
94
hw/core/clock.c | 7 +-
95
hw/core/qdev-clock.c | 6 +
96
hw/misc/unimp.c | 14 +-
97
hw/net/allwinner-sun8i-emac.c | 46 ++--
98
hw/sd/allwinner-sdhost.c | 37 +++-
99
target/arm/helper.c | 1 -
100
target/arm/mte_helper.c | 19 +-
101
target/arm/sve_helper.c | 70 ++----
102
target/arm/translate-a64.c | 110 ++++++++--
103
target/arm/translate-sve.c | 399 ++++++++++++++--------------------
104
target/arm/vec_helper.c | 182 +++++++++++-----
105
29 files changed, 629 insertions(+), 495 deletions(-)
59
106
diff view generated by jsdifflib
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
From: Graeme Gregory <graeme@nuviainc.com>
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
3
but the BCM2386State struct only defines the parent_obj field
4
as DeviceState. This would have caused problems if anything
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
8
provides.
9
2
3
Fixing a typo in a previous patch that translated an "i" to a 1
4
and therefore breaking the allocation of PCIe interrupts. This was
5
discovered when virtio-net-pci devices ceased to function correctly.
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
9
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200821083853.356490-1-graeme@nuviainc.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
14
---
13
---
15
hw/arm/bcm2836.c | 2 +-
14
hw/arm/sbsa-ref.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
17
16
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
19
--- a/hw/arm/sbsa-ref.c
21
+++ b/hw/arm/bcm2836.c
20
+++ b/hw/arm/sbsa-ref.c
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
21
@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)
23
22
24
static const TypeInfo bcm2836_type_info = {
23
for (i = 0; i < GPEX_NUM_IRQS; i++) {
25
.name = TYPE_BCM2836,
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
26
- .parent = TYPE_SYS_BUS_DEVICE,
25
- qdev_get_gpio_in(sms->gic, irq + 1));
27
+ .parent = TYPE_DEVICE,
26
+ qdev_get_gpio_in(sms->gic, irq + i));
28
.instance_size = sizeof(BCM2836State),
27
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
29
.instance_init = bcm2836_init,
28
}
30
.class_init = bcm2836_class_init,
29
31
--
30
--
32
2.16.2
31
2.20.1
33
32
34
33
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
clock_init*() inlined funtions are simple wrappers around
4
clock_set*() and are not used. Remove them in favor of clock_set*().
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200806123858.30058-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/clock.h | 13 -------------
12
1 file changed, 13 deletions(-)
13
14
diff --git a/include/hw/clock.h b/include/hw/clock.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/clock.h
17
+++ b/include/hw/clock.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool clock_is_enabled(const Clock *clk)
19
return clock_get(clk) != 0;
20
}
21
22
-static inline void clock_init(Clock *clk, uint64_t value)
23
-{
24
- clock_set(clk, value);
25
-}
26
-static inline void clock_init_hz(Clock *clk, uint64_t value)
27
-{
28
- clock_set_hz(clk, value);
29
-}
30
-static inline void clock_init_ns(Clock *clk, uint64_t value)
31
-{
32
- clock_set_ns(clk, value);
33
-}
34
-
35
#endif /* QEMU_HW_CLOCK_H */
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Let clock_set() return a boolean value whether the clock
4
has been updated or not.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200806123858.30058-3-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/clock.h | 12 +++++++-----
12
hw/core/clock.c | 7 ++++++-
13
2 files changed, 13 insertions(+), 6 deletions(-)
14
15
diff --git a/include/hw/clock.h b/include/hw/clock.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/clock.h
18
+++ b/include/hw/clock.h
19
@@ -XXX,XX +XXX,XX @@ void clock_set_source(Clock *clk, Clock *src);
20
* @value: the clock's value, 0 means unclocked
21
*
22
* Set the local cached period value of @clk to @value.
23
+ *
24
+ * @return: true if the clock is changed.
25
*/
26
-void clock_set(Clock *clk, uint64_t value);
27
+bool clock_set(Clock *clk, uint64_t value);
28
29
-static inline void clock_set_hz(Clock *clk, unsigned hz)
30
+static inline bool clock_set_hz(Clock *clk, unsigned hz)
31
{
32
- clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
33
+ return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
34
}
35
36
-static inline void clock_set_ns(Clock *clk, unsigned ns)
37
+static inline bool clock_set_ns(Clock *clk, unsigned ns)
38
{
39
- clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
40
+ return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
41
}
42
43
/**
44
diff --git a/hw/core/clock.c b/hw/core/clock.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/core/clock.c
47
+++ b/hw/core/clock.c
48
@@ -XXX,XX +XXX,XX @@ void clock_clear_callback(Clock *clk)
49
clock_set_callback(clk, NULL, NULL);
50
}
51
52
-void clock_set(Clock *clk, uint64_t period)
53
+bool clock_set(Clock *clk, uint64_t period)
54
{
55
+ if (clk->period == period) {
56
+ return false;
57
+ }
58
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
59
CLOCK_PERIOD_TO_NS(period));
60
clk->period = period;
61
+
62
+ return true;
63
}
64
65
static void clock_propagate_period(Clock *clk, bool call_callbacks)
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Avoid propagating the clock change when the clock does not change.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200806123858.30058-4-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/clock.h | 5 +++--
11
1 file changed, 3 insertions(+), 2 deletions(-)
12
13
diff --git a/include/hw/clock.h b/include/hw/clock.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/clock.h
16
+++ b/include/hw/clock.h
17
@@ -XXX,XX +XXX,XX @@ void clock_propagate(Clock *clk);
18
*/
19
static inline void clock_update(Clock *clk, uint64_t value)
20
{
21
- clock_set(clk, value);
22
- clock_propagate(clk);
23
+ if (clock_set(clk, value)) {
24
+ clock_propagate(clk);
25
+ }
26
}
27
28
static inline void clock_update_hz(Clock *clk, unsigned hz)
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
3
is required for Linux to boot.
4
2
3
Allow the device to execute the DMA transfers in a different
4
AddressSpace.
5
6
We keep using the system_memory address space, but via the
7
proper dma_memory_access() API.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200814125533.4047-1-f4bug@amsat.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
9
---
13
---
10
hw/arm/bcm2836.c | 11 +++++++----
14
hw/arm/musicpal.c | 45 +++++++++++++++++++++++++++++++--------------
11
1 file changed, 7 insertions(+), 4 deletions(-)
15
1 file changed, 31 insertions(+), 14 deletions(-)
12
16
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
19
--- a/hw/arm/musicpal.c
16
+++ b/hw/arm/bcm2836.c
20
+++ b/hw/arm/musicpal.c
17
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
18
22
#include "hw/audio/wm8750.h"
19
struct BCM283XInfo {
23
#include "sysemu/block-backend.h"
20
const char *name;
24
#include "sysemu/runstate.h"
21
+ int clusterid;
25
+#include "sysemu/dma.h"
26
#include "exec/address-spaces.h"
27
#include "ui/pixel_ops.h"
28
#include "qemu/cutils.h"
29
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
30
31
MemoryRegion iomem;
32
qemu_irq irq;
33
+ MemoryRegion *dma_mr;
34
+ AddressSpace dma_as;
35
uint32_t smir;
36
uint32_t icr;
37
uint32_t imr;
38
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
39
NICConf conf;
40
} mv88w8618_eth_state;
41
42
-static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
43
+static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr,
44
+ mv88w8618_rx_desc *desc)
45
{
46
cpu_to_le32s(&desc->cmdstat);
47
cpu_to_le16s(&desc->bytes);
48
cpu_to_le16s(&desc->buffer_size);
49
cpu_to_le32s(&desc->buffer);
50
cpu_to_le32s(&desc->next);
51
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
52
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
53
}
54
55
-static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
56
+static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr,
57
+ mv88w8618_rx_desc *desc)
58
{
59
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
60
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
61
le32_to_cpus(&desc->cmdstat);
62
le16_to_cpus(&desc->bytes);
63
le16_to_cpus(&desc->buffer_size);
64
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
65
continue;
66
}
67
do {
68
- eth_rx_desc_get(desc_addr, &desc);
69
+ eth_rx_desc_get(&s->dma_as, desc_addr, &desc);
70
if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
71
- cpu_physical_memory_write(desc.buffer + s->vlan_header,
72
+ dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header,
73
buf, size);
74
desc.bytes = size + s->vlan_header;
75
desc.cmdstat &= ~MP_ETH_RX_OWN;
76
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
77
if (s->icr & s->imr) {
78
qemu_irq_raise(s->irq);
79
}
80
- eth_rx_desc_put(desc_addr, &desc);
81
+ eth_rx_desc_put(&s->dma_as, desc_addr, &desc);
82
return size;
83
}
84
desc_addr = desc.next;
85
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
86
return size;
87
}
88
89
-static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
90
+static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr,
91
+ mv88w8618_tx_desc *desc)
92
{
93
cpu_to_le32s(&desc->cmdstat);
94
cpu_to_le16s(&desc->res);
95
cpu_to_le16s(&desc->bytes);
96
cpu_to_le32s(&desc->buffer);
97
cpu_to_le32s(&desc->next);
98
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
99
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
100
}
101
102
-static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
103
+static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr,
104
+ mv88w8618_tx_desc *desc)
105
{
106
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
107
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
108
le32_to_cpus(&desc->cmdstat);
109
le16_to_cpus(&desc->res);
110
le16_to_cpus(&desc->bytes);
111
@@ -XXX,XX +XXX,XX @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
112
int len;
113
114
do {
115
- eth_tx_desc_get(desc_addr, &desc);
116
+ eth_tx_desc_get(&s->dma_as, desc_addr, &desc);
117
next_desc = desc.next;
118
if (desc.cmdstat & MP_ETH_TX_OWN) {
119
len = desc.bytes;
120
if (len < 2048) {
121
- cpu_physical_memory_read(desc.buffer, buf, len);
122
+ dma_memory_read(&s->dma_as, desc.buffer, buf, len);
123
qemu_send_packet(qemu_get_queue(s->nic), buf, len);
124
}
125
desc.cmdstat &= ~MP_ETH_TX_OWN;
126
s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
127
- eth_tx_desc_put(desc_addr, &desc);
128
+ eth_tx_desc_put(&s->dma_as, desc_addr, &desc);
129
}
130
desc_addr = next_desc;
131
} while (desc_addr != s->tx_queue[queue_index]);
132
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_eth_realize(DeviceState *dev, Error **errp)
133
{
134
mv88w8618_eth_state *s = MV88W8618_ETH(dev);
135
136
+ if (!s->dma_mr) {
137
+ error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set");
138
+ return;
139
+ }
140
+
141
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
142
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
143
object_get_typename(OBJECT(dev)), dev->id, s);
144
}
145
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mv88w8618_eth_vmsd = {
146
147
static Property mv88w8618_eth_properties[] = {
148
DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
149
+ DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr,
150
+ TYPE_MEMORY_REGION, MemoryRegion *),
151
DEFINE_PROP_END_OF_LIST(),
22
};
152
};
23
153
24
static const BCM283XInfo bcm283x_socs[] = {
154
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
25
{
155
qemu_check_nic_model(&nd_table[0], "mv88w8618");
26
.name = TYPE_BCM2836,
156
dev = qdev_new(TYPE_MV88W8618_ETH);
27
+ .clusterid = 0xf,
157
qdev_set_nic_properties(dev, &nd_table[0]);
28
},
158
+ object_property_set_link(OBJECT(dev), "dma-memory",
29
{
159
+ OBJECT(get_system_memory()), &error_fatal);
30
.name = TYPE_BCM2837,
160
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
31
+ .clusterid = 0x0,
161
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
32
},
162
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
33
};
34
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
37
{
38
BCM283XState *s = BCM283X(dev);
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
40
+ const BCM283XInfo *info = bc->info;
41
Object *obj;
42
Error *err = NULL;
43
int n;
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
46
47
for (n = 0; n < BCM283X_NCPUS; n++) {
48
- /* Mirror bcm2836, which has clusterid set to 0xf
49
- * TODO: this should be converted to a property of ARM_CPU
50
- */
51
- s->cpus[n].mp_affinity = 0xF00 | n;
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
163
--
58
2.16.2
164
2.20.1
59
165
60
166
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
In commit ce4afed839 ("target/arm: Implement AArch32 HCR and HCR2")
4
the HCR_EL2 register has been changed from type NO_RAW (no underlying
5
state and does not support raw access for state saving/loading) to
6
type CONST (TCG can assume the value to be constant), removing the
7
read/write accessors.
8
We forgot to remove the previous type ARM_CP_NO_RAW. This is not
9
really a problem since the field is overwritten. However it makes
10
code review confuse, so remove it.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200812111223.7787-1-f4bug@amsat.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 1 -
19
1 file changed, 1 deletion(-)
20
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
26
.access = PL2_RW,
27
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
28
{ .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
29
- .type = ARM_CP_NO_RAW,
30
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
31
.access = PL2_RW,
32
.type = ARM_CP_CONST, .resetvalue = 0 },
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We need more information than just the mmu_idx in order
4
to create the proper exception syndrome. Only change the
5
function signature so far.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200813200816.3037186-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/mte_helper.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/mte_helper.c
18
+++ b/target/arm/mte_helper.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
20
}
21
22
/* Record a tag check failure. */
23
-static void mte_check_fail(CPUARMState *env, int mmu_idx,
24
+static void mte_check_fail(CPUARMState *env, uint32_t desc,
25
uint64_t dirty_ptr, uintptr_t ra)
26
{
27
+ int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
28
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
29
int el, reg_el, tcf, select;
30
uint64_t sctlr;
31
@@ -XXX,XX +XXX,XX @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc,
32
}
33
34
if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
35
- int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
36
- mte_check_fail(env, mmu_idx, ptr, ra);
37
+ mte_check_fail(env, desc, ptr, ra);
38
}
39
40
return useronly_clean_ptr(ptr);
41
@@ -XXX,XX +XXX,XX @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
42
43
fail_ofs = tag_first + n * TAG_GRANULE - ptr;
44
fail_ofs = ROUND_UP(fail_ofs, esize);
45
- mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra);
46
+ mte_check_fail(env, desc, ptr + fail_ofs, ra);
47
}
48
49
done:
50
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)
51
fail:
52
/* Locate the first nibble that differs. */
53
i = ctz64(mem_tag ^ ptr_tag) >> 4;
54
- mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra);
55
+ mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra);
56
57
done:
58
return useronly_clean_ptr(ptr);
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
According to AArch64.TagCheckFault, none of the other ISS values are
4
provided, so we do not need to go so far as merge_syn_data_abort.
5
But we were missing the WnR bit.
6
7
Tested-by: Andrey Konovalov <andreyknvl@google.com>
8
Reported-by: Andrey Konovalov <andreyknvl@google.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200813200816.3037186-3-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/mte_helper.c | 9 +++++----
15
1 file changed, 5 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/mte_helper.c
20
+++ b/target/arm/mte_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
22
{
23
int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
24
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
25
- int el, reg_el, tcf, select;
26
+ int el, reg_el, tcf, select, is_write, syn;
27
uint64_t sctlr;
28
29
reg_el = regime_el(env, arm_mmu_idx);
30
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
31
*/
32
cpu_restore_state(env_cpu(env), ra, true);
33
env->exception.vaddress = dirty_ptr;
34
- raise_exception(env, EXCP_DATA_ABORT,
35
- syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0, 0x11),
36
- exception_target_el(env));
37
+
38
+ is_write = FIELD_EX32(desc, MTEDESC, WRITE);
39
+ syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
40
+ raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
41
/* noreturn, but fall through to the assert anyway */
42
43
case 0:
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
just hard-code the CPU type they use rather than having it passed
3
through as an object property. This then lets us put the initialization
4
of the CPU object in init rather than realize.
5
2
6
Note that this change means that it's no longer possible on
3
Allow the device to execute the DMA transfers in a different
7
the command line to use -cpu to ask for a different kind of
4
AddressSpace.
8
CPU than the SoC supports. This was never a supported thing to
9
do anyway; we were just not sanity-checking the command line.
10
5
11
This does require us to only build the bcm2837 object on
6
The A10 and H3 SoC keep using the system_memory address space,
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
7
but via the proper dma_memory_access() API.
13
due to the missing cortex-a53 device and "make check" will fail.
14
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Message-id: 20200814110057.307-1-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
14
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
15
include/hw/sd/allwinner-sdhost.h | 6 ++++++
21
hw/arm/raspi.c | 2 --
16
hw/arm/allwinner-a10.c | 2 ++
22
2 files changed, 15 insertions(+), 11 deletions(-)
17
hw/arm/allwinner-h3.c | 2 ++
18
hw/sd/allwinner-sdhost.c | 37 ++++++++++++++++++++++++++------
19
4 files changed, 41 insertions(+), 6 deletions(-)
23
20
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
21
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
23
--- a/include/hw/sd/allwinner-sdhost.h
27
+++ b/hw/arm/bcm2836.c
24
+++ b/include/hw/sd/allwinner-sdhost.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSdHostState {
26
/** Interrupt output signal to notify CPU */
27
qemu_irq irq;
28
29
+ /** Memory region where DMA transfers are done */
30
+ MemoryRegion *dma_mr;
31
+
32
+ /** Address space used internally for DMA transfers */
33
+ AddressSpace dma_as;
34
+
35
/** Number of bytes left in current DMA transfer */
36
uint32_t transfer_cnt;
37
38
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/allwinner-a10.c
41
+++ b/hw/arm/allwinner-a10.c
42
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
43
}
44
45
/* SD/MMC */
46
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
47
+ OBJECT(get_system_memory()), &error_fatal);
48
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
51
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/allwinner-h3.c
54
+++ b/hw/arm/allwinner-h3.c
55
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
56
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
57
58
/* SD/MMC */
59
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
60
+ OBJECT(get_system_memory()), &error_fatal);
61
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
62
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
63
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
64
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/sd/allwinner-sdhost.c
67
+++ b/hw/sd/allwinner-sdhost.c
28
@@ -XXX,XX +XXX,XX @@
68
@@ -XXX,XX +XXX,XX @@
29
69
#include "qemu/log.h"
30
struct BCM283XInfo {
70
#include "qemu/module.h"
31
const char *name;
71
#include "qemu/units.h"
32
+ const char *cpu_type;
72
+#include "qapi/error.h"
33
int clusterid;
73
#include "sysemu/blockdev.h"
74
+#include "sysemu/dma.h"
75
+#include "hw/qdev-properties.h"
76
#include "hw/irq.h"
77
#include "hw/sd/allwinner-sdhost.h"
78
#include "migration/vmstate.h"
79
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
80
uint8_t buf[1024];
81
82
/* Read descriptor */
83
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
84
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
85
if (desc->size == 0) {
86
desc->size = klass->max_desc_size;
87
} else if (desc->size > klass->max_desc_size) {
88
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
89
90
/* Write to SD bus */
91
if (is_write) {
92
- cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
93
- buf, buf_bytes);
94
+ dma_memory_read(&s->dma_as,
95
+ (desc->addr & DESC_SIZE_MASK) + num_done,
96
+ buf, buf_bytes);
97
sdbus_write_data(&s->sdbus, buf, buf_bytes);
98
99
/* Read from SD bus */
100
} else {
101
sdbus_read_data(&s->sdbus, buf, buf_bytes);
102
- cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
103
- buf, buf_bytes);
104
+ dma_memory_write(&s->dma_as,
105
+ (desc->addr & DESC_SIZE_MASK) + num_done,
106
+ buf, buf_bytes);
107
}
108
num_done += buf_bytes;
109
}
110
111
/* Clear hold flag and flush descriptor */
112
desc->status &= ~DESC_STATUS_HOLD;
113
- cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
114
+ dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc));
115
116
return num_done;
117
}
118
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_allwinner_sdhost = {
119
}
34
};
120
};
35
121
36
static const BCM283XInfo bcm283x_socs[] = {
122
+static Property allwinner_sdhost_properties[] = {
37
{
123
+ DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
38
.name = TYPE_BCM2836,
124
+ TYPE_MEMORY_REGION, MemoryRegion *),
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
125
+ DEFINE_PROP_END_OF_LIST(),
40
.clusterid = 0xf,
126
+};
41
},
127
+
42
+#ifdef TARGET_AARCH64
128
static void allwinner_sdhost_init(Object *obj)
43
{
44
.name = TYPE_BCM2837,
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
46
.clusterid = 0x0,
47
},
48
+#endif
49
};
50
51
static void bcm2836_init(Object *obj)
52
{
129
{
53
BCM283XState *s = BCM283X(obj);
130
AwSdHostState *s = AW_SDHOST(obj);
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
131
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
55
+ const BCM283XInfo *info = bc->info;
132
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
56
+ int n;
133
}
134
135
+static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
136
+{
137
+ AwSdHostState *s = AW_SDHOST(dev);
57
+
138
+
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
139
+ if (!s->dma_mr) {
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
140
+ error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
60
+ info->cpu_type);
141
+ return;
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
62
+ &error_abort);
63
+ }
142
+ }
64
143
+
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
144
+ address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
145
+}
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
146
+
68
147
static void allwinner_sdhost_reset(DeviceState *dev)
69
/* common peripherals from bcm2835 */
148
{
70
149
AwSdHostState *s = AW_SDHOST(dev);
71
- obj = OBJECT(dev);
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
151
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
152
dc->reset = allwinner_sdhost_reset;
74
- s->cpu_type);
153
dc->vmsd = &vmstate_allwinner_sdhost;
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
154
+ dc->realize = allwinner_sdhost_realize;
76
- &error_abort);
155
+ device_class_set_props(dc, allwinner_sdhost_properties);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
156
}
84
157
85
static Property bcm2836_props[] = {
158
static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
159
--
104
2.16.2
160
2.20.1
105
161
106
162
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
3
Allow the device to execute the DMA transfers in a different
4
AddressSpace.
5
6
The H3 SoC keeps using the system_memory address space,
7
but via the proper dma_memory_access() API.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Message-id: 20200814122907.27732-1-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/net/allwinner-sun8i-emac.h | 6 ++++
17
hw/arm/allwinner-h3.c | 2 ++
18
hw/net/allwinner-sun8i-emac.c | 46 +++++++++++++++++----------
19
3 files changed, 38 insertions(+), 16 deletions(-)
20
21
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/net/allwinner-sun8i-emac.h
24
+++ b/include/hw/net/allwinner-sun8i-emac.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSun8iEmacState {
26
/** Interrupt output signal to notify CPU */
27
qemu_irq irq;
28
29
+ /** Memory region where DMA transfers are done */
30
+ MemoryRegion *dma_mr;
31
+
32
+ /** Address space used internally for DMA transfers */
33
+ AddressSpace dma_as;
34
+
35
/** Generic Network Interface Controller (NIC) for networking API */
36
NICState *nic;
37
38
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/allwinner-h3.c
41
+++ b/hw/arm/allwinner-h3.c
42
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
43
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
44
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
45
}
46
+ object_property_set_link(OBJECT(&s->emac), "dma-memory",
47
+ OBJECT(get_system_memory()), &error_fatal);
48
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
51
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/net/allwinner-sun8i-emac.c
54
+++ b/hw/net/allwinner-sun8i-emac.c
55
@@ -XXX,XX +XXX,XX @@
56
57
#include "qemu/osdep.h"
58
#include "qemu/units.h"
59
+#include "qapi/error.h"
60
#include "hw/sysbus.h"
61
#include "migration/vmstate.h"
62
#include "net/net.h"
63
@@ -XXX,XX +XXX,XX @@
64
#include "net/checksum.h"
65
#include "qemu/module.h"
66
#include "exec/cpu-common.h"
67
+#include "sysemu/dma.h"
68
#include "hw/net/allwinner-sun8i-emac.h"
69
70
/* EMAC register offsets */
71
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
72
qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
73
}
74
75
-static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
76
+static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
77
+ FrameDescriptor *desc,
78
size_t min_size)
79
{
80
uint32_t paddr = desc->next;
81
82
- cpu_physical_memory_read(paddr, desc, sizeof(*desc));
83
+ dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
84
85
if ((desc->status & DESC_STATUS_CTL) &&
86
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
87
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
88
}
89
}
90
91
-static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
92
+static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
93
+ FrameDescriptor *desc,
94
uint32_t start_addr,
95
size_t min_size)
96
{
97
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
98
99
/* Note that the list is a cycle. Last entry points back to the head. */
100
while (desc_addr != 0) {
101
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
102
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
103
104
if ((desc->status & DESC_STATUS_CTL) &&
105
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
106
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
107
FrameDescriptor *desc,
108
size_t min_size)
109
{
110
- return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
111
+ return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
112
}
113
114
static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
115
FrameDescriptor *desc,
116
size_t min_size)
117
{
118
- return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
119
+ return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
120
}
121
122
-static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
123
+static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
124
+ FrameDescriptor *desc,
125
uint32_t phys_addr)
126
{
127
- cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
128
+ dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
129
}
130
131
static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
132
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
133
<< RX_DESC_STATUS_FRM_LEN_SHIFT;
134
}
135
136
- cpu_physical_memory_write(desc.addr, buf, desc_bytes);
137
- allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
138
+ dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
139
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
140
trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
141
desc_bytes);
142
143
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
144
bytes_left -= desc_bytes;
145
146
/* Move to the next descriptor */
147
- s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
148
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
149
if (!s->rx_desc_curr) {
150
/* Not enough buffer space available */
151
s->int_sta |= INT_STA_RX_BUF_UA;
152
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
153
desc.status |= TX_DESC_STATUS_LENGTH_ERR;
154
break;
155
}
156
- cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
157
+ dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
158
packet_bytes += bytes;
159
desc.status &= ~DESC_STATUS_CTL;
160
- allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
161
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
162
163
/* After the last descriptor, send the packet */
164
if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
165
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
166
packet_bytes = 0;
167
transmitted++;
168
}
169
- s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
170
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
171
}
172
173
/* Raise transmit completed interrupt */
174
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
175
break;
176
case REG_TX_CUR_BUF: /* Transmit Current Buffer */
177
if (s->tx_desc_curr != 0) {
178
- cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
179
+ dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
180
value = desc.addr;
181
} else {
182
value = 0;
183
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
184
break;
185
case REG_RX_CUR_BUF: /* Receive Current Buffer */
186
if (s->rx_desc_curr != 0) {
187
- cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
188
+ dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
189
value = desc.addr;
190
} else {
191
value = 0;
192
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
193
{
194
AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
195
196
+ if (!s->dma_mr) {
197
+ error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set");
198
+ return;
199
+ }
200
+
201
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
202
+
203
qemu_macaddr_default_if_unset(&s->conf.macaddr);
204
s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
205
object_get_typename(OBJECT(dev)), dev->id, s);
206
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
207
static Property allwinner_sun8i_emac_properties[] = {
208
DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
209
DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
210
+ DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr,
211
+ TYPE_MEMORY_REGION, MemoryRegion *),
212
DEFINE_PROP_END_OF_LIST(),
213
};
214
215
--
216
2.20.1
217
218
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
As we want to call qdev_connect_clock_in() before the device
4
is realized, we need to uninline cadence_uart_create() first.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200803105647.22223-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/char/cadence_uart.h | 17 -----------------
12
hw/arm/xilinx_zynq.c | 14 ++++++++++++--
13
2 files changed, 12 insertions(+), 19 deletions(-)
14
15
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/char/cadence_uart.h
18
+++ b/include/hw/char/cadence_uart.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct {
20
Clock *refclk;
21
} CadenceUARTState;
22
23
-static inline DeviceState *cadence_uart_create(hwaddr addr,
24
- qemu_irq irq,
25
- Chardev *chr)
26
-{
27
- DeviceState *dev;
28
- SysBusDevice *s;
29
-
30
- dev = qdev_new(TYPE_CADENCE_UART);
31
- s = SYS_BUS_DEVICE(dev);
32
- qdev_prop_set_chr(dev, "chardev", chr);
33
- sysbus_realize_and_unref(s, &error_fatal);
34
- sysbus_mmio_map(s, 0, addr);
35
- sysbus_connect_irq(s, 0, irq);
36
-
37
- return dev;
38
-}
39
-
40
#endif
41
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/xilinx_zynq.c
44
+++ b/hw/arm/xilinx_zynq.c
45
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
46
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
47
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
48
49
- dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
50
+ dev = qdev_new(TYPE_CADENCE_UART);
51
+ busdev = SYS_BUS_DEVICE(dev);
52
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
53
+ sysbus_realize_and_unref(busdev, &error_fatal);
54
+ sysbus_mmio_map(busdev, 0, 0xE0000000);
55
+ sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
56
qdev_connect_clock_in(dev, "refclk",
57
qdev_get_clock_out(slcr, "uart0_ref_clk"));
58
- dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
59
+ dev = qdev_new(TYPE_CADENCE_UART);
60
+ busdev = SYS_BUS_DEVICE(dev);
61
+ qdev_prop_set_chr(dev, "chardev", serial_hd(1));
62
+ sysbus_realize_and_unref(busdev, &error_fatal);
63
+ sysbus_mmio_map(busdev, 0, 0xE0001000);
64
+ sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
65
qdev_connect_clock_in(dev, "refclk",
66
qdev_get_clock_out(slcr, "uart1_ref_clk"));
67
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Clock canonical name is set in device_set_realized (see the block
4
added to hw/core/qdev.c in commit 0e6934f264).
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
8
9
Fix by calling qdev_connect_clock_in() before realizing.
10
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200803105647.22223-3-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/xilinx_zynq.c | 18 +++++++++---------
17
1 file changed, 9 insertions(+), 9 deletions(-)
18
19
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/xilinx_zynq.c
22
+++ b/hw/arm/xilinx_zynq.c
23
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
24
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
25
0);
26
27
- /* Create slcr, keep a pointer to connect clocks */
28
- slcr = qdev_new("xilinx,zynq_slcr");
29
- sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
30
- sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
31
-
32
/* Create the main clock source, and feed slcr with it */
33
zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
34
object_property_add_child(OBJECT(zynq_machine), "ps_clk",
35
OBJECT(zynq_machine->ps_clk));
36
object_unref(OBJECT(zynq_machine->ps_clk));
37
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
38
+
39
+ /* Create slcr, keep a pointer to connect clocks */
40
+ slcr = qdev_new("xilinx,zynq_slcr");
41
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
42
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
43
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
44
45
dev = qdev_new(TYPE_A9MPCORE_PRIV);
46
qdev_prop_set_uint32(dev, "num-cpu", 1);
47
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
48
dev = qdev_new(TYPE_CADENCE_UART);
49
busdev = SYS_BUS_DEVICE(dev);
50
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
51
+ qdev_connect_clock_in(dev, "refclk",
52
+ qdev_get_clock_out(slcr, "uart0_ref_clk"));
53
sysbus_realize_and_unref(busdev, &error_fatal);
54
sysbus_mmio_map(busdev, 0, 0xE0000000);
55
sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
56
- qdev_connect_clock_in(dev, "refclk",
57
- qdev_get_clock_out(slcr, "uart0_ref_clk"));
58
dev = qdev_new(TYPE_CADENCE_UART);
59
busdev = SYS_BUS_DEVICE(dev);
60
qdev_prop_set_chr(dev, "chardev", serial_hd(1));
61
+ qdev_connect_clock_in(dev, "refclk",
62
+ qdev_get_clock_out(slcr, "uart1_ref_clk"));
63
sysbus_realize_and_unref(busdev, &error_fatal);
64
sysbus_mmio_map(busdev, 0, 0xE0001000);
65
sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
66
- qdev_connect_clock_in(dev, "refclk",
67
- qdev_get_clock_out(slcr, "uart1_ref_clk"));
68
69
sysbus_create_varargs("cadence_ttc", 0xF8001000,
70
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
71
--
72
2.20.1
73
74
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
We want to assert the device is not realized. To avoid overloading
4
this header including "hw/qdev-core.h", uninline the function first.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200803105647.22223-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/qdev-clock.h | 6 +-----
12
hw/core/qdev-clock.c | 5 +++++
13
2 files changed, 6 insertions(+), 5 deletions(-)
14
15
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/qdev-clock.h
18
+++ b/include/hw/qdev-clock.h
19
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
20
* Set the source clock of input clock @name of device @dev to @source.
21
* @source period update will be propagated to @name clock.
22
*/
23
-static inline void qdev_connect_clock_in(DeviceState *dev, const char *name,
24
- Clock *source)
25
-{
26
- clock_set_source(qdev_get_clock_in(dev, name), source);
27
-}
28
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
29
30
/**
31
* qdev_alias_clock:
32
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/core/qdev-clock.c
35
+++ b/hw/core/qdev-clock.c
36
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
37
38
return ncl->clock;
39
}
40
+
41
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
42
+{
43
+ clock_set_source(qdev_get_clock_in(dev, name), source);
44
+}
45
--
46
2.20.1
47
48
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Clock canonical name is set in device_set_realized (see the block
4
added to hw/core/qdev.c in commit 0e6934f264).
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
8
9
Add a comment to document qdev_connect_clock_in() must be called
10
before the device is realized, and assert this condition.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-id: 20200803105647.22223-5-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
include/hw/qdev-clock.h | 2 ++
18
hw/core/qdev-clock.c | 1 +
19
2 files changed, 3 insertions(+)
20
21
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/qdev-clock.h
24
+++ b/include/hw/qdev-clock.h
25
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
26
*
27
* Set the source clock of input clock @name of device @dev to @source.
28
* @source period update will be propagated to @name clock.
29
+ *
30
+ * Must be called before @dev is realized.
31
*/
32
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
33
34
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/core/qdev-clock.c
37
+++ b/hw/core/qdev-clock.c
38
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
39
40
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
41
{
42
+ assert(!dev->realized);
43
clock_set_source(qdev_get_clock_in(dev, name), source);
44
}
45
--
46
2.20.1
47
48
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
To better align the read/write accesses, display the value after
4
the offset (read accesses only display the offset).
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200812190206.31595-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/misc/unimp.c | 8 ++++----
12
1 file changed, 4 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/unimp.c
17
+++ b/hw/misc/unimp.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
19
{
20
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
21
22
- qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
23
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
24
"(size %d, offset 0x%" HWADDR_PRIx ")\n",
25
s->name, size, offset);
26
return 0;
27
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
28
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
29
30
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
31
- "(size %d, value 0x%" PRIx64
32
- ", offset 0x%" HWADDR_PRIx ")\n",
33
- s->name, size, value, offset);
34
+ "(size %d, offset 0x%" HWADDR_PRIx
35
+ ", value 0x%" PRIx64 ")\n",
36
+ s->name, size, offset, value);
37
}
38
39
static const MemoryRegionOps unimp_ops = {
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
To quickly notice the access size, display the value with the
4
width of the access (i.e. 16-bit access is displayed 0x0000,
5
while 8-bit access 0x00).
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200812190206.31595-3-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/unimp.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/unimp.c
18
+++ b/hw/misc/unimp.c
19
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
20
21
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
22
"(size %d, offset 0x%" HWADDR_PRIx
23
- ", value 0x%" PRIx64 ")\n",
24
- s->name, size, offset, value);
25
+ ", value 0x%0*" PRIx64 ")\n",
26
+ s->name, size, offset, size << 1, value);
27
}
28
29
static const MemoryRegionOps unimp_ops = {
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
To have a better idea of how big is the region where the offset
4
belongs, display the value with the width of the region size
5
(i.e. a region of 0x1000 bytes uses 0x000 format).
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200812190206.31595-4-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/misc/unimp.h | 1 +
13
hw/misc/unimp.c | 10 ++++++----
14
2 files changed, 7 insertions(+), 4 deletions(-)
15
16
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/misc/unimp.h
19
+++ b/include/hw/misc/unimp.h
20
@@ -XXX,XX +XXX,XX @@
21
typedef struct {
22
SysBusDevice parent_obj;
23
MemoryRegion iomem;
24
+ unsigned offset_fmt_width;
25
char *name;
26
uint64_t size;
27
} UnimplementedDeviceState;
28
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/unimp.c
31
+++ b/hw/misc/unimp.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
33
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
34
35
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
36
- "(size %d, offset 0x%" HWADDR_PRIx ")\n",
37
- s->name, size, offset);
38
+ "(size %d, offset 0x%0*" HWADDR_PRIx ")\n",
39
+ s->name, size, s->offset_fmt_width, offset);
40
return 0;
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
44
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
45
46
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
47
- "(size %d, offset 0x%" HWADDR_PRIx
48
+ "(size %d, offset 0x%0*" HWADDR_PRIx
49
", value 0x%0*" PRIx64 ")\n",
50
- s->name, size, offset, size << 1, value);
51
+ s->name, size, s->offset_fmt_width, offset, size << 1, value);
52
}
53
54
static const MemoryRegionOps unimp_ops = {
55
@@ -XXX,XX +XXX,XX @@ static void unimp_realize(DeviceState *dev, Error **errp)
56
return;
57
}
58
59
+ s->offset_fmt_width = DIV_ROUND_UP(64 - clz64(s->size - 1), 4);
60
+
61
memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
62
s->name, s->size);
63
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Eduardo Habkost <ehabkost@redhat.com>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
4
ARMSSEClass::parent_class is declared as DeviceClass.
5
controller which is supported in QEMU using the imx_fec.c module
6
(actually called imx.enet for this model.)
7
5
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
6
It never caused any problems by pure luck:
9
imx.enet device like this:
10
7
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
8
We were not setting class_size for TYPE_ARM_SSE, so class_size of
12
#define FSL_IMX6_ENET_MAC_IRQ 119
9
TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)).
10
This made the system allocate enough memory for TYPE_ARM_SSE
11
devices even though ARMSSEClass was too small for a sysbus
12
device.
13
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
14
Additionally, the ARMSSEClass::info field ended up at the same
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
15
offset as SysBusDeviceClass::explicit_ofw_unit_address. This
16
interrupts are as follows.
16
would make sysbus_get_fw_dev_path() crash for the device.
17
Luckily, sysbus_get_fw_dev_path() never gets called for
18
TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used
19
by the boot device code, and TYPE_ARM_SSE devices don't appear at
20
the fw_boot_order list.
17
21
18
150 ENET MAC 0 IRQ
22
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
19
151 ENET MAC 0 1588 Timer interrupt
23
Message-id: 20200826181006.4097163-1-ehabkost@redhat.com
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
26
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
27
include/hw/arm/armsse.h | 2 +-
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
28
hw/arm/armsse.c | 1 +
46
2 files changed, 29 insertions(+), 3 deletions(-)
29
2 files changed, 2 insertions(+), 1 deletion(-)
47
30
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
31
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
49
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
33
--- a/include/hw/arm/armsse.h
51
+++ b/include/hw/arm/fsl-imx6.h
34
+++ b/include/hw/arm/armsse.h
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
35
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
36
typedef struct ARMSSEInfo ARMSSEInfo;
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
37
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
38
typedef struct ARMSSEClass {
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
39
- DeviceClass parent_class;
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
40
+ SysBusDeviceClass parent_class;
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
41
const ARMSSEInfo *info;
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
42
} ARMSSEClass;
60
#define FSL_IMX6_PCIE1_IRQ 120
43
61
#define FSL_IMX6_PCIE2_IRQ 121
44
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
46
--- a/hw/arm/armsse.c
66
+++ b/hw/net/imx_fec.c
47
+++ b/hw/arm/armsse.c
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo armsse_info = {
68
49
.name = TYPE_ARMSSE,
69
static void imx_eth_update(IMXFECState *s)
50
.parent = TYPE_SYS_BUS_DEVICE,
70
{
51
.instance_size = sizeof(ARMSSE),
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
52
+ .class_size = sizeof(ARMSSEClass),
72
+ /*
53
.instance_init = armsse_init,
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
54
.abstract = true,
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
55
.interfaces = (InterfaceInfo[]) {
75
+ * and older) since Linux associated both interrupt lines with Ethernet
76
+ * MAC interrupts. Specifically,
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
79
+ * with swapped interrupt assignments.
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
82
+ * work, though that is accidental.
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
88
+ * Linux instead received MAC interrupts on the timer interrupt.
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
90
+ * albeit accidentally, but qemu versions with the correct interrupt
91
+ * assignment fail.
92
+ *
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
94
+ * interrrupts on both interrupt lines. This should be changed if and when
95
+ * qemu supports IOMUX.
96
+ */
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
99
qemu_set_irq(s->irq[1], 1);
100
} else {
101
qemu_set_irq(s->irq[1], 0);
102
--
56
--
103
2.16.2
57
2.20.1
104
58
105
59
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Add left-shift to match the existing right-shift.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/qemu/int128.h | 16 ++++++++++++++++
11
1 file changed, 16 insertions(+)
12
13
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/qemu/int128.h
16
+++ b/include/qemu/int128.h
17
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
18
return a >> n;
19
}
20
21
+static inline Int128 int128_lshift(Int128 a, int n)
22
+{
23
+ return a << n;
24
+}
25
+
26
static inline Int128 int128_add(Int128 a, Int128 b)
27
{
28
return a + b;
29
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
30
}
31
}
32
33
+static inline Int128 int128_lshift(Int128 a, int n)
34
+{
35
+ uint64_t l = a.lo << (n & 63);
36
+ if (n >= 64) {
37
+ return int128_make128(0, l);
38
+ } else if (n > 0) {
39
+ return int128_make128(l, (a.hi << n) | (a.lo >> (64 - n)));
40
+ }
41
+ return a;
42
+}
43
+
44
static inline Int128 int128_add(Int128 a, Int128 b)
45
{
46
uint64_t lo = a.lo + b.lo;
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Model the new function on gen_gvec_fn2 in translate-a64.c, but
4
indicating which kind of register and in which order. Since there
5
is only one user of do_vector2_z, fold it into do_mov_z.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 19 ++++++++++---------
13
1 file changed, 10 insertions(+), 9 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
20
}
21
22
/* Invoke a vector expander on two Zregs. */
23
-static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
24
- int esz, int rd, int rn)
25
+
26
+static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
27
+ int esz, int rd, int rn)
28
{
29
- if (sve_access_check(s)) {
30
- unsigned vsz = vec_full_reg_size(s);
31
- gvec_fn(esz, vec_full_reg_offset(s, rd),
32
- vec_full_reg_offset(s, rn), vsz, vsz);
33
- }
34
- return true;
35
+ unsigned vsz = vec_full_reg_size(s);
36
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
37
+ vec_full_reg_offset(s, rn), vsz, vsz);
38
}
39
40
/* Invoke a vector expander on three Zregs. */
41
@@ -XXX,XX +XXX,XX @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
42
/* Invoke a vector move on two Zregs. */
43
static bool do_mov_z(DisasContext *s, int rd, int rn)
44
{
45
- return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
46
+ if (sve_access_check(s)) {
47
+ gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
48
+ }
49
+ return true;
50
}
51
52
/* Initialize a Zreg with replications of a 64-bit immediate. */
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
From: Richard Henderson <richard.henderson@linaro.org>
2
some differences. Notably, the MPIDR affinity aff1 values it
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
2
6
Rather than trying to have one device with properties that
3
Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
7
configure it differently for the two cases, create two
4
indicating which kind of register and in which order.
8
separate QOM devices for the two SoCs. We use the same approach
9
as hw/arm/aspeed_soc.c and share code and have a data table
10
that might differ per-SoC. For the moment the two types don't
11
actually have different behaviour.
12
5
6
Model do_zzz_fn on the other do_foo functions that take an
7
argument set and verify sve enabled.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200815013145.539409-4-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
---
13
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
14
target/arm/translate-sve.c | 43 +++++++++++++++++++++-----------------
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
15
1 file changed, 24 insertions(+), 19 deletions(-)
19
hw/arm/raspi.c | 3 ++-
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
16
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
23
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
19
--- a/target/arm/translate-sve.c
25
+++ b/include/hw/arm/bcm2836.h
20
+++ b/target/arm/translate-sve.c
26
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
27
22
}
28
#define BCM283X_NCPUS 4
23
29
24
/* Invoke a vector expander on three Zregs. */
30
+/* These type names are for specific SoCs; other than instantiating
25
-static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
31
+ * them, code using these devices should always handle them via the
26
- int esz, int rd, int rn, int rm)
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
27
+static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
33
+ */
28
+ int esz, int rd, int rn, int rm)
34
+#define TYPE_BCM2836 "bcm2836"
29
{
35
+#define TYPE_BCM2837 "bcm2837"
30
- if (sve_access_check(s)) {
31
- unsigned vsz = vec_full_reg_size(s);
32
- gvec_fn(esz, vec_full_reg_offset(s, rd),
33
- vec_full_reg_offset(s, rn),
34
- vec_full_reg_offset(s, rm), vsz, vsz);
35
- }
36
- return true;
37
+ unsigned vsz = vec_full_reg_size(s);
38
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
39
+ vec_full_reg_offset(s, rn),
40
+ vec_full_reg_offset(s, rm), vsz, vsz);
41
}
42
43
/* Invoke a vector move on two Zregs. */
44
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
45
*** SVE Logical - Unpredicated Group
46
*/
47
48
+static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
49
+{
50
+ if (sve_access_check(s)) {
51
+ gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
52
+ }
53
+ return true;
54
+}
36
+
55
+
37
typedef struct BCM283XState {
56
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
38
/*< private >*/
39
DeviceState parent_obj;
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
41
BCM2835PeripheralState peripherals;
42
} BCM283XState;
43
44
+typedef struct BCM283XInfo BCM283XInfo;
45
+
46
+typedef struct BCM283XClass {
47
+ DeviceClass parent_class;
48
+ const BCM283XInfo *info;
49
+} BCM283XClass;
50
+
51
+#define BCM283X_CLASS(klass) \
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
53
+#define BCM283X_GET_CLASS(obj) \
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
55
+
56
#endif /* BCM2836_H */
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/bcm2836.c
60
+++ b/hw/arm/bcm2836.c
61
@@ -XXX,XX +XXX,XX @@
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
63
#define BCM2836_CONTROL_BASE 0x40000000
64
65
+struct BCM283XInfo {
66
+ const char *name;
67
+};
68
+
69
+static const BCM283XInfo bcm283x_socs[] = {
70
+ {
71
+ .name = TYPE_BCM2836,
72
+ },
73
+ {
74
+ .name = TYPE_BCM2837,
75
+ },
76
+};
77
+
78
static void bcm2836_init(Object *obj)
79
{
57
{
80
BCM283XState *s = BCM283X(obj);
58
- return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
59
+ return do_zzz_fn(s, a, tcg_gen_gvec_and);
82
DEFINE_PROP_END_OF_LIST()
60
}
83
};
61
84
62
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
87
{
63
{
88
DeviceClass *dc = DEVICE_CLASS(oc);
64
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
65
+ return do_zzz_fn(s, a, tcg_gen_gvec_or);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
66
}
96
67
97
-static const TypeInfo bcm2836_type_info = {
68
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
98
+static const TypeInfo bcm283x_type_info = {
99
.name = TYPE_BCM283X,
100
.parent = TYPE_DEVICE,
101
.instance_size = sizeof(BCM283XState),
102
.instance_init = bcm2836_init,
103
- .class_init = bcm2836_class_init,
104
+ .class_size = sizeof(BCM283XClass),
105
+ .abstract = true,
106
};
107
108
static void bcm2836_register_types(void)
109
{
69
{
110
- type_register_static(&bcm2836_type_info);
70
- return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
111
+ int i;
71
+ return do_zzz_fn(s, a, tcg_gen_gvec_xor);
112
+
113
+ type_register_static(&bcm283x_type_info);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
115
+ TypeInfo ti = {
116
+ .name = bcm283x_socs[i].name,
117
+ .parent = TYPE_BCM283X,
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
123
}
72
}
124
73
125
type_init(bcm2836_register_types)
74
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
75
{
127
index XXXXXXX..XXXXXXX 100644
76
- return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
128
--- a/hw/arm/raspi.c
77
+ return do_zzz_fn(s, a, tcg_gen_gvec_andc);
129
+++ b/hw/arm/raspi.c
78
}
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
79
131
BusState *bus;
80
/*
132
DeviceState *carddev;
81
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
133
82
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
83
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
135
+ object_initialize(&s->soc, sizeof(s->soc),
84
{
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
85
- return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
86
+ return do_zzz_fn(s, a, tcg_gen_gvec_add);
138
&error_abort);
87
}
139
88
89
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
90
{
91
- return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
92
+ return do_zzz_fn(s, a, tcg_gen_gvec_sub);
93
}
94
95
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
96
{
97
- return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
98
+ return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
99
}
100
101
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
104
+ return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
105
}
106
107
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
108
{
109
- return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
110
+ return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
111
}
112
113
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
114
{
115
- return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
116
+ return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
117
}
118
119
/*
140
--
120
--
141
2.16.2
121
2.20.1
142
122
143
123
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We want to ensure that access is checked by the time we ask
4
for a specific fp/vector register. We want to ensure that
5
we do not emit two lots of code to raise an exception.
6
7
But sometimes it's difficult to cleanly organize the code
8
such that we never pass through sve_check_access exactly once.
9
Allow multiple calls so long as the result is true, that is,
10
no exception to be raised.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200815013145.539409-5-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/translate.h | 1 +
18
target/arm/translate-a64.c | 27 ++++++++++++++++-----------
19
2 files changed, 17 insertions(+), 11 deletions(-)
20
21
diff --git a/target/arm/translate.h b/target/arm/translate.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/translate.h
24
+++ b/target/arm/translate.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
26
* that it is set at the point where we actually touch the FP regs.
27
*/
28
bool fp_access_checked;
29
+ bool sve_access_checked;
30
/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
31
* single-step support).
32
*/
33
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-a64.c
36
+++ b/target/arm/translate-a64.c
37
@@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
38
* unallocated-encoding checks (otherwise the syndrome information
39
* for the resulting exception will be incorrect).
40
*/
41
-static inline bool fp_access_check(DisasContext *s)
42
+static bool fp_access_check(DisasContext *s)
43
{
44
- assert(!s->fp_access_checked);
45
- s->fp_access_checked = true;
46
+ if (s->fp_excp_el) {
47
+ assert(!s->fp_access_checked);
48
+ s->fp_access_checked = true;
49
50
- if (!s->fp_excp_el) {
51
- return true;
52
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
53
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
54
+ return false;
55
}
56
-
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
58
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
59
- return false;
60
+ s->fp_access_checked = true;
61
+ return true;
62
}
63
64
/* Check that SVE access is enabled. If it is, return true.
65
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
66
bool sve_access_check(DisasContext *s)
67
{
68
if (s->sve_excp_el) {
69
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
70
- s->sve_excp_el);
71
+ assert(!s->sve_access_checked);
72
+ s->sve_access_checked = true;
73
+
74
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
75
+ syn_sve_access_trap(), s->sve_excp_el);
76
return false;
77
}
78
+ s->sve_access_checked = true;
79
return fp_access_check(s);
80
}
81
82
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
83
s->base.pc_next += 4;
84
85
s->fp_access_checked = false;
86
+ s->sve_access_checked = false;
87
88
if (dc_isar_feature(aa64_bti, s)) {
89
if (s->base.num_insns == 1) {
90
--
91
2.20.1
92
93
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This is the only user of the function.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 19 ++++++-------------
11
1 file changed, 6 insertions(+), 13 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
18
tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
19
}
20
21
-/* Invoke a vector expander on two Pregs. */
22
-static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn,
23
- int esz, int rd, int rn)
24
-{
25
- if (sve_access_check(s)) {
26
- unsigned psz = pred_gvec_reg_size(s);
27
- gvec_fn(esz, pred_full_reg_offset(s, rd),
28
- pred_full_reg_offset(s, rn), psz, psz);
29
- }
30
- return true;
31
-}
32
-
33
/* Invoke a vector expander on three Pregs. */
34
static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
35
int esz, int rd, int rn, int rm)
36
@@ -XXX,XX +XXX,XX @@ static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
37
/* Invoke a vector move on two Pregs. */
38
static bool do_mov_p(DisasContext *s, int rd, int rn)
39
{
40
- return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn);
41
+ if (sve_access_check(s)) {
42
+ unsigned psz = pred_gvec_reg_size(s);
43
+ tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd),
44
+ pred_full_reg_offset(s, rn), psz, psz);
45
+ }
46
+ return true;
47
}
48
49
/* Set the cpu flags as per a return from an SVE helper. */
50
--
51
2.20.1
52
53
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Move the check for !S into do_pppp_flags, which allows to merge in
4
do_vecop4_p. Split out gen_gvec_fn_ppp without sve_access_check,
5
to mirror gen_gvec_fn_zzz.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 111 ++++++++++++++-----------------------
13
1 file changed, 43 insertions(+), 68 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
20
}
21
22
/* Invoke a vector expander on three Pregs. */
23
-static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
24
- int esz, int rd, int rn, int rm)
25
+static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
26
+ int rd, int rn, int rm)
27
{
28
- if (sve_access_check(s)) {
29
- unsigned psz = pred_gvec_reg_size(s);
30
- gvec_fn(esz, pred_full_reg_offset(s, rd),
31
- pred_full_reg_offset(s, rn),
32
- pred_full_reg_offset(s, rm), psz, psz);
33
- }
34
- return true;
35
-}
36
-
37
-/* Invoke a vector operation on four Pregs. */
38
-static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
39
- int rd, int rn, int rm, int rg)
40
-{
41
- if (sve_access_check(s)) {
42
- unsigned psz = pred_gvec_reg_size(s);
43
- tcg_gen_gvec_4(pred_full_reg_offset(s, rd),
44
- pred_full_reg_offset(s, rn),
45
- pred_full_reg_offset(s, rm),
46
- pred_full_reg_offset(s, rg),
47
- psz, psz, gvec_op);
48
- }
49
- return true;
50
+ unsigned psz = pred_gvec_reg_size(s);
51
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
52
+ pred_full_reg_offset(s, rn),
53
+ pred_full_reg_offset(s, rm), psz, psz);
54
}
55
56
/* Invoke a vector move on two Pregs. */
57
@@ -XXX,XX +XXX,XX @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a,
58
int mofs = pred_full_reg_offset(s, a->rm);
59
int gofs = pred_full_reg_offset(s, a->pg);
60
61
+ if (!a->s) {
62
+ tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op);
63
+ return true;
64
+ }
65
+
66
if (psz == 8) {
67
/* Do the operation and the flags generation in temps. */
68
TCGv_i64 pd = tcg_temp_new_i64();
69
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
70
.fno = gen_helper_sve_and_pppp,
71
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
72
};
73
- if (a->s) {
74
- return do_pppp_flags(s, a, &op);
75
- } else if (a->rn == a->rm) {
76
- if (a->pg == a->rn) {
77
- return do_mov_p(s, a->rd, a->rn);
78
- } else {
79
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->pg);
80
+
81
+ if (!a->s) {
82
+ if (!sve_access_check(s)) {
83
+ return true;
84
+ }
85
+ if (a->rn == a->rm) {
86
+ if (a->pg == a->rn) {
87
+ do_mov_p(s, a->rd, a->rn);
88
+ } else {
89
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
90
+ }
91
+ return true;
92
+ } else if (a->pg == a->rn || a->pg == a->rm) {
93
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
94
+ return true;
95
}
96
- } else if (a->pg == a->rn || a->pg == a->rm) {
97
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
98
- } else {
99
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
100
}
101
+ return do_pppp_flags(s, a, &op);
102
}
103
104
static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
105
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
106
.fno = gen_helper_sve_bic_pppp,
107
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
108
};
109
- if (a->s) {
110
- return do_pppp_flags(s, a, &op);
111
- } else if (a->pg == a->rn) {
112
- return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
113
- } else {
114
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
115
+
116
+ if (!a->s && a->pg == a->rn) {
117
+ if (sve_access_check(s)) {
118
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
119
+ }
120
+ return true;
121
}
122
+ return do_pppp_flags(s, a, &op);
123
}
124
125
static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
126
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
127
.fno = gen_helper_sve_eor_pppp,
128
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
129
};
130
- if (a->s) {
131
- return do_pppp_flags(s, a, &op);
132
- } else {
133
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
134
- }
135
+ return do_pppp_flags(s, a, &op);
136
}
137
138
static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
139
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
140
.fno = gen_helper_sve_sel_pppp,
141
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
142
};
143
+
144
if (a->s) {
145
return false;
146
- } else {
147
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
148
}
149
+ return do_pppp_flags(s, a, &op);
150
}
151
152
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
153
@@ -XXX,XX +XXX,XX @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a)
154
.fno = gen_helper_sve_orr_pppp,
155
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
156
};
157
- if (a->s) {
158
- return do_pppp_flags(s, a, &op);
159
- } else if (a->pg == a->rn && a->rn == a->rm) {
160
+
161
+ if (!a->s && a->pg == a->rn && a->rn == a->rm) {
162
return do_mov_p(s, a->rd, a->rn);
163
- } else {
164
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
165
}
166
+ return do_pppp_flags(s, a, &op);
167
}
168
169
static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
170
@@ -XXX,XX +XXX,XX @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a)
171
.fno = gen_helper_sve_orn_pppp,
172
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
173
};
174
- if (a->s) {
175
- return do_pppp_flags(s, a, &op);
176
- } else {
177
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
178
- }
179
+ return do_pppp_flags(s, a, &op);
180
}
181
182
static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
183
@@ -XXX,XX +XXX,XX @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a)
184
.fno = gen_helper_sve_nor_pppp,
185
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
186
};
187
- if (a->s) {
188
- return do_pppp_flags(s, a, &op);
189
- } else {
190
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
191
- }
192
+ return do_pppp_flags(s, a, &op);
193
}
194
195
static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
196
@@ -XXX,XX +XXX,XX @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a)
197
.fno = gen_helper_sve_nand_pppp,
198
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
199
};
200
- if (a->s) {
201
- return do_pppp_flags(s, a, &op);
202
- } else {
203
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
204
- }
205
+ return do_pppp_flags(s, a, &op);
206
}
207
208
/*
209
--
210
2.20.1
211
212
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The gvec operation was added after the initial implementation
4
of the SEL instruction and was missed in the conversion.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 31 ++++++++-----------------------
12
1 file changed, 8 insertions(+), 23 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
19
return do_pppp_flags(s, a, &op);
20
}
21
22
-static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
23
-{
24
- tcg_gen_and_i64(pn, pn, pg);
25
- tcg_gen_andc_i64(pm, pm, pg);
26
- tcg_gen_or_i64(pd, pn, pm);
27
-}
28
-
29
-static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn,
30
- TCGv_vec pm, TCGv_vec pg)
31
-{
32
- tcg_gen_and_vec(vece, pn, pn, pg);
33
- tcg_gen_andc_vec(vece, pm, pm, pg);
34
- tcg_gen_or_vec(vece, pd, pn, pm);
35
-}
36
-
37
static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
38
{
39
- static const GVecGen4 op = {
40
- .fni8 = gen_sel_pg_i64,
41
- .fniv = gen_sel_pg_vec,
42
- .fno = gen_helper_sve_sel_pppp,
43
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
44
- };
45
-
46
if (a->s) {
47
return false;
48
}
49
- return do_pppp_flags(s, a, &op);
50
+ if (sve_access_check(s)) {
51
+ unsigned psz = pred_gvec_reg_size(s);
52
+ tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd),
53
+ pred_full_reg_offset(s, a->pg),
54
+ pred_full_reg_offset(s, a->rn),
55
+ pred_full_reg_offset(s, a->rm), psz, psz);
56
+ }
57
+ return true;
58
}
59
60
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
61
--
62
2.20.1
63
64
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Model after gen_gvec_fn_zzz et al.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-9-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 35 ++++++++++++++++-------------------
11
1 file changed, 16 insertions(+), 19 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
18
return size_for_gvec(pred_full_reg_size(s));
19
}
20
21
-/* Invoke a vector expander on two Zregs. */
22
+/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
23
+static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
24
+ int rd, int rn, int rm, int pg, int data)
25
+{
26
+ unsigned vsz = vec_full_reg_size(s);
27
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
28
+ vec_full_reg_offset(s, rn),
29
+ vec_full_reg_offset(s, rm),
30
+ pred_full_reg_offset(s, pg),
31
+ vsz, vsz, data, fn);
32
+}
33
34
+/* Invoke a vector expander on two Zregs. */
35
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
36
int esz, int rd, int rn)
37
{
38
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
39
40
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
41
{
42
- unsigned vsz = vec_full_reg_size(s);
43
if (fn == NULL) {
44
return false;
45
}
46
if (sve_access_check(s)) {
47
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
48
- vec_full_reg_offset(s, a->rn),
49
- vec_full_reg_offset(s, a->rm),
50
- pred_full_reg_offset(s, a->pg),
51
- vsz, vsz, 0, fn);
52
+ gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
53
}
54
return true;
55
}
56
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
57
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
58
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
59
};
60
- unsigned vsz = vec_full_reg_size(s);
61
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
62
- vec_full_reg_offset(s, rn),
63
- vec_full_reg_offset(s, rm),
64
- pred_full_reg_offset(s, pg),
65
- vsz, vsz, 0, fns[esz]);
66
+ gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
67
}
68
69
#define DO_ZPZZ(NAME, name) \
70
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
71
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
72
{
73
if (sve_access_check(s)) {
74
- unsigned vsz = vec_full_reg_size(s);
75
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
76
- vec_full_reg_offset(s, a->rn),
77
- vec_full_reg_offset(s, a->rm),
78
- pred_full_reg_offset(s, a->pg),
79
- vsz, vsz, a->esz, gen_helper_sve_splice);
80
+ gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
81
+ a->rd, a->rn, a->rm, a->pg, 0);
82
}
83
return true;
84
}
85
--
86
2.20.1
87
88
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
The existing clr functions have only one vector argument, and so
4
can only clear in place. The existing movz functions have two
5
vector arguments, and so can clear while moving. Merge them, with
6
a flag that controls the sense of active vs inactive elements
7
being cleared.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200815013145.539409-10-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/helper-sve.h | 5 ---
15
target/arm/sve_helper.c | 70 ++++++++------------------------------
16
target/arm/translate-sve.c | 53 +++++++++++------------------
17
3 files changed, 34 insertions(+), 94 deletions(-)
18
19
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper-sve.h
22
+++ b/target/arm/helper-sve.h
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
24
DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
25
DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
26
27
-DEF_HELPER_FLAGS_3(sve_clr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
28
-DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
29
-DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
30
-DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
31
-
32
DEF_HELPER_FLAGS_4(sve_movz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
DEF_HELPER_FLAGS_4(sve_movz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(sve_movz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
35
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/sve_helper.c
38
+++ b/target/arm/sve_helper.c
39
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)
40
return flags;
41
}
42
43
-/* Store zero into every active element of Zd. We will use this for two
44
- * and three-operand predicated instructions for which logic dictates a
45
- * zero result. In particular, logical shift by element size, which is
46
- * otherwise undefined on the host.
47
- *
48
- * For element sizes smaller than uint64_t, we use tables to expand
49
- * the N bits of the controlling predicate to a byte mask, and clear
50
- * those bytes.
51
+/*
52
+ * Copy Zn into Zd, and store zero into inactive elements.
53
+ * If inv, store zeros into the active elements.
54
*/
55
-void HELPER(sve_clr_b)(void *vd, void *vg, uint32_t desc)
56
-{
57
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
58
- uint64_t *d = vd;
59
- uint8_t *pg = vg;
60
- for (i = 0; i < opr_sz; i += 1) {
61
- d[i] &= ~expand_pred_b(pg[H1(i)]);
62
- }
63
-}
64
-
65
-void HELPER(sve_clr_h)(void *vd, void *vg, uint32_t desc)
66
-{
67
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
68
- uint64_t *d = vd;
69
- uint8_t *pg = vg;
70
- for (i = 0; i < opr_sz; i += 1) {
71
- d[i] &= ~expand_pred_h(pg[H1(i)]);
72
- }
73
-}
74
-
75
-void HELPER(sve_clr_s)(void *vd, void *vg, uint32_t desc)
76
-{
77
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
78
- uint64_t *d = vd;
79
- uint8_t *pg = vg;
80
- for (i = 0; i < opr_sz; i += 1) {
81
- d[i] &= ~expand_pred_s(pg[H1(i)]);
82
- }
83
-}
84
-
85
-void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc)
86
-{
87
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
88
- uint64_t *d = vd;
89
- uint8_t *pg = vg;
90
- for (i = 0; i < opr_sz; i += 1) {
91
- if (pg[H1(i)] & 1) {
92
- d[i] = 0;
93
- }
94
- }
95
-}
96
-
97
-/* Copy Zn into Zd, and store zero into inactive elements. */
98
void HELPER(sve_movz_b)(void *vd, void *vn, void *vg, uint32_t desc)
99
{
100
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
101
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
102
uint64_t *d = vd, *n = vn;
103
uint8_t *pg = vg;
104
+
105
for (i = 0; i < opr_sz; i += 1) {
106
- d[i] = n[i] & expand_pred_b(pg[H1(i)]);
107
+ d[i] = n[i] & (expand_pred_b(pg[H1(i)]) ^ inv);
108
}
109
}
110
111
void HELPER(sve_movz_h)(void *vd, void *vn, void *vg, uint32_t desc)
112
{
113
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
114
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
115
uint64_t *d = vd, *n = vn;
116
uint8_t *pg = vg;
117
+
118
for (i = 0; i < opr_sz; i += 1) {
119
- d[i] = n[i] & expand_pred_h(pg[H1(i)]);
120
+ d[i] = n[i] & (expand_pred_h(pg[H1(i)]) ^ inv);
121
}
122
}
123
124
void HELPER(sve_movz_s)(void *vd, void *vn, void *vg, uint32_t desc)
125
{
126
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
127
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
128
uint64_t *d = vd, *n = vn;
129
uint8_t *pg = vg;
130
+
131
for (i = 0; i < opr_sz; i += 1) {
132
- d[i] = n[i] & expand_pred_s(pg[H1(i)]);
133
+ d[i] = n[i] & (expand_pred_s(pg[H1(i)]) ^ inv);
134
}
135
}
136
137
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc)
138
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
139
uint64_t *d = vd, *n = vn;
140
uint8_t *pg = vg;
141
+ uint8_t inv = simd_data(desc);
142
+
143
for (i = 0; i < opr_sz; i += 1) {
144
- d[i] = n[i] & -(uint64_t)(pg[H1(i)] & 1);
145
+ d[i] = n[i] & -(uint64_t)((pg[H1(i)] ^ inv) & 1);
146
}
147
}
148
149
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-sve.c
152
+++ b/target/arm/translate-sve.c
153
@@ -XXX,XX +XXX,XX @@ static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
154
*** SVE Shift by Immediate - Predicated Group
155
*/
156
157
-/* Store zero into every active element of Zd. We will use this for two
158
- * and three-operand predicated instructions for which logic dictates a
159
- * zero result.
160
+/*
161
+ * Copy Zn into Zd, storing zeros into inactive elements.
162
+ * If invert, store zeros into the active elements.
163
*/
164
-static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz)
165
-{
166
- static gen_helper_gvec_2 * const fns[4] = {
167
- gen_helper_sve_clr_b, gen_helper_sve_clr_h,
168
- gen_helper_sve_clr_s, gen_helper_sve_clr_d,
169
- };
170
- if (sve_access_check(s)) {
171
- unsigned vsz = vec_full_reg_size(s);
172
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
173
- pred_full_reg_offset(s, pg),
174
- vsz, vsz, 0, fns[esz]);
175
- }
176
- return true;
177
-}
178
-
179
-/* Copy Zn into Zd, storing zeros into inactive elements. */
180
-static void do_movz_zpz(DisasContext *s, int rd, int rn, int pg, int esz)
181
+static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
182
+ int esz, bool invert)
183
{
184
static gen_helper_gvec_3 * const fns[4] = {
185
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
186
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
187
};
188
- unsigned vsz = vec_full_reg_size(s);
189
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
190
- vec_full_reg_offset(s, rn),
191
- pred_full_reg_offset(s, pg),
192
- vsz, vsz, 0, fns[esz]);
193
+
194
+ if (sve_access_check(s)) {
195
+ unsigned vsz = vec_full_reg_size(s);
196
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
197
+ vec_full_reg_offset(s, rn),
198
+ pred_full_reg_offset(s, pg),
199
+ vsz, vsz, invert, fns[esz]);
200
+ }
201
+ return true;
202
}
203
204
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
205
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
206
/* Shift by element size is architecturally valid.
207
For logical shifts, it is a zeroing operation. */
208
if (a->imm >= (8 << a->esz)) {
209
- return do_clr_zp(s, a->rd, a->pg, a->esz);
210
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
211
} else {
212
return do_zpzi_ool(s, a, fns[a->esz]);
213
}
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
215
/* Shift by element size is architecturally valid.
216
For logical shifts, it is a zeroing operation. */
217
if (a->imm >= (8 << a->esz)) {
218
- return do_clr_zp(s, a->rd, a->pg, a->esz);
219
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
220
} else {
221
return do_zpzi_ool(s, a, fns[a->esz]);
222
}
223
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
224
/* Shift by element size is architecturally valid. For arithmetic
225
right shift for division, it is a zeroing operation. */
226
if (a->imm >= (8 << a->esz)) {
227
- return do_clr_zp(s, a->rd, a->pg, a->esz);
228
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
229
} else {
230
return do_zpzi_ool(s, a, fns[a->esz]);
231
}
232
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
233
234
/* Zero the inactive elements. */
235
gen_set_label(over);
236
- do_movz_zpz(s, a->rd, a->rd, a->pg, esz);
237
- return true;
238
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false);
239
}
240
241
static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
242
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
243
244
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
245
{
246
- if (sve_access_check(s)) {
247
- do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);
248
- }
249
- return true;
250
+ return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
251
}
252
--
253
2.20.1
254
255
diff view generated by jsdifflib
1
If we're directly booting a Linux kernel and the CPU supports both
1
From: Richard Henderson <richard.henderson@linaro.org>
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
4
instruction is enabled rather than UNDEFing. Otherwise at least some
5
kernels will panic when trying to initialize KVM in the guest.
6
2
3
Model after gen_gvec_fn_zzz et al.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-11-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
9
---
9
---
10
hw/arm/boot.c | 5 +++++
10
target/arm/translate-sve.c | 29 ++++++++++++++---------------
11
1 file changed, 5 insertions(+)
11
1 file changed, 14 insertions(+), 15 deletions(-)
12
12
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
15
--- a/target/arm/translate-sve.c
16
+++ b/hw/arm/boot.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
18
assert(!info->secure_board_setup);
18
return size_for_gvec(pred_full_reg_size(s));
19
}
19
}
20
20
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
21
+/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
22
+static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
23
+ env->cp15.scr_el3 |= SCR_HCE;
23
+ int rd, int rn, int pg, int data)
24
+ }
24
+{
25
+ unsigned vsz = vec_full_reg_size(s);
26
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
27
+ vec_full_reg_offset(s, rn),
28
+ pred_full_reg_offset(s, pg),
29
+ vsz, vsz, data, fn);
30
+}
25
+
31
+
26
/* Set to non-secure if not a secure boot */
32
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
27
if (!info->secure_boot &&
33
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
28
(cs != first_cpu || !info->secure_board_setup)) {
34
int rd, int rn, int rm, int pg, int data)
35
@@ -XXX,XX +XXX,XX @@ static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
36
return false;
37
}
38
if (sve_access_check(s)) {
39
- unsigned vsz = vec_full_reg_size(s);
40
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
41
- vec_full_reg_offset(s, a->rn),
42
- pred_full_reg_offset(s, a->pg),
43
- vsz, vsz, 0, fn);
44
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
45
}
46
return true;
47
}
48
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
49
};
50
51
if (sve_access_check(s)) {
52
- unsigned vsz = vec_full_reg_size(s);
53
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
54
- vec_full_reg_offset(s, rn),
55
- pred_full_reg_offset(s, pg),
56
- vsz, vsz, invert, fns[esz]);
57
+ gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
58
}
59
return true;
60
}
61
@@ -XXX,XX +XXX,XX @@ static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
62
gen_helper_gvec_3 *fn)
63
{
64
if (sve_access_check(s)) {
65
- unsigned vsz = vec_full_reg_size(s);
66
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
67
- vec_full_reg_offset(s, a->rn),
68
- pred_full_reg_offset(s, a->pg),
69
- vsz, vsz, a->imm, fn);
70
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
71
}
72
return true;
73
}
29
--
74
--
30
2.16.2
75
2.20.1
31
76
32
77
diff view generated by jsdifflib
1
Add some assertions that if we're about to boot an AArch64 kernel,
1
From: Richard Henderson <richard.henderson@linaro.org>
2
the board code has not mistakenly set either secure_boot or
3
secure_board_setup. It doesn't make sense to set secure_boot,
4
because all AArch64 kernels must be booted in non-secure mode.
5
2
6
It might in theory make sense to set secure_board_setup, but
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
we don't currently support that, because only the AArch32
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
5
Message-id: 20200815013145.539409-12-richard.henderson@linaro.org
9
Since we don't have a current need for this functionality, just
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
assert that we don't try to use it. If it's needed we'll add
7
---
11
it later.
8
target/arm/translate-sve.c | 53 +++++++++++++-------------------------
9
1 file changed, 18 insertions(+), 35 deletions(-)
12
10
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
16
---
17
hw/arm/boot.c | 7 +++++++
18
1 file changed, 7 insertions(+)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
13
--- a/target/arm/translate-sve.c
23
+++ b/hw/arm/boot.c
14
+++ b/target/arm/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
25
} else {
16
return size_for_gvec(pred_full_reg_size(s));
26
env->pstate = PSTATE_MODE_EL1h;
17
}
27
}
18
28
+ /* AArch64 kernels never boot in secure mode */
19
+/* Invoke an out-of-line helper on 3 Zregs. */
29
+ assert(!info->secure_boot);
20
+static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
30
+ /* This hook is only supported for AArch32 currently:
21
+ int rd, int rn, int rm, int data)
31
+ * bootloader_aarch64[] will not call the hook, and
22
+{
32
+ * the code above has already dropped us into EL2 or EL1.
23
+ unsigned vsz = vec_full_reg_size(s);
33
+ */
24
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ assert(!info->secure_board_setup);
25
+ vec_full_reg_offset(s, rn),
35
}
26
+ vec_full_reg_offset(s, rm),
36
27
+ vsz, vsz, data, fn);
37
/* Set to non-secure if not a secure boot */
28
+}
29
+
30
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
31
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
32
int rd, int rn, int pg, int data)
33
@@ -XXX,XX +XXX,XX @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
34
return false;
35
}
36
if (sve_access_check(s)) {
37
- unsigned vsz = vec_full_reg_size(s);
38
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
39
- vec_full_reg_offset(s, a->rn),
40
- vec_full_reg_offset(s, a->rm),
41
- vsz, vsz, 0, fn);
42
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
43
}
44
return true;
45
}
46
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
47
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
48
{
49
if (sve_access_check(s)) {
50
- unsigned vsz = vec_full_reg_size(s);
51
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
52
- vec_full_reg_offset(s, a->rn),
53
- vec_full_reg_offset(s, a->rm),
54
- vsz, vsz, a->imm, fn);
55
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
56
}
57
return true;
58
}
59
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
60
return false;
61
}
62
if (sve_access_check(s)) {
63
- unsigned vsz = vec_full_reg_size(s);
64
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
65
- vec_full_reg_offset(s, a->rn),
66
- vec_full_reg_offset(s, a->rm),
67
- vsz, vsz, 0, fns[a->esz]);
68
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
69
}
70
return true;
71
}
72
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
73
};
74
75
if (sve_access_check(s)) {
76
- unsigned vsz = vec_full_reg_size(s);
77
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
78
- vec_full_reg_offset(s, a->rn),
79
- vec_full_reg_offset(s, a->rm),
80
- vsz, vsz, 0, fns[a->esz]);
81
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
82
}
83
return true;
84
}
85
@@ -XXX,XX +XXX,XX @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
86
gen_helper_gvec_3 *fn)
87
{
88
if (sve_access_check(s)) {
89
- unsigned vsz = vec_full_reg_size(s);
90
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
91
- vec_full_reg_offset(s, a->rn),
92
- vec_full_reg_offset(s, a->rm),
93
- vsz, vsz, data, fn);
94
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
95
}
96
return true;
97
}
98
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
99
};
100
101
if (sve_access_check(s)) {
102
- unsigned vsz = vec_full_reg_size(s);
103
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
104
- vec_full_reg_offset(s, a->rn),
105
- vec_full_reg_offset(s, a->rm),
106
- vsz, vsz, 0, fns[a->u][a->sz]);
107
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, 0);
108
}
109
return true;
110
}
111
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
112
};
113
114
if (sve_access_check(s)) {
115
- unsigned vsz = vec_full_reg_size(s);
116
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
117
- vec_full_reg_offset(s, a->rn),
118
- vec_full_reg_offset(s, a->rm),
119
- vsz, vsz, a->index, fns[a->u][a->sz]);
120
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->index);
121
}
122
return true;
123
}
38
--
124
--
39
2.16.2
125
2.20.1
40
126
41
127
diff view generated by jsdifflib
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
From: Richard Henderson <richard.henderson@linaro.org>
2
code for keeping the secondary CPUs in a pen needs to have
3
a version for A64 as well as A32. Without this, the
4
secondary CPUs go into an infinite loop of taking undefined
5
instruction exceptions.
6
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-13-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
10
---
7
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
8
target/arm/translate-sve.c | 20 ++++++++++++--------
12
1 file changed, 40 insertions(+), 1 deletion(-)
9
1 file changed, 12 insertions(+), 8 deletions(-)
13
10
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
13
--- a/target/arm/translate-sve.c
17
+++ b/hw/arm/raspi.c
14
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
16
return size_for_gvec(pred_full_reg_size(s));
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
23
24
/* Table of Linux board IDs for different Pi versions */
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
27
info->smp_loader_start);
28
}
17
}
29
18
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
19
+/* Invoke an out-of-line helper on 2 Zregs. */
20
+static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
21
+ int rd, int rn, int data)
31
+{
22
+{
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
23
+ unsigned vsz = vec_full_reg_size(s);
33
+ * The mechanism for doing the spin-table is also entirely different.
24
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
34
+ * We must have four 64-bit fields at absolute addresses
25
+ vec_full_reg_offset(s, rn),
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
26
+ vsz, vsz, data, fn);
36
+ * our CPUs, and which we must ensure are zero initialized before
37
+ * the primary CPU goes into the kernel. We put these variables inside
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
39
+ */
40
+ static const uint32_t smpboot[] = {
41
+ 0xd2801b05, /* mov x5, 0xd8 */
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
43
+ 0x924004c6, /* and x6, x6, #0x3 */
44
+ 0xd503205f, /* spin: wfe */
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
46
+ 0xb4ffffc4, /* cbz x4, spin */
47
+ 0xd2800000, /* mov x0, #0x0 */
48
+ 0xd2800001, /* mov x1, #0x0 */
49
+ 0xd2800002, /* mov x2, #0x0 */
50
+ 0xd2800003, /* mov x3, #0x0 */
51
+ 0xd61f0080, /* br x4 */
52
+ };
53
+
54
+ static const uint64_t spintables[] = {
55
+ 0, 0, 0, 0
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
27
+}
63
+
28
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
29
/* Invoke an out-of-line helper on 3 Zregs. */
65
{
30
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
31
int rd, int rn, int rm, int data)
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
32
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
68
/* Pi2 and Pi3 requires SMP setup */
33
return false;
69
if (version >= 2) {
70
binfo.smp_loader_start = SMPBOOT_ADDR;
71
- binfo.write_secondary_boot = write_smpboot;
72
+ if (version == 2) {
73
+ binfo.write_secondary_boot = write_smpboot;
74
+ } else {
75
+ binfo.write_secondary_boot = write_smpboot64;
76
+ }
77
binfo.secondary_cpu_reset_hook = reset_secondary;
78
}
34
}
79
35
if (sve_access_check(s)) {
36
- unsigned vsz = vec_full_reg_size(s);
37
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
38
- vec_full_reg_offset(s, a->rn),
39
- vsz, vsz, 0, fns[a->esz]);
40
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
41
}
42
return true;
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
45
};
46
47
if (sve_access_check(s)) {
48
- unsigned vsz = vec_full_reg_size(s);
49
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
50
- vec_full_reg_offset(s, a->rn),
51
- vsz, vsz, 0, fns[a->esz]);
52
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
53
}
54
return true;
55
}
80
--
56
--
81
2.16.2
57
2.20.1
82
58
83
59
diff view generated by jsdifflib
1
For the rpi1 and 2 we want to boot the Linux kernel via some
1
From: Richard Henderson <richard.henderson@linaro.org>
2
custom setup code that makes sure that the SMC instruction
3
acts as a no-op, because it's used for cache maintenance.
4
The rpi3 boots AArch64 kernels, which don't need SMC for
5
cache maintenance and always expect to be booted non-secure.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
2
3
Rather than require the user to fill in the immediate (shl or shr),
4
create full formats that include the immediate.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-14-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
10
---
13
hw/arm/raspi.c | 17 +++++++++++++----
11
target/arm/sve.decode | 35 ++++++++++++++++-------------------
14
1 file changed, 13 insertions(+), 4 deletions(-)
12
1 file changed, 16 insertions(+), 19 deletions(-)
15
13
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
16
--- a/target/arm/sve.decode
19
+++ b/hw/arm/raspi.c
17
+++ b/target/arm/sve.decode
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
18
@@ -XXX,XX +XXX,XX @@
21
binfo.board_id = raspi_boardid[version];
19
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
22
binfo.ram_size = ram_size;
20
23
binfo.nb_cpus = smp_cpus;
21
# Two register operand, one immediate operand, with predicate,
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
22
-# element size encoded as TSZHL. User must fill in imm.
25
- binfo.write_board_setup = write_board_setup;
23
-@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
26
- binfo.secure_board_setup = true;
24
- &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
27
- binfo.secure_boot = true;
25
+# element size encoded as TSZHL.
28
+
26
+@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
29
+ if (version <= 2) {
27
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
28
+@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
31
+ * mode before booting a kernel (to set up the SMC vectors so
29
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
32
+ * that we get a no-op SMC; this is used by Linux to call the
30
33
+ * firmware for some cache maintenance operations.
31
# Similarly without predicate.
34
+ * The rpi3 doesn't need this.
32
-@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
35
+ */
33
- &rri_esz esz=%tszimm16_esz
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
34
+@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
37
+ binfo.write_board_setup = write_board_setup;
35
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
38
+ binfo.secure_board_setup = true;
36
+@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
39
+ binfo.secure_boot = true;
37
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
40
+ }
38
41
39
# Two register operand, one immediate operand, with 4-bit predicate.
42
/* Pi2 and Pi3 requires SMP setup */
40
# User must fill in imm.
43
if (version >= 2) {
41
@@ -XXX,XX +XXX,XX @@ UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
42
### SVE Shift by Immediate - Predicated Group
43
44
# SVE bitwise shift by immediate (predicated)
45
-ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
46
- @rdn_pg_tszimm imm=%tszimm_shr
47
-LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
48
- @rdn_pg_tszimm imm=%tszimm_shr
49
-LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
50
- @rdn_pg_tszimm imm=%tszimm_shl
51
-ASRD 00000100 .. 000 100 100 ... .. ... ..... \
52
- @rdn_pg_tszimm imm=%tszimm_shr
53
+ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
54
+LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
55
+LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
56
+ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
57
58
# SVE bitwise shift by vector (predicated)
59
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
60
@@ -XXX,XX +XXX,XX @@ RDVL 00000100 101 11111 01010 imm:s6 rd:5
61
### SVE Bitwise Shift - Unpredicated Group
62
63
# SVE bitwise shift by immediate (unpredicated)
64
-ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
65
- @rd_rn_tszimm imm=%tszimm16_shr
66
-LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
67
- @rd_rn_tszimm imm=%tszimm16_shr
68
-LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
69
- @rd_rn_tszimm imm=%tszimm16_shl
70
+ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
71
+LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
72
+LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
73
74
# SVE bitwise shift by wide elements (unpredicated)
75
# Note esz != 3
44
--
76
--
45
2.16.2
77
2.20.1
46
78
47
79
diff view generated by jsdifflib
1
From: Wei Huang <wei@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
Unify add/sub helpers and add a parameter for rounding.
4
time when guest VM runs. To find the physical base address correctly,
4
This will allow saturating non-rounding to reuse this code.
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
5
10
Signed-off-by: Wei Huang <wei@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
[PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s]
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-15-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
dump.c | 14 +++++++++++---
12
target/arm/vec_helper.c | 80 +++++++++++++++--------------------------
16
1 file changed, 11 insertions(+), 3 deletions(-)
13
1 file changed, 29 insertions(+), 51 deletions(-)
17
14
18
diff --git a/dump.c b/dump.c
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
17
--- a/target/arm/vec_helper.c
21
+++ b/dump.c
18
+++ b/target/arm/vec_helper.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
19
@@ -XXX,XX +XXX,XX @@
23
20
#endif
24
lines = g_strsplit((char *)vmci, "\n", -1);
21
25
for (i = 0; lines[i]; i++) {
22
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
23
-static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
24
- int16_t src3, uint32_t *sat)
28
+ const char *prefix = NULL;
25
+static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3,
26
+ bool neg, bool round, uint32_t *sat)
27
{
28
- /* Simplify:
29
+ /*
30
+ * Simplify:
31
* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
32
* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
33
*/
34
int32_t ret = (int32_t)src1 * src2;
35
- ret = ((int32_t)src3 << 15) + ret + (1 << 14);
36
+ if (neg) {
37
+ ret = -ret;
38
+ }
39
+ ret += ((int32_t)src3 << 15) + (round << 14);
40
ret >>= 15;
29
+
41
+
30
+ if (s->dump_info.d_machine == EM_X86_64) {
42
if (ret != (int16_t)ret) {
31
+ prefix = "NUMBER(phys_base)=";
43
*sat = 1;
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
44
- ret = (ret < 0 ? -0x8000 : 0x7fff);
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
45
+ ret = (ret < 0 ? INT16_MIN : INT16_MAX);
34
+ }
46
}
47
return ret;
48
}
49
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
50
uint32_t src2, uint32_t src3)
51
{
52
uint32_t *sat = &env->vfp.qc[0];
53
- uint16_t e1 = inl_qrdmlah_s16(src1, src2, src3, sat);
54
- uint16_t e2 = inl_qrdmlah_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
55
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat);
56
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
57
+ false, true, sat);
58
return deposit32(e1, 16, 16, e2);
59
}
60
61
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
62
uintptr_t i;
63
64
for (i = 0; i < opr_sz / 2; ++i) {
65
- d[i] = inl_qrdmlah_s16(n[i], m[i], d[i], vq);
66
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq);
67
}
68
clear_tail(d, opr_sz, simd_maxsz(desc));
69
}
70
71
-/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
72
-static int16_t inl_qrdmlsh_s16(int16_t src1, int16_t src2,
73
- int16_t src3, uint32_t *sat)
74
-{
75
- /* Similarly, using subtraction:
76
- * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
77
- * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
78
- */
79
- int32_t ret = (int32_t)src1 * src2;
80
- ret = ((int32_t)src3 << 15) - ret + (1 << 14);
81
- ret >>= 15;
82
- if (ret != (int16_t)ret) {
83
- *sat = 1;
84
- ret = (ret < 0 ? -0x8000 : 0x7fff);
85
- }
86
- return ret;
87
-}
88
-
89
uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
90
uint32_t src2, uint32_t src3)
91
{
92
uint32_t *sat = &env->vfp.qc[0];
93
- uint16_t e1 = inl_qrdmlsh_s16(src1, src2, src3, sat);
94
- uint16_t e2 = inl_qrdmlsh_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
95
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat);
96
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
97
+ true, true, sat);
98
return deposit32(e1, 16, 16, e2);
99
}
100
101
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
102
uintptr_t i;
103
104
for (i = 0; i < opr_sz / 2; ++i) {
105
- d[i] = inl_qrdmlsh_s16(n[i], m[i], d[i], vq);
106
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq);
107
}
108
clear_tail(d, opr_sz, simd_maxsz(desc));
109
}
110
111
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
112
-static int32_t inl_qrdmlah_s32(int32_t src1, int32_t src2,
113
- int32_t src3, uint32_t *sat)
114
+static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
115
+ bool neg, bool round, uint32_t *sat)
116
{
117
/* Simplify similarly to int_qrdmlah_s16 above. */
118
int64_t ret = (int64_t)src1 * src2;
119
- ret = ((int64_t)src3 << 31) + ret + (1 << 30);
120
+ if (neg) {
121
+ ret = -ret;
122
+ }
123
+ ret += ((int64_t)src3 << 31) + (round << 30);
124
ret >>= 31;
35
+
125
+
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
126
if (ret != (int32_t)ret) {
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
127
*sat = 1;
38
&phys_base) < 0) {
128
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
39
- warn_report("Failed to read NUMBER(phys_base)=");
129
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
40
+ warn_report("Failed to read %s", prefix);
130
int32_t src2, int32_t src3)
41
} else {
131
{
42
s->dump_info.phys_base = phys_base;
132
uint32_t *sat = &env->vfp.qc[0];
43
}
133
- return inl_qrdmlah_s32(src1, src2, src3, sat);
134
+ return do_sqrdmlah_s(src1, src2, src3, false, true, sat);
135
}
136
137
void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
138
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
139
uintptr_t i;
140
141
for (i = 0; i < opr_sz / 4; ++i) {
142
- d[i] = inl_qrdmlah_s32(n[i], m[i], d[i], vq);
143
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq);
144
}
145
clear_tail(d, opr_sz, simd_maxsz(desc));
146
}
147
148
-/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
149
-static int32_t inl_qrdmlsh_s32(int32_t src1, int32_t src2,
150
- int32_t src3, uint32_t *sat)
151
-{
152
- /* Simplify similarly to int_qrdmlsh_s16 above. */
153
- int64_t ret = (int64_t)src1 * src2;
154
- ret = ((int64_t)src3 << 31) - ret + (1 << 30);
155
- ret >>= 31;
156
- if (ret != (int32_t)ret) {
157
- *sat = 1;
158
- ret = (ret < 0 ? INT32_MIN : INT32_MAX);
159
- }
160
- return ret;
161
-}
162
-
163
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
164
int32_t src2, int32_t src3)
165
{
166
uint32_t *sat = &env->vfp.qc[0];
167
- return inl_qrdmlsh_s32(src1, src2, src3, sat);
168
+ return do_sqrdmlah_s(src1, src2, src3, true, true, sat);
169
}
170
171
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
172
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
173
uintptr_t i;
174
175
for (i = 0; i < opr_sz / 4; ++i) {
176
- d[i] = inl_qrdmlsh_s32(n[i], m[i], d[i], vq);
177
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq);
178
}
179
clear_tail(d, opr_sz, simd_maxsz(desc));
180
}
44
--
181
--
45
2.16.2
182
2.20.1
46
183
47
184
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
doesn't really corespond to anything in real hardware and server as a
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
8
Change the code to explicitly evaluate state of interrupts reported
9
via USR1 and USR2 against corresponding masking bits and use the to
10
detemine if IRQ line should be asserted or not.
11
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
13
reasons:
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
7
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
8
target/arm/helper.h | 4 ++++
34
1 file changed, 16 insertions(+), 8 deletions(-)
9
target/arm/translate-a64.c | 16 ++++++++++++++++
10
target/arm/vec_helper.c | 29 +++++++++++++++++++++++++----
11
3 files changed, 45 insertions(+), 4 deletions(-)
35
12
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
37
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
15
--- a/target/arm/helper.h
39
+++ b/hw/char/imx_serial.c
16
+++ b/target/arm/helper.h
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
41
18
DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
42
static void imx_update(IMXSerialState *s)
19
DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
43
{
20
44
- uint32_t flags;
21
+DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
+ uint32_t usr1;
22
+DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
46
+ uint32_t usr2;
23
+DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
47
+ uint32_t mask;
24
+
48
25
#ifdef TARGET_AARCH64
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
26
#include "helper-a64.h"
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
27
#include "helper-sve.h"
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
52
- } else {
29
index XXXXXXX..XXXXXXX 100644
53
- flags &= ~USR1_TRDY;
30
--- a/target/arm/translate-a64.c
54
- }
31
+++ b/target/arm/translate-a64.c
55
+ /*
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
33
data, gen_helper_gvec_fmlal_idx_a64);
57
+ * UCR1, so we can get away with something as simple as the
34
}
58
+ * following:
35
return;
59
+ */
36
+
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
37
+ case 0x08: /* MUL */
61
+ /*
38
+ if (!is_long && !is_scalar) {
62
+ * Bits that we want in USR2 are not as conveniently laid out,
39
+ static gen_helper_gvec_3 * const fns[3] = {
63
+ * unfortunately.
40
+ gen_helper_gvec_mul_idx_h,
64
+ */
41
+ gen_helper_gvec_mul_idx_s,
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
42
+ gen_helper_gvec_mul_idx_d,
66
+ usr2 = s->usr2 & mask;
43
+ };
67
44
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
68
- qemu_set_irq(s->irq, !!flags);
45
+ vec_full_reg_offset(s, rn),
69
+ qemu_set_irq(s->irq, usr1 || usr2);
46
+ vec_full_reg_offset(s, rm),
47
+ is_q ? 16 : 8, vec_full_reg_size(s),
48
+ index, fns[size - 1]);
49
+ return;
50
+ }
51
+ break;
52
}
53
54
if (size == 3) {
55
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/vec_helper.c
58
+++ b/target/arm/vec_helper.c
59
@@ -XXX,XX +XXX,XX @@ DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
60
*/
61
62
#define DO_MUL_IDX(NAME, TYPE, H) \
63
+void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
64
+{ \
65
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
66
+ intptr_t idx = simd_data(desc); \
67
+ TYPE *d = vd, *n = vn, *m = vm; \
68
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
69
+ TYPE mm = m[H(i + idx)]; \
70
+ for (j = 0; j < segment; j++) { \
71
+ d[i + j] = n[i + j] * mm; \
72
+ } \
73
+ } \
74
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
75
+}
76
+
77
+DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2)
78
+DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4)
79
+DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
80
+
81
+#undef DO_MUL_IDX
82
+
83
+#define DO_FMUL_IDX(NAME, TYPE, H) \
84
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
85
{ \
86
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
87
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
88
clear_tail(d, oprsz, simd_maxsz(desc)); \
70
}
89
}
71
90
72
static void imx_serial_reset(IMXSerialState *s)
91
-DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
92
-DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
93
-DO_MUL_IDX(gvec_fmul_idx_d, float64, )
94
+DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2)
95
+DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4)
96
+DO_FMUL_IDX(gvec_fmul_idx_d, float64, )
97
98
-#undef DO_MUL_IDX
99
+#undef DO_FMUL_IDX
100
101
#define DO_FMLA_IDX(NAME, TYPE, H) \
102
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
73
--
103
--
74
2.16.2
104
2.20.1
75
105
76
106
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
it is needed to support guests other than Linux.
5
6
Based on the patch by Bill Paul as found here:
7
https://bugs.launchpad.net/qemu/+bug/1753314
8
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Cc: Bill Paul <wpaul@windriver.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-20-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
7
---
19
include/hw/char/imx_serial.h | 3 +++
8
target/arm/helper.h | 14 ++++++++++++++
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
9
target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
21
2 files changed, 20 insertions(+), 3 deletions(-)
10
target/arm/vec_helper.c | 25 +++++++++++++++++++++++++
11
3 files changed, 73 insertions(+)
22
12
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
24
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
15
--- a/target/arm/helper.h
26
+++ b/include/hw/char/imx_serial.h
16
+++ b/target/arm/helper.h
27
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
18
DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
29
#define UCR2_SRST (1<<0) /* Reset complete */
19
DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
30
20
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
21
+DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG,
22
+ void, ptr, ptr, ptr, ptr, i32)
23
+DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG,
24
+ void, ptr, ptr, ptr, ptr, i32)
25
+DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG,
26
+ void, ptr, ptr, ptr, ptr, i32)
32
+
27
+
33
#define UTS1_TXEMPTY (1<<6)
28
+DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG,
34
#define UTS1_RXEMPTY (1<<5)
29
+ void, ptr, ptr, ptr, ptr, i32)
35
#define UTS1_TXFULL (1<<4)
30
+DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
31
+ void, ptr, ptr, ptr, ptr, i32)
37
uint32_t ubmr;
32
+DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
38
uint32_t ubrc;
33
+ void, ptr, ptr, ptr, ptr, i32)
39
uint32_t ucr3;
34
+
40
+ uint32_t ucr4;
35
#ifdef TARGET_AARCH64
41
36
#include "helper-a64.h"
42
qemu_irq irq;
37
#include "helper-sve.h"
43
CharBackend chr;
38
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
40
--- a/target/arm/translate-a64.c
47
+++ b/hw/char/imx_serial.c
41
+++ b/target/arm/translate-a64.c
48
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
49
43
return;
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
44
}
98
break;
45
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
46
+
100
s->ucr3 = value & 0xffff;
47
+ case 0x10: /* MLA */
101
break;
48
+ if (!is_long && !is_scalar) {
102
49
+ static gen_helper_gvec_4 * const fns[3] = {
103
- case 0x2d: /* UTS1 */
50
+ gen_helper_gvec_mla_idx_h,
104
case 0x23: /* UCR4 */
51
+ gen_helper_gvec_mla_idx_s,
105
+ s->ucr4 = value & 0xffff;
52
+ gen_helper_gvec_mla_idx_d,
106
+ imx_update(s);
53
+ };
54
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
55
+ vec_full_reg_offset(s, rn),
56
+ vec_full_reg_offset(s, rm),
57
+ vec_full_reg_offset(s, rd),
58
+ is_q ? 16 : 8, vec_full_reg_size(s),
59
+ index, fns[size - 1]);
60
+ return;
61
+ }
107
+ break;
62
+ break;
108
+
63
+
109
+ case 0x2d: /* UTS1 */
64
+ case 0x14: /* MLS */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
65
+ if (!is_long && !is_scalar) {
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
66
+ static gen_helper_gvec_4 * const fns[3] = {
112
/* TODO */
67
+ gen_helper_gvec_mls_idx_h,
68
+ gen_helper_gvec_mls_idx_s,
69
+ gen_helper_gvec_mls_idx_d,
70
+ };
71
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
72
+ vec_full_reg_offset(s, rn),
73
+ vec_full_reg_offset(s, rm),
74
+ vec_full_reg_offset(s, rd),
75
+ is_q ? 16 : 8, vec_full_reg_size(s),
76
+ index, fns[size - 1]);
77
+ return;
78
+ }
79
+ break;
80
}
81
82
if (size == 3) {
83
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/vec_helper.c
86
+++ b/target/arm/vec_helper.c
87
@@ -XXX,XX +XXX,XX @@ DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
88
89
#undef DO_MUL_IDX
90
91
+#define DO_MLA_IDX(NAME, TYPE, OP, H) \
92
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
93
+{ \
94
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
95
+ intptr_t idx = simd_data(desc); \
96
+ TYPE *d = vd, *n = vn, *m = vm, *a = va; \
97
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
98
+ TYPE mm = m[H(i + idx)]; \
99
+ for (j = 0; j < segment; j++) { \
100
+ d[i + j] = a[i + j] OP n[i + j] * mm; \
101
+ } \
102
+ } \
103
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
104
+}
105
+
106
+DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2)
107
+DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4)
108
+DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, )
109
+
110
+DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2)
111
+DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4)
112
+DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
113
+
114
+#undef DO_MLA_IDX
115
+
116
#define DO_FMUL_IDX(NAME, TYPE, H) \
117
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
118
{ \
113
--
119
--
114
2.16.2
120
2.20.1
115
121
116
122
diff view generated by jsdifflib
1
Our BCM2836 type is really a generic one that can be any of
1
From: Richard Henderson <richard.henderson@linaro.org>
2
the bcm283x family. Rename it accordingly. We change only
3
the names which are visible via the header file to the
4
rest of the QEMU code, leaving private function names
5
in bcm2836.c as they are.
6
2
7
This is a preliminary to making bcm283x be an abstract
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
parent class to specific types for the bcm2836 and bcm2837.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-21-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.h | 10 ++++++++
9
target/arm/translate-a64.c | 33 ++++++++++++++++++--------
10
target/arm/vec_helper.c | 48 ++++++++++++++++++++++++++++++++++++++
11
3 files changed, 81 insertions(+), 10 deletions(-)
9
12
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
16
hw/arm/bcm2836.c | 17 +++++++++--------
17
hw/arm/raspi.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
15
--- a/target/arm/helper.h
23
+++ b/include/hw/arm/bcm2836.h
16
+++ b/target/arm/helper.h
24
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
25
#include "hw/arm/bcm2835_peripherals.h"
18
DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
26
#include "hw/intc/bcm2836_control.h"
19
void, ptr, ptr, ptr, ptr, i32)
27
20
28
-#define TYPE_BCM2836 "bcm2836"
21
+DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG,
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
22
+ void, ptr, ptr, ptr, ptr, i32)
30
+#define TYPE_BCM283X "bcm283x"
23
+DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG,
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
24
+ void, ptr, ptr, ptr, ptr, i32)
32
25
+
33
-#define BCM2836_NCPUS 4
26
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG,
34
+#define BCM283X_NCPUS 4
27
+ void, ptr, ptr, ptr, ptr, i32)
35
28
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG,
36
-typedef struct BCM2836State {
29
+ void, ptr, ptr, ptr, ptr, i32)
37
+typedef struct BCM283XState {
30
+
38
/*< private >*/
31
#ifdef TARGET_AARCH64
39
DeviceState parent_obj;
32
#include "helper-a64.h"
40
/*< public >*/
33
#include "helper-sve.h"
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
42
char *cpu_type;
43
uint32_t enabled_cpus;
44
45
- ARMCPU cpus[BCM2836_NCPUS];
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
BCM2836ControlState control;
48
BCM2835PeripheralState peripherals;
49
-} BCM2836State;
50
+} BCM283XState;
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
36
--- a/target/arm/translate-a64.c
56
+++ b/hw/arm/bcm2836.c
37
+++ b/target/arm/translate-a64.c
57
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
58
39
tcg_temp_free_ptr(fpst);
59
static void bcm2836_init(Object *obj)
60
{
61
- BCM2836State *s = BCM2836(obj);
62
+ BCM283XState *s = BCM283X(obj);
63
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
67
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
69
{
70
- BCM2836State *s = BCM2836(dev);
71
+ BCM283XState *s = BCM283X(dev);
72
Object *obj;
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
40
}
95
41
96
static Property bcm2836_props[] = {
42
+/* Expand a 3-operand + qc + operation using an out-of-line helper. */
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
43
+static void gen_gvec_op3_qc(DisasContext *s, bool is_q, int rd, int rn,
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
44
+ int rm, gen_helper_gvec_3_ptr *fn)
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
45
+{
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
46
+ TCGv_ptr qc_ptr = tcg_temp_new_ptr();
101
+ BCM283X_NCPUS),
47
+
102
DEFINE_PROP_END_OF_LIST()
48
+ tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc));
103
};
49
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
104
50
+ vec_full_reg_offset(s, rn),
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
51
+ vec_full_reg_offset(s, rm), qc_ptr,
52
+ is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
53
+ tcg_temp_free_ptr(qc_ptr);
54
+}
55
+
56
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
57
* than the 32 bit equivalent.
58
*/
59
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
60
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
61
}
62
return;
63
+ case 0x16: /* SQDMULH, SQRDMULH */
64
+ {
65
+ static gen_helper_gvec_3_ptr * const fns[2][2] = {
66
+ { gen_helper_neon_sqdmulh_h, gen_helper_neon_sqrdmulh_h },
67
+ { gen_helper_neon_sqdmulh_s, gen_helper_neon_sqrdmulh_s },
68
+ };
69
+ gen_gvec_op3_qc(s, is_q, rd, rn, rm, fns[size - 1][u]);
70
+ }
71
+ return;
72
case 0x11:
73
if (!u) { /* CMTST */
74
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size);
75
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
76
genenvfn = fns[size][u];
77
break;
78
}
79
- case 0x16: /* SQDMULH, SQRDMULH */
80
- {
81
- static NeonGenTwoOpEnvFn * const fns[2][2] = {
82
- { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
83
- { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
84
- };
85
- assert(size == 1 || size == 2);
86
- genenvfn = fns[size - 1][u];
87
- break;
88
- }
89
default:
90
g_assert_not_reached();
91
}
92
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/vec_helper.c
95
+++ b/target/arm/vec_helper.c
96
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
97
clear_tail(d, opr_sz, simd_maxsz(desc));
106
}
98
}
107
99
108
static const TypeInfo bcm2836_type_info = {
100
+void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm,
109
- .name = TYPE_BCM2836,
101
+ void *vq, uint32_t desc)
110
+ .name = TYPE_BCM283X,
102
+{
111
.parent = TYPE_DEVICE,
103
+ intptr_t i, opr_sz = simd_oprsz(desc);
112
- .instance_size = sizeof(BCM2836State),
104
+ int16_t *d = vd, *n = vn, *m = vm;
113
+ .instance_size = sizeof(BCM283XState),
105
+
114
.instance_init = bcm2836_init,
106
+ for (i = 0; i < opr_sz / 2; ++i) {
115
.class_init = bcm2836_class_init,
107
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq);
116
};
108
+ }
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
109
+ clear_tail(d, opr_sz, simd_maxsz(desc));
118
index XXXXXXX..XXXXXXX 100644
110
+}
119
--- a/hw/arm/raspi.c
111
+
120
+++ b/hw/arm/raspi.c
112
+void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm,
121
@@ -XXX,XX +XXX,XX @@
113
+ void *vq, uint32_t desc)
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
114
+{
123
115
+ intptr_t i, opr_sz = simd_oprsz(desc);
124
typedef struct RasPiState {
116
+ int16_t *d = vd, *n = vn, *m = vm;
125
- BCM2836State soc;
117
+
126
+ BCM283XState soc;
118
+ for (i = 0; i < opr_sz / 2; ++i) {
127
MemoryRegion ram;
119
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq);
128
} RasPiState;
120
+ }
129
121
+ clear_tail(d, opr_sz, simd_maxsz(desc));
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
122
+}
131
BusState *bus;
123
+
132
DeviceState *carddev;
124
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
133
125
static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
126
bool neg, bool round, uint32_t *sat)
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
127
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
128
clear_tail(d, opr_sz, simd_maxsz(desc));
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
129
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
130
131
+void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm,
132
+ void *vq, uint32_t desc)
133
+{
134
+ intptr_t i, opr_sz = simd_oprsz(desc);
135
+ int32_t *d = vd, *n = vn, *m = vm;
136
+
137
+ for (i = 0; i < opr_sz / 4; ++i) {
138
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq);
139
+ }
140
+ clear_tail(d, opr_sz, simd_maxsz(desc));
141
+}
142
+
143
+void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm,
144
+ void *vq, uint32_t desc)
145
+{
146
+ intptr_t i, opr_sz = simd_oprsz(desc);
147
+ int32_t *d = vd, *n = vn, *m = vm;
148
+
149
+ for (i = 0; i < opr_sz / 4; ++i) {
150
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq);
151
+ }
152
+ clear_tail(d, opr_sz, simd_maxsz(desc));
153
+}
154
+
155
/* Integer 8 and 16-bit dot-product.
156
*
157
* Note that for the loops herein, host endianness does not matter
165
--
158
--
166
2.16.2
159
2.20.1
167
160
168
161
diff view generated by jsdifflib