| 1 | Arm patch queue -- these are all bug fix patches but we might | 1 | Handful of bugfixes for rc2. None of these are particularly critical |
|---|---|---|---|
| 2 | as well put them in to rc0... | 2 | or exciting. |
| 3 | 3 | ||
| 4 | thanks | ||
| 5 | -- PMM | 4 | -- PMM |
| 6 | 5 | ||
| 7 | The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be: | 6 | The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345: |
| 8 | 7 | ||
| 9 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000) | 8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100) |
| 10 | 9 | ||
| 11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 12 | 11 | ||
| 13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803 |
| 14 | 13 | ||
| 15 | for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6: | 14 | for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8: |
| 16 | 15 | ||
| 17 | hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000) | 16 | hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100) |
| 18 | 17 | ||
| 19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 20 | target-arm queue: | 19 | target-arm queue: |
| 21 | * fsl-imx6: Fix incorrect Ethernet interrupt defines | 20 | * hw/timer/imx_epit: Avoid assertion when CR.SWR is written |
| 22 | * dump: Update correct kdump phys_base field for AArch64 | 21 | * netduino2, netduinoplus2, microbit: set system_clock_scale so that |
| 23 | * char: i.MX: Add support for "TX complete" interrupt | 22 | SysTick running on the CPU clock works |
| 24 | * bcm2836/raspi: Fix various bugs resulting in panics trying | 23 | * target/arm: Avoid maybe-uninitialized warning with gcc 4.9 |
| 25 | to boot a Debian Linux kernel on raspi3 | 24 | * target/arm: Fix AddPAC error indication |
| 25 | * Make AIRCR.SYSRESETREQ actually reset the system for the | ||
| 26 | microbit, mps2-*, musca-*, netduino* boards | ||
| 26 | 27 | ||
| 27 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 28 | Andrey Smirnov (2): | 29 | Kaige Li (1): |
| 29 | char: i.MX: Simplify imx_update() | 30 | target/arm: Avoid maybe-uninitialized warning with gcc 4.9 |
| 30 | char: i.MX: Add support for "TX complete" interrupt | ||
| 31 | 31 | ||
| 32 | Guenter Roeck (1): | 32 | Peter Maydell (6): |
| 33 | fsl-imx6: Swap Ethernet interrupt defines | 33 | hw/arm/netduino2, netduinoplus2: Set system_clock_scale |
| 34 | include/hw/irq.h: New function qemu_irq_is_connected() | ||
| 35 | hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ | ||
| 36 | msf2-soc, stellaris: Don't wire up SYSRESETREQ | ||
| 37 | hw/arm/nrf51_soc: Set system_clock_scale | ||
| 38 | hw/timer/imx_epit: Avoid assertion when CR.SWR is written | ||
| 34 | 39 | ||
| 35 | Peter Maydell (9): | 40 | Richard Henderson (1): |
| 36 | hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 | 41 | target/arm: Fix AddPAC error indication |
| 37 | hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 | ||
| 38 | hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE | ||
| 39 | hw/arm/bcm2386: Fix parent type of bcm2386 | ||
| 40 | hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x | ||
| 41 | hw/arm/bcm2836: Create proper bcm2837 device | ||
| 42 | hw/arm/bcm2836: Use correct affinity values for BCM2837 | ||
| 43 | hw/arm/bcm2836: Hardcode correct CPU type | ||
| 44 | hw/arm/raspi: Provide spin-loop code for AArch64 CPUs | ||
| 45 | 42 | ||
| 46 | Wei Huang (1): | 43 | include/hw/arm/armv7m.h | 4 +++- |
| 47 | dump: Update correct kdump phys_base field for AArch64 | 44 | include/hw/irq.h | 18 ++++++++++++++++++ |
| 45 | hw/arm/msf2-soc.c | 11 ----------- | ||
| 46 | hw/arm/netduino2.c | 10 ++++++++++ | ||
| 47 | hw/arm/netduinoplus2.c | 10 ++++++++++ | ||
| 48 | hw/arm/nrf51_soc.c | 5 +++++ | ||
| 49 | hw/arm/stellaris.c | 12 ------------ | ||
| 50 | hw/intc/armv7m_nvic.c | 17 ++++++++++++++++- | ||
| 51 | hw/timer/imx_epit.c | 13 ++++++++++--- | ||
| 52 | target/arm/pauth_helper.c | 6 +++++- | ||
| 53 | target/arm/translate-a64.c | 2 +- | ||
| 54 | tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++++ | ||
| 55 | tests/tcg/aarch64/Makefile.target | 2 +- | ||
| 56 | 13 files changed, 112 insertions(+), 31 deletions(-) | ||
| 57 | create mode 100644 tests/tcg/aarch64/pauth-5.c | ||
| 48 | 58 | ||
| 49 | include/hw/arm/bcm2836.h | 31 +++++++++++++--- | ||
| 50 | include/hw/arm/fsl-imx6.h | 4 +- | ||
| 51 | include/hw/char/imx_serial.h | 3 ++ | ||
| 52 | dump.c | 14 +++++-- | ||
| 53 | hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++------------- | ||
| 54 | hw/arm/boot.c | 12 ++++++ | ||
| 55 | hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++-------- | ||
| 56 | hw/char/imx_serial.c | 44 ++++++++++++++++------ | ||
| 57 | hw/net/imx_fec.c | 28 +++++++++++++- | ||
| 58 | 9 files changed, 237 insertions(+), 63 deletions(-) | ||
| 59 | diff view generated by jsdifflib |
| 1 | Now we have separate types for BCM2386 and BCM2387, we might as well | 1 | The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale |
|---|---|---|---|
| 2 | just hard-code the CPU type they use rather than having it passed | 2 | global, which meant that if guest code used the systick timer in "use |
| 3 | through as an object property. This then lets us put the initialization | 3 | the processor clock" mode it would hang because time never advances. |
| 4 | of the CPU object in init rather than realize. | ||
| 5 | 4 | ||
| 6 | Note that this change means that it's no longer possible on | 5 | Set the global to match the documented CPU clock speed of these boards. |
| 7 | the command line to use -cpu to ask for a different kind of | 6 | Judging by the data sheet this is slightly simplistic because the |
| 8 | CPU than the SoC supports. This was never a supported thing to | 7 | SoC allows configuration of the SYSCLK source and frequency via the |
| 9 | do anyway; we were just not sanity-checking the command line. | 8 | RCC (reset and clock control) module, but we don't model that. |
| 10 | 9 | ||
| 11 | This does require us to only build the bcm2837 object on | 10 | Fixes: https://bugs.launchpad.net/qemu/+bug/1876187 |
| 12 | TARGET_AARCH64 configs, since otherwise it won't instantiate | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | due to the missing cortex-a53 device and "make check" will fail. | 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | Message-id: 20200727162617.26227-1-peter.maydell@linaro.org | ||
| 14 | --- | ||
| 15 | hw/arm/netduino2.c | 10 ++++++++++ | ||
| 16 | hw/arm/netduinoplus2.c | 10 ++++++++++ | ||
| 17 | 2 files changed, 20 insertions(+) | ||
| 14 | 18 | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c |
| 16 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 17 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 18 | Message-id: 20180313153458.26822-9-peter.maydell@linaro.org | ||
| 19 | --- | ||
| 20 | hw/arm/bcm2836.c | 24 +++++++++++++++--------- | ||
| 21 | hw/arm/raspi.c | 2 -- | ||
| 22 | 2 files changed, 15 insertions(+), 11 deletions(-) | ||
| 23 | |||
| 24 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/hw/arm/bcm2836.c | 21 | --- a/hw/arm/netduino2.c |
| 27 | +++ b/hw/arm/bcm2836.c | 22 | +++ b/hw/arm/netduino2.c |
| 28 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ |
| 29 | 24 | #include "hw/arm/stm32f205_soc.h" | |
| 30 | struct BCM283XInfo { | 25 | #include "hw/arm/boot.h" |
| 31 | const char *name; | 26 | |
| 32 | + const char *cpu_type; | 27 | +/* Main SYSCLK frequency in Hz (120MHz) */ |
| 33 | int clusterid; | 28 | +#define SYSCLK_FRQ 120000000ULL |
| 34 | }; | 29 | + |
| 35 | 30 | static void netduino2_init(MachineState *machine) | |
| 36 | static const BCM283XInfo bcm283x_socs[] = { | ||
| 37 | { | ||
| 38 | .name = TYPE_BCM2836, | ||
| 39 | + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), | ||
| 40 | .clusterid = 0xf, | ||
| 41 | }, | ||
| 42 | +#ifdef TARGET_AARCH64 | ||
| 43 | { | ||
| 44 | .name = TYPE_BCM2837, | ||
| 45 | + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), | ||
| 46 | .clusterid = 0x0, | ||
| 47 | }, | ||
| 48 | +#endif | ||
| 49 | }; | ||
| 50 | |||
| 51 | static void bcm2836_init(Object *obj) | ||
| 52 | { | 31 | { |
| 53 | BCM283XState *s = BCM283X(obj); | 32 | DeviceState *dev; |
| 54 | + BCM283XClass *bc = BCM283X_GET_CLASS(obj); | 33 | |
| 55 | + const BCM283XInfo *info = bc->info; | 34 | + /* |
| 56 | + int n; | 35 | + * TODO: ideally we would model the SoC RCC and let it handle |
| 36 | + * system_clock_scale, including its ability to define different | ||
| 37 | + * possible SYSCLK sources. | ||
| 38 | + */ | ||
| 39 | + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; | ||
| 57 | + | 40 | + |
| 58 | + for (n = 0; n < BCM283X_NCPUS; n++) { | 41 | dev = qdev_new(TYPE_STM32F205_SOC); |
| 59 | + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | 42 | qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); |
| 60 | + info->cpu_type); | 43 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 61 | + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | 44 | diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c |
| 62 | + &error_abort); | ||
| 63 | + } | ||
| 64 | |||
| 65 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | ||
| 66 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 68 | |||
| 69 | /* common peripherals from bcm2835 */ | ||
| 70 | |||
| 71 | - obj = OBJECT(dev); | ||
| 72 | - for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 73 | - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
| 74 | - s->cpu_type); | ||
| 75 | - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
| 76 | - &error_abort); | ||
| 77 | - } | ||
| 78 | - | ||
| 79 | obj = object_property_get_link(OBJECT(dev), "ram", &err); | ||
| 80 | if (obj == NULL) { | ||
| 81 | error_setg(errp, "%s: required ram link not found: %s", | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 83 | } | ||
| 84 | |||
| 85 | static Property bcm2836_props[] = { | ||
| 86 | - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), | ||
| 87 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, | ||
| 88 | BCM283X_NCPUS), | ||
| 89 | DEFINE_PROP_END_OF_LIST() | ||
| 90 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 91 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
| 92 | --- a/hw/arm/raspi.c | 46 | --- a/hw/arm/netduinoplus2.c |
| 93 | +++ b/hw/arm/raspi.c | 47 | +++ b/hw/arm/netduinoplus2.c |
| 94 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | 48 | @@ -XXX,XX +XXX,XX @@ |
| 95 | /* Setup the SOC */ | 49 | #include "hw/arm/stm32f405_soc.h" |
| 96 | object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), | 50 | #include "hw/arm/boot.h" |
| 97 | &error_abort); | 51 | |
| 98 | - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", | 52 | +/* Main SYSCLK frequency in Hz (168MHz) */ |
| 99 | - &error_abort); | 53 | +#define SYSCLK_FRQ 168000000ULL |
| 100 | object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", | 54 | + |
| 101 | &error_abort); | 55 | static void netduinoplus2_init(MachineState *machine) |
| 102 | int board_rev = version == 3 ? 0xa02082 : 0xa21041; | 56 | { |
| 57 | DeviceState *dev; | ||
| 58 | |||
| 59 | + /* | ||
| 60 | + * TODO: ideally we would model the SoC RCC and let it handle | ||
| 61 | + * system_clock_scale, including its ability to define different | ||
| 62 | + * possible SYSCLK sources. | ||
| 63 | + */ | ||
| 64 | + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; | ||
| 65 | + | ||
| 66 | dev = qdev_new(TYPE_STM32F405_SOC); | ||
| 67 | qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); | ||
| 68 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
| 103 | -- | 69 | -- |
| 104 | 2.16.2 | 70 | 2.20.1 |
| 105 | 71 | ||
| 106 | 72 | diff view generated by jsdifflib |
| 1 | The raspi3 has AArch64 CPUs, which means that our smpboot | 1 | Mostly devices don't need to care whether one of their output |
|---|---|---|---|
| 2 | code for keeping the secondary CPUs in a pen needs to have | 2 | qemu_irq lines is connected, because functions like qemu_set_irq() |
| 3 | a version for A64 as well as A32. Without this, the | 3 | silently do nothing if there is nothing on the other end. However |
| 4 | secondary CPUs go into an infinite loop of taking undefined | 4 | sometimes a device might want to implement default behaviour for the |
| 5 | instruction exceptions. | 5 | case where the machine hasn't wired the line up to anywhere. |
| 6 | |||
| 7 | Provide a function qemu_irq_is_connected() that devices can use for | ||
| 8 | this purpose. (The test is trivial but encapsulating it in a | ||
| 9 | function makes it easier to see where we're doing it in case we need | ||
| 10 | to change the implementation later.) | ||
| 6 | 11 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 9 | Message-id: 20180313153458.26822-10-peter.maydell@linaro.org | 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 15 | Message-id: 20200728103744.6909-2-peter.maydell@linaro.org | ||
| 10 | --- | 16 | --- |
| 11 | hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- | 17 | include/hw/irq.h | 18 ++++++++++++++++++ |
| 12 | 1 file changed, 40 insertions(+), 1 deletion(-) | 18 | 1 file changed, 18 insertions(+) |
| 13 | 19 | ||
| 14 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 20 | diff --git a/include/hw/irq.h b/include/hw/irq.h |
| 15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/arm/raspi.c | 22 | --- a/include/hw/irq.h |
| 17 | +++ b/hw/arm/raspi.c | 23 | +++ b/include/hw/irq.h |
| 18 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); |
| 19 | #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ | 25 | on an existing vector of qemu_irq. */ |
| 20 | #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ | 26 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); |
| 21 | #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ | 27 | |
| 22 | +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ | 28 | +/** |
| 23 | 29 | + * qemu_irq_is_connected: Return true if IRQ line is wired up | |
| 24 | /* Table of Linux board IDs for different Pi versions */ | 30 | + * |
| 25 | static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | 31 | + * If a qemu_irq has a device on the other (receiving) end of it, |
| 26 | @@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) | 32 | + * return true; otherwise return false. |
| 27 | info->smp_loader_start); | 33 | + * |
| 28 | } | 34 | + * Usually device models don't need to care whether the machine model |
| 29 | 35 | + * has wired up their outbound qemu_irq lines, because functions like | |
| 30 | +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) | 36 | + * qemu_set_irq() silently do nothing if there is nothing on the other |
| 37 | + * end of the line. However occasionally a device model will want to | ||
| 38 | + * provide default behaviour if its output is left floating, and | ||
| 39 | + * it can use this function to identify when that is the case. | ||
| 40 | + */ | ||
| 41 | +static inline bool qemu_irq_is_connected(qemu_irq irq) | ||
| 31 | +{ | 42 | +{ |
| 32 | + /* Unlike the AArch32 version we don't need to call the board setup hook. | 43 | + return irq != NULL; |
| 33 | + * The mechanism for doing the spin-table is also entirely different. | ||
| 34 | + * We must have four 64-bit fields at absolute addresses | ||
| 35 | + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for | ||
| 36 | + * our CPUs, and which we must ensure are zero initialized before | ||
| 37 | + * the primary CPU goes into the kernel. We put these variables inside | ||
| 38 | + * a rom blob, so that the reset for ROM contents zeroes them for us. | ||
| 39 | + */ | ||
| 40 | + static const uint32_t smpboot[] = { | ||
| 41 | + 0xd2801b05, /* mov x5, 0xd8 */ | ||
| 42 | + 0xd53800a6, /* mrs x6, mpidr_el1 */ | ||
| 43 | + 0x924004c6, /* and x6, x6, #0x3 */ | ||
| 44 | + 0xd503205f, /* spin: wfe */ | ||
| 45 | + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ | ||
| 46 | + 0xb4ffffc4, /* cbz x4, spin */ | ||
| 47 | + 0xd2800000, /* mov x0, #0x0 */ | ||
| 48 | + 0xd2800001, /* mov x1, #0x0 */ | ||
| 49 | + 0xd2800002, /* mov x2, #0x0 */ | ||
| 50 | + 0xd2800003, /* mov x3, #0x0 */ | ||
| 51 | + 0xd61f0080, /* br x4 */ | ||
| 52 | + }; | ||
| 53 | + | ||
| 54 | + static const uint64_t spintables[] = { | ||
| 55 | + 0, 0, 0, 0 | ||
| 56 | + }; | ||
| 57 | + | ||
| 58 | + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), | ||
| 59 | + info->smp_loader_start); | ||
| 60 | + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), | ||
| 61 | + SPINTABLE_ADDR); | ||
| 62 | +} | 44 | +} |
| 63 | + | 45 | + |
| 64 | static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) | 46 | #endif |
| 65 | { | ||
| 66 | arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
| 68 | /* Pi2 and Pi3 requires SMP setup */ | ||
| 69 | if (version >= 2) { | ||
| 70 | binfo.smp_loader_start = SMPBOOT_ADDR; | ||
| 71 | - binfo.write_secondary_boot = write_smpboot; | ||
| 72 | + if (version == 2) { | ||
| 73 | + binfo.write_secondary_boot = write_smpboot; | ||
| 74 | + } else { | ||
| 75 | + binfo.write_secondary_boot = write_smpboot64; | ||
| 76 | + } | ||
| 77 | binfo.secondary_cpu_reset_hook = reset_secondary; | ||
| 78 | } | ||
| 79 | |||
| 80 | -- | 47 | -- |
| 81 | 2.16.2 | 48 | 2.20.1 |
| 82 | 49 | ||
| 83 | 50 | diff view generated by jsdifflib |
| 1 | The BCM2837 sets the Aff1 field of the MPIDR affinity values for the | 1 | The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals |
|---|---|---|---|
| 2 | CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it | 2 | when the guest sets the SYSRESETREQ bit in the AIRCR register. This |
| 3 | is required for Linux to boot. | 3 | matches the hardware design (where the CPU has a signal of this name |
| 4 | and it is up to the SoC to connect that up to an actual reset | ||
| 5 | mechanism), but in QEMU it mostly results in duplicated code in SoC | ||
| 6 | objects and bugs where SoC model implementors forget to wire up the | ||
| 7 | SYSRESETREQ line. | ||
| 8 | |||
| 9 | Provide a default behaviour for the case where SYSRESETREQ is not | ||
| 10 | actually connected to anything: use qemu_system_reset_request() to | ||
| 11 | perform a system reset. This will allow us to remove the | ||
| 12 | implementations of SYSRESETREQ handling from the boards where that's | ||
| 13 | exactly what it does, and also fixes the bugs in the board models | ||
| 14 | which forgot to wire up the signal: | ||
| 15 | |||
| 16 | * microbit | ||
| 17 | * mps2-an385 | ||
| 18 | * mps2-an505 | ||
| 19 | * mps2-an511 | ||
| 20 | * mps2-an521 | ||
| 21 | * musca-a | ||
| 22 | * musca-b1 | ||
| 23 | * netduino | ||
| 24 | * netduinoplus2 | ||
| 25 | |||
| 26 | We still allow the board to wire up the signal if it needs to, in case | ||
| 27 | we need to model more complicated reset controller logic or to model | ||
| 28 | buggy SoC hardware which forgot to wire up the line itself. But | ||
| 29 | defaulting to "reset the system" is more often going to be correct | ||
| 30 | than defaulting to "do nothing". | ||
| 4 | 31 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 33 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 8 | Message-id: 20180313153458.26822-8-peter.maydell@linaro.org | 34 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 35 | Message-id: 20200728103744.6909-3-peter.maydell@linaro.org | ||
| 9 | --- | 36 | --- |
| 10 | hw/arm/bcm2836.c | 11 +++++++---- | 37 | include/hw/arm/armv7m.h | 4 +++- |
| 11 | 1 file changed, 7 insertions(+), 4 deletions(-) | 38 | hw/intc/armv7m_nvic.c | 17 ++++++++++++++++- |
| 39 | 2 files changed, 19 insertions(+), 2 deletions(-) | ||
| 12 | 40 | ||
| 13 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 41 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h |
| 14 | index XXXXXXX..XXXXXXX 100644 | 42 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/arm/bcm2836.c | 43 | --- a/include/hw/arm/armv7m.h |
| 16 | +++ b/hw/arm/bcm2836.c | 44 | +++ b/include/hw/arm/armv7m.h |
| 45 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 46 | |||
| 47 | /* ARMv7M container object. | ||
| 48 | * + Unnamed GPIO input lines: external IRQ lines for the NVIC | ||
| 49 | - * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ | ||
| 50 | + * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ. | ||
| 51 | + * If this GPIO is not wired up then the NVIC will default to performing | ||
| 52 | + * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). | ||
| 53 | * + Property "cpu-type": CPU type to instantiate | ||
| 54 | * + Property "num-irq": number of external IRQ lines | ||
| 55 | * + Property "memory": MemoryRegion defining the physical address space | ||
| 56 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
| 57 | index XXXXXXX..XXXXXXX 100644 | ||
| 58 | --- a/hw/intc/armv7m_nvic.c | ||
| 59 | +++ b/hw/intc/armv7m_nvic.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | 60 | @@ -XXX,XX +XXX,XX @@ |
| 18 | 61 | #include "hw/intc/armv7m_nvic.h" | |
| 19 | struct BCM283XInfo { | 62 | #include "hw/irq.h" |
| 20 | const char *name; | 63 | #include "hw/qdev-properties.h" |
| 21 | + int clusterid; | 64 | +#include "sysemu/runstate.h" |
| 65 | #include "target/arm/cpu.h" | ||
| 66 | #include "exec/exec-all.h" | ||
| 67 | #include "exec/memop.h" | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = { | ||
| 69 | 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 | ||
| 22 | }; | 70 | }; |
| 23 | 71 | ||
| 24 | static const BCM283XInfo bcm283x_socs[] = { | 72 | +static void signal_sysresetreq(NVICState *s) |
| 25 | { | 73 | +{ |
| 26 | .name = TYPE_BCM2836, | 74 | + if (qemu_irq_is_connected(s->sysresetreq)) { |
| 27 | + .clusterid = 0xf, | 75 | + qemu_irq_pulse(s->sysresetreq); |
| 28 | }, | 76 | + } else { |
| 29 | { | 77 | + /* |
| 30 | .name = TYPE_BCM2837, | 78 | + * Default behaviour if the SoC doesn't need to wire up |
| 31 | + .clusterid = 0x0, | 79 | + * SYSRESETREQ (eg to a system reset controller of some kind): |
| 32 | }, | 80 | + * perform a system reset via the usual QEMU API. |
| 33 | }; | 81 | + */ |
| 34 | 82 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
| 35 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) | 83 | + } |
| 36 | static void bcm2836_realize(DeviceState *dev, Error **errp) | 84 | +} |
| 85 | + | ||
| 86 | static int nvic_pending_prio(NVICState *s) | ||
| 37 | { | 87 | { |
| 38 | BCM283XState *s = BCM283X(dev); | 88 | /* return the group priority of the current pending interrupt, |
| 39 | + BCM283XClass *bc = BCM283X_GET_CLASS(dev); | 89 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, |
| 40 | + const BCM283XInfo *info = bc->info; | 90 | if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { |
| 41 | Object *obj; | 91 | if (attrs.secure || |
| 42 | Error *err = NULL; | 92 | !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { |
| 43 | int n; | 93 | - qemu_irq_pulse(s->sysresetreq); |
| 44 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | 94 | + signal_sysresetreq(s); |
| 45 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | 95 | } |
| 46 | 96 | } | |
| 47 | for (n = 0; n < BCM283X_NCPUS; n++) { | 97 | if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { |
| 48 | - /* Mirror bcm2836, which has clusterid set to 0xf | ||
| 49 | - * TODO: this should be converted to a property of ARM_CPU | ||
| 50 | - */ | ||
| 51 | - s->cpus[n].mp_affinity = 0xF00 | n; | ||
| 52 | + /* TODO: this should be converted to a property of ARM_CPU */ | ||
| 53 | + s->cpus[n].mp_affinity = (info->clusterid << 8) | n; | ||
| 54 | |||
| 55 | /* set periphbase/CBAR value for CPU-local registers */ | ||
| 56 | object_property_set_int(OBJECT(&s->cpus[n]), | ||
| 57 | -- | 98 | -- |
| 58 | 2.16.2 | 99 | 2.20.1 |
| 59 | 100 | ||
| 60 | 101 | diff view generated by jsdifflib |
| 1 | Our BCM2836 type is really a generic one that can be any of | 1 | The MSF2 SoC model and the Stellaris board code both wire |
|---|---|---|---|
| 2 | the bcm283x family. Rename it accordingly. We change only | 2 | SYSRESETREQ up to a function that just invokes |
| 3 | the names which are visible via the header file to the | 3 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 4 | rest of the QEMU code, leaving private function names | 4 | This is now the default action that the NVIC does if the line is |
| 5 | in bcm2836.c as they are. | 5 | not connected, so we can delete the handling code. |
| 6 | |||
| 7 | This is a preliminary to making bcm283x be an abstract | ||
| 8 | parent class to specific types for the bcm2836 and bcm2837. | ||
| 9 | 6 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 13 | Message-id: 20180313153458.26822-6-peter.maydell@linaro.org | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | Message-id: 20200728103744.6909-4-peter.maydell@linaro.org | ||
| 14 | --- | 11 | --- |
| 15 | include/hw/arm/bcm2836.h | 12 ++++++------ | 12 | hw/arm/msf2-soc.c | 11 ----------- |
| 16 | hw/arm/bcm2836.c | 17 +++++++++-------- | 13 | hw/arm/stellaris.c | 12 ------------ |
| 17 | hw/arm/raspi.c | 16 ++++++++-------- | 14 | 2 files changed, 23 deletions(-) |
| 18 | 3 files changed, 23 insertions(+), 22 deletions(-) | ||
| 19 | 15 | ||
| 20 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | 16 | diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c |
| 21 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/arm/bcm2836.h | 18 | --- a/hw/arm/msf2-soc.c |
| 23 | +++ b/include/hw/arm/bcm2836.h | 19 | +++ b/hw/arm/msf2-soc.c |
| 24 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
| 25 | #include "hw/arm/bcm2835_peripherals.h" | 21 | #include "hw/irq.h" |
| 26 | #include "hw/intc/bcm2836_control.h" | 22 | #include "hw/arm/msf2-soc.h" |
| 27 | 23 | #include "hw/misc/unimp.h" | |
| 28 | -#define TYPE_BCM2836 "bcm2836" | 24 | -#include "sysemu/runstate.h" |
| 29 | -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) | 25 | #include "sysemu/sysemu.h" |
| 30 | +#define TYPE_BCM283X "bcm283x" | 26 | |
| 31 | +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) | 27 | #define MSF2_TIMER_BASE 0x40004000 |
| 32 | 28 | @@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; | |
| 33 | -#define BCM2836_NCPUS 4 | 29 | static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; |
| 34 | +#define BCM283X_NCPUS 4 | 30 | static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; |
| 35 | 31 | ||
| 36 | -typedef struct BCM2836State { | 32 | -static void do_sys_reset(void *opaque, int n, int level) |
| 37 | +typedef struct BCM283XState { | 33 | -{ |
| 38 | /*< private >*/ | 34 | - if (level) { |
| 39 | DeviceState parent_obj; | 35 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 40 | /*< public >*/ | 36 | - } |
| 41 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State { | 37 | -} |
| 42 | char *cpu_type; | 38 | - |
| 43 | uint32_t enabled_cpus; | 39 | static void m2sxxx_soc_initfn(Object *obj) |
| 44 | 40 | { | |
| 45 | - ARMCPU cpus[BCM2836_NCPUS]; | 41 | MSF2State *s = MSF2_SOC(obj); |
| 46 | + ARMCPU cpus[BCM283X_NCPUS]; | 42 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) |
| 47 | BCM2836ControlState control; | 43 | return; |
| 48 | BCM2835PeripheralState peripherals; | 44 | } |
| 49 | -} BCM2836State; | 45 | |
| 50 | +} BCM283XState; | 46 | - qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, |
| 51 | 47 | - qemu_allocate_irq(&do_sys_reset, NULL, 0)); | |
| 52 | #endif /* BCM2836_H */ | 48 | - |
| 53 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 49 | system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; |
| 50 | |||
| 51 | for (i = 0; i < MSF2_NUM_UARTS; i++) { | ||
| 52 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | 53 | index XXXXXXX..XXXXXXX 100644 |
| 55 | --- a/hw/arm/bcm2836.c | 54 | --- a/hw/arm/stellaris.c |
| 56 | +++ b/hw/arm/bcm2836.c | 55 | +++ b/hw/arm/stellaris.c |
| 57 | @@ -XXX,XX +XXX,XX @@ | 56 | @@ -XXX,XX +XXX,XX @@ |
| 58 | 57 | #include "hw/boards.h" | |
| 59 | static void bcm2836_init(Object *obj) | 58 | #include "qemu/log.h" |
| 60 | { | 59 | #include "exec/address-spaces.h" |
| 61 | - BCM2836State *s = BCM2836(obj); | 60 | -#include "sysemu/runstate.h" |
| 62 | + BCM283XState *s = BCM283X(obj); | 61 | #include "sysemu/sysemu.h" |
| 63 | 62 | #include "hw/arm/armv7m.h" | |
| 64 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | 63 | #include "hw/char/pl011.h" |
| 65 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | 64 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj) |
| 66 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) | 65 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); |
| 67 | |||
| 68 | static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 69 | { | ||
| 70 | - BCM2836State *s = BCM2836(dev); | ||
| 71 | + BCM283XState *s = BCM283X(dev); | ||
| 72 | Object *obj; | ||
| 73 | Error *err = NULL; | ||
| 74 | int n; | ||
| 75 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 76 | /* common peripherals from bcm2835 */ | ||
| 77 | |||
| 78 | obj = OBJECT(dev); | ||
| 79 | - for (n = 0; n < BCM2836_NCPUS; n++) { | ||
| 80 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 81 | object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
| 82 | s->cpu_type); | ||
| 83 | object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
| 84 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 85 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | ||
| 86 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | ||
| 87 | |||
| 88 | - for (n = 0; n < BCM2836_NCPUS; n++) { | ||
| 89 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 90 | /* Mirror bcm2836, which has clusterid set to 0xf | ||
| 91 | * TODO: this should be converted to a property of ARM_CPU | ||
| 92 | */ | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 94 | } | 66 | } |
| 95 | 67 | ||
| 96 | static Property bcm2836_props[] = { | 68 | -static |
| 97 | - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), | 69 | -void do_sys_reset(void *opaque, int n, int level) |
| 98 | - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), | 70 | -{ |
| 99 | + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), | 71 | - if (level) { |
| 100 | + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, | 72 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 101 | + BCM283X_NCPUS), | 73 | - } |
| 102 | DEFINE_PROP_END_OF_LIST() | 74 | -} |
| 103 | }; | 75 | - |
| 104 | 76 | /* Board init. */ | |
| 105 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) | 77 | static stellaris_board_info stellaris_boards[] = { |
| 106 | } | 78 | { "LM3S811EVB", |
| 107 | 79 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | |
| 108 | static const TypeInfo bcm2836_type_info = { | 80 | /* This will exit with an error if the user passed us a bad cpu_type */ |
| 109 | - .name = TYPE_BCM2836, | 81 | sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); |
| 110 | + .name = TYPE_BCM283X, | 82 | |
| 111 | .parent = TYPE_DEVICE, | 83 | - qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, |
| 112 | - .instance_size = sizeof(BCM2836State), | 84 | - qemu_allocate_irq(&do_sys_reset, NULL, 0)); |
| 113 | + .instance_size = sizeof(BCM283XState), | 85 | - |
| 114 | .instance_init = bcm2836_init, | 86 | if (board->dc1 & (1 << 16)) { |
| 115 | .class_init = bcm2836_class_init, | 87 | dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, |
| 116 | }; | 88 | qdev_get_gpio_in(nvic, 14), |
| 117 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 118 | index XXXXXXX..XXXXXXX 100644 | ||
| 119 | --- a/hw/arm/raspi.c | ||
| 120 | +++ b/hw/arm/raspi.c | ||
| 121 | @@ -XXX,XX +XXX,XX @@ | ||
| 122 | static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | ||
| 123 | |||
| 124 | typedef struct RasPiState { | ||
| 125 | - BCM2836State soc; | ||
| 126 | + BCM283XState soc; | ||
| 127 | MemoryRegion ram; | ||
| 128 | } RasPiState; | ||
| 129 | |||
| 130 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
| 131 | BusState *bus; | ||
| 132 | DeviceState *carddev; | ||
| 133 | |||
| 134 | - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); | ||
| 135 | + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); | ||
| 136 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), | ||
| 137 | &error_abort); | ||
| 138 | |||
| 139 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | ||
| 140 | mc->no_floppy = 1; | ||
| 141 | mc->no_cdrom = 1; | ||
| 142 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | ||
| 143 | - mc->max_cpus = BCM2836_NCPUS; | ||
| 144 | - mc->min_cpus = BCM2836_NCPUS; | ||
| 145 | - mc->default_cpus = BCM2836_NCPUS; | ||
| 146 | + mc->max_cpus = BCM283X_NCPUS; | ||
| 147 | + mc->min_cpus = BCM283X_NCPUS; | ||
| 148 | + mc->default_cpus = BCM283X_NCPUS; | ||
| 149 | mc->default_ram_size = 1024 * 1024 * 1024; | ||
| 150 | mc->ignore_memory_transaction_failures = true; | ||
| 151 | }; | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) | ||
| 153 | mc->no_floppy = 1; | ||
| 154 | mc->no_cdrom = 1; | ||
| 155 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); | ||
| 156 | - mc->max_cpus = BCM2836_NCPUS; | ||
| 157 | - mc->min_cpus = BCM2836_NCPUS; | ||
| 158 | - mc->default_cpus = BCM2836_NCPUS; | ||
| 159 | + mc->max_cpus = BCM283X_NCPUS; | ||
| 160 | + mc->min_cpus = BCM283X_NCPUS; | ||
| 161 | + mc->default_cpus = BCM283X_NCPUS; | ||
| 162 | mc->default_ram_size = 1024 * 1024 * 1024; | ||
| 163 | } | ||
| 164 | DEFINE_MACHINE("raspi3", raspi3_machine_init) | ||
| 165 | -- | 89 | -- |
| 166 | 2.16.2 | 90 | 2.20.1 |
| 167 | 91 | ||
| 168 | 92 | diff view generated by jsdifflib |
| 1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The sabrelite machine model used by qemu-system-arm is based on the | 3 | The definition of top_bit used in this function is one higher |
| 4 | Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet | 4 | than that used in the Arm ARM psuedo-code, which put the error |
| 5 | controller which is supported in QEMU using the imx_fec.c module | 5 | indication at top_bit - 1 at the wrong place, which meant that |
| 6 | (actually called imx.enet for this model.) | 6 | it wasn't visible to Auth. |
| 7 | 7 | ||
| 8 | The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the | 8 | Fixing the definition of top_bit requires more changes, because |
| 9 | imx.enet device like this: | 9 | its most common use is for the count of bits in top_bit:bot_bit, |
| 10 | which would then need to be computed as top_bit - bot_bit + 1. | ||
| 10 | 11 | ||
| 11 | #define FSL_IMX6_ENET_MAC_1588_IRQ 118 | 12 | For now, prefer the minimal fix to the error indication alone. |
| 12 | #define FSL_IMX6_ENET_MAC_IRQ 119 | ||
| 13 | 13 | ||
| 14 | According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf, | 14 | Fixes: 63ff0ca94cb |
| 15 | page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary, | 15 | Reported-by: Derrick McKee <derrick.mckee@gmail.com> |
| 16 | interrupts are as follows. | 16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 17 | 17 | Message-id: 20200728195706.11087-1-richard.henderson@linaro.org | |
| 18 | 150 ENET MAC 0 IRQ | ||
| 19 | 151 ENET MAC 0 1588 Timer interrupt | ||
| 20 | |||
| 21 | where | ||
| 22 | |||
| 23 | 150 - 32 == 118 | ||
| 24 | 151 - 32 == 119 | ||
| 25 | |||
| 26 | In other words, the vector definitions in the fsl-imx6.h file are reversed. | ||
| 27 | |||
| 28 | Fixing the interrupts alone causes problems with older Linux kernels: | ||
| 29 | The Ethernet interface will fail to probe with Linux v4.9 and earlier. | ||
| 30 | Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe | ||
| 31 | error handling. This is a Linux kernel problem, not a qemu problem: | ||
| 32 | the Linux kernel only worked by accident since it requested both interrupts. | ||
| 33 | |||
| 34 | For backward compatibility, generate the Ethernet interrupt on both interrupt | ||
| 35 | lines. This was shown to work from all Linux kernel releases starting with | ||
| 36 | v3.16. | ||
| 37 | |||
| 38 | Link: https://bugs.launchpad.net/qemu/+bug/1753309 | ||
| 39 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
| 40 | Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net | ||
| 41 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 19 | [PMM: added comment about the divergence from the pseudocode] | ||
| 42 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 43 | --- | 21 | --- |
| 44 | include/hw/arm/fsl-imx6.h | 4 ++-- | 22 | target/arm/pauth_helper.c | 6 +++++- |
| 45 | hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++- | 23 | tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++ |
| 46 | 2 files changed, 29 insertions(+), 3 deletions(-) | 24 | tests/tcg/aarch64/Makefile.target | 2 +- |
| 25 | 3 files changed, 39 insertions(+), 2 deletions(-) | ||
| 26 | create mode 100644 tests/tcg/aarch64/pauth-5.c | ||
| 47 | 27 | ||
| 48 | diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h | 28 | diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c |
| 49 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
| 50 | --- a/include/hw/arm/fsl-imx6.h | 30 | --- a/target/arm/pauth_helper.c |
| 51 | +++ b/include/hw/arm/fsl-imx6.h | 31 | +++ b/target/arm/pauth_helper.c |
| 52 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State { | 32 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, |
| 53 | #define FSL_IMX6_HDMI_MASTER_IRQ 115 | 33 | */ |
| 54 | #define FSL_IMX6_HDMI_CEC_IRQ 116 | 34 | test = sextract64(ptr, bot_bit, top_bit - bot_bit); |
| 55 | #define FSL_IMX6_MLB150_LOW_IRQ 117 | 35 | if (test != 0 && test != -1) { |
| 56 | -#define FSL_IMX6_ENET_MAC_1588_IRQ 118 | 36 | - pac ^= MAKE_64BIT_MASK(top_bit - 1, 1); |
| 57 | -#define FSL_IMX6_ENET_MAC_IRQ 119 | 37 | + /* |
| 58 | +#define FSL_IMX6_ENET_MAC_IRQ 118 | 38 | + * Note that our top_bit is one greater than the pseudocode's |
| 59 | +#define FSL_IMX6_ENET_MAC_1588_IRQ 119 | 39 | + * version, hence "- 2" here. |
| 60 | #define FSL_IMX6_PCIE1_IRQ 120 | 40 | + */ |
| 61 | #define FSL_IMX6_PCIE2_IRQ 121 | 41 | + pac ^= MAKE_64BIT_MASK(top_bit - 2, 1); |
| 62 | #define FSL_IMX6_PCIE3_IRQ 122 | 42 | } |
| 63 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | 43 | |
| 44 | /* | ||
| 45 | diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c | ||
| 46 | new file mode 100644 | ||
| 47 | index XXXXXXX..XXXXXXX | ||
| 48 | --- /dev/null | ||
| 49 | +++ b/tests/tcg/aarch64/pauth-5.c | ||
| 50 | @@ -XXX,XX +XXX,XX @@ | ||
| 51 | +#include <assert.h> | ||
| 52 | + | ||
| 53 | +static int x; | ||
| 54 | + | ||
| 55 | +int main() | ||
| 56 | +{ | ||
| 57 | + int *p0 = &x, *p1, *p2, *p3; | ||
| 58 | + unsigned long salt = 0; | ||
| 59 | + | ||
| 60 | + /* | ||
| 61 | + * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so | ||
| 62 | + * a 1/128 chance of auth = pac(ptr,key,salt) producing zero. | ||
| 63 | + * Find a salt that creates auth != 0. | ||
| 64 | + */ | ||
| 65 | + do { | ||
| 66 | + salt++; | ||
| 67 | + asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0)); | ||
| 68 | + } while (p0 == p1); | ||
| 69 | + | ||
| 70 | + /* | ||
| 71 | + * This pac must fail, because the input pointer bears an encryption, | ||
| 72 | + * and so is not properly extended within bits [55:47]. This will | ||
| 73 | + * toggle bit 54 in the output... | ||
| 74 | + */ | ||
| 75 | + asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1)); | ||
| 76 | + | ||
| 77 | + /* ... so that the aut must fail, setting bit 53 in the output ... */ | ||
| 78 | + asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2)); | ||
| 79 | + | ||
| 80 | + /* ... which means this equality must not hold. */ | ||
| 81 | + assert(p3 != p0); | ||
| 82 | + return 0; | ||
| 83 | +} | ||
| 84 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
| 64 | index XXXXXXX..XXXXXXX 100644 | 85 | index XXXXXXX..XXXXXXX 100644 |
| 65 | --- a/hw/net/imx_fec.c | 86 | --- a/tests/tcg/aarch64/Makefile.target |
| 66 | +++ b/hw/net/imx_fec.c | 87 | +++ b/tests/tcg/aarch64/Makefile.target |
| 67 | @@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) | 88 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt |
| 68 | 89 | ||
| 69 | static void imx_eth_update(IMXFECState *s) | 90 | # Pauth Tests |
| 70 | { | 91 | ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),) |
| 71 | - if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) { | 92 | -AARCH64_TESTS += pauth-1 pauth-2 pauth-4 |
| 72 | + /* | 93 | +AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5 |
| 73 | + * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER | 94 | pauth-%: CFLAGS += -march=armv8.3-a |
| 74 | + * interrupts swapped. This worked with older versions of Linux (4.14 | 95 | run-pauth-%: QEMU_OPTS += -cpu max |
| 75 | + * and older) since Linux associated both interrupt lines with Ethernet | 96 | run-plugin-pauth-%: QEMU_OPTS += -cpu max |
| 76 | + * MAC interrupts. Specifically, | ||
| 77 | + * - Linux 4.15 and later have separate interrupt handlers for the MAC and | ||
| 78 | + * timer interrupts. Those versions of Linux fail with versions of QEMU | ||
| 79 | + * with swapped interrupt assignments. | ||
| 80 | + * - In linux 4.14, both interrupt lines were registered with the Ethernet | ||
| 81 | + * MAC interrupt handler. As a result, all versions of qemu happen to | ||
| 82 | + * work, though that is accidental. | ||
| 83 | + * - In Linux 4.9 and older, the timer interrupt was registered directly | ||
| 84 | + * with the Ethernet MAC interrupt handler. The MAC interrupt was | ||
| 85 | + * redirected to a GPIO interrupt to work around erratum ERR006687. | ||
| 86 | + * This was implemented using the SOC's IOMUX block. In qemu, this GPIO | ||
| 87 | + * interrupt never fired since IOMUX is currently not supported in qemu. | ||
| 88 | + * Linux instead received MAC interrupts on the timer interrupt. | ||
| 89 | + * As a result, qemu versions with the swapped interrupt assignment work, | ||
| 90 | + * albeit accidentally, but qemu versions with the correct interrupt | ||
| 91 | + * assignment fail. | ||
| 92 | + * | ||
| 93 | + * To ensure that all versions of Linux work, generate ENET_INT_MAC | ||
| 94 | + * interrrupts on both interrupt lines. This should be changed if and when | ||
| 95 | + * qemu supports IOMUX. | ||
| 96 | + */ | ||
| 97 | + if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & | ||
| 98 | + (ENET_INT_MAC | ENET_INT_TS_TIMER)) { | ||
| 99 | qemu_set_irq(s->irq[1], 1); | ||
| 100 | } else { | ||
| 101 | qemu_set_irq(s->irq[1], 0); | ||
| 102 | -- | 97 | -- |
| 103 | 2.16.2 | 98 | 2.20.1 |
| 104 | 99 | ||
| 105 | 100 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Wei Huang <wei@redhat.com> | ||
| 2 | 1 | ||
| 3 | For guest kernel that supports KASLR, the load address can change every | ||
| 4 | time when guest VM runs. To find the physical base address correctly, | ||
| 5 | current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=". | ||
| 6 | However this string pattern is only available on x86_64. AArch64 uses a | ||
| 7 | different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure | ||
| 8 | QEMU dump uses the correct string on AArch64. | ||
| 9 | |||
| 10 | Signed-off-by: Wei Huang <wei@redhat.com> | ||
| 11 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> | ||
| 12 | Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | dump.c | 14 +++++++++++--- | ||
| 16 | 1 file changed, 11 insertions(+), 3 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/dump.c b/dump.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/dump.c | ||
| 21 | +++ b/dump.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s) | ||
| 23 | |||
| 24 | lines = g_strsplit((char *)vmci, "\n", -1); | ||
| 25 | for (i = 0; lines[i]; i++) { | ||
| 26 | - if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) { | ||
| 27 | - if (qemu_strtou64(lines[i] + 18, NULL, 16, | ||
| 28 | + const char *prefix = NULL; | ||
| 29 | + | ||
| 30 | + if (s->dump_info.d_machine == EM_X86_64) { | ||
| 31 | + prefix = "NUMBER(phys_base)="; | ||
| 32 | + } else if (s->dump_info.d_machine == EM_AARCH64) { | ||
| 33 | + prefix = "NUMBER(PHYS_OFFSET)="; | ||
| 34 | + } | ||
| 35 | + | ||
| 36 | + if (prefix && g_str_has_prefix(lines[i], prefix)) { | ||
| 37 | + if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16, | ||
| 38 | &phys_base) < 0) { | ||
| 39 | - warn_report("Failed to read NUMBER(phys_base)="); | ||
| 40 | + warn_report("Failed to read %s", prefix); | ||
| 41 | } else { | ||
| 42 | s->dump_info.phys_base = phys_base; | ||
| 43 | } | ||
| 44 | -- | ||
| 45 | 2.16.2 | ||
| 46 | |||
| 47 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 2 | 1 | ||
| 3 | Code of imx_update() is slightly confusing since the "flags" variable | ||
| 4 | doesn't really corespond to anything in real hardware and server as a | ||
| 5 | kitchensink accumulating events normally reported via USR1 and USR2 | ||
| 6 | registers. | ||
| 7 | |||
| 8 | Change the code to explicitly evaluate state of interrupts reported | ||
| 9 | via USR1 and USR2 against corresponding masking bits and use the to | ||
| 10 | detemine if IRQ line should be asserted or not. | ||
| 11 | |||
| 12 | NOTE: Check for UTS1_TXEMPTY being set has been dropped for two | ||
| 13 | reasons: | ||
| 14 | |||
| 15 | 1. Emulation code implements a single character FIFO, so this flag | ||
| 16 | will always be set since characters are trasmitted as a part of | ||
| 17 | the code emulating "push" into the FIFO | ||
| 18 | |||
| 19 | 2. imx_update() is really just a function doing ORing and maksing | ||
| 20 | of reported events, so checking for UTS1_TXEMPTY should happen, | ||
| 21 | if it's ever really needed should probably happen outside of | ||
| 22 | it. | ||
| 23 | |||
| 24 | Cc: qemu-devel@nongnu.org | ||
| 25 | Cc: qemu-arm@nongnu.org | ||
| 26 | Cc: Bill Paul <wpaul@windriver.com> | ||
| 27 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 28 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 29 | Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com | ||
| 30 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 32 | --- | ||
| 33 | hw/char/imx_serial.c | 24 ++++++++++++++++-------- | ||
| 34 | 1 file changed, 16 insertions(+), 8 deletions(-) | ||
| 35 | |||
| 36 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/hw/char/imx_serial.c | ||
| 39 | +++ b/hw/char/imx_serial.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { | ||
| 41 | |||
| 42 | static void imx_update(IMXSerialState *s) | ||
| 43 | { | ||
| 44 | - uint32_t flags; | ||
| 45 | + uint32_t usr1; | ||
| 46 | + uint32_t usr2; | ||
| 47 | + uint32_t mask; | ||
| 48 | |||
| 49 | - flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); | ||
| 50 | - if (s->ucr1 & UCR1_TXMPTYEN) { | ||
| 51 | - flags |= (s->uts1 & UTS1_TXEMPTY); | ||
| 52 | - } else { | ||
| 53 | - flags &= ~USR1_TRDY; | ||
| 54 | - } | ||
| 55 | + /* | ||
| 56 | + * Lucky for us TRDY and RRDY has the same offset in both USR1 and | ||
| 57 | + * UCR1, so we can get away with something as simple as the | ||
| 58 | + * following: | ||
| 59 | + */ | ||
| 60 | + usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); | ||
| 61 | + /* | ||
| 62 | + * Bits that we want in USR2 are not as conveniently laid out, | ||
| 63 | + * unfortunately. | ||
| 64 | + */ | ||
| 65 | + mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | ||
| 66 | + usr2 = s->usr2 & mask; | ||
| 67 | |||
| 68 | - qemu_set_irq(s->irq, !!flags); | ||
| 69 | + qemu_set_irq(s->irq, usr1 || usr2); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void imx_serial_reset(IMXSerialState *s) | ||
| 73 | -- | ||
| 74 | 2.16.2 | ||
| 75 | |||
| 76 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 2 | 1 | ||
| 3 | Add support for "TX complete"/TXDC interrupt generate by real HW since | ||
| 4 | it is needed to support guests other than Linux. | ||
| 5 | |||
| 6 | Based on the patch by Bill Paul as found here: | ||
| 7 | https://bugs.launchpad.net/qemu/+bug/1753314 | ||
| 8 | |||
| 9 | Cc: qemu-devel@nongnu.org | ||
| 10 | Cc: qemu-arm@nongnu.org | ||
| 11 | Cc: Bill Paul <wpaul@windriver.com> | ||
| 12 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Signed-off-by: Bill Paul <wpaul@windriver.com> | ||
| 14 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 15 | Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com | ||
| 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | --- | ||
| 19 | include/hw/char/imx_serial.h | 3 +++ | ||
| 20 | hw/char/imx_serial.c | 20 +++++++++++++++++--- | ||
| 21 | 2 files changed, 20 insertions(+), 3 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/include/hw/char/imx_serial.h | ||
| 26 | +++ b/include/hw/char/imx_serial.h | ||
| 27 | @@ -XXX,XX +XXX,XX @@ | ||
| 28 | #define UCR2_RXEN (1<<1) /* Receiver enable */ | ||
| 29 | #define UCR2_SRST (1<<0) /* Reset complete */ | ||
| 30 | |||
| 31 | +#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ | ||
| 32 | + | ||
| 33 | #define UTS1_TXEMPTY (1<<6) | ||
| 34 | #define UTS1_RXEMPTY (1<<5) | ||
| 35 | #define UTS1_TXFULL (1<<4) | ||
| 36 | @@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState { | ||
| 37 | uint32_t ubmr; | ||
| 38 | uint32_t ubrc; | ||
| 39 | uint32_t ucr3; | ||
| 40 | + uint32_t ucr4; | ||
| 41 | |||
| 42 | qemu_irq irq; | ||
| 43 | CharBackend chr; | ||
| 44 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | ||
| 45 | index XXXXXXX..XXXXXXX 100644 | ||
| 46 | --- a/hw/char/imx_serial.c | ||
| 47 | +++ b/hw/char/imx_serial.c | ||
| 48 | @@ -XXX,XX +XXX,XX @@ | ||
| 49 | |||
| 50 | static const VMStateDescription vmstate_imx_serial = { | ||
| 51 | .name = TYPE_IMX_SERIAL, | ||
| 52 | - .version_id = 1, | ||
| 53 | - .minimum_version_id = 1, | ||
| 54 | + .version_id = 2, | ||
| 55 | + .minimum_version_id = 2, | ||
| 56 | .fields = (VMStateField[]) { | ||
| 57 | VMSTATE_INT32(readbuff, IMXSerialState), | ||
| 58 | VMSTATE_UINT32(usr1, IMXSerialState), | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { | ||
| 60 | VMSTATE_UINT32(ubmr, IMXSerialState), | ||
| 61 | VMSTATE_UINT32(ubrc, IMXSerialState), | ||
| 62 | VMSTATE_UINT32(ucr3, IMXSerialState), | ||
| 63 | + VMSTATE_UINT32(ucr4, IMXSerialState), | ||
| 64 | VMSTATE_END_OF_LIST() | ||
| 65 | }, | ||
| 66 | }; | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s) | ||
| 68 | * unfortunately. | ||
| 69 | */ | ||
| 70 | mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | ||
| 71 | + /* | ||
| 72 | + * TCEN and TXDC are both bit 3 | ||
| 73 | + */ | ||
| 74 | + mask |= s->ucr4 & UCR4_TCEN; | ||
| 75 | + | ||
| 76 | usr2 = s->usr2 & mask; | ||
| 77 | |||
| 78 | qemu_set_irq(s->irq, usr1 || usr2); | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, | ||
| 80 | return s->ucr3; | ||
| 81 | |||
| 82 | case 0x23: /* UCR4 */ | ||
| 83 | + return s->ucr4; | ||
| 84 | + | ||
| 85 | case 0x29: /* BRM Incremental */ | ||
| 86 | return 0x0; /* TODO */ | ||
| 87 | |||
| 88 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, | ||
| 89 | * qemu_chr_fe_write and background I/O callbacks */ | ||
| 90 | qemu_chr_fe_write_all(&s->chr, &ch, 1); | ||
| 91 | s->usr1 &= ~USR1_TRDY; | ||
| 92 | + s->usr2 &= ~USR2_TXDC; | ||
| 93 | imx_update(s); | ||
| 94 | s->usr1 |= USR1_TRDY; | ||
| 95 | + s->usr2 |= USR2_TXDC; | ||
| 96 | imx_update(s); | ||
| 97 | } | ||
| 98 | break; | ||
| 99 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, | ||
| 100 | s->ucr3 = value & 0xffff; | ||
| 101 | break; | ||
| 102 | |||
| 103 | - case 0x2d: /* UTS1 */ | ||
| 104 | case 0x23: /* UCR4 */ | ||
| 105 | + s->ucr4 = value & 0xffff; | ||
| 106 | + imx_update(s); | ||
| 107 | + break; | ||
| 108 | + | ||
| 109 | + case 0x2d: /* UTS1 */ | ||
| 110 | qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" | ||
| 111 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); | ||
| 112 | /* TODO */ | ||
| 113 | -- | ||
| 114 | 2.16.2 | ||
| 115 | |||
| 116 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | For the rpi1 and 2 we want to boot the Linux kernel via some | ||
| 2 | custom setup code that makes sure that the SMC instruction | ||
| 3 | acts as a no-op, because it's used for cache maintenance. | ||
| 4 | The rpi3 boots AArch64 kernels, which don't need SMC for | ||
| 5 | cache maintenance and always expect to be booted non-secure. | ||
| 6 | Don't fill in the aarch32-specific parts of the binfo struct. | ||
| 7 | 1 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 11 | Message-id: 20180313153458.26822-2-peter.maydell@linaro.org | ||
| 12 | --- | ||
| 13 | hw/arm/raspi.c | 17 +++++++++++++---- | ||
| 14 | 1 file changed, 13 insertions(+), 4 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/arm/raspi.c | ||
| 19 | +++ b/hw/arm/raspi.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
| 21 | binfo.board_id = raspi_boardid[version]; | ||
| 22 | binfo.ram_size = ram_size; | ||
| 23 | binfo.nb_cpus = smp_cpus; | ||
| 24 | - binfo.board_setup_addr = BOARDSETUP_ADDR; | ||
| 25 | - binfo.write_board_setup = write_board_setup; | ||
| 26 | - binfo.secure_board_setup = true; | ||
| 27 | - binfo.secure_boot = true; | ||
| 28 | + | ||
| 29 | + if (version <= 2) { | ||
| 30 | + /* The rpi1 and 2 require some custom setup code to run in Secure | ||
| 31 | + * mode before booting a kernel (to set up the SMC vectors so | ||
| 32 | + * that we get a no-op SMC; this is used by Linux to call the | ||
| 33 | + * firmware for some cache maintenance operations. | ||
| 34 | + * The rpi3 doesn't need this. | ||
| 35 | + */ | ||
| 36 | + binfo.board_setup_addr = BOARDSETUP_ADDR; | ||
| 37 | + binfo.write_board_setup = write_board_setup; | ||
| 38 | + binfo.secure_board_setup = true; | ||
| 39 | + binfo.secure_boot = true; | ||
| 40 | + } | ||
| 41 | |||
| 42 | /* Pi2 and Pi3 requires SMP setup */ | ||
| 43 | if (version >= 2) { | ||
| 44 | -- | ||
| 45 | 2.16.2 | ||
| 46 | |||
| 47 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Add some assertions that if we're about to boot an AArch64 kernel, | ||
| 2 | the board code has not mistakenly set either secure_boot or | ||
| 3 | secure_board_setup. It doesn't make sense to set secure_boot, | ||
| 4 | because all AArch64 kernels must be booted in non-secure mode. | ||
| 5 | 1 | ||
| 6 | It might in theory make sense to set secure_board_setup, but | ||
| 7 | we don't currently support that, because only the AArch32 | ||
| 8 | bootloader[] code calls this hook; bootloader_aarch64[] does not. | ||
| 9 | Since we don't have a current need for this functionality, just | ||
| 10 | assert that we don't try to use it. If it's needed we'll add | ||
| 11 | it later. | ||
| 12 | |||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 15 | Message-id: 20180313153458.26822-3-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | hw/arm/boot.c | 7 +++++++ | ||
| 18 | 1 file changed, 7 insertions(+) | ||
| 19 | |||
| 20 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/hw/arm/boot.c | ||
| 23 | +++ b/hw/arm/boot.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
| 25 | } else { | ||
| 26 | env->pstate = PSTATE_MODE_EL1h; | ||
| 27 | } | ||
| 28 | + /* AArch64 kernels never boot in secure mode */ | ||
| 29 | + assert(!info->secure_boot); | ||
| 30 | + /* This hook is only supported for AArch32 currently: | ||
| 31 | + * bootloader_aarch64[] will not call the hook, and | ||
| 32 | + * the code above has already dropped us into EL2 or EL1. | ||
| 33 | + */ | ||
| 34 | + assert(!info->secure_board_setup); | ||
| 35 | } | ||
| 36 | |||
| 37 | /* Set to non-secure if not a secure boot */ | ||
| 38 | -- | ||
| 39 | 2.16.2 | ||
| 40 | |||
| 41 | diff view generated by jsdifflib |
| 1 | The TypeInfo and state struct for bcm2386 disagree about what the | 1 | From: Kaige Li <likaige@loongson.cn> |
|---|---|---|---|
| 2 | parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, | ||
| 3 | but the BCM2386State struct only defines the parent_obj field | ||
| 4 | as DeviceState. This would have caused problems if anything | ||
| 5 | actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. | ||
| 6 | Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't | ||
| 7 | need any of the additional functionality TYPE_SYS_BUS_DEVICE | ||
| 8 | provides. | ||
| 9 | 2 | ||
| 3 | GCC version 4.9.4 isn't clever enough to figure out that all | ||
| 4 | execution paths in disas_ldst() that use 'fn' will have initialized | ||
| 5 | it first, and so it warns: | ||
| 6 | |||
| 7 | /home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’: | ||
| 8 | /home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized] | ||
| 9 | fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), | ||
| 10 | ^ | ||
| 11 | /home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here | ||
| 12 | AtomicThreeOpFn *fn; | ||
| 13 | ^ | ||
| 14 | |||
| 15 | Make it happy by initializing the variable to NULL. | ||
| 16 | |||
| 17 | Signed-off-by: Kaige Li <likaige@loongson.cn> | ||
| 18 | Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn | ||
| 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 20 | [PMM: Clean up commit message and note which gcc version this was] | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 13 | Message-id: 20180313153458.26822-5-peter.maydell@linaro.org | ||
| 14 | --- | 22 | --- |
| 15 | hw/arm/bcm2836.c | 2 +- | 23 | target/arm/translate-a64.c | 2 +- |
| 16 | 1 file changed, 1 insertion(+), 1 deletion(-) | 24 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 17 | 25 | ||
| 18 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 26 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/hw/arm/bcm2836.c | 28 | --- a/target/arm/translate-a64.c |
| 21 | +++ b/hw/arm/bcm2836.c | 29 | +++ b/target/arm/translate-a64.c |
| 22 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) | 30 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, |
| 23 | 31 | bool r = extract32(insn, 22, 1); | |
| 24 | static const TypeInfo bcm2836_type_info = { | 32 | bool a = extract32(insn, 23, 1); |
| 25 | .name = TYPE_BCM2836, | 33 | TCGv_i64 tcg_rs, clean_addr; |
| 26 | - .parent = TYPE_SYS_BUS_DEVICE, | 34 | - AtomicThreeOpFn *fn; |
| 27 | + .parent = TYPE_DEVICE, | 35 | + AtomicThreeOpFn *fn = NULL; |
| 28 | .instance_size = sizeof(BCM2836State), | 36 | |
| 29 | .instance_init = bcm2836_init, | 37 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { |
| 30 | .class_init = bcm2836_class_init, | 38 | unallocated_encoding(s); |
| 31 | -- | 39 | -- |
| 32 | 2.16.2 | 40 | 2.20.1 |
| 33 | 41 | ||
| 34 | 42 | diff view generated by jsdifflib |
| 1 | If we're directly booting a Linux kernel and the CPU supports both | 1 | The nrf51 SoC model wasn't setting the system_clock_scale |
|---|---|---|---|
| 2 | EL3 and EL2, we start the kernel in EL2, as it expects. We must also | 2 | global.which meant that if guest code used the systick timer in "use |
| 3 | set the SCR_EL3.HCE bit in this situation, so that the HVC | 3 | the processor clock" mode it would hang because time never advances. |
| 4 | instruction is enabled rather than UNDEFing. Otherwise at least some | 4 | |
| 5 | kernels will panic when trying to initialize KVM in the guest. | 5 | Set the global to match the documented CPU clock speed for this SoC. |
| 6 | |||
| 7 | This SoC in fact doesn't have a SysTick timer (which is the only thing | ||
| 8 | currently that cares about the system_clock_scale), because it's | ||
| 9 | a configurable option in the Cortex-M0. However our Cortex-M0 and | ||
| 10 | thus our nrf51 and our micro:bit board do provide a SysTick, so | ||
| 11 | we ought to provide a functional one rather than a broken one. | ||
| 6 | 12 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Message-id: 20180313153458.26822-4-peter.maydell@linaro.org | 14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 15 | Message-id: 20200727193458.31250-1-peter.maydell@linaro.org | ||
| 9 | --- | 16 | --- |
| 10 | hw/arm/boot.c | 5 +++++ | 17 | hw/arm/nrf51_soc.c | 5 +++++ |
| 11 | 1 file changed, 5 insertions(+) | 18 | 1 file changed, 5 insertions(+) |
| 12 | 19 | ||
| 13 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 20 | diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/arm/boot.c | 22 | --- a/hw/arm/nrf51_soc.c |
| 16 | +++ b/hw/arm/boot.c | 23 | +++ b/hw/arm/nrf51_soc.c |
| 17 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | 24 | @@ -XXX,XX +XXX,XX @@ |
| 18 | assert(!info->secure_board_setup); | 25 | |
| 19 | } | 26 | #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) |
| 20 | 27 | ||
| 21 | + if (arm_feature(env, ARM_FEATURE_EL2)) { | 28 | +/* HCLK (the main CPU clock) on this SoC is always 16MHz */ |
| 22 | + /* If we have EL2 then Linux expects the HVC insn to work */ | 29 | +#define HCLK_FRQ 16000000 |
| 23 | + env->cp15.scr_el3 |= SCR_HCE; | ||
| 24 | + } | ||
| 25 | + | 30 | + |
| 26 | /* Set to non-secure if not a secure boot */ | 31 | static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) |
| 27 | if (!info->secure_boot && | 32 | { |
| 28 | (cs != first_cpu || !info->secure_board_setup)) { | 33 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", |
| 34 | @@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) | ||
| 35 | return; | ||
| 36 | } | ||
| 37 | |||
| 38 | + system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ; | ||
| 39 | + | ||
| 40 | object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), | ||
| 41 | &error_abort); | ||
| 42 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { | ||
| 29 | -- | 43 | -- |
| 30 | 2.16.2 | 44 | 2.20.1 |
| 31 | 45 | ||
| 32 | 46 | diff view generated by jsdifflib |
| 1 | The bcm2837 is pretty similar to the bcm2836, but it does have | 1 | The imx_epit device has a software-controllable reset triggered by |
|---|---|---|---|
| 2 | some differences. Notably, the MPIDR affinity aff1 values it | 2 | setting the SWR bit in the CR register. An error in commit cc2722ec83ad9 |
| 3 | sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 | 3 | means that we will end up assert()ing if the guest does this, because |
| 4 | uses, and if this is wrong Linux will not boot. | 4 | the code in imx_epit_write() starts ptimer transactions, and then |
| 5 | imx_epit_reset() also starts ptimer transactions, triggering | ||
| 6 | "ptimer_transaction_begin: Assertion `!s->in_transaction' failed". | ||
| 5 | 7 | ||
| 6 | Rather than trying to have one device with properties that | 8 | The cleanest way to avoid this double-transaction is to move the |
| 7 | configure it differently for the two cases, create two | 9 | start-transaction for the CR write handling down below the check of |
| 8 | separate QOM devices for the two SoCs. We use the same approach | 10 | the SWR bit. |
| 9 | as hw/arm/aspeed_soc.c and share code and have a data table | ||
| 10 | that might differ per-SoC. For the moment the two types don't | ||
| 11 | actually have different behaviour. | ||
| 12 | 11 | ||
| 12 | Fixes: https://bugs.launchpad.net/qemu/+bug/1880424 | ||
| 13 | Fixes: cc2722ec83ad944505fe | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 15 | Message-id: 20180313153458.26822-7-peter.maydell@linaro.org | 16 | Message-id: 20200727154550.3409-1-peter.maydell@linaro.org |
| 16 | --- | 17 | --- |
| 17 | include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ | 18 | hw/timer/imx_epit.c | 13 ++++++++++--- |
| 18 | hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- | 19 | 1 file changed, 10 insertions(+), 3 deletions(-) |
| 19 | hw/arm/raspi.c | 3 ++- | ||
| 20 | 3 files changed, 53 insertions(+), 6 deletions(-) | ||
| 21 | 20 | ||
| 22 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | 21 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c |
| 23 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/include/hw/arm/bcm2836.h | 23 | --- a/hw/timer/imx_epit.c |
| 25 | +++ b/include/hw/arm/bcm2836.h | 24 | +++ b/hw/timer/imx_epit.c |
| 26 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, |
| 27 | 26 | ||
| 28 | #define BCM283X_NCPUS 4 | 27 | switch (offset >> 2) { |
| 29 | 28 | case 0: /* CR */ | |
| 30 | +/* These type names are for specific SoCs; other than instantiating | 29 | - ptimer_transaction_begin(s->timer_cmp); |
| 31 | + * them, code using these devices should always handle them via the | 30 | - ptimer_transaction_begin(s->timer_reload); |
| 32 | + * BCM283x base class, so they have no BCM2836(obj) etc macros. | 31 | |
| 33 | + */ | 32 | oldcr = s->cr; |
| 34 | +#define TYPE_BCM2836 "bcm2836" | 33 | s->cr = value & 0x03ffffff; |
| 35 | +#define TYPE_BCM2837 "bcm2837" | 34 | if (s->cr & CR_SWR) { |
| 35 | /* handle the reset */ | ||
| 36 | imx_epit_reset(DEVICE(s)); | ||
| 37 | - } else { | ||
| 38 | + /* | ||
| 39 | + * TODO: could we 'break' here? following operations appear | ||
| 40 | + * to duplicate the work imx_epit_reset() already did. | ||
| 41 | + */ | ||
| 42 | + } | ||
| 36 | + | 43 | + |
| 37 | typedef struct BCM283XState { | 44 | + ptimer_transaction_begin(s->timer_cmp); |
| 38 | /*< private >*/ | 45 | + ptimer_transaction_begin(s->timer_reload); |
| 39 | DeviceState parent_obj; | ||
| 40 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState { | ||
| 41 | BCM2835PeripheralState peripherals; | ||
| 42 | } BCM283XState; | ||
| 43 | |||
| 44 | +typedef struct BCM283XInfo BCM283XInfo; | ||
| 45 | + | 46 | + |
| 46 | +typedef struct BCM283XClass { | 47 | + if (!(s->cr & CR_SWR)) { |
| 47 | + DeviceClass parent_class; | 48 | imx_epit_set_freq(s); |
| 48 | + const BCM283XInfo *info; | 49 | } |
| 49 | +} BCM283XClass; | ||
| 50 | + | ||
| 51 | +#define BCM283X_CLASS(klass) \ | ||
| 52 | + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) | ||
| 53 | +#define BCM283X_GET_CLASS(obj) \ | ||
| 54 | + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) | ||
| 55 | + | ||
| 56 | #endif /* BCM2836_H */ | ||
| 57 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
| 58 | index XXXXXXX..XXXXXXX 100644 | ||
| 59 | --- a/hw/arm/bcm2836.c | ||
| 60 | +++ b/hw/arm/bcm2836.c | ||
| 61 | @@ -XXX,XX +XXX,XX @@ | ||
| 62 | /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ | ||
| 63 | #define BCM2836_CONTROL_BASE 0x40000000 | ||
| 64 | |||
| 65 | +struct BCM283XInfo { | ||
| 66 | + const char *name; | ||
| 67 | +}; | ||
| 68 | + | ||
| 69 | +static const BCM283XInfo bcm283x_socs[] = { | ||
| 70 | + { | ||
| 71 | + .name = TYPE_BCM2836, | ||
| 72 | + }, | ||
| 73 | + { | ||
| 74 | + .name = TYPE_BCM2837, | ||
| 75 | + }, | ||
| 76 | +}; | ||
| 77 | + | ||
| 78 | static void bcm2836_init(Object *obj) | ||
| 79 | { | ||
| 80 | BCM283XState *s = BCM283X(obj); | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = { | ||
| 82 | DEFINE_PROP_END_OF_LIST() | ||
| 83 | }; | ||
| 84 | |||
| 85 | -static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
| 86 | +static void bcm283x_class_init(ObjectClass *oc, void *data) | ||
| 87 | { | ||
| 88 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 89 | + BCM283XClass *bc = BCM283X_CLASS(oc); | ||
| 90 | |||
| 91 | - dc->props = bcm2836_props; | ||
| 92 | + bc->info = data; | ||
| 93 | dc->realize = bcm2836_realize; | ||
| 94 | + dc->props = bcm2836_props; | ||
| 95 | } | ||
| 96 | |||
| 97 | -static const TypeInfo bcm2836_type_info = { | ||
| 98 | +static const TypeInfo bcm283x_type_info = { | ||
| 99 | .name = TYPE_BCM283X, | ||
| 100 | .parent = TYPE_DEVICE, | ||
| 101 | .instance_size = sizeof(BCM283XState), | ||
| 102 | .instance_init = bcm2836_init, | ||
| 103 | - .class_init = bcm2836_class_init, | ||
| 104 | + .class_size = sizeof(BCM283XClass), | ||
| 105 | + .abstract = true, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static void bcm2836_register_types(void) | ||
| 109 | { | ||
| 110 | - type_register_static(&bcm2836_type_info); | ||
| 111 | + int i; | ||
| 112 | + | ||
| 113 | + type_register_static(&bcm283x_type_info); | ||
| 114 | + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { | ||
| 115 | + TypeInfo ti = { | ||
| 116 | + .name = bcm283x_socs[i].name, | ||
| 117 | + .parent = TYPE_BCM283X, | ||
| 118 | + .class_init = bcm283x_class_init, | ||
| 119 | + .class_data = (void *) &bcm283x_socs[i], | ||
| 120 | + }; | ||
| 121 | + type_register(&ti); | ||
| 122 | + } | ||
| 123 | } | ||
| 124 | |||
| 125 | type_init(bcm2836_register_types) | ||
| 126 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 127 | index XXXXXXX..XXXXXXX 100644 | ||
| 128 | --- a/hw/arm/raspi.c | ||
| 129 | +++ b/hw/arm/raspi.c | ||
| 130 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
| 131 | BusState *bus; | ||
| 132 | DeviceState *carddev; | ||
| 133 | |||
| 134 | - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); | ||
| 135 | + object_initialize(&s->soc, sizeof(s->soc), | ||
| 136 | + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); | ||
| 137 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), | ||
| 138 | &error_abort); | ||
| 139 | 50 | ||
| 140 | -- | 51 | -- |
| 141 | 2.16.2 | 52 | 2.20.1 |
| 142 | 53 | ||
| 143 | 54 | diff view generated by jsdifflib |