1
Arm patch queue -- these are all bug fix patches but we might
1
Not much here, mostly documentation, but a few bug fixes.
2
as well put them in to rc0...
3
2
4
thanks
3
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
6
The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:
8
7
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
8
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720
14
13
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
14
for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:
16
15
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
16
docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
20
* virt: Don't enable MTE emulation by default
22
* dump: Update correct kdump phys_base field for AArch64
21
* virt: Diagnose attempts to use MTE with memory-hotplug or KVM
23
* char: i.MX: Add support for "TX complete" interrupt
22
(rather than silently not working correctly)
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
23
* util: Implement qemu_get_thread_id() for OpenBSD
25
to boot a Debian Linux kernel on raspi3
24
* qdev: Add doc comments for qdev_unrealize and GPIO functions,
25
and standardize on doc-comments-in-header-file
26
* hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
27
* docs/system: Document canon-a1100, collie, gumstix, virt boards
26
28
27
----------------------------------------------------------------
29
----------------------------------------------------------------
28
Andrey Smirnov (2):
30
David CARLIER (1):
29
char: i.MX: Simplify imx_update()
31
util: Implement qemu_get_thread_id() for OpenBSD
30
char: i.MX: Add support for "TX complete" interrupt
31
32
32
Guenter Roeck (1):
33
Peter Maydell (8):
33
fsl-imx6: Swap Ethernet interrupt defines
34
qdev: Move doc comments from qdev.c to qdev-core.h
35
qdev: Document qdev_unrealize()
36
qdev: Document GPIO related functions
37
hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
38
docs/system: Briefly document canon-a1100 board
39
docs/system: Briefly document collie board
40
docs/system: Briefly document gumstix boards
41
docs/system: Document the arm virt board
34
42
35
Peter Maydell (9):
43
Richard Henderson (3):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
44
hw/arm/virt: Enable MTE via a machine property
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
45
hw/arm/virt: Error for MTE enabled with KVM
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
46
hw/arm/virt: Disable memory hotplug when MTE is enabled
39
hw/arm/bcm2386: Fix parent type of bcm2386
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
41
hw/arm/bcm2836: Create proper bcm2837 device
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
43
hw/arm/bcm2836: Hardcode correct CPU type
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
47
46
Wei Huang (1):
48
docs/system/arm/collie.rst | 16 +++
47
dump: Update correct kdump phys_base field for AArch64
49
docs/system/arm/digic.rst | 11 ++
50
docs/system/arm/gumstix.rst | 21 ++++
51
docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++
52
docs/system/target-arm.rst | 4 +
53
include/hw/arm/virt.h | 1 +
54
include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++-
55
include/hw/qdev-properties.h | 13 +++
56
hw/arm/armsse.c | 2 +
57
hw/arm/virt.c | 50 +++++++-
58
hw/core/qdev.c | 33 ------
59
target/arm/cpu.c | 19 +--
60
target/arm/cpu64.c | 5 +-
61
util/oslib-posix.c | 2 +
62
MAINTAINERS | 4 +
63
15 files changed, 559 insertions(+), 50 deletions(-)
64
create mode 100644 docs/system/arm/collie.rst
65
create mode 100644 docs/system/arm/digic.rst
66
create mode 100644 docs/system/arm/gumstix.rst
67
create mode 100644 docs/system/arm/virt.rst
48
68
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
50
include/hw/arm/fsl-imx6.h | 4 +-
51
include/hw/char/imx_serial.h | 3 ++
52
dump.c | 14 +++++--
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
54
hw/arm/boot.c | 12 ++++++
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
57
hw/net/imx_fec.c | 28 +++++++++++++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
59
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
Control this cpu feature via a machine property, much as we do
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
4
with secure=on, since both require specialized support in the
5
controller which is supported in QEMU using the imx_fec.c module
5
machine setup to be functional.
6
(actually called imx.enet for this model.)
7
6
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
7
Default MTE to off, since this feature implies extra overhead.
9
imx.enet device like this:
10
8
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
#define FSL_IMX6_ENET_MAC_IRQ 119
10
Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
13
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
14
include/hw/arm/virt.h | 1 +
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
15
hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++-----
46
2 files changed, 29 insertions(+), 3 deletions(-)
16
target/arm/cpu.c | 19 +++++++++++--------
17
target/arm/cpu64.c | 5 +++--
18
4 files changed, 49 insertions(+), 15 deletions(-)
47
19
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
20
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
49
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
22
--- a/include/hw/arm/virt.h
51
+++ b/include/hw/arm/fsl-imx6.h
23
+++ b/include/hw/arm/virt.h
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
24
@@ -XXX,XX +XXX,XX @@ typedef struct {
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
25
bool its;
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
26
bool virt;
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
27
bool ras;
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
28
+ bool mte;
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
29
OnOffAuto acpi;
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
30
VirtGICType gic_version;
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
31
VirtIOMMUType iommu;
60
#define FSL_IMX6_PCIE1_IRQ 120
32
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
61
#define FSL_IMX6_PCIE2_IRQ 121
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
34
--- a/hw/arm/virt.c
66
+++ b/hw/net/imx_fec.c
35
+++ b/hw/arm/virt.c
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
36
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
68
37
OBJECT(secure_sysmem), &error_abort);
69
static void imx_eth_update(IMXFECState *s)
38
}
39
40
- /*
41
- * The cpu adds the property if and only if MemTag is supported.
42
- * If it is, we must allocate the ram to back that up.
43
- */
44
- if (object_property_find(cpuobj, "tag-memory", NULL)) {
45
+ if (vms->mte) {
46
+ /* Create the memory region only once, but link to all cpus. */
47
if (!tag_sysmem) {
48
+ /*
49
+ * The property exists only if MemTag is supported.
50
+ * If it is, we must allocate the ram to back that up.
51
+ */
52
+ if (!object_property_find(cpuobj, "tag-memory", NULL)) {
53
+ error_report("MTE requested, but not supported "
54
+ "by the guest CPU");
55
+ exit(1);
56
+ }
57
+
58
tag_sysmem = g_new(MemoryRegion, 1);
59
memory_region_init(tag_sysmem, OBJECT(machine),
60
"tag-memory", UINT64_MAX / 32);
61
@@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp)
62
vms->ras = value;
63
}
64
65
+static bool virt_get_mte(Object *obj, Error **errp)
66
+{
67
+ VirtMachineState *vms = VIRT_MACHINE(obj);
68
+
69
+ return vms->mte;
70
+}
71
+
72
+static void virt_set_mte(Object *obj, bool value, Error **errp)
73
+{
74
+ VirtMachineState *vms = VIRT_MACHINE(obj);
75
+
76
+ vms->mte = value;
77
+}
78
+
79
static char *virt_get_gic_version(Object *obj, Error **errp)
70
{
80
{
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
81
VirtMachineState *vms = VIRT_MACHINE(obj);
72
+ /*
82
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
83
"Set on/off to enable/disable reporting host memory errors "
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
84
"to a KVM guest using ACPI and guest external abort exceptions");
75
+ * and older) since Linux associated both interrupt lines with Ethernet
85
76
+ * MAC interrupts. Specifically,
86
+ /* MTE is disabled by default. */
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
87
+ vms->mte = false;
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
88
+ object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
79
+ * with swapped interrupt assignments.
89
+ object_property_set_description(obj, "mte",
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
90
+ "Set on/off to enable/disable emulating a "
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
91
+ "guest CPU which implements the ARM "
82
+ * work, though that is accidental.
92
+ "Memory Tagging Extension");
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
93
+
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
94
vms->irqmap = a15irqmap;
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
95
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
96
virt_flash_create(vms);
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
97
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
88
+ * Linux instead received MAC interrupts on the timer interrupt.
98
index XXXXXXX..XXXXXXX 100644
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
99
--- a/target/arm/cpu.c
90
+ * albeit accidentally, but qemu versions with the correct interrupt
100
+++ b/target/arm/cpu.c
91
+ * assignment fail.
101
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
92
+ *
102
cpu->id_pfr1 &= ~0xf000;
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
103
}
94
+ * interrrupts on both interrupt lines. This should be changed if and when
104
95
+ * qemu supports IOMUX.
105
+#ifndef CONFIG_USER_ONLY
96
+ */
106
+ if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
107
+ /*
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
108
+ * Disable the MTE feature bits if we do not have tag-memory
99
qemu_set_irq(s->irq[1], 1);
109
+ * provided by the machine.
100
} else {
110
+ */
101
qemu_set_irq(s->irq[1], 0);
111
+ cpu->isar.id_aa64pfr1 =
112
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
113
+ }
114
+#endif
115
+
116
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
117
* to false or by setting pmsav7-dregion to 0.
118
*/
119
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
120
cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
121
cpu->secure_tag_memory);
122
}
123
- } else if (cpu_isar_feature(aa64_mte, cpu)) {
124
- /*
125
- * Since there is no tag memory, we can't meaningfully support MTE
126
- * to its fullest. To avoid problems later, when we would come to
127
- * use the tag memory, downgrade support to insns only.
128
- */
129
- cpu->isar.id_aa64pfr1 =
130
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
131
}
132
133
cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
134
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
135
index XXXXXXX..XXXXXXX 100644
136
--- a/target/arm/cpu64.c
137
+++ b/target/arm/cpu64.c
138
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
139
t = cpu->isar.id_aa64pfr1;
140
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
141
/*
142
- * Begin with full support for MTE; will be downgraded to MTE=1
143
- * during realize if the board provides no tag memory.
144
+ * Begin with full support for MTE. This will be downgraded to MTE=0
145
+ * during realize if the board provides no tag memory, much like
146
+ * we do for EL2 with the virtualization=on property.
147
*/
148
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
149
cpu->isar.id_aa64pfr1 = t;
102
--
150
--
103
2.16.2
151
2.20.1
104
152
105
153
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
While we expect KVM to support MTE at some future point,
4
it is needed to support guests other than Linux.
4
it certainly won't be ready in time for qemu 5.1.
5
5
6
Based on the patch by Bill Paul as found here:
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
https://bugs.launchpad.net/qemu/+bug/1753314
7
Message-id: 20200713213341.590275-3-richard.henderson@linaro.org
8
9
Cc: qemu-devel@nongnu.org
10
Cc: qemu-arm@nongnu.org
11
Cc: Bill Paul <wpaul@windriver.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
10
---
19
include/hw/char/imx_serial.h | 3 +++
11
hw/arm/virt.c | 6 ++++++
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
12
1 file changed, 6 insertions(+)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
13
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
16
--- a/hw/arm/virt.c
26
+++ b/include/hw/char/imx_serial.h
17
+++ b/hw/arm/virt.c
27
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
19
exit(1);
29
#define UCR2_SRST (1<<0) /* Reset complete */
20
}
30
21
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
22
+ if (vms->mte && kvm_enabled()) {
23
+ error_report("mach-virt: KVM does not support providing "
24
+ "MTE to the guest CPU");
25
+ exit(1);
26
+ }
32
+
27
+
33
#define UTS1_TXEMPTY (1<<6)
28
create_fdt(vms);
34
#define UTS1_RXEMPTY (1<<5)
29
35
#define UTS1_TXFULL (1<<4)
30
possible_cpus = mc->possible_cpu_arch_ids(machine);
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
37
uint32_t ubmr;
38
uint32_t ubrc;
39
uint32_t ucr3;
40
+ uint32_t ucr4;
41
42
qemu_irq irq;
43
CharBackend chr;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
98
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
31
--
114
2.16.2
32
2.20.1
115
33
116
34
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
When MTE is enabled, tag memory must exist for all RAM.
4
doesn't really corespond to anything in real hardware and server as a
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
4
8
Change the code to explicitly evaluate state of interrupts reported
5
It might be possible to simultaneously hot plug tag memory
9
via USR1 and USR2 against corresponding masking bits and use the to
6
alongside the corresponding normal memory, but for now just
10
detemine if IRQ line should be asserted or not.
7
disable hotplug.
11
8
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
reasons:
10
Message-id: 20200713213341.590275-4-richard.henderson@linaro.org
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
13
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
14
hw/arm/virt.c | 5 +++++
34
1 file changed, 16 insertions(+), 8 deletions(-)
15
1 file changed, 5 insertions(+)
35
16
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
37
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
19
--- a/hw/arm/virt.c
39
+++ b/hw/char/imx_serial.c
20
+++ b/hw/arm/virt.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
21
@@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
41
22
return;
42
static void imx_update(IMXSerialState *s)
23
}
43
{
24
44
- uint32_t flags;
25
+ if (vms->mte) {
45
+ uint32_t usr1;
26
+ error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
46
+ uint32_t usr2;
27
+ return;
47
+ uint32_t mask;
28
+ }
48
29
+
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
30
if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
31
error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
32
return;
52
- } else {
53
- flags &= ~USR1_TRDY;
54
- }
55
+ /*
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
57
+ * UCR1, so we can get away with something as simple as the
58
+ * following:
59
+ */
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
71
72
static void imx_serial_reset(IMXSerialState *s)
73
--
33
--
74
2.16.2
34
2.20.1
75
35
76
36
diff view generated by jsdifflib
1
From: Wei Huang <wei@redhat.com>
1
From: David CARLIER <devnexen@gmail.com>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
Implement qemu_get_thread_id() for OpenBSD hosts, using
4
time when guest VM runs. To find the physical base address correctly,
4
getthrid().
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
5
10
Signed-off-by: Wei Huang <wei@redhat.com>
6
Signed-off-by: David Carlier <devnexen@gmail.com>
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Reviewed-by: Brad Smith <brad@comstyle.com>
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
8
Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
[PMM: tidied up commit message]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
dump.c | 14 +++++++++++---
13
util/oslib-posix.c | 2 ++
16
1 file changed, 11 insertions(+), 3 deletions(-)
14
1 file changed, 2 insertions(+)
17
15
18
diff --git a/dump.c b/dump.c
16
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
18
--- a/util/oslib-posix.c
21
+++ b/dump.c
19
+++ b/util/oslib-posix.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
20
@@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void)
23
21
return (int)tid;
24
lines = g_strsplit((char *)vmci, "\n", -1);
22
#elif defined(__NetBSD__)
25
for (i = 0; lines[i]; i++) {
23
return _lwp_self();
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
24
+#elif defined(__OpenBSD__)
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
25
+ return getthrid();
28
+ const char *prefix = NULL;
26
#else
29
+
27
return getpid();
30
+ if (s->dump_info.d_machine == EM_X86_64) {
28
#endif
31
+ prefix = "NUMBER(phys_base)=";
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
34
+ }
35
+
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
38
&phys_base) < 0) {
39
- warn_report("Failed to read NUMBER(phys_base)=");
40
+ warn_report("Failed to read %s", prefix);
41
} else {
42
s->dump_info.phys_base = phys_base;
43
}
44
--
29
--
45
2.16.2
30
2.20.1
46
31
47
32
diff view generated by jsdifflib
Deleted patch
1
For the rpi1 and 2 we want to boot the Linux kernel via some
2
custom setup code that makes sure that the SMC instruction
3
acts as a no-op, because it's used for cache maintenance.
4
The rpi3 boots AArch64 kernels, which don't need SMC for
5
cache maintenance and always expect to be booted non-secure.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
13
hw/arm/raspi.c | 17 +++++++++++++----
14
1 file changed, 13 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
21
binfo.board_id = raspi_boardid[version];
22
binfo.ram_size = ram_size;
23
binfo.nb_cpus = smp_cpus;
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
25
- binfo.write_board_setup = write_board_setup;
26
- binfo.secure_board_setup = true;
27
- binfo.secure_boot = true;
28
+
29
+ if (version <= 2) {
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
31
+ * mode before booting a kernel (to set up the SMC vectors so
32
+ * that we get a no-op SMC; this is used by Linux to call the
33
+ * firmware for some cache maintenance operations.
34
+ * The rpi3 doesn't need this.
35
+ */
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
37
+ binfo.write_board_setup = write_board_setup;
38
+ binfo.secure_board_setup = true;
39
+ binfo.secure_boot = true;
40
+ }
41
42
/* Pi2 and Pi3 requires SMP setup */
43
if (version >= 2) {
44
--
45
2.16.2
46
47
diff view generated by jsdifflib
1
Our BCM2836 type is really a generic one that can be any of
1
The doc-comments which document the qdev API are split between the
2
the bcm283x family. Rename it accordingly. We change only
2
header file and the C source files, because as a project we haven't
3
the names which are visible via the header file to the
3
been consistent about where we put them.
4
rest of the QEMU code, leaving private function names
5
in bcm2836.c as they are.
6
4
7
This is a preliminary to making bcm283x be an abstract
5
Move all the doc-comments in qdev.c to the header files, so that
8
parent class to specific types for the bcm2836 and bcm2837.
6
users of the APIs don't have to look at the implementation files for
7
this information.
8
9
In the process, unify them into our doc-comment format and expand on
10
them in some cases to clarify expected use cases.
9
11
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200711142425.16283-2-peter.maydell@linaro.org
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
15
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
16
include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++
16
hw/arm/bcm2836.c | 17 +++++++++--------
17
include/hw/qdev-properties.h | 13 ++++++++
17
hw/arm/raspi.c | 16 ++++++++--------
18
hw/core/qdev.c | 33 ---------------------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
3 files changed, 70 insertions(+), 33 deletions(-)
19
20
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
21
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
23
--- a/include/hw/qdev-core.h
23
+++ b/include/hw/arm/bcm2836.h
24
+++ b/include/hw/qdev-core.h
24
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr,
25
#include "hw/arm/bcm2835_peripherals.h"
26
26
#include "hw/intc/bcm2836_control.h"
27
/*** Board API. This should go away once we have a machine config file. ***/
27
28
28
-#define TYPE_BCM2836 "bcm2836"
29
+/**
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
30
+ * qdev_new: Create a device on the heap
30
+#define TYPE_BCM283X "bcm283x"
31
+ * @name: device type to create (we assert() that this type exists)
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
32
+ *
32
33
+ * This only allocates the memory and initializes the device state
33
-#define BCM2836_NCPUS 4
34
+ * structure, ready for the caller to set properties if they wish.
34
+#define BCM283X_NCPUS 4
35
+ * The device still needs to be realized.
35
36
+ * The returned object has a reference count of 1.
36
-typedef struct BCM2836State {
37
+ */
37
+typedef struct BCM283XState {
38
DeviceState *qdev_new(const char *name);
38
/*< private >*/
39
+/**
39
DeviceState parent_obj;
40
+ * qdev_try_new: Try to create a device on the heap
40
/*< public >*/
41
+ * @name: device type to create
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
42
+ *
42
char *cpu_type;
43
+ * This is like qdev_new(), except it returns %NULL when type @name
43
uint32_t enabled_cpus;
44
+ * does not exist, rather than asserting.
44
45
+ */
45
- ARMCPU cpus[BCM2836_NCPUS];
46
DeviceState *qdev_try_new(const char *name);
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
+/**
47
BCM2836ControlState control;
48
+ * qdev_realize: Realize @dev.
48
BCM2835PeripheralState peripherals;
49
+ * @dev: device to realize
49
-} BCM2836State;
50
+ * @bus: bus to plug it into (may be NULL)
50
+} BCM283XState;
51
+ * @errp: pointer to error object
51
52
+ *
52
#endif /* BCM2836_H */
53
+ * "Realize" the device, i.e. perform the second phase of device
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
+ * initialization.
55
+ * @dev must not be plugged into a bus already.
56
+ * If @bus, plug @dev into @bus. This takes a reference to @dev.
57
+ * If @dev has no QOM parent, make one up, taking another reference.
58
+ * On success, return true.
59
+ * On failure, store an error through @errp and return false.
60
+ *
61
+ * If you created @dev using qdev_new(), you probably want to use
62
+ * qdev_realize_and_unref() instead.
63
+ */
64
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
65
+/**
66
+ * qdev_realize_and_unref: Realize @dev and drop a reference
67
+ * @dev: device to realize
68
+ * @bus: bus to plug it into (may be NULL)
69
+ * @errp: pointer to error object
70
+ *
71
+ * Realize @dev and drop a reference.
72
+ * This is like qdev_realize(), except the caller must hold a
73
+ * (private) reference, which is dropped on return regardless of
74
+ * success or failure. Intended use::
75
+ *
76
+ * dev = qdev_new();
77
+ * [...]
78
+ * qdev_realize_and_unref(dev, bus, errp);
79
+ *
80
+ * Now @dev can go away without further ado.
81
+ *
82
+ * If you are embedding the device into some other QOM device and
83
+ * initialized it via some variant on object_initialize_child() then
84
+ * do not use this function, because that family of functions arrange
85
+ * for the only reference to the child device to be held by the parent
86
+ * via the child<> property, and so the reference-count-drop done here
87
+ * would be incorrect. For that use case you want qdev_realize().
88
+ */
89
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
90
void qdev_unrealize(DeviceState *dev);
91
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
92
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
54
index XXXXXXX..XXXXXXX 100644
93
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
94
--- a/include/hw/qdev-properties.h
56
+++ b/hw/arm/bcm2836.c
95
+++ b/include/hw/qdev-properties.h
57
@@ -XXX,XX +XXX,XX @@
96
@@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev,
58
97
*/
59
static void bcm2836_init(Object *obj)
98
void qdev_property_add_static(DeviceState *dev, Property *prop);
99
100
+/**
101
+ * qdev_alias_all_properties: Create aliases on source for all target properties
102
+ * @target: Device which has properties to be aliased
103
+ * @source: Object to add alias properties to
104
+ *
105
+ * Add alias properties to the @source object for all qdev properties on
106
+ * the @target DeviceState.
107
+ *
108
+ * This is useful when @target is an internal implementation object
109
+ * owned by @source, and you want to expose all the properties of that
110
+ * implementation object as properties on the @source object so that users
111
+ * of @source can set them.
112
+ */
113
void qdev_alias_all_properties(DeviceState *target, Object *source);
114
115
/**
116
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/core/qdev.c
119
+++ b/hw/core/qdev.c
120
@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
121
}
122
}
123
124
-/*
125
- * Create a device on the heap.
126
- * A type @name must exist.
127
- * This only initializes the device state structure and allows
128
- * properties to be set. The device still needs to be realized. See
129
- * qdev-core.h.
130
- */
131
DeviceState *qdev_new(const char *name)
60
{
132
{
61
- BCM2836State *s = BCM2836(obj);
133
if (!object_class_by_name(name)) {
62
+ BCM283XState *s = BCM283X(obj);
134
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name)
63
135
return DEVICE(object_new(name));
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
136
}
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
137
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
138
-/*
67
139
- * Try to create a device on the heap.
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
140
- * This is like qdev_new(), except it returns %NULL when type @name
141
- * does not exist.
142
- */
143
DeviceState *qdev_try_new(const char *name)
69
{
144
{
70
- BCM2836State *s = BCM2836(dev);
145
if (!module_object_class_by_name(name)) {
71
+ BCM283XState *s = BCM283X(dev);
146
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
72
Object *obj;
147
qdev_unrealize(dev);
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
148
}
95
149
96
static Property bcm2836_props[] = {
150
-/*
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
151
- * Realize @dev.
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
152
- * @dev must not be plugged into a bus.
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
153
- * If @bus, plug @dev into @bus. This takes a reference to @dev.
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
154
- * If @dev has no QOM parent, make one up, taking another reference.
101
+ BCM283X_NCPUS),
155
- * On success, return true.
102
DEFINE_PROP_END_OF_LIST()
156
- * On failure, store an error through @errp and return false.
103
};
157
- */
104
158
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
159
{
160
assert(!dev->realized && !dev->parent_bus);
161
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
162
return object_property_set_bool(OBJECT(dev), "realized", true, errp);
106
}
163
}
107
164
108
static const TypeInfo bcm2836_type_info = {
165
-/*
109
- .name = TYPE_BCM2836,
166
- * Realize @dev and drop a reference.
110
+ .name = TYPE_BCM283X,
167
- * This is like qdev_realize(), except the caller must hold a
111
.parent = TYPE_DEVICE,
168
- * (private) reference, which is dropped on return regardless of
112
- .instance_size = sizeof(BCM2836State),
169
- * success or failure. Intended use:
113
+ .instance_size = sizeof(BCM283XState),
170
- * dev = qdev_new();
114
.instance_init = bcm2836_init,
171
- * [...]
115
.class_init = bcm2836_class_init,
172
- * qdev_realize_and_unref(dev, bus, errp);
116
};
173
- * Now @dev can go away without further ado.
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
174
- */
118
index XXXXXXX..XXXXXXX 100644
175
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
119
--- a/hw/arm/raspi.c
176
{
120
+++ b/hw/arm/raspi.c
177
bool ret;
121
@@ -XXX,XX +XXX,XX @@
178
@@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop)
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
179
prop->info->description);
123
124
typedef struct RasPiState {
125
- BCM2836State soc;
126
+ BCM283XState soc;
127
MemoryRegion ram;
128
} RasPiState;
129
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
137
&error_abort);
138
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
140
mc->no_floppy = 1;
141
mc->no_cdrom = 1;
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
143
- mc->max_cpus = BCM2836_NCPUS;
144
- mc->min_cpus = BCM2836_NCPUS;
145
- mc->default_cpus = BCM2836_NCPUS;
146
+ mc->max_cpus = BCM283X_NCPUS;
147
+ mc->min_cpus = BCM283X_NCPUS;
148
+ mc->default_cpus = BCM283X_NCPUS;
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
180
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
181
182
-/* @qdev_alias_all_properties - Add alias properties to the source object for
183
- * all qdev properties on the target DeviceState.
184
- */
185
void qdev_alias_all_properties(DeviceState *target, Object *source)
186
{
187
ObjectClass *class;
165
--
188
--
166
2.16.2
189
2.20.1
167
190
168
191
diff view generated by jsdifflib
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
Add a doc comment for qdev_unrealize(), to go with the new
2
just hard-code the CPU type they use rather than having it passed
2
documentation for the realize part of the qdev lifecycle.
3
through as an object property. This then lets us put the initialization
4
of the CPU object in init rather than realize.
5
6
Note that this change means that it's no longer possible on
7
the command line to use -cpu to ask for a different kind of
8
CPU than the SoC supports. This was never a supported thing to
9
do anyway; we were just not sanity-checking the command line.
10
11
This does require us to only build the bcm2837 object on
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
13
due to the missing cortex-a53 device and "make check" will fail.
14
3
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20200711142425.16283-3-peter.maydell@linaro.org
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
7
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
8
include/hw/qdev-core.h | 19 +++++++++++++++++++
21
hw/arm/raspi.c | 2 --
9
1 file changed, 19 insertions(+)
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
10
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
11
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
13
--- a/include/hw/qdev-core.h
27
+++ b/hw/arm/bcm2836.c
14
+++ b/include/hw/qdev-core.h
28
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
29
16
* would be incorrect. For that use case you want qdev_realize().
30
struct BCM283XInfo {
17
*/
31
const char *name;
18
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
32
+ const char *cpu_type;
19
+/**
33
int clusterid;
20
+ * qdev_unrealize: Unrealize a device
34
};
21
+ * @dev: device to unrealize
35
22
+ *
36
static const BCM283XInfo bcm283x_socs[] = {
23
+ * This function will "unrealize" a device, which is the first phase
37
{
24
+ * of correctly destroying a device that has been realized. It will:
38
.name = TYPE_BCM2836,
25
+ *
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
26
+ * - unrealize any child buses by calling qbus_unrealize()
40
.clusterid = 0xf,
27
+ * (this will recursively unrealize any devices on those buses)
41
},
28
+ * - call the the unrealize method of @dev
42
+#ifdef TARGET_AARCH64
29
+ *
43
{
30
+ * The device can then be freed by causing its reference count to go
44
.name = TYPE_BCM2837,
31
+ * to zero.
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
32
+ *
46
.clusterid = 0x0,
33
+ * Warning: most devices in QEMU do not expect to be unrealized. Only
47
},
34
+ * devices which are hot-unpluggable should be unrealized (as part of
48
+#endif
35
+ * the unplugging process); all other devices are expected to last for
49
};
36
+ * the life of the simulation and should not be unrealized and freed.
50
37
+ */
51
static void bcm2836_init(Object *obj)
38
void qdev_unrealize(DeviceState *dev);
52
{
39
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
53
BCM283XState *s = BCM283X(obj);
40
int required_for_version);
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
55
+ const BCM283XInfo *info = bc->info;
56
+ int n;
57
+
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
60
+ info->cpu_type);
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
62
+ &error_abort);
63
+ }
64
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
68
69
/* common peripherals from bcm2835 */
70
71
- obj = OBJECT(dev);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
74
- s->cpu_type);
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
84
85
static Property bcm2836_props[] = {
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
41
--
104
2.16.2
42
2.20.1
105
43
106
44
diff view generated by jsdifflib
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
Add documentation comments for the various qdev functions
2
some differences. Notably, the MPIDR affinity aff1 values it
2
related to creating and connecting GPIO lines.
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
6
Rather than trying to have one device with properties that
7
configure it differently for the two cases, create two
8
separate QOM devices for the two SoCs. We use the same approach
9
as hw/arm/aspeed_soc.c and share code and have a data table
10
that might differ per-SoC. For the moment the two types don't
11
actually have different behaviour.
12
3
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
6
Message-id: 20200711142425.16283-4-peter.maydell@linaro.org
16
---
7
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
8
include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++-
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
9
1 file changed, 189 insertions(+), 2 deletions(-)
19
hw/arm/raspi.c | 3 ++-
10
20
3 files changed, 53 insertions(+), 6 deletions(-)
11
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
21
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
23
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
13
--- a/include/hw/qdev-core.h
25
+++ b/include/hw/arm/bcm2836.h
14
+++ b/include/hw/qdev-core.h
26
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
27
16
void qdev_machine_creation_done(void);
28
#define BCM283X_NCPUS 4
17
bool qdev_machine_modified(void);
29
18
30
+/* These type names are for specific SoCs; other than instantiating
19
+/**
31
+ * them, code using these devices should always handle them via the
20
+ * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
21
+ * @dev: Device whose GPIO we want
33
+ */
22
+ * @n: Number of the anonymous GPIO line (which must be in range)
34
+#define TYPE_BCM2836 "bcm2836"
23
+ *
35
+#define TYPE_BCM2837 "bcm2837"
24
+ * Returns the qemu_irq corresponding to an anonymous input GPIO line
36
+
25
+ * (which the device has set up with qdev_init_gpio_in()). The index
37
typedef struct BCM283XState {
26
+ * @n of the GPIO line must be valid (i.e. be at least 0 and less than
38
/*< private >*/
27
+ * the total number of anonymous input GPIOs the device has); this
39
DeviceState parent_obj;
28
+ * function will assert() if passed an invalid index.
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
29
+ *
41
BCM2835PeripheralState peripherals;
30
+ * This function is intended to be used by board code or SoC "container"
42
} BCM283XState;
31
+ * device models to wire up the GPIO lines; usually the return value
43
32
+ * will be passed to qdev_connect_gpio_out() or a similar function to
44
+typedef struct BCM283XInfo BCM283XInfo;
33
+ * connect another device's output GPIO line to this input.
45
+
34
+ *
46
+typedef struct BCM283XClass {
35
+ * For named input GPIO lines, use qdev_get_gpio_in_named().
47
+ DeviceClass parent_class;
36
+ */
48
+ const BCM283XInfo *info;
37
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
49
+} BCM283XClass;
38
+/**
50
+
39
+ * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines
51
+#define BCM283X_CLASS(klass) \
40
+ * @dev: Device whose GPIO we want
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
41
+ * @name: Name of the input GPIO array
53
+#define BCM283X_GET_CLASS(obj) \
42
+ * @n: Number of the GPIO line in that array (which must be in range)
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
43
+ *
55
+
44
+ * Returns the qemu_irq corresponding to a named input GPIO line
56
#endif /* BCM2836_H */
45
+ * (which the device has set up with qdev_init_gpio_in_named()).
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
46
+ * The @name string must correspond to an input GPIO array which exists on
58
index XXXXXXX..XXXXXXX 100644
47
+ * the device, and the index @n of the GPIO line must be valid (i.e.
59
--- a/hw/arm/bcm2836.c
48
+ * be at least 0 and less than the total number of input GPIOs in that
60
+++ b/hw/arm/bcm2836.c
49
+ * array); this function will assert() if passed an invalid name or index.
61
@@ -XXX,XX +XXX,XX @@
50
+ *
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
51
+ * For anonymous input GPIO lines, use qdev_get_gpio_in().
63
#define BCM2836_CONTROL_BASE 0x40000000
52
+ */
64
53
qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
65
+struct BCM283XInfo {
54
66
+ const char *name;
55
+/**
67
+};
56
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
68
+
57
+ * @dev: Device whose GPIO to connect
69
+static const BCM283XInfo bcm283x_socs[] = {
58
+ * @n: Number of the anonymous output GPIO line (which must be in range)
70
+ {
59
+ * @pin: qemu_irq to connect the output line to
71
+ .name = TYPE_BCM2836,
60
+ *
72
+ },
61
+ * This function connects an anonymous output GPIO line on a device
73
+ {
62
+ * up to an arbitrary qemu_irq, so that when the device asserts that
74
+ .name = TYPE_BCM2837,
63
+ * output GPIO line, the qemu_irq's callback is invoked.
75
+ },
64
+ * The index @n of the GPIO line must be valid (i.e. be at least 0 and
76
+};
65
+ * less than the total number of anonymous output GPIOs the device has
77
+
66
+ * created with qdev_init_gpio_out()); otherwise this function will assert().
78
static void bcm2836_init(Object *obj)
67
+ *
79
{
68
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
80
BCM283XState *s = BCM283X(obj);
69
+ * case is connecting them to another device's inbound GPIO line, using
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
70
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
82
DEFINE_PROP_END_OF_LIST()
71
+ *
83
};
72
+ * It is not valid to try to connect one outbound GPIO to multiple
84
73
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
74
+ * same qemu_irq. (Warning: there is no assertion or other guard to
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
75
+ * catch this error: the model will just not do the right thing.)
87
{
76
+ * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect
88
DeviceClass *dc = DEVICE_CLASS(oc);
77
+ * a device's outbound GPIO to the splitter's input, and connect each
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
78
+ * of the splitter's outputs to a different device. For fan-in you
90
79
+ * can use the TYPE_OR_IRQ device, which is a model of a logical OR
91
- dc->props = bcm2836_props;
80
+ * gate with multiple inputs and one output.
92
+ bc->info = data;
81
+ *
93
dc->realize = bcm2836_realize;
82
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
94
+ dc->props = bcm2836_props;
83
+ */
84
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
85
+/**
86
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
87
+ * @dev: Device whose GPIO to connect
88
+ * @name: Name of the output GPIO array
89
+ * @n: Number of the anonymous output GPIO line (which must be in range)
90
+ * @pin: qemu_irq to connect the output line to
91
+ *
92
+ * This function connects an anonymous output GPIO line on a device
93
+ * up to an arbitrary qemu_irq, so that when the device asserts that
94
+ * output GPIO line, the qemu_irq's callback is invoked.
95
+ * The @name string must correspond to an output GPIO array which exists on
96
+ * the device, and the index @n of the GPIO line must be valid (i.e.
97
+ * be at least 0 and less than the total number of input GPIOs in that
98
+ * array); this function will assert() if passed an invalid name or index.
99
+ *
100
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
101
+ * case is connecting them to another device's inbound GPIO line, using
102
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
103
+ *
104
+ * It is not valid to try to connect one outbound GPIO to multiple
105
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
106
+ * same qemu_irq; see qdev_connect_gpio_out() for details.
107
+ *
108
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
109
+ */
110
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
111
qemu_irq pin);
112
+/**
113
+ * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
114
+ * @dev: Device whose output GPIO we are interested in
115
+ * @name: Name of the output GPIO array
116
+ * @n: Number of the output GPIO line within that array
117
+ *
118
+ * Returns whatever qemu_irq is currently connected to the specified
119
+ * output GPIO line of @dev. This will be NULL if the output GPIO line
120
+ * has never been wired up to the anything. Note that the qemu_irq
121
+ * returned does not belong to @dev -- it will be the input GPIO or
122
+ * IRQ of whichever device the board code has connected up to @dev's
123
+ * output GPIO.
124
+ *
125
+ * You probably don't need to use this function -- it is used only
126
+ * by the platform-bus subsystem.
127
+ */
128
qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
129
+/**
130
+ * qdev_intercept_gpio_out: Intercept an existing GPIO connection
131
+ * @dev: Device to intercept the outbound GPIO line from
132
+ * @icpt: New qemu_irq to connect instead
133
+ * @name: Name of the output GPIO array
134
+ * @n: Number of the GPIO line in the array
135
+ *
136
+ * This function is provided only for use by the qtest testing framework
137
+ * and is not suitable for use in non-testing parts of QEMU.
138
+ *
139
+ * This function breaks an existing connection of an outbound GPIO
140
+ * line from @dev, and replaces it with the new qemu_irq @icpt, as if
141
+ * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called.
142
+ * The previously connected qemu_irq is returned, so it can be restored
143
+ * by a second call to qdev_intercept_gpio_out() if desired.
144
+ */
145
qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
146
const char *name, int n);
147
148
@@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name);
149
150
/*** Device API. ***/
151
152
-/* Register device properties. */
153
-/* GPIO inputs also double as IRQ sinks. */
154
+/**
155
+ * qdev_init_gpio_in: create an array of anonymous input GPIO lines
156
+ * @dev: Device to create input GPIOs for
157
+ * @handler: Function to call when GPIO line value is set
158
+ * @n: Number of GPIO lines to create
159
+ *
160
+ * Devices should use functions in the qdev_init_gpio_in* family in
161
+ * their instance_init or realize methods to create any input GPIO
162
+ * lines they need. There is no functional difference between
163
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
164
+ * preferable (easier to understand at callsites) unless a device
165
+ * has exactly one uniform kind of GPIO input whose purpose is obvious.
166
+ * Note that input GPIO lines can serve as 'sinks' for IRQ lines.
167
+ *
168
+ * See qdev_get_gpio_in() for how code that uses such a device can get
169
+ * hold of an input GPIO line to manipulate it.
170
+ */
171
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
172
+/**
173
+ * qdev_init_gpio_out: create an array of anonymous output GPIO lines
174
+ * @dev: Device to create output GPIOs for
175
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
176
+ * @n: Number of GPIO lines to create
177
+ *
178
+ * Devices should use functions in the qdev_init_gpio_out* family
179
+ * in their instance_init or realize methods to create any output
180
+ * GPIO lines they need. There is no functional difference between
181
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
182
+ * preferable (easier to understand at callsites) unless a device
183
+ * has exactly one uniform kind of GPIO output whose purpose is obvious.
184
+ *
185
+ * The @pins argument should be a pointer to either a "qemu_irq"
186
+ * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's
187
+ * state structure. The device implementation can then raise and
188
+ * lower the GPIO line by calling qemu_set_irq(). (If anything is
189
+ * connected to the other end of the GPIO this will cause the handler
190
+ * function for that input GPIO to be called.)
191
+ *
192
+ * See qdev_connect_gpio_out() for how code that uses such a device
193
+ * can connect to one of its output GPIO lines.
194
+ */
195
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
196
+/**
197
+ * qdev_init_gpio_out: create an array of named output GPIO lines
198
+ * @dev: Device to create output GPIOs for
199
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
200
+ * @name: Name to give this array of GPIO lines
201
+ * @n: Number of GPIO lines to create
202
+ *
203
+ * Like qdev_init_gpio_out(), but creates an array of GPIO output lines
204
+ * with a name. Code using the device can then connect these GPIO lines
205
+ * using qdev_connect_gpio_out_named().
206
+ */
207
void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
208
const char *name, int n);
209
/**
210
@@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev,
211
qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n);
95
}
212
}
96
213
97
-static const TypeInfo bcm2836_type_info = {
214
+/**
98
+static const TypeInfo bcm283x_type_info = {
215
+ * qdev_pass_gpios: create GPIO lines on container which pass through to device
99
.name = TYPE_BCM283X,
216
+ * @dev: Device which has GPIO lines
100
.parent = TYPE_DEVICE,
217
+ * @container: Container device which needs to expose them
101
.instance_size = sizeof(BCM283XState),
218
+ * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array)
102
.instance_init = bcm2836_init,
219
+ *
103
- .class_init = bcm2836_class_init,
220
+ * In QEMU, complicated devices like SoCs are often modelled with a
104
+ .class_size = sizeof(BCM283XClass),
221
+ * "container" QOM device which itself contains other QOM devices and
105
+ .abstract = true,
222
+ * which wires them up appropriately. This function allows the container
106
};
223
+ * to create GPIO arrays on itself which simply pass through to a GPIO
107
224
+ * array of one of its internal devices.
108
static void bcm2836_register_types(void)
225
+ *
109
{
226
+ * If @dev has both input and output GPIOs named @name then both will
110
- type_register_static(&bcm2836_type_info);
227
+ * be passed through. It is not possible to pass a subset of the array
111
+ int i;
228
+ * with this function.
112
+
229
+ *
113
+ type_register_static(&bcm283x_type_info);
230
+ * To users of the container device, the GPIO array created on @container
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
231
+ * behaves exactly like any other.
115
+ TypeInfo ti = {
232
+ */
116
+ .name = bcm283x_socs[i].name,
233
void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
117
+ .parent = TYPE_BCM283X,
234
const char *name);
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
123
}
124
125
type_init(bcm2836_register_types)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/raspi.c
129
+++ b/hw/arm/raspi.c
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
135
+ object_initialize(&s->soc, sizeof(s->soc),
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
138
&error_abort);
139
235
140
--
236
--
141
2.16.2
237
2.20.1
142
238
143
239
diff view generated by jsdifflib
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
In armsse_realize() we have a loop over [0, info->num_cpus), which
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
2
indexes into various fixed-size arrays in the ARMSSE struct. This
3
is required for Linux to boot.
3
confuses Coverity, which warns that we might overrun those arrays
4
(CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't
5
actually happen, because the info struct is always one of the entries
6
in the armsse_variants[] array and num_cpus is either 1 or 2; we also
7
already assert in armsse_init() that num_cpus is not too large.
8
However, adding an assert to armsse_realize() like the one in
9
armsse_init() should help Coverity figure out that these code paths
10
aren't possible.
4
11
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
14
Message-id: 20200713143716.9881-1-peter.maydell@linaro.org
9
---
15
---
10
hw/arm/bcm2836.c | 11 +++++++----
16
hw/arm/armsse.c | 2 ++
11
1 file changed, 7 insertions(+), 4 deletions(-)
17
1 file changed, 2 insertions(+)
12
18
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
19
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
21
--- a/hw/arm/armsse.c
16
+++ b/hw/arm/bcm2836.c
22
+++ b/hw/arm/armsse.c
17
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
18
24
return;
19
struct BCM283XInfo {
25
}
20
const char *name;
26
21
+ int clusterid;
27
+ assert(info->num_cpus <= SSE_MAX_CPUS);
22
};
28
+
23
29
/* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
24
static const BCM283XInfo bcm283x_socs[] = {
30
assert(is_power_of_2(info->sram_banks));
25
{
31
addr_width_max = 24 - ctz32(info->sram_banks);
26
.name = TYPE_BCM2836,
27
+ .clusterid = 0xf,
28
},
29
{
30
.name = TYPE_BCM2837,
31
+ .clusterid = 0x0,
32
},
33
};
34
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
37
{
38
BCM283XState *s = BCM283X(dev);
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
40
+ const BCM283XInfo *info = bc->info;
41
Object *obj;
42
Error *err = NULL;
43
int n;
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
46
47
for (n = 0; n < BCM283X_NCPUS; n++) {
48
- /* Mirror bcm2836, which has clusterid set to 0xf
49
- * TODO: this should be converted to a property of ARM_CPU
50
- */
51
- s->cpus[n].mp_affinity = 0xF00 | n;
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
32
--
58
2.16.2
33
2.20.1
59
34
60
35
diff view generated by jsdifflib
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
Add skeletal documentation of the canon-a1100 board.
2
code for keeping the secondary CPUs in a pen needs to have
3
a version for A64 as well as A32. Without this, the
4
secondary CPUs go into an infinite loop of taking undefined
5
instruction exceptions.
6
2
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20200713175746.5936-2-peter.maydell@linaro.org
10
---
7
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
8
docs/system/arm/digic.rst | 11 +++++++++++
12
1 file changed, 40 insertions(+), 1 deletion(-)
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 13 insertions(+)
12
create mode 100644 docs/system/arm/digic.rst
13
13
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/system/arm/digic.rst
19
@@ -XXX,XX +XXX,XX @@
20
+Canon A1100 (``canon-a1100``)
21
+=============================
22
+
23
+This machine is a model of the Canon PowerShot A1100 camera, which
24
+uses the DIGIC SoC. This model is based on reverse engineering efforts
25
+by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and
26
+`Magic Lantern <http://www.magiclantern.fm/>`_ projects.
27
+
28
+The emulation is incomplete. In particular it can't be used
29
+to run the original camera firmware, but it can successfully run
30
+an experimental version of the `barebox bootloader <http://www.barebox.org/>`_.
31
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
15
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
33
--- a/docs/system/target-arm.rst
17
+++ b/hw/arm/raspi.c
34
+++ b/docs/system/target-arm.rst
18
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
36
arm/versatile
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
37
arm/vexpress
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
38
arm/aspeed
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
39
+ arm/digic
23
40
arm/musicpal
24
/* Table of Linux board IDs for different Pi versions */
41
arm/nseries
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
42
arm/orangepi
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
43
diff --git a/MAINTAINERS b/MAINTAINERS
27
info->smp_loader_start);
44
index XXXXXXX..XXXXXXX 100644
28
}
45
--- a/MAINTAINERS
29
46
+++ b/MAINTAINERS
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
47
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h
31
+{
48
F: hw/*/digic*
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
49
F: include/hw/*/digic*
33
+ * The mechanism for doing the spin-table is also entirely different.
50
F: tests/acceptance/machine_arm_canona1100.py
34
+ * We must have four 64-bit fields at absolute addresses
51
+F: docs/system/arm/digic.rst
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
52
36
+ * our CPUs, and which we must ensure are zero initialized before
53
Goldfish RTC
37
+ * the primary CPU goes into the kernel. We put these variables inside
54
M: Anup Patel <anup.patel@wdc.com>
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
39
+ */
40
+ static const uint32_t smpboot[] = {
41
+ 0xd2801b05, /* mov x5, 0xd8 */
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
43
+ 0x924004c6, /* and x6, x6, #0x3 */
44
+ 0xd503205f, /* spin: wfe */
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
46
+ 0xb4ffffc4, /* cbz x4, spin */
47
+ 0xd2800000, /* mov x0, #0x0 */
48
+ 0xd2800001, /* mov x1, #0x0 */
49
+ 0xd2800002, /* mov x2, #0x0 */
50
+ 0xd2800003, /* mov x3, #0x0 */
51
+ 0xd61f0080, /* br x4 */
52
+ };
53
+
54
+ static const uint64_t spintables[] = {
55
+ 0, 0, 0, 0
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
63
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
65
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
68
/* Pi2 and Pi3 requires SMP setup */
69
if (version >= 2) {
70
binfo.smp_loader_start = SMPBOOT_ADDR;
71
- binfo.write_secondary_boot = write_smpboot;
72
+ if (version == 2) {
73
+ binfo.write_secondary_boot = write_smpboot;
74
+ } else {
75
+ binfo.write_secondary_boot = write_smpboot64;
76
+ }
77
binfo.secondary_cpu_reset_hook = reset_secondary;
78
}
79
80
--
55
--
81
2.16.2
56
2.20.1
82
57
83
58
diff view generated by jsdifflib
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
Add skeletal documentation of the collie board.
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
3
but the BCM2386State struct only defines the parent_obj field
4
as DeviceState. This would have caused problems if anything
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
8
provides.
9
2
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20200713175746.5936-3-peter.maydell@linaro.org
14
---
7
---
15
hw/arm/bcm2836.c | 2 +-
8
docs/system/arm/collie.rst | 16 ++++++++++++++++
16
1 file changed, 1 insertion(+), 1 deletion(-)
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 18 insertions(+)
12
create mode 100644 docs/system/arm/collie.rst
17
13
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
14
diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/system/arm/collie.rst
19
@@ -XXX,XX +XXX,XX @@
20
+Sharp Zaurus SL-5500 (``collie``)
21
+=================================
22
+
23
+This machine is a model of the Sharp Zaurus SL-5500, which was
24
+a 1990s PDA based on the StrongARM SA1110.
25
+
26
+Implemented devices:
27
+
28
+ * NOR flash
29
+ * Interrupt controller
30
+ * Timer
31
+ * RTC
32
+ * GPIO
33
+ * Peripheral Pin Controller (PPC)
34
+ * UARTs
35
+ * Synchronous Serial Ports (SSP)
36
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
19
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
38
--- a/docs/system/target-arm.rst
21
+++ b/hw/arm/bcm2836.c
39
+++ b/docs/system/target-arm.rst
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
40
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
23
41
arm/orangepi
24
static const TypeInfo bcm2836_type_info = {
42
arm/palm
25
.name = TYPE_BCM2836,
43
arm/xscale
26
- .parent = TYPE_SYS_BUS_DEVICE,
44
+ arm/collie
27
+ .parent = TYPE_DEVICE,
45
arm/sx1
28
.instance_size = sizeof(BCM2836State),
46
arm/stellaris
29
.instance_init = bcm2836_init,
47
30
.class_init = bcm2836_class_init,
48
diff --git a/MAINTAINERS b/MAINTAINERS
49
index XXXXXXX..XXXXXXX 100644
50
--- a/MAINTAINERS
51
+++ b/MAINTAINERS
52
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
53
S: Odd Fixes
54
F: hw/arm/collie.c
55
F: hw/arm/strongarm*
56
+F: docs/system/arm/collie.rst
57
58
Stellaris
59
M: Peter Maydell <peter.maydell@linaro.org>
31
--
60
--
32
2.16.2
61
2.20.1
33
62
34
63
diff view generated by jsdifflib
1
Add some assertions that if we're about to boot an AArch64 kernel,
1
Add skeletal documentation of the gumstix boards
2
the board code has not mistakenly set either secure_boot or
2
('connex' and 'verdex').
3
secure_board_setup. It doesn't make sense to set secure_boot,
4
because all AArch64 kernels must be booted in non-secure mode.
5
6
It might in theory make sense to set secure_board_setup, but
7
we don't currently support that, because only the AArch32
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
9
Since we don't have a current need for this functionality, just
10
assert that we don't try to use it. If it's needed we'll add
11
it later.
12
3
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200713175746.5936-4-peter.maydell@linaro.org
16
---
8
---
17
hw/arm/boot.c | 7 +++++++
9
docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++
18
1 file changed, 7 insertions(+)
10
docs/system/target-arm.rst | 1 +
11
MAINTAINERS | 1 +
12
3 files changed, 23 insertions(+)
13
create mode 100644 docs/system/arm/gumstix.rst
19
14
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
15
diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/gumstix.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Gumstix Connex and Verdex (``connex``, ``verdex``)
22
+==================================================
23
+
24
+These machines model the Gumstix Connex and Verdex boards.
25
+The Connex has a PXA255 CPU and the Verdex has a PXA270.
26
+
27
+Implemented devices:
28
+
29
+ * NOR flash
30
+ * SMC91C111 ethernet
31
+ * Interrupt controller
32
+ * DMA
33
+ * Timer
34
+ * GPIO
35
+ * MMC/SD card
36
+ * Fast infra-red communications port (FIR)
37
+ * LCD controller
38
+ * Synchronous serial ports (SPI)
39
+ * PCMCIA interface
40
+ * I2C
41
+ * I2S
42
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
21
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
44
--- a/docs/system/target-arm.rst
23
+++ b/hw/arm/boot.c
45
+++ b/docs/system/target-arm.rst
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
46
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
25
} else {
47
arm/aspeed
26
env->pstate = PSTATE_MODE_EL1h;
48
arm/digic
27
}
49
arm/musicpal
28
+ /* AArch64 kernels never boot in secure mode */
50
+ arm/gumstix
29
+ assert(!info->secure_boot);
51
arm/nseries
30
+ /* This hook is only supported for AArch32 currently:
52
arm/orangepi
31
+ * bootloader_aarch64[] will not call the hook, and
53
arm/palm
32
+ * the code above has already dropped us into EL2 or EL1.
54
diff --git a/MAINTAINERS b/MAINTAINERS
33
+ */
55
index XXXXXXX..XXXXXXX 100644
34
+ assert(!info->secure_board_setup);
56
--- a/MAINTAINERS
35
}
57
+++ b/MAINTAINERS
36
58
@@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org>
37
/* Set to non-secure if not a secure boot */
59
L: qemu-arm@nongnu.org
60
S: Odd Fixes
61
F: hw/arm/gumstix.c
62
+F: docs/system/arm/gumstix.rst
63
64
i.MX25 PDK
65
M: Peter Maydell <peter.maydell@linaro.org>
38
--
66
--
39
2.16.2
67
2.20.1
40
68
41
69
diff view generated by jsdifflib
1
If we're directly booting a Linux kernel and the CPU supports both
1
Document the arm 'virt' board, which has been undocumented
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
2
for far too long given that it is the main recommended board
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
3
type for arm guests.
4
instruction is enabled rather than UNDEFing. Otherwise at least some
5
kernels will panic when trying to initialize KVM in the guest.
6
4
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200713175746.5936-5-peter.maydell@linaro.org
9
---
8
---
10
hw/arm/boot.c | 5 +++++
9
docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++
11
1 file changed, 5 insertions(+)
10
docs/system/target-arm.rst | 1 +
12
11
MAINTAINERS | 1 +
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
12
3 files changed, 163 insertions(+)
13
create mode 100644 docs/system/arm/virt.rst
14
15
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@
21
+'virt' generic virtual platform (``virt``)
22
+==========================================
23
+
24
+The `virt` board is a platform which does not correspond to any
25
+real hardware; it is designed for use in virtual machines.
26
+It is the recommended board type if you simply want to run
27
+a guest such as Linux and do not care about reproducing the
28
+idiosyncrasies and limitations of a particular bit of real-world
29
+hardware.
30
+
31
+This is a "versioned" board model, so as well as the ``virt`` machine
32
+type itself (which may have improvements, bugfixes and other minor
33
+changes between QEMU versions) a version is provided that guarantees
34
+to have the same behaviour as that of previous QEMU releases, so
35
+that VM migration will work between QEMU versions. For instance the
36
+``virt-5.0`` machine type will behave like the ``virt`` machine from
37
+the QEMU 5.0 release, and migration should work between ``virt-5.0``
38
+of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
39
+is not guaranteed to work between different QEMU releases for
40
+the non-versioned ``virt`` machine type.
41
+
42
+Supported devices
43
+"""""""""""""""""
44
+
45
+The virt board supports:
46
+
47
+- PCI/PCIe devices
48
+- Flash memory
49
+- One PL011 UART
50
+- An RTC
51
+- The fw_cfg device that allows a guest to obtain data from QEMU
52
+- A PL061 GPIO controller
53
+- An optional SMMUv3 IOMMU
54
+- hotpluggable DIMMs
55
+- hotpluggable NVDIMMs
56
+- An MSI controller (GICv2M or ITS). GICv2M is selected by default along
57
+ with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
58
+ that ITS is not modeled in TCG mode.
59
+- 32 virtio-mmio transport devices
60
+- running guests using the KVM accelerator on aarch64 hardware
61
+- large amounts of RAM (at least 255GB, and more if using highmem)
62
+- many CPUs (up to 512 if using a GICv3 and highmem)
63
+- Secure-World-only devices if the CPU has TrustZone:
64
+
65
+ - A second PL011 UART
66
+ - A secure flash memory
67
+ - 16MB of secure RAM
68
+
69
+Supported guest CPU types:
70
+
71
+- ``cortex-a7`` (32-bit)
72
+- ``cortex-a15`` (32-bit; the default)
73
+- ``cortex-a53`` (64-bit)
74
+- ``cortex-a57`` (64-bit)
75
+- ``cortex-a72`` (64-bit)
76
+- ``host`` (with KVM only)
77
+- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
78
+
79
+Note that the default is ``cortex-a15``, so for an AArch64 guest you must
80
+specify a CPU type.
81
+
82
+Graphics output is available, but unlike the x86 PC machine types
83
+there is no default display device enabled: you should select one from
84
+the Display devices section of "-device help". The recommended option
85
+is ``virtio-gpu-pci``; this is the only one which will work correctly
86
+with KVM. You may also need to ensure your guest kernel is configured
87
+with support for this; see below.
88
+
89
+Machine-specific options
90
+""""""""""""""""""""""""
91
+
92
+The following machine-specific options are supported:
93
+
94
+secure
95
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
96
+ Arm Security Extensions (TrustZone). The default is ``off``.
97
+
98
+virtualization
99
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
100
+ Arm Virtualization Extensions. The default is ``off``.
101
+
102
+highmem
103
+ Set ``on``/``off`` to enable/disable placing devices and RAM in physical
104
+ address space above 32 bits. The default is ``on`` for machine types
105
+ later than ``virt-2.12``.
106
+
107
+gic-version
108
+ Specify the version of the Generic Interrupt Controller (GIC) to provide.
109
+ Valid values are:
110
+
111
+ ``2``
112
+ GICv2
113
+ ``3``
114
+ GICv3
115
+ ``host``
116
+ Use the same GIC version the host provides, when using KVM
117
+ ``max``
118
+ Use the best GIC version possible (same as host when using KVM;
119
+ currently same as ``3``` for TCG, but this may change in future)
120
+
121
+its
122
+ Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on``
123
+ for machine types later than ``virt-2.7``.
124
+
125
+iommu
126
+ Set the IOMMU type to create for the guest. Valid values are:
127
+
128
+ ``none``
129
+ Don't create an IOMMU (the default)
130
+ ``smmuv3``
131
+ Create an SMMUv3
132
+
133
+ras
134
+ Set ``on``/``off`` to enable/disable reporting host memory errors to a guest
135
+ using ACPI and guest external abort exceptions. The default is off.
136
+
137
+Linux guest kernel configuration
138
+""""""""""""""""""""""""""""""""
139
+
140
+The 'defconfig' for Linux arm and arm64 kernels should include the
141
+right device drivers for virtio and the PCI controller; however some older
142
+kernel versions, especially for 32-bit Arm, did not have everything
143
+enabled by default. If you're not seeing PCI devices that you expect,
144
+then check that your guest config has::
145
+
146
+ CONFIG_PCI=y
147
+ CONFIG_VIRTIO_PCI=y
148
+ CONFIG_PCI_HOST_GENERIC=y
149
+
150
+If you want to use the ``virtio-gpu-pci`` graphics device you will also
151
+need::
152
+
153
+ CONFIG_DRM=y
154
+ CONFIG_DRM_VIRTIO_GPU=y
155
+
156
+Hardware configuration information for bare-metal programming
157
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
158
+
159
+The ``virt`` board automatically generates a device tree blob ("dtb")
160
+which it passes to the guest. This provides information about the
161
+addresses, interrupt lines and other configuration of the various devices
162
+in the system. Guest code can rely on and hard-code the following
163
+addresses:
164
+
165
+- Flash memory starts at address 0x0000_0000
166
+
167
+- RAM starts at 0x4000_0000
168
+
169
+All other information about device locations may change between
170
+QEMU versions, so guest code must look in the DTB.
171
+
172
+QEMU supports two types of guest image boot for ``virt``, and
173
+the way for the guest code to locate the dtb binary differs:
174
+
175
+- For guests using the Linux kernel boot protocol (this means any
176
+ non-ELF file passed to the QEMU ``-kernel`` option) the address
177
+ of the DTB is passed in a register (``r2`` for 32-bit guests,
178
+ or ``x0`` for 64-bit guests)
179
+
180
+- For guests booting as "bare-metal" (any other kind of boot),
181
+ the DTB is at the start of RAM (0x4000_0000)
182
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
14
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
184
--- a/docs/system/target-arm.rst
16
+++ b/hw/arm/boot.c
185
+++ b/docs/system/target-arm.rst
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
186
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
18
assert(!info->secure_board_setup);
187
arm/collie
19
}
188
arm/sx1
20
189
arm/stellaris
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
190
+ arm/virt
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
191
23
+ env->cp15.scr_el3 |= SCR_HCE;
192
Arm CPU features
24
+ }
193
================
25
+
194
diff --git a/MAINTAINERS b/MAINTAINERS
26
/* Set to non-secure if not a secure boot */
195
index XXXXXXX..XXXXXXX 100644
27
if (!info->secure_boot &&
196
--- a/MAINTAINERS
28
(cs != first_cpu || !info->secure_board_setup)) {
197
+++ b/MAINTAINERS
198
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
199
S: Maintained
200
F: hw/arm/virt*
201
F: include/hw/arm/virt.h
202
+F: docs/system/arm/virt.rst
203
204
Xilinx Zynq
205
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
29
--
206
--
30
2.16.2
207
2.20.1
31
208
32
209
diff view generated by jsdifflib