Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc.

The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a:

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605

for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812:

target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100)

hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly

hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()

hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()

target/arm: Convert crypto insns to gvec

hw/adc/stm32f2xx_adc: Correct memory region size and access size

tests/acceptance: Add a boot test for the xlnx-versal-virt machine

docs/system: Document Aspeed boards

raspi: Add model of the USB controller

target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree

Cédric Le Goater (1):

docs/system: Document Aspeed boards

Eden Mikitas (2):

hw/ssi/imx_spi: changed while statement to prevent underflow

hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave

Paul Zimmerman (7):

raspi: add BCM2835 SOC MPHI emulation

dwc-hsotg (dwc2) USB host controller register definitions

dwc-hsotg (dwc2) USB host controller state definitions

dwc-hsotg (dwc2) USB host controller emulation

usb: add short-packet handling to usb-storage driver

wire in the dwc-hsotg (dwc2) USB host controller emulation

raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host

target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree

target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree

target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree

target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree

target/arm: Convert Neon narrowing shifts with op==8 to decodetree

target/arm: Convert Neon narrowing shifts with op==9 to decodetree

target/arm: Convert Neon VSHLL, VMOVL to decodetree

target/arm: Convert VCVT fixed-point ops to decodetree

target/arm: Convert Neon one-register-and-immediate insns to decodetree

Philippe Mathieu-Daudé (3):

hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()

hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()

hw/adc/stm32f2xx_adc: Correct memory region size and access size

Richard Henderson (6):

target/arm: Convert aes and sm4 to gvec helpers

target/arm: Convert rax1 to gvec helpers

target/arm: Convert sha512 and sm3 to gvec helpers

target/arm: Convert sha1 and sha256 to gvec helpers

target/arm: Split helper_crypto_sha1_3reg

target/arm: Split helper_crypto_sm3tt

From: Eden Mikitas <e.mikitas@gmail.com>

hw/ssi/imx_spi.c | 2 +-

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c

--- a/hw/ssi/imx_spi.c

+++ b/hw/ssi/imx_spi.c

@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)

if (fifo32_is_full(&s->rx_fifo)) {

s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;

} else {

- fifo32_push(&s->rx_fifo, (uint8_t)rx);

+ fifo32_push(&s->rx_fifo, rx);

}

if (s->burst_length <= 0) {

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw_error() calls exit(). This a bit overkill when we can log

the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to

exit. Replace some hw_error() calls by qemu_log_mask()

(missed in commit 5a0001ec7e).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200525114123.21317-2-f4bug@amsat.org

hw/input/pxa2xx_keypad.c | 10 +++++++---

1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c

--- a/hw/input/pxa2xx_keypad.c

+++ b/hw/input/pxa2xx_keypad.c

*/

#include "qemu/osdep.h"

-#include "hw/hw.h"

+#include "qemu/log.h"

#include "hw/irq.h"

#include "migration/vmstate.h"

#include "hw/arm/pxa.h"

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,

return s->kpkdi;

default:

- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, offset);

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,

default:

- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, offset);

}

}

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Replace printf() calls by qemu_log_mask(), which is disabled

by default. This avoid flooding the terminal when fuzzing the

device.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200525114123.21317-3-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++-------------

1 file changed, 49 insertions(+), 17 deletions(-)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/pxa2xx.c

+++ b/hw/arm/pxa2xx.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/blockdev.h"

#include "sysemu/qtest.h"

#include "qemu/cutils.h"

+#include "qemu/log.h"

static struct {

hwaddr io_base;

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,

return s->pm_regs[addr >> 2];

default:

fail:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,

s->pm_regs[addr >> 2] = value;

break;

}

-

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,

return s->cm_regs[CCCR >> 2] | (3 << 28);

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,

break;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,

return s->mm_regs[addr >> 2];

/* fall through */

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,

}

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,

case SSACD:

return s->ssacd;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,

break;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,

else

return s->last_swcr;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,

break;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,

s->ibmr = 0;

return s->ibmr;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,

break;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,

}

return 0;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,

}

break;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,

case ICFOR:

return s->rx_len;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

break;

}

return 0;

@@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,

case ICFOR:

break;

default:

- printf("%s: Bad register " REG_FMT "\n", __func__, addr);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",

+ __func__, addr);

}

}

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

With this conversion, we will be able to use the same helpers

with sve. In particular, pass 3 vector parameters for the

3-operand operations; for advsimd the destination register

is also an input.

This also fixes a bug in which we failed to clear the high bits

of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200514212831.31248-2-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper.h | 6 ++--

target/arm/vec_internal.h | 33 +++++++++++++++++

target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++-----------

target/arm/translate-a64.c | 55 ++++++++++++++++++-----------

target/arm/translate.c | 27 +++++++-------

target/arm/vec_helper.c | 12 +------

6 files changed, 138 insertions(+), 67 deletions(-)

create mode 100644 target/arm/vec_internal.h

diff --git a/target/arm/helper.h b/target/arm/helper.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr)

DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr)

DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)

-DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)

DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

-DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)

-DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

+DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)

DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)

diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/target/arm/vec_internal.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * ARM AdvSIMD / SVE Vector Helpers

+ *

+ * Copyright (c) 2020 Linaro

+ *

+ * This library is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU Lesser General Public

+ * License as published by the Free Software Foundation; either

+ * version 2 of the License, or (at your option) any later version.

+ *

+ * This library is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

+ * Lesser General Public License for more details.

+ *

+ * You should have received a copy of the GNU Lesser General Public

+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.

+ */

+

+#ifndef TARGET_ARM_VEC_INTERNALS_H

+#define TARGET_ARM_VEC_INTERNALS_H

+

+static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)

+{

+ uint64_t *d = vd + opr_sz;

+ uintptr_t i;

+

+ for (i = opr_sz; i < max_sz; i += 8) {

+ *d++ = 0;

+ }

+}

+

+#endif /* TARGET_ARM_VEC_INTERNALS_H */

diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/crypto_helper.c

+++ b/target/arm/crypto_helper.c

@@ -XXX,XX +XXX,XX @@

#include "cpu.h"

#include "exec/helper-proto.h"

+#include "tcg/tcg-gvec-desc.h"

#include "crypto/aes.h"

+#include "vec_internal.h"

union CRYPTO_STATE {

uint8_t bytes[16];

@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {

#define CR_ST_WORD(state, i) (state.words[i])

#endif

-void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)

+static void do_crypto_aese(uint64_t *rd, uint64_t *rn,

+ uint64_t *rm, bool decrypt)

{

static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };

static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };

- uint64_t *rd = vd;

- uint64_t *rm = vm;

union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };

- union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };

+ union CRYPTO_STATE st = { .l = { rn[0], rn[1] } };

int i;

- assert(decrypt < 2);

-

/* xor state vector with round key */

rk.l[0] ^= st.l[0];

rk.l[1] ^= st.l[1];

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)

rd[1] = st.l[1];

}

-void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)

+void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc)

+{

+ intptr_t i, opr_sz = simd_oprsz(desc);

+ bool decrypt = simd_data(desc);

+

+ for (i = 0; i < opr_sz; i += 16) {

+ do_crypto_aese(vd + i, vn + i, vm + i, decrypt);

+ }

+ clear_tail(vd, opr_sz, simd_maxsz(desc));

+}

+

+static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt)

{

static uint32_t const mc[][256] = { {

/* MixColumns lookup table */

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)

0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,

} };

- uint64_t *rd = vd;

- uint64_t *rm = vm;

union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };

int i;

- assert(decrypt < 2);

-

for (i = 0; i < 16; i += 4) {

CR_ST_WORD(st, i >> 2) =

mc[decrypt][CR_ST_BYTE(st, i)] ^

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)

rd[1] = st.l[1];

}

+void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)

+{

+ intptr_t i, opr_sz = simd_oprsz(desc);

+ bool decrypt = simd_data(desc);

+

+ for (i = 0; i < opr_sz; i += 16) {

+ do_crypto_aesmc(vd + i, vm + i, decrypt);

+ }

+ clear_tail(vd, opr_sz, simd_maxsz(desc));

+}

+

/*

* SHA-1 logical functions

*/

@@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = {

0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,

};

-void HELPER(crypto_sm4e)(void *vd, void *vn)

+static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)

{

- uint64_t *rd = vd;

- uint64_t *rn = vn;

- union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };

- union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };

+ union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };

+ union CRYPTO_STATE n = { .l = { rm[0], rm[1] } };

uint32_t t, i;

for (i = 0; i < 4; i++) {

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn)

rd[1] = d.l[1];

}

-void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)

+void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc)

+{

+ intptr_t i, opr_sz = simd_oprsz(desc);

+

+ for (i = 0; i < opr_sz; i += 16) {

+ do_crypto_sm4e(vd + i, vn + i, vm + i);

+ }

+ clear_tail(vd, opr_sz, simd_maxsz(desc));

+}

+

+static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)

{

- uint64_t *rd = vd;

- uint64_t *rn = vn;

- uint64_t *rm = vm;

union CRYPTO_STATE d;

union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };

union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)

rd[0] = d.l[0];

rd[1] = d.l[1];

}

+

+void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)

+{

+ intptr_t i, opr_sz = simd_oprsz(desc);

+

+ for (i = 0; i < opr_sz; i += 16) {

+ do_crypto_sm4ekey(vd + i, vn + i, vm + i);

+ }

+ clear_tail(vd, opr_sz, simd_maxsz(desc));

+}

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,

is_q ? 16 : 8, vec_full_reg_size(s));

}

+/* Expand a 2-operand operation using an out-of-line helper. */

+static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd,

+ int rn, int data, gen_helper_gvec_2 *fn)

+{

+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),

+ vec_full_reg_offset(s, rn),

+ is_q ? 16 : 8, vec_full_reg_size(s), data, fn);

+}

+

/* Expand a 3-operand operation using an out-of-line helper. */

static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,

int rn, int rm, int data, gen_helper_gvec_3 *fn)

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)

int rn = extract32(insn, 5, 5);

int rd = extract32(insn, 0, 5);

int decrypt;

- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;

- TCGv_i32 tcg_decrypt;

- CryptoThreeOpIntFn *genfn;

+ gen_helper_gvec_2 *genfn2 = NULL;

+ gen_helper_gvec_3 *genfn3 = NULL;

if (!dc_isar_feature(aa64_aes, s) || size != 0) {

unallocated_encoding(s);

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)

switch (opcode) {

case 0x4: /* AESE */

decrypt = 0;

- genfn = gen_helper_crypto_aese;

+ genfn3 = gen_helper_crypto_aese;

break;

case 0x6: /* AESMC */

decrypt = 0;

- genfn = gen_helper_crypto_aesmc;

+ genfn2 = gen_helper_crypto_aesmc;

break;

case 0x5: /* AESD */

decrypt = 1;

- genfn = gen_helper_crypto_aese;

+ genfn3 = gen_helper_crypto_aese;

break;

case 0x7: /* AESIMC */

decrypt = 1;

- genfn = gen_helper_crypto_aesmc;

+ genfn2 = gen_helper_crypto_aesmc;

break;

default:

unallocated_encoding(s);

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)

if (!fp_access_check(s)) {

return;

}

-

- tcg_rd_ptr = vec_full_reg_ptr(s, rd);

- tcg_rn_ptr = vec_full_reg_ptr(s, rn);

- tcg_decrypt = tcg_const_i32(decrypt);

-

- genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);

-

- tcg_temp_free_ptr(tcg_rd_ptr);

- tcg_temp_free_ptr(tcg_rn_ptr);

- tcg_temp_free_i32(tcg_decrypt);

+ if (genfn2) {

+ gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2);

+ } else {

+ gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3);

+ }

}

/* Crypto three-reg SHA

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

int rn = extract32(insn, 5, 5);

int rd = extract32(insn, 0, 5);

bool feature;

- CryptoThreeOpFn *genfn;

+ CryptoThreeOpFn *genfn = NULL;

+ gen_helper_gvec_3 *oolfn = NULL;

if (o == 0) {

switch (opcode) {

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

break;

case 2: /* SM4EKEY */

feature = dc_isar_feature(aa64_sm4, s);

- genfn = gen_helper_crypto_sm4ekey;

+ oolfn = gen_helper_crypto_sm4ekey;

break;

default:

unallocated_encoding(s);

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

return;

}

+ if (oolfn) {

+ gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);

+ return;

+ }

+

if (genfn) {

TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)

TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;

bool feature;

CryptoTwoOpFn *genfn;

+ gen_helper_gvec_3 *oolfn = NULL;

switch (opcode) {

case 0: /* SHA512SU0 */

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)

break;

case 1: /* SM4E */

feature = dc_isar_feature(aa64_sm4, s);

- genfn = gen_helper_crypto_sm4e;

+ oolfn = gen_helper_crypto_sm4e;

break;

default:

unallocated_encoding(s);

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)

return;

}

+ if (oolfn) {

+ gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);

+ return;

+ }

+

tcg_rd_ptr = vec_full_reg_ptr(s, rd);

tcg_rn_ptr = vec_full_reg_ptr(s, rn);

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)

if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {

return 1;

}

- ptr1 = vfp_reg_ptr(true, rd);

- ptr2 = vfp_reg_ptr(true, rm);

-

- /* Bit 6 is the lowest opcode bit; it distinguishes between

- * encryption (AESE/AESMC) and decryption (AESD/AESIMC)

- */

- tmp3 = tcg_const_i32(extract32(insn, 6, 1));

-

+ /*

+ * Bit 6 is the lowest opcode bit; it distinguishes

+ * between encryption (AESE/AESMC) and decryption

+ * (AESD/AESIMC).

+ */

if (op == NEON_2RM_AESE) {

- gen_helper_crypto_aese(ptr1, ptr2, tmp3);

+ tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),

+ vfp_reg_offset(true, rd),

+ vfp_reg_offset(true, rm),

+ 16, 16, extract32(insn, 6, 1),

+ gen_helper_crypto_aese);

} else {

- gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);

+ tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),

+ vfp_reg_offset(true, rm),

+ 16, 16, extract32(insn, 6, 1),

+ gen_helper_crypto_aesmc);

}

- tcg_temp_free_ptr(ptr1);

- tcg_temp_free_ptr(ptr2);

- tcg_temp_free_i32(tmp3);

break;

case NEON_2RM_SHA1H:

if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {

diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/vec_helper.c

+++ b/target/arm/vec_helper.c

@@ -XXX,XX +XXX,XX @@

#include "exec/helper-proto.h"

#include "tcg/tcg-gvec-desc.h"

#include "fpu/softfloat.h"

-

+#include "vec_internal.h"

/* Note that vector data is stored in host-endian 64-bit chunks,

so addressing units smaller than that needs a host-endian fixup. */

@@ -XXX,XX +XXX,XX @@

#define H4(x) (x)

#endif

-static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)

-{

- uint64_t *d = vd + opr_sz;

- uintptr_t i;

-

- for (i = opr_sz; i < max_sz; i += 8) {

- *d++ = 0;

- }

-}

-

/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */

static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,

int16_t src3, uint32_t *sat)

--

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

With this conversion, we will be able to use the same helpers

with sve. This also fixes a bug in which we failed to clear

the high bits of the SVE register after an AdvSIMD operation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200514212831.31248-3-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper.h | 2 ++

target/arm/translate-a64.h | 3 ++

target/arm/crypto_helper.c | 11 +++++++

target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------

4 files changed, 47 insertions(+), 28 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)

DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.h

+++ b/target/arm/translate-a64.h

@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)

bool disas_sve(DisasContext *, uint32_t);

+void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,

+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);

+

#endif /* TARGET_ARM_TRANSLATE_A64_H */

diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/crypto_helper.c

+++ b/target/arm/crypto_helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)

}

clear_tail(vd, opr_sz, simd_maxsz(desc));

}

+

+void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc)

+{

+ intptr_t i, opr_sz = simd_oprsz(desc);

+ uint64_t *d = vd, *n = vn, *m = vm;

+

+ for (i = 0; i < opr_sz / 8; ++i) {

+ d[i] = n[i] ^ rol64(m[i], 1);

+ clear_tail(vd, opr_sz, simd_maxsz(desc));

+}

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)

tcg_temp_free_ptr(tcg_rn_ptr);

}

+static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)

+{

+ tcg_gen_rotli_i64(d, m, 1);

+ tcg_gen_xor_i64(d, d, n);

+}

+

+static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m)

+{

+ tcg_gen_rotli_vec(vece, d, m, 1);

+ tcg_gen_xor_vec(vece, d, d, n);

+}

+

+void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,

+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)

+{

+ static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };

+ static const GVecGen3 op = {

+ .fni8 = gen_rax1_i64,

+ .fniv = gen_rax1_vec,

+ .opt_opc = vecop_list,

+ .fno = gen_helper_crypto_rax1,

+ .vece = MO_64,

+ };

+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op);

+}

+

/* Crypto three-reg SHA512

* 31 21 20 16 15 14 13 12 11 10 9 5 4 0

* +-----------------------+------+---+---+-----+--------+------+------+

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

bool feature;

CryptoThreeOpFn *genfn = NULL;

gen_helper_gvec_3 *oolfn = NULL;

+ GVecGen3Fn *gvecfn = NULL;

if (o == 0) {

switch (opcode) {

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

break;

case 3: /* RAX1 */

feature = dc_isar_feature(aa64_sha3, s);

- genfn = NULL;

+ gvecfn = gen_gvec_rax1;

break;

default:

g_assert_not_reached();

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

if (oolfn) {

gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);

- return;

- if (genfn) {

+ } else if (gvecfn) {

+ gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);

+ } else {

TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;

tcg_rd_ptr = vec_full_reg_ptr(s, rd);

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

tcg_temp_free_ptr(tcg_rd_ptr);

tcg_temp_free_ptr(tcg_rn_ptr);

tcg_temp_free_ptr(tcg_rm_ptr);

- } else {

- TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];

- int pass;

-

- tcg_op1 = tcg_temp_new_i64();

- tcg_op2 = tcg_temp_new_i64();

- tcg_res[0] = tcg_temp_new_i64();

- tcg_res[1] = tcg_temp_new_i64();

-

- for (pass = 0; pass < 2; pass++) {

- read_vec_element(s, tcg_op1, rn, pass, MO_64);

- read_vec_element(s, tcg_op2, rm, pass, MO_64);

-

- tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);

- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);

- }

- write_vec_element(s, tcg_res[0], rd, 0, MO_64);

- write_vec_element(s, tcg_res[1], rd, 1, MO_64);

-

- tcg_temp_free_i64(tcg_op1);

- tcg_temp_free_i64(tcg_op2);

- tcg_temp_free_i64(tcg_res[0]);

- tcg_temp_free_i64(tcg_res[1]);

}

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not yet convert the helpers to loop over opr_sz, but the

descriptor allows the vector tail to be cleared. Which fixes

an existing bug vs SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200514212831.31248-4-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper.h | 15 +++++++-----

target/arm/crypto_helper.c | 37 +++++++++++++++++++++++-----

target/arm/translate-a64.c | 50 ++++++++++++--------------------------

3 files changed, 55 insertions(+), 47 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)

DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

-DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

-DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

-DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr)

-DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

+DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

+DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,

+ void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)

-DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

-DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

+DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,

+ void, ptr, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,

+ void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/crypto_helper.c

+++ b/target/arm/crypto_helper.c

@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {

#define CR_ST_WORD(state, i) (state.words[i])

#endif

+/*

+ * The caller has not been converted to full gvec, and so only

+ * modifies the low 16 bytes of the vector register.

+ */

+static void clear_tail_16(void *vd, uint32_t desc)

+{

+ int opr_sz = simd_oprsz(desc);

+ int max_sz = simd_maxsz(desc);

+

+ assert(opr_sz == 16);

+ clear_tail(vd, opr_sz, max_sz);

+}

+

static void do_crypto_aese(uint64_t *rd, uint64_t *rn,

uint64_t *rm, bool decrypt)

{

@@ -XXX,XX +XXX,XX @@ static uint64_t s1_512(uint64_t x)

return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);

}

-void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)

+void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm, uint32_t desc)

{

uint64_t *rd = vd;

uint64_t *rn = vn;

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)

rd[0] = d0;

rd[1] = d1;

+

+ clear_tail_16(vd, desc);

}

-void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)

+void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm, uint32_t desc)

{

uint64_t *rd = vd;

uint64_t *rn = vn;

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)

rd[0] = d0;

rd[1] = d1;

+

+ clear_tail_16(vd, desc);

}

-void HELPER(crypto_sha512su0)(void *vd, void *vn)

+void HELPER(crypto_sha512su0)(void *vd, void *vn, uint32_t desc)

{

uint64_t *rd = vd;