[Qemu-devel] [PULL 00/13] target-arm queue
[PULL 00/29] target-arm queue
1
Arm patch queue -- these are all bug fix patches but we might
1
target-arm queue: nothing big, just a collection of minor things.
2
as well put them in to rc0...
3
2
4
thanks
5
-- PMM
3
-- PMM
6
4
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
5
The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71:
8
6
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
7
Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100)
10
8
11
are available in the Git repository at:
9
are available in the Git repository at:
12
10
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521
14
12
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
13
for you to fetch changes up to 17b5df7b65d0192c5d775b5e1581518580774c77:
16
14
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
15
linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 20:00:19 +0100)
18
16
19
----------------------------------------------------------------
17
----------------------------------------------------------------
20
target-arm queue:
18
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
19
* tests/acceptance: Add a test for the canon-a1100 machine
22
* dump: Update correct kdump phys_base field for AArch64
20
* docs/system: Document some of the Arm development boards
23
* char: i.MX: Add support for "TX complete" interrupt
21
* linux-user: make BKPT insn cause SIGTRAP, not be a syscall
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
22
* target/arm: Remove unused GEN_NEON_INTEGER_OP macro
25
to boot a Debian Linux kernel on raspi3
23
* fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog
24
* hw/arm: Use qemu_log_mask() instead of hw_error() in various places
25
* ARM: PL061: Introduce N_GPIOS
26
* target/arm: Improve clear_vec_high() usage
27
* target/arm: Allow user-mode code to write CPSR.E via MSR
28
* linux-user/arm: Reset CPSR_E when entering a signal handler
29
* linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
26
30
27
----------------------------------------------------------------
31
----------------------------------------------------------------
28
Andrey Smirnov (2):
32
Amanieu d'Antras (1):
29
char: i.MX: Simplify imx_update()
33
linux-user/arm: Reset CPSR_E when entering a signal handler
30
char: i.MX: Add support for "TX complete" interrupt
31
34
32
Guenter Roeck (1):
35
Geert Uytterhoeven (1):
33
fsl-imx6: Swap Ethernet interrupt defines
36
ARM: PL061: Introduce N_GPIOS
34
37
35
Peter Maydell (9):
38
Guenter Roeck (8):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
39
hw: Move i.MX watchdog driver to hw/watchdog
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
40
hw/watchdog: Implement full i.MX watchdog support
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
41
hw/arm/fsl-imx25: Wire up watchdog
39
hw/arm/bcm2386: Fix parent type of bcm2386
42
hw/arm/fsl-imx31: Wire up watchdog
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
43
hw/arm/fsl-imx6: Connect watchdog interrupts
41
hw/arm/bcm2836: Create proper bcm2837 device
44
hw/arm/fsl-imx6ul: Connect watchdog interrupts
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
45
hw/arm/fsl-imx7: Instantiate various unimplemented devices
43
hw/arm/bcm2836: Hardcode correct CPU type
46
hw/arm/fsl-imx7: Connect watchdog interrupts
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
47
46
Wei Huang (1):
48
Peter Maydell (12):
47
dump: Update correct kdump phys_base field for AArch64
49
docs/system: Add 'Arm' to the Integrator/CP document title
50
docs/system: Sort Arm board index into alphabetical order
51
docs/system: Document Arm Versatile Express boards
52
docs/system: Document the various MPS2 models
53
docs/system: Document Musca boards
54
linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
55
linux-user/arm: Remove bogus SVC 0xf0002 handling
56
linux-user/arm: Handle invalid arm-specific syscalls correctly
57
linux-user/arm: Fix identification of syscall numbers
58
target/arm: Remove unused GEN_NEON_INTEGER_OP macro
59
target/arm: Allow user-mode code to write CPSR.E via MSR
60
linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
48
61
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
62
Philippe Mathieu-Daudé (4):
50
include/hw/arm/fsl-imx6.h | 4 +-
63
hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
51
include/hw/char/imx_serial.h | 3 ++
64
hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
52
dump.c | 14 +++++--
65
hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
66
hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
54
hw/arm/boot.c | 12 ++++++
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
57
hw/net/imx_fec.c | 28 +++++++++++++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
59
67
68
Richard Henderson (2):
69
target/arm: Use tcg_gen_gvec_mov for clear_vec_high
70
target/arm: Use clear_vec_high more effectively
71
72
Thomas Huth (1):
73
tests/acceptance: Add a test for the canon-a1100 machine
74
75
docs/system/arm/integratorcp.rst | 4 +-
76
docs/system/arm/mps2.rst | 29 +++
77
docs/system/arm/musca.rst | 31 +++
78
docs/system/arm/vexpress.rst | 60 ++++++
79
docs/system/target-arm.rst | 20 +-
80
include/hw/arm/fsl-imx25.h | 5 +
81
include/hw/arm/fsl-imx31.h | 4 +
82
include/hw/arm/fsl-imx6.h | 2 +-
83
include/hw/arm/fsl-imx6ul.h | 2 +-
84
include/hw/arm/fsl-imx7.h | 23 ++-
85
include/hw/misc/imx2_wdt.h | 33 ----
86
include/hw/watchdog/wdt_imx2.h | 90 +++++++++
87
target/arm/cpu.h | 2 +-
88
hw/arm/fsl-imx25.c | 10 +
89
hw/arm/fsl-imx31.c | 6 +
90
hw/arm/fsl-imx6.c | 9 +
91
hw/arm/fsl-imx6ul.c | 10 +
92
hw/arm/fsl-imx7.c | 35 ++++
93
hw/arm/integratorcp.c | 23 ++-
94
hw/arm/pxa2xx_gpio.c | 7 +-
95
hw/char/xilinx_uartlite.c | 5 +-
96
hw/display/pxa2xx_lcd.c | 8 +-
97
hw/dma/pxa2xx_dma.c | 14 +-
98
hw/gpio/pl061.c | 12 +-
99
hw/misc/imx2_wdt.c | 90 ---------
100
hw/timer/exynos4210_mct.c | 12 +-
101
hw/watchdog/wdt_imx2.c | 303 +++++++++++++++++++++++++++++
102
linux-user/arm/cpu_loop.c | 145 ++++++++------
103
linux-user/arm/signal.c | 15 +-
104
target/arm/translate-a64.c | 63 +++---
105
target/arm/translate.c | 23 ---
106
MAINTAINERS | 6 +
107
hw/arm/Kconfig | 5 +
108
hw/misc/Makefile.objs | 1 -
109
hw/watchdog/Kconfig | 3 +
110
hw/watchdog/Makefile.objs | 1 +
111
tests/acceptance/machine_arm_canona1100.py | 35 ++++
112
37 files changed, 854 insertions(+), 292 deletions(-)
113
create mode 100644 docs/system/arm/mps2.rst
114
create mode 100644 docs/system/arm/musca.rst
115
create mode 100644 docs/system/arm/vexpress.rst
116
delete mode 100644 include/hw/misc/imx2_wdt.h
117
create mode 100644 include/hw/watchdog/wdt_imx2.h
118
delete mode 100644 hw/misc/imx2_wdt.c
119
create mode 100644 hw/watchdog/wdt_imx2.c
120
create mode 100644 tests/acceptance/machine_arm_canona1100.py
121
diff view generated by jsdifflib
New patch
[PULL 01/29] tests/acceptance: Add a test for the canon-a1100 machine
1
From: Thomas Huth <thuth@redhat.com>
1
2
3
The canon-a1100 machine can be used with the Barebox firmware. The
4
QEMU Advent Calendar 2018 features a pre-compiled image which we
5
can use for testing.
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
10
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
11
Signed-off-by: Thomas Huth <thuth@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20200514190422.23645-1-f4bug@amsat.org
14
Message-Id: <20200129090420.13954-1-thuth@redhat.com>
15
[PMD: Rebased MAINTAINERS]
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
MAINTAINERS | 1 +
20
tests/acceptance/machine_arm_canona1100.py | 35 ++++++++++++++++++++++
21
2 files changed, 36 insertions(+)
22
create mode 100644 tests/acceptance/machine_arm_canona1100.py
23
24
diff --git a/MAINTAINERS b/MAINTAINERS
25
index XXXXXXX..XXXXXXX 100644
26
--- a/MAINTAINERS
27
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
29
F: include/hw/arm/digic.h
30
F: hw/*/digic*
31
F: include/hw/*/digic*
32
+F: tests/acceptance/machine_arm_canona1100.py
33
34
Goldfish RTC
35
M: Anup Patel <anup.patel@wdc.com>
36
diff --git a/tests/acceptance/machine_arm_canona1100.py b/tests/acceptance/machine_arm_canona1100.py
37
new file mode 100644
38
index XXXXXXX..XXXXXXX
39
--- /dev/null
40
+++ b/tests/acceptance/machine_arm_canona1100.py
41
@@ -XXX,XX +XXX,XX @@
42
+# Functional test that boots the canon-a1100 machine with firmware
43
+#
44
+# Copyright (c) 2020 Red Hat, Inc.
45
+#
46
+# Author:
47
+# Thomas Huth <thuth@redhat.com>
48
+#
49
+# This work is licensed under the terms of the GNU GPL, version 2 or
50
+# later. See the COPYING file in the top-level directory.
51
+
52
+from avocado_qemu import Test
53
+from avocado_qemu import wait_for_console_pattern
54
+from avocado.utils import archive
55
+
56
+class CanonA1100Machine(Test):
57
+ """Boots the barebox firmware and checks that the console is operational"""
58
+
59
+ timeout = 90
60
+
61
+ def test_arm_canona1100(self):
62
+ """
63
+ :avocado: tags=arch:arm
64
+ :avocado: tags=machine:canon-a1100
65
+ :avocado: tags=device:pflash_cfi02
66
+ """
67
+ tar_url = ('https://www.qemu-advent-calendar.org'
68
+ '/2018/download/day18.tar.xz')
69
+ tar_hash = '068b5fc4242b29381acee94713509f8a876e9db6'
70
+ file_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
71
+ archive.extract(file_path, self.workdir)
72
+ self.vm.set_console()
73
+ self.vm.add_args('-bios',
74
+ self.workdir + '/day18/barebox.canon-a1100.bin')
75
+ self.vm.launch()
76
+ wait_for_console_pattern(self, 'running /env/bin/init')
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
New patch
[PULL 02/29] docs/system: Add 'Arm' to the Integrator/CP document title
1
Add 'Arm' to the Integrator/CP document title, for consistency with
2
the titling of the other documentation of Arm devboard models
3
(versatile, realview).
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200507151819.28444-2-peter.maydell@linaro.org
10
---
11
docs/system/arm/integratorcp.rst | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/docs/system/arm/integratorcp.rst b/docs/system/arm/integratorcp.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/integratorcp.rst
17
+++ b/docs/system/arm/integratorcp.rst
18
@@ -XXX,XX +XXX,XX @@
19
-Integrator/CP (``integratorcp``)
20
-================================
21
+Arm Integrator/CP (``integratorcp``)
22
+====================================
23
24
The Arm Integrator/CP board is emulated with the following devices:
25
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
New patch
[PULL 03/29] docs/system: Sort Arm board index into alphabetical order
1
Sort the board index into alphabetical order. (Note that we need to
2
sort alphabetically by the title text of each file, which isn't the
3
same ordering as sorting by the filename.)
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20200507151819.28444-3-peter.maydell@linaro.org
10
---
11
docs/system/target-arm.rst | 17 +++++++++++------
12
1 file changed, 11 insertions(+), 6 deletions(-)
13
14
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/target-arm.rst
17
+++ b/docs/system/target-arm.rst
18
@@ -XXX,XX +XXX,XX @@ Unfortunately many of the Arm boards QEMU supports are currently
19
undocumented; you can get a complete list by running
20
``qemu-system-aarch64 --machine help``.
21
22
+..
23
+ This table of contents should be kept sorted alphabetically
24
+ by the title text of each file, which isn't the same ordering
25
+ as an alphabetical sort by filename.
26
+
27
.. toctree::
28
:maxdepth: 1
29
30
arm/integratorcp
31
- arm/versatile
32
arm/realview
33
- arm/xscale
34
- arm/palm
35
- arm/nseries
36
- arm/stellaris
37
+ arm/versatile
38
arm/musicpal
39
- arm/sx1
40
+ arm/nseries
41
arm/orangepi
42
+ arm/palm
43
+ arm/xscale
44
+ arm/sx1
45
+ arm/stellaris
46
47
Arm CPU features
48
================
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
New patch
[PULL 04/29] docs/system: Document Arm Versatile Express boards
1
Provide a minimal documentation of the Versatile Express boards
2
(vexpress-a9, vexpress-a15).
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20200507151819.28444-4-peter.maydell@linaro.org
9
---
10
docs/system/arm/vexpress.rst | 60 ++++++++++++++++++++++++++++++++++++
11
docs/system/target-arm.rst | 1 +
12
MAINTAINERS | 1 +
13
3 files changed, 62 insertions(+)
14
create mode 100644 docs/system/arm/vexpress.rst
15
16
diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/docs/system/arm/vexpress.rst
21
@@ -XXX,XX +XXX,XX @@
22
+Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
23
+================================================================
24
+
25
+QEMU models two variants of the Arm Versatile Express development
26
+board family:
27
+
28
+- ``vexpress-a9`` models the combination of the Versatile Express
29
+ motherboard and the CoreTile Express A9x4 daughterboard
30
+- ``vexpress-a15`` models the combination of the Versatile Express
31
+ motherboard and the CoreTile Express A15x2 daughterboard
32
+
33
+Note that as this hardware does not have PCI, IDE or SCSI,
34
+the only available storage option is emulated SD card.
35
+
36
+Implemented devices:
37
+
38
+- PL041 audio
39
+- PL181 SD controller
40
+- PL050 keyboard and mouse
41
+- PL011 UARTs
42
+- SP804 timers
43
+- I2C controller
44
+- PL031 RTC
45
+- PL111 LCD display controller
46
+- Flash memory
47
+- LAN9118 ethernet
48
+
49
+Unimplemented devices:
50
+
51
+- SP810 system control block
52
+- PCI-express
53
+- USB controller (Philips ISP1761)
54
+- Local DAP ROM
55
+- CoreSight interfaces
56
+- PL301 AXI interconnect
57
+- SCC
58
+- System counter
59
+- HDLCD controller (``vexpress-a15``)
60
+- SP805 watchdog
61
+- PL341 dynamic memory controller
62
+- DMA330 DMA controller
63
+- PL354 static memory controller
64
+- BP147 TrustZone Protection Controller
65
+- TrustZone Address Space Controller
66
+
67
+Other differences between the hardware and the QEMU model:
68
+
69
+- QEMU will default to creating one CPU unless you pass a different
70
+ ``-smp`` argument
71
+- QEMU allows the amount of RAM provided to be specified with the
72
+ ``-m`` argument
73
+- QEMU defaults to providing a CPU which does not provide either
74
+ TrustZone or the Virtualization Extensions: if you want these you
75
+ must enable them with ``-machine secure=on`` and ``-machine
76
+ virtualization=on``
77
+- QEMU provides 4 virtio-mmio virtio transports; these start at
78
+ address ``0x10013000`` for ``vexpress-a9`` and at ``0x1c130000`` for
79
+ ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is
80
+ provided on the command line then QEMU will edit it to include
81
+ suitable entries describing these transports for the guest.
82
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
83
index XXXXXXX..XXXXXXX 100644
84
--- a/docs/system/target-arm.rst
85
+++ b/docs/system/target-arm.rst
86
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
87
arm/integratorcp
88
arm/realview
89
arm/versatile
90
+ arm/vexpress
91
arm/musicpal
92
arm/nseries
93
arm/orangepi
94
diff --git a/MAINTAINERS b/MAINTAINERS
95
index XXXXXXX..XXXXXXX 100644
96
--- a/MAINTAINERS
97
+++ b/MAINTAINERS
98
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
99
L: qemu-arm@nongnu.org
100
S: Maintained
101
F: hw/arm/vexpress.c
102
+F: docs/system/arm/vexpress.rst
103
104
Versatile PB
105
M: Peter Maydell <peter.maydell@linaro.org>
106
--
107
2.20.1
108
109
diff view generated by jsdifflib
New patch
[PULL 05/29] docs/system: Document the various MPS2 models
1
Add basic documentation of the MPS2 board models.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-5-peter.maydell@linaro.org
8
---
9
docs/system/arm/mps2.rst | 29 +++++++++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
11
MAINTAINERS | 1 +
12
3 files changed, 31 insertions(+)
13
create mode 100644 docs/system/arm/mps2.rst
14
15
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/mps2.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
22
+================================================================================
23
+
24
+These board models all use Arm M-profile CPUs.
25
+
26
+The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
27
+FPGA but is otherwise the same as the 2). Since the CPU itself
28
+and most of the devices are in the FPGA, the details of the board
29
+as seen by the guest depend significantly on the FPGA image.
30
+
31
+QEMU models the following FPGA images:
32
+
33
+``mps2-an385``
34
+ Cortex-M3 as documented in ARM Application Note AN385
35
+``mps2-an511``
36
+ Cortex-M3 'DesignStart' as documented in AN511
37
+``mps2-an505``
38
+ Cortex-M33 as documented in ARM Application Note AN505
39
+``mps2-an521``
40
+ Dual Cortex-M33 as documented in Application Note AN521
41
+
42
+Differences between QEMU and real hardware:
43
+
44
+- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
45
+ block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
46
+ if zbt_boot_ctrl is always zero)
47
+- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
48
+ visible difference is that the LAN9118 doesn't support checksum
49
+ offloading
50
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
51
index XXXXXXX..XXXXXXX 100644
52
--- a/docs/system/target-arm.rst
53
+++ b/docs/system/target-arm.rst
54
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
55
:maxdepth: 1
56
57
arm/integratorcp
58
+ arm/mps2
59
arm/realview
60
arm/versatile
61
arm/vexpress
62
diff --git a/MAINTAINERS b/MAINTAINERS
63
index XXXXXXX..XXXXXXX 100644
64
--- a/MAINTAINERS
65
+++ b/MAINTAINERS
66
@@ -XXX,XX +XXX,XX @@ F: hw/misc/armsse-cpuid.c
67
F: include/hw/misc/armsse-cpuid.h
68
F: hw/misc/armsse-mhu.c
69
F: include/hw/misc/armsse-mhu.h
70
+F: docs/system/arm/mps2.rst
71
72
Musca
73
M: Peter Maydell <peter.maydell@linaro.org>
74
--
75
2.20.1
76
77
diff view generated by jsdifflib
New patch
[PULL 06/29] docs/system: Document Musca boards
1
Provide a minimal documentation of the Musca boards.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200507151819.28444-6-peter.maydell@linaro.org
8
---
9
docs/system/arm/musca.rst | 31 +++++++++++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
11
MAINTAINERS | 1 +
12
3 files changed, 33 insertions(+)
13
create mode 100644 docs/system/arm/musca.rst
14
15
diff --git a/docs/system/arm/musca.rst b/docs/system/arm/musca.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/musca.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Arm Musca boards (``musca-a``, ``musca-b1``)
22
+============================================
23
+
24
+The Arm Musca development boards are a reference implementation
25
+of a system using the SSE-200 Subsystem for Embedded. They are
26
+dual Cortex-M33 systems.
27
+
28
+QEMU provides models of the A and B1 variants of this board.
29
+
30
+Unimplemented devices:
31
+
32
+- SPI
33
+- |I2C|
34
+- |I2S|
35
+- PWM
36
+- QSPI
37
+- Timer
38
+- SCC
39
+- GPIO
40
+- eFlash
41
+- MHU
42
+- PVT
43
+- SDIO
44
+- CryptoCell
45
+
46
+Note that (like the real hardware) the Musca-A machine is
47
+asymmetric: CPU 0 does not have the FPU or DSP extensions,
48
+but CPU 1 does. Also like the real hardware, the memory maps
49
+for the A and B1 variants differ significantly, so guest
50
+software must be built for the right variant.
51
+
52
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
53
index XXXXXXX..XXXXXXX 100644
54
--- a/docs/system/target-arm.rst
55
+++ b/docs/system/target-arm.rst
56
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
57
58
arm/integratorcp
59
arm/mps2
60
+ arm/musca
61
arm/realview
62
arm/versatile
63
arm/vexpress
64
diff --git a/MAINTAINERS b/MAINTAINERS
65
index XXXXXXX..XXXXXXX 100644
66
--- a/MAINTAINERS
67
+++ b/MAINTAINERS
68
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
69
L: qemu-arm@nongnu.org
70
S: Maintained
71
F: hw/arm/musca.c
72
+F: docs/system/arm/musca.rst
73
74
Musicpal
75
M: Jan Kiszka <jan.kiszka@web.de>
76
--
77
2.20.1
78
79
diff view generated by jsdifflib
New patch
[PULL 07/29] linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
1
In linux-user/arm/cpu-loop.c we incorrectly treat EXCP_BKPT similarly
2
to EXCP_SWI, which means that if the guest executes a BKPT insn then
3
QEMU will perform a syscall for it (which syscall depends on what
4
value happens to be in r7...). The correct behaviour is that the
5
guest process should take a SIGTRAP.
1
6
7
This code has been like this (more or less) since commit
8
06c949e62a098f in 2006 which added BKPT in the first place. This is
9
probably because at the time the same code path was used to handle
10
both Linux syscalls and semihosting calls, and (on M profile) BKPT
11
with a suitable magic number is used for semihosting calls. But
12
these days we've moved handling of semihosting out to an entirely
13
different codepath, so we can fix this bug by simply removing this
14
handling of EXCP_BKPT and instead making it deliver a SIGTRAP like
15
EXCP_DEBUG (as we do already on aarch64).
16
17
Reported-by: <omerg681@gmail.com>
18
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Message-id: 20200420212206.12776-2-peter.maydell@linaro.org
22
Fixes: https://bugs.launchpad.net/qemu/+bug/1873898
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
linux-user/arm/cpu_loop.c | 30 ++++++++----------------------
26
1 file changed, 8 insertions(+), 22 deletions(-)
27
28
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/linux-user/arm/cpu_loop.c
31
+++ b/linux-user/arm/cpu_loop.c
32
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
33
}
34
break;
35
case EXCP_SWI:
36
- case EXCP_BKPT:
37
{
38
env->eabi = 1;
39
/* system call */
40
- if (trapnr == EXCP_BKPT) {
41
- if (env->thumb) {
42
- /* FIXME - what to do if get_user() fails? */
43
- get_user_code_u16(insn, env->regs[15], env);
44
- n = insn & 0xff;
45
- env->regs[15] += 2;
46
- } else {
47
- /* FIXME - what to do if get_user() fails? */
48
- get_user_code_u32(insn, env->regs[15], env);
49
- n = (insn & 0xf) | ((insn >> 4) & 0xff0);
50
- env->regs[15] += 4;
51
- }
52
+ if (env->thumb) {
53
+ /* FIXME - what to do if get_user() fails? */
54
+ get_user_code_u16(insn, env->regs[15] - 2, env);
55
+ n = insn & 0xff;
56
} else {
57
- if (env->thumb) {
58
- /* FIXME - what to do if get_user() fails? */
59
- get_user_code_u16(insn, env->regs[15] - 2, env);
60
- n = insn & 0xff;
61
- } else {
62
- /* FIXME - what to do if get_user() fails? */
63
- get_user_code_u32(insn, env->regs[15] - 4, env);
64
- n = insn & 0xffffff;
65
- }
66
+ /* FIXME - what to do if get_user() fails? */
67
+ get_user_code_u32(insn, env->regs[15] - 4, env);
68
+ n = insn & 0xffffff;
69
}
70
71
if (n == ARM_NR_cacheflush) {
72
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
73
}
74
break;
75
case EXCP_DEBUG:
76
+ case EXCP_BKPT:
77
excp_debug:
78
info.si_signo = TARGET_SIGTRAP;
79
info.si_errno = 0;
80
--
81
2.20.1
82
83
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
[PULL 08/29] linux-user/arm: Remove bogus SVC 0xf0002 handling
1
Add some assertions that if we're about to boot an AArch64 kernel,
1
We incorrectly treat SVC 0xf0002 as a cacheflush request (which is a
2
the board code has not mistakenly set either secure_boot or
2
NOP for QEMU). This is the wrong syscall number, because in the
3
secure_board_setup. It doesn't make sense to set secure_boot,
3
svc-immediate OABI syscall numbers are all offset by the
4
because all AArch64 kernels must be booted in non-secure mode.
4
ARM_SYSCALL_BASE value and so the correct insn is SVC 0x9f0002.
5
(This is handled further down in the code with the other Arm-specific
6
syscalls like NR_breakpoint.)
5
7
6
It might in theory make sense to set secure_board_setup, but
8
When this code was initially added in commit 6f1f31c069b20611 in
7
we don't currently support that, because only the AArch32
9
2004, ARM_NR_cacheflush was defined as (ARM_SYSCALL_BASE + 0xf0000 + 2)
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
10
so the value in the comparison took account of the extra 0x900000
9
Since we don't have a current need for this functionality, just
11
offset. In commit fbb4a2e371f2fa7 in 2008, the ARM_SYSCALL_BASE
10
assert that we don't try to use it. If it's needed we'll add
12
was removed from the definition of ARM_NR_cacheflush and handling
11
it later.
13
for this group of syscalls was added below the point where we subtract
14
ARM_SYSCALL_BASE from the SVC immediate value. However that commit
15
forgot to remove the now-obsolete earlier handling code.
16
17
Remove the spurious ARM_NR_cacheflush condition.
12
18
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
21
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
22
Message-id: 20200420212206.12776-3-peter.maydell@linaro.org
16
---
23
---
17
hw/arm/boot.c | 7 +++++++
24
linux-user/arm/cpu_loop.c | 4 +---
18
1 file changed, 7 insertions(+)
25
1 file changed, 1 insertion(+), 3 deletions(-)
19
26
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
27
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
21
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
29
--- a/linux-user/arm/cpu_loop.c
23
+++ b/hw/arm/boot.c
30
+++ b/linux-user/arm/cpu_loop.c
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
31
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
25
} else {
32
n = insn & 0xffffff;
26
env->pstate = PSTATE_MODE_EL1h;
27
}
28
+ /* AArch64 kernels never boot in secure mode */
29
+ assert(!info->secure_boot);
30
+ /* This hook is only supported for AArch32 currently:
31
+ * bootloader_aarch64[] will not call the hook, and
32
+ * the code above has already dropped us into EL2 or EL1.
33
+ */
34
+ assert(!info->secure_board_setup);
35
}
33
}
36
34
37
/* Set to non-secure if not a secure boot */
35
- if (n == ARM_NR_cacheflush) {
36
- /* nop */
37
- } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
38
+ if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
39
/* linux syscall */
40
if (env->thumb || n == 0) {
41
n = env->regs[7];
38
--
42
--
39
2.16.2
43
2.20.1
40
44
41
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
[PULL 09/29] linux-user/arm: Handle invalid arm-specific syscalls correctly
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
The kernel has different handling for syscalls with invalid
2
code for keeping the secondary CPUs in a pen needs to have
2
numbers that are in the "arm-specific" range 0x9f0000 and up:
3
a version for A64 as well as A32. Without this, the
3
* 0x9f0000..0x9f07ff return -ENOSYS if not implemented
4
secondary CPUs go into an infinite loop of taking undefined
4
* other out of range syscalls cause a SIGILL
5
instruction exceptions.
5
(see the kernel's arch/arm/kernel/traps.c:arm_syscall())
6
7
Implement this distinction. (Note that our code doesn't look
8
quite like the kernel's, because we have removed the
9
0x900000 prefix by this point, whereas the kernel retains
10
it in arm_syscall().)
6
11
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
14
Message-id: 20200420212206.12776-4-peter.maydell@linaro.org
10
---
15
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
16
linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++----
12
1 file changed, 40 insertions(+), 1 deletion(-)
17
1 file changed, 26 insertions(+), 4 deletions(-)
13
18
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
19
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
21
--- a/linux-user/arm/cpu_loop.c
17
+++ b/hw/arm/raspi.c
22
+++ b/linux-user/arm/cpu_loop.c
18
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
24
env->regs[0] = cpu_get_tls(env);
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
25
break;
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
26
default:
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
27
- qemu_log_mask(LOG_UNIMP,
23
28
- "qemu: Unsupported ARM syscall: 0x%x\n",
24
/* Table of Linux board IDs for different Pi versions */
29
- n);
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
30
- env->regs[0] = -TARGET_ENOSYS;
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
31
+ if (n < 0xf0800) {
27
info->smp_loader_start);
32
+ /*
28
}
33
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
29
34
+ * 0x9f07ff in OABI numbering) are defined
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
35
+ * to return -ENOSYS rather than raising
31
+{
36
+ * SIGILL. Note that we have already
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
37
+ * removed the 0x900000 prefix.
33
+ * The mechanism for doing the spin-table is also entirely different.
38
+ */
34
+ * We must have four 64-bit fields at absolute addresses
39
+ qemu_log_mask(LOG_UNIMP,
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
40
+ "qemu: Unsupported ARM syscall: 0x%x\n",
36
+ * our CPUs, and which we must ensure are zero initialized before
41
+ n);
37
+ * the primary CPU goes into the kernel. We put these variables inside
42
+ env->regs[0] = -TARGET_ENOSYS;
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
43
+ } else {
39
+ */
44
+ /* Otherwise SIGILL */
40
+ static const uint32_t smpboot[] = {
45
+ info.si_signo = TARGET_SIGILL;
41
+ 0xd2801b05, /* mov x5, 0xd8 */
46
+ info.si_errno = 0;
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
47
+ info.si_code = TARGET_ILL_ILLTRP;
43
+ 0x924004c6, /* and x6, x6, #0x3 */
48
+ info._sifields._sigfault._addr = env->regs[15];
44
+ 0xd503205f, /* spin: wfe */
49
+ if (env->thumb) {
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
50
+ info._sifields._sigfault._addr -= 2;
46
+ 0xb4ffffc4, /* cbz x4, spin */
51
+ } else {
47
+ 0xd2800000, /* mov x0, #0x0 */
52
+ info._sifields._sigfault._addr -= 4;
48
+ 0xd2800001, /* mov x1, #0x0 */
53
+ }
49
+ 0xd2800002, /* mov x2, #0x0 */
54
+ queue_signal(env, info.si_signo,
50
+ 0xd2800003, /* mov x3, #0x0 */
55
+ QEMU_SI_FAULT, &info);
51
+ 0xd61f0080, /* br x4 */
56
+ }
52
+ };
57
break;
53
+
58
}
54
+ static const uint64_t spintables[] = {
59
} else {
55
+ 0, 0, 0, 0
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
63
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
65
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
68
/* Pi2 and Pi3 requires SMP setup */
69
if (version >= 2) {
70
binfo.smp_loader_start = SMPBOOT_ADDR;
71
- binfo.write_secondary_boot = write_smpboot;
72
+ if (version == 2) {
73
+ binfo.write_secondary_boot = write_smpboot;
74
+ } else {
75
+ binfo.write_secondary_boot = write_smpboot64;
76
+ }
77
binfo.secondary_cpu_reset_hook = reset_secondary;
78
}
79
80
--
60
--
81
2.16.2
61
2.20.1
82
62
83
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
[PULL 10/29] linux-user/arm: Fix identification of syscall numbers
1
If we're directly booting a Linux kernel and the CPU supports both
1
Our code to identify syscall numbers has some issues:
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
2
* for Thumb mode, we never need the immediate value from the insn,
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
3
but we always read it anyway
4
instruction is enabled rather than UNDEFing. Otherwise at least some
4
* bad immediate values in the svc insn should cause a SIGILL, but we
5
kernels will panic when trying to initialize KVM in the guest.
5
were abort()ing instead (via "goto error")
6
7
We can fix both these things by refactoring the code that identifies
8
the syscall number to more closely follow the kernel COMPAT_OABI code:
9
* for Thumb it is always r7
10
* for Arm, if the immediate value is 0, then this is an EABI call
11
with the syscall number in r7
12
* otherwise, we XOR the immediate value with 0x900000
13
(ARM_SYSCALL_BASE for QEMU; __NR_OABI_SYSCALL_BASE in the kernel),
14
which converts valid syscall immediates into the desired value,
15
and puts all invalid immediates in the range 0x100000 or above
16
* then we can just let the existing "value too large, deliver
17
SIGILL" case handle invalid numbers, and drop the 'goto error'
6
18
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
21
Message-id: 20200420212206.12776-5-peter.maydell@linaro.org
9
---
22
---
10
hw/arm/boot.c | 5 +++++
23
linux-user/arm/cpu_loop.c | 143 ++++++++++++++++++++------------------
11
1 file changed, 5 insertions(+)
24
1 file changed, 77 insertions(+), 66 deletions(-)
12
25
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
26
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
28
--- a/linux-user/arm/cpu_loop.c
16
+++ b/hw/arm/boot.c
29
+++ b/linux-user/arm/cpu_loop.c
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
30
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
18
assert(!info->secure_board_setup);
31
env->eabi = 1;
19
}
32
/* system call */
20
33
if (env->thumb) {
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
34
- /* FIXME - what to do if get_user() fails? */
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
35
- get_user_code_u16(insn, env->regs[15] - 2, env);
23
+ env->cp15.scr_el3 |= SCR_HCE;
36
- n = insn & 0xff;
37
+ /* Thumb is always EABI style with syscall number in r7 */
38
+ n = env->regs[7];
39
} else {
40
+ /*
41
+ * Equivalent of kernel CONFIG_OABI_COMPAT: read the
42
+ * Arm SVC insn to extract the immediate, which is the
43
+ * syscall number in OABI.
44
+ */
45
/* FIXME - what to do if get_user() fails? */
46
get_user_code_u32(insn, env->regs[15] - 4, env);
47
n = insn & 0xffffff;
48
- }
49
-
50
- if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
51
- /* linux syscall */
52
- if (env->thumb || n == 0) {
53
+ if (n == 0) {
54
+ /* zero immediate: EABI, syscall number in r7 */
55
n = env->regs[7];
56
} else {
57
- n -= ARM_SYSCALL_BASE;
58
+ /*
59
+ * This XOR matches the kernel code: an immediate
60
+ * in the valid range (0x900000 .. 0x9fffff) is
61
+ * converted into the correct EABI-style syscall
62
+ * number; invalid immediates end up as values
63
+ * > 0xfffff and are handled below as out-of-range.
64
+ */
65
+ n ^= ARM_SYSCALL_BASE;
66
env->eabi = 0;
67
}
68
- if ( n > ARM_NR_BASE) {
69
- switch (n) {
70
- case ARM_NR_cacheflush:
71
- /* nop */
72
- break;
73
- case ARM_NR_set_tls:
74
- cpu_set_tls(env, env->regs[0]);
75
- env->regs[0] = 0;
76
- break;
77
- case ARM_NR_breakpoint:
78
- env->regs[15] -= env->thumb ? 2 : 4;
79
- goto excp_debug;
80
- case ARM_NR_get_tls:
81
- env->regs[0] = cpu_get_tls(env);
82
- break;
83
- default:
84
- if (n < 0xf0800) {
85
- /*
86
- * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
87
- * 0x9f07ff in OABI numbering) are defined
88
- * to return -ENOSYS rather than raising
89
- * SIGILL. Note that we have already
90
- * removed the 0x900000 prefix.
91
- */
92
- qemu_log_mask(LOG_UNIMP,
93
- "qemu: Unsupported ARM syscall: 0x%x\n",
94
- n);
95
- env->regs[0] = -TARGET_ENOSYS;
24
+ }
96
+ }
25
+
97
+
26
/* Set to non-secure if not a secure boot */
98
+ if (n > ARM_NR_BASE) {
27
if (!info->secure_boot &&
99
+ switch (n) {
28
(cs != first_cpu || !info->secure_board_setup)) {
100
+ case ARM_NR_cacheflush:
101
+ /* nop */
102
+ break;
103
+ case ARM_NR_set_tls:
104
+ cpu_set_tls(env, env->regs[0]);
105
+ env->regs[0] = 0;
106
+ break;
107
+ case ARM_NR_breakpoint:
108
+ env->regs[15] -= env->thumb ? 2 : 4;
109
+ goto excp_debug;
110
+ case ARM_NR_get_tls:
111
+ env->regs[0] = cpu_get_tls(env);
112
+ break;
113
+ default:
114
+ if (n < 0xf0800) {
115
+ /*
116
+ * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
117
+ * 0x9f07ff in OABI numbering) are defined
118
+ * to return -ENOSYS rather than raising
119
+ * SIGILL. Note that we have already
120
+ * removed the 0x900000 prefix.
121
+ */
122
+ qemu_log_mask(LOG_UNIMP,
123
+ "qemu: Unsupported ARM syscall: 0x%x\n",
124
+ n);
125
+ env->regs[0] = -TARGET_ENOSYS;
126
+ } else {
127
+ /*
128
+ * Otherwise SIGILL. This includes any SWI with
129
+ * immediate not originally 0x9fxxxx, because
130
+ * of the earlier XOR.
131
+ */
132
+ info.si_signo = TARGET_SIGILL;
133
+ info.si_errno = 0;
134
+ info.si_code = TARGET_ILL_ILLTRP;
135
+ info._sifields._sigfault._addr = env->regs[15];
136
+ if (env->thumb) {
137
+ info._sifields._sigfault._addr -= 2;
138
} else {
139
- /* Otherwise SIGILL */
140
- info.si_signo = TARGET_SIGILL;
141
- info.si_errno = 0;
142
- info.si_code = TARGET_ILL_ILLTRP;
143
- info._sifields._sigfault._addr = env->regs[15];
144
- if (env->thumb) {
145
- info._sifields._sigfault._addr -= 2;
146
- } else {
147
- info._sifields._sigfault._addr -= 4;
148
- }
149
- queue_signal(env, info.si_signo,
150
- QEMU_SI_FAULT, &info);
151
+ info._sifields._sigfault._addr -= 4;
152
}
153
- break;
154
- }
155
- } else {
156
- ret = do_syscall(env,
157
- n,
158
- env->regs[0],
159
- env->regs[1],
160
- env->regs[2],
161
- env->regs[3],
162
- env->regs[4],
163
- env->regs[5],
164
- 0, 0);
165
- if (ret == -TARGET_ERESTARTSYS) {
166
- env->regs[15] -= env->thumb ? 2 : 4;
167
- } else if (ret != -TARGET_QEMU_ESIGRETURN) {
168
- env->regs[0] = ret;
169
+ queue_signal(env, info.si_signo,
170
+ QEMU_SI_FAULT, &info);
171
}
172
+ break;
173
}
174
} else {
175
- goto error;
176
+ ret = do_syscall(env,
177
+ n,
178
+ env->regs[0],
179
+ env->regs[1],
180
+ env->regs[2],
181
+ env->regs[3],
182
+ env->regs[4],
183
+ env->regs[5],
184
+ 0, 0);
185
+ if (ret == -TARGET_ERESTARTSYS) {
186
+ env->regs[15] -= env->thumb ? 2 : 4;
187
+ } else if (ret != -TARGET_QEMU_ESIGRETURN) {
188
+ env->regs[0] = ret;
189
+ }
190
}
191
}
192
break;
29
--
193
--
30
2.16.2
194
2.20.1
31
195
32
196
diff view generated by jsdifflib
New patch
[PULL 11/29] target/arm: Remove unused GEN_NEON_INTEGER_OP macro
1
The GEN_NEON_INTEGER_OP macro is no longer used; remove it.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/arm/translate.c | 23 -----------------------
7
1 file changed, 23 deletions(-)
8
9
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/arm/translate.c
12
+++ b/target/arm/translate.c
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
14
default: return 1; \
15
}} while (0)
16
17
-#define GEN_NEON_INTEGER_OP(name) do { \
18
- switch ((size << 1) | u) { \
19
- case 0: \
20
- gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
21
- break; \
22
- case 1: \
23
- gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
24
- break; \
25
- case 2: \
26
- gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
27
- break; \
28
- case 3: \
29
- gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
30
- break; \
31
- case 4: \
32
- gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
33
- break; \
34
- case 5: \
35
- gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
36
- break; \
37
- default: return 1; \
38
- }} while (0)
39
-
40
static TCGv_i32 neon_load_scratch(int scratch)
41
{
42
TCGv_i32 tmp = tcg_temp_new_i32();
43
--
44
2.20.1
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
[PULL 12/29] hw: Move i.MX watchdog driver to hw/watchdog
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Guenter Roeck <linux@roeck-us.net>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
In preparation for a full implementation, move i.MX watchdog driver
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
4
from hw/misc to hw/watchdog. While at it, add the watchdog files
5
controller which is supported in QEMU using the imx_fec.c module
5
to MAINTAINERS.
6
(actually called imx.enet for this model.)
7
6
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
imx.enet device like this:
10
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
12
#define FSL_IMX6_ENET_MAC_IRQ 119
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
9
Message-id: 20200517162135.110364-2-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
11
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
12
include/hw/arm/fsl-imx6.h | 2 +-
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
13
include/hw/arm/fsl-imx6ul.h | 2 +-
46
2 files changed, 29 insertions(+), 3 deletions(-)
14
include/hw/arm/fsl-imx7.h | 2 +-
15
include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} | 0
16
hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} | 2 +-
17
MAINTAINERS | 2 ++
18
hw/arm/Kconfig | 3 +++
19
hw/misc/Makefile.objs | 1 -
20
hw/watchdog/Kconfig | 3 +++
21
hw/watchdog/Makefile.objs | 1 +
22
10 files changed, 13 insertions(+), 5 deletions(-)
23
rename include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} (100%)
24
rename hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} (98%)
47
25
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
26
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
49
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
28
--- a/include/hw/arm/fsl-imx6.h
51
+++ b/include/hw/arm/fsl-imx6.h
29
+++ b/include/hw/arm/fsl-imx6.h
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
30
@@ -XXX,XX +XXX,XX @@
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
31
#include "hw/cpu/a9mpcore.h"
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
32
#include "hw/misc/imx6_ccm.h"
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
33
#include "hw/misc/imx6_src.h"
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
34
-#include "hw/misc/imx2_wdt.h"
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
35
+#include "hw/watchdog/wdt_imx2.h"
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
36
#include "hw/char/imx_serial.h"
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
37
#include "hw/timer/imx_gpt.h"
60
#define FSL_IMX6_PCIE1_IRQ 120
38
#include "hw/timer/imx_epit.h"
61
#define FSL_IMX6_PCIE2_IRQ 121
39
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
41
--- a/include/hw/arm/fsl-imx6ul.h
66
+++ b/hw/net/imx_fec.c
42
+++ b/include/hw/arm/fsl-imx6ul.h
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
43
@@ -XXX,XX +XXX,XX @@
68
44
#include "hw/misc/imx7_snvs.h"
69
static void imx_eth_update(IMXFECState *s)
45
#include "hw/misc/imx7_gpr.h"
70
{
46
#include "hw/intc/imx_gpcv2.h"
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
47
-#include "hw/misc/imx2_wdt.h"
72
+ /*
48
+#include "hw/watchdog/wdt_imx2.h"
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
49
#include "hw/gpio/imx_gpio.h"
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
50
#include "hw/char/imx_serial.h"
75
+ * and older) since Linux associated both interrupt lines with Ethernet
51
#include "hw/timer/imx_gpt.h"
76
+ * MAC interrupts. Specifically,
52
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
53
index XXXXXXX..XXXXXXX 100644
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
54
--- a/include/hw/arm/fsl-imx7.h
79
+ * with swapped interrupt assignments.
55
+++ b/include/hw/arm/fsl-imx7.h
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
56
@@ -XXX,XX +XXX,XX @@
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
57
#include "hw/misc/imx7_snvs.h"
82
+ * work, though that is accidental.
58
#include "hw/misc/imx7_gpr.h"
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
59
#include "hw/misc/imx6_src.h"
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
60
-#include "hw/misc/imx2_wdt.h"
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
61
+#include "hw/watchdog/wdt_imx2.h"
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
62
#include "hw/gpio/imx_gpio.h"
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
63
#include "hw/char/imx_serial.h"
88
+ * Linux instead received MAC interrupts on the timer interrupt.
64
#include "hw/timer/imx_gpt.h"
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
65
diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/watchdog/wdt_imx2.h
90
+ * albeit accidentally, but qemu versions with the correct interrupt
66
similarity index 100%
91
+ * assignment fail.
67
rename from include/hw/misc/imx2_wdt.h
92
+ *
68
rename to include/hw/watchdog/wdt_imx2.h
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
69
diff --git a/hw/misc/imx2_wdt.c b/hw/watchdog/wdt_imx2.c
94
+ * interrrupts on both interrupt lines. This should be changed if and when
70
similarity index 98%
95
+ * qemu supports IOMUX.
71
rename from hw/misc/imx2_wdt.c
96
+ */
72
rename to hw/watchdog/wdt_imx2.c
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
73
index XXXXXXX..XXXXXXX 100644
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
74
--- a/hw/misc/imx2_wdt.c
99
qemu_set_irq(s->irq[1], 1);
75
+++ b/hw/watchdog/wdt_imx2.c
100
} else {
76
@@ -XXX,XX +XXX,XX @@
101
qemu_set_irq(s->irq[1], 0);
77
#include "qemu/module.h"
78
#include "sysemu/watchdog.h"
79
80
-#include "hw/misc/imx2_wdt.h"
81
+#include "hw/watchdog/wdt_imx2.h"
82
83
#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
84
#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
85
diff --git a/MAINTAINERS b/MAINTAINERS
86
index XXXXXXX..XXXXXXX 100644
87
--- a/MAINTAINERS
88
+++ b/MAINTAINERS
89
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
90
F: hw/arm/fsl-imx25.c
91
F: hw/arm/imx25_pdk.c
92
F: hw/misc/imx25_ccm.c
93
+F: hw/watchdog/wdt_imx2.c
94
F: include/hw/arm/fsl-imx25.h
95
F: include/hw/misc/imx25_ccm.h
96
+F: include/hw/watchdog/wdt_imx2.h
97
98
i.MX31 (kzm)
99
M: Peter Chubb <peter.chubb@nicta.com.au>
100
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/arm/Kconfig
103
+++ b/hw/arm/Kconfig
104
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
105
select IMX_FEC
106
select IMX_I2C
107
select IMX_USBPHY
108
+ select WDT_IMX2
109
select SDHCI
110
111
config ASPEED_SOC
112
@@ -XXX,XX +XXX,XX @@ config FSL_IMX7
113
select IMX
114
select IMX_FEC
115
select IMX_I2C
116
+ select WDT_IMX2
117
select PCI_EXPRESS_DESIGNWARE
118
select SDHCI
119
select UNIMP
120
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
121
select IMX
122
select IMX_FEC
123
select IMX_I2C
124
+ select WDT_IMX2
125
select SDHCI
126
select UNIMP
127
128
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/misc/Makefile.objs
131
+++ b/hw/misc/Makefile.objs
132
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx6_ccm.o
133
common-obj-$(CONFIG_IMX) += imx6ul_ccm.o
134
obj-$(CONFIG_IMX) += imx6_src.o
135
common-obj-$(CONFIG_IMX) += imx7_ccm.o
136
-common-obj-$(CONFIG_IMX) += imx2_wdt.o
137
common-obj-$(CONFIG_IMX) += imx7_snvs.o
138
common-obj-$(CONFIG_IMX) += imx7_gpr.o
139
common-obj-$(CONFIG_IMX) += imx_rngc.o
140
diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig
141
index XXXXXXX..XXXXXXX 100644
142
--- a/hw/watchdog/Kconfig
143
+++ b/hw/watchdog/Kconfig
144
@@ -XXX,XX +XXX,XX @@ config WDT_IB700
145
146
config WDT_DIAG288
147
bool
148
+
149
+config WDT_IMX2
150
+ bool
151
diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/watchdog/Makefile.objs
154
+++ b/hw/watchdog/Makefile.objs
155
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
156
common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
157
common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
158
common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
159
+common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o
102
--
160
--
103
2.16.2
161
2.20.1
104
162
105
163
diff view generated by jsdifflib
New patch
[PULL 13/29] hw/watchdog: Implement full i.MX watchdog support
1
1
From: Guenter Roeck <linux@roeck-us.net>
2
3
Implement full support for the watchdog in i.MX systems.
4
Pretimeout support is optional because the watchdog hardware
5
on i.MX31 does not support pretimeouts.
6
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-3-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/watchdog/wdt_imx2.h | 61 ++++++++-
13
hw/watchdog/wdt_imx2.c | 239 +++++++++++++++++++++++++++++++--
14
2 files changed, 285 insertions(+), 15 deletions(-)
15
16
diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/watchdog/wdt_imx2.h
19
+++ b/include/hw/watchdog/wdt_imx2.h
20
@@ -XXX,XX +XXX,XX @@
21
#ifndef IMX2_WDT_H
22
#define IMX2_WDT_H
23
24
+#include "qemu/bitops.h"
25
#include "hw/sysbus.h"
26
+#include "hw/irq.h"
27
+#include "hw/ptimer.h"
28
29
#define TYPE_IMX2_WDT "imx2.wdt"
30
#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
31
32
enum IMX2WdtRegisters {
33
- IMX2_WDT_WCR = 0x0000,
34
- IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1,
35
+ IMX2_WDT_WCR = 0x0000, /* Control Register */
36
+ IMX2_WDT_WSR = 0x0002, /* Service Register */
37
+ IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
38
+ IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
39
+ IMX2_WDT_WMCR = 0x0008, /* Misc Register */
40
};
41
42
+#define IMX2_WDT_MMIO_SIZE 0x000a
43
+
44
+/* Control Register definitions */
45
+#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
46
+#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */
47
+#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */
48
+#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */
49
+#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */
50
+#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
51
+#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
52
+#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
53
+
54
+#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
55
+ | IMX2_WDT_WCR_WDW)
56
+
57
+/* Service Register definitions */
58
+#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */
59
+#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */
60
+
61
+/* Reset Status Register definitions */
62
+#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */
63
+#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */
64
+
65
+/* Interrupt Control Register definitions */
66
+#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
67
+#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */
68
+#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */
69
+#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */
70
+
71
+#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
72
+
73
+/* Misc Control Register definitions */
74
+#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
75
76
typedef struct IMX2WdtState {
77
/* <private> */
78
SysBusDevice parent_obj;
79
80
+ /*< public >*/
81
MemoryRegion mmio;
82
+ qemu_irq irq;
83
+
84
+ struct ptimer_state *timer;
85
+ struct ptimer_state *itimer;
86
+
87
+ bool pretimeout_support;
88
+ bool wicr_locked;
89
+
90
+ uint16_t wcr;
91
+ uint16_t wsr;
92
+ uint16_t wrsr;
93
+ uint16_t wicr;
94
+ uint16_t wmcr;
95
+
96
+ bool wcr_locked; /* affects WDZST, WDBG, and WDW */
97
+ bool wcr_wde_locked; /* affects WDE */
98
+ bool wcr_wdt_locked; /* affects WDT (never cleared) */
99
} IMX2WdtState;
100
101
#endif /* IMX2_WDT_H */
102
diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/watchdog/wdt_imx2.c
105
+++ b/hw/watchdog/wdt_imx2.c
106
@@ -XXX,XX +XXX,XX @@
107
#include "qemu/bitops.h"
108
#include "qemu/module.h"
109
#include "sysemu/watchdog.h"
110
+#include "migration/vmstate.h"
111
+#include "hw/qdev-properties.h"
112
113
#include "hw/watchdog/wdt_imx2.h"
114
115
-#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
116
-#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
117
-
118
-static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
119
- unsigned int size)
120
+static void imx2_wdt_interrupt(void *opaque)
121
{
122
+ IMX2WdtState *s = IMX2_WDT(opaque);
123
+
124
+ s->wicr |= IMX2_WDT_WICR_WTIS;
125
+ qemu_set_irq(s->irq, 1);
126
+}
127
+
128
+static void imx2_wdt_expired(void *opaque)
129
+{
130
+ IMX2WdtState *s = IMX2_WDT(opaque);
131
+
132
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
133
+
134
+ /* Perform watchdog action if watchdog is enabled */
135
+ if (s->wcr & IMX2_WDT_WCR_WDE) {
136
+ s->wrsr = IMX2_WDT_WRSR_TOUT;
137
+ watchdog_perform_action();
138
+ }
139
+}
140
+
141
+static void imx2_wdt_reset(DeviceState *dev)
142
+{
143
+ IMX2WdtState *s = IMX2_WDT(dev);
144
+
145
+ ptimer_transaction_begin(s->timer);
146
+ ptimer_stop(s->timer);
147
+ ptimer_transaction_commit(s->timer);
148
+
149
+ if (s->pretimeout_support) {
150
+ ptimer_transaction_begin(s->itimer);
151
+ ptimer_stop(s->itimer);
152
+ ptimer_transaction_commit(s->itimer);
153
+ }
154
+
155
+ s->wicr_locked = false;
156
+ s->wcr_locked = false;
157
+ s->wcr_wde_locked = false;
158
+
159
+ s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS;
160
+ s->wsr = 0;
161
+ s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW);
162
+ s->wicr = IMX2_WDT_WICR_WICT_DEF;
163
+ s->wmcr = IMX2_WDT_WMCR_PDE;
164
+}
165
+
166
+static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size)
167
+{
168
+ IMX2WdtState *s = IMX2_WDT(opaque);
169
+
170
+ switch (addr) {
171
+ case IMX2_WDT_WCR:
172
+ return s->wcr;
173
+ case IMX2_WDT_WSR:
174
+ return s->wsr;
175
+ case IMX2_WDT_WRSR:
176
+ return s->wrsr;
177
+ case IMX2_WDT_WICR:
178
+ return s->wicr;
179
+ case IMX2_WDT_WMCR:
180
+ return s->wmcr;
181
+ }
182
return 0;
183
}
184
185
+static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start)
186
+{
187
+ bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT);
188
+ bool enabled = s->wicr & IMX2_WDT_WICR_WIE;
189
+
190
+ ptimer_transaction_begin(s->itimer);
191
+ if (start || !enabled) {
192
+ ptimer_stop(s->itimer);
193
+ }
194
+ if (running && enabled) {
195
+ int count = ptimer_get_count(s->timer);
196
+ int pretimeout = s->wicr & IMX2_WDT_WICR_WICT;
197
+
198
+ /*
199
+ * Only (re-)start pretimeout timer if its counter value is larger
200
+ * than 0. Otherwise it will fire right away and we'll get an
201
+ * interrupt loop.
202
+ */
203
+ if (count > pretimeout) {
204
+ ptimer_set_count(s->itimer, count - pretimeout);
205
+ if (start) {
206
+ ptimer_run(s->itimer, 1);
207
+ }
208
+ }
209
+ }
210
+ ptimer_transaction_commit(s->itimer);
211
+}
212
+
213
+static void imx_wdt2_update_timer(IMX2WdtState *s, bool start)
214
+{
215
+ ptimer_transaction_begin(s->timer);
216
+ if (start) {
217
+ ptimer_stop(s->timer);
218
+ }
219
+ if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) {
220
+ int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8;
221
+
222
+ /* A value of 0 reflects one period (0.5s). */
223
+ ptimer_set_count(s->timer, count + 1);
224
+ if (start) {
225
+ ptimer_run(s->timer, 1);
226
+ }
227
+ }
228
+ ptimer_transaction_commit(s->timer);
229
+ if (s->pretimeout_support) {
230
+ imx_wdt2_update_itimer(s, start);
231
+ }
232
+}
233
+
234
static void imx2_wdt_write(void *opaque, hwaddr addr,
235
uint64_t value, unsigned int size)
236
{
237
- if (addr == IMX2_WDT_WCR &&
238
- (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
239
- watchdog_perform_action();
240
+ IMX2WdtState *s = IMX2_WDT(opaque);
241
+
242
+ switch (addr) {
243
+ case IMX2_WDT_WCR:
244
+ if (s->wcr_locked) {
245
+ value &= ~IMX2_WDT_WCR_LOCK_MASK;
246
+ value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK);
247
+ }
248
+ s->wcr_locked = true;
249
+ if (s->wcr_wde_locked) {
250
+ value &= ~IMX2_WDT_WCR_WDE;
251
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDE);
252
+ } else if (value & IMX2_WDT_WCR_WDE) {
253
+ s->wcr_wde_locked = true;
254
+ }
255
+ if (s->wcr_wdt_locked) {
256
+ value &= ~IMX2_WDT_WCR_WDT;
257
+ value |= (s->wicr & ~IMX2_WDT_WCR_WDT);
258
+ } else if (value & IMX2_WDT_WCR_WDT) {
259
+ s->wcr_wdt_locked = true;
260
+ }
261
+
262
+ s->wcr = value;
263
+ if (!(value & IMX2_WDT_WCR_SRS)) {
264
+ s->wrsr = IMX2_WDT_WRSR_SFTW;
265
+ }
266
+ if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) ||
267
+ (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) {
268
+ watchdog_perform_action();
269
+ }
270
+ s->wcr |= IMX2_WDT_WCR_SRS;
271
+ imx_wdt2_update_timer(s, true);
272
+ break;
273
+ case IMX2_WDT_WSR:
274
+ if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) {
275
+ imx_wdt2_update_timer(s, false);
276
+ }
277
+ s->wsr = value;
278
+ break;
279
+ case IMX2_WDT_WRSR:
280
+ break;
281
+ case IMX2_WDT_WICR:
282
+ if (!s->pretimeout_support) {
283
+ return;
284
+ }
285
+ value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS;
286
+ if (s->wicr_locked) {
287
+ value &= IMX2_WDT_WICR_WTIS;
288
+ value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK);
289
+ }
290
+ s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS);
291
+ if (value & IMX2_WDT_WICR_WTIS) {
292
+ s->wicr &= ~IMX2_WDT_WICR_WTIS;
293
+ qemu_set_irq(s->irq, 0);
294
+ }
295
+ imx_wdt2_update_itimer(s, true);
296
+ s->wicr_locked = true;
297
+ break;
298
+ case IMX2_WDT_WMCR:
299
+ s->wmcr = value & IMX2_WDT_WMCR_PDE;
300
+ break;
301
}
302
}
303
304
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx2_wdt_ops = {
305
* real device but in practice there is no reason for a guest
306
* to access this device unaligned.
307
*/
308
- .min_access_size = 4,
309
- .max_access_size = 4,
310
+ .min_access_size = 2,
311
+ .max_access_size = 2,
312
.unaligned = false,
313
},
314
};
315
316
+static const VMStateDescription vmstate_imx2_wdt = {
317
+ .name = "imx2.wdt",
318
+ .fields = (VMStateField[]) {
319
+ VMSTATE_PTIMER(timer, IMX2WdtState),
320
+ VMSTATE_PTIMER(itimer, IMX2WdtState),
321
+ VMSTATE_BOOL(wicr_locked, IMX2WdtState),
322
+ VMSTATE_BOOL(wcr_locked, IMX2WdtState),
323
+ VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState),
324
+ VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState),
325
+ VMSTATE_UINT16(wcr, IMX2WdtState),
326
+ VMSTATE_UINT16(wsr, IMX2WdtState),
327
+ VMSTATE_UINT16(wrsr, IMX2WdtState),
328
+ VMSTATE_UINT16(wmcr, IMX2WdtState),
329
+ VMSTATE_UINT16(wicr, IMX2WdtState),
330
+ VMSTATE_END_OF_LIST()
331
+ }
332
+};
333
+
334
static void imx2_wdt_realize(DeviceState *dev, Error **errp)
335
{
336
IMX2WdtState *s = IMX2_WDT(dev);
337
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
338
339
memory_region_init_io(&s->mmio, OBJECT(dev),
340
&imx2_wdt_ops, s,
341
- TYPE_IMX2_WDT".mmio",
342
- IMX2_WDT_REG_NUM * sizeof(uint16_t));
343
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
344
+ TYPE_IMX2_WDT,
345
+ IMX2_WDT_MMIO_SIZE);
346
+ sysbus_init_mmio(sbd, &s->mmio);
347
+ sysbus_init_irq(sbd, &s->irq);
348
+
349
+ s->timer = ptimer_init(imx2_wdt_expired, s,
350
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
351
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
352
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
353
+ ptimer_transaction_begin(s->timer);
354
+ ptimer_set_freq(s->timer, 2);
355
+ ptimer_set_limit(s->timer, 0xff, 1);
356
+ ptimer_transaction_commit(s->timer);
357
+ if (s->pretimeout_support) {
358
+ s->itimer = ptimer_init(imx2_wdt_interrupt, s,
359
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
360
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
361
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
362
+ ptimer_transaction_begin(s->itimer);
363
+ ptimer_set_freq(s->itimer, 2);
364
+ ptimer_set_limit(s->itimer, 0xff, 1);
365
+ ptimer_transaction_commit(s->itimer);
366
+ }
367
}
368
369
+static Property imx2_wdt_properties[] = {
370
+ DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support,
371
+ false),
372
+};
373
+
374
static void imx2_wdt_class_init(ObjectClass *klass, void *data)
375
{
376
DeviceClass *dc = DEVICE_CLASS(klass);
377
378
+ device_class_set_props(dc, imx2_wdt_properties);
379
dc->realize = imx2_wdt_realize;
380
+ dc->reset = imx2_wdt_reset;
381
+ dc->vmsd = &vmstate_imx2_wdt;
382
+ dc->desc = "i.MX watchdog timer";
383
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
384
}
385
386
--
387
2.20.1
388
389
diff view generated by jsdifflib
New patch
[PULL 14/29] hw/arm/fsl-imx25: Wire up watchdog
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
With this commit, the watchdog on imx25-pdk is fully operational,
4
including pretimeout support.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-4-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx25.h | 5 +++++
12
hw/arm/fsl-imx25.c | 10 ++++++++++
13
hw/arm/Kconfig | 1 +
14
3 files changed, 16 insertions(+)
15
16
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx25.h
19
+++ b/include/hw/arm/fsl-imx25.h
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/gpio/imx_gpio.h"
22
#include "hw/sd/sdhci.h"
23
#include "hw/usb/chipidea.h"
24
+#include "hw/watchdog/wdt_imx2.h"
25
#include "exec/memory.h"
26
#include "target/arm/cpu.h"
27
28
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
29
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
30
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
31
ChipideaState usb[FSL_IMX25_NUM_USBS];
32
+ IMX2WdtState wdt;
33
MemoryRegion rom[2];
34
MemoryRegion iram;
35
MemoryRegion iram_alias;
36
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
37
#define FSL_IMX25_GPIO1_SIZE 0x4000
38
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
39
#define FSL_IMX25_GPIO2_SIZE 0x4000
40
+#define FSL_IMX25_WDT_ADDR 0x53FDC000
41
+#define FSL_IMX25_WDT_SIZE 0x4000
42
#define FSL_IMX25_USB1_ADDR 0x53FF4000
43
#define FSL_IMX25_USB1_SIZE 0x0200
44
#define FSL_IMX25_USB2_ADDR 0x53FF4400
45
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
46
#define FSL_IMX25_ESDHC2_IRQ 8
47
#define FSL_IMX25_USB1_IRQ 37
48
#define FSL_IMX25_USB2_IRQ 35
49
+#define FSL_IMX25_WDT_IRQ 55
50
51
#endif /* FSL_IMX25_H */
52
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/fsl-imx25.c
55
+++ b/hw/arm/fsl-imx25.c
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
57
TYPE_CHIPIDEA);
58
}
59
60
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
61
}
62
63
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
64
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
65
usb_table[i].irq));
66
}
67
68
+ /* Watchdog */
69
+ object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
70
+ &error_abort);
71
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
72
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
73
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
74
+ qdev_get_gpio_in(DEVICE(&s->avic),
75
+ FSL_IMX25_WDT_IRQ));
76
+
77
/* initialize 2 x 16 KB ROM */
78
memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
79
FSL_IMX25_ROM0_SIZE, &err);
80
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/Kconfig
83
+++ b/hw/arm/Kconfig
84
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
85
select IMX
86
select IMX_FEC
87
select IMX_I2C
88
+ select WDT_IMX2
89
select DS1338
90
91
config FSL_IMX31
92
--
93
2.20.1
94
95
diff view generated by jsdifflib
New patch
[PULL 15/29] hw/arm/fsl-imx31: Wire up watchdog
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
With this patch, the watchdog on i.MX31 emulations is fully operational.
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
7
Message-id: 20200517162135.110364-5-linux@roeck-us.net
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/arm/fsl-imx31.h | 4 ++++
11
hw/arm/fsl-imx31.c | 6 ++++++
12
hw/arm/Kconfig | 1 +
13
3 files changed, 11 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx31.h
18
+++ b/include/hw/arm/fsl-imx31.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/timer/imx_epit.h"
21
#include "hw/i2c/imx_i2c.h"
22
#include "hw/gpio/imx_gpio.h"
23
+#include "hw/watchdog/wdt_imx2.h"
24
#include "exec/memory.h"
25
#include "target/arm/cpu.h"
26
27
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
28
IMXEPITState epit[FSL_IMX31_NUM_EPITS];
29
IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
30
IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
31
+ IMX2WdtState wdt;
32
MemoryRegion secure_rom;
33
MemoryRegion rom;
34
MemoryRegion iram;
35
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX31State {
36
#define FSL_IMX31_GPIO1_SIZE 0x4000
37
#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
38
#define FSL_IMX31_GPIO2_SIZE 0x4000
39
+#define FSL_IMX31_WDT_ADDR 0x53FDC000
40
+#define FSL_IMX31_WDT_SIZE 0x4000
41
#define FSL_IMX31_AVIC_ADDR 0x68000000
42
#define FSL_IMX31_AVIC_SIZE 0x100
43
#define FSL_IMX31_SDRAM0_ADDR 0x80000000
44
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/fsl-imx31.c
47
+++ b/hw/arm/fsl-imx31.c
48
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_init(Object *obj)
49
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
50
TYPE_IMX_GPIO);
51
}
52
+
53
+ sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
54
}
55
56
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
57
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
58
gpio_table[i].irq));
59
}
60
61
+ /* Watchdog */
62
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
63
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
64
+
65
/* On a real system, the first 16k is a `secure boot rom' */
66
memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
67
FSL_IMX31_SECURE_ROM_SIZE, &err);
68
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/Kconfig
71
+++ b/hw/arm/Kconfig
72
@@ -XXX,XX +XXX,XX @@ config FSL_IMX31
73
select SERIAL
74
select IMX
75
select IMX_I2C
76
+ select WDT_IMX2
77
select LAN9118
78
79
config FSL_IMX6
80
--
81
2.20.1
82
83
diff view generated by jsdifflib
New patch
[PULL 16/29] hw/arm/fsl-imx6: Connect watchdog interrupts
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
With this patch applied, the watchdog in the sabrelite emulation
4
is fully operational, including pretimeout support.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-6-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/fsl-imx6.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6.c
17
+++ b/hw/arm/fsl-imx6.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
19
FSL_IMX6_WDOG1_ADDR,
20
FSL_IMX6_WDOG2_ADDR,
21
};
22
+ static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
23
+ FSL_IMX6_WDOG1_IRQ,
24
+ FSL_IMX6_WDOG2_IRQ,
25
+ };
26
27
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
28
+ &error_abort);
29
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
30
&error_abort);
31
32
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
33
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
34
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
35
+ FSL_IMX6_WDOGn_IRQ[i]));
36
}
37
38
/* ROM memory */
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
New patch
[PULL 17/29] hw/arm/fsl-imx6ul: Connect watchdog interrupts
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
With this commit, the watchdog on mcimx6ul-evk is fully operational,
4
including pretimeout support.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-7-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/fsl-imx6ul.c | 10 ++++++++++
12
1 file changed, 10 insertions(+)
13
14
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/fsl-imx6ul.c
17
+++ b/hw/arm/fsl-imx6ul.c
18
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
19
FSL_IMX6UL_WDOG2_ADDR,
20
FSL_IMX6UL_WDOG3_ADDR,
21
};
22
+ static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
23
+ FSL_IMX6UL_WDOG1_IRQ,
24
+ FSL_IMX6UL_WDOG2_IRQ,
25
+ FSL_IMX6UL_WDOG3_IRQ,
26
+ };
27
28
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
29
+ &error_abort);
30
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
31
&error_abort);
32
33
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
34
FSL_IMX6UL_WDOGn_ADDR[i]);
35
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
36
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
37
+ FSL_IMX6UL_WDOGn_IRQ[i]));
38
}
39
40
/*
41
--
42
2.20.1
43
44
diff view generated by jsdifflib
New patch
[PULL 18/29] hw/arm/fsl-imx7: Instantiate various unimplemented devices
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
Instantiating PWM, CAN, CAAM, and OCOTP devices is necessary to avoid
4
crashes when booting mainline Linux.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20200517162135.110364-8-linux@roeck-us.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx7.h | 16 ++++++++++++++++
12
hw/arm/fsl-imx7.c | 24 ++++++++++++++++++++++++
13
2 files changed, 40 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
20
FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
21
FSL_IMX7_IOMUXCn_SIZE = 0x1000,
22
23
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
24
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
25
+
26
FSL_IMX7_ANALOG_ADDR = 0x30360000,
27
FSL_IMX7_SNVS_ADDR = 0x30370000,
28
FSL_IMX7_CCM_ADDR = 0x30380000,
29
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
30
FSL_IMX7_ADC2_ADDR = 0x30620000,
31
FSL_IMX7_ADCn_SIZE = 0x1000,
32
33
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
34
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
35
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
36
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
37
+ FSL_IMX7_PWMn_SIZE = 0x10000,
38
+
39
FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
40
FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
41
42
FSL_IMX7_GPC_ADDR = 0x303A0000,
43
44
+ FSL_IMX7_CAAM_ADDR = 0x30900000,
45
+ FSL_IMX7_CAAM_SIZE = 0x40000,
46
+
47
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
48
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
49
+ FSL_IMX7_CANn_SIZE = 0x10000,
50
+
51
FSL_IMX7_I2C1_ADDR = 0x30A20000,
52
FSL_IMX7_I2C2_ADDR = 0x30A30000,
53
FSL_IMX7_I2C3_ADDR = 0x30A40000,
54
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/fsl-imx7.c
57
+++ b/hw/arm/fsl-imx7.c
58
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
59
*/
60
create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
61
62
+ /*
63
+ * CAAM
64
+ */
65
+ create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
66
+
67
+ /*
68
+ * PWM
69
+ */
70
+ create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
71
+ create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
72
+ create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
73
+ create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
74
+
75
+ /*
76
+ * CAN
77
+ */
78
+ create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
79
+ create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
80
+
81
+ /*
82
+ * OCOTP
83
+ */
84
+ create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
85
+ FSL_IMX7_OCOTP_SIZE);
86
87
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
88
&error_abort);
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
New patch
[PULL 19/29] hw/arm/fsl-imx7: Connect watchdog interrupts
1
From: Guenter Roeck <linux@roeck-us.net>
1
2
3
i.MX7 supports watchdog pretimeout interupts. With this commit,
4
the watchdog in mcimx7d-sabre is fully operational, including
5
pretimeout support.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20200517162135.110364-9-linux@roeck-us.net
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/fsl-imx7.h | 5 +++++
13
hw/arm/fsl-imx7.c | 11 +++++++++++
14
2 files changed, 16 insertions(+)
15
16
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/fsl-imx7.h
19
+++ b/include/hw/arm/fsl-imx7.h
20
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
21
FSL_IMX7_USB2_IRQ = 42,
22
FSL_IMX7_USB3_IRQ = 40,
23
24
+ FSL_IMX7_WDOG1_IRQ = 78,
25
+ FSL_IMX7_WDOG2_IRQ = 79,
26
+ FSL_IMX7_WDOG3_IRQ = 10,
27
+ FSL_IMX7_WDOG4_IRQ = 109,
28
+
29
FSL_IMX7_PCI_INTA_IRQ = 125,
30
FSL_IMX7_PCI_INTB_IRQ = 124,
31
FSL_IMX7_PCI_INTC_IRQ = 123,
32
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/fsl-imx7.c
35
+++ b/hw/arm/fsl-imx7.c
36
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
37
FSL_IMX7_WDOG3_ADDR,
38
FSL_IMX7_WDOG4_ADDR,
39
};
40
+ static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
41
+ FSL_IMX7_WDOG1_IRQ,
42
+ FSL_IMX7_WDOG2_IRQ,
43
+ FSL_IMX7_WDOG3_IRQ,
44
+ FSL_IMX7_WDOG4_IRQ,
45
+ };
46
47
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
48
+ &error_abort);
49
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
50
&error_abort);
51
52
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
53
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
54
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
55
+ FSL_IMX7_WDOGn_IRQ[i]));
56
}
57
58
/*
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
New patch
[PULL 20/29] hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
hw_error() calls exit(). This a bit overkill when we can log
4
the accesses as unimplemented or guest error.
5
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200518140309.5220-2-f4bug@amsat.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/integratorcp.c | 23 +++++++++++++++--------
15
1 file changed, 15 insertions(+), 8 deletions(-)
16
17
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/integratorcp.c
20
+++ b/hw/arm/integratorcp.c
21
@@ -XXX,XX +XXX,XX @@
22
#include "exec/address-spaces.h"
23
#include "sysemu/runstate.h"
24
#include "sysemu/sysemu.h"
25
+#include "qemu/log.h"
26
#include "qemu/error-report.h"
27
#include "hw/char/pl011.h"
28
#include "hw/hw.h"
29
@@ -XXX,XX +XXX,XX @@ static uint64_t integratorcm_read(void *opaque, hwaddr offset,
30
/* ??? Voltage control unimplemented. */
31
return 0;
32
default:
33
- hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
34
- (int)offset);
35
+ qemu_log_mask(LOG_UNIMP,
36
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
37
+ __func__, offset);
38
return 0;
39
}
40
}
41
@@ -XXX,XX +XXX,XX @@ static void integratorcm_write(void *opaque, hwaddr offset,
42
/* ??? Voltage control unimplemented. */
43
break;
44
default:
45
- hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
46
- (int)offset);
47
+ qemu_log_mask(LOG_UNIMP,
48
+ "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
49
+ __func__, offset);
50
break;
51
}
52
}
53
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_pic_read(void *opaque, hwaddr offset,
54
case 5: /* INT_SOFTCLR */
55
case 11: /* FRQ_ENABLECLR */
56
default:
57
- printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
58
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
59
+ __func__, offset);
60
return 0;
61
}
62
}
63
@@ -XXX,XX +XXX,XX @@ static void icp_pic_write(void *opaque, hwaddr offset,
64
case 8: /* FRQ_STATUS */
65
case 9: /* FRQ_RAWSTAT */
66
default:
67
- printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
68
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
69
+ __func__, offset);
70
return;
71
}
72
icp_pic_update(s);
73
@@ -XXX,XX +XXX,XX @@ static uint64_t icp_control_read(void *opaque, hwaddr offset,
74
case 3: /* CP_DECODE */
75
return 0x11;
76
default:
77
- hw_error("icp_control_read: Bad offset %x\n", (int)offset);
78
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
79
+ __func__, offset);
80
return 0;
81
}
82
}
83
@@ -XXX,XX +XXX,XX @@ static void icp_control_write(void *opaque, hwaddr offset,
84
/* Nothing interesting implemented yet. */
85
break;
86
default:
87
- hw_error("icp_control_write: Bad offset %x\n", (int)offset);
88
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
89
+ __func__, offset);
90
}
91
}
92
93
--
94
2.20.1
95
96
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
[PULL 21/29] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
some differences. Notably, the MPIDR affinity aff1 values it
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
2
6
Rather than trying to have one device with properties that
3
hw_error() calls exit(). This a bit overkill when we can log
7
configure it differently for the two cases, create two
4
the accesses as unimplemented or guest error.
8
separate QOM devices for the two SoCs. We use the same approach
9
as hw/arm/aspeed_soc.c and share code and have a data table
10
that might differ per-SoC. For the moment the two types don't
11
actually have different behaviour.
12
5
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200518140309.5220-3-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
---
13
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
14
hw/arm/pxa2xx_gpio.c | 7 ++++---
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
15
hw/display/pxa2xx_lcd.c | 8 +++++---
19
hw/arm/raspi.c | 3 ++-
16
hw/dma/pxa2xx_dma.c | 14 +++++++++-----
20
3 files changed, 53 insertions(+), 6 deletions(-)
17
3 files changed, 18 insertions(+), 11 deletions(-)
21
18
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
19
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
23
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
21
--- a/hw/arm/pxa2xx_gpio.c
25
+++ b/include/hw/arm/bcm2836.h
22
+++ b/hw/arm/pxa2xx_gpio.c
26
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
27
24
28
#define BCM283X_NCPUS 4
25
#include "qemu/osdep.h"
29
26
#include "cpu.h"
30
+/* These type names are for specific SoCs; other than instantiating
27
-#include "hw/hw.h"
31
+ * them, code using these devices should always handle them via the
28
#include "hw/irq.h"
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
29
#include "hw/qdev-properties.h"
33
+ */
30
#include "hw/sysbus.h"
34
+#define TYPE_BCM2836 "bcm2836"
31
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
35
+#define TYPE_BCM2837 "bcm2837"
32
return s->status[bank];
36
+
33
37
typedef struct BCM283XState {
34
default:
38
/*< private >*/
35
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
39
DeviceState parent_obj;
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
37
+ __func__, offset);
41
BCM2835PeripheralState peripherals;
38
}
42
} BCM283XState;
39
43
40
return 0;
44
+typedef struct BCM283XInfo BCM283XInfo;
41
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
45
+
42
break;
46
+typedef struct BCM283XClass {
43
47
+ DeviceClass parent_class;
44
default:
48
+ const BCM283XInfo *info;
45
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
49
+} BCM283XClass;
46
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
50
+
47
+ __func__, offset);
51
+#define BCM283X_CLASS(klass) \
48
}
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
49
}
53
+#define BCM283X_GET_CLASS(obj) \
50
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
51
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
55
+
56
#endif /* BCM2836_H */
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
58
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/bcm2836.c
53
--- a/hw/display/pxa2xx_lcd.c
60
+++ b/hw/arm/bcm2836.c
54
+++ b/hw/display/pxa2xx_lcd.c
61
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
56
*/
63
#define BCM2836_CONTROL_BASE 0x40000000
57
64
58
#include "qemu/osdep.h"
65
+struct BCM283XInfo {
59
-#include "hw/hw.h"
66
+ const char *name;
60
+#include "qemu/log.h"
67
+};
61
#include "hw/irq.h"
68
+
62
#include "migration/vmstate.h"
69
+static const BCM283XInfo bcm283x_socs[] = {
63
#include "ui/console.h"
70
+ {
64
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
71
+ .name = TYPE_BCM2836,
65
72
+ },
66
default:
73
+ {
67
fail:
74
+ .name = TYPE_BCM2837,
68
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
75
+ },
69
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
76
+};
70
+ __func__, offset);
77
+
71
}
78
static void bcm2836_init(Object *obj)
72
79
{
73
return 0;
80
BCM283XState *s = BCM283X(obj);
74
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
75
82
DEFINE_PROP_END_OF_LIST()
76
default:
83
};
77
fail:
84
78
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
79
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
80
+ __func__, offset);
87
{
81
}
88
DeviceClass *dc = DEVICE_CLASS(oc);
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
82
}
96
83
97
-static const TypeInfo bcm2836_type_info = {
84
diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
98
+static const TypeInfo bcm283x_type_info = {
85
index XXXXXXX..XXXXXXX 100644
99
.name = TYPE_BCM283X,
86
--- a/hw/dma/pxa2xx_dma.c
100
.parent = TYPE_DEVICE,
87
+++ b/hw/dma/pxa2xx_dma.c
101
.instance_size = sizeof(BCM283XState),
88
@@ -XXX,XX +XXX,XX @@
102
.instance_init = bcm2836_init,
89
*/
103
- .class_init = bcm2836_class_init,
90
104
+ .class_size = sizeof(BCM283XClass),
91
#include "qemu/osdep.h"
105
+ .abstract = true,
92
+#include "qemu/log.h"
106
};
93
#include "hw/hw.h"
107
94
#include "hw/irq.h"
108
static void bcm2836_register_types(void)
95
#include "hw/qdev-properties.h"
109
{
96
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
110
- type_register_static(&bcm2836_type_info);
97
unsigned int channel;
111
+ int i;
98
112
+
99
if (size != 4) {
113
+ type_register_static(&bcm283x_type_info);
100
- hw_error("%s: Bad access width\n", __func__);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
101
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
115
+ TypeInfo ti = {
102
+ __func__, size);
116
+ .name = bcm283x_socs[i].name,
103
return 5;
117
+ .parent = TYPE_BCM283X,
104
}
118
+ .class_init = bcm283x_class_init,
105
119
+ .class_data = (void *) &bcm283x_socs[i],
106
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
120
+ };
107
return s->chan[channel].cmd;
121
+ type_register(&ti);
108
}
122
+ }
109
}
110
-
111
- hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
112
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
113
+ __func__, offset);
114
return 7;
123
}
115
}
124
116
125
type_init(bcm2836_register_types)
117
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
118
unsigned int channel;
127
index XXXXXXX..XXXXXXX 100644
119
128
--- a/hw/arm/raspi.c
120
if (size != 4) {
129
+++ b/hw/arm/raspi.c
121
- hw_error("%s: Bad access width\n", __func__);
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
122
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
131
BusState *bus;
123
+ __func__, size);
132
DeviceState *carddev;
124
return;
133
125
}
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
126
135
+ object_initialize(&s->soc, sizeof(s->soc),
127
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
128
break;
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
129
}
138
&error_abort);
130
fail:
131
- hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
132
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
133
+ __func__, offset);
134
}
135
}
139
136
140
--
137
--
141
2.16.2
138
2.20.1
142
139
143
140
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
[PULL 22/29] hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
hw_error() calls exit(). This a bit overkill when we can log
4
it is needed to support guests other than Linux.
4
the accesses as unimplemented or guest error.
5
5
6
Based on the patch by Bill Paul as found here:
6
When fuzzing the devices, we don't want the whole process to
7
https://bugs.launchpad.net/qemu/+bug/1753314
7
exit. Replace some hw_error() calls by qemu_log_mask().
8
8
9
Cc: qemu-devel@nongnu.org
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Cc: qemu-arm@nongnu.org
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Cc: Bill Paul <wpaul@windriver.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20200518140309.5220-4-f4bug@amsat.org
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
14
---
19
include/hw/char/imx_serial.h | 3 +++
15
hw/char/xilinx_uartlite.c | 5 +++--
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
16
1 file changed, 3 insertions(+), 2 deletions(-)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
17
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
18
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
20
--- a/hw/char/xilinx_uartlite.c
26
+++ b/include/hw/char/imx_serial.h
21
+++ b/hw/char/xilinx_uartlite.c
27
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
23
*/
29
#define UCR2_SRST (1<<0) /* Reset complete */
24
30
25
#include "qemu/osdep.h"
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
26
-#include "hw/hw.h"
32
+
27
+#include "qemu/log.h"
33
#define UTS1_TXEMPTY (1<<6)
28
#include "hw/irq.h"
34
#define UTS1_RXEMPTY (1<<5)
29
#include "hw/qdev-properties.h"
35
#define UTS1_TXFULL (1<<4)
30
#include "hw/sysbus.h"
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
31
@@ -XXX,XX +XXX,XX @@ uart_write(void *opaque, hwaddr addr,
37
uint32_t ubmr;
32
switch (addr)
38
uint32_t ubrc;
33
{
39
uint32_t ucr3;
34
case R_STATUS:
40
+ uint32_t ucr4;
35
- hw_error("write to UART STATUS?\n");
41
36
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
42
qemu_irq irq;
37
+ __func__);
43
CharBackend chr;
38
break;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
39
45
index XXXXXXX..XXXXXXX 100644
40
case R_CTRL:
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
98
break;
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
100
s->ucr3 = value & 0xffff;
101
break;
102
103
- case 0x2d: /* UTS1 */
104
case 0x23: /* UCR4 */
105
+ s->ucr4 = value & 0xffff;
106
+ imx_update(s);
107
+ break;
108
+
109
+ case 0x2d: /* UTS1 */
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
112
/* TODO */
113
--
41
--
114
2.16.2
42
2.20.1
115
43
116
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
[PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
just hard-code the CPU type they use rather than having it passed
3
through as an object property. This then lets us put the initialization
4
of the CPU object in init rather than realize.
5
2
6
Note that this change means that it's no longer possible on
3
hw_error() calls exit(). This a bit overkill when we can log
7
the command line to use -cpu to ask for a different kind of
4
the accesses as unimplemented or guest error.
8
CPU than the SoC supports. This was never a supported thing to
9
do anyway; we were just not sanity-checking the command line.
10
5
11
This does require us to only build the bcm2837 object on
6
When fuzzing the devices, we don't want the whole process to
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
7
exit. Replace some hw_error() calls by qemu_log_mask().
13
due to the missing cortex-a53 device and "make check" will fail.
14
8
9
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
10
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
11
the default value on the APB bus is 0.
12
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20200518140309.5220-5-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
17
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
18
hw/timer/exynos4210_mct.c | 12 +++++-------
21
hw/arm/raspi.c | 2 --
19
1 file changed, 5 insertions(+), 7 deletions(-)
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
20
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
21
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
23
--- a/hw/timer/exynos4210_mct.c
27
+++ b/hw/arm/bcm2836.c
24
+++ b/hw/timer/exynos4210_mct.c
28
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@
29
26
30
struct BCM283XInfo {
27
#include "qemu/osdep.h"
31
const char *name;
28
#include "qemu/log.h"
32
+ const char *cpu_type;
29
-#include "hw/hw.h"
33
int clusterid;
30
#include "hw/sysbus.h"
34
};
31
#include "migration/vmstate.h"
35
32
#include "qemu/timer.h"
36
static const BCM283XInfo bcm283x_socs[] = {
33
@@ -XXX,XX +XXX,XX @@
37
{
34
#include "hw/ptimer.h"
38
.name = TYPE_BCM2836,
35
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
36
#include "hw/arm/exynos4210.h"
40
.clusterid = 0xf,
37
-#include "hw/hw.h"
41
},
38
#include "hw/irq.h"
42
+#ifdef TARGET_AARCH64
39
43
{
40
//#define DEBUG_MCT
44
.name = TYPE_BCM2837,
41
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
42
int index;
46
.clusterid = 0x0,
43
int shift;
47
},
44
uint64_t count;
48
+#endif
45
- uint32_t value;
49
};
46
+ uint32_t value = 0;
50
47
int lt_i;
51
static void bcm2836_init(Object *obj)
48
52
{
49
switch (offset) {
53
BCM283XState *s = BCM283X(obj);
50
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
51
break;
55
+ const BCM283XInfo *info = bc->info;
52
56
+ int n;
53
default:
57
+
54
- hw_error("exynos4210.mct: bad read offset "
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
55
- TARGET_FMT_plx "\n", offset);
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
56
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
60
+ info->cpu_type);
57
+ __func__, offset);
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
58
break;
62
+ &error_abort);
59
}
63
+ }
60
return value;
64
61
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
62
break;
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
63
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
64
default:
68
65
- hw_error("exynos4210.mct: bad write offset "
69
/* common peripherals from bcm2835 */
66
- TARGET_FMT_plx "\n", offset);
70
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
71
- obj = OBJECT(dev);
68
+ __func__, offset);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
69
break;
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
70
}
74
- s->cpu_type);
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
71
}
84
85
static Property bcm2836_props[] = {
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
72
--
104
2.16.2
73
2.20.1
105
74
106
75
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
[PULL 24/29] ARM: PL061: Introduce N_GPIOS
1
From: Wei Huang <wei@redhat.com>
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
Add a definition for the number of GPIO lines controlled by a PL061
4
time when guest VM runs. To find the physical base address correctly,
4
instance, and use it instead of the hardcoded magic value 8.
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
5
10
Signed-off-by: Wei Huang <wei@redhat.com>
6
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
7
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200519085143.1376-1-geert+renesas@glider.be
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
dump.c | 14 +++++++++++---
12
hw/gpio/pl061.c | 12 +++++++-----
16
1 file changed, 11 insertions(+), 3 deletions(-)
13
1 file changed, 7 insertions(+), 5 deletions(-)
17
14
18
diff --git a/dump.c b/dump.c
15
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
17
--- a/hw/gpio/pl061.c
21
+++ b/dump.c
18
+++ b/hw/gpio/pl061.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
19
@@ -XXX,XX +XXX,XX @@ static const uint8_t pl061_id_luminary[12] =
23
20
#define TYPE_PL061 "pl061"
24
lines = g_strsplit((char *)vmci, "\n", -1);
21
#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
25
for (i = 0; lines[i]; i++) {
22
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
23
+#define N_GPIOS 8
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
28
+ const char *prefix = NULL;
29
+
24
+
30
+ if (s->dump_info.d_machine == EM_X86_64) {
25
typedef struct PL061State {
31
+ prefix = "NUMBER(phys_base)=";
26
SysBusDevice parent_obj;
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
27
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
28
@@ -XXX,XX +XXX,XX @@ typedef struct PL061State {
34
+ }
29
uint32_t cr;
35
+
30
uint32_t amsel;
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
31
qemu_irq irq;
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
32
- qemu_irq out[8];
38
&phys_base) < 0) {
33
+ qemu_irq out[N_GPIOS];
39
- warn_report("Failed to read NUMBER(phys_base)=");
34
const unsigned char *id;
40
+ warn_report("Failed to read %s", prefix);
35
uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
41
} else {
36
} PL061State;
42
s->dump_info.phys_base = phys_base;
37
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
43
}
38
changed = s->old_out_data ^ out;
39
if (changed) {
40
s->old_out_data = out;
41
- for (i = 0; i < 8; i++) {
42
+ for (i = 0; i < N_GPIOS; i++) {
43
mask = 1 << i;
44
if (changed & mask) {
45
DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
46
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
47
changed = (s->old_in_data ^ s->data) & ~s->dir;
48
if (changed) {
49
s->old_in_data = s->data;
50
- for (i = 0; i < 8; i++) {
51
+ for (i = 0; i < N_GPIOS; i++) {
52
mask = 1 << i;
53
if (changed & mask) {
54
DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
55
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
56
memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
57
sysbus_init_mmio(sbd, &s->iomem);
58
sysbus_init_irq(sbd, &s->irq);
59
- qdev_init_gpio_in(dev, pl061_set_irq, 8);
60
- qdev_init_gpio_out(dev, s->out, 8);
61
+ qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
62
+ qdev_init_gpio_out(dev, s->out, N_GPIOS);
63
}
64
65
static void pl061_class_init(ObjectClass *klass, void *data)
44
--
66
--
45
2.16.2
67
2.20.1
46
68
47
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
[PULL 25/29] target/arm: Use tcg_gen_gvec_mov for clear_vec_high
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
The 8-byte store for the end a !is_q operation can be
4
doesn't really corespond to anything in real hardware and server as a
4
merged with the other stores. Use a no-op vector move
5
kitchensink accumulating events normally reported via USR1 and USR2
5
to trigger the expand_clr portion of tcg_gen_gvec_mov.
6
registers.
7
6
8
Change the code to explicitly evaluate state of interrupts reported
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
via USR1 and USR2 against corresponding masking bits and use the to
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
detemine if IRQ line should be asserted or not.
9
Message-id: 20200519212453.28494-2-richard.henderson@linaro.org
11
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
13
reasons:
14
15
1. Emulation code implements a single character FIFO, so this flag
16
will always be set since characters are trasmitted as a part of
17
the code emulating "push" into the FIFO
18
19
2. imx_update() is really just a function doing ORing and maksing
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
24
Cc: qemu-devel@nongnu.org
25
Cc: qemu-arm@nongnu.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
11
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
12
target/arm/translate-a64.c | 10 ++--------
34
1 file changed, 16 insertions(+), 8 deletions(-)
13
1 file changed, 2 insertions(+), 8 deletions(-)
35
14
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
37
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
17
--- a/target/arm/translate-a64.c
39
+++ b/hw/char/imx_serial.c
18
+++ b/target/arm/translate-a64.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
19
@@ -XXX,XX +XXX,XX @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
41
20
unsigned ofs = fp_reg_offset(s, rd, MO_64);
42
static void imx_update(IMXSerialState *s)
21
unsigned vsz = vec_full_reg_size(s);
43
{
22
44
- uint32_t flags;
23
- if (!is_q) {
45
+ uint32_t usr1;
24
- TCGv_i64 tcg_zero = tcg_const_i64(0);
46
+ uint32_t usr2;
25
- tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
47
+ uint32_t mask;
26
- tcg_temp_free_i64(tcg_zero);
48
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
52
- } else {
53
- flags &= ~USR1_TRDY;
54
- }
27
- }
55
+ /*
28
- if (vsz > 16) {
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
29
- tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
57
+ * UCR1, so we can get away with something as simple as the
30
- }
58
+ * following:
31
+ /* Nop move, with side effect of clearing the tail. */
59
+ */
32
+ tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz);
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
33
}
71
34
72
static void imx_serial_reset(IMXSerialState *s)
35
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
73
--
36
--
74
2.16.2
37
2.20.1
75
38
76
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
[PULL 26/29] target/arm: Use clear_vec_high more effectively
1
Our BCM2836 type is really a generic one that can be any of
1
From: Richard Henderson <richard.henderson@linaro.org>
2
the bcm283x family. Rename it accordingly. We change only
3
the names which are visible via the header file to the
4
rest of the QEMU code, leaving private function names
5
in bcm2836.c as they are.
6
2
7
This is a preliminary to making bcm283x be an abstract
3
Do not explicitly store zero to the NEON high part
8
parent class to specific types for the bcm2836 and bcm2837.
4
when we can pass !is_q to clear_vec_high.
9
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200519212453.28494-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
10
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
11
target/arm/translate-a64.c | 53 +++++++++++++++++++++++---------------
16
hw/arm/bcm2836.c | 17 +++++++++--------
12
1 file changed, 32 insertions(+), 21 deletions(-)
17
hw/arm/raspi.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
13
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
16
--- a/target/arm/translate-a64.c
23
+++ b/include/hw/arm/bcm2836.h
17
+++ b/target/arm/translate-a64.c
24
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
25
#include "hw/arm/bcm2835_peripherals.h"
26
#include "hw/intc/bcm2836_control.h"
27
28
-#define TYPE_BCM2836 "bcm2836"
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
30
+#define TYPE_BCM283X "bcm283x"
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
32
33
-#define BCM2836_NCPUS 4
34
+#define BCM283X_NCPUS 4
35
36
-typedef struct BCM2836State {
37
+typedef struct BCM283XState {
38
/*< private >*/
39
DeviceState parent_obj;
40
/*< public >*/
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
42
char *cpu_type;
43
uint32_t enabled_cpus;
44
45
- ARMCPU cpus[BCM2836_NCPUS];
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
BCM2836ControlState control;
48
BCM2835PeripheralState peripherals;
49
-} BCM2836State;
50
+} BCM283XState;
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
56
+++ b/hw/arm/bcm2836.c
57
@@ -XXX,XX +XXX,XX @@
58
59
static void bcm2836_init(Object *obj)
60
{
19
{
61
- BCM2836State *s = BCM2836(obj);
20
/* This always zero-extends and writes to a full 128 bit wide vector */
62
+ BCM283XState *s = BCM283X(obj);
21
TCGv_i64 tmplo = tcg_temp_new_i64();
63
22
- TCGv_i64 tmphi;
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
23
+ TCGv_i64 tmphi = NULL;
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
24
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
25
if (size < 4) {
67
26
MemOp memop = s->be_data + size;
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
27
- tmphi = tcg_const_i64(0);
69
{
28
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
70
- BCM2836State *s = BCM2836(dev);
29
} else {
71
+ BCM283XState *s = BCM283X(dev);
30
bool be = s->be_data == MO_BE;
72
Object *obj;
31
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
73
Error *err = NULL;
32
}
74
int n;
33
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
34
tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
76
/* common peripherals from bcm2835 */
35
- tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
77
36
-
78
obj = OBJECT(dev);
37
tcg_temp_free_i64(tmplo);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
38
- tcg_temp_free_i64(tmphi);
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
39
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
40
- clear_vec_high(s, true, destidx);
82
s->cpu_type);
41
+ if (tmphi) {
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
42
+ tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
43
+ tcg_temp_free_i64(tmphi);
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
44
+ }
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
45
+ clear_vec_high(s, tmphi != NULL, destidx);
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
46
}
95
47
96
static Property bcm2836_props[] = {
48
/*
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
49
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
50
read_vec_element(s, tcg_resh, rm, 0, MO_64);
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
51
do_ext64(s, tcg_resh, tcg_resl, pos);
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
52
}
101
+ BCM283X_NCPUS),
53
- tcg_gen_movi_i64(tcg_resh, 0);
102
DEFINE_PROP_END_OF_LIST()
54
} else {
103
};
55
TCGv_i64 tcg_hh;
104
56
typedef struct {
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
57
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
58
59
write_vec_element(s, tcg_resl, rd, 0, MO_64);
60
tcg_temp_free_i64(tcg_resl);
61
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
62
+ if (is_q) {
63
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
64
+ }
65
tcg_temp_free_i64(tcg_resh);
66
- clear_vec_high(s, true, rd);
67
+ clear_vec_high(s, is_q, rd);
106
}
68
}
107
69
108
static const TypeInfo bcm2836_type_info = {
70
/* TBL/TBX
109
- .name = TYPE_BCM2836,
71
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
110
+ .name = TYPE_BCM283X,
72
* the input.
111
.parent = TYPE_DEVICE,
73
*/
112
- .instance_size = sizeof(BCM2836State),
74
tcg_resl = tcg_temp_new_i64();
113
+ .instance_size = sizeof(BCM283XState),
75
- tcg_resh = tcg_temp_new_i64();
114
.instance_init = bcm2836_init,
76
+ tcg_resh = NULL;
115
.class_init = bcm2836_class_init,
77
116
};
78
if (is_tblx) {
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
79
read_vec_element(s, tcg_resl, rd, 0, MO_64);
118
index XXXXXXX..XXXXXXX 100644
80
} else {
119
--- a/hw/arm/raspi.c
81
tcg_gen_movi_i64(tcg_resl, 0);
120
+++ b/hw/arm/raspi.c
82
}
121
@@ -XXX,XX +XXX,XX @@
83
- if (is_tblx && is_q) {
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
84
- read_vec_element(s, tcg_resh, rd, 1, MO_64);
123
85
- } else {
124
typedef struct RasPiState {
86
- tcg_gen_movi_i64(tcg_resh, 0);
125
- BCM2836State soc;
87
+
126
+ BCM283XState soc;
88
+ if (is_q) {
127
MemoryRegion ram;
89
+ tcg_resh = tcg_temp_new_i64();
128
} RasPiState;
90
+ if (is_tblx) {
129
91
+ read_vec_element(s, tcg_resh, rd, 1, MO_64);
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
92
+ } else {
131
BusState *bus;
93
+ tcg_gen_movi_i64(tcg_resh, 0);
132
DeviceState *carddev;
94
+ }
133
95
}
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
96
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
97
tcg_idx = tcg_temp_new_i64();
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
98
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
137
&error_abort);
99
138
100
write_vec_element(s, tcg_resl, rd, 0, MO_64);
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
101
tcg_temp_free_i64(tcg_resl);
140
mc->no_floppy = 1;
102
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
141
mc->no_cdrom = 1;
103
- tcg_temp_free_i64(tcg_resh);
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
104
- clear_vec_high(s, true, rd);
143
- mc->max_cpus = BCM2836_NCPUS;
105
+
144
- mc->min_cpus = BCM2836_NCPUS;
106
+ if (is_q) {
145
- mc->default_cpus = BCM2836_NCPUS;
107
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
146
+ mc->max_cpus = BCM283X_NCPUS;
108
+ tcg_temp_free_i64(tcg_resh);
147
+ mc->min_cpus = BCM283X_NCPUS;
109
+ }
148
+ mc->default_cpus = BCM283X_NCPUS;
110
+ clear_vec_high(s, is_q, rd);
149
mc->default_ram_size = 1024 * 1024 * 1024;
150
mc->ignore_memory_transaction_failures = true;
151
};
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
153
mc->no_floppy = 1;
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
111
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
112
113
/* ZIP/UZP/TRN
114
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
115
}
116
117
tcg_resl = tcg_const_i64(0);
118
- tcg_resh = tcg_const_i64(0);
119
+ tcg_resh = is_q ? tcg_const_i64(0) : NULL;
120
tcg_res = tcg_temp_new_i64();
121
122
for (i = 0; i < elements; i++) {
123
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
124
125
write_vec_element(s, tcg_resl, rd, 0, MO_64);
126
tcg_temp_free_i64(tcg_resl);
127
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
128
- tcg_temp_free_i64(tcg_resh);
129
- clear_vec_high(s, true, rd);
130
+
131
+ if (is_q) {
132
+ write_vec_element(s, tcg_resh, rd, 1, MO_64);
133
+ tcg_temp_free_i64(tcg_resh);
134
+ }
135
+ clear_vec_high(s, is_q, rd);
136
}
137
138
/*
165
--
139
--
166
2.16.2
140
2.20.1
167
141
168
142
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
[PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
Using the MSR instruction to write to CPSR.E is deprecated, but it is
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
2
required to work from any mode including unprivileged code. We were
3
but the BCM2386State struct only defines the parent_obj field
3
incorrectly forbidding usermode code from writing it because
4
as DeviceState. This would have caused problems if anything
4
CPSR_USER did not include the CPSR_E bit.
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
5
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
6
We use CPSR_USER in only three places:
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
7
* as the mask of what to allow userspace MSR to write to CPSR
8
provides.
8
* when deciding what bits a linux-user signal-return should be
9
able to write from the sigcontext structure
10
* in target_user_copy_regs() when we set up the initial
11
registers for the linux-user process
12
13
In the first two cases not being able to update CPSR.E is a bug, and
14
in the third case it doesn't matter because CPSR.E is always 0 there.
15
So we can fix both bugs by adding CPSR_E to CPSR_USER.
16
17
Because the cpsr_write() in restore_sigcontext() is now changing
18
a CPSR bit which is cached in hflags, we need to add an
19
arm_rebuild_hflags() call there; the callsite in
20
target_user_copy_regs() was already rebuilding hflags for other
21
reasons.
22
23
(The recommended way to change CPSR.E is to use the 'SETEND'
24
instruction, which we do correctly allow from usermode code.)
9
25
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Message-id: 20200518142801.20503-1-peter.maydell@linaro.org
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
14
---
29
---
15
hw/arm/bcm2836.c | 2 +-
30
target/arm/cpu.h | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
31
linux-user/arm/signal.c | 1 +
32
2 files changed, 2 insertions(+), 1 deletion(-)
17
33
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
34
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
36
--- a/target/arm/cpu.h
21
+++ b/hw/arm/bcm2836.c
37
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
38
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
23
39
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
24
static const TypeInfo bcm2836_type_info = {
40
| CPSR_NZCV)
25
.name = TYPE_BCM2836,
41
/* Bits writable in user mode. */
26
- .parent = TYPE_SYS_BUS_DEVICE,
42
-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
27
+ .parent = TYPE_DEVICE,
43
+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
28
.instance_size = sizeof(BCM2836State),
44
/* Execution state bits. MRS read as zero, MSR writes ignored. */
29
.instance_init = bcm2836_init,
45
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
30
.class_init = bcm2836_class_init,
46
47
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/linux-user/arm/signal.c
50
+++ b/linux-user/arm/signal.c
51
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
52
#ifdef TARGET_CONFIG_CPU_32
53
__get_user(cpsr, &sc->arm_cpsr);
54
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
55
+ arm_rebuild_hflags(env);
56
#endif
57
58
err |= !valid_user_regs(env);
31
--
59
--
32
2.16.2
60
2.20.1
33
61
34
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
[PULL 28/29] linux-user/arm: Reset CPSR_E when entering a signal handler
1
For the rpi1 and 2 we want to boot the Linux kernel via some
1
From: Amanieu d'Antras <amanieu@gmail.com>
2
custom setup code that makes sure that the SMC instruction
3
acts as a no-op, because it's used for cache maintenance.
4
The rpi3 boots AArch64 kernels, which don't need SMC for
5
cache maintenance and always expect to be booted non-secure.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
2
3
This fixes signal handlers running with the wrong endianness if the
4
interrupted code used SETEND to dynamically switch endianness.
5
6
Signed-off-by: Amanieu d'Antras <amanieu@gmail.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200511131117.2486486-1-amanieu@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
10
---
13
hw/arm/raspi.c | 17 +++++++++++++----
11
linux-user/arm/signal.c | 8 +++++++-
14
1 file changed, 13 insertions(+), 4 deletions(-)
12
1 file changed, 7 insertions(+), 1 deletion(-)
15
13
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
16
--- a/linux-user/arm/signal.c
19
+++ b/hw/arm/raspi.c
17
+++ b/linux-user/arm/signal.c
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
18
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
21
binfo.board_id = raspi_boardid[version];
19
} else {
22
binfo.ram_size = ram_size;
20
cpsr &= ~CPSR_T;
23
binfo.nb_cpus = smp_cpus;
21
}
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
22
+ if (env->cp15.sctlr_el[1] & SCTLR_E0E) {
25
- binfo.write_board_setup = write_board_setup;
23
+ cpsr |= CPSR_E;
26
- binfo.secure_board_setup = true;
24
+ } else {
27
- binfo.secure_boot = true;
25
+ cpsr &= ~CPSR_E;
28
+
29
+ if (version <= 2) {
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
31
+ * mode before booting a kernel (to set up the SMC vectors so
32
+ * that we get a no-op SMC; this is used by Linux to call the
33
+ * firmware for some cache maintenance operations.
34
+ * The rpi3 doesn't need this.
35
+ */
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
37
+ binfo.write_board_setup = write_board_setup;
38
+ binfo.secure_board_setup = true;
39
+ binfo.secure_boot = true;
40
+ }
26
+ }
41
27
42
/* Pi2 and Pi3 requires SMP setup */
28
if (ka->sa_flags & TARGET_SA_RESTORER) {
43
if (version >= 2) {
29
if (is_fdpic) {
30
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
31
env->regs[13] = frame_addr;
32
env->regs[14] = retcode;
33
env->regs[15] = handler & (thumb ? ~1 : ~3);
34
- cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr);
35
+ cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr);
36
+ arm_rebuild_hflags(env);
37
38
return 0;
39
}
44
--
40
--
45
2.16.2
41
2.20.1
46
42
47
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
[PULL 29/29] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
The Arm signal-handling code has some parts ifdeffed with a
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
2
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
3
is required for Linux to boot.
3
from when this code's structure was based on the Linux kernel
4
signal handling code, where it was intended to support 26-bit
5
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
6
4da8b8208eded0ba21e3 in 2009.
7
8
QEMU has never had 26-bit CPU support and is unlikely to ever
9
add it; we certainly aren't going to support 26-bit Linux
10
binaries via linux-user mode. The ifdef is just unhelpful
11
noise, so remove it entirely.
4
12
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20200518143014.20689-1-peter.maydell@linaro.org
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
9
---
16
---
10
hw/arm/bcm2836.c | 11 +++++++----
17
linux-user/arm/signal.c | 6 ------
11
1 file changed, 7 insertions(+), 4 deletions(-)
18
1 file changed, 6 deletions(-)
12
19
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
20
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
22
--- a/linux-user/arm/signal.c
16
+++ b/hw/arm/bcm2836.c
23
+++ b/linux-user/arm/signal.c
17
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ struct rt_sigframe_v2
18
25
abi_ulong retcode[4];
19
struct BCM283XInfo {
20
const char *name;
21
+ int clusterid;
22
};
26
};
23
27
24
static const BCM283XInfo bcm283x_socs[] = {
28
-#define TARGET_CONFIG_CPU_32 1
25
{
29
-
26
.name = TYPE_BCM2836,
30
/*
27
+ .clusterid = 0xf,
31
* For ARM syscalls, we encode the syscall number into the instruction.
28
},
32
*/
29
{
33
@@ -XXX,XX +XXX,XX @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
30
.name = TYPE_BCM2837,
34
__put_user(env->regs[13], &sc->arm_sp);
31
+ .clusterid = 0x0,
35
__put_user(env->regs[14], &sc->arm_lr);
32
},
36
__put_user(env->regs[15], &sc->arm_pc);
33
};
37
-#ifdef TARGET_CONFIG_CPU_32
34
38
__put_user(cpsr_read(env), &sc->arm_cpsr);
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
39
-#endif
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
40
37
{
41
__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);
38
BCM283XState *s = BCM283X(dev);
42
__put_user(/* current->thread.error_code */ 0, &sc->error_code);
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
43
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
40
+ const BCM283XInfo *info = bc->info;
44
__get_user(env->regs[13], &sc->arm_sp);
41
Object *obj;
45
__get_user(env->regs[14], &sc->arm_lr);
42
Error *err = NULL;
46
__get_user(env->regs[15], &sc->arm_pc);
43
int n;
47
-#ifdef TARGET_CONFIG_CPU_32
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
48
__get_user(cpsr, &sc->arm_cpsr);
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
49
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
46
50
arm_rebuild_hflags(env);
47
for (n = 0; n < BCM283X_NCPUS; n++) {
51
-#endif
48
- /* Mirror bcm2836, which has clusterid set to 0xf
52
49
- * TODO: this should be converted to a property of ARM_CPU
53
err |= !valid_user_regs(env);
50
- */
54
51
- s->cpus[n].mp_affinity = 0xF00 | n;
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
55
--
58
2.16.2
56
2.20.1
59
57
60
58
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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