| 1 | Arm patch queue -- these are all bug fix patches but we might | 1 | Just a few minor bugfixes, but we might as well get them in |
|---|---|---|---|
| 2 | as well put them in to rc0... | 2 | for rc0 tomorrow. |
| 3 | 3 | ||
| 4 | thanks | ||
| 5 | -- PMM | 4 | -- PMM |
| 6 | 5 | ||
| 7 | The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be: | 6 | The following changes since commit 787f82407c5056a8b1097e39e53d01dd1abe406b: |
| 8 | 7 | ||
| 9 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000) | 8 | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200323' into staging (2020-03-23 15:38:30 +0000) |
| 10 | 9 | ||
| 11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 12 | 11 | ||
| 13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200323 |
| 14 | 13 | ||
| 15 | for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6: | 14 | for you to fetch changes up to 550a04893c2bd4442211b353680b9a6408d94dba: |
| 16 | 15 | ||
| 17 | hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000) | 16 | target/arm: Move computation of index in handle_simd_dupe (2020-03-23 17:22:30 +0000) |
| 18 | 17 | ||
| 19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 20 | target-arm queue: | 19 | target-arm queue: |
| 21 | * fsl-imx6: Fix incorrect Ethernet interrupt defines | 20 | * target/arm: avoid undefined behaviour shift in watchpoint code |
| 22 | * dump: Update correct kdump phys_base field for AArch64 | 21 | * target/arm: avoid undefined behaviour shift in handle_simd_dupe() |
| 23 | * char: i.MX: Add support for "TX complete" interrupt | 22 | * target/arm: add assert that immh != 0 in disas_simd_shift_imm() |
| 24 | * bcm2836/raspi: Fix various bugs resulting in panics trying | 23 | * aspeed/smc: Fix DMA support for AST2600 |
| 25 | to boot a Debian Linux kernel on raspi3 | 24 | * hw/arm/bcm283x: Correct the license text ('and' vs 'or') |
| 26 | 25 | ||
| 27 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 28 | Andrey Smirnov (2): | 27 | Cédric Le Goater (1): |
| 29 | char: i.MX: Simplify imx_update() | 28 | aspeed/smc: Fix DMA support for AST2600 |
| 30 | char: i.MX: Add support for "TX complete" interrupt | ||
| 31 | 29 | ||
| 32 | Guenter Roeck (1): | 30 | Philippe Mathieu-Daudé (1): |
| 33 | fsl-imx6: Swap Ethernet interrupt defines | 31 | hw/arm/bcm283x: Correct the license text |
| 34 | 32 | ||
| 35 | Peter Maydell (9): | 33 | Richard Henderson (3): |
| 36 | hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 | 34 | target/arm: Rearrange disabled check for watchpoints |
| 37 | hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 | 35 | target/arm: Assert immh != 0 in disas_simd_shift_imm |
| 38 | hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE | 36 | target/arm: Move computation of index in handle_simd_dupe |
| 39 | hw/arm/bcm2386: Fix parent type of bcm2386 | ||
| 40 | hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x | ||
| 41 | hw/arm/bcm2836: Create proper bcm2837 device | ||
| 42 | hw/arm/bcm2836: Use correct affinity values for BCM2837 | ||
| 43 | hw/arm/bcm2836: Hardcode correct CPU type | ||
| 44 | hw/arm/raspi: Provide spin-loop code for AArch64 CPUs | ||
| 45 | 37 | ||
| 46 | Wei Huang (1): | 38 | include/hw/arm/bcm2835_peripherals.h | 3 ++- |
| 47 | dump: Update correct kdump phys_base field for AArch64 | 39 | include/hw/arm/bcm2836.h | 3 ++- |
| 40 | include/hw/char/bcm2835_aux.h | 3 ++- | ||
| 41 | include/hw/display/bcm2835_fb.h | 3 ++- | ||
| 42 | include/hw/dma/bcm2835_dma.h | 4 +++- | ||
| 43 | include/hw/intc/bcm2835_ic.h | 4 +++- | ||
| 44 | include/hw/intc/bcm2836_control.h | 3 ++- | ||
| 45 | include/hw/misc/bcm2835_mbox.h | 4 +++- | ||
| 46 | include/hw/misc/bcm2835_mbox_defs.h | 4 +++- | ||
| 47 | include/hw/misc/bcm2835_property.h | 4 +++- | ||
| 48 | hw/arm/aspeed_ast2600.c | 6 ++++++ | ||
| 49 | hw/arm/bcm2835_peripherals.c | 3 ++- | ||
| 50 | hw/arm/bcm2836.c | 3 ++- | ||
| 51 | hw/arm/raspi.c | 3 ++- | ||
| 52 | hw/display/bcm2835_fb.c | 1 - | ||
| 53 | hw/dma/bcm2835_dma.c | 4 +++- | ||
| 54 | hw/intc/bcm2835_ic.c | 4 ++-- | ||
| 55 | hw/intc/bcm2836_control.c | 4 +++- | ||
| 56 | hw/misc/bcm2835_mbox.c | 4 +++- | ||
| 57 | hw/misc/bcm2835_property.c | 4 +++- | ||
| 58 | hw/ssi/aspeed_smc.c | 15 +++++++++++++-- | ||
| 59 | target/arm/helper.c | 11 ++++++----- | ||
| 60 | target/arm/translate-a64.c | 6 +++++- | ||
| 61 | hw/ssi/trace-events | 1 + | ||
| 62 | 24 files changed, 76 insertions(+), 28 deletions(-) | ||
| 48 | 63 | ||
| 49 | include/hw/arm/bcm2836.h | 31 +++++++++++++--- | ||
| 50 | include/hw/arm/fsl-imx6.h | 4 +- | ||
| 51 | include/hw/char/imx_serial.h | 3 ++ | ||
| 52 | dump.c | 14 +++++-- | ||
| 53 | hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++------------- | ||
| 54 | hw/arm/boot.c | 12 ++++++ | ||
| 55 | hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++-------- | ||
| 56 | hw/char/imx_serial.c | 44 ++++++++++++++++------ | ||
| 57 | hw/net/imx_fec.c | 28 +++++++++++++- | ||
| 58 | 9 files changed, 237 insertions(+), 63 deletions(-) | ||
| 59 | diff view generated by jsdifflib |
| 1 | Our BCM2836 type is really a generic one that can be any of | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
|---|---|---|---|
| 2 | the bcm283x family. Rename it accordingly. We change only | 2 | |
| 3 | the names which are visible via the header file to the | 3 | The license is the 'GNU General Public License v2.0 or later', |
| 4 | rest of the QEMU code, leaving private function names | 4 | not 'and': |
| 5 | in bcm2836.c as they are. | 5 | |
| 6 | 6 | This program is free software; you can redistribute it and/ori | |
| 7 | This is a preliminary to making bcm283x be an abstract | 7 | modify it under the terms of the GNU General Public License as |
| 8 | parent class to specific types for the bcm2836 and bcm2837. | 8 | published by the Free Software Foundation; either version 2 of |
| 9 | 9 | the License, or (at your option) any later version. | |
| 10 | |||
| 11 | Fix the license comment. | ||
| 12 | |||
| 13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 14 | Message-id: 20200312213455.15854-1-philmd@redhat.com | ||
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 13 | Message-id: 20180313153458.26822-6-peter.maydell@linaro.org | ||
| 14 | --- | 17 | --- |
| 15 | include/hw/arm/bcm2836.h | 12 ++++++------ | 18 | include/hw/arm/bcm2835_peripherals.h | 3 ++- |
| 16 | hw/arm/bcm2836.c | 17 +++++++++-------- | 19 | include/hw/arm/bcm2836.h | 3 ++- |
| 17 | hw/arm/raspi.c | 16 ++++++++-------- | 20 | include/hw/char/bcm2835_aux.h | 3 ++- |
| 18 | 3 files changed, 23 insertions(+), 22 deletions(-) | 21 | include/hw/display/bcm2835_fb.h | 3 ++- |
| 19 | 22 | include/hw/dma/bcm2835_dma.h | 4 +++- | |
| 23 | include/hw/intc/bcm2835_ic.h | 4 +++- | ||
| 24 | include/hw/intc/bcm2836_control.h | 3 ++- | ||
| 25 | include/hw/misc/bcm2835_mbox.h | 4 +++- | ||
| 26 | include/hw/misc/bcm2835_mbox_defs.h | 4 +++- | ||
| 27 | include/hw/misc/bcm2835_property.h | 4 +++- | ||
| 28 | hw/arm/bcm2835_peripherals.c | 3 ++- | ||
| 29 | hw/arm/bcm2836.c | 3 ++- | ||
| 30 | hw/arm/raspi.c | 3 ++- | ||
| 31 | hw/display/bcm2835_fb.c | 1 - | ||
| 32 | hw/dma/bcm2835_dma.c | 4 +++- | ||
| 33 | hw/intc/bcm2835_ic.c | 4 ++-- | ||
| 34 | hw/intc/bcm2836_control.c | 4 +++- | ||
| 35 | hw/misc/bcm2835_mbox.c | 4 +++- | ||
| 36 | hw/misc/bcm2835_property.c | 4 +++- | ||
| 37 | 19 files changed, 45 insertions(+), 20 deletions(-) | ||
| 38 | |||
| 39 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/include/hw/arm/bcm2835_peripherals.h | ||
| 42 | +++ b/include/hw/arm/bcm2835_peripherals.h | ||
| 43 | @@ -XXX,XX +XXX,XX @@ | ||
| 44 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | ||
| 45 | * Written by Andrew Baumann | ||
| 46 | * | ||
| 47 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 48 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 49 | + * See the COPYING file in the top-level directory. | ||
| 50 | */ | ||
| 51 | |||
| 52 | #ifndef BCM2835_PERIPHERALS_H | ||
| 20 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | 53 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h |
| 21 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/include/hw/arm/bcm2836.h | 55 | --- a/include/hw/arm/bcm2836.h |
| 23 | +++ b/include/hw/arm/bcm2836.h | 56 | +++ b/include/hw/arm/bcm2836.h |
| 24 | @@ -XXX,XX +XXX,XX @@ | 57 | @@ -XXX,XX +XXX,XX @@ |
| 25 | #include "hw/arm/bcm2835_peripherals.h" | 58 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft |
| 26 | #include "hw/intc/bcm2836_control.h" | 59 | * Written by Andrew Baumann |
| 27 | 60 | * | |
| 28 | -#define TYPE_BCM2836 "bcm2836" | 61 | - * This code is licensed under the GNU GPLv2 and later. |
| 29 | -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) | 62 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 30 | +#define TYPE_BCM283X "bcm283x" | 63 | + * See the COPYING file in the top-level directory. |
| 31 | +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) | 64 | */ |
| 32 | 65 | ||
| 33 | -#define BCM2836_NCPUS 4 | 66 | #ifndef BCM2836_H |
| 34 | +#define BCM283X_NCPUS 4 | 67 | diff --git a/include/hw/char/bcm2835_aux.h b/include/hw/char/bcm2835_aux.h |
| 35 | 68 | index XXXXXXX..XXXXXXX 100644 | |
| 36 | -typedef struct BCM2836State { | 69 | --- a/include/hw/char/bcm2835_aux.h |
| 37 | +typedef struct BCM283XState { | 70 | +++ b/include/hw/char/bcm2835_aux.h |
| 38 | /*< private >*/ | 71 | @@ -XXX,XX +XXX,XX @@ |
| 39 | DeviceState parent_obj; | 72 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft |
| 40 | /*< public >*/ | 73 | * Written by Andrew Baumann |
| 41 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State { | 74 | * |
| 42 | char *cpu_type; | 75 | - * This code is licensed under the GNU GPLv2 and later. |
| 43 | uint32_t enabled_cpus; | 76 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 44 | 77 | + * See the COPYING file in the top-level directory. | |
| 45 | - ARMCPU cpus[BCM2836_NCPUS]; | 78 | */ |
| 46 | + ARMCPU cpus[BCM283X_NCPUS]; | 79 | |
| 47 | BCM2836ControlState control; | 80 | #ifndef BCM2835_AUX_H |
| 48 | BCM2835PeripheralState peripherals; | 81 | diff --git a/include/hw/display/bcm2835_fb.h b/include/hw/display/bcm2835_fb.h |
| 49 | -} BCM2836State; | 82 | index XXXXXXX..XXXXXXX 100644 |
| 50 | +} BCM283XState; | 83 | --- a/include/hw/display/bcm2835_fb.h |
| 51 | 84 | +++ b/include/hw/display/bcm2835_fb.h | |
| 52 | #endif /* BCM2836_H */ | 85 | @@ -XXX,XX +XXX,XX @@ |
| 86 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | ||
| 87 | * Written by Andrew Baumann | ||
| 88 | * | ||
| 89 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 90 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 91 | + * See the COPYING file in the top-level directory. | ||
| 92 | */ | ||
| 93 | |||
| 94 | #ifndef BCM2835_FB_H | ||
| 95 | diff --git a/include/hw/dma/bcm2835_dma.h b/include/hw/dma/bcm2835_dma.h | ||
| 96 | index XXXXXXX..XXXXXXX 100644 | ||
| 97 | --- a/include/hw/dma/bcm2835_dma.h | ||
| 98 | +++ b/include/hw/dma/bcm2835_dma.h | ||
| 99 | @@ -XXX,XX +XXX,XX @@ | ||
| 100 | /* | ||
| 101 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 102 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 103 | + * | ||
| 104 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 105 | + * See the COPYING file in the top-level directory. | ||
| 106 | */ | ||
| 107 | |||
| 108 | #ifndef BCM2835_DMA_H | ||
| 109 | diff --git a/include/hw/intc/bcm2835_ic.h b/include/hw/intc/bcm2835_ic.h | ||
| 110 | index XXXXXXX..XXXXXXX 100644 | ||
| 111 | --- a/include/hw/intc/bcm2835_ic.h | ||
| 112 | +++ b/include/hw/intc/bcm2835_ic.h | ||
| 113 | @@ -XXX,XX +XXX,XX @@ | ||
| 114 | /* | ||
| 115 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 116 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 117 | + * | ||
| 118 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 119 | + * See the COPYING file in the top-level directory. | ||
| 120 | */ | ||
| 121 | |||
| 122 | #ifndef BCM2835_IC_H | ||
| 123 | diff --git a/include/hw/intc/bcm2836_control.h b/include/hw/intc/bcm2836_control.h | ||
| 124 | index XXXXXXX..XXXXXXX 100644 | ||
| 125 | --- a/include/hw/intc/bcm2836_control.h | ||
| 126 | +++ b/include/hw/intc/bcm2836_control.h | ||
| 127 | @@ -XXX,XX +XXX,XX @@ | ||
| 128 | * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti | ||
| 129 | * Added basic IRQ_TIMER interrupt support | ||
| 130 | * | ||
| 131 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 132 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 133 | + * See the COPYING file in the top-level directory. | ||
| 134 | */ | ||
| 135 | |||
| 136 | #ifndef BCM2836_CONTROL_H | ||
| 137 | diff --git a/include/hw/misc/bcm2835_mbox.h b/include/hw/misc/bcm2835_mbox.h | ||
| 138 | index XXXXXXX..XXXXXXX 100644 | ||
| 139 | --- a/include/hw/misc/bcm2835_mbox.h | ||
| 140 | +++ b/include/hw/misc/bcm2835_mbox.h | ||
| 141 | @@ -XXX,XX +XXX,XX @@ | ||
| 142 | /* | ||
| 143 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 144 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 145 | + * | ||
| 146 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 147 | + * See the COPYING file in the top-level directory. | ||
| 148 | */ | ||
| 149 | |||
| 150 | #ifndef BCM2835_MBOX_H | ||
| 151 | diff --git a/include/hw/misc/bcm2835_mbox_defs.h b/include/hw/misc/bcm2835_mbox_defs.h | ||
| 152 | index XXXXXXX..XXXXXXX 100644 | ||
| 153 | --- a/include/hw/misc/bcm2835_mbox_defs.h | ||
| 154 | +++ b/include/hw/misc/bcm2835_mbox_defs.h | ||
| 155 | @@ -XXX,XX +XXX,XX @@ | ||
| 156 | /* | ||
| 157 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 158 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 159 | + * | ||
| 160 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 161 | + * See the COPYING file in the top-level directory. | ||
| 162 | */ | ||
| 163 | |||
| 164 | #ifndef BCM2835_MBOX_DEFS_H | ||
| 165 | diff --git a/include/hw/misc/bcm2835_property.h b/include/hw/misc/bcm2835_property.h | ||
| 166 | index XXXXXXX..XXXXXXX 100644 | ||
| 167 | --- a/include/hw/misc/bcm2835_property.h | ||
| 168 | +++ b/include/hw/misc/bcm2835_property.h | ||
| 169 | @@ -XXX,XX +XXX,XX @@ | ||
| 170 | /* | ||
| 171 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 172 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 173 | + * | ||
| 174 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 175 | + * See the COPYING file in the top-level directory. | ||
| 176 | */ | ||
| 177 | |||
| 178 | #ifndef BCM2835_PROPERTY_H | ||
| 179 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
| 180 | index XXXXXXX..XXXXXXX 100644 | ||
| 181 | --- a/hw/arm/bcm2835_peripherals.c | ||
| 182 | +++ b/hw/arm/bcm2835_peripherals.c | ||
| 183 | @@ -XXX,XX +XXX,XX @@ | ||
| 184 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | ||
| 185 | * Written by Andrew Baumann | ||
| 186 | * | ||
| 187 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 188 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 189 | + * See the COPYING file in the top-level directory. | ||
| 190 | */ | ||
| 191 | |||
| 192 | #include "qemu/osdep.h" | ||
| 53 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 193 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c |
| 54 | index XXXXXXX..XXXXXXX 100644 | 194 | index XXXXXXX..XXXXXXX 100644 |
| 55 | --- a/hw/arm/bcm2836.c | 195 | --- a/hw/arm/bcm2836.c |
| 56 | +++ b/hw/arm/bcm2836.c | 196 | +++ b/hw/arm/bcm2836.c |
| 57 | @@ -XXX,XX +XXX,XX @@ | 197 | @@ -XXX,XX +XXX,XX @@ |
| 58 | 198 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | |
| 59 | static void bcm2836_init(Object *obj) | 199 | * Written by Andrew Baumann |
| 60 | { | 200 | * |
| 61 | - BCM2836State *s = BCM2836(obj); | 201 | - * This code is licensed under the GNU GPLv2 and later. |
| 62 | + BCM283XState *s = BCM283X(obj); | 202 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 63 | 203 | + * See the COPYING file in the top-level directory. | |
| 64 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | 204 | */ |
| 65 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | 205 | |
| 66 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) | 206 | #include "qemu/osdep.h" |
| 67 | |||
| 68 | static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 69 | { | ||
| 70 | - BCM2836State *s = BCM2836(dev); | ||
| 71 | + BCM283XState *s = BCM283X(dev); | ||
| 72 | Object *obj; | ||
| 73 | Error *err = NULL; | ||
| 74 | int n; | ||
| 75 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 76 | /* common peripherals from bcm2835 */ | ||
| 77 | |||
| 78 | obj = OBJECT(dev); | ||
| 79 | - for (n = 0; n < BCM2836_NCPUS; n++) { | ||
| 80 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 81 | object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
| 82 | s->cpu_type); | ||
| 83 | object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
| 84 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 85 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | ||
| 86 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | ||
| 87 | |||
| 88 | - for (n = 0; n < BCM2836_NCPUS; n++) { | ||
| 89 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 90 | /* Mirror bcm2836, which has clusterid set to 0xf | ||
| 91 | * TODO: this should be converted to a property of ARM_CPU | ||
| 92 | */ | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 94 | } | ||
| 95 | |||
| 96 | static Property bcm2836_props[] = { | ||
| 97 | - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), | ||
| 98 | - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), | ||
| 99 | + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), | ||
| 100 | + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, | ||
| 101 | + BCM283X_NCPUS), | ||
| 102 | DEFINE_PROP_END_OF_LIST() | ||
| 103 | }; | ||
| 104 | |||
| 105 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
| 106 | } | ||
| 107 | |||
| 108 | static const TypeInfo bcm2836_type_info = { | ||
| 109 | - .name = TYPE_BCM2836, | ||
| 110 | + .name = TYPE_BCM283X, | ||
| 111 | .parent = TYPE_DEVICE, | ||
| 112 | - .instance_size = sizeof(BCM2836State), | ||
| 113 | + .instance_size = sizeof(BCM283XState), | ||
| 114 | .instance_init = bcm2836_init, | ||
| 115 | .class_init = bcm2836_class_init, | ||
| 116 | }; | ||
| 117 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 207 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c |
| 118 | index XXXXXXX..XXXXXXX 100644 | 208 | index XXXXXXX..XXXXXXX 100644 |
| 119 | --- a/hw/arm/raspi.c | 209 | --- a/hw/arm/raspi.c |
| 120 | +++ b/hw/arm/raspi.c | 210 | +++ b/hw/arm/raspi.c |
| 121 | @@ -XXX,XX +XXX,XX @@ | 211 | @@ -XXX,XX +XXX,XX @@ |
| 122 | static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | 212 | * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti |
| 123 | 213 | * Upstream code cleanup (c) 2018 Pekka Enberg | |
| 124 | typedef struct RasPiState { | 214 | * |
| 125 | - BCM2836State soc; | 215 | - * This code is licensed under the GNU GPLv2 and later. |
| 126 | + BCM283XState soc; | 216 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 127 | MemoryRegion ram; | 217 | + * See the COPYING file in the top-level directory. |
| 128 | } RasPiState; | 218 | */ |
| 129 | 219 | ||
| 130 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | 220 | #include "qemu/osdep.h" |
| 131 | BusState *bus; | 221 | diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c |
| 132 | DeviceState *carddev; | 222 | index XXXXXXX..XXXXXXX 100644 |
| 133 | 223 | --- a/hw/display/bcm2835_fb.c | |
| 134 | - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); | 224 | +++ b/hw/display/bcm2835_fb.c |
| 135 | + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); | 225 | @@ -XXX,XX +XXX,XX @@ |
| 136 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), | 226 | /* |
| 137 | &error_abort); | 227 | * Raspberry Pi emulation (c) 2012 Gregory Estrade |
| 138 | 228 | * Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann. | |
| 139 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | 229 | - * This code is licensed under the GNU GPLv2 and later. |
| 140 | mc->no_floppy = 1; | 230 | * |
| 141 | mc->no_cdrom = 1; | 231 | * Heavily based on milkymist-vgafb.c, copyright terms below: |
| 142 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | 232 | * QEMU model of the Milkymist VGA framebuffer. |
| 143 | - mc->max_cpus = BCM2836_NCPUS; | 233 | diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c |
| 144 | - mc->min_cpus = BCM2836_NCPUS; | 234 | index XXXXXXX..XXXXXXX 100644 |
| 145 | - mc->default_cpus = BCM2836_NCPUS; | 235 | --- a/hw/dma/bcm2835_dma.c |
| 146 | + mc->max_cpus = BCM283X_NCPUS; | 236 | +++ b/hw/dma/bcm2835_dma.c |
| 147 | + mc->min_cpus = BCM283X_NCPUS; | 237 | @@ -XXX,XX +XXX,XX @@ |
| 148 | + mc->default_cpus = BCM283X_NCPUS; | 238 | /* |
| 149 | mc->default_ram_size = 1024 * 1024 * 1024; | 239 | * Raspberry Pi emulation (c) 2012 Gregory Estrade |
| 150 | mc->ignore_memory_transaction_failures = true; | 240 | - * This code is licensed under the GNU GPLv2 and later. |
| 151 | }; | 241 | + * |
| 152 | @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) | 242 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 153 | mc->no_floppy = 1; | 243 | + * See the COPYING file in the top-level directory. |
| 154 | mc->no_cdrom = 1; | 244 | */ |
| 155 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); | 245 | |
| 156 | - mc->max_cpus = BCM2836_NCPUS; | 246 | #include "qemu/osdep.h" |
| 157 | - mc->min_cpus = BCM2836_NCPUS; | 247 | diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c |
| 158 | - mc->default_cpus = BCM2836_NCPUS; | 248 | index XXXXXXX..XXXXXXX 100644 |
| 159 | + mc->max_cpus = BCM283X_NCPUS; | 249 | --- a/hw/intc/bcm2835_ic.c |
| 160 | + mc->min_cpus = BCM283X_NCPUS; | 250 | +++ b/hw/intc/bcm2835_ic.c |
| 161 | + mc->default_cpus = BCM283X_NCPUS; | 251 | @@ -XXX,XX +XXX,XX @@ |
| 162 | mc->default_ram_size = 1024 * 1024 * 1024; | 252 | /* |
| 163 | } | 253 | * Raspberry Pi emulation (c) 2012 Gregory Estrade |
| 164 | DEFINE_MACHINE("raspi3", raspi3_machine_init) | 254 | * Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann. |
| 255 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 256 | * Heavily based on pl190.c, copyright terms below: | ||
| 257 | * | ||
| 258 | * Arm PrimeCell PL190 Vector Interrupt Controller | ||
| 259 | @@ -XXX,XX +XXX,XX @@ | ||
| 260 | * Copyright (c) 2006 CodeSourcery. | ||
| 261 | * Written by Paul Brook | ||
| 262 | * | ||
| 263 | - * This code is licensed under the GPL. | ||
| 264 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 265 | + * See the COPYING file in the top-level directory. | ||
| 266 | */ | ||
| 267 | |||
| 268 | #include "qemu/osdep.h" | ||
| 269 | diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c | ||
| 270 | index XXXXXXX..XXXXXXX 100644 | ||
| 271 | --- a/hw/intc/bcm2836_control.c | ||
| 272 | +++ b/hw/intc/bcm2836_control.c | ||
| 273 | @@ -XXX,XX +XXX,XX @@ | ||
| 274 | * Written by Andrew Baumann | ||
| 275 | * | ||
| 276 | * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade | ||
| 277 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 278 | * | ||
| 279 | * At present, only implements interrupt routing, and mailboxes (i.e., | ||
| 280 | * not PMU interrupt, or AXI counters). | ||
| 281 | @@ -XXX,XX +XXX,XX @@ | ||
| 282 | * | ||
| 283 | * Ref: | ||
| 284 | * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf | ||
| 285 | + * | ||
| 286 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 287 | + * See the COPYING file in the top-level directory. | ||
| 288 | */ | ||
| 289 | |||
| 290 | #include "qemu/osdep.h" | ||
| 291 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | ||
| 292 | index XXXXXXX..XXXXXXX 100644 | ||
| 293 | --- a/hw/misc/bcm2835_mbox.c | ||
| 294 | +++ b/hw/misc/bcm2835_mbox.c | ||
| 295 | @@ -XXX,XX +XXX,XX @@ | ||
| 296 | /* | ||
| 297 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 298 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 299 | * | ||
| 300 | * This file models the system mailboxes, which are used for | ||
| 301 | * communication with low-bandwidth GPU peripherals. Refs: | ||
| 302 | * https://github.com/raspberrypi/firmware/wiki/Mailboxes | ||
| 303 | * https://github.com/raspberrypi/firmware/wiki/Accessing-mailboxes | ||
| 304 | + * | ||
| 305 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 306 | + * See the COPYING file in the top-level directory. | ||
| 307 | */ | ||
| 308 | |||
| 309 | #include "qemu/osdep.h" | ||
| 310 | diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c | ||
| 311 | index XXXXXXX..XXXXXXX 100644 | ||
| 312 | --- a/hw/misc/bcm2835_property.c | ||
| 313 | +++ b/hw/misc/bcm2835_property.c | ||
| 314 | @@ -XXX,XX +XXX,XX @@ | ||
| 315 | /* | ||
| 316 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | ||
| 317 | - * This code is licensed under the GNU GPLv2 and later. | ||
| 318 | + * | ||
| 319 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 320 | + * See the COPYING file in the top-level directory. | ||
| 321 | */ | ||
| 322 | |||
| 323 | #include "qemu/osdep.h" | ||
| 165 | -- | 324 | -- |
| 166 | 2.16.2 | 325 | 2.20.1 |
| 167 | 326 | ||
| 168 | 327 | diff view generated by jsdifflib |
| 1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | 1 | From: Cédric Le Goater <clg@kaod.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for "TX complete"/TXDC interrupt generate by real HW since | 3 | Recent firmwares uses SPI DMA transfers in U-Boot to load the |
| 4 | it is needed to support guests other than Linux. | 4 | different images (kernel, initrd, dtb) in the SoC DRAM. The AST2600 |
| 5 | FMC model is missing the masks to be applied on the DMA registers | ||
| 6 | which resulted in incorrect values. Fix that and wire the SPI | ||
| 7 | controllers which have DMA support on the AST2600. | ||
| 5 | 8 | ||
| 6 | Based on the patch by Bill Paul as found here: | 9 | Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support") |
| 7 | https://bugs.launchpad.net/qemu/+bug/1753314 | 10 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
| 8 | 11 | Reviewed-by: Joel Stanley <joel@jms.id.au> | |
| 9 | Cc: qemu-devel@nongnu.org | 12 | Message-id: 20200320053923.20565-1-clg@kaod.org |
| 10 | Cc: qemu-arm@nongnu.org | ||
| 11 | Cc: Bill Paul <wpaul@windriver.com> | ||
| 12 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Signed-off-by: Bill Paul <wpaul@windriver.com> | ||
| 14 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 15 | Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com | ||
| 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | --- | 14 | --- |
| 19 | include/hw/char/imx_serial.h | 3 +++ | 15 | hw/arm/aspeed_ast2600.c | 6 ++++++ |
| 20 | hw/char/imx_serial.c | 20 +++++++++++++++++--- | 16 | hw/ssi/aspeed_smc.c | 15 +++++++++++++-- |
| 21 | 2 files changed, 20 insertions(+), 3 deletions(-) | 17 | hw/ssi/trace-events | 1 + |
| 18 | 3 files changed, 20 insertions(+), 2 deletions(-) | ||
| 22 | 19 | ||
| 23 | diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h | 20 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c |
| 24 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/include/hw/char/imx_serial.h | 22 | --- a/hw/arm/aspeed_ast2600.c |
| 26 | +++ b/include/hw/char/imx_serial.h | 23 | +++ b/hw/arm/aspeed_ast2600.c |
| 27 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) |
| 28 | #define UCR2_RXEN (1<<1) /* Receiver enable */ | 25 | |
| 29 | #define UCR2_SRST (1<<0) /* Reset complete */ | 26 | /* SPI */ |
| 30 | 27 | for (i = 0; i < sc->spis_num; i++) { | |
| 31 | +#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ | 28 | + object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), |
| 32 | + | 29 | + "dram", &err); |
| 33 | #define UTS1_TXEMPTY (1<<6) | 30 | + if (err) { |
| 34 | #define UTS1_RXEMPTY (1<<5) | 31 | + error_propagate(errp, err); |
| 35 | #define UTS1_TXFULL (1<<4) | 32 | + return; |
| 36 | @@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState { | 33 | + } |
| 37 | uint32_t ubmr; | 34 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); |
| 38 | uint32_t ubrc; | 35 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", |
| 39 | uint32_t ucr3; | 36 | &local_err); |
| 40 | + uint32_t ucr4; | 37 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c |
| 41 | |||
| 42 | qemu_irq irq; | ||
| 43 | CharBackend chr; | ||
| 44 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | ||
| 45 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
| 46 | --- a/hw/char/imx_serial.c | 39 | --- a/hw/ssi/aspeed_smc.c |
| 47 | +++ b/hw/char/imx_serial.c | 40 | +++ b/hw/ssi/aspeed_smc.c |
| 48 | @@ -XXX,XX +XXX,XX @@ | 41 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { |
| 49 | 42 | .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE, | |
| 50 | static const VMStateDescription vmstate_imx_serial = { | 43 | .flash_window_size = 0x10000000, |
| 51 | .name = TYPE_IMX_SERIAL, | 44 | .has_dma = true, |
| 52 | - .version_id = 1, | 45 | + .dma_flash_mask = 0x0FFFFFFC, |
| 53 | - .minimum_version_id = 1, | 46 | + .dma_dram_mask = 0x3FFFFFFC, |
| 54 | + .version_id = 2, | 47 | .nregs = ASPEED_SMC_R_MAX, |
| 55 | + .minimum_version_id = 2, | 48 | .segment_to_reg = aspeed_2600_smc_segment_to_reg, |
| 56 | .fields = (VMStateField[]) { | 49 | .reg_to_segment = aspeed_2600_smc_reg_to_segment, |
| 57 | VMSTATE_INT32(readbuff, IMXSerialState), | 50 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { |
| 58 | VMSTATE_UINT32(usr1, IMXSerialState), | 51 | .segments = aspeed_segments_ast2600_spi1, |
| 59 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { | 52 | .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE, |
| 60 | VMSTATE_UINT32(ubmr, IMXSerialState), | 53 | .flash_window_size = 0x10000000, |
| 61 | VMSTATE_UINT32(ubrc, IMXSerialState), | 54 | - .has_dma = false, |
| 62 | VMSTATE_UINT32(ucr3, IMXSerialState), | 55 | + .has_dma = true, |
| 63 | + VMSTATE_UINT32(ucr4, IMXSerialState), | 56 | + .dma_flash_mask = 0x0FFFFFFC, |
| 64 | VMSTATE_END_OF_LIST() | 57 | + .dma_dram_mask = 0x3FFFFFFC, |
| 65 | }, | 58 | .nregs = ASPEED_SMC_R_MAX, |
| 66 | }; | 59 | .segment_to_reg = aspeed_2600_smc_segment_to_reg, |
| 67 | @@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s) | 60 | .reg_to_segment = aspeed_2600_smc_reg_to_segment, |
| 68 | * unfortunately. | 61 | @@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = { |
| 69 | */ | 62 | .segments = aspeed_segments_ast2600_spi2, |
| 70 | mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | 63 | .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE, |
| 71 | + /* | 64 | .flash_window_size = 0x10000000, |
| 72 | + * TCEN and TXDC are both bit 3 | 65 | - .has_dma = false, |
| 73 | + */ | 66 | + .has_dma = true, |
| 74 | + mask |= s->ucr4 & UCR4_TCEN; | 67 | + .dma_flash_mask = 0x0FFFFFFC, |
| 75 | + | 68 | + .dma_dram_mask = 0x3FFFFFFC, |
| 76 | usr2 = s->usr2 & mask; | 69 | .nregs = ASPEED_SMC_R_MAX, |
| 77 | 70 | .segment_to_reg = aspeed_2600_smc_segment_to_reg, | |
| 78 | qemu_set_irq(s->irq, usr1 || usr2); | 71 | .reg_to_segment = aspeed_2600_smc_reg_to_segment, |
| 79 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, | 72 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_rw(AspeedSMCState *s) |
| 80 | return s->ucr3; | 73 | MemTxResult result; |
| 81 | 74 | uint32_t data; | |
| 82 | case 0x23: /* UCR4 */ | 75 | |
| 83 | + return s->ucr4; | 76 | + trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? |
| 84 | + | 77 | + "write" : "read", |
| 85 | case 0x29: /* BRM Incremental */ | 78 | + s->regs[R_DMA_FLASH_ADDR], |
| 86 | return 0x0; /* TODO */ | 79 | + s->regs[R_DMA_DRAM_ADDR], |
| 87 | 80 | + s->regs[R_DMA_LEN]); | |
| 88 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, | 81 | while (s->regs[R_DMA_LEN]) { |
| 89 | * qemu_chr_fe_write and background I/O callbacks */ | 82 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { |
| 90 | qemu_chr_fe_write_all(&s->chr, &ch, 1); | 83 | data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], |
| 91 | s->usr1 &= ~USR1_TRDY; | 84 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events |
| 92 | + s->usr2 &= ~USR2_TXDC; | 85 | index XXXXXXX..XXXXXXX 100644 |
| 93 | imx_update(s); | 86 | --- a/hw/ssi/trace-events |
| 94 | s->usr1 |= USR1_TRDY; | 87 | +++ b/hw/ssi/trace-events |
| 95 | + s->usr2 |= USR2_TXDC; | 88 | @@ -XXX,XX +XXX,XX @@ aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x d |
| 96 | imx_update(s); | 89 | aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d" |
| 97 | } | 90 | aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 |
| 98 | break; | 91 | aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" |
| 99 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, | 92 | +aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x" |
| 100 | s->ucr3 = value & 0xffff; | 93 | aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 |
| 101 | break; | 94 | aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" |
| 102 | |||
| 103 | - case 0x2d: /* UTS1 */ | ||
| 104 | case 0x23: /* UCR4 */ | ||
| 105 | + s->ucr4 = value & 0xffff; | ||
| 106 | + imx_update(s); | ||
| 107 | + break; | ||
| 108 | + | ||
| 109 | + case 0x2d: /* UTS1 */ | ||
| 110 | qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" | ||
| 111 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); | ||
| 112 | /* TODO */ | ||
| 113 | -- | 95 | -- |
| 114 | 2.16.2 | 96 | 2.20.1 |
| 115 | 97 | ||
| 116 | 98 | diff view generated by jsdifflib |
| 1 | From: Wei Huang <wei@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | For guest kernel that supports KASLR, the load address can change every | 3 | Coverity rightly notes that ctz32(bas) on 0 will return 32, |
| 4 | time when guest VM runs. To find the physical base address correctly, | 4 | which makes the len calculation a BAD_SHIFT. |
| 5 | current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=". | ||
| 6 | However this string pattern is only available on x86_64. AArch64 uses a | ||
| 7 | different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure | ||
| 8 | QEMU dump uses the correct string on AArch64. | ||
| 9 | 5 | ||
| 10 | Signed-off-by: Wei Huang <wei@redhat.com> | 6 | A value of 0 in DBGWCR<n>_EL1.BAS is reserved. Simply move |
| 11 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> | 7 | the existing check we have for this case. |
| 12 | Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com | 8 | |
| 9 | Reported-by: Coverity (CID 1421964) | ||
| 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 12 | Message-id: 20200320160622.8040-2-richard.henderson@linaro.org | ||
| 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | --- | 15 | --- |
| 15 | dump.c | 14 +++++++++++--- | 16 | target/arm/helper.c | 11 ++++++----- |
| 16 | 1 file changed, 11 insertions(+), 3 deletions(-) | 17 | 1 file changed, 6 insertions(+), 5 deletions(-) |
| 17 | 18 | ||
| 18 | diff --git a/dump.c b/dump.c | 19 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/dump.c | 21 | --- a/target/arm/helper.c |
| 21 | +++ b/dump.c | 22 | +++ b/target/arm/helper.c |
| 22 | @@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s) | 23 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) |
| 23 | 24 | int bas = extract64(wcr, 5, 8); | |
| 24 | lines = g_strsplit((char *)vmci, "\n", -1); | 25 | int basstart; |
| 25 | for (i = 0; lines[i]; i++) { | 26 | |
| 26 | - if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) { | 27 | - if (bas == 0) { |
| 27 | - if (qemu_strtou64(lines[i] + 18, NULL, 16, | 28 | - /* This must act as if the watchpoint is disabled */ |
| 28 | + const char *prefix = NULL; | 29 | - return; |
| 30 | - } | ||
| 31 | - | ||
| 32 | if (extract64(wvr, 2, 1)) { | ||
| 33 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 34 | * ignored, and BAS[3:0] define which bytes to watch. | ||
| 35 | */ | ||
| 36 | bas &= 0xf; | ||
| 37 | } | ||
| 29 | + | 38 | + |
| 30 | + if (s->dump_info.d_machine == EM_X86_64) { | 39 | + if (bas == 0) { |
| 31 | + prefix = "NUMBER(phys_base)="; | 40 | + /* This must act as if the watchpoint is disabled */ |
| 32 | + } else if (s->dump_info.d_machine == EM_AARCH64) { | 41 | + return; |
| 33 | + prefix = "NUMBER(PHYS_OFFSET)="; | ||
| 34 | + } | 42 | + } |
| 35 | + | 43 | + |
| 36 | + if (prefix && g_str_has_prefix(lines[i], prefix)) { | 44 | /* The BAS bits are supposed to be programmed to indicate a contiguous |
| 37 | + if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16, | 45 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether |
| 38 | &phys_base) < 0) { | 46 | * we fire for each byte in the word/doubleword addressed by the WVR. |
| 39 | - warn_report("Failed to read NUMBER(phys_base)="); | ||
| 40 | + warn_report("Failed to read %s", prefix); | ||
| 41 | } else { | ||
| 42 | s->dump_info.phys_base = phys_base; | ||
| 43 | } | ||
| 44 | -- | 47 | -- |
| 45 | 2.16.2 | 48 | 2.20.1 |
| 46 | 49 | ||
| 47 | 50 | diff view generated by jsdifflib |
| 1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Code of imx_update() is slightly confusing since the "flags" variable | 3 | Coverity raised a shed-load of errors cascading from inferring |
| 4 | doesn't really corespond to anything in real hardware and server as a | 4 | that clz32(immh) might yield 32, from immh might be 0. |
| 5 | kitchensink accumulating events normally reported via USR1 and USR2 | ||
| 6 | registers. | ||
| 7 | 5 | ||
| 8 | Change the code to explicitly evaluate state of interrupts reported | 6 | While immh cannot be 0 from encoding, it is not obvious even to |
| 9 | via USR1 and USR2 against corresponding masking bits and use the to | 7 | a human how we've checked that: via the filtering provided by |
| 10 | detemine if IRQ line should be asserted or not. | 8 | data_proc_simd[]. |
| 11 | 9 | ||
| 12 | NOTE: Check for UTS1_TXEMPTY being set has been dropped for two | 10 | Reported-by: Coverity (CID 1421923, and more) |
| 13 | reasons: | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 14 | 12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | |
| 15 | 1. Emulation code implements a single character FIFO, so this flag | 13 | Message-id: 20200320160622.8040-3-richard.henderson@linaro.org |
| 16 | will always be set since characters are trasmitted as a part of | ||
| 17 | the code emulating "push" into the FIFO | ||
| 18 | |||
| 19 | 2. imx_update() is really just a function doing ORing and maksing | ||
| 20 | of reported events, so checking for UTS1_TXEMPTY should happen, | ||
| 21 | if it's ever really needed should probably happen outside of | ||
| 22 | it. | ||
| 23 | |||
| 24 | Cc: qemu-devel@nongnu.org | ||
| 25 | Cc: qemu-arm@nongnu.org | ||
| 26 | Cc: Bill Paul <wpaul@windriver.com> | ||
| 27 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 28 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 29 | Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com | ||
| 30 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 32 | --- | 16 | --- |
| 33 | hw/char/imx_serial.c | 24 ++++++++++++++++-------- | 17 | target/arm/translate-a64.c | 3 +++ |
| 34 | 1 file changed, 16 insertions(+), 8 deletions(-) | 18 | 1 file changed, 3 insertions(+) |
| 35 | 19 | ||
| 36 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | 20 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
| 37 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 38 | --- a/hw/char/imx_serial.c | 22 | --- a/target/arm/translate-a64.c |
| 39 | +++ b/hw/char/imx_serial.c | 23 | +++ b/target/arm/translate-a64.c |
| 40 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { | 24 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) |
| 41 | 25 | bool is_u = extract32(insn, 29, 1); | |
| 42 | static void imx_update(IMXSerialState *s) | 26 | bool is_q = extract32(insn, 30, 1); |
| 43 | { | 27 | |
| 44 | - uint32_t flags; | 28 | + /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */ |
| 45 | + uint32_t usr1; | 29 | + assert(immh != 0); |
| 46 | + uint32_t usr2; | 30 | + |
| 47 | + uint32_t mask; | 31 | switch (opcode) { |
| 48 | 32 | case 0x08: /* SRI */ | |
| 49 | - flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); | 33 | if (!is_u) { |
| 50 | - if (s->ucr1 & UCR1_TXMPTYEN) { | ||
| 51 | - flags |= (s->uts1 & UTS1_TXEMPTY); | ||
| 52 | - } else { | ||
| 53 | - flags &= ~USR1_TRDY; | ||
| 54 | - } | ||
| 55 | + /* | ||
| 56 | + * Lucky for us TRDY and RRDY has the same offset in both USR1 and | ||
| 57 | + * UCR1, so we can get away with something as simple as the | ||
| 58 | + * following: | ||
| 59 | + */ | ||
| 60 | + usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); | ||
| 61 | + /* | ||
| 62 | + * Bits that we want in USR2 are not as conveniently laid out, | ||
| 63 | + * unfortunately. | ||
| 64 | + */ | ||
| 65 | + mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | ||
| 66 | + usr2 = s->usr2 & mask; | ||
| 67 | |||
| 68 | - qemu_set_irq(s->irq, !!flags); | ||
| 69 | + qemu_set_irq(s->irq, usr1 || usr2); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void imx_serial_reset(IMXSerialState *s) | ||
| 73 | -- | 34 | -- |
| 74 | 2.16.2 | 35 | 2.20.1 |
| 75 | 36 | ||
| 76 | 37 | diff view generated by jsdifflib |
| 1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The sabrelite machine model used by qemu-system-arm is based on the | 3 | Coverity reports a BAD_SHIFT with ctz32(imm5), with imm5 == 0. |
| 4 | Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet | 4 | This is an invalid encoding, but we diagnose that just below |
| 5 | controller which is supported in QEMU using the imx_fec.c module | 5 | by rejecting size > 3. Avoid the warning by sinking the |
| 6 | (actually called imx.enet for this model.) | 6 | computation of index below the check. |
| 7 | 7 | ||
| 8 | The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the | 8 | Reported-by: Coverity (CID 1421965) |
| 9 | imx.enet device like this: | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | |
| 11 | #define FSL_IMX6_ENET_MAC_1588_IRQ 118 | 11 | Message-id: 20200320160622.8040-4-richard.henderson@linaro.org |
| 12 | #define FSL_IMX6_ENET_MAC_IRQ 119 | ||
| 13 | |||
| 14 | According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf, | ||
| 15 | page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary, | ||
| 16 | interrupts are as follows. | ||
| 17 | |||
| 18 | 150 ENET MAC 0 IRQ | ||
| 19 | 151 ENET MAC 0 1588 Timer interrupt | ||
| 20 | |||
| 21 | where | ||
| 22 | |||
| 23 | 150 - 32 == 118 | ||
| 24 | 151 - 32 == 119 | ||
| 25 | |||
| 26 | In other words, the vector definitions in the fsl-imx6.h file are reversed. | ||
| 27 | |||
| 28 | Fixing the interrupts alone causes problems with older Linux kernels: | ||
| 29 | The Ethernet interface will fail to probe with Linux v4.9 and earlier. | ||
| 30 | Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe | ||
| 31 | error handling. This is a Linux kernel problem, not a qemu problem: | ||
| 32 | the Linux kernel only worked by accident since it requested both interrupts. | ||
| 33 | |||
| 34 | For backward compatibility, generate the Ethernet interrupt on both interrupt | ||
| 35 | lines. This was shown to work from all Linux kernel releases starting with | ||
| 36 | v3.16. | ||
| 37 | |||
| 38 | Link: https://bugs.launchpad.net/qemu/+bug/1753309 | ||
| 39 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
| 40 | Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net | ||
| 41 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 42 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 43 | --- | 14 | --- |
| 44 | include/hw/arm/fsl-imx6.h | 4 ++-- | 15 | target/arm/translate-a64.c | 3 ++- |
| 45 | hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++- | 16 | 1 file changed, 2 insertions(+), 1 deletion(-) |
| 46 | 2 files changed, 29 insertions(+), 3 deletions(-) | ||
| 47 | 17 | ||
| 48 | diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h | 18 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
| 49 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 50 | --- a/include/hw/arm/fsl-imx6.h | 20 | --- a/target/arm/translate-a64.c |
| 51 | +++ b/include/hw/arm/fsl-imx6.h | 21 | +++ b/target/arm/translate-a64.c |
| 52 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State { | 22 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, |
| 53 | #define FSL_IMX6_HDMI_MASTER_IRQ 115 | 23 | int imm5) |
| 54 | #define FSL_IMX6_HDMI_CEC_IRQ 116 | ||
| 55 | #define FSL_IMX6_MLB150_LOW_IRQ 117 | ||
| 56 | -#define FSL_IMX6_ENET_MAC_1588_IRQ 118 | ||
| 57 | -#define FSL_IMX6_ENET_MAC_IRQ 119 | ||
| 58 | +#define FSL_IMX6_ENET_MAC_IRQ 118 | ||
| 59 | +#define FSL_IMX6_ENET_MAC_1588_IRQ 119 | ||
| 60 | #define FSL_IMX6_PCIE1_IRQ 120 | ||
| 61 | #define FSL_IMX6_PCIE2_IRQ 121 | ||
| 62 | #define FSL_IMX6_PCIE3_IRQ 122 | ||
| 63 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
| 64 | index XXXXXXX..XXXXXXX 100644 | ||
| 65 | --- a/hw/net/imx_fec.c | ||
| 66 | +++ b/hw/net/imx_fec.c | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) | ||
| 68 | |||
| 69 | static void imx_eth_update(IMXFECState *s) | ||
| 70 | { | 24 | { |
| 71 | - if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) { | 25 | int size = ctz32(imm5); |
| 72 | + /* | 26 | - int index = imm5 >> (size + 1); |
| 73 | + * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER | 27 | + int index; |
| 74 | + * interrupts swapped. This worked with older versions of Linux (4.14 | 28 | |
| 75 | + * and older) since Linux associated both interrupt lines with Ethernet | 29 | if (size > 3 || (size == 3 && !is_q)) { |
| 76 | + * MAC interrupts. Specifically, | 30 | unallocated_encoding(s); |
| 77 | + * - Linux 4.15 and later have separate interrupt handlers for the MAC and | 31 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, |
| 78 | + * timer interrupts. Those versions of Linux fail with versions of QEMU | 32 | return; |
| 79 | + * with swapped interrupt assignments. | 33 | } |
| 80 | + * - In linux 4.14, both interrupt lines were registered with the Ethernet | 34 | |
| 81 | + * MAC interrupt handler. As a result, all versions of qemu happen to | 35 | + index = imm5 >> (size + 1); |
| 82 | + * work, though that is accidental. | 36 | tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), |
| 83 | + * - In Linux 4.9 and older, the timer interrupt was registered directly | 37 | vec_reg_offset(s, rn, index, size), |
| 84 | + * with the Ethernet MAC interrupt handler. The MAC interrupt was | 38 | is_q ? 16 : 8, vec_full_reg_size(s)); |
| 85 | + * redirected to a GPIO interrupt to work around erratum ERR006687. | ||
| 86 | + * This was implemented using the SOC's IOMUX block. In qemu, this GPIO | ||
| 87 | + * interrupt never fired since IOMUX is currently not supported in qemu. | ||
| 88 | + * Linux instead received MAC interrupts on the timer interrupt. | ||
| 89 | + * As a result, qemu versions with the swapped interrupt assignment work, | ||
| 90 | + * albeit accidentally, but qemu versions with the correct interrupt | ||
| 91 | + * assignment fail. | ||
| 92 | + * | ||
| 93 | + * To ensure that all versions of Linux work, generate ENET_INT_MAC | ||
| 94 | + * interrrupts on both interrupt lines. This should be changed if and when | ||
| 95 | + * qemu supports IOMUX. | ||
| 96 | + */ | ||
| 97 | + if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & | ||
| 98 | + (ENET_INT_MAC | ENET_INT_TS_TIMER)) { | ||
| 99 | qemu_set_irq(s->irq[1], 1); | ||
| 100 | } else { | ||
| 101 | qemu_set_irq(s->irq[1], 0); | ||
| 102 | -- | 39 | -- |
| 103 | 2.16.2 | 40 | 2.20.1 |
| 104 | 41 | ||
| 105 | 42 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | For the rpi1 and 2 we want to boot the Linux kernel via some | ||
| 2 | custom setup code that makes sure that the SMC instruction | ||
| 3 | acts as a no-op, because it's used for cache maintenance. | ||
| 4 | The rpi3 boots AArch64 kernels, which don't need SMC for | ||
| 5 | cache maintenance and always expect to be booted non-secure. | ||
| 6 | Don't fill in the aarch32-specific parts of the binfo struct. | ||
| 7 | 1 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 11 | Message-id: 20180313153458.26822-2-peter.maydell@linaro.org | ||
| 12 | --- | ||
| 13 | hw/arm/raspi.c | 17 +++++++++++++---- | ||
| 14 | 1 file changed, 13 insertions(+), 4 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/arm/raspi.c | ||
| 19 | +++ b/hw/arm/raspi.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
| 21 | binfo.board_id = raspi_boardid[version]; | ||
| 22 | binfo.ram_size = ram_size; | ||
| 23 | binfo.nb_cpus = smp_cpus; | ||
| 24 | - binfo.board_setup_addr = BOARDSETUP_ADDR; | ||
| 25 | - binfo.write_board_setup = write_board_setup; | ||
| 26 | - binfo.secure_board_setup = true; | ||
| 27 | - binfo.secure_boot = true; | ||
| 28 | + | ||
| 29 | + if (version <= 2) { | ||
| 30 | + /* The rpi1 and 2 require some custom setup code to run in Secure | ||
| 31 | + * mode before booting a kernel (to set up the SMC vectors so | ||
| 32 | + * that we get a no-op SMC; this is used by Linux to call the | ||
| 33 | + * firmware for some cache maintenance operations. | ||
| 34 | + * The rpi3 doesn't need this. | ||
| 35 | + */ | ||
| 36 | + binfo.board_setup_addr = BOARDSETUP_ADDR; | ||
| 37 | + binfo.write_board_setup = write_board_setup; | ||
| 38 | + binfo.secure_board_setup = true; | ||
| 39 | + binfo.secure_boot = true; | ||
| 40 | + } | ||
| 41 | |||
| 42 | /* Pi2 and Pi3 requires SMP setup */ | ||
| 43 | if (version >= 2) { | ||
| 44 | -- | ||
| 45 | 2.16.2 | ||
| 46 | |||
| 47 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Add some assertions that if we're about to boot an AArch64 kernel, | ||
| 2 | the board code has not mistakenly set either secure_boot or | ||
| 3 | secure_board_setup. It doesn't make sense to set secure_boot, | ||
| 4 | because all AArch64 kernels must be booted in non-secure mode. | ||
| 5 | 1 | ||
| 6 | It might in theory make sense to set secure_board_setup, but | ||
| 7 | we don't currently support that, because only the AArch32 | ||
| 8 | bootloader[] code calls this hook; bootloader_aarch64[] does not. | ||
| 9 | Since we don't have a current need for this functionality, just | ||
| 10 | assert that we don't try to use it. If it's needed we'll add | ||
| 11 | it later. | ||
| 12 | |||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 15 | Message-id: 20180313153458.26822-3-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | hw/arm/boot.c | 7 +++++++ | ||
| 18 | 1 file changed, 7 insertions(+) | ||
| 19 | |||
| 20 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/hw/arm/boot.c | ||
| 23 | +++ b/hw/arm/boot.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
| 25 | } else { | ||
| 26 | env->pstate = PSTATE_MODE_EL1h; | ||
| 27 | } | ||
| 28 | + /* AArch64 kernels never boot in secure mode */ | ||
| 29 | + assert(!info->secure_boot); | ||
| 30 | + /* This hook is only supported for AArch32 currently: | ||
| 31 | + * bootloader_aarch64[] will not call the hook, and | ||
| 32 | + * the code above has already dropped us into EL2 or EL1. | ||
| 33 | + */ | ||
| 34 | + assert(!info->secure_board_setup); | ||
| 35 | } | ||
| 36 | |||
| 37 | /* Set to non-secure if not a secure boot */ | ||
| 38 | -- | ||
| 39 | 2.16.2 | ||
| 40 | |||
| 41 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | If we're directly booting a Linux kernel and the CPU supports both | ||
| 2 | EL3 and EL2, we start the kernel in EL2, as it expects. We must also | ||
| 3 | set the SCR_EL3.HCE bit in this situation, so that the HVC | ||
| 4 | instruction is enabled rather than UNDEFing. Otherwise at least some | ||
| 5 | kernels will panic when trying to initialize KVM in the guest. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20180313153458.26822-4-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | hw/arm/boot.c | 5 +++++ | ||
| 11 | 1 file changed, 5 insertions(+) | ||
| 12 | |||
| 13 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/hw/arm/boot.c | ||
| 16 | +++ b/hw/arm/boot.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
| 18 | assert(!info->secure_board_setup); | ||
| 19 | } | ||
| 20 | |||
| 21 | + if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 22 | + /* If we have EL2 then Linux expects the HVC insn to work */ | ||
| 23 | + env->cp15.scr_el3 |= SCR_HCE; | ||
| 24 | + } | ||
| 25 | + | ||
| 26 | /* Set to non-secure if not a secure boot */ | ||
| 27 | if (!info->secure_boot && | ||
| 28 | (cs != first_cpu || !info->secure_board_setup)) { | ||
| 29 | -- | ||
| 30 | 2.16.2 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The TypeInfo and state struct for bcm2386 disagree about what the | ||
| 2 | parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, | ||
| 3 | but the BCM2386State struct only defines the parent_obj field | ||
| 4 | as DeviceState. This would have caused problems if anything | ||
| 5 | actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. | ||
| 6 | Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't | ||
| 7 | need any of the additional functionality TYPE_SYS_BUS_DEVICE | ||
| 8 | provides. | ||
| 9 | 1 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 13 | Message-id: 20180313153458.26822-5-peter.maydell@linaro.org | ||
| 14 | --- | ||
| 15 | hw/arm/bcm2836.c | 2 +- | ||
| 16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 17 | |||
| 18 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/hw/arm/bcm2836.c | ||
| 21 | +++ b/hw/arm/bcm2836.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
| 23 | |||
| 24 | static const TypeInfo bcm2836_type_info = { | ||
| 25 | .name = TYPE_BCM2836, | ||
| 26 | - .parent = TYPE_SYS_BUS_DEVICE, | ||
| 27 | + .parent = TYPE_DEVICE, | ||
| 28 | .instance_size = sizeof(BCM2836State), | ||
| 29 | .instance_init = bcm2836_init, | ||
| 30 | .class_init = bcm2836_class_init, | ||
| 31 | -- | ||
| 32 | 2.16.2 | ||
| 33 | |||
| 34 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The bcm2837 is pretty similar to the bcm2836, but it does have | ||
| 2 | some differences. Notably, the MPIDR affinity aff1 values it | ||
| 3 | sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 | ||
| 4 | uses, and if this is wrong Linux will not boot. | ||
| 5 | 1 | ||
| 6 | Rather than trying to have one device with properties that | ||
| 7 | configure it differently for the two cases, create two | ||
| 8 | separate QOM devices for the two SoCs. We use the same approach | ||
| 9 | as hw/arm/aspeed_soc.c and share code and have a data table | ||
| 10 | that might differ per-SoC. For the moment the two types don't | ||
| 11 | actually have different behaviour. | ||
| 12 | |||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 15 | Message-id: 20180313153458.26822-7-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ | ||
| 18 | hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- | ||
| 19 | hw/arm/raspi.c | 3 ++- | ||
| 20 | 3 files changed, 53 insertions(+), 6 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/include/hw/arm/bcm2836.h | ||
| 25 | +++ b/include/hw/arm/bcm2836.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ | ||
| 27 | |||
| 28 | #define BCM283X_NCPUS 4 | ||
| 29 | |||
| 30 | +/* These type names are for specific SoCs; other than instantiating | ||
| 31 | + * them, code using these devices should always handle them via the | ||
| 32 | + * BCM283x base class, so they have no BCM2836(obj) etc macros. | ||
| 33 | + */ | ||
| 34 | +#define TYPE_BCM2836 "bcm2836" | ||
| 35 | +#define TYPE_BCM2837 "bcm2837" | ||
| 36 | + | ||
| 37 | typedef struct BCM283XState { | ||
| 38 | /*< private >*/ | ||
| 39 | DeviceState parent_obj; | ||
| 40 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState { | ||
| 41 | BCM2835PeripheralState peripherals; | ||
| 42 | } BCM283XState; | ||
| 43 | |||
| 44 | +typedef struct BCM283XInfo BCM283XInfo; | ||
| 45 | + | ||
| 46 | +typedef struct BCM283XClass { | ||
| 47 | + DeviceClass parent_class; | ||
| 48 | + const BCM283XInfo *info; | ||
| 49 | +} BCM283XClass; | ||
| 50 | + | ||
| 51 | +#define BCM283X_CLASS(klass) \ | ||
| 52 | + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) | ||
| 53 | +#define BCM283X_GET_CLASS(obj) \ | ||
| 54 | + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) | ||
| 55 | + | ||
| 56 | #endif /* BCM2836_H */ | ||
| 57 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
| 58 | index XXXXXXX..XXXXXXX 100644 | ||
| 59 | --- a/hw/arm/bcm2836.c | ||
| 60 | +++ b/hw/arm/bcm2836.c | ||
| 61 | @@ -XXX,XX +XXX,XX @@ | ||
| 62 | /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ | ||
| 63 | #define BCM2836_CONTROL_BASE 0x40000000 | ||
| 64 | |||
| 65 | +struct BCM283XInfo { | ||
| 66 | + const char *name; | ||
| 67 | +}; | ||
| 68 | + | ||
| 69 | +static const BCM283XInfo bcm283x_socs[] = { | ||
| 70 | + { | ||
| 71 | + .name = TYPE_BCM2836, | ||
| 72 | + }, | ||
| 73 | + { | ||
| 74 | + .name = TYPE_BCM2837, | ||
| 75 | + }, | ||
| 76 | +}; | ||
| 77 | + | ||
| 78 | static void bcm2836_init(Object *obj) | ||
| 79 | { | ||
| 80 | BCM283XState *s = BCM283X(obj); | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = { | ||
| 82 | DEFINE_PROP_END_OF_LIST() | ||
| 83 | }; | ||
| 84 | |||
| 85 | -static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
| 86 | +static void bcm283x_class_init(ObjectClass *oc, void *data) | ||
| 87 | { | ||
| 88 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 89 | + BCM283XClass *bc = BCM283X_CLASS(oc); | ||
| 90 | |||
| 91 | - dc->props = bcm2836_props; | ||
| 92 | + bc->info = data; | ||
| 93 | dc->realize = bcm2836_realize; | ||
| 94 | + dc->props = bcm2836_props; | ||
| 95 | } | ||
| 96 | |||
| 97 | -static const TypeInfo bcm2836_type_info = { | ||
| 98 | +static const TypeInfo bcm283x_type_info = { | ||
| 99 | .name = TYPE_BCM283X, | ||
| 100 | .parent = TYPE_DEVICE, | ||
| 101 | .instance_size = sizeof(BCM283XState), | ||
| 102 | .instance_init = bcm2836_init, | ||
| 103 | - .class_init = bcm2836_class_init, | ||
| 104 | + .class_size = sizeof(BCM283XClass), | ||
| 105 | + .abstract = true, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static void bcm2836_register_types(void) | ||
| 109 | { | ||
| 110 | - type_register_static(&bcm2836_type_info); | ||
| 111 | + int i; | ||
| 112 | + | ||
| 113 | + type_register_static(&bcm283x_type_info); | ||
| 114 | + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { | ||
| 115 | + TypeInfo ti = { | ||
| 116 | + .name = bcm283x_socs[i].name, | ||
| 117 | + .parent = TYPE_BCM283X, | ||
| 118 | + .class_init = bcm283x_class_init, | ||
| 119 | + .class_data = (void *) &bcm283x_socs[i], | ||
| 120 | + }; | ||
| 121 | + type_register(&ti); | ||
| 122 | + } | ||
| 123 | } | ||
| 124 | |||
| 125 | type_init(bcm2836_register_types) | ||
| 126 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 127 | index XXXXXXX..XXXXXXX 100644 | ||
| 128 | --- a/hw/arm/raspi.c | ||
| 129 | +++ b/hw/arm/raspi.c | ||
| 130 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
| 131 | BusState *bus; | ||
| 132 | DeviceState *carddev; | ||
| 133 | |||
| 134 | - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); | ||
| 135 | + object_initialize(&s->soc, sizeof(s->soc), | ||
| 136 | + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); | ||
| 137 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), | ||
| 138 | &error_abort); | ||
| 139 | |||
| 140 | -- | ||
| 141 | 2.16.2 | ||
| 142 | |||
| 143 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The BCM2837 sets the Aff1 field of the MPIDR affinity values for the | ||
| 2 | CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it | ||
| 3 | is required for Linux to boot. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Message-id: 20180313153458.26822-8-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | hw/arm/bcm2836.c | 11 +++++++---- | ||
| 11 | 1 file changed, 7 insertions(+), 4 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/hw/arm/bcm2836.c | ||
| 16 | +++ b/hw/arm/bcm2836.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | ||
| 18 | |||
| 19 | struct BCM283XInfo { | ||
| 20 | const char *name; | ||
| 21 | + int clusterid; | ||
| 22 | }; | ||
| 23 | |||
| 24 | static const BCM283XInfo bcm283x_socs[] = { | ||
| 25 | { | ||
| 26 | .name = TYPE_BCM2836, | ||
| 27 | + .clusterid = 0xf, | ||
| 28 | }, | ||
| 29 | { | ||
| 30 | .name = TYPE_BCM2837, | ||
| 31 | + .clusterid = 0x0, | ||
| 32 | }, | ||
| 33 | }; | ||
| 34 | |||
| 35 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) | ||
| 36 | static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 37 | { | ||
| 38 | BCM283XState *s = BCM283X(dev); | ||
| 39 | + BCM283XClass *bc = BCM283X_GET_CLASS(dev); | ||
| 40 | + const BCM283XInfo *info = bc->info; | ||
| 41 | Object *obj; | ||
| 42 | Error *err = NULL; | ||
| 43 | int n; | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 45 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | ||
| 46 | |||
| 47 | for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 48 | - /* Mirror bcm2836, which has clusterid set to 0xf | ||
| 49 | - * TODO: this should be converted to a property of ARM_CPU | ||
| 50 | - */ | ||
| 51 | - s->cpus[n].mp_affinity = 0xF00 | n; | ||
| 52 | + /* TODO: this should be converted to a property of ARM_CPU */ | ||
| 53 | + s->cpus[n].mp_affinity = (info->clusterid << 8) | n; | ||
| 54 | |||
| 55 | /* set periphbase/CBAR value for CPU-local registers */ | ||
| 56 | object_property_set_int(OBJECT(&s->cpus[n]), | ||
| 57 | -- | ||
| 58 | 2.16.2 | ||
| 59 | |||
| 60 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Now we have separate types for BCM2386 and BCM2387, we might as well | ||
| 2 | just hard-code the CPU type they use rather than having it passed | ||
| 3 | through as an object property. This then lets us put the initialization | ||
| 4 | of the CPU object in init rather than realize. | ||
| 5 | 1 | ||
| 6 | Note that this change means that it's no longer possible on | ||
| 7 | the command line to use -cpu to ask for a different kind of | ||
| 8 | CPU than the SoC supports. This was never a supported thing to | ||
| 9 | do anyway; we were just not sanity-checking the command line. | ||
| 10 | |||
| 11 | This does require us to only build the bcm2837 object on | ||
| 12 | TARGET_AARCH64 configs, since otherwise it won't instantiate | ||
| 13 | due to the missing cortex-a53 device and "make check" will fail. | ||
| 14 | |||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 17 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 18 | Message-id: 20180313153458.26822-9-peter.maydell@linaro.org | ||
| 19 | --- | ||
| 20 | hw/arm/bcm2836.c | 24 +++++++++++++++--------- | ||
| 21 | hw/arm/raspi.c | 2 -- | ||
| 22 | 2 files changed, 15 insertions(+), 11 deletions(-) | ||
| 23 | |||
| 24 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/hw/arm/bcm2836.c | ||
| 27 | +++ b/hw/arm/bcm2836.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ | ||
| 29 | |||
| 30 | struct BCM283XInfo { | ||
| 31 | const char *name; | ||
| 32 | + const char *cpu_type; | ||
| 33 | int clusterid; | ||
| 34 | }; | ||
| 35 | |||
| 36 | static const BCM283XInfo bcm283x_socs[] = { | ||
| 37 | { | ||
| 38 | .name = TYPE_BCM2836, | ||
| 39 | + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), | ||
| 40 | .clusterid = 0xf, | ||
| 41 | }, | ||
| 42 | +#ifdef TARGET_AARCH64 | ||
| 43 | { | ||
| 44 | .name = TYPE_BCM2837, | ||
| 45 | + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), | ||
| 46 | .clusterid = 0x0, | ||
| 47 | }, | ||
| 48 | +#endif | ||
| 49 | }; | ||
| 50 | |||
| 51 | static void bcm2836_init(Object *obj) | ||
| 52 | { | ||
| 53 | BCM283XState *s = BCM283X(obj); | ||
| 54 | + BCM283XClass *bc = BCM283X_GET_CLASS(obj); | ||
| 55 | + const BCM283XInfo *info = bc->info; | ||
| 56 | + int n; | ||
| 57 | + | ||
| 58 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 59 | + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
| 60 | + info->cpu_type); | ||
| 61 | + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
| 62 | + &error_abort); | ||
| 63 | + } | ||
| 64 | |||
| 65 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | ||
| 66 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 68 | |||
| 69 | /* common peripherals from bcm2835 */ | ||
| 70 | |||
| 71 | - obj = OBJECT(dev); | ||
| 72 | - for (n = 0; n < BCM283X_NCPUS; n++) { | ||
| 73 | - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
| 74 | - s->cpu_type); | ||
| 75 | - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
| 76 | - &error_abort); | ||
| 77 | - } | ||
| 78 | - | ||
| 79 | obj = object_property_get_link(OBJECT(dev), "ram", &err); | ||
| 80 | if (obj == NULL) { | ||
| 81 | error_setg(errp, "%s: required ram link not found: %s", | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
| 83 | } | ||
| 84 | |||
| 85 | static Property bcm2836_props[] = { | ||
| 86 | - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), | ||
| 87 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, | ||
| 88 | BCM283X_NCPUS), | ||
| 89 | DEFINE_PROP_END_OF_LIST() | ||
| 90 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 91 | index XXXXXXX..XXXXXXX 100644 | ||
| 92 | --- a/hw/arm/raspi.c | ||
| 93 | +++ b/hw/arm/raspi.c | ||
| 94 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
| 95 | /* Setup the SOC */ | ||
| 96 | object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), | ||
| 97 | &error_abort); | ||
| 98 | - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", | ||
| 99 | - &error_abort); | ||
| 100 | object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", | ||
| 101 | &error_abort); | ||
| 102 | int board_rev = version == 3 ? 0xa02082 : 0xa21041; | ||
| 103 | -- | ||
| 104 | 2.16.2 | ||
| 105 | |||
| 106 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The raspi3 has AArch64 CPUs, which means that our smpboot | ||
| 2 | code for keeping the secondary CPUs in a pen needs to have | ||
| 3 | a version for A64 as well as A32. Without this, the | ||
| 4 | secondary CPUs go into an infinite loop of taking undefined | ||
| 5 | instruction exceptions. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 9 | Message-id: 20180313153458.26822-10-peter.maydell@linaro.org | ||
| 10 | --- | ||
| 11 | hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- | ||
| 12 | 1 file changed, 40 insertions(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/hw/arm/raspi.c | ||
| 17 | +++ b/hw/arm/raspi.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ | ||
| 19 | #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ | ||
| 20 | #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ | ||
| 21 | #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ | ||
| 22 | +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ | ||
| 23 | |||
| 24 | /* Table of Linux board IDs for different Pi versions */ | ||
| 25 | static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) | ||
| 27 | info->smp_loader_start); | ||
| 28 | } | ||
| 29 | |||
| 30 | +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) | ||
| 31 | +{ | ||
| 32 | + /* Unlike the AArch32 version we don't need to call the board setup hook. | ||
| 33 | + * The mechanism for doing the spin-table is also entirely different. | ||
| 34 | + * We must have four 64-bit fields at absolute addresses | ||
| 35 | + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for | ||
| 36 | + * our CPUs, and which we must ensure are zero initialized before | ||
| 37 | + * the primary CPU goes into the kernel. We put these variables inside | ||
| 38 | + * a rom blob, so that the reset for ROM contents zeroes them for us. | ||
| 39 | + */ | ||
| 40 | + static const uint32_t smpboot[] = { | ||
| 41 | + 0xd2801b05, /* mov x5, 0xd8 */ | ||
| 42 | + 0xd53800a6, /* mrs x6, mpidr_el1 */ | ||
| 43 | + 0x924004c6, /* and x6, x6, #0x3 */ | ||
| 44 | + 0xd503205f, /* spin: wfe */ | ||
| 45 | + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ | ||
| 46 | + 0xb4ffffc4, /* cbz x4, spin */ | ||
| 47 | + 0xd2800000, /* mov x0, #0x0 */ | ||
| 48 | + 0xd2800001, /* mov x1, #0x0 */ | ||
| 49 | + 0xd2800002, /* mov x2, #0x0 */ | ||
| 50 | + 0xd2800003, /* mov x3, #0x0 */ | ||
| 51 | + 0xd61f0080, /* br x4 */ | ||
| 52 | + }; | ||
| 53 | + | ||
| 54 | + static const uint64_t spintables[] = { | ||
| 55 | + 0, 0, 0, 0 | ||
| 56 | + }; | ||
| 57 | + | ||
| 58 | + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), | ||
| 59 | + info->smp_loader_start); | ||
| 60 | + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), | ||
| 61 | + SPINTABLE_ADDR); | ||
| 62 | +} | ||
| 63 | + | ||
| 64 | static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) | ||
| 65 | { | ||
| 66 | arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
| 68 | /* Pi2 and Pi3 requires SMP setup */ | ||
| 69 | if (version >= 2) { | ||
| 70 | binfo.smp_loader_start = SMPBOOT_ADDR; | ||
| 71 | - binfo.write_secondary_boot = write_smpboot; | ||
| 72 | + if (version == 2) { | ||
| 73 | + binfo.write_secondary_boot = write_smpboot; | ||
| 74 | + } else { | ||
| 75 | + binfo.write_secondary_boot = write_smpboot64; | ||
| 76 | + } | ||
| 77 | binfo.secondary_cpu_reset_hook = reset_secondary; | ||
| 78 | } | ||
| 79 | |||
| 80 | -- | ||
| 81 | 2.16.2 | ||
| 82 | |||
| 83 | diff view generated by jsdifflib |