Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[PULL 00/15] target-arm queue
-Arm patch queue -- these are all bug fix patches but we might
+Latest arm queue, a mixed bag of features and bug fixes.
 as well put them in to rc0...
 thanks
 -- PMM
-The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
+The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
+  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (2020-01-17 12:13:17 +0000)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200117-1
-for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
+for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:
-  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
+  target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +0000)
 ----------------------------------------------------------------
-target-arm queue:
+Add model of the Netduino Plus 2 board
- * fsl-imx6: Fix incorrect Ethernet interrupt defines
+Some allwinner-a10 code cleanup
- * dump: Update correct kdump phys_base field for AArch64
+New test cases for cubieboard
- * char: i.MX: Add support for "TX complete" interrupt
+target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
- * bcm2836/raspi: Fix various bugs resulting in panics trying
+i.MX: add an emulation for RNGC device
-   to boot a Debian Linux kernel on raspi3
+target/arm: adjust program counter for wfi exception in AArch32
 arm/gicv3: update virtual irq state after IAR register read
 Set IL bit correctly for syndrome information for data aborts
 ----------------------------------------------------------------
-Andrey Smirnov (2):
+Alistair Francis (4):
-      char: i.MX: Simplify imx_update()
+      hw/misc: Add the STM32F4xx Sysconfig device
-      char: i.MX: Add support for "TX complete" interrupt
+      hw/misc: Add the STM32F4xx EXTI device
       hw/arm: Add the STM32F4xx SoC
       hw/arm: Add the Netduino Plus 2
-Guenter Roeck (1):
+Jeff Kubascik (3):
-      fsl-imx6: Swap Ethernet interrupt defines
+      target/arm: adjust program counter for wfi exception in AArch32
       arm/gicv3: update virtual irq state after IAR register read
       target/arm: Return correct IL bit in merge_syn_data_abort
-Peter Maydell (9):
+Martin Kaiser (1):
-      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+      i.MX: add an emulation for RNGC
       hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
       hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
       hw/arm/bcm2386: Fix parent type of bcm2386
       hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
       hw/arm/bcm2836: Create proper bcm2837 device
       hw/arm/bcm2836: Use correct affinity values for BCM2837
       hw/arm/bcm2836: Hardcode correct CPU type
       hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
-Wei Huang (1):
+Masahiro Yamada (1):
-      dump: Update correct kdump phys_base field for AArch64
+      target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
- include/hw/arm/bcm2836.h     | 31 +++++++++++++---
+Philippe Mathieu-Daudé (5):
- include/hw/arm/fsl-imx6.h    |  4 +-
+      tests/boot_linux_console: Add initrd test for the CubieBoard
- include/hw/char/imx_serial.h |  3 ++
+      tests/boot_linux_console: Add a SD card test for the CubieBoard
- dump.c                       | 14 +++++--
+      hw/arm/allwinner-a10: Move SoC definitions out of header
- hw/arm/bcm2836.c             | 87 +++++++++++++++++++++++++++++++-------------
+      hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
- hw/arm/boot.c                | 12 ++++++
+      hw/arm/allwinner-a10: Remove local qemu_irq variables
  hw/arm/raspi.c               | 77 +++++++++++++++++++++++++++++++--------
  hw/char/imx_serial.c         | 44 ++++++++++++++++------
  hw/net/imx_fec.c             | 28 +++++++++++++-
 files changed, 237 insertions(+), 63 deletions(-)
+Richard Henderson (1):
+      target/arm: Set ISSIs16Bit in make_issinfo
+ hw/arm/Makefile.objs                   |   2 +
+ hw/misc/Makefile.objs                  |   3 +
+ include/hw/arm/allwinner-a10.h         |   7 -
+ include/hw/arm/fsl-imx25.h             |   5 +
+ include/hw/arm/stm32f405_soc.h         |  73 ++++++++
+ include/hw/misc/imx_rngc.h             |  35 ++++
+ include/hw/misc/stm32f4xx_exti.h       |  60 +++++++
+ include/hw/misc/stm32f4xx_syscfg.h     |  61 +++++++
+ hw/arm/allwinner-a10.c                 |  39 +++--
+ hw/arm/fsl-imx25.c                     |  11 ++
+ hw/arm/netduinoplus2.c                 |  52 ++++++
+ hw/arm/stm32f405_soc.c                 | 302 +++++++++++++++++++++++++++++++++
+ hw/intc/arm_gicv3_cpuif.c              |   3 +
+ hw/misc/imx_rngc.c                     | 278 ++++++++++++++++++++++++++++++
+ hw/misc/stm32f4xx_exti.c               | 188 ++++++++++++++++++++
+ hw/misc/stm32f4xx_syscfg.c             | 171 +++++++++++++++++++
+ target/arm/arm-semi.c                  |   5 +-
+ target/arm/op_helper.c                 |   7 +-
+ target/arm/tlb_helper.c                |   2 +-
+ target/arm/translate.c                 |   3 +
+ MAINTAINERS                            |  14 ++
+ default-configs/arm-softmmu.mak        |   1 +
+ hw/arm/Kconfig                         |  10 ++
+ hw/misc/Kconfig                        |   6 +
+ hw/misc/trace-events                   |  11 ++
+ tests/acceptance/boot_linux_console.py |  85 ++++++++++
+files changed, 1405 insertions(+), 29 deletions(-)
+ create mode 100644 include/hw/arm/stm32f405_soc.h
+ create mode 100644 include/hw/misc/imx_rngc.h
+ create mode 100644 include/hw/misc/stm32f4xx_exti.h
+ create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
+ create mode 100644 hw/arm/netduinoplus2.c
+ create mode 100644 hw/arm/stm32f405_soc.c
+ create mode 100644 hw/misc/imx_rngc.c
+ create mode 100644 hw/misc/stm32f4xx_exti.c
+ create mode 100644 hw/misc/stm32f4xx_syscfg.c

-[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
+[PULL 01/15] hw/misc: Add the STM32F4xx Sysconfig device
-The bcm2837 is pretty similar to the bcm2836, but it does have
+From: Alistair Francis <alistair@alistair23.me>
 some differences. Notably, the MPIDR affinity aff1 values it
 sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
 uses, and if this is wrong Linux will not boot.
-Rather than trying to have one device with properties that
+Signed-off-by: Alistair Francis <alistair@alistair23.me>
-configure it differently for the two cases, create two
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-separate QOM devices for the two SoCs. We use the same approach
+Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me
-as hw/arm/aspeed_soc.c and share code and have a data table
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-that might differ per-SoC. For the moment the two types don't
+---
-actually have different behaviour.
+ hw/misc/Makefile.objs              |   1 +
  include/hw/misc/stm32f4xx_syscfg.h |  61 ++++++++++
  hw/misc/stm32f4xx_syscfg.c         | 171 +++++++++++++++++++++++++++++
  default-configs/arm-softmmu.mak    |   1 +
  hw/arm/Kconfig                     |   9 ++
  hw/misc/Kconfig                    |   3 +
  hw/misc/trace-events               |   6 +
 files changed, 252 insertions(+)
  create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
  create mode 100644 hw/misc/stm32f4xx_syscfg.c
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+index XXXXXXX..XXXXXXX 100644
-Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
+--- a/hw/misc/Makefile.objs
----
++++ b/hw/misc/Makefile.objs
- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
+@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
- hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
+ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
- hw/arm/raspi.c           |  3 ++-
+ common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
-files changed, 53 insertions(+), 6 deletions(-)
+ common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
++common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+ obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
-index XXXXXXX..XXXXXXX 100644
+ obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
---- a/include/hw/arm/bcm2836.h
+ obj-$(CONFIG_MIPS_ITU) += mips_itu.o
-+++ b/include/hw/arm/bcm2836.h
+diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/stm32f4xx_syscfg.h
 @@ -XXX,XX +XXX,XX @@
++/*
- #define BCM283X_NCPUS 4
++ * STM32F4xx SYSCFG
++ *
-+/* These type names are for specific SoCs; other than instantiating
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
-+ * them, code using these devices should always handle them via the
++ *
-+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
-+#define TYPE_BCM2836 "bcm2836"
++
-+#define TYPE_BCM2837 "bcm2837"
++#ifndef HW_STM_SYSCFG_H
-+
++#define HW_STM_SYSCFG_H
- typedef struct BCM283XState {
++
-     /*< private >*/
++#include "hw/sysbus.h"
-     DeviceState parent_obj;
++#include "hw/hw.h"
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
++
-     BCM2835PeripheralState peripherals;
++#define SYSCFG_MEMRMP  0x00
- } BCM283XState;
++#define SYSCFG_PMC     0x04
++#define SYSCFG_EXTICR1 0x08
-+typedef struct BCM283XInfo BCM283XInfo;
++#define SYSCFG_EXTICR2 0x0C
-+
++#define SYSCFG_EXTICR3 0x10
-+typedef struct BCM283XClass {
++#define SYSCFG_EXTICR4 0x14
-+    DeviceClass parent_class;
++#define SYSCFG_CMPCR   0x20
-+    const BCM283XInfo *info;
++
-+} BCM283XClass;
++#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
-+
++#define STM32F4XX_SYSCFG(obj) \
-+#define BCM283X_CLASS(klass) \
++    OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG)
-+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
++
-+#define BCM283X_GET_CLASS(obj) \
++#define SYSCFG_NUM_EXTICR 4
-+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
++
-+
++typedef struct {
- #endif /* BCM2836_H */
++    /* <private> */
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
++    SysBusDevice parent_obj;
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/arm/bcm2836.c
++    /* <public> */
-+++ b/hw/arm/bcm2836.c
++    MemoryRegion mmio;
 +
 +    uint32_t syscfg_memrmp;
 +    uint32_t syscfg_pmc;
 +    uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];
 +    uint32_t syscfg_cmpcr;
 +
 +    qemu_irq irq;
 +    qemu_irq gpio_out[16];
 +} STM32F4xxSyscfgState;
 +
 +#endif
 diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/stm32f4xx_syscfg.c
 @@ -XXX,XX +XXX,XX @@
- /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
++/*
- #define BCM2836_CONTROL_BASE    0x40000000
++ * STM32F4xx SYSCFG
++ *
-+struct BCM283XInfo {
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
-+    const char *name;
++ *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "trace.h"
 +#include "hw/irq.h"
 +#include "migration/vmstate.h"
 +#include "hw/misc/stm32f4xx_syscfg.h"
 +
 +static void stm32f4xx_syscfg_reset(DeviceState *dev)
 +{
 +    STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);
 +
 +    s->syscfg_memrmp = 0x00000000;
 +    s->syscfg_pmc = 0x00000000;
 +    s->syscfg_exticr[0] = 0x00000000;
 +    s->syscfg_exticr[1] = 0x00000000;
 +    s->syscfg_exticr[2] = 0x00000000;
 +    s->syscfg_exticr[3] = 0x00000000;
 +    s->syscfg_cmpcr = 0x00000000;
 +}
 +
 +static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)
 +{
 +    STM32F4xxSyscfgState *s = opaque;
 +    int icrreg = irq / 4;
 +    int startbit = (irq & 3) * 4;
 +    uint8_t config = config = irq / 16;
 +
 +    trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);
 +
 +    g_assert(icrreg < SYSCFG_NUM_EXTICR);
 +
 +    if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
 +        qemu_set_irq(s->gpio_out[irq], level);
 +        trace_stm32f4xx_pulse_exti(irq);
 +   }
 +}
 +
 +static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,
 +                                     unsigned int size)
 +{
 +    STM32F4xxSyscfgState *s = opaque;
 +
 +    trace_stm32f4xx_syscfg_read(addr);
 +
 +    switch (addr) {
 +    case SYSCFG_MEMRMP:
 +        return s->syscfg_memrmp;
 +    case SYSCFG_PMC:
 +        return s->syscfg_pmc;
 +    case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
 +        return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];
 +    case SYSCFG_CMPCR:
 +        return s->syscfg_cmpcr;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +        return 0;
 +    }
 +}
 +
 +static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,
 +                       uint64_t val64, unsigned int size)
 +{
 +    STM32F4xxSyscfgState *s = opaque;
 +    uint32_t value = val64;
 +
 +    trace_stm32f4xx_syscfg_write(value, addr);
 +
 +    switch (addr) {
 +    case SYSCFG_MEMRMP:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: Changing the memory mapping isn't supported " \
 +                      "in QEMU\n", __func__);
 +        return;
 +    case SYSCFG_PMC:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: Changing the memory mapping isn't supported " \
 +                      "in QEMU\n", __func__);
 +        return;
 +    case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
 +        s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);
 +        return;
 +    case SYSCFG_CMPCR:
 +        s->syscfg_cmpcr = value;
 +        return;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 +    }
 +}
 +
 +static const MemoryRegionOps stm32f4xx_syscfg_ops = {
 +    .read = stm32f4xx_syscfg_read,
 +    .write = stm32f4xx_syscfg_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +};
 +
-+static const BCM283XInfo bcm283x_socs[] = {
++static void stm32f4xx_syscfg_init(Object *obj)
-+    {
++{
-+        .name = TYPE_BCM2836,
++    STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);
-+    },
++
-+    {
++    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-+        .name = TYPE_BCM2837,
++
-+    },
++    memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,
 +                          TYPE_STM32F4XX_SYSCFG, 0x400);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 +
 +    qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);
 +    qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
 +}
 +
 +static const VMStateDescription vmstate_stm32f4xx_syscfg = {
 +    .name = TYPE_STM32F4XX_SYSCFG,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),
 +        VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),
 +        VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,
 +                             SYSCFG_NUM_EXTICR),
 +        VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
- static void bcm2836_init(Object *obj)
++static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)
- {
++{
-     BCM283XState *s = BCM283X(obj);
++    DeviceClass *dc = DEVICE_CLASS(klass);
-@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
++
-     DEFINE_PROP_END_OF_LIST()
++    dc->reset = stm32f4xx_syscfg_reset;
- };
++    dc->vmsd = &vmstate_stm32f4xx_syscfg;
++}
--static void bcm2836_class_init(ObjectClass *oc, void *data)
++
-+static void bcm283x_class_init(ObjectClass *oc, void *data)
++static const TypeInfo stm32f4xx_syscfg_info = {
- {
++    .name          = TYPE_STM32F4XX_SYSCFG,
-     DeviceClass *dc = DEVICE_CLASS(oc);
++    .parent        = TYPE_SYS_BUS_DEVICE,
-+    BCM283XClass *bc = BCM283X_CLASS(oc);
++    .instance_size = sizeof(STM32F4xxSyscfgState),
++    .instance_init = stm32f4xx_syscfg_init,
--    dc->props = bcm2836_props;
++    .class_init    = stm32f4xx_syscfg_class_init,
-+    bc->info = data;
++};
-     dc->realize = bcm2836_realize;
++
-+    dc->props = bcm2836_props;
++static void stm32f4xx_syscfg_register_types(void)
- }
++{
++    type_register_static(&stm32f4xx_syscfg_info);
--static const TypeInfo bcm2836_type_info = {
++}
-+static const TypeInfo bcm283x_type_info = {
++
-     .name = TYPE_BCM283X,
++type_init(stm32f4xx_syscfg_register_types)
-     .parent = TYPE_DEVICE,
+diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
-     .instance_size = sizeof(BCM283XState),
+index XXXXXXX..XXXXXXX 100644
-     .instance_init = bcm2836_init,
+--- a/default-configs/arm-softmmu.mak
--    .class_init = bcm2836_class_init,
++++ b/default-configs/arm-softmmu.mak
-+    .class_size = sizeof(BCM283XClass),
+@@ -XXX,XX +XXX,XX @@ CONFIG_Z2=y
-+    .abstract = true,
+ CONFIG_COLLIE=y
- };
+ CONFIG_ASPEED_SOC=y
+ CONFIG_NETDUINO2=y
- static void bcm2836_register_types(void)
++CONFIG_NETDUINOPLUS2=y
- {
+ CONFIG_MPS2=y
--    type_register_static(&bcm2836_type_info);
+ CONFIG_RASPI=y
-+    int i;
+ CONFIG_DIGIC=y
-+
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
-+    type_register_static(&bcm283x_type_info);
+index XXXXXXX..XXXXXXX 100644
-+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+--- a/hw/arm/Kconfig
-+        TypeInfo ti = {
++++ b/hw/arm/Kconfig
-+            .name = bcm283x_socs[i].name,
+@@ -XXX,XX +XXX,XX @@ config NETDUINO2
-+            .parent = TYPE_BCM283X,
+     bool
-+            .class_init = bcm283x_class_init,
+     select STM32F205_SOC
-+            .class_data = (void *) &bcm283x_socs[i],
-+        };
++config NETDUINOPLUS2
-+        type_register(&ti);
++    bool
-+    }
++    select STM32F405_SOC
- }
++
+ config NSERIES
- type_init(bcm2836_register_types)
+     bool
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+     select OMAP
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC
---- a/hw/arm/raspi.c
+     select STM32F2XX_ADC
-+++ b/hw/arm/raspi.c
+     select STM32F2XX_SPI
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
-     BusState *bus;
++config STM32F405_SOC
-     DeviceState *carddev;
++    bool
++    select ARM_V7M
--    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
++    select STM32F4XX_SYSCFG
-+    object_initialize(&s->soc, sizeof(s->soc),
++
-+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
+ config XLNX_ZYNQMP_ARM
-     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
+     bool
-                               &error_abort);
+     select AHCI
+diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config IMX
  config STM32F2XX_SYSCFG
      bool
 +config STM32F4XX_SYSCFG
 +    bool
 +
  config MIPS_ITU
      bool
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
  mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
  mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
 +# stm32f4xx_syscfg
 +stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
 +stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
 +stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
 +stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
 +
  # tz-mpc.c
  tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
  tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
+[PULL 02/15] hw/misc: Add the STM32F4xx EXTI device
-Now we have separate types for BCM2386 and BCM2387, we might as well
+From: Alistair Francis <alistair@alistair23.me>
 just hard-code the CPU type they use rather than having it passed
 through as an object property. This then lets us put the initialization
 of the CPU object in init rather than realize.
-Note that this change means that it's no longer possible on
+Signed-off-by: Alistair Francis <alistair@alistair23.me>
-the command line to use -cpu to ask for a different kind of
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-CPU than the SoC supports. This was never a supported thing to
+Message-id: ef941d59fd8658589d34ed432e1d6dfdcf7fb1d0.1576658572.git.alistair@alistair23.me
-do anyway; we were just not sanity-checking the command line.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/misc/Makefile.objs            |   1 +
  include/hw/misc/stm32f4xx_exti.h |  60 ++++++++++
  hw/misc/stm32f4xx_exti.c         | 188 +++++++++++++++++++++++++++++++
  hw/arm/Kconfig                   |   1 +
  hw/misc/Kconfig                  |   3 +
  hw/misc/trace-events             |   5 +
 files changed, 258 insertions(+)
  create mode 100644 include/hw/misc/stm32f4xx_exti.h
  create mode 100644 hw/misc/stm32f4xx_exti.c
-This does require us to only build the bcm2837 object on
+diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
 TARGET_AARCH64 configs, since otherwise it won't instantiate
 due to the missing cortex-a53 device and "make check" will fail.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
 ---
  hw/arm/bcm2836.c | 24 +++++++++++++++---------
  hw/arm/raspi.c   |  2 --
 files changed, 15 insertions(+), 11 deletions(-)
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/misc/Makefile.objs
-+++ b/hw/arm/bcm2836.c
++++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
  common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
  common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
  common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
 +common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o
  obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
  obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
  obj-$(CONFIG_MIPS_ITU) += mips_itu.o
 diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/stm32f4xx_exti.h
 @@ -XXX,XX +XXX,XX @@
++/*
- struct BCM283XInfo {
++ * STM32F4XX EXTI
-     const char *name;
++ *
-+    const char *cpu_type;
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
-     int clusterid;
++ *
- };
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * of this software and associated documentation files (the "Software"), to deal
- static const BCM283XInfo bcm283x_socs[] = {
++ * in the Software without restriction, including without limitation the rights
-     {
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-         .name = TYPE_BCM2836,
++ * copies of the Software, and to permit persons to whom the Software is
-+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
++ * furnished to do so, subject to the following conditions:
-         .clusterid = 0xf,
++ *
-     },
++ * The above copyright notice and this permission notice shall be included in
-+#ifdef TARGET_AARCH64
++ * all copies or substantial portions of the Software.
-     {
++ *
-         .name = TYPE_BCM2837,
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-         .clusterid = 0x0,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-     },
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_STM_EXTI_H
 +#define HW_STM_EXTI_H
 +
 +#include "hw/sysbus.h"
 +#include "hw/hw.h"
 +
 +#define EXTI_IMR   0x00
 +#define EXTI_EMR   0x04
 +#define EXTI_RTSR  0x08
 +#define EXTI_FTSR  0x0C
 +#define EXTI_SWIER 0x10
 +#define EXTI_PR    0x14
 +
 +#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"
 +#define STM32F4XX_EXTI(obj) \
 +    OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI)
 +
 +#define NUM_GPIO_EVENT_IN_LINES 16
 +#define NUM_INTERRUPT_OUT_LINES 16
 +
 +typedef struct {
 +    SysBusDevice parent_obj;
 +
 +    MemoryRegion mmio;
 +
 +    uint32_t exti_imr;
 +    uint32_t exti_emr;
 +    uint32_t exti_rtsr;
 +    uint32_t exti_ftsr;
 +    uint32_t exti_swier;
 +    uint32_t exti_pr;
 +
 +    qemu_irq irq[NUM_INTERRUPT_OUT_LINES];
 +} STM32F4xxExtiState;
 +
 +#endif
- };
+diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c
+new file mode 100644
- static void bcm2836_init(Object *obj)
+index XXXXXXX..XXXXXXX
- {
+--- /dev/null
-     BCM283XState *s = BCM283X(obj);
++++ b/hw/misc/stm32f4xx_exti.c
-+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+@@ -XXX,XX +XXX,XX @@
-+    const BCM283XInfo *info = bc->info;
++/*
-+    int n;
++ * STM32F4XX EXTI
-+
++ *
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
-+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
++ *
-+                          info->cpu_type);
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
++ * of this software and associated documentation files (the "Software"), to deal
-+                                  &error_abort);
++ * in the Software without restriction, including without limitation the rights
-+    }
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
++ * copies of the Software, and to permit persons to whom the Software is
-     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
++ * furnished to do so, subject to the following conditions:
-     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
++ *
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
-     /* common peripherals from bcm2835 */
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--    obj = OBJECT(dev);
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--    for (n = 0; n < BCM283X_NCPUS; n++) {
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
--        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--                          s->cpu_type);
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
--                                  &error_abort);
++ * THE SOFTWARE.
--    }
++ */
--
++
-     obj = object_property_get_link(OBJECT(dev), "ram", &err);
++#include "qemu/osdep.h"
-     if (obj == NULL) {
++#include "qemu/log.h"
-         error_setg(errp, "%s: required ram link not found: %s",
++#include "trace.h"
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
++#include "hw/irq.h"
- }
++#include "migration/vmstate.h"
++#include "hw/misc/stm32f4xx_exti.h"
- static Property bcm2836_props[] = {
++
--    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
++static void stm32f4xx_exti_reset(DeviceState *dev)
-     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
++{
-                        BCM283X_NCPUS),
++    STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);
-     DEFINE_PROP_END_OF_LIST()
++
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
++    s->exti_imr = 0x00000000;
 +    s->exti_emr = 0x00000000;
 +    s->exti_rtsr = 0x00000000;
 +    s->exti_ftsr = 0x00000000;
 +    s->exti_swier = 0x00000000;
 +    s->exti_pr = 0x00000000;
 +}
 +
 +static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)
 +{
 +    STM32F4xxExtiState *s = opaque;
 +
 +    trace_stm32f4xx_exti_set_irq(irq, level);
 +
 +    if (((1 << irq) & s->exti_rtsr) && level) {
 +        /* Rising Edge */
 +        s->exti_pr |= 1 << irq;
 +    }
 +
 +    if (((1 << irq) & s->exti_ftsr) && !level) {
 +        /* Falling Edge */
 +        s->exti_pr |= 1 << irq;
 +    }
 +
 +    if (!((1 << irq) & s->exti_imr)) {
 +        /* Interrupt is masked */
 +        return;
 +    }
 +    qemu_irq_pulse(s->irq[irq]);
 +}
 +
 +static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,
 +                                     unsigned int size)
 +{
 +    STM32F4xxExtiState *s = opaque;
 +
 +    trace_stm32f4xx_exti_read(addr);
 +
 +    switch (addr) {
 +    case EXTI_IMR:
 +        return s->exti_imr;
 +    case EXTI_EMR:
 +        return s->exti_emr;
 +    case EXTI_RTSR:
 +        return s->exti_rtsr;
 +    case EXTI_FTSR:
 +        return s->exti_ftsr;
 +    case EXTI_SWIER:
 +        return s->exti_swier;
 +    case EXTI_PR:
 +        return s->exti_pr;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);
 +        return 0;
 +    }
 +    return 0;
 +}
 +
 +static void stm32f4xx_exti_write(void *opaque, hwaddr addr,
 +                       uint64_t val64, unsigned int size)
 +{
 +    STM32F4xxExtiState *s = opaque;
 +    uint32_t value = (uint32_t) val64;
 +
 +    trace_stm32f4xx_exti_write(addr, value);
 +
 +    switch (addr) {
 +    case EXTI_IMR:
 +        s->exti_imr = value;
 +        return;
 +    case EXTI_EMR:
 +        s->exti_emr = value;
 +        return;
 +    case EXTI_RTSR:
 +        s->exti_rtsr = value;
 +        return;
 +    case EXTI_FTSR:
 +        s->exti_ftsr = value;
 +        return;
 +    case EXTI_SWIER:
 +        s->exti_swier = value;
 +        return;
 +    case EXTI_PR:
 +        /* This bit is cleared by writing a 1 to it */
 +        s->exti_pr &= ~value;
 +        return;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);
 +    }
 +}
 +
 +static const MemoryRegionOps stm32f4xx_exti_ops = {
 +    .read = stm32f4xx_exti_read,
 +    .write = stm32f4xx_exti_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +};
 +
 +static void stm32f4xx_exti_init(Object *obj)
 +{
 +    STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);
 +    int i;
 +
 +    for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {
 +        sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
 +    }
 +
 +    memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,
 +                          TYPE_STM32F4XX_EXTI, 0x400);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 +
 +    qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,
 +                      NUM_GPIO_EVENT_IN_LINES);
 +}
 +
 +static const VMStateDescription vmstate_stm32f4xx_exti = {
 +    .name = TYPE_STM32F4XX_EXTI,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),
 +        VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),
 +        VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),
 +        VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),
 +        VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),
 +        VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->reset = stm32f4xx_exti_reset;
 +    dc->vmsd = &vmstate_stm32f4xx_exti;
 +}
 +
 +static const TypeInfo stm32f4xx_exti_info = {
 +    .name          = TYPE_STM32F4XX_EXTI,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(STM32F4xxExtiState),
 +    .instance_init = stm32f4xx_exti_init,
 +    .class_init    = stm32f4xx_exti_class_init,
 +};
 +
 +static void stm32f4xx_exti_register_types(void)
 +{
 +    type_register_static(&stm32f4xx_exti_info);
 +}
 +
 +type_init(stm32f4xx_exti_register_types)
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/hw/arm/Kconfig
-+++ b/hw/arm/raspi.c
++++ b/hw/arm/Kconfig
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
-     /* Setup the SOC */
+     bool
-     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
+     select ARM_V7M
-                                    &error_abort);
+     select STM32F4XX_SYSCFG
--    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
++    select STM32F4XX_EXTI
--                            &error_abort);
-     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
+ config XLNX_ZYNQMP_ARM
-                             &error_abort);
+     bool
-     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
+diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG
  config STM32F4XX_SYSCFG
      bool
 +config STM32F4XX_EXTI
 +    bool
 +
  config MIPS_ITU
      bool
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
  stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
  stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
 +# stm32f4xx_exti
 +stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
 +stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
 +stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
 +
  # tz-mpc.c
  tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
  tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
 --
-.16.2
+.20.1

-New patch
+[PULL 03/15] hw/arm: Add the STM32F4xx SoC
+From: Alistair Francis <alistair@alistair23.me>
+Signed-off-by: Alistair Francis <alistair@alistair23.me>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/Makefile.objs           |   1 +
+ include/hw/arm/stm32f405_soc.h |  73 ++++++++
+ hw/arm/stm32f405_soc.c         | 302 +++++++++++++++++++++++++++++++++
+ MAINTAINERS                    |   8 +
+files changed, 384 insertions(+)
+ create mode 100644 include/hw/arm/stm32f405_soc.h
+ create mode 100644 hw/arm/stm32f405_soc.c
+diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Makefile.objs
++++ b/hw/arm/Makefile.objs
+@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STRONGARM) += strongarm.o
+ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+ obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
+ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
++obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
+ obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
+ obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
+ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
+diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/arm/stm32f405_soc.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * STM32F405 SoC
++ *
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * of this software and associated documentation files (the "Software"), to deal
++ * in the Software without restriction, including without limitation the rights
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
++ * copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
++ * THE SOFTWARE.
++ */
++
++#ifndef HW_ARM_STM32F405_SOC_H
++#define HW_ARM_STM32F405_SOC_H
++
++#include "hw/misc/stm32f4xx_syscfg.h"
++#include "hw/timer/stm32f2xx_timer.h"
++#include "hw/char/stm32f2xx_usart.h"
++#include "hw/adc/stm32f2xx_adc.h"
++#include "hw/misc/stm32f4xx_exti.h"
++#include "hw/or-irq.h"
++#include "hw/ssi/stm32f2xx_spi.h"
++#include "hw/arm/armv7m.h"
++
++#define TYPE_STM32F405_SOC "stm32f405-soc"
++#define STM32F405_SOC(obj) \
++    OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
++
++#define STM_NUM_USARTS 7
++#define STM_NUM_TIMERS 4
++#define STM_NUM_ADCS 6
++#define STM_NUM_SPIS 6
++
++#define FLASH_BASE_ADDRESS 0x08000000
++#define FLASH_SIZE (1024 * 1024)
++#define SRAM_BASE_ADDRESS 0x20000000
++#define SRAM_SIZE (192 * 1024)
++
++typedef struct STM32F405State {
++    /*< private >*/
++    SysBusDevice parent_obj;
++    /*< public >*/
++
++    char *cpu_type;
++
++    ARMv7MState armv7m;
++
++    STM32F4xxSyscfgState syscfg;
++    STM32F4xxExtiState exti;
++    STM32F2XXUsartState usart[STM_NUM_USARTS];
++    STM32F2XXTimerState timer[STM_NUM_TIMERS];
++    qemu_or_irq adc_irqs;
++    STM32F2XXADCState adc[STM_NUM_ADCS];
++    STM32F2XXSPIState spi[STM_NUM_SPIS];
++
++    MemoryRegion sram;
++    MemoryRegion flash;
++    MemoryRegion flash_alias;
++} STM32F405State;
++
++#endif
+diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/arm/stm32f405_soc.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * STM32F405 SoC
++ *
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * of this software and associated documentation files (the "Software"), to deal
++ * in the Software without restriction, including without limitation the rights
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
++ * copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
++ * THE SOFTWARE.
++ */
++
++#include "qemu/osdep.h"
++#include "qapi/error.h"
++#include "qemu-common.h"
++#include "exec/address-spaces.h"
++#include "sysemu/sysemu.h"
++#include "hw/arm/stm32f405_soc.h"
++#include "hw/misc/unimp.h"
++
++#define SYSCFG_ADD                     0x40013800
++static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
++                                       0x40004C00, 0x40005000, 0x40011400,
++                                       0x40007800, 0x40007C00 };
++/* At the moment only Timer 2 to 5 are modelled */
++static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
++                                       0x40000800, 0x40000C00 };
++#define ADC_ADDR                       0x40012000
++static const uint32_t spi_addr[] =   { 0x40013000, 0x40003800, 0x40003C00,
++                                       0x40013400, 0x40015000, 0x40015400 };
++#define EXTI_ADDR                      0x40013C00
++
++#define SYSCFG_IRQ               71
++static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
++static const int timer_irq[] = { 28, 29, 30, 50 };
++#define ADC_IRQ 18
++static const int spi_irq[] =   { 35, 36, 51, 0, 0, 0 };
++static const int exti_irq[] =  { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
++                                 40, 40, 40, 40, 40} ;
++
++
++static void stm32f405_soc_initfn(Object *obj)
++{
++    STM32F405State *s = STM32F405_SOC(obj);
++    int i;
++
++    sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
++                          TYPE_ARMV7M);
++
++    sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
++                          TYPE_STM32F4XX_SYSCFG);
++
++    for (i = 0; i < STM_NUM_USARTS; i++) {
++        sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
++                              sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
++    }
++
++    for (i = 0; i < STM_NUM_TIMERS; i++) {
++        sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
++                              sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
++    }
++
++    for (i = 0; i < STM_NUM_ADCS; i++) {
++        sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
++                              TYPE_STM32F2XX_ADC);
++    }
++
++    for (i = 0; i < STM_NUM_SPIS; i++) {
++        sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
++                              TYPE_STM32F2XX_SPI);
++    }
++
++    sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
++                          TYPE_STM32F4XX_EXTI);
++}
++
++static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
++{
++    STM32F405State *s = STM32F405_SOC(dev_soc);
++    MemoryRegion *system_memory = get_system_memory();
++    DeviceState *dev, *armv7m;
++    SysBusDevice *busdev;
++    Error *err = NULL;
++    int i;
++
++    memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE,
++                           &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias",
++                             &s->flash, 0, FLASH_SIZE);
++
++    memory_region_set_readonly(&s->flash, true);
++    memory_region_set_readonly(&s->flash_alias, true);
++
++    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
++    memory_region_add_subregion(system_memory, 0, &s->flash_alias);
++
++    memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
++                           &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
++
++    armv7m = DEVICE(&s->armv7m);
++    qdev_prop_set_uint32(armv7m, "num-irq", 96);
++    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
++    qdev_prop_set_bit(armv7m, "enable-bitband", true);
++    object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
++                                     "memory", &error_abort);
++    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++
++    /* System configuration controller */
++    dev = DEVICE(&s->syscfg);
++    object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    busdev = SYS_BUS_DEVICE(dev);
++    sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
++    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
++
++    /* Attach UART (uses USART registers) and USART controllers */
++    for (i = 0; i < STM_NUM_USARTS; i++) {
++        dev = DEVICE(&(s->usart[i]));
++        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
++        object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
++        if (err != NULL) {
++            error_propagate(errp, err);
++            return;
++        }
++        busdev = SYS_BUS_DEVICE(dev);
++        sysbus_mmio_map(busdev, 0, usart_addr[i]);
++        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
++    }
++
++    /* Timer 2 to 5 */
++    for (i = 0; i < STM_NUM_TIMERS; i++) {
++        dev = DEVICE(&(s->timer[i]));
++        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
++        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
++        if (err != NULL) {
++            error_propagate(errp, err);
++            return;
++        }
++        busdev = SYS_BUS_DEVICE(dev);
++        sysbus_mmio_map(busdev, 0, timer_addr[i]);
++        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
++    }
++
++    /* ADC device, the IRQs are ORed together */
++    object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
++                            sizeof(s->adc_irqs), TYPE_OR_IRQ,
++                            &err, NULL);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
++                            "num-lines", &err);
++    object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
++                          qdev_get_gpio_in(armv7m, ADC_IRQ));
++
++    dev = DEVICE(&(s->adc[i]));
++    object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    busdev = SYS_BUS_DEVICE(dev);
++    sysbus_mmio_map(busdev, 0, ADC_ADDR);
++    sysbus_connect_irq(busdev, 0,
++                       qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
++
++    /* SPI devices */
++    for (i = 0; i < STM_NUM_SPIS; i++) {
++        dev = DEVICE(&(s->spi[i]));
++        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
++        if (err != NULL) {
++            error_propagate(errp, err);
++            return;
++        }
++        busdev = SYS_BUS_DEVICE(dev);
++        sysbus_mmio_map(busdev, 0, spi_addr[i]);
++        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
++    }
++
++    /* EXTI device */
++    dev = DEVICE(&s->exti);
++    object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
++    if (err != NULL) {
++        error_propagate(errp, err);
++        return;
++    }
++    busdev = SYS_BUS_DEVICE(dev);
++    sysbus_mmio_map(busdev, 0, EXTI_ADDR);
++    for (i = 0; i < 16; i++) {
++        sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
++    }
++    for (i = 0; i < 16; i++) {
++        qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
++    }
++
++    create_unimplemented_device("timer[7]",    0x40001400, 0x400);
++    create_unimplemented_device("timer[12]",   0x40001800, 0x400);
++    create_unimplemented_device("timer[6]",    0x40001000, 0x400);
++    create_unimplemented_device("timer[13]",   0x40001C00, 0x400);
++    create_unimplemented_device("timer[14]",   0x40002000, 0x400);
++    create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
++    create_unimplemented_device("WWDG",        0x40002C00, 0x400);
++    create_unimplemented_device("IWDG",        0x40003000, 0x400);
++    create_unimplemented_device("I2S2ext",     0x40003000, 0x400);
++    create_unimplemented_device("I2S3ext",     0x40004000, 0x400);
++    create_unimplemented_device("I2C1",        0x40005400, 0x400);
++    create_unimplemented_device("I2C2",        0x40005800, 0x400);
++    create_unimplemented_device("I2C3",        0x40005C00, 0x400);
++    create_unimplemented_device("CAN1",        0x40006400, 0x400);
++    create_unimplemented_device("CAN2",        0x40006800, 0x400);
++    create_unimplemented_device("PWR",         0x40007000, 0x400);
++    create_unimplemented_device("DAC",         0x40007400, 0x400);
++    create_unimplemented_device("timer[1]",    0x40010000, 0x400);
++    create_unimplemented_device("timer[8]",    0x40010400, 0x400);
++    create_unimplemented_device("SDIO",        0x40012C00, 0x400);
++    create_unimplemented_device("timer[9]",    0x40014000, 0x400);
++    create_unimplemented_device("timer[10]",   0x40014400, 0x400);
++    create_unimplemented_device("timer[11]",   0x40014800, 0x400);
++    create_unimplemented_device("GPIOA",       0x40020000, 0x400);
++    create_unimplemented_device("GPIOB",       0x40020400, 0x400);
++    create_unimplemented_device("GPIOC",       0x40020800, 0x400);
++    create_unimplemented_device("GPIOD",       0x40020C00, 0x400);
++    create_unimplemented_device("GPIOE",       0x40021000, 0x400);
++    create_unimplemented_device("GPIOF",       0x40021400, 0x400);
++    create_unimplemented_device("GPIOG",       0x40021800, 0x400);
++    create_unimplemented_device("GPIOH",       0x40021C00, 0x400);
++    create_unimplemented_device("GPIOI",       0x40022000, 0x400);
++    create_unimplemented_device("CRC",         0x40023000, 0x400);
++    create_unimplemented_device("RCC",         0x40023800, 0x400);
++    create_unimplemented_device("Flash Int",   0x40023C00, 0x400);
++    create_unimplemented_device("BKPSRAM",     0x40024000, 0x400);
++    create_unimplemented_device("DMA1",        0x40026000, 0x400);
++    create_unimplemented_device("DMA2",        0x40026400, 0x400);
++    create_unimplemented_device("Ethernet",    0x40028000, 0x1400);
++    create_unimplemented_device("USB OTG HS",  0x40040000, 0x30000);
++    create_unimplemented_device("USB OTG FS",  0x50000000, 0x31000);
++    create_unimplemented_device("DCMI",        0x50050000, 0x400);
++    create_unimplemented_device("RNG",         0x50060800, 0x400);
++}
++
++static Property stm32f405_soc_properties[] = {
++    DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
++    DEFINE_PROP_END_OF_LIST(),
++};
++
++static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
++{
++    DeviceClass *dc = DEVICE_CLASS(klass);
++
++    dc->realize = stm32f405_soc_realize;
++    dc->props = stm32f405_soc_properties;
++    /* No vmstate or reset required: device has no internal state */
++}
++
++static const TypeInfo stm32f405_soc_info = {
++    .name          = TYPE_STM32F405_SOC,
++    .parent        = TYPE_SYS_BUS_DEVICE,
++    .instance_size = sizeof(STM32F405State),
++    .instance_init = stm32f405_soc_initfn,
++    .class_init    = stm32f405_soc_class_init,
++};
++
++static void stm32f405_soc_types(void)
++{
++    type_register_static(&stm32f405_soc_info);
++}
++
++type_init(stm32f405_soc_types)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: hw/adc/*
+ F: hw/ssi/stm32f2xx_spi.c
+ F: include/hw/*/stm32*.h
++STM32F405
++M: Alistair Francis <alistair@alistair23.me>
++M: Peter Maydell <peter.maydell@linaro.org>
++S: Maintained
++F: hw/arm/stm32f405_soc.c
++F: hw/misc/stm32f4xx_syscfg.c
++F: hw/misc/stm32f4xx_exti.c
++
+ Netduino 2
+ M: Alistair Francis <alistair@alistair23.me>
+ M: Peter Maydell <peter.maydell@linaro.org>
+--
+.20.1

-[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
+[PULL 04/15] hw/arm: Add the Netduino Plus 2
-The raspi3 has AArch64 CPUs, which means that our smpboot
+From: Alistair Francis <alistair@alistair23.me>
 code for keeping the secondary CPUs in a pen needs to have
 a version for A64 as well as A32. Without this, the
 secondary CPUs go into an infinite loop of taking undefined
 instruction exceptions.
+Signed-off-by: Alistair Francis <alistair@alistair23.me>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: dad8d8d47f7625913e35e27a1c00f603a6b08f9a.1576658572.git.alistair@alistair23.me
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
+ hw/arm/Makefile.objs   |  1 +
-file changed, 40 insertions(+), 1 deletion(-)
+ hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++
  MAINTAINERS            |  6 +++++
 files changed, 59 insertions(+)
  create mode 100644 hw/arm/netduinoplus2.c
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/hw/arm/Makefile.objs
-+++ b/hw/arm/raspi.c
++++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o
  obj-$(CONFIG_MICROBIT) += microbit.o
  obj-$(CONFIG_MUSICPAL) += musicpal.o
  obj-$(CONFIG_NETDUINO2) += netduino2.o
 +obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o
  obj-$(CONFIG_NSERIES) += nseries.o
  obj-$(CONFIG_SX1) += omap_sx1.o
  obj-$(CONFIG_CHEETAH) += palm.o
 diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/netduinoplus2.c
 @@ -XXX,XX +XXX,XX @@
- #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
++/*
- #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
++ * Netduino Plus 2 Machine Model
- #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
++ *
-+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
++ *
- /* Table of Linux board IDs for different Pi versions */
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
- static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
++ * of this software and associated documentation files (the "Software"), to deal
-@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
++ * in the Software without restriction, including without limitation the rights
-                        info->smp_loader_start);
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- }
++ * copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
-+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
++ *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "hw/boards.h"
 +#include "hw/qdev-properties.h"
 +#include "qemu/error-report.h"
 +#include "hw/arm/stm32f405_soc.h"
 +#include "hw/arm/boot.h"
 +
 +static void netduinoplus2_init(MachineState *machine)
 +{
-+    /* Unlike the AArch32 version we don't need to call the board setup hook.
++    DeviceState *dev;
 +     * The mechanism for doing the spin-table is also entirely different.
 +     * We must have four 64-bit fields at absolute addresses
 +     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
 +     * our CPUs, and which we must ensure are zero initialized before
 +     * the primary CPU goes into the kernel. We put these variables inside
 +     * a rom blob, so that the reset for ROM contents zeroes them for us.
 +     */
 +    static const uint32_t smpboot[] = {
 +        0xd2801b05, /*        mov     x5, 0xd8 */
 +        0xd53800a6, /*        mrs     x6, mpidr_el1 */
 +        0x924004c6, /*        and     x6, x6, #0x3 */
 +        0xd503205f, /* spin:  wfe */
 +        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
 +        0xb4ffffc4, /*        cbz     x4, spin */
 +        0xd2800000, /*        mov     x0, #0x0 */
 +        0xd2800001, /*        mov     x1, #0x0 */
 +        0xd2800002, /*        mov     x2, #0x0 */
 +        0xd2800003, /*        mov     x3, #0x0 */
 +        0xd61f0080, /*        br      x4 */
 +    };
 +
-+    static const uint64_t spintables[] = {
++    dev = qdev_create(NULL, TYPE_STM32F405_SOC);
-+        0, 0, 0, 0
++    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
-+    };
++    object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
 +
-+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
++    armv7m_load_kernel(ARM_CPU(first_cpu),
-+                       info->smp_loader_start);
++                       machine->kernel_filename,
-+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
++                       FLASH_SIZE);
 +                       SPINTABLE_ADDR);
 +}
 +
- static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
++static void netduinoplus2_machine_init(MachineClass *mc)
- {
++{
-     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
++    mc->desc = "Netduino Plus 2 Machine";
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
++    mc->init = netduinoplus2_init;
-     /* Pi2 and Pi3 requires SMP setup */
++}
-     if (version >= 2) {
++
-         binfo.smp_loader_start = SMPBOOT_ADDR;
++DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
--        binfo.write_secondary_boot = write_smpboot;
+diff --git a/MAINTAINERS b/MAINTAINERS
-+        if (version == 2) {
+index XXXXXXX..XXXXXXX 100644
-+            binfo.write_secondary_boot = write_smpboot;
+--- a/MAINTAINERS
-+        } else {
++++ b/MAINTAINERS
-+            binfo.write_secondary_boot = write_smpboot64;
+@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
-+        }
+ S: Maintained
-         binfo.secondary_cpu_reset_hook = reset_secondary;
+ F: hw/arm/netduino2.c
-     }
++Netduino Plus 2
 +M: Alistair Francis <alistair@alistair23.me>
 +M: Peter Maydell <peter.maydell@linaro.org>
 +S: Maintained
 +F: hw/arm/netduinoplus2.c
 +
  SmartFusion2
  M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
  M: Peter Maydell <peter.maydell@linaro.org>
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
+[PULL 05/15] tests/boot_linux_console: Add initrd test for the CubieBoard
-The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
 is required for Linux to boot.
+This test boots a Linux kernel on a CubieBoard and verify
+the serial output is working.
+The kernel image and DeviceTree blob are built by the Armbian
+project (based on Debian):
+https://docs.armbian.com/Developer-Guide_Build-Preparation/
+The cpio image used comes from the linux-build-test project:
+https://github.com/groeck/linux-build-test
+If ARM is a target being built, "make check-acceptance" will
+automatically include this test by the use of the "arch:arm" tags.
+Alternatively, this test can be run using:
+  $ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
+  console: Uncompressing Linux... done, booting the kernel.
+  console: Booting Linux on physical CPU 0x0
+  console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
+  console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=50c5387d
+  console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
+  console: OF: fdt: Machine model: Cubietech Cubieboard
+  [...]
+  console: Boot successful.
+  console: cat /proc/cpuinfo
+  console: / # cat /proc/cpuinfo
+  console: processor      : 0
+  console: model name     : ARMv7 Processor rev 0 (v7l)
+  console: BogoMIPS       : 832.51
+  [...]
+  console: Hardware       : Allwinner sun4i/sun5i Families
+  console: Revision       : 0000
+  console: Serial         : 0000000000000000
+  console: cat /proc/iomem
+  console: / # cat /proc/iomem
+  console: 01c00000-01c0002f : system-control@1c00000
+  console: 01c02000-01c02fff : dma-controller@1c02000
+  console: 01c05000-01c05fff : spi@1c05000
+  console: 01c0b080-01c0b093 : mdio@1c0b080
+  console: 01c0c000-01c0cfff : lcd-controller@1c0c000
+  console: 01c0d000-01c0dfff : lcd-controller@1c0d000
+  console: 01c0f000-01c0ffff : mmc@1c0f000
+  [...]
+  PASS (54.35 s)
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
+Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
+Message-id: 20191230110953.25496-2-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 11 +++++++----
+ tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++
-file changed, 7 insertions(+), 4 deletions(-)
+file changed, 41 insertions(+)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/tests/acceptance/boot_linux_console.py
-+++ b/hw/arm/bcm2836.c
++++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
+         self.wait_for_console_pattern('Boot successful.')
- struct BCM283XInfo {
+         # TODO user command, for now the uart is stuck
-     const char *name;
-+    int clusterid;
++    def test_arm_cubieboard_initrd(self):
- };
++        """
++        :avocado: tags=arch:arm
- static const BCM283XInfo bcm283x_socs[] = {
++        :avocado: tags=machine:cubieboard
-     {
++        """
-         .name = TYPE_BCM2836,
++        deb_url = ('https://apt.armbian.com/pool/main/l/'
-+        .clusterid = 0xf,
++                   'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
-     },
++        deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
-     {
++        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
-         .name = TYPE_BCM2837,
++        kernel_path = self.extract_from_deb(deb_path,
-+        .clusterid = 0x0,
++                                            '/boot/vmlinuz-4.20.7-sunxi')
-     },
++        dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
- };
++        dtb_path = self.extract_from_deb(deb_path, dtb_path)
++        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
++                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
- static void bcm2836_realize(DeviceState *dev, Error **errp)
++                      'arm/rootfs-armv5.cpio.gz')
- {
++        initrd_hash = '2b50f1873e113523967806f4da2afe385462ff9b'
-     BCM283XState *s = BCM283X(dev);
++        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
-+    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
++        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
-+    const BCM283XInfo *info = bc->info;
++        archive.gzip_uncompress(initrd_path_gz, initrd_path)
-     Object *obj;
++
-     Error *err = NULL;
++        self.vm.set_console()
-     int n;
++        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
++                               'console=ttyS0,115200 '
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
++                               'usbcore.nousb '
++                               'panic=-1 noreboot')
-     for (n = 0; n < BCM283X_NCPUS; n++) {
++        self.vm.add_args('-kernel', kernel_path,
--        /* Mirror bcm2836, which has clusterid set to 0xf
++                         '-dtb', dtb_path,
--         * TODO: this should be converted to a property of ARM_CPU
++                         '-initrd', initrd_path,
--         */
++                         '-append', kernel_command_line,
--        s->cpus[n].mp_affinity = 0xF00 | n;
++                         '-no-reboot')
-+        /* TODO: this should be converted to a property of ARM_CPU */
++        self.vm.launch()
-+        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
++        self.wait_for_console_pattern('Boot successful.')
++
-         /* set periphbase/CBAR value for CPU-local registers */
++        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
-         object_property_set_int(OBJECT(&s->cpus[n]),
++                                                'Allwinner sun4i/sun5i')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
 +                                                'system-control@1c00000')
 +        exec_command_and_wait_for_pattern(self, 'reboot',
 +                                                'reboot: Restarting system')
 +
      def test_s390x_s390_ccw_virtio(self):
          """
          :avocado: tags=arch:s390x
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+[PULL 06/15] tests/boot_linux_console: Add a SD card test for the CubieBoard
-If we're directly booting a Linux kernel and the CPU supports both
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 EL3 and EL2, we start the kernel in EL2, as it expects. We must also
 set the SCR_EL3.HCE bit in this situation, so that the HVC
 instruction is enabled rather than UNDEFing. Otherwise at least some
 kernels will panic when trying to initialize KVM in the guest.
+The kernel image and DeviceTree blob are built by the Armbian
+project (based on Debian):
+https://docs.armbian.com/Developer-Guide_Build-Preparation/
+The cpio image used comes from the linux-build-test project:
+https://github.com/groeck/linux-build-test
+If ARM is a target being built, "make check-acceptance" will
+automatically include this test by the use of the "arch:arm" tags.
+Alternatively, this test can be run using:
+  $ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
+  console: Uncompressing Linux... done, booting the kernel.
+  console: Booting Linux on physical CPU 0x0
+  console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
+  [...]
+  console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4
+  console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit
+  console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps 0x1 impl platform mode
+  console: ahci-sunxi 1c18000.sata: flags: ncq only
+  console: scsi host0: ahci-sunxi
+  console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 27
+  console: of_cfs_init
+  console: of_cfs_init: OK
+  console: vcc3v0: disabling
+  console: vcc5v0: disabling
+  console: usb1-vbus: disabling
+  console: usb2-vbus: disabling
+  console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
+  console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100
+  console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32)
+  console: ata1.00: applying bridge limits
+  console: ata1.00: configured for UDMA/100
+  console: scsi 0:0:0:0: Direct-Access     ATA      QEMU HARDDISK    2.5+ PQ: 0 ANSI: 5
+  console: sd 0:0:0:0: Attached scsi generic sg0 type 0
+  console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB)
+  console: sd 0:0:0:0: [sda] Write Protect is off
+  console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
+  console: sd 0:0:0:0: [sda] Attached SCSI disk
+  console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem
+  console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null)
+  console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0.
+  [...]
+  console: cat /proc/partitions
+  console: / # cat /proc/partitions
+  console: major minor  #blocks  name
+  console: 1        0       4096 ram0
+  console: 1        1       4096 ram1
+  console: 1        2       4096 ram2
+  console: 1        3       4096 ram3
+  console: 8        0      20480 sda
+  console: reboot
+  console: / # reboot
+  [...]
+  console: sd 0:0:0:0: [sda] Synchronizing SCSI cache
+  console: reboot: Restarting system
+  PASS (48.39 s)
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20191230110953.25496-3-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 5 +++++
+ tests/acceptance/boot_linux_console.py | 44 ++++++++++++++++++++++++++
-file changed, 5 insertions(+)
+file changed, 44 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/tests/acceptance/boot_linux_console.py
-+++ b/hw/arm/boot.c
++++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
-                     assert(!info->secure_board_setup);
+         exec_command_and_wait_for_pattern(self, 'reboot',
-                 }
+                                                 'reboot: Restarting system')
-+                if (arm_feature(env, ARM_FEATURE_EL2)) {
++    def test_arm_cubieboard_sata(self):
-+                    /* If we have EL2 then Linux expects the HVC insn to work */
++        """
-+                    env->cp15.scr_el3 |= SCR_HCE;
++        :avocado: tags=arch:arm
-+                }
++        :avocado: tags=machine:cubieboard
 +        """
 +        deb_url = ('https://apt.armbian.com/pool/main/l/'
 +                   'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
 +        deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
 +        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
 +        kernel_path = self.extract_from_deb(deb_path,
 +                                            '/boot/vmlinuz-4.20.7-sunxi')
 +        dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
 +        dtb_path = self.extract_from_deb(deb_path, dtb_path)
 +        rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
 +                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
 +                      'arm/rootfs-armv5.ext2.gz')
 +        rootfs_hash = '093e89d2b4d982234bf528bc9fb2f2f17a9d1f93'
 +        rootfs_path_gz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
 +        rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
 +        archive.gzip_uncompress(rootfs_path_gz, rootfs_path)
 +
-                 /* Set to non-secure if not a secure boot */
++        self.vm.set_console()
-                 if (!info->secure_boot &&
++        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-                     (cs != first_cpu || !info->secure_board_setup)) {
++                               'console=ttyS0,115200 '
 +                               'usbcore.nousb '
 +                               'root=/dev/sda ro '
 +                               'panic=-1 noreboot')
 +        self.vm.add_args('-kernel', kernel_path,
 +                         '-dtb', dtb_path,
 +                         '-drive', 'if=none,format=raw,id=disk0,file='
 +                                   + rootfs_path,
 +                         '-device', 'ide-hd,bus=ide.0,drive=disk0',
 +                         '-append', kernel_command_line,
 +                         '-no-reboot')
 +        self.vm.launch()
 +        self.wait_for_console_pattern('Boot successful.')
 +
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
 +                                                'Allwinner sun4i/sun5i')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
 +                                                'sda')
 +        exec_command_and_wait_for_pattern(self, 'reboot',
 +                                                'reboot: Restarting system')
 +
      def test_s390x_s390_ccw_virtio(self):
          """
          :avocado: tags=arch:s390x
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
+[PULL 07/15] hw/arm/allwinner-a10: Move SoC definitions out of header
-The TypeInfo and state struct for bcm2386 disagree about what the
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
 but the BCM2386State struct only defines the parent_obj field
 as DeviceState. This would have caused problems if anything
 actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
 Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
 need any of the additional functionality TYPE_SYS_BUS_DEVICE
 provides.
+These definitions are specific to the A10 SoC and don't need
+to be exported to the different Allwinner peripherals.
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20191230110953.25496-4-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 2 +-
+ include/hw/arm/allwinner-a10.h | 6 ------
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/arm/allwinner-a10.c         | 6 ++++++
 files changed, 6 insertions(+), 6 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/include/hw/arm/allwinner-a10.h
-+++ b/hw/arm/bcm2836.c
++++ b/include/hw/arm/allwinner-a10.h
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@
+ #include "target/arm/cpu.h"
- static const TypeInfo bcm2836_type_info = {
-     .name = TYPE_BCM2836,
--    .parent = TYPE_SYS_BUS_DEVICE,
+-#define AW_A10_PIC_REG_BASE     0x01c20400
-+    .parent = TYPE_DEVICE,
+-#define AW_A10_PIT_REG_BASE     0x01c20c00
-     .instance_size = sizeof(BCM2836State),
+-#define AW_A10_UART0_REG_BASE   0x01c28000
-     .instance_init = bcm2836_init,
+-#define AW_A10_EMAC_BASE        0x01c0b000
-     .class_init = bcm2836_class_init,
+-#define AW_A10_SATA_BASE        0x01c18000
 -
  #define AW_A10_SDRAM_BASE       0x40000000
  #define TYPE_AW_A10 "allwinner-a10"
 diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/allwinner-a10.c
 +++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/unimp.h"
  #include "sysemu/sysemu.h"
 +#define AW_A10_PIC_REG_BASE     0x01c20400
 +#define AW_A10_PIT_REG_BASE     0x01c20c00
 +#define AW_A10_UART0_REG_BASE   0x01c28000
 +#define AW_A10_EMAC_BASE        0x01c0b000
 +#define AW_A10_SATA_BASE        0x01c18000
 +
  static void aw_a10_init(Object *obj)
  {
      AwA10State *s = AW_A10(obj);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+[PULL 08/15] hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
-Our BCM2836 type is really a generic one that can be any of
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 the bcm283x family. Rename it accordingly. We change only
 the names which are visible via the header file to the
 rest of the QEMU code, leaving private function names
 in bcm2836.c as they are.
-This is a preliminary to making bcm283x be an abstract
+By calling qdev_pass_gpios() we don't need to hold a copy of the
-parent class to specific types for the bcm2836 and bcm2837.
+IRQs from the INTC into the SoC state.
 Instead of filling an array of qemu_irq and passing it around, we
 can now directly call qdev_get_gpio_in() on the SoC.
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20191230110953.25496-5-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 12 ++++++------
+ include/hw/arm/allwinner-a10.h |  1 -
- hw/arm/bcm2836.c         | 17 +++++++++--------
+ hw/arm/allwinner-a10.c         | 24 +++++++++++-------------
- hw/arm/raspi.c           | 16 ++++++++--------
+files changed, 11 insertions(+), 14 deletions(-)
 files changed, 23 insertions(+), 22 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/include/hw/arm/allwinner-a10.h
-+++ b/include/hw/arm/bcm2836.h
++++ b/include/hw/arm/allwinner-a10.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
  #include "hw/arm/bcm2835_peripherals.h"
  #include "hw/intc/bcm2836_control.h"
 -#define TYPE_BCM2836 "bcm2836"
 -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
 +#define TYPE_BCM283X "bcm283x"
 +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 -#define BCM2836_NCPUS 4
 +#define BCM283X_NCPUS 4
 -typedef struct BCM2836State {
 +typedef struct BCM283XState {
      /*< private >*/
      DeviceState parent_obj;
      /*< public >*/
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
-     char *cpu_type;
+     ARMCPU cpu;
-     uint32_t enabled_cpus;
+-    qemu_irq irq[AW_A10_PIC_INT_NR];
+     AwA10PITState timer;
--    ARMCPU cpus[BCM2836_NCPUS];
+     AwA10PICState intc;
-+    ARMCPU cpus[BCM283X_NCPUS];
+     AwEmacState emac;
-     BCM2836ControlState control;
+diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
      BCM2835PeripheralState peripherals;
 -} BCM2836State;
 +} BCM283XState;
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/arm/allwinner-a10.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/arm/allwinner-a10.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
  static void bcm2836_init(Object *obj)
  {
--    BCM2836State *s = BCM2836(obj);
+     AwA10State *s = AW_A10(dev);
-+    BCM283XState *s = BCM283X(obj);
+     SysBusDevice *sysbusdev;
+-    uint8_t i;
-     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
+     qemu_irq fiq, irq;
      object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
  static void bcm2836_realize(DeviceState *dev, Error **errp)
  {
 -    BCM2836State *s = BCM2836(dev);
 +    BCM283XState *s = BCM283X(dev);
      Object *obj;
      Error *err = NULL;
-     int n;
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
-     /* common peripherals from bcm2835 */
+     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
+     sysbus_connect_irq(sysbusdev, 0, irq);
-     obj = OBJECT(dev);
+     sysbus_connect_irq(sysbusdev, 1, fiq);
--    for (n = 0; n < BCM2836_NCPUS; n++) {
+-    for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
+-        s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
-         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+-    }
-                           s->cpu_type);
++    qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
-         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
-     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+     if (err != NULL) {
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
+     }
--    for (n = 0; n < BCM2836_NCPUS; n++) {
+     sysbusdev = SYS_BUS_DEVICE(&s->timer);
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
+     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
-         /* Mirror bcm2836, which has clusterid set to 0xf
+-    sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
-          * TODO: this should be converted to a property of ARM_CPU
+-    sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
-          */
+-    sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+-    sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
 -    sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
 -    sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
 +    sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
 +    sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
 +    sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
 +    sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
 +    sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
 +    sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
      memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
                             &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
      }
      sysbusdev = SYS_BUS_DEVICE(&s->emac);
      sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
 -    sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
 +    sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
      object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
      if (err) {
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
          return;
      }
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
 -    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
      /* FIXME use a qdev chardev prop instead of serial_hd() */
 -    serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
 +    serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
 +                   qdev_get_gpio_in(dev, 1),
 , serial_hd(0), DEVICE_NATIVE_ENDIAN);
  }
- static Property bcm2836_props[] = {
--    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
--    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
-+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
-+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
-+                       BCM283X_NCPUS),
-     DEFINE_PROP_END_OF_LIST()
- };
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
- }
- static const TypeInfo bcm2836_type_info = {
--    .name = TYPE_BCM2836,
-+    .name = TYPE_BCM283X,
-     .parent = TYPE_DEVICE,
--    .instance_size = sizeof(BCM2836State),
-+    .instance_size = sizeof(BCM283XState),
-     .instance_init = bcm2836_init,
-     .class_init = bcm2836_class_init,
- };
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
-+++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
- static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
- typedef struct RasPiState {
--    BCM2836State soc;
-+    BCM283XState soc;
-     MemoryRegion ram;
- } RasPiState;
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
-     BusState *bus;
-     DeviceState *carddev;
--    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
-+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
-     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
-                               &error_abort);
-@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
-     mc->no_floppy = 1;
-     mc->no_cdrom = 1;
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
--    mc->max_cpus = BCM2836_NCPUS;
--    mc->min_cpus = BCM2836_NCPUS;
--    mc->default_cpus = BCM2836_NCPUS;
-+    mc->max_cpus = BCM283X_NCPUS;
-+    mc->min_cpus = BCM283X_NCPUS;
-+    mc->default_cpus = BCM283X_NCPUS;
-     mc->default_ram_size = 1024 * 1024 * 1024;
-     mc->ignore_memory_transaction_failures = true;
- };
-@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
-     mc->no_floppy = 1;
-     mc->no_cdrom = 1;
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
--    mc->max_cpus = BCM2836_NCPUS;
--    mc->min_cpus = BCM2836_NCPUS;
--    mc->default_cpus = BCM2836_NCPUS;
-+    mc->max_cpus = BCM283X_NCPUS;
-+    mc->min_cpus = BCM283X_NCPUS;
-+    mc->default_cpus = BCM283X_NCPUS;
-     mc->default_ram_size = 1024 * 1024 * 1024;
- }
- DEFINE_MACHINE("raspi3", raspi3_machine_init)
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+[PULL 09/15] hw/arm/allwinner-a10: Remove local qemu_irq variables
-Add some assertions that if we're about to boot an AArch64 kernel,
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 the board code has not mistakenly set either secure_boot or
 secure_board_setup. It doesn't make sense to set secure_boot,
 because all AArch64 kernels must be booted in non-secure mode.
-It might in theory make sense to set secure_board_setup, but
+We won't reuse the CPU IRQ/FIQ variables. Simplify by calling
-we don't currently support that, because only the AArch32
+qdev_get_gpio_in() in place.
 bootloader[] code calls this hook; bootloader_aarch64[] does not.
 Since we don't have a current need for this functionality, just
 assert that we don't try to use it. If it's needed we'll add
 it later.
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20191230110953.25496-6-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 7 +++++++
+ hw/arm/allwinner-a10.c | 9 ++++-----
-file changed, 7 insertions(+)
+file changed, 4 insertions(+), 5 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/arm/allwinner-a10.c
-+++ b/hw/arm/boot.c
++++ b/hw/arm/allwinner-a10.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
-                     } else {
+ {
-                         env->pstate = PSTATE_MODE_EL1h;
+     AwA10State *s = AW_A10(dev);
-                     }
+     SysBusDevice *sysbusdev;
-+                    /* AArch64 kernels never boot in secure mode */
+-    qemu_irq fiq, irq;
-+                    assert(!info->secure_boot);
+     Error *err = NULL;
-+                    /* This hook is only supported for AArch32 currently:
-+                     * bootloader_aarch64[] will not call the hook, and
+     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
-+                     * the code above has already dropped us into EL2 or EL1.
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
-+                     */
+         error_propagate(errp, err);
-+                    assert(!info->secure_board_setup);
+         return;
-                 }
+     }
+-    irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
-                 /* Set to non-secure if not a secure boot */
+-    fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
      object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
      if (err != NULL) {
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
      }
      sysbusdev = SYS_BUS_DEVICE(&s->intc);
      sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
 -    sysbus_connect_irq(sysbusdev, 0, irq);
 -    sysbus_connect_irq(sysbusdev, 1, fiq);
 +    sysbus_connect_irq(sysbusdev, 0,
 +                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 +    sysbus_connect_irq(sysbusdev, 1,
 +                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
      qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
      object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+[PULL 10/15] target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
-For the rpi1 and 2 we want to boot the Linux kernel via some
+From: Masahiro Yamada <masahiroy@kernel.org>
 custom setup code that makes sure that the SMC instruction
 acts as a no-op, because it's used for cache maintenance.
 The rpi3 boots AArch64 kernels, which don't need SMC for
 cache maintenance and always expect to be booted non-secure.
 Don't fill in the aarch32-specific parts of the binfo struct.
+According to the specification "Semihosting for AArch32 and Aarch64",
+the SYS_OPEN operation should return:
+ - A nonzero handle if the call is successful
+ - -1 if the call is not successful
+So, it should never return 0.
+Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting
+code hand out its own file descriptors"), the guest fd matched to the
+host fd. It returned a nonzero handle on success since the fd 0 is
+already used for stdin.
+Now that the guest fd is the index of guestfd_array, it starts from 0.
+I noticed this issue particularly because Trusted Firmware-A built with
+PLAT=qemu is no longer working. Its io_semihosting driver only handles
+a positive return value as a valid filehandle.
+Basically, there are two ways to fix this:
+  - Use (guestfd - 1) as the index of guestfs_arrary. We need to insert
+    increment/decrement to convert the guestfd and the array index back
+    and forth.
+  - Keep using guestfd as the index of guestfs_array. The first entry
+    of guestfs_array is left unused.
+I thought the latter is simpler. We end up with wasting a small piece
+of memory for the unused first entry of guestfd_array, but this is
+probably not a big deal.
+Fixes: 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting code hand out its own file descriptors")
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20200109041228.10131-1-masahiroy@kernel.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 17 +++++++++++++----
+ target/arm/arm-semi.c | 5 +++--
-file changed, 13 insertions(+), 4 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/arm-semi.c
-+++ b/hw/arm/raspi.c
++++ b/target/arm/arm-semi.c
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ static int alloc_guestfd(void)
-     binfo.board_id = raspi_boardid[version];
+         guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD));
-     binfo.ram_size = ram_size;
+     }
-     binfo.nb_cpus = smp_cpus;
--    binfo.board_setup_addr = BOARDSETUP_ADDR;
+-    for (i = 0; i < guestfd_array->len; i++) {
--    binfo.write_board_setup = write_board_setup;
++    /* SYS_OPEN should return nonzero handle on success. Start guestfd from 1 */
--    binfo.secure_board_setup = true;
++    for (i = 1; i < guestfd_array->len; i++) {
--    binfo.secure_boot = true;
+         GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i);
-+
-+    if (version <= 2) {
+         if (gf->type == GuestFDUnused) {
-+        /* The rpi1 and 2 require some custom setup code to run in Secure
+@@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd)
-+         * mode before booting a kernel (to set up the SMC vectors so
+         return NULL;
-+         * that we get a no-op SMC; this is used by Linux to call the
+     }
-+         * firmware for some cache maintenance operations.
-+         * The rpi3 doesn't need this.
+-    if (guestfd < 0 || guestfd >= guestfd_array->len) {
-+         */
++    if (guestfd <= 0 || guestfd >= guestfd_array->len) {
-+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+         return NULL;
-+        binfo.write_board_setup = write_board_setup;
+     }
-+        binfo.secure_board_setup = true;
 +        binfo.secure_boot = true;
 +    }
      /* Pi2 and Pi3 requires SMP setup */
      if (version >= 2) {
 --
-.16.2
+.20.1

-New patch
+[PULL 11/15] i.MX: add an emulation for RNGC
+From: Martin Kaiser <martin@kaiser.cx>
 Add an emulation for the RNGC random number generator and the compatible
 RNGB variant. These peripherals are included (at least) in imx25 and
 imx35 chipsets.
 The emulation supports the initial self test, reseeding the prng and
 reading random numbers.
 Signed-off-by: Martin Kaiser <martin@kaiser.cx>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/misc/Makefile.objs      |   1 +
  include/hw/arm/fsl-imx25.h |   5 +
  include/hw/misc/imx_rngc.h |  35 +++++
  hw/arm/fsl-imx25.c         |  11 ++
  hw/misc/imx_rngc.c         | 278 +++++++++++++++++++++++++++++++++++++
 files changed, 330 insertions(+)
  create mode 100644 include/hw/misc/imx_rngc.h
  create mode 100644 hw/misc/imx_rngc.c
 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Makefile.objs
 +++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o
  common-obj-$(CONFIG_IMX) += imx2_wdt.o
  common-obj-$(CONFIG_IMX) += imx7_snvs.o
  common-obj-$(CONFIG_IMX) += imx7_gpr.o
 +common-obj-$(CONFIG_IMX) += imx_rngc.o
  common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
  common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
  common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o
 diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx25.h
 +++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/timer/imx_gpt.h"
  #include "hw/timer/imx_epit.h"
  #include "hw/net/imx_fec.h"
 +#include "hw/misc/imx_rngc.h"
  #include "hw/i2c/imx_i2c.h"
  #include "hw/gpio/imx_gpio.h"
  #include "exec/memory.h"
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
      IMXGPTState    gpt[FSL_IMX25_NUM_GPTS];
      IMXEPITState   epit[FSL_IMX25_NUM_EPITS];
      IMXFECState    fec;
 +    IMXRNGCState   rngc;
      IMXI2CState    i2c[FSL_IMX25_NUM_I2CS];
      IMXGPIOState   gpio[FSL_IMX25_NUM_GPIOS];
      MemoryRegion   rom[2];
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
  #define FSL_IMX25_GPIO4_SIZE    0x4000
  #define FSL_IMX25_GPIO3_ADDR    0x53FA4000
  #define FSL_IMX25_GPIO3_SIZE    0x4000
 +#define FSL_IMX25_RNGC_ADDR     0x53FB0000
 +#define FSL_IMX25_RNGC_SIZE     0x4000
  #define FSL_IMX25_GPIO1_ADDR    0x53FCC000
  #define FSL_IMX25_GPIO1_SIZE    0x4000
  #define FSL_IMX25_GPIO2_ADDR    0x53FD0000
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
  #define FSL_IMX25_EPIT1_IRQ     28
  #define FSL_IMX25_EPIT2_IRQ     27
  #define FSL_IMX25_FEC_IRQ       57
 +#define FSL_IMX25_RNGC_IRQ      22
  #define FSL_IMX25_I2C1_IRQ      3
  #define FSL_IMX25_I2C2_IRQ      4
  #define FSL_IMX25_I2C3_IRQ      10
 diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/imx_rngc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Freescale i.MX RNGC emulation
 + *
 + * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#ifndef IMX_RNGC_H
 +#define IMX_RNGC_H
 +
 +#include "hw/sysbus.h"
 +
 +#define TYPE_IMX_RNGC "imx.rngc"
 +#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC)
 +
 +typedef struct IMXRNGCState {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +
 +    /*< public >*/
 +    MemoryRegion  iomem;
 +
 +    uint8_t op_self_test;
 +    uint8_t op_seed;
 +    uint8_t mask;
 +    bool    auto_seed;
 +
 +    QEMUBH *self_test_bh;
 +    QEMUBH *seed_bh;
 +    qemu_irq irq;
 +} IMXRNGCState;
 +
 +#endif /* IMX_RNGC_H */
 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx25.c
 +++ b/hw/arm/fsl-imx25.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
      sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
 +    sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
 +                          TYPE_IMX_RNGC);
 +
      for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
          sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
                                TYPE_IMX_I2C);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                         qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
 +    object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
      /* Initialize all I2C */
      for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
 diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/imx_rngc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Freescale i.MX RNGC emulation
 + *
 + * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + * This driver provides the minimum functionality to initialize and seed
 + * an rngc and to read random numbers. The rngb that is found in imx25
 + * chipsets is also supported.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/main-loop.h"
 +#include "qemu/module.h"
 +#include "qemu/log.h"
 +#include "qemu/guest-random.h"
 +#include "hw/irq.h"
 +#include "hw/misc/imx_rngc.h"
 +#include "migration/vmstate.h"
 +
 +#define RNGC_NAME "i.MX RNGC"
 +
 +#define RNGC_VER_ID  0x00
 +#define RNGC_COMMAND 0x04
 +#define RNGC_CONTROL 0x08
 +#define RNGC_STATUS  0x0C
 +#define RNGC_FIFO    0x14
 +
 +/* These version info are reported by the rngb in an imx258 chip. */
 +#define RNG_TYPE_RNGB 0x1
 +#define V_MAJ 0x2
 +#define V_MIN 0x40
 +
 +#define RNGC_CMD_BIT_SW_RST    0x40
 +#define RNGC_CMD_BIT_CLR_ERR   0x20
 +#define RNGC_CMD_BIT_CLR_INT   0x10
 +#define RNGC_CMD_BIT_SEED      0x02
 +#define RNGC_CMD_BIT_SELF_TEST 0x01
 +
 +#define RNGC_CTRL_BIT_MASK_ERR  0x40
 +#define RNGC_CTRL_BIT_MASK_DONE 0x20
 +#define RNGC_CTRL_BIT_AUTO_SEED 0x10
 +
 +/* the current status for self-test and seed operations */
 +#define OP_IDLE 0
 +#define OP_RUN  1
 +#define OP_DONE 2
 +
 +static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    IMXRNGCState *s = IMX_RNGC(opaque);
 +    uint64_t val = 0;
 +
 +    switch (offset) {
 +    case RNGC_VER_ID:
 +        val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN;
 +        break;
 +
 +    case RNGC_COMMAND:
 +        if (s->op_seed == OP_RUN) {
 +            val |= RNGC_CMD_BIT_SEED;
 +        }
 +        if (s->op_self_test == OP_RUN) {
 +            val |= RNGC_CMD_BIT_SELF_TEST;
 +        }
 +        break;
 +
 +    case RNGC_CONTROL:
 +        /*
 +         * The CTL_ACC and VERIF_MODE bits are not supported yet.
 +         * They read as 0.
 +         */
 +        val |= s->mask;
 +        if (s->auto_seed) {
 +            val |= RNGC_CTRL_BIT_AUTO_SEED;
 +        }
 +        /*
 +         * We don't have an internal fifo like the real hardware.
 +         * There's no need for strategy to handle fifo underflows.
 +         * We return the FIFO_UFLOW_RESPONSE bits as 0.
 +         */
 +        break;
 +
 +    case RNGC_STATUS:
 +        /*
 +         * We never report any statistics test or self-test errors or any
 +         * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0.
 +         */
 +
 +        /*
 +         * We don't have an internal fifo, see above. Therefore, we
 +         * report back the default fifo size (5 32-bit words) and
 +         * indicate that our fifo is always full.
 +         */
 +        val |= 5 << 12 | 5 << 8;
 +
 +        /* We always have a new seed available. */
 +        val |= 1 << 6;
 +
 +        if (s->op_seed == OP_DONE) {
 +            val |= 1 << 5;
 +        }
 +        if (s->op_self_test == OP_DONE) {
 +            val |= 1 << 4;
 +        }
 +        if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) {
 +            /*
 +             * We're busy if self-test is running or if we're
 +             * seeding the prng.
 +             */
 +            val |= 1 << 1;
 +        } else {
 +            /*
 +             * We're ready to provide secure random numbers whenever
 +             * we're not busy.
 +             */
 +            val |= 1;
 +        }
 +        break;
 +
 +    case RNGC_FIFO:
 +        qemu_guest_getrandom_nofail(&val, sizeof(val));
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void imx_rngc_do_reset(IMXRNGCState *s)
 +{
 +    s->op_self_test = OP_IDLE;
 +    s->op_seed = OP_IDLE;
 +    s->mask = 0;
 +    s->auto_seed = false;
 +}
 +
 +static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value,
 +                           unsigned size)
 +{
 +    IMXRNGCState *s = IMX_RNGC(opaque);
 +
 +    switch (offset) {
 +    case RNGC_COMMAND:
 +        if (value & RNGC_CMD_BIT_SW_RST) {
 +            imx_rngc_do_reset(s);
 +        }
 +
 +        /*
 +         * For now, both CLR_ERR and CLR_INT clear the interrupt. We
 +         * don't report any errors yet.
 +         */
 +        if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) {
 +            qemu_irq_lower(s->irq);
 +        }
 +
 +        if (value & RNGC_CMD_BIT_SEED) {
 +            s->op_seed = OP_RUN;
 +            qemu_bh_schedule(s->seed_bh);
 +        }
 +
 +        if (value & RNGC_CMD_BIT_SELF_TEST) {
 +            s->op_self_test = OP_RUN;
 +            qemu_bh_schedule(s->self_test_bh);
 +        }
 +        break;
 +
 +    case RNGC_CONTROL:
 +        /*
 +         * The CTL_ACC and VERIF_MODE bits are not supported yet.
 +         * We ignore them if they're set by the caller.
 +         */
 +
 +        if (value & RNGC_CTRL_BIT_MASK_ERR) {
 +            s->mask |= RNGC_CTRL_BIT_MASK_ERR;
 +        } else {
 +            s->mask &= ~RNGC_CTRL_BIT_MASK_ERR;
 +        }
 +
 +        if (value & RNGC_CTRL_BIT_MASK_DONE) {
 +            s->mask |= RNGC_CTRL_BIT_MASK_DONE;
 +        } else {
 +            s->mask &= ~RNGC_CTRL_BIT_MASK_DONE;
 +        }
 +
 +        if (value & RNGC_CTRL_BIT_AUTO_SEED) {
 +            s->auto_seed = true;
 +        } else {
 +            s->auto_seed = false;
 +        }
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps imx_rngc_ops = {
 +    .read  = imx_rngc_read,
 +    .write = imx_rngc_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +};
 +
 +static void imx_rngc_self_test(void *opaque)
 +{
 +    IMXRNGCState *s = IMX_RNGC(opaque);
 +
 +    s->op_self_test = OP_DONE;
 +    if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
 +        qemu_irq_raise(s->irq);
 +    }
 +}
 +
 +static void imx_rngc_seed(void *opaque)
 +{
 +    IMXRNGCState *s = IMX_RNGC(opaque);
 +
 +    s->op_seed = OP_DONE;
 +    if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
 +        qemu_irq_raise(s->irq);
 +    }
 +}
 +
 +static void imx_rngc_realize(DeviceState *dev, Error **errp)
 +{
 +    IMXRNGCState *s = IMX_RNGC(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s,
 +                          TYPE_IMX_RNGC, 0x1000);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +    s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s);
 +    s->seed_bh = qemu_bh_new(imx_rngc_seed, s);
 +}
 +
 +static void imx_rngc_reset(DeviceState *dev)
 +{
 +    IMXRNGCState *s = IMX_RNGC(dev);
 +
 +    imx_rngc_do_reset(s);
 +}
 +
 +static const VMStateDescription vmstate_imx_rngc = {
 +    .name = RNGC_NAME,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT8(op_self_test, IMXRNGCState),
 +        VMSTATE_UINT8(op_seed, IMXRNGCState),
 +        VMSTATE_UINT8(mask, IMXRNGCState),
 +        VMSTATE_BOOL(auto_seed, IMXRNGCState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void imx_rngc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = imx_rngc_realize;
 +    dc->reset = imx_rngc_reset;
 +    dc->desc = RNGC_NAME,
 +    dc->vmsd = &vmstate_imx_rngc;
 +}
 +
 +static const TypeInfo imx_rngc_info = {
 +    .name          = TYPE_IMX_RNGC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMXRNGCState),
 +    .class_init    = imx_rngc_class_init,
 +};
 +
 +static void imx_rngc_register_types(void)
 +{
 +    type_register_static(&imx_rngc_info);
 +}
 +
 +type_init(imx_rngc_register_types)
 --
 .20.1

-[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
+[PULL 12/15] target/arm: adjust program counter for wfi exception in AArch32
-From: Wei Huang <wei@redhat.com>
+From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
-For guest kernel that supports KASLR, the load address can change every
+The wfi instruction can be configured to be trapped by a higher exception
-time when guest VM runs. To find the physical base address correctly,
+level, such as the EL2 hypervisor. When the instruction is trapped, the
-current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
+program counter should contain the address of the wfi instruction that
-However this string pattern is only available on x86_64. AArch64 uses a
+caused the exception. The program counter is adjusted for this in the wfi op
-different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
+helper function.
 QEMU dump uses the correct string on AArch64.
-Signed-off-by: Wei Huang <wei@redhat.com>
+However, this correction is done to env->pc, which only applies to AArch64
-Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
+mode. For AArch32, the program counter is stored in env->regs[15]. This
-Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
+adds an if-else statement to modify the correct program counter location
 based on the the current CPU mode.
 Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- dump.c | 14 +++++++++++---
+ target/arm/op_helper.c | 7 ++++++-
-file changed, 11 insertions(+), 3 deletions(-)
+file changed, 6 insertions(+), 1 deletion(-)
-diff --git a/dump.c b/dump.c
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/dump.c
+--- a/target/arm/op_helper.c
-+++ b/dump.c
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
+@@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
+     }
-     lines = g_strsplit((char *)vmci, "\n", -1);
-     for (i = 0; lines[i]; i++) {
+     if (target_el) {
--        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
+-        env->pc -= insn_len;
--            if (qemu_strtou64(lines[i] + 18, NULL, 16,
++        if (env->aarch64) {
-+        const char *prefix = NULL;
++            env->pc -= insn_len;
-+
++        } else {
-+        if (s->dump_info.d_machine == EM_X86_64) {
++            env->regs[15] -= insn_len;
 +            prefix = "NUMBER(phys_base)=";
 +        } else if (s->dump_info.d_machine == EM_AARCH64) {
 +            prefix = "NUMBER(PHYS_OFFSET)=";
 +        }
 +
-+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+         raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
-+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
+                         target_el);
-                               &phys_base) < 0) {
+     }
 -                warn_report("Failed to read NUMBER(phys_base)=");
 +                warn_report("Failed to read %s", prefix);
              } else {
                  s->dump_info.phys_base = phys_base;
              }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
+[PULL 13/15] arm/gicv3: update virtual irq state after IAR register read
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
-Code of imx_update() is slightly confusing since the "flags" variable
+The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
-doesn't really corespond to anything in real hardware and server as a
+register activates the highest priority pending interrupt and provides its
-kitchensink accumulating events normally reported via USR1 and USR2
+interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
-registers.
+state - this change makes sure the virtual irq state is updated.
-Change the code to explicitly evaluate state of interrupts reported
+Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
-via USR1 and USR2 against corresponding masking bits and use the to
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-detemine if IRQ line should be asserted or not.
+Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
 NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
 reasons:
 . Emulation code implements a single character FIFO, so this flag
        will always be set since characters are trasmitted as a part of
        the code emulating "push" into the FIFO
 . imx_update() is really just a function doing ORing and maksing
        of reported events, so checking for UTS1_TXEMPTY should happen,
        if it's ever really needed should probably happen outside of
        it.
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/imx_serial.c | 24 ++++++++++++++++--------
+ hw/intc/arm_gicv3_cpuif.c | 3 +++
-file changed, 16 insertions(+), 8 deletions(-)
+file changed, 3 insertions(+)
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/char/imx_serial.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
- static void imx_update(IMXSerialState *s)
+     trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
- {
+                              gicv3_redist_affid(cs), intid);
--    uint32_t flags;
++
-+    uint32_t usr1;
++    gicv3_cpuif_virt_update(cs);
-+    uint32_t usr2;
++
-+    uint32_t mask;
+     return intid;
 -    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
 -    if (s->ucr1 & UCR1_TXMPTYEN) {
 -        flags |= (s->uts1 & UTS1_TXEMPTY);
 -    } else {
 -        flags &= ~USR1_TRDY;
 -    }
 +    /*
 +     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
 +     * UCR1, so we can get away with something as simple as the
 +     * following:
 +     */
 +    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
 +    /*
 +     * Bits that we want in USR2 are not as conveniently laid out,
 +     * unfortunately.
 +     */
 +    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    usr2 = s->usr2 & mask;
 -    qemu_set_irq(s->irq, !!flags);
 +    qemu_set_irq(s->irq, usr1 || usr2);
  }
- static void imx_serial_reset(IMXSerialState *s)
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
+[PULL 14/15] target/arm: Return correct IL bit in merge_syn_data_abort
-From: Guenter Roeck <linux@roeck-us.net>
+From: Jeff Kubascik <jeff.kubascik@dornerworks.com>
-The sabrelite machine model used by qemu-system-arm is based on the
+The IL bit is set for 32-bit instructions, thus passing false
-Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
+with the is_16bit parameter to syn_data_abort_with_iss() makes
-controller which is supported in QEMU using the imx_fec.c module
+a syn mask that always has the IL bit set.
 (actually called imx.enet for this model.)
-The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
+Pass is_16bit as true to make the initial syn mask have IL=0,
-imx.enet device like this:
+so that the final IL value comes from or'ing template_syn.
- #define FSL_IMX6_ENET_MAC_1588_IRQ 118
+Cc: qemu-stable@nongnu.org
- #define FSL_IMX6_ENET_MAC_IRQ 119
+Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts")
+Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
-According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
+Message-id: 20200117004618.2742-2-richard.henderson@linaro.org
-interrupts are as follows.
+[rth: Extracted this as a self-contained bug fix from a larger patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ENET MAC 0 IRQ
 ENET MAC 0 1588 Timer interrupt
 where
 - 32 == 118
 - 32 == 119
 In other words, the vector definitions in the fsl-imx6.h file are reversed.
 Fixing the interrupts alone causes problems with older Linux kernels:
 The Ethernet interface will fail to probe with Linux v4.9 and earlier.
 Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
 error handling. This is a Linux kernel problem, not a qemu problem:
 the Linux kernel only worked by accident since it requested both interrupts.
 For backward compatibility, generate the Ethernet interrupt on both interrupt
 lines. This was shown to work from all Linux kernel releases starting with
 v3.16.
 Link: https://bugs.launchpad.net/qemu/+bug/1753309
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6.h |  4 ++--
+ target/arm/tlb_helper.c | 2 +-
- hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 29 insertions(+), 3 deletions(-)
-diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
+--- a/target/arm/tlb_helper.c
-+++ b/include/hw/arm/fsl-imx6.h
++++ b/target/arm/tlb_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
- #define FSL_IMX6_HDMI_MASTER_IRQ 115
+         syn = syn_data_abort_with_iss(same_el,
- #define FSL_IMX6_HDMI_CEC_IRQ 116
+, 0, 0, 0, 0,
- #define FSL_IMX6_MLB150_LOW_IRQ 117
+                                       ea, 0, s1ptw, is_write, fsc,
--#define FSL_IMX6_ENET_MAC_1588_IRQ 118
+-                                      false);
--#define FSL_IMX6_ENET_MAC_IRQ 119
++                                      true);
-+#define FSL_IMX6_ENET_MAC_IRQ 118
+         /* Merge the runtime syndrome with the template syndrome.  */
-+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
+         syn |= template_syn;
- #define FSL_IMX6_PCIE1_IRQ 120
+     }
  #define FSL_IMX6_PCIE2_IRQ 121
  #define FSL_IMX6_PCIE3_IRQ 122
 diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/imx_fec.c
 +++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
  static void imx_eth_update(IMXFECState *s)
  {
 -    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
 +    /*
 +     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
 +     * interrupts swapped. This worked with older versions of Linux (4.14
 +     * and older) since Linux associated both interrupt lines with Ethernet
 +     * MAC interrupts. Specifically,
 +     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
 +     *   timer interrupts. Those versions of Linux fail with versions of QEMU
 +     *   with swapped interrupt assignments.
 +     * - In linux 4.14, both interrupt lines were registered with the Ethernet
 +     *   MAC interrupt handler. As a result, all versions of qemu happen to
 +     *   work, though that is accidental.
 +     * - In Linux 4.9 and older, the timer interrupt was registered directly
 +     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
 +     *   redirected to a GPIO interrupt to work around erratum ERR006687.
 +     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
 +     *   interrupt never fired since IOMUX is currently not supported in qemu.
 +     *   Linux instead received MAC interrupts on the timer interrupt.
 +     *   As a result, qemu versions with the swapped interrupt assignment work,
 +     *   albeit accidentally, but qemu versions with the correct interrupt
 +     *   assignment fail.
 +     *
 +     * To ensure that all versions of Linux work, generate ENET_INT_MAC
 +     * interrrupts on both interrupt lines. This should be changed if and when
 +     * qemu supports IOMUX.
 +     */
 +    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
 +        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
          qemu_set_irq(s->irq[1], 1);
      } else {
          qemu_set_irq(s->irq[1], 0);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
+[PULL 15/15] target/arm: Set ISSIs16Bit in make_issinfo
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Add support for "TX complete"/TXDC interrupt generate by real HW since
+During the conversion to decodetree, the setting of
-it is needed to support guests other than Linux.
+ISSIs16Bit got lost.  This causes the guest os to
 incorrectly adjust trapping memory operations.
-Based on the patch by Bill Paul as found here:
+Cc: qemu-stable@nongnu.org
-https://bugs.launchpad.net/qemu/+bug/1753314
+Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
+Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
-Cc: qemu-devel@nongnu.org
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Cc: qemu-arm@nongnu.org
+Message-id: 20200117004618.2742-3-richard.henderson@linaro.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Bill Paul <wpaul@windriver.com>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/char/imx_serial.h |  3 +++
+ target/arm/translate.c | 3 +++
- hw/char/imx_serial.c         | 20 +++++++++++++++++---
+file changed, 3 insertions(+)
 files changed, 20 insertions(+), 3 deletions(-)
-diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/imx_serial.h
+--- a/target/arm/translate.c
-+++ b/include/hw/char/imx_serial.h
++++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
- #define UCR2_RXEN       (1<<1)    /* Receiver enable */
+     /* ISS not valid if writeback */
- #define UCR2_SRST       (1<<0)    /* Reset complete */
+     if (p && !w) {
+         ret = rd;
-+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
++        if (s->base.pc_next - s->pc_curr == 2) {
-+
++            ret |= ISSIs16Bit;
- #define UTS1_TXEMPTY    (1<<6)
++        }
- #define UTS1_RXEMPTY    (1<<5)
+     } else {
- #define UTS1_TXFULL     (1<<4)
+         ret = ISSInvalid;
-@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
+     }
      uint32_t ubmr;
      uint32_t ubrc;
      uint32_t ucr3;
 +    uint32_t ucr4;
      qemu_irq irq;
      CharBackend chr;
 diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/imx_serial.c
 +++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
  static const VMStateDescription vmstate_imx_serial = {
      .name = TYPE_IMX_SERIAL,
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_INT32(readbuff, IMXSerialState),
          VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
          VMSTATE_UINT32(ubmr, IMXSerialState),
          VMSTATE_UINT32(ubrc, IMXSerialState),
          VMSTATE_UINT32(ucr3, IMXSerialState),
 +        VMSTATE_UINT32(ucr4, IMXSerialState),
          VMSTATE_END_OF_LIST()
      },
  };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
       * unfortunately.
       */
      mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    /*
 +     * TCEN and TXDC are both bit 3
 +     */
 +    mask |= s->ucr4 & UCR4_TCEN;
 +
      usr2 = s->usr2 & mask;
      qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
          return s->ucr3;
      case 0x23: /* UCR4 */
 +        return s->ucr4;
 +
      case 0x29: /* BRM Incremental */
          return 0x0; /* TODO */
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
               * qemu_chr_fe_write and background I/O callbacks */
              qemu_chr_fe_write_all(&s->chr, &ch, 1);
              s->usr1 &= ~USR1_TRDY;
 +            s->usr2 &= ~USR2_TXDC;
              imx_update(s);
              s->usr1 |= USR1_TRDY;
 +            s->usr2 |= USR2_TXDC;
              imx_update(s);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
          s->ucr3 = value & 0xffff;
          break;
 -    case 0x2d: /* UTS1 */
      case 0x23: /* UCR4 */
 +        s->ucr4 = value & 0xffff;
 +        imx_update(s);
 +        break;
 +
 +    case 0x2d: /* UTS1 */
          qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                        HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
          /* TODO */
 --
-.16.2
+.20.1

Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3

----------------------------------------------------------------
Andrey Smirnov (2):
      char: i.MX: Simplify imx_update()
      char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
      fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
      hw/arm/bcm2386: Fix parent type of bcm2386
      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
      hw/arm/bcm2836: Create proper bcm2837 device
      hw/arm/bcm2836: Use correct affinity values for BCM2837
      hw/arm/bcm2836: Hardcode correct CPU type
      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
      dump: Update correct kdump phys_base field for AArch64

From: Guenter Roeck <linux@roeck-us.net>

The sabrelite machine model used by qemu-system-arm is based on the
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
controller which is supported in QEMU using the imx_fec.c module
(actually called imx.enet for this model.)

The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
imx.enet device like this:

#define FSL_IMX6_ENET_MAC_1588_IRQ 118
 #define FSL_IMX6_ENET_MAC_IRQ 119

According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
interrupts are as follows.

150 ENET MAC 0 IRQ
151 ENET MAC 0 1588 Timer interrupt

where

150 - 32 == 118
151 - 32 == 119

In other words, the vector definitions in the fsl-imx6.h file are reversed.

Fixing the interrupts alone causes problems with older Linux kernels:
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
error handling. This is a Linux kernel problem, not a qemu problem:
the Linux kernel only worked by accident since it requested both interrupts.

For backward compatibility, generate the Ethernet interrupt on both interrupt
lines. This was shown to work from all Linux kernel releases starting with
v3.16.

Link: https://bugs.launchpad.net/qemu/+bug/1753309
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  4 ++--
 hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
 #define FSL_IMX6_HDMI_MASTER_IRQ 115
 #define FSL_IMX6_HDMI_CEC_IRQ 116
 #define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
-#define FSL_IMX6_ENET_MAC_IRQ 119
+#define FSL_IMX6_ENET_MAC_IRQ 118
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
 #define FSL_IMX6_PCIE1_IRQ 120
 #define FSL_IMX6_PCIE2_IRQ 121
 #define FSL_IMX6_PCIE3_IRQ 122
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
 
 static void imx_eth_update(IMXFECState *s)
 {
-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+    /*
+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+     * interrupts swapped. This worked with older versions of Linux (4.14
+     * and older) since Linux associated both interrupt lines with Ethernet
+     * MAC interrupts. Specifically,
+     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
+     *   timer interrupts. Those versions of Linux fail with versions of QEMU
+     *   with swapped interrupt assignments.
+     * - In linux 4.14, both interrupt lines were registered with the Ethernet
+     *   MAC interrupt handler. As a result, all versions of qemu happen to
+     *   work, though that is accidental.
+     * - In Linux 4.9 and older, the timer interrupt was registered directly
+     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
+     *   redirected to a GPIO interrupt to work around erratum ERR006687.
+     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
+     *   interrupt never fired since IOMUX is currently not supported in qemu.
+     *   Linux instead received MAC interrupts on the timer interrupt.
+     *   As a result, qemu versions with the swapped interrupt assignment work,
+     *   albeit accidentally, but qemu versions with the correct interrupt
+     *   assignment fail.
+     *
+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
+     * interrrupts on both interrupt lines. This should be changed if and when
+     * qemu supports IOMUX.
+     */
+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
         qemu_set_irq(s->irq[1], 1);
     } else {
         qemu_set_irq(s->irq[1], 0);
-- 
2.16.2

From: Wei Huang <wei@redhat.com>

For guest kernel that supports KASLR, the load address can change every
time when guest VM runs. To find the physical base address correctly,
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
However this string pattern is only available on x86_64. AArch64 uses a
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
QEMU dump uses the correct string on AArch64.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 dump.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/dump.c b/dump.c
index XXXXXXX..XXXXXXX 100644
--- a/dump.c
+++ b/dump.c
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
 
     lines = g_strsplit((char *)vmci, "\n", -1);
     for (i = 0; lines[i]; i++) {
-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+        const char *prefix = NULL;
+
+        if (s->dump_info.d_machine == EM_X86_64) {
+            prefix = "NUMBER(phys_base)=";
+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+            prefix = "NUMBER(PHYS_OFFSET)=";
+        }
+
+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
                               &phys_base) < 0) {
-                warn_report("Failed to read NUMBER(phys_base)=");
+                warn_report("Failed to read %s", prefix);
             } else {
                 s->dump_info.phys_base = phys_base;
             }
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Code of imx_update() is slightly confusing since the "flags" variable
doesn't really corespond to anything in real hardware and server as a
kitchensink accumulating events normally reported via USR1 and USR2
registers.

Change the code to explicitly evaluate state of interrupts reported
via USR1 and USR2 against corresponding masking bits and use the to
detemine if IRQ line should be asserted or not.

NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
reasons:

1. Emulation code implements a single character FIFO, so this flag
       will always be set since characters are trasmitted as a part of
       the code emulating "push" into the FIFO

2. imx_update() is really just a function doing ORing and maksing
       of reported events, so checking for UTS1_TXEMPTY should happen,
       if it's ever really needed should probably happen outside of
       it.

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/imx_serial.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
 
 static void imx_update(IMXSerialState *s)
 {
-    uint32_t flags;
+    uint32_t usr1;
+    uint32_t usr2;
+    uint32_t mask;
 
-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
-    if (s->ucr1 & UCR1_TXMPTYEN) {
-        flags |= (s->uts1 & UTS1_TXEMPTY);
-    } else {
-        flags &= ~USR1_TRDY;
-    }
+    /*
+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+     * UCR1, so we can get away with something as simple as the
+     * following:
+     */
+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+    /*
+     * Bits that we want in USR2 are not as conveniently laid out,
+     * unfortunately.
+     */
+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    usr2 = s->usr2 & mask;
 
-    qemu_set_irq(s->irq, !!flags);
+    qemu_set_irq(s->irq, usr1 || usr2);
 }
 
 static void imx_serial_reset(IMXSerialState *s)
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.

Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/imx_serial.h |  3 +++
 hw/char/imx_serial.c         | 20 +++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -XXX,XX +XXX,XX @@
 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
 #define UCR2_SRST       (1<<0)    /* Reset complete */
 
+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+
 #define UTS1_TXEMPTY    (1<<6)
 #define UTS1_RXEMPTY    (1<<5)
 #define UTS1_TXFULL     (1<<4)
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
     uint32_t ubmr;
     uint32_t ubrc;
     uint32_t ucr3;
+    uint32_t ucr4;
 
     qemu_irq irq;
     CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
 
 static const VMStateDescription vmstate_imx_serial = {
     .name = TYPE_IMX_SERIAL,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_INT32(readbuff, IMXSerialState),
         VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
         VMSTATE_UINT32(ubmr, IMXSerialState),
         VMSTATE_UINT32(ubrc, IMXSerialState),
         VMSTATE_UINT32(ucr3, IMXSerialState),
+        VMSTATE_UINT32(ucr4, IMXSerialState),
         VMSTATE_END_OF_LIST()
     },
 };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
      * unfortunately.
      */
     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    /*
+     * TCEN and TXDC are both bit 3
+     */
+    mask |= s->ucr4 & UCR4_TCEN;
+
     usr2 = s->usr2 & mask;
 
     qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
         return s->ucr3;
 
     case 0x23: /* UCR4 */
+        return s->ucr4;
+
     case 0x29: /* BRM Incremental */
         return 0x0; /* TODO */
 
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
              * qemu_chr_fe_write and background I/O callbacks */
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->usr1 &= ~USR1_TRDY;
+            s->usr2 &= ~USR2_TXDC;
             imx_update(s);
             s->usr1 |= USR1_TRDY;
+            s->usr2 |= USR2_TXDC;
             imx_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
         s->ucr3 = value & 0xffff;
         break;
 
-    case 0x2d: /* UTS1 */
     case 0x23: /* UCR4 */
+        s->ucr4 = value & 0xffff;
+        imx_update(s);
+        break;
+
+    case 0x2d: /* UTS1 */
         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
         /* TODO */
-- 
2.16.2

For the rpi1 and 2 we want to boot the Linux kernel via some
custom setup code that makes sure that the SMC instruction
acts as a no-op, because it's used for cache maintenance.
The rpi3 boots AArch64 kernels, which don't need SMC for
cache maintenance and always expect to be booted non-secure.
Don't fill in the aarch32-specific parts of the binfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     binfo.board_id = raspi_boardid[version];
     binfo.ram_size = ram_size;
     binfo.nb_cpus = smp_cpus;
-    binfo.board_setup_addr = BOARDSETUP_ADDR;
-    binfo.write_board_setup = write_board_setup;
-    binfo.secure_board_setup = true;
-    binfo.secure_boot = true;
+
+    if (version <= 2) {
+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         * mode before booting a kernel (to set up the SMC vectors so
+         * that we get a no-op SMC; this is used by Linux to call the
+         * firmware for some cache maintenance operations.
+         * The rpi3 doesn't need this.
+         */
+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+        binfo.write_board_setup = write_board_setup;
+        binfo.secure_board_setup = true;
+        binfo.secure_boot = true;
+    }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-- 
2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,
the board code has not mistakenly set either secure_boot or
secure_board_setup. It doesn't make sense to set secure_boot,
because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but
we don't currently support that, because only the AArch32
bootloader[] code calls this hook; bootloader_aarch64[] does not.
Since we don't have a current need for this functionality, just
assert that we don't try to use it. If it's needed we'll add
it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     } else {
                         env->pstate = PSTATE_MODE_EL1h;
                     }
+                    /* AArch64 kernels never boot in secure mode */
+                    assert(!info->secure_boot);
+                    /* This hook is only supported for AArch32 currently:
+                     * bootloader_aarch64[] will not call the hook, and
+                     * the code above has already dropped us into EL2 or EL1.
+                     */
+                    assert(!info->secure_board_setup);
                 }
 
                 /* Set to non-secure if not a secure boot */
-- 
2.16.2

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

The TypeInfo and state struct for bcm2386 disagree about what the
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
but the BCM2386State struct only defines the parent_obj field
as DeviceState. This would have caused problems if anything
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
need any of the additional functionality TYPE_SYS_BUS_DEVICE
provides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo bcm2836_type_info = {
     .name = TYPE_BCM2836,
-    .parent = TYPE_SYS_BUS_DEVICE,
+    .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM2836State),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
-- 
2.16.2

Our BCM2836 type is really a generic one that can be any of
the bcm283x family. Rename it accordingly. We change only
the names which are visible via the header file to the
rest of the QEMU code, leaving private function names
in bcm2836.c as they are.

This is a preliminary to making bcm283x be an abstract
parent class to specific types for the bcm2836 and bcm2837.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 12 ++++++------
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           | 16 ++++++++--------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
-#define TYPE_BCM2836 "bcm2836"
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+#define TYPE_BCM283X "bcm283x"
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 
-#define BCM2836_NCPUS 4
+#define BCM283X_NCPUS 4
 
-typedef struct BCM2836State {
+typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
     char *cpu_type;
     uint32_t enabled_cpus;
 
-    ARMCPU cpus[BCM2836_NCPUS];
+    ARMCPU cpus[BCM283X_NCPUS];
     BCM2836ControlState control;
     BCM2835PeripheralState peripherals;
-} BCM2836State;
+} BCM283XState;
 
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 static void bcm2836_init(Object *obj)
 {
-    BCM2836State *s = BCM2836(obj);
+    BCM283XState *s = BCM283X(obj);
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
 
 static void bcm2836_realize(DeviceState *dev, Error **errp)
 {
-    BCM2836State *s = BCM2836(dev);
+    BCM283XState *s = BCM283X(dev);
     Object *obj;
     Error *err = NULL;
     int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     /* common peripherals from bcm2835 */
 
     obj = OBJECT(dev);
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                           s->cpu_type);
         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         /* Mirror bcm2836, which has clusterid set to 0xf
          * TODO: this should be converted to a property of ARM_CPU
          */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                       BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 }
 
 static const TypeInfo bcm2836_type_info = {
-    .name = TYPE_BCM2836,
+    .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
-    .instance_size = sizeof(BCM2836State),
+    .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
 
 typedef struct RasPiState {
-    BCM2836State soc;
+    BCM283XState soc;
     MemoryRegion ram;
 } RasPiState;
 
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
 }
 DEFINE_MACHINE("raspi3", raspi3_machine_init)
-- 
2.16.2

The bcm2837 is pretty similar to the bcm2836, but it does have
some differences. Notably, the MPIDR affinity aff1 values it
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
uses, and if this is wrong Linux will not boot.

Rather than trying to have one device with properties that
configure it differently for the two cases, create two
separate QOM devices for the two SoCs. We use the same approach
as hw/arm/aspeed_soc.c and share code and have a data table
that might differ per-SoC. For the moment the two types don't
actually have different behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
 hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
 hw/arm/raspi.c           |  3 ++-
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 
 #define BCM283X_NCPUS 4
 
+/* These type names are for specific SoCs; other than instantiating
+ * them, code using these devices should always handle them via the
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ */
+#define TYPE_BCM2836 "bcm2836"
+#define TYPE_BCM2837 "bcm2837"
+
 typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
     BCM2835PeripheralState peripherals;
 } BCM283XState;
 
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+    DeviceClass parent_class;
+    const BCM283XInfo *info;
+} BCM283XClass;
+
+#define BCM283X_CLASS(klass) \
+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
 #define BCM2836_CONTROL_BASE    0x40000000
 
+struct BCM283XInfo {
+    const char *name;
+};
+
+static const BCM283XInfo bcm283x_socs[] = {
+    {
+        .name = TYPE_BCM2836,
+    },
+    {
+        .name = TYPE_BCM2837,
+    },
+};
+
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void bcm2836_class_init(ObjectClass *oc, void *data)
+static void bcm283x_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
+    BCM283XClass *bc = BCM283X_CLASS(oc);
 
-    dc->props = bcm2836_props;
+    bc->info = data;
     dc->realize = bcm2836_realize;
+    dc->props = bcm2836_props;
 }
 
-static const TypeInfo bcm2836_type_info = {
+static const TypeInfo bcm283x_type_info = {
     .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
-    .class_init = bcm2836_class_init,
+    .class_size = sizeof(BCM283XClass),
+    .abstract = true,
 };
 
 static void bcm2836_register_types(void)
 {
-    type_register_static(&bcm2836_type_info);
+    int i;
+
+    type_register_static(&bcm283x_type_info);
+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+        TypeInfo ti = {
+            .name = bcm283x_socs[i].name,
+            .parent = TYPE_BCM283X,
+            .class_init = bcm283x_class_init,
+            .class_data = (void *) &bcm283x_socs[i],
+        };
+        type_register(&ti);
+    }
 }
 
 type_init(bcm2836_register_types)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+    object_initialize(&s->soc, sizeof(s->soc),
+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
-- 
2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
is required for Linux to boot.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Now we have separate types for BCM2386 and BCM2387, we might as well
just hard-code the CPU type they use rather than having it passed
through as an object property. This then lets us put the initialization
of the CPU object in init rather than realize.

Note that this change means that it's no longer possible on
the command line to use -cpu to ask for a different kind of
CPU than the SoC supports. This was never a supported thing to
do anyway; we were just not sanity-checking the command line.

This does require us to only build the bcm2837 object on
TARGET_AARCH64 configs, since otherwise it won't instantiate
due to the missing cortex-a53 device and "make check" will fail.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 24 +++++++++++++++---------
 hw/arm/raspi.c   |  2 --
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 struct BCM283XInfo {
     const char *name;
+    const char *cpu_type;
     int clusterid;
 };
 
 static const BCM283XInfo bcm283x_socs[] = {
     {
         .name = TYPE_BCM2836,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
         .clusterid = 0xf,
     },
+#ifdef TARGET_AARCH64
     {
         .name = TYPE_BCM2837,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
         .clusterid = 0x0,
     },
+#endif
 };
 
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+    const BCM283XInfo *info = bc->info;
+    int n;
+
+    for (n = 0; n < BCM283X_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          info->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
-    obj = OBJECT(dev);
-    for (n = 0; n < BCM283X_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          s->cpu_type);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
-
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                        BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
-                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
-- 
2.16.2

The raspi3 has AArch64 CPUs, which means that our smpboot
code for keeping the secondary CPUs in a pen needs to have
a version for A64 as well as A32. Without this, the
secondary CPUs go into an infinite loop of taking undefined
instruction exceptions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
 
 /* Table of Linux board IDs for different Pi versions */
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                        info->smp_loader_start);
 }
 
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+     * The mechanism for doing the spin-table is also entirely different.
+     * We must have four 64-bit fields at absolute addresses
+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+     * our CPUs, and which we must ensure are zero initialized before
+     * the primary CPU goes into the kernel. We put these variables inside
+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+     */
+    static const uint32_t smpboot[] = {
+        0xd2801b05, /*        mov     x5, 0xd8 */
+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+        0x924004c6, /*        and     x6, x6, #0x3 */
+        0xd503205f, /* spin:  wfe */
+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+        0xb4ffffc4, /*        cbz     x4, spin */
+        0xd2800000, /*        mov     x0, #0x0 */
+        0xd2800001, /*        mov     x1, #0x0 */
+        0xd2800002, /*        mov     x2, #0x0 */
+        0xd2800003, /*        mov     x3, #0x0 */
+        0xd61f0080, /*        br      x4 */
+    };
+
+    static const uint64_t spintables[] = {
+        0, 0, 0, 0
+    };
+
+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
+                       info->smp_loader_start);
+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+                       SPINTABLE_ADDR);
+}
+
 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
         binfo.smp_loader_start = SMPBOOT_ADDR;
-        binfo.write_secondary_boot = write_smpboot;
+        if (version == 2) {
+            binfo.write_secondary_boot = write_smpboot;
+        } else {
+            binfo.write_secondary_boot = write_smpboot64;
+        }
         binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
-- 
2.16.2

Latest arm queue, a mixed bag of features and bug fixes.

thanks
-- PMM

The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (2020-01-17 12:13:17 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200117-1

for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:

target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +0000)

----------------------------------------------------------------
Add model of the Netduino Plus 2 board
Some allwinner-a10 code cleanup
New test cases for cubieboard
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
i.MX: add an emulation for RNGC device
target/arm: adjust program counter for wfi exception in AArch32
arm/gicv3: update virtual irq state after IAR register read
Set IL bit correctly for syndrome information for data aborts

----------------------------------------------------------------
Alistair Francis (4):
      hw/misc: Add the STM32F4xx Sysconfig device
      hw/misc: Add the STM32F4xx EXTI device
      hw/arm: Add the STM32F4xx SoC
      hw/arm: Add the Netduino Plus 2

Jeff Kubascik (3):
      target/arm: adjust program counter for wfi exception in AArch32
      arm/gicv3: update virtual irq state after IAR register read
      target/arm: Return correct IL bit in merge_syn_data_abort

Martin Kaiser (1):
      i.MX: add an emulation for RNGC

Masahiro Yamada (1):
      target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle

Philippe Mathieu-Daudé (5):
      tests/boot_linux_console: Add initrd test for the CubieBoard
      tests/boot_linux_console: Add a SD card test for the CubieBoard
      hw/arm/allwinner-a10: Move SoC definitions out of header
      hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
      hw/arm/allwinner-a10: Remove local qemu_irq variables

Richard Henderson (1):
      target/arm: Set ISSIs16Bit in make_issinfo

hw/arm/Makefile.objs                   |   2 +
 hw/misc/Makefile.objs                  |   3 +
 include/hw/arm/allwinner-a10.h         |   7 -
 include/hw/arm/fsl-imx25.h             |   5 +
 include/hw/arm/stm32f405_soc.h         |  73 ++++++++
 include/hw/misc/imx_rngc.h             |  35 ++++
 include/hw/misc/stm32f4xx_exti.h       |  60 +++++++
 include/hw/misc/stm32f4xx_syscfg.h     |  61 +++++++
 hw/arm/allwinner-a10.c                 |  39 +++--
 hw/arm/fsl-imx25.c                     |  11 ++
 hw/arm/netduinoplus2.c                 |  52 ++++++
 hw/arm/stm32f405_soc.c                 | 302 +++++++++++++++++++++++++++++++++
 hw/intc/arm_gicv3_cpuif.c              |   3 +
 hw/misc/imx_rngc.c                     | 278 ++++++++++++++++++++++++++++++
 hw/misc/stm32f4xx_exti.c               | 188 ++++++++++++++++++++
 hw/misc/stm32f4xx_syscfg.c             | 171 +++++++++++++++++++
 target/arm/arm-semi.c                  |   5 +-
 target/arm/op_helper.c                 |   7 +-
 target/arm/tlb_helper.c                |   2 +-
 target/arm/translate.c                 |   3 +
 MAINTAINERS                            |  14 ++
 default-configs/arm-softmmu.mak        |   1 +
 hw/arm/Kconfig                         |  10 ++
 hw/misc/Kconfig                        |   6 +
 hw/misc/trace-events                   |  11 ++
 tests/acceptance/boot_linux_console.py |  85 ++++++++++
 26 files changed, 1405 insertions(+), 29 deletions(-)
 create mode 100644 include/hw/arm/stm32f405_soc.h
 create mode 100644 include/hw/misc/imx_rngc.h
 create mode 100644 include/hw/misc/stm32f4xx_exti.h
 create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
 create mode 100644 hw/arm/netduinoplus2.c
 create mode 100644 hw/arm/stm32f405_soc.c
 create mode 100644 hw/misc/imx_rngc.c
 create mode 100644 hw/misc/stm32f4xx_exti.c
 create mode 100644 hw/misc/stm32f4xx_syscfg.c

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/Makefile.objs              |   1 +
 include/hw/misc/stm32f4xx_syscfg.h |  61 ++++++++++
 hw/misc/stm32f4xx_syscfg.c         | 171 +++++++++++++++++++++++++++++
 default-configs/arm-softmmu.mak    |   1 +
 hw/arm/Kconfig                     |   9 ++
 hw/misc/Kconfig                    |   3 +
 hw/misc/trace-events               |   6 +
 7 files changed, 252 insertions(+)
 create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
 create mode 100644 hw/misc/stm32f4xx_syscfg.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
 common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
 common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
+common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
 obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
 obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
 obj-$(CONFIG_MIPS_ITU) += mips_itu.o
diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/stm32f4xx_syscfg.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F4xx SYSCFG
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM_SYSCFG_H
+#define HW_STM_SYSCFG_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+
+#define SYSCFG_MEMRMP  0x00
+#define SYSCFG_PMC     0x04
+#define SYSCFG_EXTICR1 0x08
+#define SYSCFG_EXTICR2 0x0C
+#define SYSCFG_EXTICR3 0x10
+#define SYSCFG_EXTICR4 0x14
+#define SYSCFG_CMPCR   0x20
+
+#define TYPE_STM32F4XX_SYSCFG "stm32f4xx-syscfg"
+#define STM32F4XX_SYSCFG(obj) \
+    OBJECT_CHECK(STM32F4xxSyscfgState, (obj), TYPE_STM32F4XX_SYSCFG)
+
+#define SYSCFG_NUM_EXTICR 4
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    uint32_t syscfg_memrmp;
+    uint32_t syscfg_pmc;
+    uint32_t syscfg_exticr[SYSCFG_NUM_EXTICR];
+    uint32_t syscfg_cmpcr;
+
+    qemu_irq irq;
+    qemu_irq gpio_out[16];
+} STM32F4xxSyscfgState;
+
+#endif
diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/stm32f4xx_syscfg.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F4xx SYSCFG
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "hw/misc/stm32f4xx_syscfg.h"
+
+static void stm32f4xx_syscfg_reset(DeviceState *dev)
+{
+    STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);
+
+    s->syscfg_memrmp = 0x00000000;
+    s->syscfg_pmc = 0x00000000;
+    s->syscfg_exticr[0] = 0x00000000;
+    s->syscfg_exticr[1] = 0x00000000;
+    s->syscfg_exticr[2] = 0x00000000;
+    s->syscfg_exticr[3] = 0x00000000;
+    s->syscfg_cmpcr = 0x00000000;
+}
+
+static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)
+{
+    STM32F4xxSyscfgState *s = opaque;
+    int icrreg = irq / 4;
+    int startbit = (irq & 3) * 4;
+    uint8_t config = config = irq / 16;
+
+    trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);
+
+    g_assert(icrreg < SYSCFG_NUM_EXTICR);
+
+    if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
+        qemu_set_irq(s->gpio_out[irq], level);
+        trace_stm32f4xx_pulse_exti(irq);
+   }
+}
+
+static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,
+                                     unsigned int size)
+{
+    STM32F4xxSyscfgState *s = opaque;
+
+    trace_stm32f4xx_syscfg_read(addr);
+
+    switch (addr) {
+    case SYSCFG_MEMRMP:
+        return s->syscfg_memrmp;
+    case SYSCFG_PMC:
+        return s->syscfg_pmc;
+    case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
+        return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];
+    case SYSCFG_CMPCR:
+        return s->syscfg_cmpcr;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+        return 0;
+    }
+}
+
+static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,
+                       uint64_t val64, unsigned int size)
+{
+    STM32F4xxSyscfgState *s = opaque;
+    uint32_t value = val64;
+
+    trace_stm32f4xx_syscfg_write(value, addr);
+
+    switch (addr) {
+    case SYSCFG_MEMRMP:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: Changing the memory mapping isn't supported " \
+                      "in QEMU\n", __func__);
+        return;
+    case SYSCFG_PMC:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: Changing the memory mapping isn't supported " \
+                      "in QEMU\n", __func__);
+        return;
+    case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
+        s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);
+        return;
+    case SYSCFG_CMPCR:
+        s->syscfg_cmpcr = value;
+        return;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps stm32f4xx_syscfg_ops = {
+    .read = stm32f4xx_syscfg_read,
+    .write = stm32f4xx_syscfg_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f4xx_syscfg_init(Object *obj)
+{
+    STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,
+                          TYPE_STM32F4XX_SYSCFG, 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);
+    qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
+}
+
+static const VMStateDescription vmstate_stm32f4xx_syscfg = {
+    .name = TYPE_STM32F4XX_SYSCFG,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),
+        VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),
+        VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,
+                             SYSCFG_NUM_EXTICR),
+        VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f4xx_syscfg_reset;
+    dc->vmsd = &vmstate_stm32f4xx_syscfg;
+}
+
+static const TypeInfo stm32f4xx_syscfg_info = {
+    .name          = TYPE_STM32F4XX_SYSCFG,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F4xxSyscfgState),
+    .instance_init = stm32f4xx_syscfg_init,
+    .class_init    = stm32f4xx_syscfg_class_init,
+};
+
+static void stm32f4xx_syscfg_register_types(void)
+{
+    type_register_static(&stm32f4xx_syscfg_info);
+}
+
+type_init(stm32f4xx_syscfg_register_types)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_Z2=y
 CONFIG_COLLIE=y
 CONFIG_ASPEED_SOC=y
 CONFIG_NETDUINO2=y
+CONFIG_NETDUINOPLUS2=y
 CONFIG_MPS2=y
 CONFIG_RASPI=y
 CONFIG_DIGIC=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config NETDUINO2
     bool
     select STM32F205_SOC
 
+config NETDUINOPLUS2
+    bool
+    select STM32F405_SOC
+
 config NSERIES
     bool
     select OMAP
@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC
     select STM32F2XX_ADC
     select STM32F2XX_SPI
 
+config STM32F405_SOC
+    bool
+    select ARM_V7M
+    select STM32F4XX_SYSCFG
+
 config XLNX_ZYNQMP_ARM
     bool
     select AHCI
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config IMX
 config STM32F2XX_SYSCFG
     bool
 
+config STM32F4XX_SYSCFG
+    bool
+
 config MIPS_ITU
     bool
 
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
 mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
 
+# stm32f4xx_syscfg
+stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
+stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
+stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
+stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+
 # tz-mpc.c
 tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
 tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
-- 
2.20.1

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ef941d59fd8658589d34ed432e1d6dfdcf7fb1d0.1576658572.git.alistair@alistair23.me
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/Makefile.objs            |   1 +
 include/hw/misc/stm32f4xx_exti.h |  60 ++++++++++
 hw/misc/stm32f4xx_exti.c         | 188 +++++++++++++++++++++++++++++++
 hw/arm/Kconfig                   |   1 +
 hw/misc/Kconfig                  |   3 +
 hw/misc/trace-events             |   5 +
 6 files changed, 258 insertions(+)
 create mode 100644 include/hw/misc/stm32f4xx_exti.h
 create mode 100644 hw/misc/stm32f4xx_exti.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
 common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
 common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o
+common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o
 obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
 obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
 obj-$(CONFIG_MIPS_ITU) += mips_itu.o
diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/stm32f4xx_exti.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F4XX EXTI
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM_EXTI_H
+#define HW_STM_EXTI_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+
+#define EXTI_IMR   0x00
+#define EXTI_EMR   0x04
+#define EXTI_RTSR  0x08
+#define EXTI_FTSR  0x0C
+#define EXTI_SWIER 0x10
+#define EXTI_PR    0x14
+
+#define TYPE_STM32F4XX_EXTI "stm32f4xx-exti"
+#define STM32F4XX_EXTI(obj) \
+    OBJECT_CHECK(STM32F4xxExtiState, (obj), TYPE_STM32F4XX_EXTI)
+
+#define NUM_GPIO_EVENT_IN_LINES 16
+#define NUM_INTERRUPT_OUT_LINES 16
+
+typedef struct {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    uint32_t exti_imr;
+    uint32_t exti_emr;
+    uint32_t exti_rtsr;
+    uint32_t exti_ftsr;
+    uint32_t exti_swier;
+    uint32_t exti_pr;
+
+    qemu_irq irq[NUM_INTERRUPT_OUT_LINES];
+} STM32F4xxExtiState;
+
+#endif
diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/stm32f4xx_exti.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F4XX EXTI
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "hw/misc/stm32f4xx_exti.h"
+
+static void stm32f4xx_exti_reset(DeviceState *dev)
+{
+    STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);
+
+    s->exti_imr = 0x00000000;
+    s->exti_emr = 0x00000000;
+    s->exti_rtsr = 0x00000000;
+    s->exti_ftsr = 0x00000000;
+    s->exti_swier = 0x00000000;
+    s->exti_pr = 0x00000000;
+}
+
+static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)
+{
+    STM32F4xxExtiState *s = opaque;
+
+    trace_stm32f4xx_exti_set_irq(irq, level);
+
+    if (((1 << irq) & s->exti_rtsr) && level) {
+        /* Rising Edge */
+        s->exti_pr |= 1 << irq;
+    }
+
+    if (((1 << irq) & s->exti_ftsr) && !level) {
+        /* Falling Edge */
+        s->exti_pr |= 1 << irq;
+    }
+
+    if (!((1 << irq) & s->exti_imr)) {
+        /* Interrupt is masked */
+        return;
+    }
+    qemu_irq_pulse(s->irq[irq]);
+}
+
+static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,
+                                     unsigned int size)
+{
+    STM32F4xxExtiState *s = opaque;
+
+    trace_stm32f4xx_exti_read(addr);
+
+    switch (addr) {
+    case EXTI_IMR:
+        return s->exti_imr;
+    case EXTI_EMR:
+        return s->exti_emr;
+    case EXTI_RTSR:
+        return s->exti_rtsr;
+    case EXTI_FTSR:
+        return s->exti_ftsr;
+    case EXTI_SWIER:
+        return s->exti_swier;
+    case EXTI_PR:
+        return s->exti_pr;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);
+        return 0;
+    }
+    return 0;
+}
+
+static void stm32f4xx_exti_write(void *opaque, hwaddr addr,
+                       uint64_t val64, unsigned int size)
+{
+    STM32F4xxExtiState *s = opaque;
+    uint32_t value = (uint32_t) val64;
+
+    trace_stm32f4xx_exti_write(addr, value);
+
+    switch (addr) {
+    case EXTI_IMR:
+        s->exti_imr = value;
+        return;
+    case EXTI_EMR:
+        s->exti_emr = value;
+        return;
+    case EXTI_RTSR:
+        s->exti_rtsr = value;
+        return;
+    case EXTI_FTSR:
+        s->exti_ftsr = value;
+        return;
+    case EXTI_SWIER:
+        s->exti_swier = value;
+        return;
+    case EXTI_PR:
+        /* This bit is cleared by writing a 1 to it */
+        s->exti_pr &= ~value;
+        return;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);
+    }
+}
+
+static const MemoryRegionOps stm32f4xx_exti_ops = {
+    .read = stm32f4xx_exti_read,
+    .write = stm32f4xx_exti_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f4xx_exti_init(Object *obj)
+{
+    STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);
+    int i;
+
+    for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {
+        sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
+    }
+
+    memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,
+                          TYPE_STM32F4XX_EXTI, 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,
+                      NUM_GPIO_EVENT_IN_LINES);
+}
+
+static const VMStateDescription vmstate_stm32f4xx_exti = {
+    .name = TYPE_STM32F4XX_EXTI,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),
+        VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),
+        VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),
+        VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),
+        VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),
+        VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f4xx_exti_reset;
+    dc->vmsd = &vmstate_stm32f4xx_exti;
+}
+
+static const TypeInfo stm32f4xx_exti_info = {
+    .name          = TYPE_STM32F4XX_EXTI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F4xxExtiState),
+    .instance_init = stm32f4xx_exti_init,
+    .class_init    = stm32f4xx_exti_class_init,
+};
+
+static void stm32f4xx_exti_register_types(void)
+{
+    type_register_static(&stm32f4xx_exti_info);
+}
+
+type_init(stm32f4xx_exti_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
     bool
     select ARM_V7M
     select STM32F4XX_SYSCFG
+    select STM32F4XX_EXTI
 
 config XLNX_ZYNQMP_ARM
     bool
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config STM32F2XX_SYSCFG
 config STM32F4XX_SYSCFG
     bool
 
+config STM32F4XX_EXTI
+    bool
+
 config MIPS_ITU
     bool
 
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
 stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
 stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
 
+# stm32f4xx_exti
+stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
+stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
+stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+
 # tz-mpc.c
 tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u"
 tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u"
-- 
2.20.1

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1d145c4c13e5fa140caf131232a6f524c88fcd72.1576658572.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/Makefile.objs           |   1 +
 include/hw/arm/stm32f405_soc.h |  73 ++++++++
 hw/arm/stm32f405_soc.c         | 302 +++++++++++++++++++++++++++++++++
 MAINTAINERS                    |   8 +
 4 files changed, 384 insertions(+)
 create mode 100644 include/hw/arm/stm32f405_soc.h
 create mode 100644 hw/arm/stm32f405_soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STRONGARM) += strongarm.o
 obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
 obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
+obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
 obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
 obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
 obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/stm32f405_soc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F405 SoC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_STM32F405_SOC_H
+#define HW_ARM_STM32F405_SOC_H
+
+#include "hw/misc/stm32f4xx_syscfg.h"
+#include "hw/timer/stm32f2xx_timer.h"
+#include "hw/char/stm32f2xx_usart.h"
+#include "hw/adc/stm32f2xx_adc.h"
+#include "hw/misc/stm32f4xx_exti.h"
+#include "hw/or-irq.h"
+#include "hw/ssi/stm32f2xx_spi.h"
+#include "hw/arm/armv7m.h"
+
+#define TYPE_STM32F405_SOC "stm32f405-soc"
+#define STM32F405_SOC(obj) \
+    OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
+
+#define STM_NUM_USARTS 7
+#define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 6
+#define STM_NUM_SPIS 6
+
+#define FLASH_BASE_ADDRESS 0x08000000
+#define FLASH_SIZE (1024 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (192 * 1024)
+
+typedef struct STM32F405State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    char *cpu_type;
+
+    ARMv7MState armv7m;
+
+    STM32F4xxSyscfgState syscfg;
+    STM32F4xxExtiState exti;
+    STM32F2XXUsartState usart[STM_NUM_USARTS];
+    STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    qemu_or_irq adc_irqs;
+    STM32F2XXADCState adc[STM_NUM_ADCS];
+    STM32F2XXSPIState spi[STM_NUM_SPIS];
+
+    MemoryRegion sram;
+    MemoryRegion flash;
+    MemoryRegion flash_alias;
+} STM32F405State;
+
+#endif
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32f405_soc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F405 SoC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "hw/arm/stm32f405_soc.h"
+#include "hw/misc/unimp.h"
+
+#define SYSCFG_ADD                     0x40013800
+static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
+                                       0x40004C00, 0x40005000, 0x40011400,
+                                       0x40007800, 0x40007C00 };
+/* At the moment only Timer 2 to 5 are modelled */
+static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
+                                       0x40000800, 0x40000C00 };
+#define ADC_ADDR                       0x40012000
+static const uint32_t spi_addr[] =   { 0x40013000, 0x40003800, 0x40003C00,
+                                       0x40013400, 0x40015000, 0x40015400 };
+#define EXTI_ADDR                      0x40013C00
+
+#define SYSCFG_IRQ               71
+static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
+static const int timer_irq[] = { 28, 29, 30, 50 };
+#define ADC_IRQ 18
+static const int spi_irq[] =   { 35, 36, 51, 0, 0, 0 };
+static const int exti_irq[] =  { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
+                                 40, 40, 40, 40, 40} ;
+
+
+static void stm32f405_soc_initfn(Object *obj)
+{
+    STM32F405State *s = STM32F405_SOC(obj);
+    int i;
+
+    sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
+                          TYPE_ARMV7M);
+
+    sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
+                          TYPE_STM32F4XX_SYSCFG);
+
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
+                              sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
+    }
+
+    for (i = 0; i < STM_NUM_TIMERS; i++) {
+        sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
+                              sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
+    }
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
+                              TYPE_STM32F2XX_ADC);
+    }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
+                              TYPE_STM32F2XX_SPI);
+    }
+
+    sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
+                          TYPE_STM32F4XX_EXTI);
+}
+
+static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    STM32F405State *s = STM32F405_SOC(dev_soc);
+    MemoryRegion *system_memory = get_system_memory();
+    DeviceState *dev, *armv7m;
+    SysBusDevice *busdev;
+    Error *err = NULL;
+    int i;
+
+    memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE,
+                           &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias",
+                             &s->flash, 0, FLASH_SIZE);
+
+    memory_region_set_readonly(&s->flash, true);
+    memory_region_set_readonly(&s->flash_alias, true);
+
+    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
+    memory_region_add_subregion(system_memory, 0, &s->flash_alias);
+
+    memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
+                           &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
+
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 96);
+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+    qdev_prop_set_bit(armv7m, "enable-bitband", true);
+    object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
+                                     "memory", &error_abort);
+    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    /* System configuration controller */
+    dev = DEVICE(&s->syscfg);
+    object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
+    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
+
+    /* Attach UART (uses USART registers) and USART controllers */
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        dev = DEVICE(&(s->usart[i]));
+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+        object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+    }
+
+    /* Timer 2 to 5 */
+    for (i = 0; i < STM_NUM_TIMERS; i++) {
+        dev = DEVICE(&(s->timer[i]));
+        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
+        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, timer_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
+    }
+
+    /* ADC device, the IRQs are ORed together */
+    object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs,
+                            sizeof(s->adc_irqs), TYPE_OR_IRQ,
+                            &err, NULL);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
+                            "num-lines", &err);
+    object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
+                          qdev_get_gpio_in(armv7m, ADC_IRQ));
+
+    dev = DEVICE(&(s->adc[i]));
+    object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, ADC_ADDR);
+    sysbus_connect_irq(busdev, 0,
+                       qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
+
+    /* SPI devices */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
+    }
+
+    /* EXTI device */
+    dev = DEVICE(&s->exti);
+    object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, EXTI_ADDR);
+    for (i = 0; i < 16; i++) {
+        sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
+    }
+    for (i = 0; i < 16; i++) {
+        qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
+    }
+
+    create_unimplemented_device("timer[7]",    0x40001400, 0x400);
+    create_unimplemented_device("timer[12]",   0x40001800, 0x400);
+    create_unimplemented_device("timer[6]",    0x40001000, 0x400);
+    create_unimplemented_device("timer[13]",   0x40001C00, 0x400);
+    create_unimplemented_device("timer[14]",   0x40002000, 0x400);
+    create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
+    create_unimplemented_device("WWDG",        0x40002C00, 0x400);
+    create_unimplemented_device("IWDG",        0x40003000, 0x400);
+    create_unimplemented_device("I2S2ext",     0x40003000, 0x400);
+    create_unimplemented_device("I2S3ext",     0x40004000, 0x400);
+    create_unimplemented_device("I2C1",        0x40005400, 0x400);
+    create_unimplemented_device("I2C2",        0x40005800, 0x400);
+    create_unimplemented_device("I2C3",        0x40005C00, 0x400);
+    create_unimplemented_device("CAN1",        0x40006400, 0x400);
+    create_unimplemented_device("CAN2",        0x40006800, 0x400);
+    create_unimplemented_device("PWR",         0x40007000, 0x400);
+    create_unimplemented_device("DAC",         0x40007400, 0x400);
+    create_unimplemented_device("timer[1]",    0x40010000, 0x400);
+    create_unimplemented_device("timer[8]",    0x40010400, 0x400);
+    create_unimplemented_device("SDIO",        0x40012C00, 0x400);
+    create_unimplemented_device("timer[9]",    0x40014000, 0x400);
+    create_unimplemented_device("timer[10]",   0x40014400, 0x400);
+    create_unimplemented_device("timer[11]",   0x40014800, 0x400);
+    create_unimplemented_device("GPIOA",       0x40020000, 0x400);
+    create_unimplemented_device("GPIOB",       0x40020400, 0x400);
+    create_unimplemented_device("GPIOC",       0x40020800, 0x400);
+    create_unimplemented_device("GPIOD",       0x40020C00, 0x400);
+    create_unimplemented_device("GPIOE",       0x40021000, 0x400);
+    create_unimplemented_device("GPIOF",       0x40021400, 0x400);
+    create_unimplemented_device("GPIOG",       0x40021800, 0x400);
+    create_unimplemented_device("GPIOH",       0x40021C00, 0x400);
+    create_unimplemented_device("GPIOI",       0x40022000, 0x400);
+    create_unimplemented_device("CRC",         0x40023000, 0x400);
+    create_unimplemented_device("RCC",         0x40023800, 0x400);
+    create_unimplemented_device("Flash Int",   0x40023C00, 0x400);
+    create_unimplemented_device("BKPSRAM",     0x40024000, 0x400);
+    create_unimplemented_device("DMA1",        0x40026000, 0x400);
+    create_unimplemented_device("DMA2",        0x40026400, 0x400);
+    create_unimplemented_device("Ethernet",    0x40028000, 0x1400);
+    create_unimplemented_device("USB OTG HS",  0x40040000, 0x30000);
+    create_unimplemented_device("USB OTG FS",  0x50000000, 0x31000);
+    create_unimplemented_device("DCMI",        0x50050000, 0x400);
+    create_unimplemented_device("RNG",         0x50060800, 0x400);
+}
+
+static Property stm32f405_soc_properties[] = {
+    DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = stm32f405_soc_realize;
+    dc->props = stm32f405_soc_properties;
+    /* No vmstate or reset required: device has no internal state */
+}
+
+static const TypeInfo stm32f405_soc_info = {
+    .name          = TYPE_STM32F405_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F405State),
+    .instance_init = stm32f405_soc_initfn,
+    .class_init    = stm32f405_soc_class_init,
+};
+
+static void stm32f405_soc_types(void)
+{
+    type_register_static(&stm32f405_soc_info);
+}
+
+type_init(stm32f405_soc_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/adc/*
 F: hw/ssi/stm32f2xx_spi.c
 F: include/hw/*/stm32*.h
 
+STM32F405
+M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
+S: Maintained
+F: hw/arm/stm32f405_soc.c
+F: hw/misc/stm32f4xx_syscfg.c
+F: hw/misc/stm32f4xx_exti.c
+
 Netduino 2
 M: Alistair Francis <alistair@alistair23.me>
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

From: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: dad8d8d47f7625913e35e27a1c00f603a6b08f9a.1576658572.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/Makefile.objs   |  1 +
 hw/arm/netduinoplus2.c | 52 ++++++++++++++++++++++++++++++++++++++++++
 MAINTAINERS            |  6 +++++
 3 files changed, 59 insertions(+)
 create mode 100644 hw/arm/netduinoplus2.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MAINSTONE) += mainstone.o
 obj-$(CONFIG_MICROBIT) += microbit.o
 obj-$(CONFIG_MUSICPAL) += musicpal.o
 obj-$(CONFIG_NETDUINO2) += netduino2.o
+obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o
 obj-$(CONFIG_NSERIES) += nseries.o
 obj-$(CONFIG_SX1) += omap_sx1.o
 obj-$(CONFIG_CHEETAH) += palm.o
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/netduinoplus2.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Netduino Plus 2 Machine Model
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f405_soc.h"
+#include "hw/arm/boot.h"
+
+static void netduinoplus2_init(MachineState *machine)
+{
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, TYPE_STM32F405_SOC);
+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+    object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+
+    armv7m_load_kernel(ARM_CPU(first_cpu),
+                       machine->kernel_filename,
+                       FLASH_SIZE);
+}
+
+static void netduinoplus2_machine_init(MachineClass *mc)
+{
+    mc->desc = "Netduino Plus 2 Machine";
+    mc->init = netduinoplus2_init;
+}
+
+DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/netduino2.c
 
+Netduino Plus 2
+M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
+S: Maintained
+F: hw/arm/netduinoplus2.c
+
 SmartFusion2
 M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

This test boots a Linux kernel on a CubieBoard and verify
the serial output is working.

The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://docs.armbian.com/Developer-Guide_Build-Preparation/

The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test

If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.

Alternatively, this test can be run using:

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20191230110953.25496-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
         self.wait_for_console_pattern('Boot successful.')
         # TODO user command, for now the uart is stuck
 
+    def test_arm_cubieboard_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:cubieboard
+        """
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+        deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path,
+                                            '/boot/vmlinuz-4.20.7-sunxi')
+        dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
+        dtb_path = self.extract_from_deb(deb_path, dtb_path)
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv5.cpio.gz')
+        initrd_hash = '2b50f1873e113523967806f4da2afe385462ff9b'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'console=ttyS0,115200 '
+                               'usbcore.nousb '
+                               'panic=-1 noreboot')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'Allwinner sun4i/sun5i')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                'system-control@1c00000')
+        exec_command_and_wait_for_pattern(self, 'reboot',
+                                                'reboot: Restarting system')
+
     def test_s390x_s390_ccw_virtio(self):
         """
         :avocado: tags=arch:s390x
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://docs.armbian.com/Developer-Guide_Build-Preparation/

The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test

If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.

Alternatively, this test can be run using:

$ avocado --show=console run -t machine:cubieboard tests/acceptance/boot_linux_console.py
  console: Uncompressing Linux... done, booting the kernel.
  console: Booting Linux on physical CPU 0x0
  console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
  [...]
  console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4
  console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit
  console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps 0x1 impl platform mode
  console: ahci-sunxi 1c18000.sata: flags: ncq only
  console: scsi host0: ahci-sunxi
  console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 27
  console: of_cfs_init
  console: of_cfs_init: OK
  console: vcc3v0: disabling
  console: vcc5v0: disabling
  console: usb1-vbus: disabling
  console: usb2-vbus: disabling
  console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
  console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100
  console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32)
  console: ata1.00: applying bridge limits
  console: ata1.00: configured for UDMA/100
  console: scsi 0:0:0:0: Direct-Access     ATA      QEMU HARDDISK    2.5+ PQ: 0 ANSI: 5
  console: sd 0:0:0:0: Attached scsi generic sg0 type 0
  console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB)
  console: sd 0:0:0:0: [sda] Write Protect is off
  console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
  console: sd 0:0:0:0: [sda] Attached SCSI disk
  console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem
  console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null)
  console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0.
  [...]
  console: cat /proc/partitions
  console: / # cat /proc/partitions
  console: major minor  #blocks  name
  console: 1        0       4096 ram0
  console: 1        1       4096 ram1
  console: 1        2       4096 ram2
  console: 1        3       4096 ram3
  console: 8        0      20480 sda
  console: reboot
  console: / # reboot
  [...]
  console: sd 0:0:0:0: [sda] Synchronizing SCSI cache
  console: reboot: Restarting system
  PASS (48.39 s)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20191230110953.25496-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test):
         exec_command_and_wait_for_pattern(self, 'reboot',
                                                 'reboot: Restarting system')
 
+    def test_arm_cubieboard_sata(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:cubieboard
+        """
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb')
+        deb_hash = '1334c29c44d984ffa05ed10de8c3361f33d78315'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path,
+                                            '/boot/vmlinuz-4.20.7-sunxi')
+        dtb_path = '/usr/lib/linux-image-dev-sunxi/sun4i-a10-cubieboard.dtb'
+        dtb_path = self.extract_from_deb(deb_path, dtb_path)
+        rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv5.ext2.gz')
+        rootfs_hash = '093e89d2b4d982234bf528bc9fb2f2f17a9d1f93'
+        rootfs_path_gz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
+        rootfs_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(rootfs_path_gz, rootfs_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'console=ttyS0,115200 '
+                               'usbcore.nousb '
+                               'root=/dev/sda ro '
+                               'panic=-1 noreboot')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-drive', 'if=none,format=raw,id=disk0,file='
+                                   + rootfs_path,
+                         '-device', 'ide-hd,bus=ide.0,drive=disk0',
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'Allwinner sun4i/sun5i')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
+                                                'sda')
+        exec_command_and_wait_for_pattern(self, 'reboot',
+                                                'reboot: Restarting system')
+
     def test_s390x_s390_ccw_virtio(self):
         """
         :avocado: tags=arch:s390x
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

These definitions are specific to the A10 SoC and don't need
to be exported to the different Allwinner peripherals.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20191230110953.25496-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-a10.h | 6 ------
 hw/arm/allwinner-a10.c         | 6 ++++++
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "target/arm/cpu.h"
 
 
-#define AW_A10_PIC_REG_BASE     0x01c20400
-#define AW_A10_PIT_REG_BASE     0x01c20c00
-#define AW_A10_UART0_REG_BASE   0x01c28000
-#define AW_A10_EMAC_BASE        0x01c0b000
-#define AW_A10_SATA_BASE        0x01c18000
-
 #define AW_A10_SDRAM_BASE       0x40000000
 
 #define TYPE_AW_A10 "allwinner-a10"
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "sysemu/sysemu.h"
 
+#define AW_A10_PIC_REG_BASE     0x01c20400
+#define AW_A10_PIT_REG_BASE     0x01c20c00
+#define AW_A10_UART0_REG_BASE   0x01c28000
+#define AW_A10_EMAC_BASE        0x01c0b000
+#define AW_A10_SATA_BASE        0x01c18000
+
 static void aw_a10_init(Object *obj)
 {
     AwA10State *s = AW_A10(obj);
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By calling qdev_pass_gpios() we don't need to hold a copy of the
IRQs from the INTC into the SoC state.
Instead of filling an array of qemu_irq and passing it around, we
can now directly call qdev_get_gpio_in() on the SoC.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20191230110953.25496-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-a10.h |  1 -
 hw/arm/allwinner-a10.c         | 24 +++++++++++-------------
 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@ typedef struct AwA10State {
     /*< public >*/
 
     ARMCPU cpu;
-    qemu_irq irq[AW_A10_PIC_INT_NR];
     AwA10PITState timer;
     AwA10PICState intc;
     AwEmacState emac;
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
 {
     AwA10State *s = AW_A10(dev);
     SysBusDevice *sysbusdev;
-    uint8_t i;
     qemu_irq fiq, irq;
     Error *err = NULL;
 
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
     sysbus_connect_irq(sysbusdev, 0, irq);
     sysbus_connect_irq(sysbusdev, 1, fiq);
-    for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
-        s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
-    }
+    qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
 
     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
     if (err != NULL) {
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     }
     sysbusdev = SYS_BUS_DEVICE(&s->timer);
     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
-    sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
-    sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
-    sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
-    sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
-    sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
-    sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
+    sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
+    sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
+    sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
+    sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
+    sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
+    sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
 
     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
                            &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     }
     sysbusdev = SYS_BUS_DEVICE(&s->emac);
     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
-    sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
+    sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
 
     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
     if (err) {
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
 
     /* FIXME use a qdev chardev prop instead of serial_hd() */
-    serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
+    serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
+                   qdev_get_gpio_in(dev, 1),
                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 }
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We won't reuse the CPU IRQ/FIQ variables. Simplify by calling
qdev_get_gpio_in() in place.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20191230110953.25496-6-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/allwinner-a10.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
 {
     AwA10State *s = AW_A10(dev);
     SysBusDevice *sysbusdev;
-    qemu_irq fiq, irq;
     Error *err = NULL;
 
     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
         error_propagate(errp, err);
         return;
     }
-    irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
-    fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
 
     object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
     if (err != NULL) {
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     }
     sysbusdev = SYS_BUS_DEVICE(&s->intc);
     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
-    sysbus_connect_irq(sysbusdev, 0, irq);
-    sysbus_connect_irq(sysbusdev, 1, fiq);
+    sysbus_connect_irq(sysbusdev, 0,
+                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+    sysbus_connect_irq(sysbusdev, 1,
+                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
 
     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
-- 
2.20.1

From: Masahiro Yamada <masahiroy@kernel.org>

According to the specification "Semihosting for AArch32 and Aarch64",
the SYS_OPEN operation should return:

- A nonzero handle if the call is successful
 - -1 if the call is not successful

So, it should never return 0.

Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting
code hand out its own file descriptors"), the guest fd matched to the
host fd. It returned a nonzero handle on success since the fd 0 is
already used for stdin.

Now that the guest fd is the index of guestfd_array, it starts from 0.

I noticed this issue particularly because Trusted Firmware-A built with
PLAT=qemu is no longer working. Its io_semihosting driver only handles
a positive return value as a valid filehandle.

Basically, there are two ways to fix this:

- Use (guestfd - 1) as the index of guestfs_arrary. We need to insert
    increment/decrement to convert the guestfd and the array index back
    and forth.

- Keep using guestfd as the index of guestfs_array. The first entry
    of guestfs_array is left unused.

I thought the latter is simpler. We end up with wasting a small piece
of memory for the unused first entry of guestfd_array, but this is
probably not a big deal.

Fixes: 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting code hand out its own file descriptors")
Cc: qemu-stable@nongnu.org
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200109041228.10131-1-masahiroy@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/arm-semi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@ static int alloc_guestfd(void)
         guestfd_array = g_array_new(FALSE, TRUE, sizeof(GuestFD));
     }
 
-    for (i = 0; i < guestfd_array->len; i++) {
+    /* SYS_OPEN should return nonzero handle on success. Start guestfd from 1 */
+    for (i = 1; i < guestfd_array->len; i++) {
         GuestFD *gf = &g_array_index(guestfd_array, GuestFD, i);
 
         if (gf->type == GuestFDUnused) {
@@ -XXX,XX +XXX,XX @@ static GuestFD *do_get_guestfd(int guestfd)
         return NULL;
     }
 
-    if (guestfd < 0 || guestfd >= guestfd_array->len) {
+    if (guestfd <= 0 || guestfd >= guestfd_array->len) {
         return NULL;
     }
 
-- 
2.20.1

From: Martin Kaiser <martin@kaiser.cx>

Add an emulation for the RNGC random number generator and the compatible
RNGB variant. These peripherals are included (at least) in imx25 and
imx35 chipsets.

The emulation supports the initial self test, reseeding the prng and
reading random numbers.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/Makefile.objs      |   1 +
 include/hw/arm/fsl-imx25.h |   5 +
 include/hw/misc/imx_rngc.h |  35 +++++
 hw/arm/fsl-imx25.c         |  11 ++
 hw/misc/imx_rngc.c         | 278 +++++++++++++++++++++++++++++++++++++
 5 files changed, 330 insertions(+)
 create mode 100644 include/hw/misc/imx_rngc.h
 create mode 100644 hw/misc/imx_rngc.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx7_ccm.o
 common-obj-$(CONFIG_IMX) += imx2_wdt.o
 common-obj-$(CONFIG_IMX) += imx7_snvs.o
 common-obj-$(CONFIG_IMX) += imx7_gpr.o
+common-obj-$(CONFIG_IMX) += imx_rngc.o
 common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
 common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
 common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/timer/imx_gpt.h"
 #include "hw/timer/imx_epit.h"
 #include "hw/net/imx_fec.h"
+#include "hw/misc/imx_rngc.h"
 #include "hw/i2c/imx_i2c.h"
 #include "hw/gpio/imx_gpio.h"
 #include "exec/memory.h"
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
     IMXGPTState    gpt[FSL_IMX25_NUM_GPTS];
     IMXEPITState   epit[FSL_IMX25_NUM_EPITS];
     IMXFECState    fec;
+    IMXRNGCState   rngc;
     IMXI2CState    i2c[FSL_IMX25_NUM_I2CS];
     IMXGPIOState   gpio[FSL_IMX25_NUM_GPIOS];
     MemoryRegion   rom[2];
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
 #define FSL_IMX25_GPIO4_SIZE    0x4000
 #define FSL_IMX25_GPIO3_ADDR    0x53FA4000
 #define FSL_IMX25_GPIO3_SIZE    0x4000
+#define FSL_IMX25_RNGC_ADDR     0x53FB0000
+#define FSL_IMX25_RNGC_SIZE     0x4000
 #define FSL_IMX25_GPIO1_ADDR    0x53FCC000
 #define FSL_IMX25_GPIO1_SIZE    0x4000
 #define FSL_IMX25_GPIO2_ADDR    0x53FD0000
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX25State {
 #define FSL_IMX25_EPIT1_IRQ     28
 #define FSL_IMX25_EPIT2_IRQ     27
 #define FSL_IMX25_FEC_IRQ       57
+#define FSL_IMX25_RNGC_IRQ      22
 #define FSL_IMX25_I2C1_IRQ      3
 #define FSL_IMX25_I2C2_IRQ      4
 #define FSL_IMX25_I2C3_IRQ      10
diff --git a/include/hw/misc/imx_rngc.h b/include/hw/misc/imx_rngc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/imx_rngc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Freescale i.MX RNGC emulation
+ *
+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX_RNGC_H
+#define IMX_RNGC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_IMX_RNGC "imx.rngc"
+#define IMX_RNGC(obj) OBJECT_CHECK(IMXRNGCState, (obj), TYPE_IMX_RNGC)
+
+typedef struct IMXRNGCState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion  iomem;
+
+    uint8_t op_self_test;
+    uint8_t op_seed;
+    uint8_t mask;
+    bool    auto_seed;
+
+    QEMUBH *self_test_bh;
+    QEMUBH *seed_bh;
+    qemu_irq irq;
+} IMXRNGCState;
+
+#endif /* IMX_RNGC_H */
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_init(Object *obj)
 
     sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
 
+    sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc),
+                          TYPE_IMX_RNGC);
+
     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
         sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
                               TYPE_IMX_I2C);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
 
+    object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
+                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
 
     /* Initialize all I2C */
     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/imx_rngc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Freescale i.MX RNGC emulation
+ *
+ * Copyright (C) 2020 Martin Kaiser <martin@kaiser.cx>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * This driver provides the minimum functionality to initialize and seed
+ * an rngc and to read random numbers. The rngb that is found in imx25
+ * chipsets is also supported.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "qemu/module.h"
+#include "qemu/log.h"
+#include "qemu/guest-random.h"
+#include "hw/irq.h"
+#include "hw/misc/imx_rngc.h"
+#include "migration/vmstate.h"
+
+#define RNGC_NAME "i.MX RNGC"
+
+#define RNGC_VER_ID  0x00
+#define RNGC_COMMAND 0x04
+#define RNGC_CONTROL 0x08
+#define RNGC_STATUS  0x0C
+#define RNGC_FIFO    0x14
+
+/* These version info are reported by the rngb in an imx258 chip. */
+#define RNG_TYPE_RNGB 0x1
+#define V_MAJ 0x2
+#define V_MIN 0x40
+
+#define RNGC_CMD_BIT_SW_RST    0x40
+#define RNGC_CMD_BIT_CLR_ERR   0x20
+#define RNGC_CMD_BIT_CLR_INT   0x10
+#define RNGC_CMD_BIT_SEED      0x02
+#define RNGC_CMD_BIT_SELF_TEST 0x01
+
+#define RNGC_CTRL_BIT_MASK_ERR  0x40
+#define RNGC_CTRL_BIT_MASK_DONE 0x20
+#define RNGC_CTRL_BIT_AUTO_SEED 0x10
+
+/* the current status for self-test and seed operations */
+#define OP_IDLE 0
+#define OP_RUN  1
+#define OP_DONE 2
+
+static uint64_t imx_rngc_read(void *opaque, hwaddr offset, unsigned size)
+{
+    IMXRNGCState *s = IMX_RNGC(opaque);
+    uint64_t val = 0;
+
+    switch (offset) {
+    case RNGC_VER_ID:
+        val |= RNG_TYPE_RNGB << 28 | V_MAJ << 8 | V_MIN;
+        break;
+
+    case RNGC_COMMAND:
+        if (s->op_seed == OP_RUN) {
+            val |= RNGC_CMD_BIT_SEED;
+        }
+        if (s->op_self_test == OP_RUN) {
+            val |= RNGC_CMD_BIT_SELF_TEST;
+        }
+        break;
+
+    case RNGC_CONTROL:
+        /*
+         * The CTL_ACC and VERIF_MODE bits are not supported yet.
+         * They read as 0.
+         */
+        val |= s->mask;
+        if (s->auto_seed) {
+            val |= RNGC_CTRL_BIT_AUTO_SEED;
+        }
+        /*
+         * We don't have an internal fifo like the real hardware.
+         * There's no need for strategy to handle fifo underflows.
+         * We return the FIFO_UFLOW_RESPONSE bits as 0.
+         */
+        break;
+
+    case RNGC_STATUS:
+        /*
+         * We never report any statistics test or self-test errors or any
+         * other errors. STAT_TEST_PF, ST_PF and ERROR are always 0.
+         */
+
+        /*
+         * We don't have an internal fifo, see above. Therefore, we
+         * report back the default fifo size (5 32-bit words) and
+         * indicate that our fifo is always full.
+         */
+        val |= 5 << 12 | 5 << 8;
+
+        /* We always have a new seed available. */
+        val |= 1 << 6;
+
+        if (s->op_seed == OP_DONE) {
+            val |= 1 << 5;
+        }
+        if (s->op_self_test == OP_DONE) {
+            val |= 1 << 4;
+        }
+        if (s->op_seed == OP_RUN || s->op_self_test == OP_RUN) {
+            /*
+             * We're busy if self-test is running or if we're
+             * seeding the prng.
+             */
+            val |= 1 << 1;
+        } else {
+            /*
+             * We're ready to provide secure random numbers whenever
+             * we're not busy.
+             */
+            val |= 1;
+        }
+        break;
+
+    case RNGC_FIFO:
+        qemu_guest_getrandom_nofail(&val, sizeof(val));
+        break;
+    }
+
+    return val;
+}
+
+static void imx_rngc_do_reset(IMXRNGCState *s)
+{
+    s->op_self_test = OP_IDLE;
+    s->op_seed = OP_IDLE;
+    s->mask = 0;
+    s->auto_seed = false;
+}
+
+static void imx_rngc_write(void *opaque, hwaddr offset, uint64_t value,
+                           unsigned size)
+{
+    IMXRNGCState *s = IMX_RNGC(opaque);
+
+    switch (offset) {
+    case RNGC_COMMAND:
+        if (value & RNGC_CMD_BIT_SW_RST) {
+            imx_rngc_do_reset(s);
+        }
+
+        /*
+         * For now, both CLR_ERR and CLR_INT clear the interrupt. We
+         * don't report any errors yet.
+         */
+        if (value & (RNGC_CMD_BIT_CLR_ERR | RNGC_CMD_BIT_CLR_INT)) {
+            qemu_irq_lower(s->irq);
+        }
+
+        if (value & RNGC_CMD_BIT_SEED) {
+            s->op_seed = OP_RUN;
+            qemu_bh_schedule(s->seed_bh);
+        }
+
+        if (value & RNGC_CMD_BIT_SELF_TEST) {
+            s->op_self_test = OP_RUN;
+            qemu_bh_schedule(s->self_test_bh);
+        }
+        break;
+
+    case RNGC_CONTROL:
+        /*
+         * The CTL_ACC and VERIF_MODE bits are not supported yet.
+         * We ignore them if they're set by the caller.
+         */
+
+        if (value & RNGC_CTRL_BIT_MASK_ERR) {
+            s->mask |= RNGC_CTRL_BIT_MASK_ERR;
+        } else {
+            s->mask &= ~RNGC_CTRL_BIT_MASK_ERR;
+        }
+
+        if (value & RNGC_CTRL_BIT_MASK_DONE) {
+            s->mask |= RNGC_CTRL_BIT_MASK_DONE;
+        } else {
+            s->mask &= ~RNGC_CTRL_BIT_MASK_DONE;
+        }
+
+        if (value & RNGC_CTRL_BIT_AUTO_SEED) {
+            s->auto_seed = true;
+        } else {
+            s->auto_seed = false;
+        }
+        break;
+    }
+}
+
+static const MemoryRegionOps imx_rngc_ops = {
+    .read  = imx_rngc_read,
+    .write = imx_rngc_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void imx_rngc_self_test(void *opaque)
+{
+    IMXRNGCState *s = IMX_RNGC(opaque);
+
+    s->op_self_test = OP_DONE;
+    if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
+        qemu_irq_raise(s->irq);
+    }
+}
+
+static void imx_rngc_seed(void *opaque)
+{
+    IMXRNGCState *s = IMX_RNGC(opaque);
+
+    s->op_seed = OP_DONE;
+    if (!(s->mask & RNGC_CTRL_BIT_MASK_DONE)) {
+        qemu_irq_raise(s->irq);
+    }
+}
+
+static void imx_rngc_realize(DeviceState *dev, Error **errp)
+{
+    IMXRNGCState *s = IMX_RNGC(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &imx_rngc_ops, s,
+                          TYPE_IMX_RNGC, 0x1000);
+    sysbus_init_mmio(sbd, &s->iomem);
+
+    sysbus_init_irq(sbd, &s->irq);
+    s->self_test_bh = qemu_bh_new(imx_rngc_self_test, s);
+    s->seed_bh = qemu_bh_new(imx_rngc_seed, s);
+}
+
+static void imx_rngc_reset(DeviceState *dev)
+{
+    IMXRNGCState *s = IMX_RNGC(dev);
+
+    imx_rngc_do_reset(s);
+}
+
+static const VMStateDescription vmstate_imx_rngc = {
+    .name = RNGC_NAME,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(op_self_test, IMXRNGCState),
+        VMSTATE_UINT8(op_seed, IMXRNGCState),
+        VMSTATE_UINT8(mask, IMXRNGCState),
+        VMSTATE_BOOL(auto_seed, IMXRNGCState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void imx_rngc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = imx_rngc_realize;
+    dc->reset = imx_rngc_reset;
+    dc->desc = RNGC_NAME,
+    dc->vmsd = &vmstate_imx_rngc;
+}
+
+static const TypeInfo imx_rngc_info = {
+    .name          = TYPE_IMX_RNGC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IMXRNGCState),
+    .class_init    = imx_rngc_class_init,
+};
+
+static void imx_rngc_register_types(void)
+{
+    type_register_static(&imx_rngc_info);
+}
+
+type_init(imx_rngc_register_types)
-- 
2.20.1

From: Jeff Kubascik <jeff.kubascik@dornerworks.com>

The wfi instruction can be configured to be trapped by a higher exception
level, such as the EL2 hypervisor. When the instruction is trapped, the
program counter should contain the address of the wfi instruction that
caused the exception. The program counter is adjusted for this in the wfi op
helper function.

However, this correction is done to env->pc, which only applies to AArch64
mode. For AArch32, the program counter is stored in env->regs[15]. This
adds an if-else statement to modify the correct program counter location
based on the the current CPU mode.

Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/op_helper.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
     }
 
     if (target_el) {
-        env->pc -= insn_len;
+        if (env->aarch64) {
+            env->pc -= insn_len;
+        } else {
+            env->regs[15] -= insn_len;
+        }
+
         raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
                         target_el);
     }
-- 
2.20.1

From: Jeff Kubascik <jeff.kubascik@dornerworks.com>

The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
register activates the highest priority pending interrupt and provides its
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
state - this change makes sure the virtual irq state is updated.

Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
 
     trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
                              gicv3_redist_affid(cs), intid);
+
+    gicv3_cpuif_virt_update(cs);
+
     return intid;
 }
 
-- 
2.20.1

From: Jeff Kubascik <jeff.kubascik@dornerworks.com>

The IL bit is set for 32-bit instructions, thus passing false
with the is_16bit parameter to syn_data_abort_with_iss() makes
a syn mask that always has the IL bit set.

Pass is_16bit as true to make the initial syn mask have IL=0,
so that the final IL value comes from or'ing template_syn.

Cc: qemu-stable@nongnu.org
Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts")
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200117004618.2742-2-richard.henderson@linaro.org
[rth: Extracted this as a self-contained bug fix from a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tlb_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
         syn = syn_data_abort_with_iss(same_el,
                                       0, 0, 0, 0, 0,
                                       ea, 0, s1ptw, is_write, fsc,
-                                      false);
+                                      true);
         /* Merge the runtime syndrome with the template syndrome.  */
         syn |= template_syn;
     }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

During the conversion to decodetree, the setting of
ISSIs16Bit got lost.  This causes the guest os to
incorrectly adjust trapping memory operations.

Cc: qemu-stable@nongnu.org
Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200117004618.2742-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
     /* ISS not valid if writeback */
     if (p && !w) {
         ret = rd;
+        if (s->base.pc_next - s->pc_curr == 2) {
+            ret |= ISSIs16Bit;
+        }
     } else {
         ret = ISSInvalid;
     }
-- 
2.20.1