1 | Arm patch queue -- these are all bug fix patches but we might | 1 | target-arm queue for rc2. This has 3 Arm related bug fixes, |
---|---|---|---|
2 | as well put them in to rc0... | 2 | and a couple of non-arm patches which don't have an obviously |
3 | better route into the tree. | ||
3 | 4 | ||
4 | thanks | 5 | thanks |
5 | -- PMM | 6 | -- PMM |
6 | 7 | ||
7 | The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be: | 8 | The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b: |
8 | 9 | ||
9 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000) | 10 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100) |
10 | 11 | ||
11 | are available in the Git repository at: | 12 | are available in the Git repository at: |
12 | 13 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722 |
14 | 15 | ||
15 | for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6: | 16 | for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e: |
16 | 17 | ||
17 | hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000) | 18 | contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100) |
18 | 19 | ||
19 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
20 | target-arm queue: | 21 | target-arm queue: |
21 | * fsl-imx6: Fix incorrect Ethernet interrupt defines | 22 | * target/arm: Add missing break statement for Hypervisor Trap Exception |
22 | * dump: Update correct kdump phys_base field for AArch64 | 23 | (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC) |
23 | * char: i.MX: Add support for "TX complete" interrupt | 24 | * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code |
24 | * bcm2836/raspi: Fix various bugs resulting in panics trying | 25 | * target/arm: Limit ID register assertions to TCG |
25 | to boot a Debian Linux kernel on raspi3 | 26 | * configure: Clarify URL to source downloads |
27 | * contrib/elf2dmp: Build download.o with CURL_CFLAGS | ||
26 | 28 | ||
27 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
28 | Andrey Smirnov (2): | 30 | Peter Maydell (4): |
29 | char: i.MX: Simplify imx_update() | 31 | hw/arm/fsl-imx6ul.c: Remove dead SMP-related code |
30 | char: i.MX: Add support for "TX complete" interrupt | 32 | target/arm: Limit ID register assertions to TCG |
33 | configure: Clarify URL to source downloads | ||
34 | contrib/elf2dmp: Build download.o with CURL_CFLAGS | ||
31 | 35 | ||
32 | Guenter Roeck (1): | 36 | Philippe Mathieu-Daudé (1): |
33 | fsl-imx6: Swap Ethernet interrupt defines | 37 | target/arm: Add missing break statement for Hypervisor Trap Exception |
34 | 38 | ||
35 | Peter Maydell (9): | 39 | configure | 2 +- |
36 | hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 | 40 | Makefile | 1 - |
37 | hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 | 41 | contrib/elf2dmp/Makefile.objs | 3 +++ |
38 | hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE | 42 | include/hw/arm/fsl-imx6ul.h | 2 +- |
39 | hw/arm/bcm2386: Fix parent type of bcm2386 | 43 | hw/arm/fsl-imx6ul.c | 62 +++++++++++++------------------------------ |
40 | hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x | 44 | hw/arm/mcimx6ul-evk.c | 2 +- |
41 | hw/arm/bcm2836: Create proper bcm2837 device | 45 | target/arm/cpu.c | 7 +++-- |
42 | hw/arm/bcm2836: Use correct affinity values for BCM2837 | 46 | target/arm/helper.c | 1 + |
43 | hw/arm/bcm2836: Hardcode correct CPU type | 47 | 8 files changed, 30 insertions(+), 50 deletions(-) |
44 | hw/arm/raspi: Provide spin-loop code for AArch64 CPUs | ||
45 | 48 | ||
46 | Wei Huang (1): | ||
47 | dump: Update correct kdump phys_base field for AArch64 | ||
48 | |||
49 | include/hw/arm/bcm2836.h | 31 +++++++++++++--- | ||
50 | include/hw/arm/fsl-imx6.h | 4 +- | ||
51 | include/hw/char/imx_serial.h | 3 ++ | ||
52 | dump.c | 14 +++++-- | ||
53 | hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++------------- | ||
54 | hw/arm/boot.c | 12 ++++++ | ||
55 | hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++-------- | ||
56 | hw/char/imx_serial.c | 44 ++++++++++++++++------ | ||
57 | hw/net/imx_fec.c | 28 +++++++++++++- | ||
58 | 9 files changed, 237 insertions(+), 63 deletions(-) | ||
59 | diff view generated by jsdifflib |
1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Code of imx_update() is slightly confusing since the "flags" variable | 3 | Reported by GCC9 when building with -Wimplicit-fallthrough=2: |
4 | doesn't really corespond to anything in real hardware and server as a | ||
5 | kitchensink accumulating events normally reported via USR1 and USR2 | ||
6 | registers. | ||
7 | 4 | ||
8 | Change the code to explicitly evaluate state of interrupts reported | 5 | target/arm/helper.c: In function ‘arm_cpu_do_interrupt_aarch32_hyp’: |
9 | via USR1 and USR2 against corresponding masking bits and use the to | 6 | target/arm/helper.c:7958:14: error: this statement may fall through [-Werror=implicit-fallthrough=] |
10 | detemine if IRQ line should be asserted or not. | 7 | 7958 | addr = 0x14; |
8 | | ~~~~~^~~~~~ | ||
9 | target/arm/helper.c:7959:5: note: here | ||
10 | 7959 | default: | ||
11 | | ^~~~~~~ | ||
12 | cc1: all warnings being treated as errors | ||
11 | 13 | ||
12 | NOTE: Check for UTS1_TXEMPTY being set has been dropped for two | 14 | Fixes: b9bc21ff9f9 |
13 | reasons: | 15 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
14 | 16 | Reported-by: Stefan Weil <sw@weilnetz.de> | |
15 | 1. Emulation code implements a single character FIFO, so this flag | ||
16 | will always be set since characters are trasmitted as a part of | ||
17 | the code emulating "push" into the FIFO | ||
18 | |||
19 | 2. imx_update() is really just a function doing ORing and maksing | ||
20 | of reported events, so checking for UTS1_TXEMPTY should happen, | ||
21 | if it's ever really needed should probably happen outside of | ||
22 | it. | ||
23 | |||
24 | Cc: qemu-devel@nongnu.org | ||
25 | Cc: qemu-arm@nongnu.org | ||
26 | Cc: Bill Paul <wpaul@windriver.com> | ||
27 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
28 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
29 | Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com | ||
30 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Message-id: 20190719111451.12406-1-philmd@redhat.com | ||
31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
32 | --- | 20 | --- |
33 | hw/char/imx_serial.c | 24 ++++++++++++++++-------- | 21 | target/arm/helper.c | 1 + |
34 | 1 file changed, 16 insertions(+), 8 deletions(-) | 22 | 1 file changed, 1 insertion(+) |
35 | 23 | ||
36 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | 24 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
37 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/hw/char/imx_serial.c | 26 | --- a/target/arm/helper.c |
39 | +++ b/hw/char/imx_serial.c | 27 | +++ b/target/arm/helper.c |
40 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { | 28 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
41 | 29 | break; | |
42 | static void imx_update(IMXSerialState *s) | 30 | case EXCP_HYP_TRAP: |
43 | { | 31 | addr = 0x14; |
44 | - uint32_t flags; | 32 | + break; |
45 | + uint32_t usr1; | 33 | default: |
46 | + uint32_t usr2; | 34 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
47 | + uint32_t mask; | 35 | } |
48 | |||
49 | - flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY); | ||
50 | - if (s->ucr1 & UCR1_TXMPTYEN) { | ||
51 | - flags |= (s->uts1 & UTS1_TXEMPTY); | ||
52 | - } else { | ||
53 | - flags &= ~USR1_TRDY; | ||
54 | - } | ||
55 | + /* | ||
56 | + * Lucky for us TRDY and RRDY has the same offset in both USR1 and | ||
57 | + * UCR1, so we can get away with something as simple as the | ||
58 | + * following: | ||
59 | + */ | ||
60 | + usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); | ||
61 | + /* | ||
62 | + * Bits that we want in USR2 are not as conveniently laid out, | ||
63 | + * unfortunately. | ||
64 | + */ | ||
65 | + mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | ||
66 | + usr2 = s->usr2 & mask; | ||
67 | |||
68 | - qemu_set_irq(s->irq, !!flags); | ||
69 | + qemu_set_irq(s->irq, usr1 || usr2); | ||
70 | } | ||
71 | |||
72 | static void imx_serial_reset(IMXSerialState *s) | ||
73 | -- | 36 | -- |
74 | 2.16.2 | 37 | 2.20.1 |
75 | 38 | ||
76 | 39 | diff view generated by jsdifflib |
1 | Now we have separate types for BCM2386 and BCM2387, we might as well | 1 | The i.MX6UL always has a single Cortex-A7 CPU (we set FSL_IMX6UL_NUM_CPUS |
---|---|---|---|
2 | just hard-code the CPU type they use rather than having it passed | 2 | to 1 in line with this). This means that all the code in fsl-imx6ul.c to |
3 | through as an object property. This then lets us put the initialization | 3 | handle multiple CPUs is dead code, and Coverity is now complaining that |
4 | of the CPU object in init rather than realize. | 4 | it is unreachable (CID 1403008, 1403011). |
5 | 5 | ||
6 | Note that this change means that it's no longer possible on | 6 | Remove the unreachable code and the only-executes-once loops, |
7 | the command line to use -cpu to ask for a different kind of | 7 | and replace the single-entry cpu[] array in the FSLIMX6ULState |
8 | CPU than the SoC supports. This was never a supported thing to | 8 | with a simple cpu member. |
9 | do anyway; we were just not sanity-checking the command line. | ||
10 | |||
11 | This does require us to only build the bcm2837 object on | ||
12 | TARGET_AARCH64 configs, since otherwise it won't instantiate | ||
13 | due to the missing cortex-a53 device and "make check" will fail. | ||
14 | 9 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
17 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 12 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
18 | Message-id: 20180313153458.26822-9-peter.maydell@linaro.org | 13 | Message-id: 20190712115030.26895-1-peter.maydell@linaro.org |
19 | --- | 14 | --- |
20 | hw/arm/bcm2836.c | 24 +++++++++++++++--------- | 15 | include/hw/arm/fsl-imx6ul.h | 2 +- |
21 | hw/arm/raspi.c | 2 -- | 16 | hw/arm/fsl-imx6ul.c | 62 +++++++++++-------------------------- |
22 | 2 files changed, 15 insertions(+), 11 deletions(-) | 17 | hw/arm/mcimx6ul-evk.c | 2 +- |
18 | 3 files changed, 20 insertions(+), 46 deletions(-) | ||
23 | 19 | ||
24 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | 20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
25 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/arm/bcm2836.c | 22 | --- a/include/hw/arm/fsl-imx6ul.h |
27 | +++ b/hw/arm/bcm2836.c | 23 | +++ b/include/hw/arm/fsl-imx6ul.h |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState { | ||
25 | DeviceState parent_obj; | ||
26 | |||
27 | /*< public >*/ | ||
28 | - ARMCPU cpu[FSL_IMX6UL_NUM_CPUS]; | ||
29 | + ARMCPU cpu; | ||
30 | A15MPPrivState a7mpcore; | ||
31 | IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS]; | ||
32 | IMXEPITState epit[FSL_IMX6UL_NUM_EPITS]; | ||
33 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/arm/fsl-imx6ul.c | ||
36 | +++ b/hw/arm/fsl-imx6ul.c | ||
28 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
29 | 38 | ||
30 | struct BCM283XInfo { | 39 | static void fsl_imx6ul_init(Object *obj) |
31 | const char *name; | ||
32 | + const char *cpu_type; | ||
33 | int clusterid; | ||
34 | }; | ||
35 | |||
36 | static const BCM283XInfo bcm283x_socs[] = { | ||
37 | { | ||
38 | .name = TYPE_BCM2836, | ||
39 | + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), | ||
40 | .clusterid = 0xf, | ||
41 | }, | ||
42 | +#ifdef TARGET_AARCH64 | ||
43 | { | ||
44 | .name = TYPE_BCM2837, | ||
45 | + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), | ||
46 | .clusterid = 0x0, | ||
47 | }, | ||
48 | +#endif | ||
49 | }; | ||
50 | |||
51 | static void bcm2836_init(Object *obj) | ||
52 | { | 40 | { |
53 | BCM283XState *s = BCM283X(obj); | 41 | - MachineState *ms = MACHINE(qdev_get_machine()); |
54 | + BCM283XClass *bc = BCM283X_GET_CLASS(obj); | 42 | FslIMX6ULState *s = FSL_IMX6UL(obj); |
55 | + const BCM283XInfo *info = bc->info; | 43 | char name[NAME_SIZE]; |
56 | + int n; | 44 | int i; |
57 | + | 45 | |
58 | + for (n = 0; n < BCM283X_NCPUS; n++) { | 46 | - for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6UL_NUM_CPUS); i++) { |
59 | + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | 47 | - snprintf(name, NAME_SIZE, "cpu%d", i); |
60 | + info->cpu_type); | 48 | - object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), |
61 | + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | 49 | - "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); |
62 | + &error_abort); | ||
63 | + } | ||
64 | |||
65 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | ||
66 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | ||
67 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
68 | |||
69 | /* common peripherals from bcm2835 */ | ||
70 | |||
71 | - obj = OBJECT(dev); | ||
72 | - for (n = 0; n < BCM283X_NCPUS; n++) { | ||
73 | - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
74 | - s->cpu_type); | ||
75 | - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
76 | - &error_abort); | ||
77 | - } | 50 | - } |
51 | + object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu), | ||
52 | + "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); | ||
53 | |||
54 | /* | ||
55 | * A7MPCORE | ||
56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
57 | MachineState *ms = MACHINE(qdev_get_machine()); | ||
58 | FslIMX6ULState *s = FSL_IMX6UL(dev); | ||
59 | int i; | ||
60 | - qemu_irq irq; | ||
61 | char name[NAME_SIZE]; | ||
62 | - unsigned int smp_cpus = ms->smp.cpus; | ||
63 | + SysBusDevice *sbd; | ||
64 | + DeviceState *d; | ||
65 | |||
66 | - if (smp_cpus > FSL_IMX6UL_NUM_CPUS) { | ||
67 | - error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", | ||
68 | - TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus); | ||
69 | + if (ms->smp.cpus > 1) { | ||
70 | + error_setg(errp, "%s: Only a single CPU is supported (%d requested)", | ||
71 | + TYPE_FSL_IMX6UL, ms->smp.cpus); | ||
72 | return; | ||
73 | } | ||
74 | |||
75 | - for (i = 0; i < smp_cpus; i++) { | ||
76 | - Object *o = OBJECT(&s->cpu[i]); | ||
78 | - | 77 | - |
79 | obj = object_property_get_link(OBJECT(dev), "ram", &err); | 78 | - object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, |
80 | if (obj == NULL) { | 79 | - "psci-conduit", &error_abort); |
81 | error_setg(errp, "%s: required ram link not found: %s", | 80 | - |
82 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | 81 | - /* On uniprocessor, the CBAR is set to 0 */ |
82 | - if (smp_cpus > 1) { | ||
83 | - object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR, | ||
84 | - "reset-cbar", &error_abort); | ||
85 | - } | ||
86 | - | ||
87 | - if (i) { | ||
88 | - /* Secondary CPUs start in PSCI powered-down state */ | ||
89 | - object_property_set_bool(o, true, | ||
90 | - "start-powered-off", &error_abort); | ||
91 | - } | ||
92 | - | ||
93 | - object_property_set_bool(o, true, "realized", &error_abort); | ||
94 | - } | ||
95 | + object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC, | ||
96 | + "psci-conduit", &error_abort); | ||
97 | + object_property_set_bool(OBJECT(&s->cpu), true, | ||
98 | + "realized", &error_abort); | ||
99 | |||
100 | /* | ||
101 | * A7MPCORE | ||
102 | */ | ||
103 | - object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", | ||
104 | - &error_abort); | ||
105 | + object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort); | ||
106 | object_property_set_int(OBJECT(&s->a7mpcore), | ||
107 | FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, | ||
108 | "num-irq", &error_abort); | ||
109 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
110 | &error_abort); | ||
111 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); | ||
112 | |||
113 | - for (i = 0; i < smp_cpus; i++) { | ||
114 | - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | ||
115 | - DeviceState *d = DEVICE(qemu_get_cpu(i)); | ||
116 | + sbd = SYS_BUS_DEVICE(&s->a7mpcore); | ||
117 | + d = DEVICE(&s->cpu); | ||
118 | |||
119 | - irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | ||
120 | - sysbus_connect_irq(sbd, i, irq); | ||
121 | - sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ)); | ||
122 | - sysbus_connect_irq(sbd, i + 2 * smp_cpus, | ||
123 | - qdev_get_gpio_in(d, ARM_CPU_VIRQ)); | ||
124 | - sysbus_connect_irq(sbd, i + 3 * smp_cpus, | ||
125 | - qdev_get_gpio_in(d, ARM_CPU_VFIQ)); | ||
126 | - } | ||
127 | + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); | ||
128 | + sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); | ||
129 | + sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); | ||
130 | + sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); | ||
131 | |||
132 | /* | ||
133 | * A7MPCORE DAP | ||
134 | diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/hw/arm/mcimx6ul-evk.c | ||
137 | +++ b/hw/arm/mcimx6ul-evk.c | ||
138 | @@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine) | ||
139 | } | ||
140 | |||
141 | if (!qtest_enabled()) { | ||
142 | - arm_load_kernel(&s->soc.cpu[0], &boot_info); | ||
143 | + arm_load_kernel(&s->soc.cpu, &boot_info); | ||
144 | } | ||
83 | } | 145 | } |
84 | 146 | ||
85 | static Property bcm2836_props[] = { | ||
86 | - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), | ||
87 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, | ||
88 | BCM283X_NCPUS), | ||
89 | DEFINE_PROP_END_OF_LIST() | ||
90 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/hw/arm/raspi.c | ||
93 | +++ b/hw/arm/raspi.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
95 | /* Setup the SOC */ | ||
96 | object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), | ||
97 | &error_abort); | ||
98 | - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", | ||
99 | - &error_abort); | ||
100 | object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", | ||
101 | &error_abort); | ||
102 | int board_rev = version == 3 ? 0xa02082 : 0xa21041; | ||
103 | -- | 147 | -- |
104 | 2.16.2 | 148 | 2.20.1 |
105 | 149 | ||
106 | 150 | diff view generated by jsdifflib |
1 | From: Wei Huang <wei@redhat.com> | 1 | In arm_cpu_realizefn() we make several assertions about the values of |
---|---|---|---|
2 | guest ID registers: | ||
3 | * if the CPU provides AArch32 v7VE or better it must advertise the | ||
4 | ARM_DIV feature | ||
5 | * if the CPU provides AArch32 A-profile v6 or better it must | ||
6 | advertise the Jazelle feature | ||
2 | 7 | ||
3 | For guest kernel that supports KASLR, the load address can change every | 8 | These are essentially consistency checks that our ID register |
4 | time when guest VM runs. To find the physical base address correctly, | 9 | specifications in cpu.c didn't accidentally miss out a feature, |
5 | current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=". | 10 | because increasingly the TCG emulation gates features on the values |
6 | However this string pattern is only available on x86_64. AArch64 uses a | 11 | in ID registers rather than using old-style checks of ARM_FEATURE_FOO |
7 | different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure | 12 | bits. |
8 | QEMU dump uses the correct string on AArch64. | ||
9 | 13 | ||
10 | Signed-off-by: Wei Huang <wei@redhat.com> | 14 | Unfortunately, these asserts can cause problems if we're running KVM, |
11 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> | 15 | because in that case we don't control the values of the ID registers |
12 | Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com | 16 | -- we read them from the host kernel. In particular, if the host |
17 | kernel is older than 4.15 then it doesn't expose the ID registers via | ||
18 | the KVM_GET_ONE_REG ioctl, and we set up dummy values for some | ||
19 | registers and leave the rest at zero. (See the comment in | ||
20 | target/arm/kvm64.c kvm_arm_get_host_cpu_features().) This set of | ||
21 | dummy values is not sufficient to pass our assertions, and so on | ||
22 | those kernels running an AArch32 guest on AArch64 will assert. | ||
23 | |||
24 | We could provide a more sophisticated set of dummy ID registers in | ||
25 | this case, but that still leaves the possibility of a host CPU which | ||
26 | reports bogus ID register values that would cause us to assert. It's | ||
27 | more robust to only do these ID register checks if we're using TCG, | ||
28 | as that is the only case where this is truly a QEMU code bug. | ||
29 | |||
30 | Reported-by: Laszlo Ersek <lersek@redhat.com> | ||
31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
32 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
33 | Tested-by: Laszlo Ersek <lersek@redhat.com> | ||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | Message-id: 20190718125928.20147-1-peter.maydell@linaro.org | ||
36 | Fixes: https://bugs.launchpad.net/qemu/+bug/1830864 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 38 | --- |
15 | dump.c | 14 +++++++++++--- | 39 | target/arm/cpu.c | 7 +++++-- |
16 | 1 file changed, 11 insertions(+), 3 deletions(-) | 40 | 1 file changed, 5 insertions(+), 2 deletions(-) |
17 | 41 | ||
18 | diff --git a/dump.c b/dump.c | 42 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
19 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/dump.c | 44 | --- a/target/arm/cpu.c |
21 | +++ b/dump.c | 45 | +++ b/target/arm/cpu.c |
22 | @@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s) | 46 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
23 | 47 | * There exist AArch64 cpus without AArch32 support. When KVM | |
24 | lines = g_strsplit((char *)vmci, "\n", -1); | 48 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. |
25 | for (i = 0; lines[i]; i++) { | 49 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. |
26 | - if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) { | 50 | + * As a general principle, we also do not make ID register |
27 | - if (qemu_strtou64(lines[i] + 18, NULL, 16, | 51 | + * consistency checks anywhere unless using TCG, because only |
28 | + const char *prefix = NULL; | 52 | + * for TCG would a consistency-check failure be a QEMU bug. |
29 | + | 53 | */ |
30 | + if (s->dump_info.d_machine == EM_X86_64) { | 54 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
31 | + prefix = "NUMBER(phys_base)="; | 55 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); |
32 | + } else if (s->dump_info.d_machine == EM_AARCH64) { | 56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
33 | + prefix = "NUMBER(PHYS_OFFSET)="; | 57 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the |
34 | + } | 58 | * Security Extensions is ARM_FEATURE_EL3. |
35 | + | 59 | */ |
36 | + if (prefix && g_str_has_prefix(lines[i], prefix)) { | 60 | - assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); |
37 | + if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16, | 61 | + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); |
38 | &phys_base) < 0) { | 62 | set_feature(env, ARM_FEATURE_LPAE); |
39 | - warn_report("Failed to read NUMBER(phys_base)="); | 63 | set_feature(env, ARM_FEATURE_V7); |
40 | + warn_report("Failed to read %s", prefix); | 64 | } |
41 | } else { | 65 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
42 | s->dump_info.phys_base = phys_base; | 66 | if (arm_feature(env, ARM_FEATURE_V6)) { |
43 | } | 67 | set_feature(env, ARM_FEATURE_V5); |
68 | if (!arm_feature(env, ARM_FEATURE_M)) { | ||
69 | - assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); | ||
70 | + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); | ||
71 | set_feature(env, ARM_FEATURE_AUXCR); | ||
72 | } | ||
73 | } | ||
44 | -- | 74 | -- |
45 | 2.16.2 | 75 | 2.20.1 |
46 | 76 | ||
47 | 77 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | If configure detects that it's being run on a source tree which |
---|---|---|---|
2 | is missing git modules, it prints an error messages suggesting | ||
3 | that the user downloads a correct source archive from the project | ||
4 | website. However https://www.qemu.org/download/ is a link to a | ||
5 | page with multiple tabs, with the default being the one telling | ||
6 | users how to get binaries from their distro. Clarify the URL | ||
7 | we print to include the #source anchor, so that the browser will | ||
8 | go directly to the source-tarball instructions. | ||
2 | 9 | ||
3 | The sabrelite machine model used by qemu-system-arm is based on the | 10 | Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
4 | Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet | 11 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
5 | controller which is supported in QEMU using the imx_fec.c module | 12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
6 | (actually called imx.enet for this model.) | 13 | Reviewed-by: Stefan Weil <sw@weilnetz.de> |
7 | 14 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | |
8 | The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | imx.enet device like this: | 16 | Message-id: 20190718131659.20783-1-peter.maydell@linaro.org |
10 | 17 | Suggested-by: Stefan Weil <sw@weilnetz.de> | |
11 | #define FSL_IMX6_ENET_MAC_1588_IRQ 118 | ||
12 | #define FSL_IMX6_ENET_MAC_IRQ 119 | ||
13 | |||
14 | According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf, | ||
15 | page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary, | ||
16 | interrupts are as follows. | ||
17 | |||
18 | 150 ENET MAC 0 IRQ | ||
19 | 151 ENET MAC 0 1588 Timer interrupt | ||
20 | |||
21 | where | ||
22 | |||
23 | 150 - 32 == 118 | ||
24 | 151 - 32 == 119 | ||
25 | |||
26 | In other words, the vector definitions in the fsl-imx6.h file are reversed. | ||
27 | |||
28 | Fixing the interrupts alone causes problems with older Linux kernels: | ||
29 | The Ethernet interface will fail to probe with Linux v4.9 and earlier. | ||
30 | Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe | ||
31 | error handling. This is a Linux kernel problem, not a qemu problem: | ||
32 | the Linux kernel only worked by accident since it requested both interrupts. | ||
33 | |||
34 | For backward compatibility, generate the Ethernet interrupt on both interrupt | ||
35 | lines. This was shown to work from all Linux kernel releases starting with | ||
36 | v3.16. | ||
37 | |||
38 | Link: https://bugs.launchpad.net/qemu/+bug/1753309 | ||
39 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
40 | Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net | ||
41 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
42 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
43 | --- | 19 | --- |
44 | include/hw/arm/fsl-imx6.h | 4 ++-- | 20 | configure | 2 +- |
45 | hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++- | 21 | 1 file changed, 1 insertion(+), 1 deletion(-) |
46 | 2 files changed, 29 insertions(+), 3 deletions(-) | ||
47 | 22 | ||
48 | diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h | 23 | diff --git a/configure b/configure |
49 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100755 |
50 | --- a/include/hw/arm/fsl-imx6.h | 25 | --- a/configure |
51 | +++ b/include/hw/arm/fsl-imx6.h | 26 | +++ b/configure |
52 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State { | 27 | @@ -XXX,XX +XXX,XX @@ else |
53 | #define FSL_IMX6_HDMI_MASTER_IRQ 115 | 28 | echo "to acquire QEMU source archives. Non-GIT builds are only" |
54 | #define FSL_IMX6_HDMI_CEC_IRQ 116 | 29 | echo "supported with source archives linked from:" |
55 | #define FSL_IMX6_MLB150_LOW_IRQ 117 | 30 | echo |
56 | -#define FSL_IMX6_ENET_MAC_1588_IRQ 118 | 31 | - echo " https://www.qemu.org/download/" |
57 | -#define FSL_IMX6_ENET_MAC_IRQ 119 | 32 | + echo " https://www.qemu.org/download/#source" |
58 | +#define FSL_IMX6_ENET_MAC_IRQ 118 | 33 | echo |
59 | +#define FSL_IMX6_ENET_MAC_1588_IRQ 119 | 34 | echo "Developers working with GIT can use scripts/archive-source.sh" |
60 | #define FSL_IMX6_PCIE1_IRQ 120 | 35 | echo "if they need to create valid source archives." |
61 | #define FSL_IMX6_PCIE2_IRQ 121 | ||
62 | #define FSL_IMX6_PCIE3_IRQ 122 | ||
63 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/net/imx_fec.c | ||
66 | +++ b/hw/net/imx_fec.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) | ||
68 | |||
69 | static void imx_eth_update(IMXFECState *s) | ||
70 | { | ||
71 | - if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) { | ||
72 | + /* | ||
73 | + * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER | ||
74 | + * interrupts swapped. This worked with older versions of Linux (4.14 | ||
75 | + * and older) since Linux associated both interrupt lines with Ethernet | ||
76 | + * MAC interrupts. Specifically, | ||
77 | + * - Linux 4.15 and later have separate interrupt handlers for the MAC and | ||
78 | + * timer interrupts. Those versions of Linux fail with versions of QEMU | ||
79 | + * with swapped interrupt assignments. | ||
80 | + * - In linux 4.14, both interrupt lines were registered with the Ethernet | ||
81 | + * MAC interrupt handler. As a result, all versions of qemu happen to | ||
82 | + * work, though that is accidental. | ||
83 | + * - In Linux 4.9 and older, the timer interrupt was registered directly | ||
84 | + * with the Ethernet MAC interrupt handler. The MAC interrupt was | ||
85 | + * redirected to a GPIO interrupt to work around erratum ERR006687. | ||
86 | + * This was implemented using the SOC's IOMUX block. In qemu, this GPIO | ||
87 | + * interrupt never fired since IOMUX is currently not supported in qemu. | ||
88 | + * Linux instead received MAC interrupts on the timer interrupt. | ||
89 | + * As a result, qemu versions with the swapped interrupt assignment work, | ||
90 | + * albeit accidentally, but qemu versions with the correct interrupt | ||
91 | + * assignment fail. | ||
92 | + * | ||
93 | + * To ensure that all versions of Linux work, generate ENET_INT_MAC | ||
94 | + * interrrupts on both interrupt lines. This should be changed if and when | ||
95 | + * qemu supports IOMUX. | ||
96 | + */ | ||
97 | + if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & | ||
98 | + (ENET_INT_MAC | ENET_INT_TS_TIMER)) { | ||
99 | qemu_set_irq(s->irq[1], 1); | ||
100 | } else { | ||
101 | qemu_set_irq(s->irq[1], 0); | ||
102 | -- | 36 | -- |
103 | 2.16.2 | 37 | 2.20.1 |
104 | 38 | ||
105 | 39 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
2 | 1 | ||
3 | Add support for "TX complete"/TXDC interrupt generate by real HW since | ||
4 | it is needed to support guests other than Linux. | ||
5 | |||
6 | Based on the patch by Bill Paul as found here: | ||
7 | https://bugs.launchpad.net/qemu/+bug/1753314 | ||
8 | |||
9 | Cc: qemu-devel@nongnu.org | ||
10 | Cc: qemu-arm@nongnu.org | ||
11 | Cc: Bill Paul <wpaul@windriver.com> | ||
12 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Bill Paul <wpaul@windriver.com> | ||
14 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
15 | Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | include/hw/char/imx_serial.h | 3 +++ | ||
20 | hw/char/imx_serial.c | 20 +++++++++++++++++--- | ||
21 | 2 files changed, 20 insertions(+), 3 deletions(-) | ||
22 | |||
23 | diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/include/hw/char/imx_serial.h | ||
26 | +++ b/include/hw/char/imx_serial.h | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | #define UCR2_RXEN (1<<1) /* Receiver enable */ | ||
29 | #define UCR2_SRST (1<<0) /* Reset complete */ | ||
30 | |||
31 | +#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ | ||
32 | + | ||
33 | #define UTS1_TXEMPTY (1<<6) | ||
34 | #define UTS1_RXEMPTY (1<<5) | ||
35 | #define UTS1_TXFULL (1<<4) | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState { | ||
37 | uint32_t ubmr; | ||
38 | uint32_t ubrc; | ||
39 | uint32_t ucr3; | ||
40 | + uint32_t ucr4; | ||
41 | |||
42 | qemu_irq irq; | ||
43 | CharBackend chr; | ||
44 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/char/imx_serial.c | ||
47 | +++ b/hw/char/imx_serial.c | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | |||
50 | static const VMStateDescription vmstate_imx_serial = { | ||
51 | .name = TYPE_IMX_SERIAL, | ||
52 | - .version_id = 1, | ||
53 | - .minimum_version_id = 1, | ||
54 | + .version_id = 2, | ||
55 | + .minimum_version_id = 2, | ||
56 | .fields = (VMStateField[]) { | ||
57 | VMSTATE_INT32(readbuff, IMXSerialState), | ||
58 | VMSTATE_UINT32(usr1, IMXSerialState), | ||
59 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = { | ||
60 | VMSTATE_UINT32(ubmr, IMXSerialState), | ||
61 | VMSTATE_UINT32(ubrc, IMXSerialState), | ||
62 | VMSTATE_UINT32(ucr3, IMXSerialState), | ||
63 | + VMSTATE_UINT32(ucr4, IMXSerialState), | ||
64 | VMSTATE_END_OF_LIST() | ||
65 | }, | ||
66 | }; | ||
67 | @@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s) | ||
68 | * unfortunately. | ||
69 | */ | ||
70 | mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | ||
71 | + /* | ||
72 | + * TCEN and TXDC are both bit 3 | ||
73 | + */ | ||
74 | + mask |= s->ucr4 & UCR4_TCEN; | ||
75 | + | ||
76 | usr2 = s->usr2 & mask; | ||
77 | |||
78 | qemu_set_irq(s->irq, usr1 || usr2); | ||
79 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, | ||
80 | return s->ucr3; | ||
81 | |||
82 | case 0x23: /* UCR4 */ | ||
83 | + return s->ucr4; | ||
84 | + | ||
85 | case 0x29: /* BRM Incremental */ | ||
86 | return 0x0; /* TODO */ | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, | ||
89 | * qemu_chr_fe_write and background I/O callbacks */ | ||
90 | qemu_chr_fe_write_all(&s->chr, &ch, 1); | ||
91 | s->usr1 &= ~USR1_TRDY; | ||
92 | + s->usr2 &= ~USR2_TXDC; | ||
93 | imx_update(s); | ||
94 | s->usr1 |= USR1_TRDY; | ||
95 | + s->usr2 |= USR2_TXDC; | ||
96 | imx_update(s); | ||
97 | } | ||
98 | break; | ||
99 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset, | ||
100 | s->ucr3 = value & 0xffff; | ||
101 | break; | ||
102 | |||
103 | - case 0x2d: /* UTS1 */ | ||
104 | case 0x23: /* UCR4 */ | ||
105 | + s->ucr4 = value & 0xffff; | ||
106 | + imx_update(s); | ||
107 | + break; | ||
108 | + | ||
109 | + case 0x2d: /* UTS1 */ | ||
110 | qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%" | ||
111 | HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset); | ||
112 | /* TODO */ | ||
113 | -- | ||
114 | 2.16.2 | ||
115 | |||
116 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For the rpi1 and 2 we want to boot the Linux kernel via some | ||
2 | custom setup code that makes sure that the SMC instruction | ||
3 | acts as a no-op, because it's used for cache maintenance. | ||
4 | The rpi3 boots AArch64 kernels, which don't need SMC for | ||
5 | cache maintenance and always expect to be booted non-secure. | ||
6 | Don't fill in the aarch32-specific parts of the binfo struct. | ||
7 | 1 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Message-id: 20180313153458.26822-2-peter.maydell@linaro.org | ||
12 | --- | ||
13 | hw/arm/raspi.c | 17 +++++++++++++---- | ||
14 | 1 file changed, 13 insertions(+), 4 deletions(-) | ||
15 | |||
16 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/arm/raspi.c | ||
19 | +++ b/hw/arm/raspi.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
21 | binfo.board_id = raspi_boardid[version]; | ||
22 | binfo.ram_size = ram_size; | ||
23 | binfo.nb_cpus = smp_cpus; | ||
24 | - binfo.board_setup_addr = BOARDSETUP_ADDR; | ||
25 | - binfo.write_board_setup = write_board_setup; | ||
26 | - binfo.secure_board_setup = true; | ||
27 | - binfo.secure_boot = true; | ||
28 | + | ||
29 | + if (version <= 2) { | ||
30 | + /* The rpi1 and 2 require some custom setup code to run in Secure | ||
31 | + * mode before booting a kernel (to set up the SMC vectors so | ||
32 | + * that we get a no-op SMC; this is used by Linux to call the | ||
33 | + * firmware for some cache maintenance operations. | ||
34 | + * The rpi3 doesn't need this. | ||
35 | + */ | ||
36 | + binfo.board_setup_addr = BOARDSETUP_ADDR; | ||
37 | + binfo.write_board_setup = write_board_setup; | ||
38 | + binfo.secure_board_setup = true; | ||
39 | + binfo.secure_boot = true; | ||
40 | + } | ||
41 | |||
42 | /* Pi2 and Pi3 requires SMP setup */ | ||
43 | if (version >= 2) { | ||
44 | -- | ||
45 | 2.16.2 | ||
46 | |||
47 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add some assertions that if we're about to boot an AArch64 kernel, | ||
2 | the board code has not mistakenly set either secure_boot or | ||
3 | secure_board_setup. It doesn't make sense to set secure_boot, | ||
4 | because all AArch64 kernels must be booted in non-secure mode. | ||
5 | 1 | ||
6 | It might in theory make sense to set secure_board_setup, but | ||
7 | we don't currently support that, because only the AArch32 | ||
8 | bootloader[] code calls this hook; bootloader_aarch64[] does not. | ||
9 | Since we don't have a current need for this functionality, just | ||
10 | assert that we don't try to use it. If it's needed we'll add | ||
11 | it later. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | Message-id: 20180313153458.26822-3-peter.maydell@linaro.org | ||
16 | --- | ||
17 | hw/arm/boot.c | 7 +++++++ | ||
18 | 1 file changed, 7 insertions(+) | ||
19 | |||
20 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/arm/boot.c | ||
23 | +++ b/hw/arm/boot.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
25 | } else { | ||
26 | env->pstate = PSTATE_MODE_EL1h; | ||
27 | } | ||
28 | + /* AArch64 kernels never boot in secure mode */ | ||
29 | + assert(!info->secure_boot); | ||
30 | + /* This hook is only supported for AArch32 currently: | ||
31 | + * bootloader_aarch64[] will not call the hook, and | ||
32 | + * the code above has already dropped us into EL2 or EL1. | ||
33 | + */ | ||
34 | + assert(!info->secure_board_setup); | ||
35 | } | ||
36 | |||
37 | /* Set to non-secure if not a secure boot */ | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | If we're directly booting a Linux kernel and the CPU supports both | ||
2 | EL3 and EL2, we start the kernel in EL2, as it expects. We must also | ||
3 | set the SCR_EL3.HCE bit in this situation, so that the HVC | ||
4 | instruction is enabled rather than UNDEFing. Otherwise at least some | ||
5 | kernels will panic when trying to initialize KVM in the guest. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20180313153458.26822-4-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/arm/boot.c | 5 +++++ | ||
11 | 1 file changed, 5 insertions(+) | ||
12 | |||
13 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/boot.c | ||
16 | +++ b/hw/arm/boot.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
18 | assert(!info->secure_board_setup); | ||
19 | } | ||
20 | |||
21 | + if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
22 | + /* If we have EL2 then Linux expects the HVC insn to work */ | ||
23 | + env->cp15.scr_el3 |= SCR_HCE; | ||
24 | + } | ||
25 | + | ||
26 | /* Set to non-secure if not a secure boot */ | ||
27 | if (!info->secure_boot && | ||
28 | (cs != first_cpu || !info->secure_board_setup)) { | ||
29 | -- | ||
30 | 2.16.2 | ||
31 | |||
32 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The TypeInfo and state struct for bcm2386 disagree about what the | ||
2 | parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, | ||
3 | but the BCM2386State struct only defines the parent_obj field | ||
4 | as DeviceState. This would have caused problems if anything | ||
5 | actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. | ||
6 | Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't | ||
7 | need any of the additional functionality TYPE_SYS_BUS_DEVICE | ||
8 | provides. | ||
9 | 1 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Message-id: 20180313153458.26822-5-peter.maydell@linaro.org | ||
14 | --- | ||
15 | hw/arm/bcm2836.c | 2 +- | ||
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/arm/bcm2836.c | ||
21 | +++ b/hw/arm/bcm2836.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
23 | |||
24 | static const TypeInfo bcm2836_type_info = { | ||
25 | .name = TYPE_BCM2836, | ||
26 | - .parent = TYPE_SYS_BUS_DEVICE, | ||
27 | + .parent = TYPE_DEVICE, | ||
28 | .instance_size = sizeof(BCM2836State), | ||
29 | .instance_init = bcm2836_init, | ||
30 | .class_init = bcm2836_class_init, | ||
31 | -- | ||
32 | 2.16.2 | ||
33 | |||
34 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Our BCM2836 type is really a generic one that can be any of | ||
2 | the bcm283x family. Rename it accordingly. We change only | ||
3 | the names which are visible via the header file to the | ||
4 | rest of the QEMU code, leaving private function names | ||
5 | in bcm2836.c as they are. | ||
6 | 1 | ||
7 | This is a preliminary to making bcm283x be an abstract | ||
8 | parent class to specific types for the bcm2836 and bcm2837. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Message-id: 20180313153458.26822-6-peter.maydell@linaro.org | ||
14 | --- | ||
15 | include/hw/arm/bcm2836.h | 12 ++++++------ | ||
16 | hw/arm/bcm2836.c | 17 +++++++++-------- | ||
17 | hw/arm/raspi.c | 16 ++++++++-------- | ||
18 | 3 files changed, 23 insertions(+), 22 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/arm/bcm2836.h | ||
23 | +++ b/include/hw/arm/bcm2836.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "hw/arm/bcm2835_peripherals.h" | ||
26 | #include "hw/intc/bcm2836_control.h" | ||
27 | |||
28 | -#define TYPE_BCM2836 "bcm2836" | ||
29 | -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) | ||
30 | +#define TYPE_BCM283X "bcm283x" | ||
31 | +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) | ||
32 | |||
33 | -#define BCM2836_NCPUS 4 | ||
34 | +#define BCM283X_NCPUS 4 | ||
35 | |||
36 | -typedef struct BCM2836State { | ||
37 | +typedef struct BCM283XState { | ||
38 | /*< private >*/ | ||
39 | DeviceState parent_obj; | ||
40 | /*< public >*/ | ||
41 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State { | ||
42 | char *cpu_type; | ||
43 | uint32_t enabled_cpus; | ||
44 | |||
45 | - ARMCPU cpus[BCM2836_NCPUS]; | ||
46 | + ARMCPU cpus[BCM283X_NCPUS]; | ||
47 | BCM2836ControlState control; | ||
48 | BCM2835PeripheralState peripherals; | ||
49 | -} BCM2836State; | ||
50 | +} BCM283XState; | ||
51 | |||
52 | #endif /* BCM2836_H */ | ||
53 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/arm/bcm2836.c | ||
56 | +++ b/hw/arm/bcm2836.c | ||
57 | @@ -XXX,XX +XXX,XX @@ | ||
58 | |||
59 | static void bcm2836_init(Object *obj) | ||
60 | { | ||
61 | - BCM2836State *s = BCM2836(obj); | ||
62 | + BCM283XState *s = BCM283X(obj); | ||
63 | |||
64 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | ||
65 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | ||
66 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) | ||
67 | |||
68 | static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
69 | { | ||
70 | - BCM2836State *s = BCM2836(dev); | ||
71 | + BCM283XState *s = BCM283X(dev); | ||
72 | Object *obj; | ||
73 | Error *err = NULL; | ||
74 | int n; | ||
75 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
76 | /* common peripherals from bcm2835 */ | ||
77 | |||
78 | obj = OBJECT(dev); | ||
79 | - for (n = 0; n < BCM2836_NCPUS; n++) { | ||
80 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
81 | object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
82 | s->cpu_type); | ||
83 | object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
84 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
85 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | ||
86 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | ||
87 | |||
88 | - for (n = 0; n < BCM2836_NCPUS; n++) { | ||
89 | + for (n = 0; n < BCM283X_NCPUS; n++) { | ||
90 | /* Mirror bcm2836, which has clusterid set to 0xf | ||
91 | * TODO: this should be converted to a property of ARM_CPU | ||
92 | */ | ||
93 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
94 | } | ||
95 | |||
96 | static Property bcm2836_props[] = { | ||
97 | - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), | ||
98 | - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), | ||
99 | + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), | ||
100 | + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, | ||
101 | + BCM283X_NCPUS), | ||
102 | DEFINE_PROP_END_OF_LIST() | ||
103 | }; | ||
104 | |||
105 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
106 | } | ||
107 | |||
108 | static const TypeInfo bcm2836_type_info = { | ||
109 | - .name = TYPE_BCM2836, | ||
110 | + .name = TYPE_BCM283X, | ||
111 | .parent = TYPE_DEVICE, | ||
112 | - .instance_size = sizeof(BCM2836State), | ||
113 | + .instance_size = sizeof(BCM283XState), | ||
114 | .instance_init = bcm2836_init, | ||
115 | .class_init = bcm2836_class_init, | ||
116 | }; | ||
117 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/hw/arm/raspi.c | ||
120 | +++ b/hw/arm/raspi.c | ||
121 | @@ -XXX,XX +XXX,XX @@ | ||
122 | static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | ||
123 | |||
124 | typedef struct RasPiState { | ||
125 | - BCM2836State soc; | ||
126 | + BCM283XState soc; | ||
127 | MemoryRegion ram; | ||
128 | } RasPiState; | ||
129 | |||
130 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
131 | BusState *bus; | ||
132 | DeviceState *carddev; | ||
133 | |||
134 | - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); | ||
135 | + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); | ||
136 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), | ||
137 | &error_abort); | ||
138 | |||
139 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | ||
140 | mc->no_floppy = 1; | ||
141 | mc->no_cdrom = 1; | ||
142 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | ||
143 | - mc->max_cpus = BCM2836_NCPUS; | ||
144 | - mc->min_cpus = BCM2836_NCPUS; | ||
145 | - mc->default_cpus = BCM2836_NCPUS; | ||
146 | + mc->max_cpus = BCM283X_NCPUS; | ||
147 | + mc->min_cpus = BCM283X_NCPUS; | ||
148 | + mc->default_cpus = BCM283X_NCPUS; | ||
149 | mc->default_ram_size = 1024 * 1024 * 1024; | ||
150 | mc->ignore_memory_transaction_failures = true; | ||
151 | }; | ||
152 | @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) | ||
153 | mc->no_floppy = 1; | ||
154 | mc->no_cdrom = 1; | ||
155 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); | ||
156 | - mc->max_cpus = BCM2836_NCPUS; | ||
157 | - mc->min_cpus = BCM2836_NCPUS; | ||
158 | - mc->default_cpus = BCM2836_NCPUS; | ||
159 | + mc->max_cpus = BCM283X_NCPUS; | ||
160 | + mc->min_cpus = BCM283X_NCPUS; | ||
161 | + mc->default_cpus = BCM283X_NCPUS; | ||
162 | mc->default_ram_size = 1024 * 1024 * 1024; | ||
163 | } | ||
164 | DEFINE_MACHINE("raspi3", raspi3_machine_init) | ||
165 | -- | ||
166 | 2.16.2 | ||
167 | |||
168 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The bcm2837 is pretty similar to the bcm2836, but it does have | ||
2 | some differences. Notably, the MPIDR affinity aff1 values it | ||
3 | sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 | ||
4 | uses, and if this is wrong Linux will not boot. | ||
5 | 1 | ||
6 | Rather than trying to have one device with properties that | ||
7 | configure it differently for the two cases, create two | ||
8 | separate QOM devices for the two SoCs. We use the same approach | ||
9 | as hw/arm/aspeed_soc.c and share code and have a data table | ||
10 | that might differ per-SoC. For the moment the two types don't | ||
11 | actually have different behaviour. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | Message-id: 20180313153458.26822-7-peter.maydell@linaro.org | ||
16 | --- | ||
17 | include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ | ||
18 | hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- | ||
19 | hw/arm/raspi.c | 3 ++- | ||
20 | 3 files changed, 53 insertions(+), 6 deletions(-) | ||
21 | |||
22 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/include/hw/arm/bcm2836.h | ||
25 | +++ b/include/hw/arm/bcm2836.h | ||
26 | @@ -XXX,XX +XXX,XX @@ | ||
27 | |||
28 | #define BCM283X_NCPUS 4 | ||
29 | |||
30 | +/* These type names are for specific SoCs; other than instantiating | ||
31 | + * them, code using these devices should always handle them via the | ||
32 | + * BCM283x base class, so they have no BCM2836(obj) etc macros. | ||
33 | + */ | ||
34 | +#define TYPE_BCM2836 "bcm2836" | ||
35 | +#define TYPE_BCM2837 "bcm2837" | ||
36 | + | ||
37 | typedef struct BCM283XState { | ||
38 | /*< private >*/ | ||
39 | DeviceState parent_obj; | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState { | ||
41 | BCM2835PeripheralState peripherals; | ||
42 | } BCM283XState; | ||
43 | |||
44 | +typedef struct BCM283XInfo BCM283XInfo; | ||
45 | + | ||
46 | +typedef struct BCM283XClass { | ||
47 | + DeviceClass parent_class; | ||
48 | + const BCM283XInfo *info; | ||
49 | +} BCM283XClass; | ||
50 | + | ||
51 | +#define BCM283X_CLASS(klass) \ | ||
52 | + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) | ||
53 | +#define BCM283X_GET_CLASS(obj) \ | ||
54 | + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) | ||
55 | + | ||
56 | #endif /* BCM2836_H */ | ||
57 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/hw/arm/bcm2836.c | ||
60 | +++ b/hw/arm/bcm2836.c | ||
61 | @@ -XXX,XX +XXX,XX @@ | ||
62 | /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ | ||
63 | #define BCM2836_CONTROL_BASE 0x40000000 | ||
64 | |||
65 | +struct BCM283XInfo { | ||
66 | + const char *name; | ||
67 | +}; | ||
68 | + | ||
69 | +static const BCM283XInfo bcm283x_socs[] = { | ||
70 | + { | ||
71 | + .name = TYPE_BCM2836, | ||
72 | + }, | ||
73 | + { | ||
74 | + .name = TYPE_BCM2837, | ||
75 | + }, | ||
76 | +}; | ||
77 | + | ||
78 | static void bcm2836_init(Object *obj) | ||
79 | { | ||
80 | BCM283XState *s = BCM283X(obj); | ||
81 | @@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = { | ||
82 | DEFINE_PROP_END_OF_LIST() | ||
83 | }; | ||
84 | |||
85 | -static void bcm2836_class_init(ObjectClass *oc, void *data) | ||
86 | +static void bcm283x_class_init(ObjectClass *oc, void *data) | ||
87 | { | ||
88 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
89 | + BCM283XClass *bc = BCM283X_CLASS(oc); | ||
90 | |||
91 | - dc->props = bcm2836_props; | ||
92 | + bc->info = data; | ||
93 | dc->realize = bcm2836_realize; | ||
94 | + dc->props = bcm2836_props; | ||
95 | } | ||
96 | |||
97 | -static const TypeInfo bcm2836_type_info = { | ||
98 | +static const TypeInfo bcm283x_type_info = { | ||
99 | .name = TYPE_BCM283X, | ||
100 | .parent = TYPE_DEVICE, | ||
101 | .instance_size = sizeof(BCM283XState), | ||
102 | .instance_init = bcm2836_init, | ||
103 | - .class_init = bcm2836_class_init, | ||
104 | + .class_size = sizeof(BCM283XClass), | ||
105 | + .abstract = true, | ||
106 | }; | ||
107 | |||
108 | static void bcm2836_register_types(void) | ||
109 | { | ||
110 | - type_register_static(&bcm2836_type_info); | ||
111 | + int i; | ||
112 | + | ||
113 | + type_register_static(&bcm283x_type_info); | ||
114 | + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { | ||
115 | + TypeInfo ti = { | ||
116 | + .name = bcm283x_socs[i].name, | ||
117 | + .parent = TYPE_BCM283X, | ||
118 | + .class_init = bcm283x_class_init, | ||
119 | + .class_data = (void *) &bcm283x_socs[i], | ||
120 | + }; | ||
121 | + type_register(&ti); | ||
122 | + } | ||
123 | } | ||
124 | |||
125 | type_init(bcm2836_register_types) | ||
126 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
127 | index XXXXXXX..XXXXXXX 100644 | ||
128 | --- a/hw/arm/raspi.c | ||
129 | +++ b/hw/arm/raspi.c | ||
130 | @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) | ||
131 | BusState *bus; | ||
132 | DeviceState *carddev; | ||
133 | |||
134 | - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); | ||
135 | + object_initialize(&s->soc, sizeof(s->soc), | ||
136 | + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); | ||
137 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), | ||
138 | &error_abort); | ||
139 | |||
140 | -- | ||
141 | 2.16.2 | ||
142 | |||
143 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The BCM2837 sets the Aff1 field of the MPIDR affinity values for the | ||
2 | CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it | ||
3 | is required for Linux to boot. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20180313153458.26822-8-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/arm/bcm2836.c | 11 +++++++---- | ||
11 | 1 file changed, 7 insertions(+), 4 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/bcm2836.c | ||
16 | +++ b/hw/arm/bcm2836.c | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | |||
19 | struct BCM283XInfo { | ||
20 | const char *name; | ||
21 | + int clusterid; | ||
22 | }; | ||
23 | |||
24 | static const BCM283XInfo bcm283x_socs[] = { | ||
25 | { | ||
26 | .name = TYPE_BCM2836, | ||
27 | + .clusterid = 0xf, | ||
28 | }, | ||
29 | { | ||
30 | .name = TYPE_BCM2837, | ||
31 | + .clusterid = 0x0, | ||
32 | }, | ||
33 | }; | ||
34 | |||
35 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj) | ||
36 | static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
37 | { | ||
38 | BCM283XState *s = BCM283X(dev); | ||
39 | + BCM283XClass *bc = BCM283X_GET_CLASS(dev); | ||
40 | + const BCM283XInfo *info = bc->info; | ||
41 | Object *obj; | ||
42 | Error *err = NULL; | ||
43 | int n; | ||
44 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
45 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | ||
46 | |||
47 | for (n = 0; n < BCM283X_NCPUS; n++) { | ||
48 | - /* Mirror bcm2836, which has clusterid set to 0xf | ||
49 | - * TODO: this should be converted to a property of ARM_CPU | ||
50 | - */ | ||
51 | - s->cpus[n].mp_affinity = 0xF00 | n; | ||
52 | + /* TODO: this should be converted to a property of ARM_CPU */ | ||
53 | + s->cpus[n].mp_affinity = (info->clusterid << 8) | n; | ||
54 | |||
55 | /* set periphbase/CBAR value for CPU-local registers */ | ||
56 | object_property_set_int(OBJECT(&s->cpus[n]), | ||
57 | -- | ||
58 | 2.16.2 | ||
59 | |||
60 | diff view generated by jsdifflib |
1 | The raspi3 has AArch64 CPUs, which means that our smpboot | 1 | contrib/elf2dmp has a source file which uses curl/curl.h; |
---|---|---|---|
2 | code for keeping the secondary CPUs in a pen needs to have | 2 | although we link the final executable with CURL_LIBS, we |
3 | a version for A64 as well as A32. Without this, the | 3 | forgot to build this source file with CURL_CFLAGS, so if |
4 | secondary CPUs go into an infinite loop of taking undefined | 4 | the curl header is in a place that's not already on the |
5 | instruction exceptions. | 5 | system include path then it will fail to build. |
6 | |||
7 | Add a line specifying the cflags needed for download.o; | ||
8 | while we are here, bring the specification of the libs | ||
9 | into line with this, since using a per-object variable | ||
10 | setting is preferred over adding them to the final | ||
11 | executable link line. | ||
6 | 12 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 14 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
9 | Message-id: 20180313153458.26822-10-peter.maydell@linaro.org | 15 | Message-id: 20190719100955.17180-1-peter.maydell@linaro.org |
10 | --- | 16 | --- |
11 | hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- | 17 | Makefile | 1 - |
12 | 1 file changed, 40 insertions(+), 1 deletion(-) | 18 | contrib/elf2dmp/Makefile.objs | 3 +++ |
19 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
13 | 20 | ||
14 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 21 | diff --git a/Makefile b/Makefile |
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/raspi.c | 23 | --- a/Makefile |
17 | +++ b/hw/arm/raspi.c | 24 | +++ b/Makefile |
18 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ ifneq ($(EXESUF),) |
19 | #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ | 26 | qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) |
20 | #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ | 27 | endif |
21 | #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ | 28 | |
22 | +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ | 29 | -elf2dmp$(EXESUF): LIBS += $(CURL_LIBS) |
23 | 30 | elf2dmp$(EXESUF): $(elf2dmp-obj-y) | |
24 | /* Table of Linux board IDs for different Pi versions */ | 31 | $(call LINK, $^) |
25 | static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | 32 | |
26 | @@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) | 33 | diff --git a/contrib/elf2dmp/Makefile.objs b/contrib/elf2dmp/Makefile.objs |
27 | info->smp_loader_start); | 34 | index XXXXXXX..XXXXXXX 100644 |
28 | } | 35 | --- a/contrib/elf2dmp/Makefile.objs |
29 | 36 | +++ b/contrib/elf2dmp/Makefile.objs | |
30 | +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) | 37 | @@ -1 +1,4 @@ |
31 | +{ | 38 | elf2dmp-obj-y = main.o addrspace.o download.o pdb.o qemu_elf.o |
32 | + /* Unlike the AArch32 version we don't need to call the board setup hook. | ||
33 | + * The mechanism for doing the spin-table is also entirely different. | ||
34 | + * We must have four 64-bit fields at absolute addresses | ||
35 | + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for | ||
36 | + * our CPUs, and which we must ensure are zero initialized before | ||
37 | + * the primary CPU goes into the kernel. We put these variables inside | ||
38 | + * a rom blob, so that the reset for ROM contents zeroes them for us. | ||
39 | + */ | ||
40 | + static const uint32_t smpboot[] = { | ||
41 | + 0xd2801b05, /* mov x5, 0xd8 */ | ||
42 | + 0xd53800a6, /* mrs x6, mpidr_el1 */ | ||
43 | + 0x924004c6, /* and x6, x6, #0x3 */ | ||
44 | + 0xd503205f, /* spin: wfe */ | ||
45 | + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ | ||
46 | + 0xb4ffffc4, /* cbz x4, spin */ | ||
47 | + 0xd2800000, /* mov x0, #0x0 */ | ||
48 | + 0xd2800001, /* mov x1, #0x0 */ | ||
49 | + 0xd2800002, /* mov x2, #0x0 */ | ||
50 | + 0xd2800003, /* mov x3, #0x0 */ | ||
51 | + 0xd61f0080, /* br x4 */ | ||
52 | + }; | ||
53 | + | 39 | + |
54 | + static const uint64_t spintables[] = { | 40 | +download.o-cflags := $(CURL_CFLAGS) |
55 | + 0, 0, 0, 0 | 41 | +download.o-libs := $(CURL_LIBS) |
56 | + }; | ||
57 | + | ||
58 | + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), | ||
59 | + info->smp_loader_start); | ||
60 | + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), | ||
61 | + SPINTABLE_ADDR); | ||
62 | +} | ||
63 | + | ||
64 | static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) | ||
65 | { | ||
66 | arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); | ||
67 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
68 | /* Pi2 and Pi3 requires SMP setup */ | ||
69 | if (version >= 2) { | ||
70 | binfo.smp_loader_start = SMPBOOT_ADDR; | ||
71 | - binfo.write_secondary_boot = write_smpboot; | ||
72 | + if (version == 2) { | ||
73 | + binfo.write_secondary_boot = write_smpboot; | ||
74 | + } else { | ||
75 | + binfo.write_secondary_boot = write_smpboot64; | ||
76 | + } | ||
77 | binfo.secondary_cpu_reset_hook = reset_secondary; | ||
78 | } | ||
79 | |||
80 | -- | 42 | -- |
81 | 2.16.2 | 43 | 2.20.1 |
82 | 44 | ||
83 | 45 | diff view generated by jsdifflib |