Arm patch queue -- these are all bug fix patches but we might

as well put them in to rc0...

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

* fsl-imx6: Fix incorrect Ethernet interrupt defines

* dump: Update correct kdump phys_base field for AArch64

* char: i.MX: Add support for "TX complete" interrupt

* bcm2836/raspi: Fix various bugs resulting in panics trying

to boot a Debian Linux kernel on raspi3

Andrey Smirnov (2):

char: i.MX: Simplify imx_update()

char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):

fsl-imx6: Swap Ethernet interrupt defines

If we're directly booting a Linux kernel and the CPU supports both

EL3 and EL2, we start the kernel in EL2, as it expects. We must also

set the SCR_EL3.HCE bit in this situation, so that the HVC

instruction is enabled rather than UNDEFing. Otherwise at least some

kernels will panic when trying to initialize KVM in the guest.

Message-id: 20180313153458.26822-4-peter.maydell@linaro.org

hw/arm/boot.c | 5 +++++

1 file changed, 5 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)

assert(!info->secure_board_setup);

}

+ if (arm_feature(env, ARM_FEATURE_EL2)) {

+ /* If we have EL2 then Linux expects the HVC insn to work */

+ env->cp15.scr_el3 |= SCR_HCE;

+ }

/* Set to non-secure if not a secure boot */

if (!info->secure_boot &&

(cs != first_cpu || !info->secure_board_setup)) {

2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,

the board code has not mistakenly set either secure_boot or

secure_board_setup. It doesn't make sense to set secure_boot,

because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but

we don't currently support that, because only the AArch32

bootloader[] code calls this hook; bootloader_aarch64[] does not.

Since we don't have a current need for this functionality, just

assert that we don't try to use it. If it's needed we'll add

it later.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20180313153458.26822-3-peter.maydell@linaro.org

hw/arm/boot.c | 7 +++++++

1 file changed, 7 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)

} else {

env->pstate = PSTATE_MODE_EL1h;

}

+ /* AArch64 kernels never boot in secure mode */

+ assert(!info->secure_boot);

+ /* This hook is only supported for AArch32 currently:

+ * bootloader_aarch64[] will not call the hook, and

+ * the code above has already dropped us into EL2 or EL1.

+ */

+ assert(!info->secure_board_setup);

}

/* Set to non-secure if not a secure boot */

2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the

CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it

is required for Linux to boot.

Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20180313153458.26822-8-peter.maydell@linaro.org

hw/arm/bcm2836.c | 11 +++++++----

1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c

--- a/hw/arm/bcm2836.c

+++ b/hw/arm/bcm2836.c

struct BCM283XInfo {

const char *name;

+ int clusterid;

static const BCM283XInfo bcm283x_socs[] = {

{

.name = TYPE_BCM2836,

+ .clusterid = 0xf,

.name = TYPE_BCM2837,

+ .clusterid = 0x0,

@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)

static void bcm2836_realize(DeviceState *dev, Error **errp)

BCM283XState *s = BCM283X(dev);

+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);

+ const BCM283XInfo *info = bc->info;

Object *obj;

Error *err = NULL;

int n;

@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)

qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));

for (n = 0; n < BCM283X_NCPUS; n++) {

- /* Mirror bcm2836, which has clusterid set to 0xf

- * TODO: this should be converted to a property of ARM_CPU

- */

- s->cpus[n].mp_affinity = 0xF00 | n;

+ /* TODO: this should be converted to a property of ARM_CPU */

+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;

/* set periphbase/CBAR value for CPU-local registers */

object_property_set_int(OBJECT(&s->cpus[n]),

2.16.2