Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[Qemu-devel] [PULL 00/10] target-arm queue
-Arm patch queue -- these are all bug fix patches but we might
+Some Arm bugfixes for rc2...
 as well put them in to rc0...
 thanks
 -- PMM
-The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
+The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
+  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119
-for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
+for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:
-  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
+  MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * fsl-imx6: Fix incorrect Ethernet interrupt defines
+ * various MAINTAINERS file updates
- * dump: Update correct kdump phys_base field for AArch64
+ * hw/block/onenand: use qemu_log_mask() for reporting
- * char: i.MX: Add support for "TX complete" interrupt
+ * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
- * bcm2836/raspi: Fix various bugs resulting in panics trying
+   on the n800 and n810 machine models
-   to boot a Debian Linux kernel on raspi3
+ * target/arm: fix smc incorrectly trapping to EL3 when secure is off
  * hw/arm/stm32f205: Fix the UART and Timer region size
  * target/arm: read ID registers for KVM guests so they can be
    used to gate "is feature X present" checks
 ----------------------------------------------------------------
-Andrey Smirnov (2):
+Luc Michel (1):
-      char: i.MX: Simplify imx_update()
+      target/arm: fix smc incorrectly trapping to EL3 when secure is off
       char: i.MX: Add support for "TX complete" interrupt
-Guenter Roeck (1):
+Peter Maydell (3):
-      fsl-imx6: Swap Ethernet interrupt defines
+      hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
       hw/block/onenand: use qemu_log_mask() for reporting
       MAINTAINERS: list myself as maintainer for various Arm boards
-Peter Maydell (9):
+Richard Henderson (4):
-      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+      target/arm: Install ARMISARegisters from kvm host
-      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+      target/arm: Fill in ARMISARegisters for kvm64
-      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+      target/arm: Introduce read_sys_reg32 for kvm32
-      hw/arm/bcm2386: Fix parent type of bcm2386
+      target/arm: Fill in ARMISARegisters for kvm32
       hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
       hw/arm/bcm2836: Create proper bcm2837 device
       hw/arm/bcm2836: Use correct affinity values for BCM2837
       hw/arm/bcm2836: Hardcode correct CPU type
       hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
-Wei Huang (1):
+Seth Kintigh (1):
-      dump: Update correct kdump phys_base field for AArch64
+      hw/arm/stm32f205: Fix the UART and Timer region size
- include/hw/arm/bcm2836.h     | 31 +++++++++++++---
+Thomas Huth (1):
- include/hw/arm/fsl-imx6.h    |  4 +-
+      MAINTAINERS: Add entries for missing ARM boards
  include/hw/char/imx_serial.h |  3 ++
  dump.c                       | 14 +++++--
  hw/arm/bcm2836.c             | 87 +++++++++++++++++++++++++++++++-------------
  hw/arm/boot.c                | 12 ++++++
  hw/arm/raspi.c               | 77 +++++++++++++++++++++++++++++++--------
  hw/char/imx_serial.c         | 44 ++++++++++++++++------
  hw/net/imx_fec.c             | 28 +++++++++++++-
 files changed, 237 insertions(+), 63 deletions(-)
+ target/arm/kvm_arm.h       |   1 +
+ hw/block/onenand.c         |  24 +++++-----
+ hw/char/stm32f2xx_usart.c  |   2 +-
+ hw/timer/stm32f2xx_timer.c |   2 +-
+ target/arm/kvm.c           |   1 +
+ target/arm/kvm32.c         |  77 ++++++++++++++++++++------------
+ target/arm/kvm64.c         |  90 +++++++++++++++++++++++++++++++++++++-
+ target/arm/op_helper.c     |  54 +++++++++++++++++++----
+ MAINTAINERS                | 106 +++++++++++++++++++++++++++++++++++++++------
+files changed, 293 insertions(+), 64 deletions(-)

-[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
+[Qemu-devel] [PULL 01/10] target/arm: Install ARMISARegisters from kvm host
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Code of imx_update() is slightly confusing since the "flags" variable
+The ID registers are replacing (some of) the feature bits.
-doesn't really corespond to anything in real hardware and server as a
+We need (some of) these values to determine the set of data
-kitchensink accumulating events normally reported via USR1 and USR2
+to be handled during migration.
 registers.
-Change the code to explicitly evaluate state of interrupts reported
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-via USR1 and USR2 against corresponding masking bits and use the to
+Message-id: 20181113180154.17903-2-richard.henderson@linaro.org
 detemine if IRQ line should be asserted or not.
 NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
 reasons:
 . Emulation code implements a single character FIFO, so this flag
        will always be set since characters are trasmitted as a part of
        the code emulating "push" into the FIFO
 . imx_update() is really just a function doing ORing and maksing
        of reported events, so checking for UTS1_TXEMPTY should happen,
        if it's ever really needed should probably happen outside of
        it.
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/imx_serial.c | 24 ++++++++++++++++--------
+ target/arm/kvm_arm.h | 1 +
-file changed, 16 insertions(+), 8 deletions(-)
+ target/arm/kvm.c     | 1 +
 files changed, 2 insertions(+)
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/imx_serial.c
+--- a/target/arm/kvm_arm.h
-+++ b/hw/char/imx_serial.c
++++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
+  * by asking the host kernel)
- static void imx_update(IMXSerialState *s)
+  */
- {
+ typedef struct ARMHostCPUFeatures {
--    uint32_t flags;
++    ARMISARegisters isar;
-+    uint32_t usr1;
+     uint64_t features;
-+    uint32_t usr2;
+     uint32_t target;
-+    uint32_t mask;
+     const char *dtb_compatible;
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
--    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
+index XXXXXXX..XXXXXXX 100644
--    if (s->ucr1 & UCR1_TXMPTYEN) {
+--- a/target/arm/kvm.c
--        flags |= (s->uts1 & UTS1_TXEMPTY);
++++ b/target/arm/kvm.c
--    } else {
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
--        flags &= ~USR1_TRDY;
--    }
+     cpu->kvm_target = arm_host_cpu_features.target;
-+    /*
+     cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
-+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
++    cpu->isar = arm_host_cpu_features.isar;
-+     * UCR1, so we can get away with something as simple as the
+     env->features = arm_host_cpu_features.features;
 +     * following:
 +     */
 +    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
 +    /*
 +     * Bits that we want in USR2 are not as conveniently laid out,
 +     * unfortunately.
 +     */
 +    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    usr2 = s->usr2 & mask;
 -    qemu_set_irq(s->irq, !!flags);
 +    qemu_set_irq(s->irq, usr1 || usr2);
  }
- static void imx_serial_reset(IMXSerialState *s)
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
+[Qemu-devel] [PULL 02/10] target/arm: Fill in ARMISARegisters for kvm64
-The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
+From: Richard Henderson <richard.henderson@linaro.org>
 CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
 is required for Linux to boot.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20181113180154.17903-3-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 11 +++++++----
+ target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--
-file changed, 7 insertions(+), 4 deletions(-)
+file changed, 88 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/kvm64.c
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature)
+     *features &= ~(1ULL << feature);
- struct BCM283XInfo {
+ }
-     const char *name;
-+    int clusterid;
++static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
- };
++{
++    uint64_t ret;
- static const BCM283XInfo bcm283x_socs[] = {
++    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
-     {
++    int err;
-         .name = TYPE_BCM2836,
++
-+        .clusterid = 0xf,
++    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
-     },
++    err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
-     {
++    if (err < 0) {
-         .name = TYPE_BCM2837,
++        return -1;
-+        .clusterid = 0x0,
++    }
-     },
++    *pret = ret;
- };
++    return 0;
++}
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
++
- static void bcm2836_realize(DeviceState *dev, Error **errp)
++static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
 +{
 +    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
 +
 +    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
 +    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
 +}
 +
  bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  {
-     BCM283XState *s = BCM283X(dev);
+     /* Identify the feature bits corresponding to the host CPU, and
-+    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
+      * fill out the ARMHostCPUClass fields accordingly. To do this
-+    const BCM283XInfo *info = bc->info;
+      * we have to create a scratch VM, create a single CPU inside it,
-     Object *obj;
+      * and then query that CPU for the relevant ID registers.
-     Error *err = NULL;
+-     * For AArch64 we currently don't care about ID registers at
-     int n;
+-     * all; we just want to know the CPU type.
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+      */
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
+     int fdarray[3];
+     uint64_t features = 0;
-     for (n = 0; n < BCM283X_NCPUS; n++) {
++    int err;
--        /* Mirror bcm2836, which has clusterid set to 0xf
++
--         * TODO: this should be converted to a property of ARM_CPU
+     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
--         */
+      * we know these will only support creating one kind of guest CPU,
--        s->cpus[n].mp_affinity = 0xF00 | n;
+      * which is its preferred CPU type. Fortunately these old kernels
-+        /* TODO: this should be converted to a property of ARM_CPU */
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-+        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
+     ahcf->target = init.target;
+     ahcf->dtb_compatible = "arm,arm-v8";
-         /* set periphbase/CBAR value for CPU-local registers */
-         object_property_set_int(OBJECT(&s->cpus[n]),
++    err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
 +                         ARM64_SYS_REG(3, 0, 0, 4, 0));
 +    if (unlikely(err < 0)) {
 +        /*
 +         * Before v4.15, the kernel only exposed a limited number of system
 +         * registers, not including any of the interesting AArch64 ID regs.
 +         * For the most part we could leave these fields as zero with minimal
 +         * effect, since this does not affect the values seen by the guest.
 +         *
 +         * However, it could cause problems down the line for QEMU,
 +         * so provide a minimal v8.0 default.
 +         *
 +         * ??? Could read MIDR and use knowledge from cpu64.c.
 +         * ??? Could map a page of memory into our temp guest and
 +         *     run the tiniest of hand-crafted kernels to extract
 +         *     the values seen by the guest.
 +         * ??? Either of these sounds like too much effort just
 +         *     to work around running a modern host kernel.
 +         */
 +        ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
 +        err = 0;
 +    } else {
 +        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
 +                              ARM64_SYS_REG(3, 0, 0, 4, 1));
 +        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
 +                              ARM64_SYS_REG(3, 0, 0, 6, 0));
 +        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
 +                              ARM64_SYS_REG(3, 0, 0, 6, 1));
 +
 +        /*
 +         * Note that if AArch32 support is not present in the host,
 +         * the AArch32 sysregs are present to be read, but will
 +         * return UNKNOWN values.  This is neither better nor worse
 +         * than skipping the reads and leaving 0, as we must avoid
 +         * considering the values in every case.
 +         */
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 0));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 1));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 2));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 3));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 4));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 5));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
 +                              ARM64_SYS_REG(3, 0, 0, 2, 7));
 +
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
 +                              ARM64_SYS_REG(3, 0, 0, 3, 0));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
 +                              ARM64_SYS_REG(3, 0, 0, 3, 1));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
 +                              ARM64_SYS_REG(3, 0, 0, 3, 2));
 +    }
 +
      kvm_arm_destroy_scratch_host_vcpu(fdarray);
 +    if (err < 0) {
 +        return false;
 +    }
 +
     /* We can assume any KVM supporting CPU is at least a v8
       * with VFPv4+Neon; this in turn implies most of the other
       * feature bits.
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
+[Qemu-devel] [PULL 03/10] target/arm: Introduce read_sys_reg32 for kvm32
-The raspi3 has AArch64 CPUs, which means that our smpboot
+From: Richard Henderson <richard.henderson@linaro.org>
 code for keeping the secondary CPUs in a pen needs to have
 a version for A64 as well as A32. Without this, the
 secondary CPUs go into an infinite loop of taking undefined
 instruction exceptions.
+Assert that the value to be written is the correct size.
+No change in functionality here, just mirroring the same
+function from kvm64.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20181113180154.17903-4-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
 ---
- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
+ target/arm/kvm32.c | 41 ++++++++++++++++-------------------------
-file changed, 40 insertions(+), 1 deletion(-)
+file changed, 16 insertions(+), 25 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/kvm32.c
-+++ b/hw/arm/raspi.c
++++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature)
- #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
+     *features |= 1ULL << feature;
  #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
  #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
 +#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
  /* Table of Linux board IDs for different Pi versions */
  static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                         info->smp_loader_start);
  }
-+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
++static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
 +{
-+    /* Unlike the AArch32 version we don't need to call the board setup hook.
++    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
 +     * The mechanism for doing the spin-table is also entirely different.
 +     * We must have four 64-bit fields at absolute addresses
 +     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
 +     * our CPUs, and which we must ensure are zero initialized before
 +     * the primary CPU goes into the kernel. We put these variables inside
 +     * a rom blob, so that the reset for ROM contents zeroes them for us.
 +     */
 +    static const uint32_t smpboot[] = {
 +        0xd2801b05, /*        mov     x5, 0xd8 */
 +        0xd53800a6, /*        mrs     x6, mpidr_el1 */
 +        0x924004c6, /*        and     x6, x6, #0x3 */
 +        0xd503205f, /* spin:  wfe */
 +        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
 +        0xb4ffffc4, /*        cbz     x4, spin */
 +        0xd2800000, /*        mov     x0, #0x0 */
 +        0xd2800001, /*        mov     x1, #0x0 */
 +        0xd2800002, /*        mov     x2, #0x0 */
 +        0xd2800003, /*        mov     x3, #0x0 */
 +        0xd61f0080, /*        br      x4 */
 +    };
 +
-+    static const uint64_t spintables[] = {
++    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
-+        0, 0, 0, 0
++    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
 +    };
 +
 +    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
 +                       info->smp_loader_start);
 +    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
 +                       SPINTABLE_ADDR);
 +}
 +
- static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
+ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  {
-     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
+     /* Identify the feature bits corresponding to the host CPU, and
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-     /* Pi2 and Pi3 requires SMP setup */
+      * we have to create a scratch VM, create a single CPU inside it,
-     if (version >= 2) {
+      * and then query that CPU for the relevant ID registers.
-         binfo.smp_loader_start = SMPBOOT_ADDR;
+      */
--        binfo.write_secondary_boot = write_smpboot;
+-    int i, ret, fdarray[3];
-+        if (version == 2) {
++    int err = 0, fdarray[3];
-+            binfo.write_secondary_boot = write_smpboot;
+     uint32_t midr, id_pfr0, mvfr1;
-+        } else {
+     uint64_t features = 0;
-+            binfo.write_secondary_boot = write_smpboot64;
++
-+        }
+     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
-         binfo.secondary_cpu_reset_hook = reset_secondary;
+      * we know these will only support creating one kind of guest CPU,
       * which is its preferred CPU type.
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          QEMU_KVM_ARM_TARGET_NONE
      };
      struct kvm_vcpu_init init;
 -    struct kvm_one_reg idregs[] = {
 -        {
 -            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
 -            | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
 -            .addr = (uintptr_t)&midr,
 -        },
 -        {
 -            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
 -            | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
 -            .addr = (uintptr_t)&id_pfr0,
 -        },
 -        {
 -            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
 -            | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
 -            .addr = (uintptr_t)&mvfr1,
 -        },
 -    };
      if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
          return false;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
       */
      ahcf->dtb_compatible = "arm,arm-v7";
 -    for (i = 0; i < ARRAY_SIZE(idregs); i++) {
 -        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
 -        if (ret) {
 -            break;
 -        }
 -    }
 +    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
 +    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
 +    err |= read_sys_reg32(fdarray[2], &mvfr1,
 +                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
 +                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
      kvm_arm_destroy_scratch_host_vcpu(fdarray);
 -    if (ret) {
 +    if (err < 0) {
          return false;
      }
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
+[Qemu-devel] [PULL 04/10] target/arm: Fill in ARMISARegisters for kvm32
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Add support for "TX complete"/TXDC interrupt generate by real HW since
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-it is needed to support guests other than Linux.
+Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
 Based on the patch by Bill Paul as found here:
 https://bugs.launchpad.net/qemu/+bug/1753314
 Cc: qemu-devel@nongnu.org
 Cc: qemu-arm@nongnu.org
 Cc: Bill Paul <wpaul@windriver.com>
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Bill Paul <wpaul@windriver.com>
 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
 Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/char/imx_serial.h |  3 +++
+ target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++-----
- hw/char/imx_serial.c         | 20 +++++++++++++++++---
+file changed, 35 insertions(+), 5 deletions(-)
 files changed, 20 insertions(+), 3 deletions(-)
-diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
+diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/imx_serial.h
+--- a/target/arm/kvm32.c
-+++ b/include/hw/char/imx_serial.h
++++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
- #define UCR2_RXEN       (1<<1)    /* Receiver enable */
+      * and then query that CPU for the relevant ID registers.
- #define UCR2_SRST       (1<<0)    /* Reset complete */
+      */
+     int err = 0, fdarray[3];
-+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+-    uint32_t midr, id_pfr0, mvfr1;
 +    uint32_t midr, id_pfr0;
      uint64_t features = 0;
      /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
      err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
 -    err |= read_sys_reg32(fdarray[2], &mvfr1,
 +
- #define UTS1_TXEMPTY    (1<<6)
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
- #define UTS1_RXEMPTY    (1<<5)
++                          ARM_CP15_REG32(0, 0, 2, 0));
- #define UTS1_TXFULL     (1<<4)
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
-@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
++                          ARM_CP15_REG32(0, 0, 2, 1));
-     uint32_t ubmr;
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
-     uint32_t ubrc;
++                          ARM_CP15_REG32(0, 0, 2, 2));
-     uint32_t ucr3;
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
-+    uint32_t ucr4;
++                          ARM_CP15_REG32(0, 0, 2, 3));
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
-     qemu_irq irq;
++                          ARM_CP15_REG32(0, 0, 2, 4));
-     CharBackend chr;
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
-diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
++                          ARM_CP15_REG32(0, 0, 2, 5));
-index XXXXXXX..XXXXXXX 100644
++    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
---- a/hw/char/imx_serial.c
++                       ARM_CP15_REG32(0, 0, 2, 7))) {
-+++ b/hw/char/imx_serial.c
++        /*
-@@ -XXX,XX +XXX,XX @@
++         * Older kernels don't support reading ID_ISAR6. This register was
++         * only introduced in ARMv8, so we can assume that it is zero on a
- static const VMStateDescription vmstate_imx_serial = {
++         * CPU that a kernel this old is running on.
-     .name = TYPE_IMX_SERIAL,
++         */
--    .version_id = 1,
++        ahcf->isar.id_isar6 = 0;
--    .minimum_version_id = 1,
++    }
-+    .version_id = 2,
++
-+    .minimum_version_id = 2,
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
-     .fields = (VMStateField[]) {
++                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
-         VMSTATE_INT32(readbuff, IMXSerialState),
++                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
-         VMSTATE_UINT32(usr1, IMXSerialState),
++    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
-         VMSTATE_UINT32(ubmr, IMXSerialState),
+                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
          VMSTATE_UINT32(ubrc, IMXSerialState),
          VMSTATE_UINT32(ucr3, IMXSerialState),
 +        VMSTATE_UINT32(ucr4, IMXSerialState),
          VMSTATE_END_OF_LIST()
      },
  };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
       * unfortunately.
       */
      mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
 +    /*
-+     * TCEN and TXDC are both bit 3
++     * FIXME: There is not yet a way to read MVFR2.
 +     * Fortunately there is not yet anything in there that affects migration.
 +     */
-+    mask |= s->ucr4 & UCR4_TCEN;
-+
+     kvm_arm_destroy_scratch_host_vcpu(fdarray);
-     usr2 = s->usr2 & mask;
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-     qemu_set_irq(s->irq, usr1 || usr2);
+     if (extract32(id_pfr0, 12, 4) == 1) {
-@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
+         set_feature(&features, ARM_FEATURE_THUMB2EE);
-         return s->ucr3;
+     }
+-    if (extract32(mvfr1, 20, 4) == 1) {
-     case 0x23: /* UCR4 */
++    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
-+        return s->ucr4;
+         set_feature(&features, ARM_FEATURE_VFP_FP16);
-+
+     }
-     case 0x29: /* BRM Incremental */
+-    if (extract32(mvfr1, 12, 4) == 1) {
-         return 0x0; /* TODO */
++    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
+         set_feature(&features, ARM_FEATURE_NEON);
-@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
+     }
-              * qemu_chr_fe_write and background I/O callbacks */
+-    if (extract32(mvfr1, 28, 4) == 1) {
-             qemu_chr_fe_write_all(&s->chr, &ch, 1);
++    if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
-             s->usr1 &= ~USR1_TRDY;
+         /* FMAC support implies VFPv4 */
-+            s->usr2 &= ~USR2_TXDC;
+         set_feature(&features, ARM_FEATURE_VFP4);
-             imx_update(s);
+     }
              s->usr1 |= USR1_TRDY;
 +            s->usr2 |= USR2_TXDC;
              imx_update(s);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
          s->ucr3 = value & 0xffff;
          break;
 -    case 0x2d: /* UTS1 */
      case 0x23: /* UCR4 */
 +        s->ucr4 = value & 0xffff;
 +        imx_update(s);
 +        break;
 +
 +    case 0x2d: /* UTS1 */
          qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                        HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
          /* TODO */
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
+[Qemu-devel] [PULL 05/10] MAINTAINERS: Add entries for missing ARM boards
-From: Wei Huang <wei@redhat.com>
+From: Thomas Huth <thuth@redhat.com>
-For guest kernel that supports KASLR, the load address can change every
+Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2",
-time when guest VM runs. To find the physical base address correctly,
+"raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt".
-current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
+While we're at it, also adjust the "i.MX31" section a little bit,
-However this string pattern is only available on x86_64. AArch64 uses a
+so that the wildcards there do not match anymore for unrelated files
-different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
+(e.g. the new hw/misc/imx6ul_ccm.c file).
 QEMU dump uses the correct string on AArch64.
-Signed-off-by: Wei Huang <wei@redhat.com>
+Signed-off-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
+Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com
 Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- dump.c | 14 +++++++++++---
+ MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++----
-file changed, 11 insertions(+), 3 deletions(-)
+file changed, 65 insertions(+), 5 deletions(-)
-diff --git a/dump.c b/dump.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/dump.c
+--- a/MAINTAINERS
-+++ b/dump.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
+@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
+ S: Odd Fixes
-     lines = g_strsplit((char *)vmci, "\n", -1);
+ F: hw/arm/gumstix.c
-     for (i = 0; lines[i]; i++) {
--        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
+-i.MX31
--            if (qemu_strtou64(lines[i] + 18, NULL, 16,
++i.MX31 (kzm)
-+        const char *prefix = NULL;
+ M: Peter Chubb <peter.chubb@nicta.com.au>
  L: qemu-arm@nongnu.org
 -S: Odd fixes
 -F: hw/*/imx*
 -F: include/hw/*/imx*
 +S: Odd Fixes
  F: hw/arm/kzm.c
 -F: include/hw/arm/fsl-imx31.h
 +F: hw/*/imx_*
 +F: hw/*/*imx31*
 +F: include/hw/*/imx_*
 +F: include/hw/*/*imx31*
  Integrator CP
  M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ S: Maintained
  F: hw/arm/integratorcp.c
  F: hw/misc/arm_integrator_debug.c
 +MCIMX6UL EVK / i.MX6ul
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Jean-Christophe Dubois <jcd@tribudubois.net>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/mcimx6ul-evk.c
 +F: hw/arm/fsl-imx6ul.c
 +F: hw/misc/imx6ul_ccm.c
 +F: include/hw/arm/fsl-imx6ul.h
 +F: include/hw/misc/imx6ul_ccm.h
 +
-+        if (s->dump_info.d_machine == EM_X86_64) {
++MCIMX7D SABRE / i.MX7
-+            prefix = "NUMBER(phys_base)=";
++M: Peter Maydell <peter.maydell@linaro.org>
-+        } else if (s->dump_info.d_machine == EM_AARCH64) {
++R: Andrey Smirnov <andrew.smirnov@gmail.com>
-+            prefix = "NUMBER(PHYS_OFFSET)=";
++L: qemu-arm@nongnu.org
-+        }
++S: Odd Fixes
 +F: hw/arm/mcimx7d-sabre.c
 +F: hw/arm/fsl-imx7.c
 +F: include/hw/arm/fsl-imx7.h
 +F: hw/pci-host/designware.c
 +F: include/hw/pci-host/designware.h
 +
-+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+ MPS2
-+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
+ M: Peter Maydell <peter.maydell@linaro.org>
-                               &phys_base) < 0) {
+ L: qemu-arm@nongnu.org
--                warn_report("Failed to read NUMBER(phys_base)=");
+@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
-+                warn_report("Failed to read %s", prefix);
+ S: Maintained
-             } else {
+ F: hw/arm/palm.c
-                 s->dump_info.phys_base = phys_base;
-             }
++Raspberry Pi
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Andrew Baumann <Andrew.Baumann@microsoft.com>
 +R: Philippe Mathieu-Daudé <f4bug@amsat.org>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/raspi_platform.h
 +F: hw/*/bcm283*
 +F: include/hw/arm/raspi*
 +F: include/hw/*/bcm283*
 +
  Real View
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx*
  F: hw/misc/mst_fpga.c
  F: include/hw/arm/pxa.h
 +SABRELITE / i.MX6
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Jean-Christophe Dubois <jcd@tribudubois.net>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/sabrelite.c
 +F: hw/arm/fsl-imx6.c
 +F: hw/misc/imx6_src.c
 +F: hw/ssi/imx_spi.c
 +F: include/hw/arm/fsl-imx6.h
 +F: include/hw/misc/imx6_src.h
 +F: include/hw/ssi/imx_spi.h
 +
  Sharp SL-5500 (Collie) PDA
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/*/stellaris*
 +Versatile Express
 +M: Peter Maydell <peter.maydell@linaro.org>
 +L: qemu-arm@nongnu.org
 +S: Maintained
 +F: hw/arm/vexpress.c
 +
  Versatile PB
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ S: Maintained
  F: hw/*/versatile*
  F: hw/misc/arm_sysctl.c
 +Virt
 +M: Peter Maydell <peter.maydell@linaro.org>
 +L: qemu-arm@nongnu.org
 +S: Maintained
 +F: hw/arm/virt*
 +F: include/hw/arm/virt.h
 +
  Xilinx Zynq
  M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
  M: Alistair Francis <alistair@alistair23.me>
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
+[Qemu-devel] [PULL 06/10] hw/arm/stm32f205: Fix the UART and Timer region size
-Now we have separate types for BCM2386 and BCM2387, we might as well
+From: Seth Kintigh <skintigh@gmail.com>
 just hard-code the CPU type they use rather than having it passed
 through as an object property. This then lets us put the initialization
 of the CPU object in init rather than realize.
-Note that this change means that it's no longer possible on
+The UART and timer devices for the stm32f205 were being created
-the command line to use -cpu to ask for a different kind of
+with memory regions that were too large. Use the size specified
-CPU than the SoC supports. This was never a supported thing to
+in the chip datasheet.
 do anyway; we were just not sanity-checking the command line.
-This does require us to only build the bcm2837 object on
+The old sizes were so large that the devices would overlap with
-TARGET_AARCH64 configs, since otherwise it won't instantiate
+each other in the SoC memory map, so this fixes a bug that
-due to the missing cortex-a53 device and "make check" will fail.
+caused odd behavior and/or crashes when trying to set up multiple
 UARTs.
+Signed-off-by: Seth Kintigh <skintigh@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+[PMM: rephrased commit message to follow our usual standard]
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
 ---
- hw/arm/bcm2836.c | 24 +++++++++++++++---------
+ hw/char/stm32f2xx_usart.c  | 2 +-
- hw/arm/raspi.c   |  2 --
+ hw/timer/stm32f2xx_timer.c | 2 +-
-files changed, 15 insertions(+), 11 deletions(-)
+files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/char/stm32f2xx_usart.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/char/stm32f2xx_usart.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj)
+     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
- struct BCM283XInfo {
-     const char *name;
+     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
-+    const char *cpu_type;
+-                          TYPE_STM32F2XX_USART, 0x2000);
-     int clusterid;
++                          TYPE_STM32F2XX_USART, 0x400);
- };
+     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
  static const BCM283XInfo bcm283x_socs[] = {
      {
          .name = TYPE_BCM2836,
 +        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
          .clusterid = 0xf,
      },
 +#ifdef TARGET_AARCH64
      {
          .name = TYPE_BCM2837,
 +        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
          .clusterid = 0x0,
      },
 +#endif
  };
  static void bcm2836_init(Object *obj)
  {
      BCM283XState *s = BCM283X(obj);
 +    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
 +    const BCM283XInfo *info = bc->info;
 +    int n;
 +
 +    for (n = 0; n < BCM283X_NCPUS; n++) {
 +        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 +                          info->cpu_type);
 +        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 +                                  &error_abort);
 +    }
      object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
      object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
      /* common peripherals from bcm2835 */
 -    obj = OBJECT(dev);
 -    for (n = 0; n < BCM283X_NCPUS; n++) {
 -        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
 -                          s->cpu_type);
 -        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
 -                                  &error_abort);
 -    }
 -
      obj = object_property_get_link(OBJECT(dev), "ram", &err);
      if (obj == NULL) {
          error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
  }
- static Property bcm2836_props[] = {
+diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
 -    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
      DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                         BCM283X_NCPUS),
      DEFINE_PROP_END_OF_LIST()
 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/hw/timer/stm32f2xx_timer.c
-+++ b/hw/arm/raspi.c
++++ b/hw/timer/stm32f2xx_timer.c
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj)
-     /* Setup the SOC */
+     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
-                                    &error_abort);
+     memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
--    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+-                          "stm32f2xx_timer", 0x4000);
--                            &error_abort);
++                          "stm32f2xx_timer", 0x400);
-     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
+     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
-                             &error_abort);
-     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
+     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
+[Qemu-devel] [PULL 07/10] target/arm: fix smc incorrectly trapping to EL3 when secure is off
-From: Guenter Roeck <linux@roeck-us.net>
+From: Luc Michel <luc.michel@greensocs.com>
-The sabrelite machine model used by qemu-system-arm is based on the
+This commit fixes a case where the CPU would try to go to EL3 when
-Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
+executing an smc instruction, even though ARM_FEATURE_EL3 is false. This
-controller which is supported in QEMU using the imx_fec.c module
+case is raised when the PSCI conduit is set to smc, but the smc
-(actually called imx.enet for this model.)
+instruction does not lead to a valid PSCI call.
-The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
+QEMU crashes with an assertion failure latter on because of incoherent
-imx.enet device like this:
+mmu_idx.
- #define FSL_IMX6_ENET_MAC_1588_IRQ 118
+This commit refactors the pre_smc helper by enumerating all the possible
- #define FSL_IMX6_ENET_MAC_IRQ 119
+way of handling an scm instruction, and covering the previously missing
 case leading to the crash.
-According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
+The following minimal test would crash before this commit:
 page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
 interrupts are as follows.
-ENET MAC 0 IRQ
+.global _start
-ENET MAC 0 1588 Timer interrupt
+    .text
 _start:
     ldr x0, =0xdeadbeef  ; invalid PSCI call
     smc #0
-where
+run with the following command line:
-- 32 == 118
+aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \
-- 32 == 119
+                      -o test test.s
-In other words, the vector definitions in the fsl-imx6.h file are reversed.
+qemu-system-aarch64 -M virt,virtualization=on,secure=off \
                     -cpu cortex-a57 -kernel test
-Fixing the interrupts alone causes problems with older Linux kernels:
+Signed-off-by: Luc Michel <luc.michel@greensocs.com>
-The Ethernet interface will fail to probe with Linux v4.9 and earlier.
+Message-id: 20181117160213.18995-1-luc.michel@greensocs.com
 Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
 error handling. This is a Linux kernel problem, not a qemu problem:
 the Linux kernel only worked by accident since it requested both interrupts.
 For backward compatibility, generate the Ethernet interrupt on both interrupt
 lines. This was shown to work from all Linux kernel releases starting with
 v3.16.
 Link: https://bugs.launchpad.net/qemu/+bug/1753309
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6.h |  4 ++--
+ target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++-------
- hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
+file changed, 46 insertions(+), 8 deletions(-)
 files changed, 29 insertions(+), 3 deletions(-)
-diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
+--- a/target/arm/op_helper.c
-+++ b/include/hw/arm/fsl-imx6.h
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
+@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
- #define FSL_IMX6_HDMI_MASTER_IRQ 115
+     ARMCPU *cpu = arm_env_get_cpu(env);
- #define FSL_IMX6_HDMI_CEC_IRQ 116
+     int cur_el = arm_current_el(env);
- #define FSL_IMX6_MLB150_LOW_IRQ 117
+     bool secure = arm_is_secure(env);
--#define FSL_IMX6_ENET_MAC_1588_IRQ 118
+-    bool smd = env->cp15.scr_el3 & SCR_SMD;
--#define FSL_IMX6_ENET_MAC_IRQ 119
++    bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
-+#define FSL_IMX6_ENET_MAC_IRQ 118
++
 +#define FSL_IMX6_ENET_MAC_1588_IRQ 119
  #define FSL_IMX6_PCIE1_IRQ 120
  #define FSL_IMX6_PCIE2_IRQ 121
  #define FSL_IMX6_PCIE3_IRQ 122
 diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/imx_fec.c
 +++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
  static void imx_eth_update(IMXFECState *s)
  {
 -    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
 +    /*
-+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
++     * SMC behaviour is summarized in the following table.
-+     * interrupts swapped. This worked with older versions of Linux (4.14
++     * This helper handles the "Trap to EL2" and "Undef insn" cases.
-+     * and older) since Linux associated both interrupt lines with Ethernet
++     * The "Trap to EL3" and "PSCI call" cases are handled in the exception
-+     * MAC interrupts. Specifically,
++     * helper.
 +     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
 +     *   timer interrupts. Those versions of Linux fail with versions of QEMU
 +     *   with swapped interrupt assignments.
 +     * - In linux 4.14, both interrupt lines were registered with the Ethernet
 +     *   MAC interrupt handler. As a result, all versions of qemu happen to
 +     *   work, though that is accidental.
 +     * - In Linux 4.9 and older, the timer interrupt was registered directly
 +     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
 +     *   redirected to a GPIO interrupt to work around erratum ERR006687.
 +     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
 +     *   interrupt never fired since IOMUX is currently not supported in qemu.
 +     *   Linux instead received MAC interrupts on the timer interrupt.
 +     *   As a result, qemu versions with the swapped interrupt assignment work,
 +     *   albeit accidentally, but qemu versions with the correct interrupt
 +     *   assignment fail.
 +     *
-+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
++     *  -> ARM_FEATURE_EL3 and !SMD
-+     * interrrupts on both interrupt lines. This should be changed if and when
++     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
-+     * qemu supports IOMUX.
++     *
 +     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
 +     *  Conduit SMC, inval call  Trap to EL2         Trap to EL3
 +     *  Conduit not SMC          Trap to EL2         Trap to EL3
 +     *
 +     *
 +     *  -> ARM_FEATURE_EL3 and SMD
 +     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
 +     *
 +     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
 +     *  Conduit SMC, inval call  Trap to EL2         Undef insn
 +     *  Conduit not SMC          Trap to EL2         Undef insn
 +     *
 +     *
 +     *  -> !ARM_FEATURE_EL3
 +     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
 +     *
 +     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
 +     *  Conduit SMC, inval call  Trap to EL2         Undef insn
 +     *  Conduit not SMC          Undef insn          Undef insn
 +     */
-+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
++
-+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
+     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
-         qemu_set_irq(s->irq[1], 1);
+      * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
-     } else {
+      *  extensions, SMD only applies to NS state.
-         qemu_set_irq(s->irq[1], 0);
+@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
       * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
       * so we need not special case this here.
       */
 -    bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
 +    bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag
 +                                                     : smd_flag && !secure;
      if (!arm_feature(env, ARM_FEATURE_EL3) &&
          cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
           * to forbid its EL1 from making PSCI calls into QEMU's
           * "firmware" via HCR.TSC, so for these purposes treat
           * PSCI-via-SMC as implying an EL3.
 +         * This handles the very last line of the previous table.
           */
 -        undef = true;
 -    } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
 +        raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 +                        exception_target_el(env));
 +    }
 +
 +    if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
          /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
           * We also want an EL2 guest to be able to forbid its EL1 from
           * making PSCI calls into QEMU's "firmware" via HCR.TSC.
 +         * This handles all the "Trap to EL2" cases of the previous table.
           */
          raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
      }
 -    /* If PSCI is enabled and this looks like a valid PSCI call then
 -     * suppress the UNDEF -- we'll catch the SMC exception and
 -     * implement the PSCI call behaviour there.
 +    /* Catch the two remaining "Undef insn" cases of the previous table:
 +     *    - PSCI conduit is SMC but we don't have a valid PCSI call,
 +     *    - We don't have EL3 or SMD is set.
       */
 -    if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) {
 +    if (!arm_is_psci_call(cpu, EXCP_SMC) &&
 +        (smd || !arm_feature(env, ARM_FEATURE_EL3))) {
          raise_exception(env, EXCP_UDEF, syn_uncategorized(),
                          exception_target_el(env));
      }
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+Deleted patch
-For the rpi1 and 2 we want to boot the Linux kernel via some
-custom setup code that makes sure that the SMC instruction
-acts as a no-op, because it's used for cache maintenance.
-The rpi3 boots AArch64 kernels, which don't need SMC for
-cache maintenance and always expect to be booted non-secure.
-Don't fill in the aarch32-specific parts of the binfo struct.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
----
- hw/arm/raspi.c | 17 +++++++++++++----
-file changed, 13 insertions(+), 4 deletions(-)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
-+++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
-     binfo.board_id = raspi_boardid[version];
-     binfo.ram_size = ram_size;
-     binfo.nb_cpus = smp_cpus;
--    binfo.board_setup_addr = BOARDSETUP_ADDR;
--    binfo.write_board_setup = write_board_setup;
--    binfo.secure_board_setup = true;
--    binfo.secure_boot = true;
-+
-+    if (version <= 2) {
-+        /* The rpi1 and 2 require some custom setup code to run in Secure
-+         * mode before booting a kernel (to set up the SMC vectors so
-+         * that we get a no-op SMC; this is used by Linux to call the
-+         * firmware for some cache maintenance operations.
-+         * The rpi3 doesn't need this.
-+         */
-+        binfo.board_setup_addr = BOARDSETUP_ADDR;
-+        binfo.write_board_setup = write_board_setup;
-+        binfo.secure_board_setup = true;
-+        binfo.secure_boot = true;
-+    }
-     /* Pi2 and Pi3 requires SMP setup */
-     if (version >= 2) {
---
-.16.2

-[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
+Deleted patch
-Add some assertions that if we're about to boot an AArch64 kernel,
-the board code has not mistakenly set either secure_boot or
-secure_board_setup. It doesn't make sense to set secure_boot,
-because all AArch64 kernels must be booted in non-secure mode.
-It might in theory make sense to set secure_board_setup, but
-we don't currently support that, because only the AArch32
-bootloader[] code calls this hook; bootloader_aarch64[] does not.
-Since we don't have a current need for this functionality, just
-assert that we don't try to use it. If it's needed we'll add
-it later.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
----
- hw/arm/boot.c | 7 +++++++
-file changed, 7 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
-+++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-                     } else {
-                         env->pstate = PSTATE_MODE_EL1h;
-                     }
-+                    /* AArch64 kernels never boot in secure mode */
-+                    assert(!info->secure_boot);
-+                    /* This hook is only supported for AArch32 currently:
-+                     * bootloader_aarch64[] will not call the hook, and
-+                     * the code above has already dropped us into EL2 or EL1.
-+                     */
-+                    assert(!info->secure_board_setup);
-                 }
-                 /* Set to non-secure if not a secure boot */
---
-.16.2

-[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+Deleted patch
-If we're directly booting a Linux kernel and the CPU supports both
-EL3 and EL2, we start the kernel in EL2, as it expects. We must also
-set the SCR_EL3.HCE bit in this situation, so that the HVC
-instruction is enabled rather than UNDEFing. Otherwise at least some
-kernels will panic when trying to initialize KVM in the guest.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
----
- hw/arm/boot.c | 5 +++++
-file changed, 5 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
-+++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-                     assert(!info->secure_board_setup);
-                 }
-+                if (arm_feature(env, ARM_FEATURE_EL2)) {
-+                    /* If we have EL2 then Linux expects the HVC insn to work */
-+                    env->cp15.scr_el3 |= SCR_HCE;
-+                }
-+
-                 /* Set to non-secure if not a secure boot */
-                 if (!info->secure_boot &&
-                     (cs != first_cpu || !info->secure_board_setup)) {
---
-.16.2

-[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
+[Qemu-devel] [PULL 08/10] hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
-The TypeInfo and state struct for bcm2386 disagree about what the
+An off-by-one error in a switch case in onenand_read() allowed
-parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
+a misbehaving guest to read off the end of a block of memory.
 but the BCM2386State struct only defines the parent_obj field
 as DeviceState. This would have caused problems if anything
 actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
 Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
 need any of the additional functionality TYPE_SYS_BUS_DEVICE
 provides.
+NB: the onenand device is used only by the "n800" and "n810"
+machines, which are usable only with TCG, not KVM, so this is
+not a security issue.
+Reported-by: Thomas Huth <thuth@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Message-id: 20181115143535.5885-2-peter.maydell@linaro.org
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/bcm2836.c | 2 +-
+ hw/block/onenand.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/hw/block/onenand.c b/hw/block/onenand.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/hw/block/onenand.c
-+++ b/hw/arm/bcm2836.c
++++ b/hw/block/onenand.c
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
+     int offset = addr >> s->shift;
- static const TypeInfo bcm2836_type_info = {
-     .name = TYPE_BCM2836,
+     switch (offset) {
--    .parent = TYPE_SYS_BUS_DEVICE,
+-    case 0x0000 ... 0xc000:
-+    .parent = TYPE_DEVICE,
++    case 0x0000 ... 0xbffe:
-     .instance_size = sizeof(BCM2836State),
+         return lduw_le_p(s->boot[0] + addr);
-     .instance_init = bcm2836_init,
-     .class_init = bcm2836_class_init,
+     case 0xf000:    /* Manufacturer ID */
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
+[Qemu-devel] [PULL 09/10] hw/block/onenand: use qemu_log_mask() for reporting
-The bcm2837 is pretty similar to the bcm2836, but it does have
+Update the onenand device to use qemu_log_mask() for reporting
-some differences. Notably, the MPIDR affinity aff1 values it
+guest errors and unimplemented features, rather than plain
-sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
+fprintf() and hw_error().
 uses, and if this is wrong Linux will not boot.
-Rather than trying to have one device with properties that
+(We leave the hw_error() in onenand_reset(), as that is
-configure it differently for the two cases, create two
+triggered by a failure to read the underlying block device
-separate QOM devices for the two SoCs. We use the same approach
+for the bootRAM, not by guest action.)
 as hw/arm/aspeed_soc.c and share code and have a data table
 that might differ per-SoC. For the moment the two types don't
 actually have different behaviour.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Thomas Huth <thuth@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20181115143535.5885-3-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
+ hw/block/onenand.c | 22 +++++++++++++---------
- hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
+file changed, 13 insertions(+), 9 deletions(-)
  hw/arm/raspi.c           |  3 ++-
 files changed, 53 insertions(+), 6 deletions(-)
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+diff --git a/hw/block/onenand.c b/hw/block/onenand.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/hw/block/onenand.c
-+++ b/include/hw/arm/bcm2836.h
++++ b/hw/block/onenand.c
 @@ -XXX,XX +XXX,XX @@
+ #include "exec/memory.h"
- #define BCM283X_NCPUS 4
+ #include "hw/sysbus.h"
+ #include "qemu/error-report.h"
-+/* These type names are for specific SoCs; other than instantiating
++#include "qemu/log.h"
-+ * them, code using these devices should always handle them via the
-+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
-+ */
+ #define PAGE_SHIFT    11
-+#define TYPE_BCM2836 "bcm2836"
+@@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s)
-+#define TYPE_BCM2837 "bcm2837"
+     default:
-+
+         s->status |= ONEN_ERR_CMD;
- typedef struct BCM283XState {
+         s->intstatus |= ONEN_INT;
-     /*< private >*/
+-        fprintf(stderr, "%s: unknown OneNAND command %x\n",
-     DeviceState parent_obj;
+-                        __func__, s->command);
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
++        qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
-     BCM2835PeripheralState peripherals;
++                      s->command);
- } BCM283XState;
+     }
-+typedef struct BCM283XInfo BCM283XInfo;
+     onenand_intr_update(s);
-+
+@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
-+typedef struct BCM283XClass {
+     case 0xff02:    /* ECC Result of spare area data */
-+    DeviceClass parent_class;
+     case 0xff03:    /* ECC Result of main area data */
-+    const BCM283XInfo *info;
+     case 0xff04:    /* ECC Result of spare area data */
-+} BCM283XClass;
+-        hw_error("%s: implement ECC\n", __func__);
-+
++        qemu_log_mask(LOG_UNIMP,
-+#define BCM283X_CLASS(klass) \
++                      "onenand: ECC result registers unimplemented\n");
-+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+         return 0x0000;
-+#define BCM283X_GET_CLASS(obj) \
+     }
-+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
-+
+-    fprintf(stderr, "%s: unknown OneNAND register %x\n",
- #endif /* BCM2836_H */
+-                    __func__, offset);
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
++    qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n",
-index XXXXXXX..XXXXXXX 100644
++                  offset);
---- a/hw/arm/bcm2836.c
+     return 0;
 +++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
  /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
  #define BCM2836_CONTROL_BASE    0x40000000
 +struct BCM283XInfo {
 +    const char *name;
 +};
 +
 +static const BCM283XInfo bcm283x_socs[] = {
 +    {
 +        .name = TYPE_BCM2836,
 +    },
 +    {
 +        .name = TYPE_BCM2837,
 +    },
 +};
 +
  static void bcm2836_init(Object *obj)
  {
      BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
      DEFINE_PROP_END_OF_LIST()
  };
 -static void bcm2836_class_init(ObjectClass *oc, void *data)
 +static void bcm283x_class_init(ObjectClass *oc, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(oc);
 +    BCM283XClass *bc = BCM283X_CLASS(oc);
 -    dc->props = bcm2836_props;
 +    bc->info = data;
      dc->realize = bcm2836_realize;
 +    dc->props = bcm2836_props;
  }
--static const TypeInfo bcm2836_type_info = {
+@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
-+static const TypeInfo bcm283x_type_info = {
+             break;
-     .name = TYPE_BCM283X,
-     .parent = TYPE_DEVICE,
+         default:
-     .instance_size = sizeof(BCM283XState),
+-            fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
-     .instance_init = bcm2836_init,
+-                            __func__, value);
--    .class_init = bcm2836_class_init,
++            qemu_log_mask(LOG_GUEST_ERROR,
-+    .class_size = sizeof(BCM283XClass),
++                          "unknown OneNAND boot command %" PRIx64 "\n",
-+    .abstract = true,
++                          value);
- };
+         }
+         break;
- static void bcm2836_register_types(void)
- {
+@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
--    type_register_static(&bcm2836_type_info);
+         break;
-+    int i;
-+
+     default:
-+    type_register_static(&bcm283x_type_info);
+-        fprintf(stderr, "%s: unknown OneNAND register %x\n",
-+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+-                        __func__, offset);
-+        TypeInfo ti = {
++        qemu_log_mask(LOG_GUEST_ERROR,
-+            .name = bcm283x_socs[i].name,
++                      "write to unknown OneNAND register 0x%x\n",
-+            .parent = TYPE_BCM283X,
++                      offset);
-+            .class_init = bcm283x_class_init,
+     }
 +            .class_data = (void *) &bcm283x_socs[i],
 +        };
 +        type_register(&ti);
 +    }
  }
- type_init(bcm2836_register_types)
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
-+++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
-     BusState *bus;
-     DeviceState *carddev;
--    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
-+    object_initialize(&s->soc, sizeof(s->soc),
-+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
-     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
-                               &error_abort);
 --
-.16.2
+.19.1

-[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+[Qemu-devel] [PULL 10/10] MAINTAINERS: list myself as maintainer for various Arm boards
-Our BCM2836 type is really a generic one that can be any of
+In practice for most of the more-or-less orphan Arm board models,
-the bcm283x family. Rename it accordingly. We change only
+I will review patches and put them in via the target-arm tree.
-the names which are visible via the header file to the
+So list myself as an "Odd Fixes" status maintainer for them.
-rest of the QEMU code, leaving private function names
-in bcm2836.c as they are.
+This commit downgrades these boards to "Odd Fixes":
+ * Allwinner-A10
-This is a preliminary to making bcm283x be an abstract
+ * Exynos
-parent class to specific types for the bcm2836 and bcm2837.
+ * Calxeda Highbank
  * Canon DIGIC
  * Musicpal
  * nSeries
  * Palm
  * PXA2xx
 These boards were already "Odd Fixes":
  * Gumstix
  * i.MX31 (kzm)
 Philippe Mathieu-Daudé has requested to be moved to R:
 status for Gumstix now that I am listed as the M: contact.
 Some boards are maintained, but their patches still go
 via the target-arm tree, so add myself as a secondary
 maintainer contact for those:
  * Xilinx Zynq
  * Xilinx ZynqMP
  * STM32F205
  * Netduino 2
  * SmartFusion2
  * Mecraft M2S-FG484
  * ASPEED BMCs
  * NRF51
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
-Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
+Message-id: 20181108134139.31666-1-peter.maydell@linaro.org
 ---
- include/hw/arm/bcm2836.h | 12 ++++++------
+ MAINTAINERS | 36 +++++++++++++++++++++++++++---------
- hw/arm/bcm2836.c         | 17 +++++++++--------
+file changed, 27 insertions(+), 9 deletions(-)
- hw/arm/raspi.c           | 16 ++++++++--------
-files changed, 23 insertions(+), 22 deletions(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
 diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
+--- a/MAINTAINERS
-+++ b/include/hw/arm/bcm2836.h
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ ARM Machines
- #include "hw/arm/bcm2835_peripherals.h"
+ ------------
- #include "hw/intc/bcm2836_control.h"
+ Allwinner-a10
+ M: Beniamino Galvani <b.galvani@gmail.com>
--#define TYPE_BCM2836 "bcm2836"
++M: Peter Maydell <peter.maydell@linaro.org>
--#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+ L: qemu-arm@nongnu.org
-+#define TYPE_BCM283X "bcm283x"
+-S: Maintained
-+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
++S: Odd Fixes
+ F: hw/*/allwinner*
--#define BCM2836_NCPUS 4
+ F: include/hw/*/allwinner*
-+#define BCM283X_NCPUS 4
+ F: hw/arm/cubieboard.c
+@@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c
--typedef struct BCM2836State {
-+typedef struct BCM283XState {
+ Exynos
-     /*< private >*/
+ M: Igor Mitsyanko <i.mitsyanko@gmail.com>
-     DeviceState parent_obj;
++M: Peter Maydell <peter.maydell@linaro.org>
-     /*< public >*/
+ L: qemu-arm@nongnu.org
-@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
+-S: Maintained
-     char *cpu_type;
++S: Odd Fixes
-     uint32_t enabled_cpus;
+ F: hw/*/exynos*
+ F: include/hw/arm/exynos4210.h
--    ARMCPU cpus[BCM2836_NCPUS];
-+    ARMCPU cpus[BCM283X_NCPUS];
+ Calxeda Highbank
-     BCM2836ControlState control;
+ M: Rob Herring <robh@kernel.org>
-     BCM2835PeripheralState peripherals;
++M: Peter Maydell <peter.maydell@linaro.org>
--} BCM2836State;
+ L: qemu-arm@nongnu.org
-+} BCM283XState;
+-S: Maintained
++S: Odd Fixes
- #endif /* BCM2836_H */
+ F: hw/arm/highbank.c
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+ F: hw/net/xgmac.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+ Canon DIGIC
-+++ b/hw/arm/bcm2836.c
+ M: Antony Pavlov <antonynpavlov@gmail.com>
-@@ -XXX,XX +XXX,XX @@
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
- static void bcm2836_init(Object *obj)
+-S: Maintained
- {
++S: Odd Fixes
--    BCM2836State *s = BCM2836(obj);
+ F: include/hw/arm/digic.h
-+    BCM283XState *s = BCM283X(obj);
+ F: hw/*/digic*
-     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
+ Gumstix
-     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
+-M: Philippe Mathieu-Daudé <f4bug@amsat.org>
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
++M: Peter Maydell <peter.maydell@linaro.org>
++R: Philippe Mathieu-Daudé <f4bug@amsat.org>
- static void bcm2836_realize(DeviceState *dev, Error **errp)
+ L: qemu-devel@nongnu.org
- {
+ L: qemu-arm@nongnu.org
--    BCM2836State *s = BCM2836(dev);
+ S: Odd Fixes
-+    BCM283XState *s = BCM283X(dev);
+@@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c
-     Object *obj;
-     Error *err = NULL;
+ i.MX31 (kzm)
-     int n;
+ M: Peter Chubb <peter.chubb@nicta.com.au>
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
++M: Peter Maydell <peter.maydell@linaro.org>
-     /* common peripherals from bcm2835 */
+ L: qemu-arm@nongnu.org
+ S: Odd Fixes
-     obj = OBJECT(dev);
+ F: hw/arm/kzm.c
--    for (n = 0; n < BCM2836_NCPUS; n++) {
+@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
-         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+ Musicpal
-                           s->cpu_type);
+ M: Jan Kiszka <jan.kiszka@web.de>
-         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
++M: Peter Maydell <peter.maydell@linaro.org>
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+ L: qemu-arm@nongnu.org
-     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+-S: Maintained
-         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
++S: Odd Fixes
+ F: hw/arm/musicpal.c
--    for (n = 0; n < BCM2836_NCPUS; n++) {
-+    for (n = 0; n < BCM283X_NCPUS; n++) {
+ nSeries
-         /* Mirror bcm2836, which has clusterid set to 0xf
+ M: Andrzej Zaborowski <balrogg@gmail.com>
-          * TODO: this should be converted to a property of ARM_CPU
++M: Peter Maydell <peter.maydell@linaro.org>
-          */
+ L: qemu-arm@nongnu.org
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+-S: Maintained
- }
++S: Odd Fixes
+ F: hw/arm/nseries.c
- static Property bcm2836_props[] = {
--    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
+ Palm
--    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+ M: Andrzej Zaborowski <balrogg@gmail.com>
-+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
++M: Peter Maydell <peter.maydell@linaro.org>
-+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+ L: qemu-arm@nongnu.org
-+                       BCM283X_NCPUS),
+-S: Maintained
-     DEFINE_PROP_END_OF_LIST()
++S: Odd Fixes
- };
+ F: hw/arm/palm.c
-@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+ Raspberry Pi
- }
+@@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h
- static const TypeInfo bcm2836_type_info = {
+ PXA2XX
--    .name = TYPE_BCM2836,
+ M: Andrzej Zaborowski <balrogg@gmail.com>
-+    .name = TYPE_BCM283X,
++M: Peter Maydell <peter.maydell@linaro.org>
-     .parent = TYPE_DEVICE,
+ L: qemu-arm@nongnu.org
--    .instance_size = sizeof(BCM2836State),
+-S: Maintained
-+    .instance_size = sizeof(BCM283XState),
++S: Odd Fixes
-     .instance_init = bcm2836_init,
+ F: hw/arm/mainstone.c
-     .class_init = bcm2836_class_init,
+ F: hw/arm/spitz.c
- };
+ F: hw/arm/tosa.c
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h
-index XXXXXXX..XXXXXXX 100644
+ Xilinx Zynq
---- a/hw/arm/raspi.c
+ M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-+++ b/hw/arm/raspi.c
+ M: Alistair Francis <alistair@alistair23.me>
-@@ -XXX,XX +XXX,XX @@
++M: Peter Maydell <peter.maydell@linaro.org>
- static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
+ L: qemu-arm@nongnu.org
+ S: Maintained
- typedef struct RasPiState {
+ F: hw/*/xilinx_*
--    BCM2836State soc;
+@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
-+    BCM283XState soc;
+ Xilinx ZynqMP
-     MemoryRegion ram;
+ M: Alistair Francis <alistair@alistair23.me>
- } RasPiState;
+ M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
-@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+ L: qemu-arm@nongnu.org
-     BusState *bus;
+ S: Maintained
-     DeviceState *carddev;
+ F: hw/*/xlnx*.c
+@@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c
--    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
-+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+ STM32F205
-     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
+ M: Alistair Francis <alistair@alistair23.me>
-                               &error_abort);
++M: Peter Maydell <peter.maydell@linaro.org>
+ S: Maintained
-@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
+ F: hw/arm/stm32f205_soc.c
-     mc->no_floppy = 1;
+ F: hw/misc/stm32f2xx_syscfg.c
-     mc->no_cdrom = 1;
+@@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
--    mc->max_cpus = BCM2836_NCPUS;
+ Netduino 2
--    mc->min_cpus = BCM2836_NCPUS;
+ M: Alistair Francis <alistair@alistair23.me>
--    mc->default_cpus = BCM2836_NCPUS;
++M: Peter Maydell <peter.maydell@linaro.org>
-+    mc->max_cpus = BCM283X_NCPUS;
+ S: Maintained
-+    mc->min_cpus = BCM283X_NCPUS;
+ F: hw/arm/netduino2.c
-+    mc->default_cpus = BCM283X_NCPUS;
-     mc->default_ram_size = 1024 * 1024 * 1024;
+ SmartFusion2
-     mc->ignore_memory_transaction_failures = true;
+ M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
- };
++M: Peter Maydell <peter.maydell@linaro.org>
-@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
+ S: Maintained
-     mc->no_floppy = 1;
+ F: hw/arm/msf2-soc.c
-     mc->no_cdrom = 1;
+ F: hw/misc/msf2-sysreg.c
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
+@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h
--    mc->max_cpus = BCM2836_NCPUS;
--    mc->min_cpus = BCM2836_NCPUS;
+ Emcraft M2S-FG484
--    mc->default_cpus = BCM2836_NCPUS;
+ M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
-+    mc->max_cpus = BCM283X_NCPUS;
++M: Peter Maydell <peter.maydell@linaro.org>
-+    mc->min_cpus = BCM283X_NCPUS;
+ S: Maintained
-+    mc->default_cpus = BCM283X_NCPUS;
+ F: hw/arm/msf2-som.c
-     mc->default_ram_size = 1024 * 1024 * 1024;
- }
+ ASPEED BMCs
- DEFINE_MACHINE("raspi3", raspi3_machine_init)
+ M: Cédric Le Goater <clg@kaod.org>
 +M: Peter Maydell <peter.maydell@linaro.org>
  R: Andrew Jeffery <andrew@aj.id.au>
  R: Joel Stanley <joel@jms.id.au>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h
  NRF51
  M: Joel Stanley <joel@jms.id.au>
 +M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/arm/nrf51_soc.c
 --
-.16.2
+.19.1

Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3

----------------------------------------------------------------
Andrey Smirnov (2):
      char: i.MX: Simplify imx_update()
      char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
      fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
      hw/arm/bcm2386: Fix parent type of bcm2386
      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
      hw/arm/bcm2836: Create proper bcm2837 device
      hw/arm/bcm2836: Use correct affinity values for BCM2837
      hw/arm/bcm2836: Hardcode correct CPU type
      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
      dump: Update correct kdump phys_base field for AArch64

From: Guenter Roeck <linux@roeck-us.net>

The sabrelite machine model used by qemu-system-arm is based on the
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
controller which is supported in QEMU using the imx_fec.c module
(actually called imx.enet for this model.)

The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
imx.enet device like this:

#define FSL_IMX6_ENET_MAC_1588_IRQ 118
 #define FSL_IMX6_ENET_MAC_IRQ 119

According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
interrupts are as follows.

150 ENET MAC 0 IRQ
151 ENET MAC 0 1588 Timer interrupt

where

150 - 32 == 118
151 - 32 == 119

In other words, the vector definitions in the fsl-imx6.h file are reversed.

Fixing the interrupts alone causes problems with older Linux kernels:
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
error handling. This is a Linux kernel problem, not a qemu problem:
the Linux kernel only worked by accident since it requested both interrupts.

For backward compatibility, generate the Ethernet interrupt on both interrupt
lines. This was shown to work from all Linux kernel releases starting with
v3.16.

Link: https://bugs.launchpad.net/qemu/+bug/1753309
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  4 ++--
 hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
 #define FSL_IMX6_HDMI_MASTER_IRQ 115
 #define FSL_IMX6_HDMI_CEC_IRQ 116
 #define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
-#define FSL_IMX6_ENET_MAC_IRQ 119
+#define FSL_IMX6_ENET_MAC_IRQ 118
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
 #define FSL_IMX6_PCIE1_IRQ 120
 #define FSL_IMX6_PCIE2_IRQ 121
 #define FSL_IMX6_PCIE3_IRQ 122
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
 
 static void imx_eth_update(IMXFECState *s)
 {
-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+    /*
+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+     * interrupts swapped. This worked with older versions of Linux (4.14
+     * and older) since Linux associated both interrupt lines with Ethernet
+     * MAC interrupts. Specifically,
+     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
+     *   timer interrupts. Those versions of Linux fail with versions of QEMU
+     *   with swapped interrupt assignments.
+     * - In linux 4.14, both interrupt lines were registered with the Ethernet
+     *   MAC interrupt handler. As a result, all versions of qemu happen to
+     *   work, though that is accidental.
+     * - In Linux 4.9 and older, the timer interrupt was registered directly
+     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
+     *   redirected to a GPIO interrupt to work around erratum ERR006687.
+     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
+     *   interrupt never fired since IOMUX is currently not supported in qemu.
+     *   Linux instead received MAC interrupts on the timer interrupt.
+     *   As a result, qemu versions with the swapped interrupt assignment work,
+     *   albeit accidentally, but qemu versions with the correct interrupt
+     *   assignment fail.
+     *
+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
+     * interrrupts on both interrupt lines. This should be changed if and when
+     * qemu supports IOMUX.
+     */
+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
         qemu_set_irq(s->irq[1], 1);
     } else {
         qemu_set_irq(s->irq[1], 0);
-- 
2.16.2

From: Wei Huang <wei@redhat.com>

For guest kernel that supports KASLR, the load address can change every
time when guest VM runs. To find the physical base address correctly,
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
However this string pattern is only available on x86_64. AArch64 uses a
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
QEMU dump uses the correct string on AArch64.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 dump.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/dump.c b/dump.c
index XXXXXXX..XXXXXXX 100644
--- a/dump.c
+++ b/dump.c
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
 
     lines = g_strsplit((char *)vmci, "\n", -1);
     for (i = 0; lines[i]; i++) {
-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+        const char *prefix = NULL;
+
+        if (s->dump_info.d_machine == EM_X86_64) {
+            prefix = "NUMBER(phys_base)=";
+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+            prefix = "NUMBER(PHYS_OFFSET)=";
+        }
+
+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
                               &phys_base) < 0) {
-                warn_report("Failed to read NUMBER(phys_base)=");
+                warn_report("Failed to read %s", prefix);
             } else {
                 s->dump_info.phys_base = phys_base;
             }
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Code of imx_update() is slightly confusing since the "flags" variable
doesn't really corespond to anything in real hardware and server as a
kitchensink accumulating events normally reported via USR1 and USR2
registers.

Change the code to explicitly evaluate state of interrupts reported
via USR1 and USR2 against corresponding masking bits and use the to
detemine if IRQ line should be asserted or not.

NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
reasons:

1. Emulation code implements a single character FIFO, so this flag
       will always be set since characters are trasmitted as a part of
       the code emulating "push" into the FIFO

2. imx_update() is really just a function doing ORing and maksing
       of reported events, so checking for UTS1_TXEMPTY should happen,
       if it's ever really needed should probably happen outside of
       it.

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/imx_serial.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
 
 static void imx_update(IMXSerialState *s)
 {
-    uint32_t flags;
+    uint32_t usr1;
+    uint32_t usr2;
+    uint32_t mask;
 
-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
-    if (s->ucr1 & UCR1_TXMPTYEN) {
-        flags |= (s->uts1 & UTS1_TXEMPTY);
-    } else {
-        flags &= ~USR1_TRDY;
-    }
+    /*
+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+     * UCR1, so we can get away with something as simple as the
+     * following:
+     */
+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+    /*
+     * Bits that we want in USR2 are not as conveniently laid out,
+     * unfortunately.
+     */
+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    usr2 = s->usr2 & mask;
 
-    qemu_set_irq(s->irq, !!flags);
+    qemu_set_irq(s->irq, usr1 || usr2);
 }
 
 static void imx_serial_reset(IMXSerialState *s)
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.

Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/imx_serial.h |  3 +++
 hw/char/imx_serial.c         | 20 +++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -XXX,XX +XXX,XX @@
 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
 #define UCR2_SRST       (1<<0)    /* Reset complete */
 
+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+
 #define UTS1_TXEMPTY    (1<<6)
 #define UTS1_RXEMPTY    (1<<5)
 #define UTS1_TXFULL     (1<<4)
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
     uint32_t ubmr;
     uint32_t ubrc;
     uint32_t ucr3;
+    uint32_t ucr4;
 
     qemu_irq irq;
     CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
 
 static const VMStateDescription vmstate_imx_serial = {
     .name = TYPE_IMX_SERIAL,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_INT32(readbuff, IMXSerialState),
         VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
         VMSTATE_UINT32(ubmr, IMXSerialState),
         VMSTATE_UINT32(ubrc, IMXSerialState),
         VMSTATE_UINT32(ucr3, IMXSerialState),
+        VMSTATE_UINT32(ucr4, IMXSerialState),
         VMSTATE_END_OF_LIST()
     },
 };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
      * unfortunately.
      */
     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    /*
+     * TCEN and TXDC are both bit 3
+     */
+    mask |= s->ucr4 & UCR4_TCEN;
+
     usr2 = s->usr2 & mask;
 
     qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
         return s->ucr3;
 
     case 0x23: /* UCR4 */
+        return s->ucr4;
+
     case 0x29: /* BRM Incremental */
         return 0x0; /* TODO */
 
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
              * qemu_chr_fe_write and background I/O callbacks */
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->usr1 &= ~USR1_TRDY;
+            s->usr2 &= ~USR2_TXDC;
             imx_update(s);
             s->usr1 |= USR1_TRDY;
+            s->usr2 |= USR2_TXDC;
             imx_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
         s->ucr3 = value & 0xffff;
         break;
 
-    case 0x2d: /* UTS1 */
     case 0x23: /* UCR4 */
+        s->ucr4 = value & 0xffff;
+        imx_update(s);
+        break;
+
+    case 0x2d: /* UTS1 */
         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
         /* TODO */
-- 
2.16.2

For the rpi1 and 2 we want to boot the Linux kernel via some
custom setup code that makes sure that the SMC instruction
acts as a no-op, because it's used for cache maintenance.
The rpi3 boots AArch64 kernels, which don't need SMC for
cache maintenance and always expect to be booted non-secure.
Don't fill in the aarch32-specific parts of the binfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     binfo.board_id = raspi_boardid[version];
     binfo.ram_size = ram_size;
     binfo.nb_cpus = smp_cpus;
-    binfo.board_setup_addr = BOARDSETUP_ADDR;
-    binfo.write_board_setup = write_board_setup;
-    binfo.secure_board_setup = true;
-    binfo.secure_boot = true;
+
+    if (version <= 2) {
+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         * mode before booting a kernel (to set up the SMC vectors so
+         * that we get a no-op SMC; this is used by Linux to call the
+         * firmware for some cache maintenance operations.
+         * The rpi3 doesn't need this.
+         */
+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+        binfo.write_board_setup = write_board_setup;
+        binfo.secure_board_setup = true;
+        binfo.secure_boot = true;
+    }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-- 
2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,
the board code has not mistakenly set either secure_boot or
secure_board_setup. It doesn't make sense to set secure_boot,
because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but
we don't currently support that, because only the AArch32
bootloader[] code calls this hook; bootloader_aarch64[] does not.
Since we don't have a current need for this functionality, just
assert that we don't try to use it. If it's needed we'll add
it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     } else {
                         env->pstate = PSTATE_MODE_EL1h;
                     }
+                    /* AArch64 kernels never boot in secure mode */
+                    assert(!info->secure_boot);
+                    /* This hook is only supported for AArch32 currently:
+                     * bootloader_aarch64[] will not call the hook, and
+                     * the code above has already dropped us into EL2 or EL1.
+                     */
+                    assert(!info->secure_board_setup);
                 }
 
                 /* Set to non-secure if not a secure boot */
-- 
2.16.2

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

The TypeInfo and state struct for bcm2386 disagree about what the
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
but the BCM2386State struct only defines the parent_obj field
as DeviceState. This would have caused problems if anything
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
need any of the additional functionality TYPE_SYS_BUS_DEVICE
provides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo bcm2836_type_info = {
     .name = TYPE_BCM2836,
-    .parent = TYPE_SYS_BUS_DEVICE,
+    .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM2836State),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
-- 
2.16.2

Our BCM2836 type is really a generic one that can be any of
the bcm283x family. Rename it accordingly. We change only
the names which are visible via the header file to the
rest of the QEMU code, leaving private function names
in bcm2836.c as they are.

This is a preliminary to making bcm283x be an abstract
parent class to specific types for the bcm2836 and bcm2837.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 12 ++++++------
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           | 16 ++++++++--------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
-#define TYPE_BCM2836 "bcm2836"
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+#define TYPE_BCM283X "bcm283x"
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 
-#define BCM2836_NCPUS 4
+#define BCM283X_NCPUS 4
 
-typedef struct BCM2836State {
+typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
     char *cpu_type;
     uint32_t enabled_cpus;
 
-    ARMCPU cpus[BCM2836_NCPUS];
+    ARMCPU cpus[BCM283X_NCPUS];
     BCM2836ControlState control;
     BCM2835PeripheralState peripherals;
-} BCM2836State;
+} BCM283XState;
 
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 static void bcm2836_init(Object *obj)
 {
-    BCM2836State *s = BCM2836(obj);
+    BCM283XState *s = BCM283X(obj);
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
 
 static void bcm2836_realize(DeviceState *dev, Error **errp)
 {
-    BCM2836State *s = BCM2836(dev);
+    BCM283XState *s = BCM283X(dev);
     Object *obj;
     Error *err = NULL;
     int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     /* common peripherals from bcm2835 */
 
     obj = OBJECT(dev);
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                           s->cpu_type);
         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         /* Mirror bcm2836, which has clusterid set to 0xf
          * TODO: this should be converted to a property of ARM_CPU
          */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                       BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 }
 
 static const TypeInfo bcm2836_type_info = {
-    .name = TYPE_BCM2836,
+    .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
-    .instance_size = sizeof(BCM2836State),
+    .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
 
 typedef struct RasPiState {
-    BCM2836State soc;
+    BCM283XState soc;
     MemoryRegion ram;
 } RasPiState;
 
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
 }
 DEFINE_MACHINE("raspi3", raspi3_machine_init)
-- 
2.16.2

The bcm2837 is pretty similar to the bcm2836, but it does have
some differences. Notably, the MPIDR affinity aff1 values it
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
uses, and if this is wrong Linux will not boot.

Rather than trying to have one device with properties that
configure it differently for the two cases, create two
separate QOM devices for the two SoCs. We use the same approach
as hw/arm/aspeed_soc.c and share code and have a data table
that might differ per-SoC. For the moment the two types don't
actually have different behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
 hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
 hw/arm/raspi.c           |  3 ++-
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 
 #define BCM283X_NCPUS 4
 
+/* These type names are for specific SoCs; other than instantiating
+ * them, code using these devices should always handle them via the
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ */
+#define TYPE_BCM2836 "bcm2836"
+#define TYPE_BCM2837 "bcm2837"
+
 typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
     BCM2835PeripheralState peripherals;
 } BCM283XState;
 
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+    DeviceClass parent_class;
+    const BCM283XInfo *info;
+} BCM283XClass;
+
+#define BCM283X_CLASS(klass) \
+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
 #define BCM2836_CONTROL_BASE    0x40000000
 
+struct BCM283XInfo {
+    const char *name;
+};
+
+static const BCM283XInfo bcm283x_socs[] = {
+    {
+        .name = TYPE_BCM2836,
+    },
+    {
+        .name = TYPE_BCM2837,
+    },
+};
+
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void bcm2836_class_init(ObjectClass *oc, void *data)
+static void bcm283x_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
+    BCM283XClass *bc = BCM283X_CLASS(oc);
 
-    dc->props = bcm2836_props;
+    bc->info = data;
     dc->realize = bcm2836_realize;
+    dc->props = bcm2836_props;
 }
 
-static const TypeInfo bcm2836_type_info = {
+static const TypeInfo bcm283x_type_info = {
     .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
-    .class_init = bcm2836_class_init,
+    .class_size = sizeof(BCM283XClass),
+    .abstract = true,
 };
 
 static void bcm2836_register_types(void)
 {
-    type_register_static(&bcm2836_type_info);
+    int i;
+
+    type_register_static(&bcm283x_type_info);
+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+        TypeInfo ti = {
+            .name = bcm283x_socs[i].name,
+            .parent = TYPE_BCM283X,
+            .class_init = bcm283x_class_init,
+            .class_data = (void *) &bcm283x_socs[i],
+        };
+        type_register(&ti);
+    }
 }
 
 type_init(bcm2836_register_types)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+    object_initialize(&s->soc, sizeof(s->soc),
+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
-- 
2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
is required for Linux to boot.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Now we have separate types for BCM2386 and BCM2387, we might as well
just hard-code the CPU type they use rather than having it passed
through as an object property. This then lets us put the initialization
of the CPU object in init rather than realize.

Note that this change means that it's no longer possible on
the command line to use -cpu to ask for a different kind of
CPU than the SoC supports. This was never a supported thing to
do anyway; we were just not sanity-checking the command line.

This does require us to only build the bcm2837 object on
TARGET_AARCH64 configs, since otherwise it won't instantiate
due to the missing cortex-a53 device and "make check" will fail.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 24 +++++++++++++++---------
 hw/arm/raspi.c   |  2 --
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 struct BCM283XInfo {
     const char *name;
+    const char *cpu_type;
     int clusterid;
 };
 
 static const BCM283XInfo bcm283x_socs[] = {
     {
         .name = TYPE_BCM2836,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
         .clusterid = 0xf,
     },
+#ifdef TARGET_AARCH64
     {
         .name = TYPE_BCM2837,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
         .clusterid = 0x0,
     },
+#endif
 };
 
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+    const BCM283XInfo *info = bc->info;
+    int n;
+
+    for (n = 0; n < BCM283X_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          info->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
-    obj = OBJECT(dev);
-    for (n = 0; n < BCM283X_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          s->cpu_type);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
-
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                        BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
-                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
-- 
2.16.2

The raspi3 has AArch64 CPUs, which means that our smpboot
code for keeping the secondary CPUs in a pen needs to have
a version for A64 as well as A32. Without this, the
secondary CPUs go into an infinite loop of taking undefined
instruction exceptions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
 
 /* Table of Linux board IDs for different Pi versions */
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                        info->smp_loader_start);
 }
 
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+     * The mechanism for doing the spin-table is also entirely different.
+     * We must have four 64-bit fields at absolute addresses
+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+     * our CPUs, and which we must ensure are zero initialized before
+     * the primary CPU goes into the kernel. We put these variables inside
+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+     */
+    static const uint32_t smpboot[] = {
+        0xd2801b05, /*        mov     x5, 0xd8 */
+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+        0x924004c6, /*        and     x6, x6, #0x3 */
+        0xd503205f, /* spin:  wfe */
+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+        0xb4ffffc4, /*        cbz     x4, spin */
+        0xd2800000, /*        mov     x0, #0x0 */
+        0xd2800001, /*        mov     x1, #0x0 */
+        0xd2800002, /*        mov     x2, #0x0 */
+        0xd2800003, /*        mov     x3, #0x0 */
+        0xd61f0080, /*        br      x4 */
+    };
+
+    static const uint64_t spintables[] = {
+        0, 0, 0, 0
+    };
+
+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
+                       info->smp_loader_start);
+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+                       SPINTABLE_ADDR);
+}
+
 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
         binfo.smp_loader_start = SMPBOOT_ADDR;
-        binfo.write_secondary_boot = write_smpboot;
+        if (version == 2) {
+            binfo.write_secondary_boot = write_smpboot;
+        } else {
+            binfo.write_secondary_boot = write_smpboot64;
+        }
         binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
-- 
2.16.2

Some Arm bugfixes for rc2...

thanks
-- PMM

The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119

for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:

MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)

----------------------------------------------------------------
target-arm queue:
 * various MAINTAINERS file updates
 * hw/block/onenand: use qemu_log_mask() for reporting
 * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
   on the n800 and n810 machine models
 * target/arm: fix smc incorrectly trapping to EL3 when secure is off
 * hw/arm/stm32f205: Fix the UART and Timer region size
 * target/arm: read ID registers for KVM guests so they can be
   used to gate "is feature X present" checks

----------------------------------------------------------------
Luc Michel (1):
      target/arm: fix smc incorrectly trapping to EL3 when secure is off

Peter Maydell (3):
      hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
      hw/block/onenand: use qemu_log_mask() for reporting
      MAINTAINERS: list myself as maintainer for various Arm boards

Richard Henderson (4):
      target/arm: Install ARMISARegisters from kvm host
      target/arm: Fill in ARMISARegisters for kvm64
      target/arm: Introduce read_sys_reg32 for kvm32
      target/arm: Fill in ARMISARegisters for kvm32

Seth Kintigh (1):
      hw/arm/stm32f205: Fix the UART and Timer region size

Thomas Huth (1):
      MAINTAINERS: Add entries for missing ARM boards

target/arm/kvm_arm.h       |   1 +
 hw/block/onenand.c         |  24 +++++-----
 hw/char/stm32f2xx_usart.c  |   2 +-
 hw/timer/stm32f2xx_timer.c |   2 +-
 target/arm/kvm.c           |   1 +
 target/arm/kvm32.c         |  77 ++++++++++++++++++++------------
 target/arm/kvm64.c         |  90 +++++++++++++++++++++++++++++++++++++-
 target/arm/op_helper.c     |  54 +++++++++++++++++++----
 MAINTAINERS                | 106 +++++++++++++++++++++++++++++++++++++++------
 9 files changed, 293 insertions(+), 64 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

The ID registers are replacing (some of) the feature bits.
We need (some of) these values to determine the set of data
to be handled during migration.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h | 1 +
 target/arm/kvm.c     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
  * by asking the host kernel)
  */
 typedef struct ARMHostCPUFeatures {
+    ARMISARegisters isar;
     uint64_t features;
     uint32_t target;
     const char *dtb_compatible;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
 
     cpu->kvm_target = arm_host_cpu_features.target;
     cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
+    cpu->isar = arm_host_cpu_features.isar;
     env->features = arm_host_cpu_features.features;
 }
 
-- 
2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 88 insertions(+), 2 deletions(-)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature)
     *features &= ~(1ULL << feature);
 }
 
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
+{
+    uint64_t ret;
+    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
+    int err;
+
+    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
+    err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
+    if (err < 0) {
+        return -1;
+    }
+    *pret = ret;
+    return 0;
+}
+
+static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
+{
+    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
+
+    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
+    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
+}
+
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 {
     /* Identify the feature bits corresponding to the host CPU, and
      * fill out the ARMHostCPUClass fields accordingly. To do this
      * we have to create a scratch VM, create a single CPU inside it,
      * and then query that CPU for the relevant ID registers.
-     * For AArch64 we currently don't care about ID registers at
-     * all; we just want to know the CPU type.
      */
     int fdarray[3];
     uint64_t features = 0;
+    int err;
+
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
      * we know these will only support creating one kind of guest CPU,
      * which is its preferred CPU type. Fortunately these old kernels
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     ahcf->target = init.target;
     ahcf->dtb_compatible = "arm,arm-v8";
 
+    err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
+                         ARM64_SYS_REG(3, 0, 0, 4, 0));
+    if (unlikely(err < 0)) {
+        /*
+         * Before v4.15, the kernel only exposed a limited number of system
+         * registers, not including any of the interesting AArch64 ID regs.
+         * For the most part we could leave these fields as zero with minimal
+         * effect, since this does not affect the values seen by the guest.
+         *
+         * However, it could cause problems down the line for QEMU,
+         * so provide a minimal v8.0 default.
+         *
+         * ??? Could read MIDR and use knowledge from cpu64.c.
+         * ??? Could map a page of memory into our temp guest and
+         *     run the tiniest of hand-crafted kernels to extract
+         *     the values seen by the guest.
+         * ??? Either of these sounds like too much effort just
+         *     to work around running a modern host kernel.
+         */
+        ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
+        err = 0;
+    } else {
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
+                              ARM64_SYS_REG(3, 0, 0, 4, 1));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
+                              ARM64_SYS_REG(3, 0, 0, 6, 0));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
+                              ARM64_SYS_REG(3, 0, 0, 6, 1));
+
+        /*
+         * Note that if AArch32 support is not present in the host,
+         * the AArch32 sysregs are present to be read, but will
+         * return UNKNOWN values.  This is neither better nor worse
+         * than skipping the reads and leaving 0, as we must avoid
+         * considering the values in every case.
+         */
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
+                              ARM64_SYS_REG(3, 0, 0, 2, 0));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
+                              ARM64_SYS_REG(3, 0, 0, 2, 1));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
+                              ARM64_SYS_REG(3, 0, 0, 2, 2));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
+                              ARM64_SYS_REG(3, 0, 0, 2, 3));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
+                              ARM64_SYS_REG(3, 0, 0, 2, 4));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
+                              ARM64_SYS_REG(3, 0, 0, 2, 5));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
+                              ARM64_SYS_REG(3, 0, 0, 2, 7));
+
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
+                              ARM64_SYS_REG(3, 0, 0, 3, 0));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
+                              ARM64_SYS_REG(3, 0, 0, 3, 1));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
+                              ARM64_SYS_REG(3, 0, 0, 3, 2));
+    }
+
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
+    if (err < 0) {
+        return false;
+    }
+
    /* We can assume any KVM supporting CPU is at least a v8
      * with VFPv4+Neon; this in turn implies most of the other
      * feature bits.
-- 
2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

Assert that the value to be written is the correct size.
No change in functionality here, just mirroring the same
function from kvm64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm32.c | 41 ++++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 25 deletions(-)

diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature)
     *features |= 1ULL << feature;
 }
 
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
+{
+    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
+
+    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
+    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
+}
+
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 {
     /* Identify the feature bits corresponding to the host CPU, and
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      * we have to create a scratch VM, create a single CPU inside it,
      * and then query that CPU for the relevant ID registers.
      */
-    int i, ret, fdarray[3];
+    int err = 0, fdarray[3];
     uint32_t midr, id_pfr0, mvfr1;
     uint64_t features = 0;
+
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
      * we know these will only support creating one kind of guest CPU,
      * which is its preferred CPU type.
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         QEMU_KVM_ARM_TARGET_NONE
     };
     struct kvm_vcpu_init init;
-    struct kvm_one_reg idregs[] = {
-        {
-            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
-            | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
-            .addr = (uintptr_t)&midr,
-        },
-        {
-            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
-            | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
-            .addr = (uintptr_t)&id_pfr0,
-        },
-        {
-            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
-            | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
-            .addr = (uintptr_t)&mvfr1,
-        },
-    };
 
     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
         return false;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      */
     ahcf->dtb_compatible = "arm,arm-v7";
 
-    for (i = 0; i < ARRAY_SIZE(idregs); i++) {
-        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
-        if (ret) {
-            break;
-        }
-    }
+    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
+    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
+    err |= read_sys_reg32(fdarray[2], &mvfr1,
+                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
+                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
-    if (ret) {
+    if (err < 0) {
         return false;
     }
 
-- 
2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      * and then query that CPU for the relevant ID registers.
      */
     int err = 0, fdarray[3];
-    uint32_t midr, id_pfr0, mvfr1;
+    uint32_t midr, id_pfr0;
     uint64_t features = 0;
 
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 
     err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
     err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
-    err |= read_sys_reg32(fdarray[2], &mvfr1,
+
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
+                          ARM_CP15_REG32(0, 0, 2, 0));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
+                          ARM_CP15_REG32(0, 0, 2, 1));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
+                          ARM_CP15_REG32(0, 0, 2, 2));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
+                          ARM_CP15_REG32(0, 0, 2, 3));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
+                          ARM_CP15_REG32(0, 0, 2, 4));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
+                          ARM_CP15_REG32(0, 0, 2, 5));
+    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
+                       ARM_CP15_REG32(0, 0, 2, 7))) {
+        /*
+         * Older kernels don't support reading ID_ISAR6. This register was
+         * only introduced in ARMv8, so we can assume that it is zero on a
+         * CPU that a kernel this old is running on.
+         */
+        ahcf->isar.id_isar6 = 0;
+    }
+
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
+                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
+                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
+    /*
+     * FIXME: There is not yet a way to read MVFR2.
+     * Fortunately there is not yet anything in there that affects migration.
+     */
 
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     if (extract32(id_pfr0, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_THUMB2EE);
     }
-    if (extract32(mvfr1, 20, 4) == 1) {
+    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
         set_feature(&features, ARM_FEATURE_VFP_FP16);
     }
-    if (extract32(mvfr1, 12, 4) == 1) {
+    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_NEON);
     }
-    if (extract32(mvfr1, 28, 4) == 1) {
+    if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
         /* FMAC support implies VFPv4 */
         set_feature(&features, ARM_FEATURE_VFP4);
     }
-- 
2.19.1

From: Thomas Huth <thuth@redhat.com>

Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2",
"raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt".
While we're at it, also adjust the "i.MX31" section a little bit,
so that the wildcards there do not match anymore for unrelated files
(e.g. the new hw/misc/imx6ul_ccm.c file).

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 65 insertions(+), 5 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/arm/gumstix.c
 
-i.MX31
+i.MX31 (kzm)
 M: Peter Chubb <peter.chubb@nicta.com.au>
 L: qemu-arm@nongnu.org
-S: Odd fixes
-F: hw/*/imx*
-F: include/hw/*/imx*
+S: Odd Fixes
 F: hw/arm/kzm.c
-F: include/hw/arm/fsl-imx31.h
+F: hw/*/imx_*
+F: hw/*/*imx31*
+F: include/hw/*/imx_*
+F: include/hw/*/*imx31*
 
 Integrator CP
 M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/arm/integratorcp.c
 F: hw/misc/arm_integrator_debug.c
 
+MCIMX6UL EVK / i.MX6ul
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/mcimx6ul-evk.c
+F: hw/arm/fsl-imx6ul.c
+F: hw/misc/imx6ul_ccm.c
+F: include/hw/arm/fsl-imx6ul.h
+F: include/hw/misc/imx6ul_ccm.h
+
+MCIMX7D SABRE / i.MX7
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Andrey Smirnov <andrew.smirnov@gmail.com>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/mcimx7d-sabre.c
+F: hw/arm/fsl-imx7.c
+F: include/hw/arm/fsl-imx7.h
+F: hw/pci-host/designware.c
+F: include/hw/pci-host/designware.h
+
 MPS2
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/palm.c
 
+Raspberry Pi
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Andrew Baumann <Andrew.Baumann@microsoft.com>
+R: Philippe Mathieu-Daudé <f4bug@amsat.org>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/raspi_platform.h
+F: hw/*/bcm283*
+F: include/hw/arm/raspi*
+F: include/hw/*/bcm283*
+
 Real View
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx*
 F: hw/misc/mst_fpga.c
 F: include/hw/arm/pxa.h
 
+SABRELITE / i.MX6
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/sabrelite.c
+F: hw/arm/fsl-imx6.c
+F: hw/misc/imx6_src.c
+F: hw/ssi/imx_spi.c
+F: include/hw/arm/fsl-imx6.h
+F: include/hw/misc/imx6_src.h
+F: include/hw/ssi/imx_spi.h
+
 Sharp SL-5500 (Collie) PDA
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/stellaris*
 
+Versatile Express
+M: Peter Maydell <peter.maydell@linaro.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/vexpress.c
+
 Versatile PB
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/*/versatile*
 F: hw/misc/arm_sysctl.c
 
+Virt
+M: Peter Maydell <peter.maydell@linaro.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/virt*
+F: include/hw/arm/virt.h
+
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 M: Alistair Francis <alistair@alistair23.me>
-- 
2.19.1

From: Seth Kintigh <skintigh@gmail.com>

The UART and timer devices for the stm32f205 were being created
with memory regions that were too large. Use the size specified
in the chip datasheet.

The old sizes were so large that the devices would overlap with
each other in the SoC memory map, so this fixes a bug that
caused odd behavior and/or crashes when trying to set up multiple
UARTs.

Signed-off-by: Seth Kintigh <skintigh@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: rephrased commit message to follow our usual standard]
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/stm32f2xx_usart.c  | 2 +-
 hw/timer/stm32f2xx_timer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/stm32f2xx_usart.c
+++ b/hw/char/stm32f2xx_usart.c
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj)
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 
     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
-                          TYPE_STM32F2XX_USART, 0x2000);
+                          TYPE_STM32F2XX_USART, 0x400);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj)
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 
     memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
-                          "stm32f2xx_timer", 0x4000);
+                          "stm32f2xx_timer", 0x400);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 
     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
-- 
2.19.1

From: Luc Michel <luc.michel@greensocs.com>

This commit fixes a case where the CPU would try to go to EL3 when
executing an smc instruction, even though ARM_FEATURE_EL3 is false. This
case is raised when the PSCI conduit is set to smc, but the smc
instruction does not lead to a valid PSCI call.

QEMU crashes with an assertion failure latter on because of incoherent
mmu_idx.

This commit refactors the pre_smc helper by enumerating all the possible
way of handling an scm instruction, and covering the previously missing
case leading to the crash.

The following minimal test would crash before this commit:

.global _start
    .text
_start:
    ldr x0, =0xdeadbeef  ; invalid PSCI call
    smc #0

run with the following command line:

aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \
                      -o test test.s

qemu-system-aarch64 -M virt,virtualization=on,secure=off \
                    -cpu cortex-a57 -kernel test

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20181117160213.18995-1-luc.michel@greensocs.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++-------
 1 file changed, 46 insertions(+), 8 deletions(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
     ARMCPU *cpu = arm_env_get_cpu(env);
     int cur_el = arm_current_el(env);
     bool secure = arm_is_secure(env);
-    bool smd = env->cp15.scr_el3 & SCR_SMD;
+    bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
+
+    /*
+     * SMC behaviour is summarized in the following table.
+     * This helper handles the "Trap to EL2" and "Undef insn" cases.
+     * The "Trap to EL3" and "PSCI call" cases are handled in the exception
+     * helper.
+     *
+     *  -> ARM_FEATURE_EL3 and !SMD
+     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
+     *
+     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
+     *  Conduit SMC, inval call  Trap to EL2         Trap to EL3
+     *  Conduit not SMC          Trap to EL2         Trap to EL3
+     *
+     *
+     *  -> ARM_FEATURE_EL3 and SMD
+     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
+     *
+     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
+     *  Conduit SMC, inval call  Trap to EL2         Undef insn
+     *  Conduit not SMC          Trap to EL2         Undef insn
+     *
+     *
+     *  -> !ARM_FEATURE_EL3
+     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
+     *
+     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
+     *  Conduit SMC, inval call  Trap to EL2         Undef insn
+     *  Conduit not SMC          Undef insn          Undef insn
+     */
+
     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
      * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
      *  extensions, SMD only applies to NS state.
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
      * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
      * so we need not special case this here.
      */
-    bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
+    bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag
+                                                     : smd_flag && !secure;
 
     if (!arm_feature(env, ARM_FEATURE_EL3) &&
         cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
          * to forbid its EL1 from making PSCI calls into QEMU's
          * "firmware" via HCR.TSC, so for these purposes treat
          * PSCI-via-SMC as implying an EL3.
+         * This handles the very last line of the previous table.
          */
-        undef = true;
-    } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
+        raise_exception(env, EXCP_UDEF, syn_uncategorized(),
+                        exception_target_el(env));
+    }
+
+    if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
         /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
          * We also want an EL2 guest to be able to forbid its EL1 from
          * making PSCI calls into QEMU's "firmware" via HCR.TSC.
+         * This handles all the "Trap to EL2" cases of the previous table.
          */
         raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
     }
 
-    /* If PSCI is enabled and this looks like a valid PSCI call then
-     * suppress the UNDEF -- we'll catch the SMC exception and
-     * implement the PSCI call behaviour there.
+    /* Catch the two remaining "Undef insn" cases of the previous table:
+     *    - PSCI conduit is SMC but we don't have a valid PCSI call,
+     *    - We don't have EL3 or SMD is set.
      */
-    if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) {
+    if (!arm_is_psci_call(cpu, EXCP_SMC) &&
+        (smd || !arm_feature(env, ARM_FEATURE_EL3))) {
         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
                         exception_target_el(env));
     }
-- 
2.19.1

An off-by-one error in a switch case in onenand_read() allowed
a misbehaving guest to read off the end of a block of memory.

NB: the onenand device is used only by the "n800" and "n810"
machines, which are usable only with TCG, not KVM, so this is
not a security issue.

Reported-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20181115143535.5885-2-peter.maydell@linaro.org
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/onenand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/block/onenand.c b/hw/block/onenand.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/onenand.c
+++ b/hw/block/onenand.c
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
     int offset = addr >> s->shift;
 
     switch (offset) {
-    case 0x0000 ... 0xc000:
+    case 0x0000 ... 0xbffe:
         return lduw_le_p(s->boot[0] + addr);
 
     case 0xf000:	/* Manufacturer ID */
-- 
2.19.1

Update the onenand device to use qemu_log_mask() for reporting
guest errors and unimplemented features, rather than plain
fprintf() and hw_error().

(We leave the hw_error() in onenand_reset(), as that is
triggered by a failure to read the underlying block device
for the bootRAM, not by guest action.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20181115143535.5885-3-peter.maydell@linaro.org
---
 hw/block/onenand.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/hw/block/onenand.c b/hw/block/onenand.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/onenand.c
+++ b/hw/block/onenand.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "hw/sysbus.h"
 #include "qemu/error-report.h"
+#include "qemu/log.h"
 
 /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
 #define PAGE_SHIFT	11
@@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s)
     default:
         s->status |= ONEN_ERR_CMD;
         s->intstatus |= ONEN_INT;
-        fprintf(stderr, "%s: unknown OneNAND command %x\n",
-                        __func__, s->command);
+        qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
+                      s->command);
     }
 
     onenand_intr_update(s);
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
     case 0xff02:	/* ECC Result of spare area data */
     case 0xff03:	/* ECC Result of main area data */
     case 0xff04:	/* ECC Result of spare area data */
-        hw_error("%s: implement ECC\n", __func__);
+        qemu_log_mask(LOG_UNIMP,
+                      "onenand: ECC result registers unimplemented\n");
         return 0x0000;
     }
 
-    fprintf(stderr, "%s: unknown OneNAND register %x\n",
-                    __func__, offset);
+    qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n",
+                  offset);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
             break;
 
         default:
-            fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
-                            __func__, value);
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "unknown OneNAND boot command %" PRIx64 "\n",
+                          value);
         }
         break;
 
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        fprintf(stderr, "%s: unknown OneNAND register %x\n",
-                        __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "write to unknown OneNAND register 0x%x\n",
+                      offset);
     }
 }
 
-- 
2.19.1

In practice for most of the more-or-less orphan Arm board models,
I will review patches and put them in via the target-arm tree.
So list myself as an "Odd Fixes" status maintainer for them.

This commit downgrades these boards to "Odd Fixes":
 * Allwinner-A10
 * Exynos
 * Calxeda Highbank
 * Canon DIGIC
 * Musicpal
 * nSeries
 * Palm
 * PXA2xx

These boards were already "Odd Fixes":
 * Gumstix
 * i.MX31 (kzm)

Philippe Mathieu-Daudé has requested to be moved to R:
status for Gumstix now that I am listed as the M: contact.

Some boards are maintained, but their patches still go
via the target-arm tree, so add myself as a secondary
maintainer contact for those:
 * Xilinx Zynq
 * Xilinx ZynqMP
 * STM32F205
 * Netduino 2
 * SmartFusion2
 * Mecraft M2S-FG484
 * ASPEED BMCs
 * NRF51

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20181108134139.31666-1-peter.maydell@linaro.org
---
 MAINTAINERS | 36 +++++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ ARM Machines
 ------------
 Allwinner-a10
 M: Beniamino Galvani <b.galvani@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/*/allwinner*
 F: include/hw/*/allwinner*
 F: hw/arm/cubieboard.c
@@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c
 
 Exynos
 M: Igor Mitsyanko <i.mitsyanko@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/*/exynos*
 F: include/hw/arm/exynos4210.h
 
 Calxeda Highbank
 M: Rob Herring <robh@kernel.org>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/highbank.c
 F: hw/net/xgmac.c
 
 Canon DIGIC
 M: Antony Pavlov <antonynpavlov@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: include/hw/arm/digic.h
 F: hw/*/digic*
 
 Gumstix
-M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Philippe Mathieu-Daudé <f4bug@amsat.org>
 L: qemu-devel@nongnu.org
 L: qemu-arm@nongnu.org
 S: Odd Fixes
@@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c
 
 i.MX31 (kzm)
 M: Peter Chubb <peter.chubb@nicta.com.au>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/arm/kzm.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h
 
 Musicpal
 M: Jan Kiszka <jan.kiszka@web.de>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/musicpal.c
 
 nSeries
 M: Andrzej Zaborowski <balrogg@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/nseries.c
 
 Palm
 M: Andrzej Zaborowski <balrogg@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/palm.c
 
 Raspberry Pi
@@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h
 
 PXA2XX
 M: Andrzej Zaborowski <balrogg@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/mainstone.c
 F: hw/arm/spitz.c
 F: hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/xilinx_*
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
 Xilinx ZynqMP
 M: Alistair Francis <alistair@alistair23.me>
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/xlnx*.c
@@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c
 
 STM32F205
 M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/stm32f205_soc.c
 F: hw/misc/stm32f2xx_syscfg.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h
 
 Netduino 2
 M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/netduino2.c
 
 SmartFusion2
 M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/msf2-soc.c
 F: hw/misc/msf2-sysreg.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h
 
 Emcraft M2S-FG484
 M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/msf2-som.c
 
 ASPEED BMCs
 M: Cédric Le Goater <clg@kaod.org>
+M: Peter Maydell <peter.maydell@linaro.org>
 R: Andrew Jeffery <andrew@aj.id.au>
 R: Joel Stanley <joel@jms.id.au>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h
 
 NRF51
 M: Joel Stanley <joel@jms.id.au>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/nrf51_soc.c
-- 
2.19.1