target-arm queue: a smallish set of patches for rc1 tomorrow.

I've included the tcg patches because RTH has no others that

would merit a pullreq.

I haven't included Thomas Huth's 17-patch set to deal with

the introspection crashes, to give that a little more time

on-list for review.

The following changes since commit 102ad0a80f5110483efd06877c29c4236be267f9:

Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-07-16' into staging (2018-07-16 15:34:38 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180716

for you to fetch changes up to 3474c98a2a2afcefa7c665f02ad2bed2a43ab0f7:

accel/tcg: Assert that tlb fill gave us a valid TLB entry (2018-07-16 17:26:01 +0100)

* accel/tcg: Use correct test when looking in victim TLB for code

* bcm2835_aux: Swap RX and TX interrupt assignments

* hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false

* hw/intc/arm_gic: Fix handling of GICD_ITARGETSR

* hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()

* aspeed: Implement write-1-{set, clear} for AST2500 strapping

* target/arm: Fix LD1W and LDFF1W (scalar plus vector)

Andrew Jeffery (1):

aspeed: Implement write-1-{set, clear} for AST2500 strapping

bcm2835_aux: Swap RX and TX interrupt assignments

Peter Maydell (4):

hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()

hw/intc/arm_gic: Fix handling of GICD_ITARGETSR

accel/tcg: Use correct test when looking in victim TLB for code

accel/tcg: Assert that tlb fill gave us a valid TLB entry

Richard Henderson (1):

target/arm: Fix LD1W and LDFF1W (scalar plus vector)

Thomas Huth (1):

hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false

From: Richard Henderson <richard.henderson@linaro.org>

'I' was being double-incremented; correctly within the inner loop

and incorrectly within the outer loop.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180711103957.3040-1-richard.henderson@linaro.org

target/arm/sve_helper.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c

--- a/target/arm/sve_helper.c

+++ b/target/arm/sve_helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \

intptr_t i, oprsz = simd_oprsz(desc); \

unsigned scale = simd_data(desc); \

uintptr_t ra = GETPC(); \

- for (i = 0; i < oprsz; i++) { \

+ for (i = 0; i < oprsz; ) { \

uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \

do { \

TYPEM m = 0; \

@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \

uintptr_t ra = GETPC(); \

bool first = true; \

mmap_lock(); \

- for (i = 0; i < oprsz; i++) { \

+ for (i = 0; i < oprsz; ) { \

uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \

do { \

TYPEM m = 0; \

2.17.1

From: Andrew Jeffery <andrew@aj.id.au>

The AST2500 SoC family changes the runtime behaviour of the hardware

strapping register (SCU70) to write-1-set/write-1-clear, with

write-1-clear implemented on the "read-only" SoC revision register

(SCU7C). For the the AST2400, the hardware strapping is

runtime-configured with read-modify-write semantics.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-id: 20180709143524.17480-1-andrew@aj.id.au

include/hw/misc/aspeed_scu.h | 2 ++

hw/misc/aspeed_scu.c | 19 +++++++++++++++++--

2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h

--- a/include/hw/misc/aspeed_scu.h

+++ b/include/hw/misc/aspeed_scu.h

@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {

#define AST2500_A0_SILICON_REV 0x04000303U

#define AST2500_A1_SILICON_REV 0x04010303U

+#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)

extern bool is_supported_silicon_rev(uint32_t silicon_rev);

#define ASPEED_SCU_PROT_KEY 0x1688A8A8

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,

s->regs[reg] = data;

aspeed_scu_set_apb_freq(s);

break;

-

+ case HW_STRAP1:

+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {

+ s->regs[HW_STRAP1] |= data;

+ return;

+ /* Jump to assignment below */

+ break;

+ case SILICON_REV:

+ if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {

+ s->regs[HW_STRAP1] &= ~data;

+ } else {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

+ }

+ /* Avoid assignment below, we've handled everything */

+ return;

case FREQ_CNTR_EVAL:

case VGA_SCRATCH1 ... VGA_SCRATCH8:

case RNG_DATA:

- case SILICON_REV:

case FREE_CNTR4:

case FREE_CNTR4_EXT:

qemu_log_mask(LOG_GUEST_ERROR,

2.17.1

In gic_deactivate_irq() the interrupt number comes from the guest

(on a write to the GICC_DIR register), so we need to sanity check

that it isn't out of range before we use it as an array index.

Handle this in a similar manner to the check we do in

gic_complete_irq() for the GICC_EOI register.

The array overrun is not disastrous because the calling code

uses (value & 0x3ff) to extract the interrupt field, so the

only out-of-range values possible are 1020..1023, which allow

overrunning only from irq_state[] into the following

irq_target[] array which the guest can already manipulate.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20180712154152.32183-2-peter.maydell@linaro.org

hw/intc/arm_gic.c | 16 +++++++++++++++-

1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c

--- a/hw/intc/arm_gic.c

+++ b/hw/intc/arm_gic.c

@@ -XXX,XX +XXX,XX @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)

static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)

int cm = 1 << cpu;

- int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);

+ int group;

+

+ if (irq >= s->num_irq) {

+ /*

+ * This handles two cases:

+ * 1. If software writes the ID of a spurious interrupt [ie 1023]

+ * to the GICC_DIR, the GIC ignores that write.

+ * 2. If software writes the number of a non-existent interrupt

+ * this must be a subcase of "value written is not an active interrupt"

+ * and so this is UNPREDICTABLE. We choose to ignore it.

+ */

+ return;

+ }

+

+ group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);

if (!gic_eoi_split(s, cpu, attrs)) {

/* This is UNPREDICTABLE; we choose to ignore it */

2.17.1

The GICD_ITARGETSR implementation still has some 11MPCore behaviour

that we were incorrectly using in our GICv1 and GICv2 implementations

for the case where the interrupt number is less than GIC_INTERNAL.

The desired behaviour here is:

* for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the

CPU doing the read for irqs 29..31

* for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a

number matching the CPU doing the read for all irqs < 32

Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this

is an 11MPCore GIC.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20180712154152.32183-3-peter.maydell@linaro.org

hw/intc/arm_gic.c | 6 ++++--

1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c

--- a/hw/intc/arm_gic.c

+++ b/hw/intc/arm_gic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

if (irq >= s->num_irq) {

goto bad_reg;

}

- if (irq >= 29 && irq <= 31) {

+ if (irq < 29 && s->revision == REV_11MPCORE) {

+ res = 0;

+ } else if (irq < GIC_INTERNAL) {

res = cm;

} else {

res = GIC_TARGET(irq);

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

if (irq >= s->num_irq) {

goto bad_reg;

}

- if (irq < 29) {

+ if (irq < 29 && s->revision == REV_11MPCORE) {

value = 0;

} else if (irq < GIC_INTERNAL) {

value = ALL_CPU_MASK;

2.17.1

From: Thomas Huth <thuth@redhat.com>

These devices are currently causing some problems when a user is trying

to hot-plug or introspect them during runtime. Since these devices can

not be instantiated by the user at all (they need to be wired up in code

instead), we should mark them with user_creatable = false anyway, then we

avoid at least the crashes with the hot-plugging. The introspection problem

will be handled by a separate patch.

Signed-off-by: Thomas Huth <thuth@redhat.com>

Message-id: 1531415537-26037-1-git-send-email-thuth@redhat.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Markus Armbruster <armbru@redhat.com>

hw/arm/bcm2836.c | 2 ++

1 file changed, 2 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void bcm283x_class_init(ObjectClass *oc, void *data)

bc->info = data;

dc->realize = bcm2836_realize;

dc->props = bcm2836_props;

+ /* Reason: Must be wired up in code (see raspi_init() function) */

+ dc->user_creatable = false;

static const TypeInfo bcm283x_type_info = {

2.17.1

RX and TX interrupt bits were reversed, resulting in an endless sequence

of serial interupts in the emulated system and the following repeated

error message when booting Linux.

serial8250: too much work for irq61

This results in a boot failure most of the time.

Qemu command line used to reproduce the problem:

    qemu-system-aarch64 -M raspi3 -m 1024 \

    -kernel arch/arm64/boot/Image \

    --append "rdinit=/sbin/init console=ttyS1,115200"

    -initrd rootfs.cpio \

    -dtb arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dtb \

    -nographic -monitor null -serial null -serial stdio

This is with arm64:defconfig. The root file system was generated using

buildroot.

NB that this error likely arises from an erratum in the

BCM2835 datasheet where the TX and RX bits were swapped

in the AU_MU_IER_REG description (but correct for IIR):

https://elinux.org/BCM2835_datasheet_errata#p12

Message-id: 1529355846-25102-1-git-send-email-linux@roeck-us.net

hw/char/bcm2835_aux.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c

--- a/hw/char/bcm2835_aux.c

+++ b/hw/char/bcm2835_aux.c

@@ -XXX,XX +XXX,XX @@

#define AUX_MU_BAUD_REG 0x68

/* bits in IER/IIR registers */

-#define TX_INT 0x1

-#define RX_INT 0x2

+#define RX_INT 0x1

+#define TX_INT 0x2

static void bcm2835_aux_update(BCM2835AuxState *s)

2.17.1

In get_page_addr_code(), we were incorrectly looking in the victim

TLB for an entry which matched the target address for reads, not

for code accesses. This meant that we could hit on a victim TLB

entry that indicated that the address was readable but not

executable, and incorrectly bypass the call to tlb_fill() which

should generate the guest MMU exception. Fix this bug.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180713141636.18665-2-peter.maydell@linaro.org

accel/tcg/cputlb.c | 2 +-

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)

index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

mmu_idx = cpu_mmu_index(env, true);

if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))) {

- if (!VICTIM_TLB_HIT(addr_read, addr)) {

+ if (!VICTIM_TLB_HIT(addr_code, addr)) {

tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);

}

}

2.17.1

In commit 4b1a3e1e34ad97 we added a check for whether the TLB entry

we had following a tlb_fill had the INVALID bit set. This could

happen in some circumstances because a stale or wrong TLB entry was

pulled out of the victim cache. However, after commit

68fea038553039e (which prevents stale entries being in the victim

cache) and the previous commit (which ensures we don't incorrectly

hit in the victim cache)) this should never be possible.

Drop the check on TLB_INVALID_MASK from the "is this a TLB_RECHECK?"

condition, and instead assert that the tlb fill procedure has given

us a valid TLB entry (or longjumped out with a guest exception).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180713141636.18665-3-peter.maydell@linaro.org

accel/tcg/cputlb.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

--- a/accel/tcg/cputlb.c

+++ b/accel/tcg/cputlb.c

@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)

if (!VICTIM_TLB_HIT(addr_code, addr)) {

tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);

}

+ assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));

2.17.1