target-arm queue. This has the "plumb txattrs through various

bits of exec.c" patches, and a collection of bug fixes from

various people.

The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:

Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531

for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)

* target/arm: Honour FPCR.FZ in FRECPX

* MAINTAINERS: Add entries for newer MPS2 boards and devices

* hw/intc/arm_gicv3: Fix APxR<n> register dispatching

* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel

GIC state

* tcg: Fix helper function vs host abi for float16

* arm: fix qemu crash on startup with -bios option

* arm: fix malloc type mismatch

* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

* Correct CPACR reset value for v7 cores

* memory.h: Improve IOMMU related documentation

* exec: Plumb transaction attributes through various functions in

preparation for allowing IOMMUs to see them

* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

* ARM: ACPI: Fix use-after-free due to memory realloc

* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

Francisco Iglesias (1):

xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

Igor Mammedov (1):

arm: fix qemu crash on startup with -bios option

Jan Kiszka (1):

hw/intc/arm_gicv3: Fix APxR<n> register dispatching

Paolo Bonzini (1):

arm: fix malloc type mismatch

Peter Maydell (17):

target/arm: Honour FPCR.FZ in FRECPX

MAINTAINERS: Add entries for newer MPS2 boards and devices

Correct CPACR reset value for v7 cores

memory.h: Improve IOMMU related documentation

Make tb_invalidate_phys_addr() take a MemTxAttrs argument

Make address_space_translate{, _cached}() take a MemTxAttrs argument

Make address_space_map() take a MemTxAttrs argument

Make address_space_access_valid() take a MemTxAttrs argument

Make flatview_extend_translation() take a MemTxAttrs argument

Make memory_region_access_valid() take a MemTxAttrs argument

Make MemoryRegion valid.accepts callback take a MemTxAttrs argument

Make flatview_access_valid() take a MemTxAttrs argument

Make flatview_translate() take a MemTxAttrs argument

Make address_space_get_iotlb_entry() take a MemTxAttrs argument

Make flatview_do_translate() take a MemTxAttrs argument

Make address_space_translate_iommu take a MemTxAttrs argument

vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

From: Jan Kiszka <jan.kiszka@siemens.com>

There was a nasty flip in identifying which register group an access is

targeting. The issue caused spuriously raised priorities of the guest

when handing CPUs over in the Jailhouse hypervisor.

Cc: qemu-stable@nongnu.org

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com

hw/intc/arm_gicv3_cpuif.c | 12 ++++++------

1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c

--- a/hw/intc/arm_gicv3_cpuif.c

+++ b/hw/intc/arm_gicv3_cpuif.c

@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)

GICv3CPUState *cs = icc_cs_from_env(env);

int regno = ri->opc2 & 3;

- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;

+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;

uint64_t value = cs->ich_apr[grp][regno];

trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);

@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,

{

GICv3CPUState *cs = icc_cs_from_env(env);

int regno = ri->opc2 & 3;

- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;

+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;

trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);

@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)

uint64_t value;

int regno = ri->opc2 & 3;

- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;

+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;

if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {

return icv_ap_read(env, ri);

@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,

GICv3CPUState *cs = icc_cs_from_env(env);

int regno = ri->opc2 & 3;

- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;

+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;

if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {

icv_ap_write(env, ri, value);

@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)

{

GICv3CPUState *cs = icc_cs_from_env(env);

int regno = ri->opc2 & 3;

- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;

+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;

uint64_t value;

value = cs->ich_apr[grp][regno];

@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,

{

GICv3CPUState *cs = icc_cs_from_env(env);

int regno = ri->opc2 & 3;

- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;

+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;

trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);

2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

It forgot to increase clroffset during the loop. So it only clear the

first 4 bytes.

Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920

Cc: qemu-stable@nongnu.org

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com

hw/intc/arm_gicv3_kvm.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c

--- a/hw/intc/arm_gicv3_kvm.c

+++ b/hw/intc/arm_gicv3_kvm.c

@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,

if (clroffset != 0) {

reg = 0;

kvm_gicd_access(s, clroffset, &reg, true);

+ clroffset += 4;

reg = *gic_bmp_ptr32(bmp, irq);

kvm_gicd_access(s, offset, &reg, true);

2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Depending on the host abi, float16, aka uint16_t, values are

passed and returned either zero-extended in the host register

or with garbage at the top of the host register.

The tcg code generator has so far been assuming garbage, as that

matches the x86 abi, but this is incorrect for other host abis.

Further, target/arm has so far been assuming zero-extended results,

so that it may store the 16-bit value into a 32-bit slot with the

high 16-bits already clear.

Rectify both problems by mapping "f16" in the helper definition

to uint32_t instead of (a typedef for) uint16_t. This forces

the host compiler to assume garbage in the upper 16 bits on input

and to zero-extend the result on output.

Cc: qemu-stable@nongnu.org

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20180522175629.24932-1-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/exec/helper-head.h | 2 +-

target/arm/helper-a64.c | 35 +++++++++--------

target/arm/helper.c | 80 +++++++++++++++++++-------------------

3 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h

index XXXXXXX..XXXXXXX 100644

--- a/include/exec/helper-head.h

+++ b/include/exec/helper-head.h

@@ -XXX,XX +XXX,XX @@

#define dh_ctype_int int

#define dh_ctype_i64 uint64_t

#define dh_ctype_s64 int64_t

-#define dh_ctype_f16 float16

+#define dh_ctype_f16 uint32_t

#define dh_ctype_f32 float32

#define dh_ctype_f64 float64

#define dh_ctype_ptr void *

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper-a64.c

+++ b/target/arm/helper-a64.c

@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)

return flags;

}

-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)

+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)

{

return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));

}

-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)

+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)

{

return float_rel_to_flags(float16_compare(x, y, fp_status));

}

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)

#define float64_three make_float64(0x4008000000000000ULL)

#define float64_one_point_five make_float64(0x3FF8000000000000ULL)

-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)

return float64_muladd(a, b, float64_two, 0, fpst);

}

-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)

}

/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */

-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)

+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)

{

float_status *fpst = fpstp;

uint16_t val16, sbit;

@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,

#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))

#define ADVSIMD_HALFOP(name) \

-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \

+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \

{ \

float_status *fpst = fpstp; \

return float16_ ## name(a, b, fpst); \

@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)

ADVSIMD_TWOHALFOP(mulx)

/* fused multiply-accumulate */

-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)

+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,

+ void *fpstp)

{

float_status *fpst = fpstp;

return float16_muladd(a, b, c, 0, fpst);

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,

#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0

-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

int compare = float16_compare_quiet(a, b, fpst);

return ADVSIMD_CMPRES(compare == float_relation_equal);

}

-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

int compare = float16_compare(a, b, fpst);

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)

compare == float_relation_equal);

}

-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

int compare = float16_compare(a, b, fpst);

return ADVSIMD_CMPRES(compare == float_relation_greater);

}

-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

float16 f0 = float16_abs(a);

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)

compare == float_relation_equal);

}

-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)

+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)

{

float_status *fpst = fpstp;

float16 f0 = float16_abs(a);

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)

}

/* round to integral */

-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)

+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)

{

return float16_round_to_int(x, fp_status);

}

-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)

+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)

{

int old_flags = get_float_exception_flags(fp_status), new_flags;

float16 ret;

@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)

* setting the mode appropriately before calling the helper.

*/

-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)

+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)

{

float_status *fpst = fpstp;

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)

return float16_to_int16(a, fpst);

}

-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)

+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)

{

float_status *fpst = fpstp;

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)

* Square Root and Reciprocal square root

*/

-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)

+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)

{

float_status *s = fpstp;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)

/* Integer to float and float to integer conversions */

-#define CONV_ITOF(name, fsz, sign) \

- float##fsz HELPER(name)(uint32_t x, void *fpstp) \

-{ \

- float_status *fpst = fpstp; \

- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \

+#define CONV_ITOF(name, ftype, fsz, sign) \

+ftype HELPER(name)(uint32_t x, void *fpstp) \

+{ \

+ float_status *fpst = fpstp; \

+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \

}

-#define CONV_FTOI(name, fsz, sign, round) \

-uint32_t HELPER(name)(float##fsz x, void *fpstp) \

-{ \

- float_status *fpst = fpstp; \

- if (float##fsz##_is_any_nan(x)) { \

- float_raise(float_flag_invalid, fpst); \

- return 0; \

- } \

- return float##fsz##_to_##sign##int32##round(x, fpst); \

+#define CONV_FTOI(name, ftype, fsz, sign, round) \

+uint32_t HELPER(name)(ftype x, void *fpstp) \

+{ \

+ float_status *fpst = fpstp; \

+ if (float##fsz##_is_any_nan(x)) { \

+ float_raise(float_flag_invalid, fpst); \

+ return 0; \

+ } \

+ return float##fsz##_to_##sign##int32##round(x, fpst); \

}

-#define FLOAT_CONVS(name, p, fsz, sign) \

-CONV_ITOF(vfp_##name##to##p, fsz, sign) \

-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \

-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)

+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \

+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \

+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \

+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)

-FLOAT_CONVS(si, h, 16, )

-FLOAT_CONVS(si, s, 32, )

-FLOAT_CONVS(si, d, 64, )

-FLOAT_CONVS(ui, h, 16, u)

-FLOAT_CONVS(ui, s, 32, u)

-FLOAT_CONVS(ui, d, 64, u)

+FLOAT_CONVS(si, h, uint32_t, 16, )

+FLOAT_CONVS(si, s, float32, 32, )

+FLOAT_CONVS(si, d, float64, 64, )

+FLOAT_CONVS(ui, h, uint32_t, 16, u)

+FLOAT_CONVS(ui, s, float32, 32, u)

+FLOAT_CONVS(ui, d, float64, 64, u)

#undef CONV_ITOF

#undef CONV_FTOI

@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)

return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);

}

-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)

{

return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);

}

-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)

{

return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);

}

-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)

{

return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);

}

-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)

{

return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);

}

@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)

}

}

-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)

{

return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);

}

-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)

{

return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);

}

-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)

{

return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);

}

-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)

+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)

{

return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);

}

-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)

+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)

{

return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);

}

-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)

+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)

{

return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);

}

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)

}

/* Half precision conversions. */

-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)

+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)

{

/* Squash FZ16 to 0 for the duration of conversion. In this case,

* it would affect flushing input denormals.

@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)

return r;

}

-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)

+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)

{

/* Squash FZ16 to 0 for the duration of conversion. In this case,

* it would affect flushing output denormals.

@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)

return r;

}

-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)

+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)

{

/* Squash FZ16 to 0 for the duration of conversion. In this case,

* it would affect flushing input denormals.

@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)

return r;

}

-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)

+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)

{

/* Squash FZ16 to 0 for the duration of conversion. In this case,

* it would affect flushing output denormals.

@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)

g_assert_not_reached();

}

-float16 HELPER(recpe_f16)(float16 input, void *fpstp)

+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)

{

float_status *fpst = fpstp;

float16 f16 = float16_squash_input_denormal(input, fpst);

@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)

return extract64(estimate, 0, 8) << 44;

}

-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)

+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)

{

float_status *s = fpstp;

float16 f16 = float16_squash_input_denormal(input, s);

--

2.17.1

From: Igor Mammedov <imammedo@redhat.com>

When QEMU is started with following CLI

-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd

it crashes with abort at

accel/kvm/kvm-all.c:2164:

KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument

hw/arm/boot.c | 18 +++++++++---------

1 file changed, 9 insertions(+), 9 deletions(-)

@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)

static const ARMInsnFixup *primary_loader;

AddressSpace *as = arm_boot_address_space(cpu, info);

+ /* CPU objects (unlike devices) are not automatically reset on system

+ * reset, so we must always register a handler to do so. If we're

+ * actually loading a kernel, the handler is also responsible for

+ * arranging that we start it correctly.

+ */

+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {

+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));

+ }

+

/* The board code is not supposed to set secure_board_setup unless

* running its code in secure mode is actually possible, and KVM

* doesn't support secure.

@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)

ARM_CPU(cs)->env.boot_info = info;

}

- /* CPU objects (unlike devices) are not automatically reset on system

- * reset, so we must always register a handler to do so. If we're

- * actually loading a kernel, the handler is also responsible for

- * arranging that we start it correctly.

- */

- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {

- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));

- }

-

if (!info->skip_dtb_autoload && have_dtb(info)) {

if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {

exit(1);

2.17.1

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Coverity found that the string return by 'object_get_canonical_path' was not

being freed at two locations in the model (CID 1391294 and CID 1391293) and

also that a memset was being called with a value greater than the max of a byte

on the second argument (CID 1391286). This patch corrects this by adding the

freeing of the strings and also changing to memset to zero instead on

descriptor unaligned errors.

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com

hw/dma/xlnx-zdma.c | 10 +++++++---

1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c

--- a/hw/dma/xlnx-zdma.c

+++ b/hw/dma/xlnx-zdma.c

@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)

qemu_log_mask(LOG_GUEST_ERROR,

"zdma: unaligned descriptor at %" PRIx64,

addr);

- memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));

+ memset(buf, 0x0, sizeof(XlnxZDMADescr));

s->error = true;

return false;

}

@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)

RegisterInfo *r = &s->regs_info[addr / 4];

if (!r->data) {

+ gchar *path = object_get_canonical_path(OBJECT(s));

qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",

- object_get_canonical_path(OBJECT(s)),

+ path,

addr);

+ g_free(path);

ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);

zdma_ch_imr_update_irq(s);

return 0;

@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,

RegisterInfo *r = &s->regs_info[addr / 4];

if (!r->data) {

+ gchar *path = object_get_canonical_path(OBJECT(s));

qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",

- object_get_canonical_path(OBJECT(s)),

+ path,

addr, value);

+ g_free(path);

ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);

zdma_ch_imr_update_irq(s);

return;

2.17.1

Add more detail to the documentation for memory_region_init_iommu()

and other IOMMU-related functions and data structures.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Message-id: 20180521140402.23318-2-peter.maydell@linaro.org

include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----

1 file changed, 95 insertions(+), 10 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h

--- a/include/exec/memory.h

+++ b/include/exec/memory.h

@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {

IOMMU_ATTR_SPAPR_TCE_FD

+/**

+ * IOMMUMemoryRegionClass:

+ *

+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION

+ * and provide an implementation of at least the @translate method here

+ * to handle requests to the memory region. Other methods are optional.

+ *

+ * The IOMMU implementation must use the IOMMU notifier infrastructure

+ * to report whenever mappings are changed, by calling

+ * memory_region_notify_iommu() (or, if necessary, by calling

+ * memory_region_notify_one() for each registered notifier).

+ */

typedef struct IOMMUMemoryRegionClass {

/* private */

struct DeviceClass parent_class;

/*

- * Return a TLB entry that contains a given address. Flag should

- * be the access permission of this translation operation. We can

- * set flag to IOMMU_NONE to mean that we don't need any

- * read/write permission checks, like, when for region replay.

+ * Return a TLB entry that contains a given address.

+ *

+ * The IOMMUAccessFlags indicated via @flag are optional and may

+ * be specified as IOMMU_NONE to indicate that the caller needs

+ * the full translation information for both reads and writes. If

+ * the access flags are specified then the IOMMU implementation

+ * may use this as an optimization, to stop doing a page table

+ * walk as soon as it knows that the requested permissions are not

+ * allowed. If IOMMU_NONE is passed then the IOMMU must do the

+ * full page table walk and report the permissions in the returned

+ * IOMMUTLBEntry. (Note that this implies that an IOMMU may not

+ * return different mappings for reads and writes.)

+ *

+ * The returned information remains valid while the caller is

+ * holding the big QEMU lock or is inside an RCU critical section;

+ * if the caller wishes to cache the mapping beyond that it must

+ * register an IOMMU notifier so it can invalidate its cached

+ * information when the IOMMU mapping changes.

+ *

+ * @iommu: the IOMMUMemoryRegion

+ * @hwaddr: address to be translated within the memory region

+ * @flag: requested access permissions

*/

IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,

IOMMUAccessFlags flag);

- /* Returns minimum supported page size */

+ /* Returns minimum supported page size in bytes.

+ * If this method is not provided then the minimum is assumed to

+ * be TARGET_PAGE_SIZE.

+ *

+ * @iommu: the IOMMUMemoryRegion

+ */

uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);

- /* Called when IOMMU Notifier flag changed */

+ /* Called when IOMMU Notifier flag changes (ie when the set of

+ * events which IOMMU users are requesting notification for changes).

+ * Optional method -- need not be provided if the IOMMU does not

+ * need to know exactly which events must be notified.

+ *

+ * @iommu: the IOMMUMemoryRegion

+ * @old_flags: events which previously needed to be notified

+ * @new_flags: events which now need to be notified

+ */

void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,

IOMMUNotifierFlag old_flags,

IOMMUNotifierFlag new_flags);

- /* Set this up to provide customized IOMMU replay function */

+ /* Called to handle memory_region_iommu_replay().

+ *

+ * The default implementation of memory_region_iommu_replay() is to

+ * call the IOMMU translate method for every page in the address space

+ * with flag == IOMMU_NONE and then call the notifier if translate

+ * returns a valid mapping. If this method is implemented then it

+ * overrides the default behaviour, and must provide the full semantics

+ * of memory_region_iommu_replay(), by calling @notifier for every

+ * translation present in the IOMMU.

+ *

+ * Optional method -- an IOMMU only needs to provide this method

+ * if the default is inefficient or produces undesirable side effects.

+ *

+ * Note: this is not related to record-and-replay functionality.

+ */

void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);

- /* Get IOMMU misc attributes */

- int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,

+ /* Get IOMMU misc attributes. This is an optional method that

+ * can be used to allow users of the IOMMU to get implementation-specific

+ * information. The IOMMU implements this method to handle calls

+ * by IOMMU users to memory_region_iommu_get_attr() by filling in

+ * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that

+ * the IOMMU supports. If the method is unimplemented then

+ * memory_region_iommu_get_attr() will always return -EINVAL.

+ *

+ * @iommu: the IOMMUMemoryRegion

+ * @attr: attribute being queried

+ * @data: memory to fill in with the attribute data

+ *

+ * Returns 0 on success, or a negative errno; in particular

+ * returns -EINVAL for unrecognized or unimplemented attribute types.

+ */

+ int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,

void *data);

} IOMMUMemoryRegionClass;

@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,

* An IOMMU region translates addresses and forwards accesses to a target

* memory region.

*

+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.

+ * @_iommu_mr should be a pointer to enough memory for an instance of

+ * that subclass, @instance_size is the size of that subclass, and

+ * @mrtypename is its name. This function will initialize @_iommu_mr as an

+ * instance of the subclass, and its methods will then be called to handle

+ * accesses to the memory region. See the documentation of

+ * #IOMMUMemoryRegionClass for further details.

+ *

* @_iommu_mr: the #IOMMUMemoryRegion to be initialized

* @instance_size: the IOMMUMemoryRegion subclass instance size

* @mrtypename: the type name of the #IOMMUMemoryRegion

@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,

* a notifier with the minimum page granularity returned by

* mr->iommu_ops->get_page_size().

*

+ * Note: this is not related to record-and-replay functionality.

+ *

* @iommu_mr: the memory region to observe

* @n: the notifier to which to replay iommu mappings

*/

@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);

* memory_region_iommu_replay_all: replay existing IOMMU translations

* to all the notifiers registered.

*

+ * Note: this is not related to record-and-replay functionality.