[Qemu-devel] [PULL 00/13] target-arm queue
[Qemu-devel] [PULL 00/16] target-arm queue
1
Arm patch queue -- these are all bug fix patches but we might
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
2
as well put them in to rc0...
3
2
4
thanks
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
5
-- PMM
6
7
The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
8
9
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
10
4
11
are available in the Git repository at:
5
are available in the Git repository at:
12
6
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
14
8
15
for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
16
10
17
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* fsl-imx6: Fix incorrect Ethernet interrupt defines
15
* Fix coverity nit in int_to_float code
22
* dump: Update correct kdump phys_base field for AArch64
16
* Don't set Invalid for float-to-int(MAXINT)
23
* char: i.MX: Add support for "TX complete" interrupt
17
* Fix fp_status_f16 tininess before rounding
24
* bcm2836/raspi: Fix various bugs resulting in panics trying
18
* Add various missing insns from the v8.2-FP16 extension
25
to boot a Debian Linux kernel on raspi3
19
* Fix sqrt_f16 exception raising
20
* sdcard: Correct CRC16 offset in sd_function_switch()
21
* tcg: Optionally log FPU state in TCG -d cpu logging
26
22
27
----------------------------------------------------------------
23
----------------------------------------------------------------
28
Andrey Smirnov (2):
24
Alex Bennée (5):
29
char: i.MX: Simplify imx_update()
25
fpu/softfloat: int_to_float ensure r fully initialised
30
char: i.MX: Add support for "TX complete" interrupt
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
31
30
32
Guenter Roeck (1):
31
Peter Maydell (3):
33
fsl-imx6: Swap Ethernet interrupt defines
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
33
target/arm: Fix fp_status_f16 tininess before rounding
34
tcg: Optionally log FPU state in TCG -d cpu logging
34
35
35
Peter Maydell (9):
36
Philippe Mathieu-Daudé (1):
36
hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
37
sdcard: Correct CRC16 offset in sd_function_switch()
37
hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
38
hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
39
hw/arm/bcm2386: Fix parent type of bcm2386
40
hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
41
hw/arm/bcm2836: Create proper bcm2837 device
42
hw/arm/bcm2836: Use correct affinity values for BCM2837
43
hw/arm/bcm2836: Hardcode correct CPU type
44
hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
45
38
46
Wei Huang (1):
39
Richard Henderson (7):
47
dump: Update correct kdump phys_base field for AArch64
40
target/arm: Implement FMOV (general) for fp16
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
48
47
49
include/hw/arm/bcm2836.h | 31 +++++++++++++---
48
include/qemu/log.h | 1 +
50
include/hw/arm/fsl-imx6.h | 4 +-
49
target/arm/helper-a64.h | 2 +
51
include/hw/char/imx_serial.h | 3 ++
50
target/arm/helper.h | 6 +
52
dump.c | 14 +++++--
51
accel/tcg/cpu-exec.c | 9 +-
53
hw/arm/bcm2836.c | 87 +++++++++++++++++++++++++++++++-------------
52
fpu/softfloat.c | 6 +-
54
hw/arm/boot.c | 12 ++++++
53
hw/sd/sd.c | 2 +-
55
hw/arm/raspi.c | 77 +++++++++++++++++++++++++++++++--------
54
target/arm/cpu.c | 2 +
56
hw/char/imx_serial.c | 44 ++++++++++++++++------
55
target/arm/helper-a64.c | 10 ++
57
hw/net/imx_fec.c | 28 +++++++++++++-
56
target/arm/helper.c | 38 +++-
58
9 files changed, 237 insertions(+), 63 deletions(-)
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
58
util/log.c | 2 +
59
11 files changed, 428 insertions(+), 71 deletions(-)
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
1
The TypeInfo and state struct for bcm2386 disagree about what the
1
From: Alex Bennée <alex.bennee@linaro.org>
2
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
3
but the BCM2386State struct only defines the parent_obj field
4
as DeviceState. This would have caused problems if anything
5
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
6
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
7
need any of the additional functionality TYPE_SYS_BUS_DEVICE
8
provides.
9
2
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
4
later on so we might as well mirror that.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
14
---
10
---
15
hw/arm/bcm2836.c | 2 +-
11
fpu/softfloat.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
17
13
18
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/bcm2836.c
16
--- a/fpu/softfloat.c
21
+++ b/hw/arm/bcm2836.c
17
+++ b/fpu/softfloat.c
22
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
23
19
24
static const TypeInfo bcm2836_type_info = {
20
static FloatParts int_to_float(int64_t a, float_status *status)
25
.name = TYPE_BCM2836,
21
{
26
- .parent = TYPE_SYS_BUS_DEVICE,
22
- FloatParts r;
27
+ .parent = TYPE_DEVICE,
23
+ FloatParts r = {};
28
.instance_size = sizeof(BCM2836State),
24
if (a == 0) {
29
.instance_init = bcm2836_init,
25
r.cls = float_class_zero;
30
.class_init = bcm2836_class_init,
26
r.sign = false;
31
--
27
--
32
2.16.2
28
2.17.0
33
29
34
30
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
1
In float-to-integer conversion, if the floating point input
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
1
8
9
Fix the boundary case to take the right half of the if()
10
statements.
11
12
This fixes a regression from 2.11 introduced by the softfloat
13
refactoring.
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
20
---
21
fpu/softfloat.c | 4 ++--
22
1 file changed, 2 insertions(+), 2 deletions(-)
23
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
27
+++ b/fpu/softfloat.c
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
29
r = UINT64_MAX;
30
}
31
if (p.sign) {
32
- if (r < -(uint64_t) min) {
33
+ if (r <= -(uint64_t) min) {
34
return -r;
35
} else {
36
s->float_exception_flags = orig_flags | float_flag_invalid;
37
return min;
38
}
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
45
--
46
2.17.0
47
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
1
Now we have separate types for BCM2386 and BCM2387, we might as well
1
In commit d81ce0ef2c4f105 we added an extra float_status field
2
just hard-code the CPU type they use rather than having it passed
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
through as an object property. This then lets us put the initialization
3
by setting it to float_tininess_before_rounding. This currently
4
of the CPU object in init rather than realize.
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
5
8
6
Note that this change means that it's no longer possible on
9
Add the missing initialization.
7
the command line to use -cpu to ask for a different kind of
8
CPU than the SoC supports. This was never a supported thing to
9
do anyway; we were just not sanity-checking the command line.
10
10
11
This does require us to only build the bcm2837 object on
11
Fixes: d81ce0ef2c4f105
12
TARGET_AARCH64 configs, since otherwise it won't instantiate
12
Cc: qemu-stable@nongnu.org
13
due to the missing cortex-a53 device and "make check" will fail.
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
18
target/arm/cpu.c | 2 ++
19
1 file changed, 2 insertions(+)
14
20
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
19
---
20
hw/arm/bcm2836.c | 24 +++++++++++++++---------
21
hw/arm/raspi.c | 2 --
22
2 files changed, 15 insertions(+), 11 deletions(-)
23
24
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/bcm2836.c
23
--- a/target/arm/cpu.c
27
+++ b/hw/arm/bcm2836.c
24
+++ b/target/arm/cpu.c
28
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
29
26
&env->vfp.fp_status);
30
struct BCM283XInfo {
27
set_float_detect_tininess(float_tininess_before_rounding,
31
const char *name;
28
&env->vfp.standard_fp_status);
32
+ const char *cpu_type;
29
+ set_float_detect_tininess(float_tininess_before_rounding,
33
int clusterid;
30
+ &env->vfp.fp_status_f16);
34
};
31
#ifndef CONFIG_USER_ONLY
35
32
if (kvm_enabled()) {
36
static const BCM283XInfo bcm283x_socs[] = {
33
kvm_arm_reset_vcpu(cpu);
37
{
38
.name = TYPE_BCM2836,
39
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
40
.clusterid = 0xf,
41
},
42
+#ifdef TARGET_AARCH64
43
{
44
.name = TYPE_BCM2837,
45
+ .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
46
.clusterid = 0x0,
47
},
48
+#endif
49
};
50
51
static void bcm2836_init(Object *obj)
52
{
53
BCM283XState *s = BCM283X(obj);
54
+ BCM283XClass *bc = BCM283X_GET_CLASS(obj);
55
+ const BCM283XInfo *info = bc->info;
56
+ int n;
57
+
58
+ for (n = 0; n < BCM283X_NCPUS; n++) {
59
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
60
+ info->cpu_type);
61
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
62
+ &error_abort);
63
+ }
64
65
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
66
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
67
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
68
69
/* common peripherals from bcm2835 */
70
71
- obj = OBJECT(dev);
72
- for (n = 0; n < BCM283X_NCPUS; n++) {
73
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
74
- s->cpu_type);
75
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
76
- &error_abort);
77
- }
78
-
79
obj = object_property_get_link(OBJECT(dev), "ram", &err);
80
if (obj == NULL) {
81
error_setg(errp, "%s: required ram link not found: %s",
82
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
83
}
84
85
static Property bcm2836_props[] = {
86
- DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
87
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
88
BCM283X_NCPUS),
89
DEFINE_PROP_END_OF_LIST()
90
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/arm/raspi.c
93
+++ b/hw/arm/raspi.c
94
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
95
/* Setup the SOC */
96
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
97
&error_abort);
98
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
99
- &error_abort);
100
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
101
&error_abort);
102
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
103
--
34
--
104
2.16.2
35
2.17.0
105
36
106
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for "TX complete"/TXDC interrupt generate by real HW since
3
Adding the fp16 moves to/from general registers.
4
it is needed to support guests other than Linux.
5
4
6
Based on the patch by Bill Paul as found here:
5
Cc: qemu-stable@nongnu.org
7
https://bugs.launchpad.net/qemu/+bug/1753314
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Cc: qemu-devel@nongnu.org
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
10
Cc: qemu-arm@nongnu.org
11
Cc: Bill Paul <wpaul@windriver.com>
12
Cc: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Bill Paul <wpaul@windriver.com>
14
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
15
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/char/imx_serial.h | 3 +++
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
20
hw/char/imx_serial.c | 20 +++++++++++++++++---
13
1 file changed, 21 insertions(+)
21
2 files changed, 20 insertions(+), 3 deletions(-)
22
14
23
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/char/imx_serial.h
17
--- a/target/arm/translate-a64.c
26
+++ b/include/hw/char/imx_serial.h
18
+++ b/target/arm/translate-a64.c
27
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
28
#define UCR2_RXEN (1<<1) /* Receiver enable */
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
29
#define UCR2_SRST (1<<0) /* Reset complete */
21
clear_vec_high(s, true, rd);
30
22
break;
31
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
23
+ case 3:
32
+
24
+ /* 16 bit */
33
#define UTS1_TXEMPTY (1<<6)
25
+ tmp = tcg_temp_new_i64();
34
#define UTS1_RXEMPTY (1<<5)
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
35
#define UTS1_TXFULL (1<<4)
27
+ write_fp_dreg(s, rd, tmp);
36
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
28
+ tcg_temp_free_i64(tmp);
37
uint32_t ubmr;
29
+ break;
38
uint32_t ubrc;
30
+ default:
39
uint32_t ucr3;
31
+ g_assert_not_reached();
40
+ uint32_t ucr4;
41
42
qemu_irq irq;
43
CharBackend chr;
44
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/char/imx_serial.c
47
+++ b/hw/char/imx_serial.c
48
@@ -XXX,XX +XXX,XX @@
49
50
static const VMStateDescription vmstate_imx_serial = {
51
.name = TYPE_IMX_SERIAL,
52
- .version_id = 1,
53
- .minimum_version_id = 1,
54
+ .version_id = 2,
55
+ .minimum_version_id = 2,
56
.fields = (VMStateField[]) {
57
VMSTATE_INT32(readbuff, IMXSerialState),
58
VMSTATE_UINT32(usr1, IMXSerialState),
59
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
60
VMSTATE_UINT32(ubmr, IMXSerialState),
61
VMSTATE_UINT32(ubrc, IMXSerialState),
62
VMSTATE_UINT32(ucr3, IMXSerialState),
63
+ VMSTATE_UINT32(ucr4, IMXSerialState),
64
VMSTATE_END_OF_LIST()
65
},
66
};
67
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
68
* unfortunately.
69
*/
70
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
71
+ /*
72
+ * TCEN and TXDC are both bit 3
73
+ */
74
+ mask |= s->ucr4 & UCR4_TCEN;
75
+
76
usr2 = s->usr2 & mask;
77
78
qemu_set_irq(s->irq, usr1 || usr2);
79
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
80
return s->ucr3;
81
82
case 0x23: /* UCR4 */
83
+ return s->ucr4;
84
+
85
case 0x29: /* BRM Incremental */
86
return 0x0; /* TODO */
87
88
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
89
* qemu_chr_fe_write and background I/O callbacks */
90
qemu_chr_fe_write_all(&s->chr, &ch, 1);
91
s->usr1 &= ~USR1_TRDY;
92
+ s->usr2 &= ~USR2_TXDC;
93
imx_update(s);
94
s->usr1 |= USR1_TRDY;
95
+ s->usr2 |= USR2_TXDC;
96
imx_update(s);
97
}
32
}
98
break;
33
} else {
99
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
100
s->ucr3 = value & 0xffff;
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
101
break;
36
/* 64 bits from top half */
102
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
103
- case 0x2d: /* UTS1 */
38
break;
104
case 0x23: /* UCR4 */
39
+ case 3:
105
+ s->ucr4 = value & 0xffff;
40
+ /* 16 bit */
106
+ imx_update(s);
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
107
+ break;
42
+ break;
108
+
43
+ default:
109
+ case 0x2d: /* UTS1 */
44
+ g_assert_not_reached();
110
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
45
}
111
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
46
}
112
/* TODO */
47
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
49
case 0xa: /* 64 bit */
50
case 0xd: /* 64 bit to top half of quad */
51
break;
52
+ case 0x6: /* 16-bit float, 32-bit int */
53
+ case 0xe: /* 16-bit float, 64-bit int */
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
55
+ break;
56
+ }
57
+ /* fallthru */
58
default:
59
/* all other sf/type/rmode combinations are invalid */
60
unallocated_encoding(s);
113
--
61
--
114
2.16.2
62
2.17.0
115
63
116
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The sabrelite machine model used by qemu-system-arm is based on the
3
No sense in emitting code after the exception.
4
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
5
controller which is supported in QEMU using the imx_fec.c module
6
(actually called imx.enet for this model.)
7
4
8
The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
imx.enet device like this:
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
11
#define FSL_IMX6_ENET_MAC_1588_IRQ 118
12
#define FSL_IMX6_ENET_MAC_IRQ 119
13
14
According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
15
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
16
interrupts are as follows.
17
18
150 ENET MAC 0 IRQ
19
151 ENET MAC 0 1588 Timer interrupt
20
21
where
22
23
150 - 32 == 118
24
151 - 32 == 119
25
26
In other words, the vector definitions in the fsl-imx6.h file are reversed.
27
28
Fixing the interrupts alone causes problems with older Linux kernels:
29
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
30
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
31
error handling. This is a Linux kernel problem, not a qemu problem:
32
the Linux kernel only worked by accident since it requested both interrupts.
33
34
For backward compatibility, generate the Ethernet interrupt on both interrupt
35
lines. This was shown to work from all Linux kernel releases starting with
36
v3.16.
37
38
Link: https://bugs.launchpad.net/qemu/+bug/1753309
39
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
40
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
41
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
10
---
44
include/hw/arm/fsl-imx6.h | 4 ++--
11
target/arm/translate-a64.c | 2 +-
45
hw/net/imx_fec.c | 28 +++++++++++++++++++++++++++-
12
1 file changed, 1 insertion(+), 1 deletion(-)
46
2 files changed, 29 insertions(+), 3 deletions(-)
47
13
48
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
49
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/arm/fsl-imx6.h
16
--- a/target/arm/translate-a64.c
51
+++ b/include/hw/arm/fsl-imx6.h
17
+++ b/target/arm/translate-a64.c
52
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
53
#define FSL_IMX6_HDMI_MASTER_IRQ 115
19
default:
54
#define FSL_IMX6_HDMI_CEC_IRQ 116
20
/* all other sf/type/rmode combinations are invalid */
55
#define FSL_IMX6_MLB150_LOW_IRQ 117
21
unallocated_encoding(s);
56
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
22
- break;
57
-#define FSL_IMX6_ENET_MAC_IRQ 119
23
+ return;
58
+#define FSL_IMX6_ENET_MAC_IRQ 118
24
}
59
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
25
60
#define FSL_IMX6_PCIE1_IRQ 120
26
if (!fp_access_check(s)) {
61
#define FSL_IMX6_PCIE2_IRQ 121
62
#define FSL_IMX6_PCIE3_IRQ 122
63
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/net/imx_fec.c
66
+++ b/hw/net/imx_fec.c
67
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
68
69
static void imx_eth_update(IMXFECState *s)
70
{
71
- if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
72
+ /*
73
+ * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
74
+ * interrupts swapped. This worked with older versions of Linux (4.14
75
+ * and older) since Linux associated both interrupt lines with Ethernet
76
+ * MAC interrupts. Specifically,
77
+ * - Linux 4.15 and later have separate interrupt handlers for the MAC and
78
+ * timer interrupts. Those versions of Linux fail with versions of QEMU
79
+ * with swapped interrupt assignments.
80
+ * - In linux 4.14, both interrupt lines were registered with the Ethernet
81
+ * MAC interrupt handler. As a result, all versions of qemu happen to
82
+ * work, though that is accidental.
83
+ * - In Linux 4.9 and older, the timer interrupt was registered directly
84
+ * with the Ethernet MAC interrupt handler. The MAC interrupt was
85
+ * redirected to a GPIO interrupt to work around erratum ERR006687.
86
+ * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
87
+ * interrupt never fired since IOMUX is currently not supported in qemu.
88
+ * Linux instead received MAC interrupts on the timer interrupt.
89
+ * As a result, qemu versions with the swapped interrupt assignment work,
90
+ * albeit accidentally, but qemu versions with the correct interrupt
91
+ * assignment fail.
92
+ *
93
+ * To ensure that all versions of Linux work, generate ENET_INT_MAC
94
+ * interrrupts on both interrupt lines. This should be changed if and when
95
+ * qemu supports IOMUX.
96
+ */
97
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
98
+ (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
99
qemu_set_irq(s->irq[1], 1);
100
} else {
101
qemu_set_irq(s->irq[1], 0);
102
--
27
--
103
2.16.2
28
2.17.0
104
29
105
30
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Cc: qemu-stable@nongnu.org
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.h | 6 +++
11
target/arm/helper.c | 38 ++++++++++++++-
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
44
#undef VFP_CONV_FIX_A64
45
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
47
- * Therefore we convert to f64 (which does not round), scale,
48
- * and then convert f64 to f16 (which may round).
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
50
+ * vice versa for conversion to integer.
51
+ *
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
53
+ * For 64-bit integers, any integer that would cause rounding will also
54
+ * overflow to f16 infinity, so there is no double rounding problem.
55
*/
56
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
61
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
65
+}
66
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
68
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
70
+}
71
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
266
2.17.0
267
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
1
The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
1
From: Richard Henderson <richard.henderson@linaro.org>
2
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
3
is required for Linux to boot.
4
2
3
Cc: qemu-stable@nongnu.org
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
9
---
9
---
10
hw/arm/bcm2836.c | 11 +++++++----
10
target/arm/translate-a64.c | 17 +++++++++++++++--
11
1 file changed, 7 insertions(+), 4 deletions(-)
11
1 file changed, 15 insertions(+), 2 deletions(-)
12
12
13
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/bcm2836.c
15
--- a/target/arm/translate-a64.c
16
+++ b/hw/arm/bcm2836.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
18
18
bool sf = extract32(insn, 31, 1);
19
struct BCM283XInfo {
19
bool itof;
20
const char *name;
20
21
+ int clusterid;
21
- if (sbit || (type > 1)
22
};
22
- || (!sf && scale < 32)) {
23
23
+ if (sbit || (!sf && scale < 32)) {
24
static const BCM283XInfo bcm283x_socs[] = {
24
+ unallocated_encoding(s);
25
{
25
+ return;
26
.name = TYPE_BCM2836,
26
+ }
27
+ .clusterid = 0xf,
27
+
28
},
28
+ switch (type) {
29
{
29
+ case 0: /* float32 */
30
.name = TYPE_BCM2837,
30
+ case 1: /* float64 */
31
+ .clusterid = 0x0,
31
+ break;
32
},
32
+ case 3: /* float16 */
33
};
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
34
34
+ break;
35
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
35
+ }
36
static void bcm2836_realize(DeviceState *dev, Error **errp)
36
+ /* fallthru */
37
{
37
+ default:
38
BCM283XState *s = BCM283X(dev);
38
unallocated_encoding(s);
39
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
39
return;
40
+ const BCM283XInfo *info = bc->info;
40
}
41
Object *obj;
42
Error *err = NULL;
43
int n;
44
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
45
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
46
47
for (n = 0; n < BCM283X_NCPUS; n++) {
48
- /* Mirror bcm2836, which has clusterid set to 0xf
49
- * TODO: this should be converted to a property of ARM_CPU
50
- */
51
- s->cpus[n].mp_affinity = 0xF00 | n;
52
+ /* TODO: this should be converted to a property of ARM_CPU */
53
+ s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
54
55
/* set periphbase/CBAR value for CPU-local registers */
56
object_property_set_int(OBJECT(&s->cpus[n]),
57
--
41
--
58
2.16.2
42
2.17.0
59
43
60
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
1
The raspi3 has AArch64 CPUs, which means that our smpboot
1
From: Richard Henderson <richard.henderson@linaro.org>
2
code for keeping the secondary CPUs in a pen needs to have
3
a version for A64 as well as A32. Without this, the
4
secondary CPUs go into an infinite loop of taking undefined
5
instruction exceptions.
6
2
3
Cc: qemu-stable@nongnu.org
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
10
---
9
---
11
hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
12
1 file changed, 40 insertions(+), 1 deletion(-)
11
1 file changed, 14 insertions(+), 16 deletions(-)
13
12
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
15
--- a/target/arm/translate-a64.c
17
+++ b/hw/arm/raspi.c
16
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
19
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
18
return v;
20
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
21
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
22
+#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
23
24
/* Table of Linux board IDs for different Pi versions */
25
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
26
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
27
info->smp_loader_start);
28
}
19
}
29
20
30
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
31
+{
22
+{
32
+ /* Unlike the AArch32 version we don't need to call the board setup hook.
23
+ TCGv_i32 v = tcg_temp_new_i32();
33
+ * The mechanism for doing the spin-table is also entirely different.
34
+ * We must have four 64-bit fields at absolute addresses
35
+ * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
36
+ * our CPUs, and which we must ensure are zero initialized before
37
+ * the primary CPU goes into the kernel. We put these variables inside
38
+ * a rom blob, so that the reset for ROM contents zeroes them for us.
39
+ */
40
+ static const uint32_t smpboot[] = {
41
+ 0xd2801b05, /* mov x5, 0xd8 */
42
+ 0xd53800a6, /* mrs x6, mpidr_el1 */
43
+ 0x924004c6, /* and x6, x6, #0x3 */
44
+ 0xd503205f, /* spin: wfe */
45
+ 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */
46
+ 0xb4ffffc4, /* cbz x4, spin */
47
+ 0xd2800000, /* mov x0, #0x0 */
48
+ 0xd2800001, /* mov x1, #0x0 */
49
+ 0xd2800002, /* mov x2, #0x0 */
50
+ 0xd2800003, /* mov x3, #0x0 */
51
+ 0xd61f0080, /* br x4 */
52
+ };
53
+
24
+
54
+ static const uint64_t spintables[] = {
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
55
+ 0, 0, 0, 0
26
+ return v;
56
+ };
57
+
58
+ rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
59
+ info->smp_loader_start);
60
+ rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
61
+ SPINTABLE_ADDR);
62
+}
27
+}
63
+
28
+
64
static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
30
* If SVE is not enabled, then there are only 128 bits in the vector.
31
*/
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
65
{
34
{
66
arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
35
TCGv_ptr fpst = NULL;
67
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
68
/* Pi2 and Pi3 requires SMP setup */
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
69
if (version >= 2) {
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
70
binfo.smp_loader_start = SMPBOOT_ADDR;
39
71
- binfo.write_secondary_boot = write_smpboot;
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
72
+ if (version == 2) {
41
-
73
+ binfo.write_secondary_boot = write_smpboot;
42
switch (opcode) {
74
+ } else {
43
case 0x0: /* FMOV */
75
+ binfo.write_secondary_boot = write_smpboot64;
44
tcg_gen_mov_i32(tcg_res, tcg_op);
76
+ }
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
77
binfo.secondary_cpu_reset_hook = reset_secondary;
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
48
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
78
}
79
79
80
if (is_scalar) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
80
--
90
--
81
2.16.2
91
2.17.0
82
92
83
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
1
The bcm2837 is pretty similar to the bcm2836, but it does have
1
From: Richard Henderson <richard.henderson@linaro.org>
2
some differences. Notably, the MPIDR affinity aff1 values it
3
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
4
uses, and if this is wrong Linux will not boot.
5
2
6
Rather than trying to have one device with properties that
3
We missed all of the scalar fp16 binary operations.
7
configure it differently for the two cases, create two
8
separate QOM devices for the two SoCs. We use the same approach
9
as hw/arm/aspeed_soc.c and share code and have a data table
10
that might differ per-SoC. For the moment the two types don't
11
actually have different behaviour.
12
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
16
---
11
---
17
include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
18
hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++-----
13
1 file changed, 65 insertions(+)
19
hw/arm/raspi.c | 3 ++-
20
3 files changed, 53 insertions(+), 6 deletions(-)
21
14
22
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/bcm2836.h
17
--- a/target/arm/translate-a64.c
25
+++ b/include/hw/arm/bcm2836.h
18
+++ b/target/arm/translate-a64.c
26
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
27
20
tcg_temp_free_i64(tcg_res);
28
#define BCM283X_NCPUS 4
21
}
29
22
30
+/* These type names are for specific SoCs; other than instantiating
23
+/* Floating-point data-processing (2 source) - half precision */
31
+ * them, code using these devices should always handle them via the
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
32
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
25
+ int rd, int rn, int rm)
33
+ */
26
+{
34
+#define TYPE_BCM2836 "bcm2836"
27
+ TCGv_i32 tcg_op1;
35
+#define TYPE_BCM2837 "bcm2837"
28
+ TCGv_i32 tcg_op2;
29
+ TCGv_i32 tcg_res;
30
+ TCGv_ptr fpst;
36
+
31
+
37
typedef struct BCM283XState {
32
+ tcg_res = tcg_temp_new_i32();
38
/*< private >*/
33
+ fpst = get_fpstatus_ptr(true);
39
DeviceState parent_obj;
34
+ tcg_op1 = read_fp_hreg(s, rn);
40
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
35
+ tcg_op2 = read_fp_hreg(s, rm);
41
BCM2835PeripheralState peripherals;
42
} BCM283XState;
43
44
+typedef struct BCM283XInfo BCM283XInfo;
45
+
36
+
46
+typedef struct BCM283XClass {
37
+ switch (opcode) {
47
+ DeviceClass parent_class;
38
+ case 0x0: /* FMUL */
48
+ const BCM283XInfo *info;
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+} BCM283XClass;
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
50
+
69
+
51
+#define BCM283X_CLASS(klass) \
70
+ write_fp_sreg(s, rd, tcg_res);
52
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
53
+#define BCM283X_GET_CLASS(obj) \
54
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
55
+
71
+
56
#endif /* BCM2836_H */
72
+ tcg_temp_free_ptr(fpst);
57
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
73
+ tcg_temp_free_i32(tcg_op1);
58
index XXXXXXX..XXXXXXX 100644
74
+ tcg_temp_free_i32(tcg_op2);
59
--- a/hw/arm/bcm2836.c
75
+ tcg_temp_free_i32(tcg_res);
60
+++ b/hw/arm/bcm2836.c
76
+}
61
@@ -XXX,XX +XXX,XX @@
62
/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
63
#define BCM2836_CONTROL_BASE 0x40000000
64
65
+struct BCM283XInfo {
66
+ const char *name;
67
+};
68
+
77
+
69
+static const BCM283XInfo bcm283x_socs[] = {
78
/* Floating point data-processing (2 source)
70
+ {
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
71
+ .name = TYPE_BCM2836,
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
72
+ },
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
73
+ {
82
}
74
+ .name = TYPE_BCM2837,
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
75
+ },
84
break;
76
+};
85
+ case 3:
77
+
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
78
static void bcm2836_init(Object *obj)
87
+ unallocated_encoding(s);
79
{
88
+ return;
80
BCM283XState *s = BCM283X(obj);
89
+ }
81
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
90
+ if (!fp_access_check(s)) {
82
DEFINE_PROP_END_OF_LIST()
91
+ return;
83
};
92
+ }
84
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
85
-static void bcm2836_class_init(ObjectClass *oc, void *data)
94
+ break;
86
+static void bcm283x_class_init(ObjectClass *oc, void *data)
95
default:
87
{
96
unallocated_encoding(s);
88
DeviceClass *dc = DEVICE_CLASS(oc);
97
}
89
+ BCM283XClass *bc = BCM283X_CLASS(oc);
90
91
- dc->props = bcm2836_props;
92
+ bc->info = data;
93
dc->realize = bcm2836_realize;
94
+ dc->props = bcm2836_props;
95
}
96
97
-static const TypeInfo bcm2836_type_info = {
98
+static const TypeInfo bcm283x_type_info = {
99
.name = TYPE_BCM283X,
100
.parent = TYPE_DEVICE,
101
.instance_size = sizeof(BCM283XState),
102
.instance_init = bcm2836_init,
103
- .class_init = bcm2836_class_init,
104
+ .class_size = sizeof(BCM283XClass),
105
+ .abstract = true,
106
};
107
108
static void bcm2836_register_types(void)
109
{
110
- type_register_static(&bcm2836_type_info);
111
+ int i;
112
+
113
+ type_register_static(&bcm283x_type_info);
114
+ for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
115
+ TypeInfo ti = {
116
+ .name = bcm283x_socs[i].name,
117
+ .parent = TYPE_BCM283X,
118
+ .class_init = bcm283x_class_init,
119
+ .class_data = (void *) &bcm283x_socs[i],
120
+ };
121
+ type_register(&ti);
122
+ }
123
}
124
125
type_init(bcm2836_register_types)
126
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/raspi.c
129
+++ b/hw/arm/raspi.c
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
131
BusState *bus;
132
DeviceState *carddev;
133
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
135
+ object_initialize(&s->soc, sizeof(s->soc),
136
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
137
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
138
&error_abort);
139
140
--
98
--
141
2.16.2
99
2.17.0
142
100
143
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
1
Our BCM2836 type is really a generic one that can be any of
1
From: Richard Henderson <richard.henderson@linaro.org>
2
the bcm283x family. Rename it accordingly. We change only
3
the names which are visible via the header file to the
4
rest of the QEMU code, leaving private function names
5
in bcm2836.c as they are.
6
2
7
This is a preliminary to making bcm283x be an abstract
3
We missed all of the scalar fp16 fma operations.
8
parent class to specific types for the bcm2836 and bcm2837.
9
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
14
---
11
---
15
include/hw/arm/bcm2836.h | 12 ++++++------
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
16
hw/arm/bcm2836.c | 17 +++++++++--------
13
1 file changed, 48 insertions(+)
17
hw/arm/raspi.c | 16 ++++++++--------
18
3 files changed, 23 insertions(+), 22 deletions(-)
19
14
20
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/bcm2836.h
17
--- a/target/arm/translate-a64.c
23
+++ b/include/hw/arm/bcm2836.h
18
+++ b/target/arm/translate-a64.c
24
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
25
#include "hw/arm/bcm2835_peripherals.h"
20
tcg_temp_free_i64(tcg_res);
26
#include "hw/intc/bcm2836_control.h"
27
28
-#define TYPE_BCM2836 "bcm2836"
29
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
30
+#define TYPE_BCM283X "bcm283x"
31
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
32
33
-#define BCM2836_NCPUS 4
34
+#define BCM283X_NCPUS 4
35
36
-typedef struct BCM2836State {
37
+typedef struct BCM283XState {
38
/*< private >*/
39
DeviceState parent_obj;
40
/*< public >*/
41
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
42
char *cpu_type;
43
uint32_t enabled_cpus;
44
45
- ARMCPU cpus[BCM2836_NCPUS];
46
+ ARMCPU cpus[BCM283X_NCPUS];
47
BCM2836ControlState control;
48
BCM2835PeripheralState peripherals;
49
-} BCM2836State;
50
+} BCM283XState;
51
52
#endif /* BCM2836_H */
53
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/bcm2836.c
56
+++ b/hw/arm/bcm2836.c
57
@@ -XXX,XX +XXX,XX @@
58
59
static void bcm2836_init(Object *obj)
60
{
61
- BCM2836State *s = BCM2836(obj);
62
+ BCM283XState *s = BCM283X(obj);
63
64
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
65
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
66
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
67
68
static void bcm2836_realize(DeviceState *dev, Error **errp)
69
{
70
- BCM2836State *s = BCM2836(dev);
71
+ BCM283XState *s = BCM283X(dev);
72
Object *obj;
73
Error *err = NULL;
74
int n;
75
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
76
/* common peripherals from bcm2835 */
77
78
obj = OBJECT(dev);
79
- for (n = 0; n < BCM2836_NCPUS; n++) {
80
+ for (n = 0; n < BCM283X_NCPUS; n++) {
81
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
82
s->cpu_type);
83
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
84
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
85
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
86
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
87
88
- for (n = 0; n < BCM2836_NCPUS; n++) {
89
+ for (n = 0; n < BCM283X_NCPUS; n++) {
90
/* Mirror bcm2836, which has clusterid set to 0xf
91
* TODO: this should be converted to a property of ARM_CPU
92
*/
93
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
94
}
21
}
95
22
96
static Property bcm2836_props[] = {
23
+/* Floating-point data-processing (3 source) - half precision */
97
- DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
98
- DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
25
+ int rd, int rn, int rm, int ra)
99
+ DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
26
+{
100
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
101
+ BCM283X_NCPUS),
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
102
DEFINE_PROP_END_OF_LIST()
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
103
};
30
+
104
31
+ tcg_op1 = read_fp_hreg(s, rn);
105
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
32
+ tcg_op2 = read_fp_hreg(s, rm);
106
}
33
+ tcg_op3 = read_fp_hreg(s, ra);
107
34
+
108
static const TypeInfo bcm2836_type_info = {
35
+ /* These are fused multiply-add, and must be done as one
109
- .name = TYPE_BCM2836,
36
+ * floating point operation with no rounding between the
110
+ .name = TYPE_BCM283X,
37
+ * multiplication and addition steps.
111
.parent = TYPE_DEVICE,
38
+ * NB that doing the negations here as separate steps is
112
- .instance_size = sizeof(BCM2836State),
39
+ * correct : an input NaN should come out with its sign bit
113
+ .instance_size = sizeof(BCM283XState),
40
+ * flipped if it is a negated-input.
114
.instance_init = bcm2836_init,
41
+ */
115
.class_init = bcm2836_class_init,
42
+ if (o1 == true) {
116
};
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
117
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
44
+ }
118
index XXXXXXX..XXXXXXX 100644
45
+
119
--- a/hw/arm/raspi.c
46
+ if (o0 != o1) {
120
+++ b/hw/arm/raspi.c
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
121
@@ -XXX,XX +XXX,XX @@
48
+ }
122
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
49
+
123
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
124
typedef struct RasPiState {
51
+
125
- BCM2836State soc;
52
+ write_fp_sreg(s, rd, tcg_res);
126
+ BCM283XState soc;
53
+
127
MemoryRegion ram;
54
+ tcg_temp_free_ptr(fpst);
128
} RasPiState;
55
+ tcg_temp_free_i32(tcg_op1);
129
56
+ tcg_temp_free_i32(tcg_op2);
130
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
57
+ tcg_temp_free_i32(tcg_op3);
131
BusState *bus;
58
+ tcg_temp_free_i32(tcg_res);
132
DeviceState *carddev;
59
+}
133
60
+
134
- object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
61
/* Floating point data-processing (3 source)
135
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
136
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
137
&error_abort);
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
138
65
}
139
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
140
mc->no_floppy = 1;
67
break;
141
mc->no_cdrom = 1;
68
+ case 3:
142
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
143
- mc->max_cpus = BCM2836_NCPUS;
70
+ unallocated_encoding(s);
144
- mc->min_cpus = BCM2836_NCPUS;
71
+ return;
145
- mc->default_cpus = BCM2836_NCPUS;
72
+ }
146
+ mc->max_cpus = BCM283X_NCPUS;
73
+ if (!fp_access_check(s)) {
147
+ mc->min_cpus = BCM283X_NCPUS;
74
+ return;
148
+ mc->default_cpus = BCM283X_NCPUS;
75
+ }
149
mc->default_ram_size = 1024 * 1024 * 1024;
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
150
mc->ignore_memory_transaction_failures = true;
77
+ break;
151
};
78
default:
152
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
79
unallocated_encoding(s);
153
mc->no_floppy = 1;
80
}
154
mc->no_cdrom = 1;
155
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
156
- mc->max_cpus = BCM2836_NCPUS;
157
- mc->min_cpus = BCM2836_NCPUS;
158
- mc->default_cpus = BCM2836_NCPUS;
159
+ mc->max_cpus = BCM283X_NCPUS;
160
+ mc->min_cpus = BCM283X_NCPUS;
161
+ mc->default_cpus = BCM283X_NCPUS;
162
mc->default_ram_size = 1024 * 1024 * 1024;
163
}
164
DEFINE_MACHINE("raspi3", raspi3_machine_init)
165
--
81
--
166
2.16.2
82
2.17.0
167
83
168
84
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
1
1
From: Alex Bennée <alex.bennee@linaro.org>
2
3
These where missed out from the rest of the half-precision work.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/helper-a64.h | 2 +
16
target/arm/helper-a64.c | 10 +++++
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
23
+++ b/target/arm/helper-a64.h
24
@@ -XXX,XX +XXX,XX @@
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
36
+++ b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
38
return flags;
39
}
40
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
42
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
44
+}
45
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
52
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
60
}
61
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
63
+static void handle_fp_compare(DisasContext *s, int size,
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
165
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
215
2.17.0
216
217
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
1
If we're directly booting a Linux kernel and the CPU supports both
1
From: Alex Bennée <alex.bennee@linaro.org>
2
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
3
set the SCR_EL3.HCE bit in this situation, so that the HVC
4
instruction is enabled rather than UNDEFing. Otherwise at least some
5
kernels will panic when trying to initialize KVM in the guest.
6
2
3
These were missed out from the rest of the half-precision work.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
9
---
14
---
10
hw/arm/boot.c | 5 +++++
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
11
1 file changed, 5 insertions(+)
16
1 file changed, 25 insertions(+), 6 deletions(-)
12
17
13
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/boot.c
20
--- a/target/arm/translate-a64.c
16
+++ b/hw/arm/boot.c
21
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
18
assert(!info->secure_board_setup);
23
unsigned int mos, type, rm, cond, rn, rd;
19
}
24
TCGv_i64 t_true, t_false, t_zero;
20
25
DisasCompare64 c;
21
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
26
+ TCGMemOp sz;
22
+ /* If we have EL2 then Linux expects the HVC insn to work */
27
23
+ env->cp15.scr_el3 |= SCR_HCE;
28
mos = extract32(insn, 29, 3);
24
+ }
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
30
+ type = extract32(insn, 22, 2);
31
rm = extract32(insn, 16, 5);
32
cond = extract32(insn, 12, 4);
33
rn = extract32(insn, 5, 5);
34
rd = extract32(insn, 0, 5);
35
36
- if (mos || type > 1) {
37
+ if (mos) {
38
+ unallocated_encoding(s);
39
+ return;
40
+ }
25
+
41
+
26
/* Set to non-secure if not a secure boot */
42
+ switch (type) {
27
if (!info->secure_boot &&
43
+ case 0:
28
(cs != first_cpu || !info->secure_board_setup)) {
44
+ sz = MO_32;
45
+ break;
46
+ case 1:
47
+ sz = MO_64;
48
+ break;
49
+ case 3:
50
+ sz = MO_16;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
52
+ break;
53
+ }
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
60
return;
61
}
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
29
--
83
--
30
2.16.2
84
2.17.0
31
85
32
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
1
Add some assertions that if we're about to boot an AArch64 kernel,
1
From: Alex Bennée <alex.bennee@linaro.org>
2
the board code has not mistakenly set either secure_boot or
3
secure_board_setup. It doesn't make sense to set secure_boot,
4
because all AArch64 kernels must be booted in non-secure mode.
5
2
6
It might in theory make sense to set secure_board_setup, but
3
All the hard work is already done by vfp_expand_imm, we just need to
7
we don't currently support that, because only the AArch32
4
make sure we pick up the correct size.
8
bootloader[] code calls this hook; bootloader_aarch64[] does not.
9
Since we don't have a current need for this functionality, just
10
assert that we don't try to use it. If it's needed we'll add
11
it later.
12
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
16
---
15
---
17
hw/arm/boot.c | 7 +++++++
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
18
1 file changed, 7 insertions(+)
17
1 file changed, 17 insertions(+), 3 deletions(-)
19
18
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
21
--- a/target/arm/translate-a64.c
23
+++ b/hw/arm/boot.c
22
+++ b/target/arm/translate-a64.c
24
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
25
} else {
24
{
26
env->pstate = PSTATE_MODE_EL1h;
25
int rd = extract32(insn, 0, 5);
27
}
26
int imm8 = extract32(insn, 13, 8);
28
+ /* AArch64 kernels never boot in secure mode */
27
- int is_double = extract32(insn, 22, 2);
29
+ assert(!info->secure_boot);
28
+ int type = extract32(insn, 22, 2);
30
+ /* This hook is only supported for AArch32 currently:
29
uint64_t imm;
31
+ * bootloader_aarch64[] will not call the hook, and
30
TCGv_i64 tcg_res;
32
+ * the code above has already dropped us into EL2 or EL1.
31
+ TCGMemOp sz;
33
+ */
32
34
+ assert(!info->secure_board_setup);
33
- if (is_double > 1) {
35
}
34
+ switch (type) {
36
35
+ case 0:
37
/* Set to non-secure if not a secure boot */
36
+ sz = MO_32;
37
+ break;
38
+ case 1:
39
+ sz = MO_64;
40
+ break;
41
+ case 3:
42
+ sz = MO_16;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
44
+ break;
45
+ }
46
+ /* fallthru */
47
+ default:
48
unallocated_encoding(s);
49
return;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
52
return;
53
}
54
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
56
+ imm = vfp_expand_imm(sz, imm8);
57
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
38
--
60
--
39
2.16.2
61
2.17.0
40
62
41
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
1
From: Wei Huang <wei@redhat.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
For guest kernel that supports KASLR, the load address can change every
3
We are meant to explicitly pass fpst, not cpu_env.
4
time when guest VM runs. To find the physical base address correctly,
5
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
6
However this string pattern is only available on x86_64. AArch64 uses a
7
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
8
QEMU dump uses the correct string on AArch64.
9
4
10
Signed-off-by: Wei Huang <wei@redhat.com>
5
Cc: qemu-stable@nongnu.org
11
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
dump.c | 14 +++++++++++---
13
target/arm/translate-a64.c | 3 ++-
16
1 file changed, 11 insertions(+), 3 deletions(-)
14
1 file changed, 2 insertions(+), 1 deletion(-)
17
15
18
diff --git a/dump.c b/dump.c
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/dump.c
18
--- a/target/arm/translate-a64.c
21
+++ b/dump.c
19
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
23
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
24
lines = g_strsplit((char *)vmci, "\n", -1);
22
break;
25
for (i = 0; lines[i]; i++) {
23
case 0x3: /* FSQRT */
26
- if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
27
- if (qemu_strtou64(lines[i] + 18, NULL, 16,
25
+ fpst = get_fpstatus_ptr(true);
28
+ const char *prefix = NULL;
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
29
+
27
break;
30
+ if (s->dump_info.d_machine == EM_X86_64) {
28
case 0x8: /* FRINTN */
31
+ prefix = "NUMBER(phys_base)=";
29
case 0x9: /* FRINTP */
32
+ } else if (s->dump_info.d_machine == EM_AARCH64) {
33
+ prefix = "NUMBER(PHYS_OFFSET)=";
34
+ }
35
+
36
+ if (prefix && g_str_has_prefix(lines[i], prefix)) {
37
+ if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
38
&phys_base) < 0) {
39
- warn_report("Failed to read NUMBER(phys_base)=");
40
+ warn_report("Failed to read %s", prefix);
41
} else {
42
s->dump_info.phys_base = phys_base;
43
}
44
--
30
--
45
2.16.2
31
2.17.0
46
32
47
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Code of imx_update() is slightly confusing since the "flags" variable
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
4
doesn't really corespond to anything in real hardware and server as a
5
kitchensink accumulating events normally reported via USR1 and USR2
6
registers.
7
4
8
Change the code to explicitly evaluate state of interrupts reported
5
The block length is predefined to 512 bits
9
via USR1 and USR2 against corresponding masking bits and use the to
10
detemine if IRQ line should be asserted or not.
11
6
12
NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
7
and "4.10.2 SD Status":
13
reasons:
14
8
15
1. Emulation code implements a single character FIFO, so this flag
9
The SD Status contains status bits that are related to the SD Memory Card
16
will always be set since characters are trasmitted as a part of
10
proprietary features and may be used for future application-specific usage.
17
the code emulating "push" into the FIFO
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
18
13
19
2. imx_update() is really just a function doing ORing and maksing
14
Thus the 16-bit CRC goes at offset 64.
20
of reported events, so checking for UTS1_TXEMPTY should happen,
21
if it's ever really needed should probably happen outside of
22
it.
23
15
24
Cc: qemu-devel@nongnu.org
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Cc: qemu-arm@nongnu.org
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
26
Cc: Bill Paul <wpaul@windriver.com>
27
Cc: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
29
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
---
20
---
33
hw/char/imx_serial.c | 24 ++++++++++++++++--------
21
hw/sd/sd.c | 2 +-
34
1 file changed, 16 insertions(+), 8 deletions(-)
22
1 file changed, 1 insertion(+), 1 deletion(-)
35
23
36
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
37
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/char/imx_serial.c
26
--- a/hw/sd/sd.c
39
+++ b/hw/char/imx_serial.c
27
+++ b/hw/sd/sd.c
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
41
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
42
static void imx_update(IMXSerialState *s)
30
}
43
{
31
memset(&sd->data[17], 0, 47);
44
- uint32_t flags;
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
45
+ uint32_t usr1;
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
46
+ uint32_t usr2;
47
+ uint32_t mask;
48
49
- flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
50
- if (s->ucr1 & UCR1_TXMPTYEN) {
51
- flags |= (s->uts1 & UTS1_TXEMPTY);
52
- } else {
53
- flags &= ~USR1_TRDY;
54
- }
55
+ /*
56
+ * Lucky for us TRDY and RRDY has the same offset in both USR1 and
57
+ * UCR1, so we can get away with something as simple as the
58
+ * following:
59
+ */
60
+ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
61
+ /*
62
+ * Bits that we want in USR2 are not as conveniently laid out,
63
+ * unfortunately.
64
+ */
65
+ mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
66
+ usr2 = s->usr2 & mask;
67
68
- qemu_set_irq(s->irq, !!flags);
69
+ qemu_set_irq(s->irq, usr1 || usr2);
70
}
34
}
71
35
72
static void imx_serial_reset(IMXSerialState *s)
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
73
--
37
--
74
2.16.2
38
2.17.0
75
39
76
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
1
For the rpi1 and 2 we want to boot the Linux kernel via some
1
Usually the logging of the CPU state produced by -d cpu is sufficient
2
custom setup code that makes sure that the SMC instruction
2
to diagnose problems, but sometimes you want to see the state of
3
acts as a no-op, because it's used for cache maintenance.
3
the floating point registers as well. We don't want to enable that
4
The rpi3 boots AArch64 kernels, which don't need SMC for
4
by default as it adds a lot of extra data to the log; instead,
5
cache maintenance and always expect to be booted non-secure.
5
allow it to be optionally enabled via -d fpu.
6
Don't fill in the aarch32-specific parts of the binfo struct.
7
6
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
11
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
12
---
10
---
13
hw/arm/raspi.c | 17 +++++++++++++----
11
include/qemu/log.h | 1 +
14
1 file changed, 13 insertions(+), 4 deletions(-)
12
accel/tcg/cpu-exec.c | 9 ++++++---
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
18
--- a/include/qemu/log.h
19
+++ b/hw/arm/raspi.c
19
+++ b/include/qemu/log.h
20
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
21
binfo.board_id = raspi_boardid[version];
21
#define CPU_LOG_PAGE (1 << 14)
22
binfo.ram_size = ram_size;
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
23
binfo.nb_cpus = smp_cpus;
23
#define CPU_LOG_TB_OP_IND (1 << 16)
24
- binfo.board_setup_addr = BOARDSETUP_ADDR;
24
+#define CPU_LOG_TB_FPU (1 << 17)
25
- binfo.write_board_setup = write_board_setup;
25
26
- binfo.secure_board_setup = true;
26
/* Lock output for a series of related logs. Since this is not needed
27
- binfo.secure_boot = true;
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
28
+
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
29
+ if (version <= 2) {
29
index XXXXXXX..XXXXXXX 100644
30
+ /* The rpi1 and 2 require some custom setup code to run in Secure
30
--- a/accel/tcg/cpu-exec.c
31
+ * mode before booting a kernel (to set up the SMC vectors so
31
+++ b/accel/tcg/cpu-exec.c
32
+ * that we get a no-op SMC; this is used by Linux to call the
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
33
+ * firmware for some cache maintenance operations.
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
34
+ * The rpi3 doesn't need this.
34
&& qemu_log_in_addr_range(itb->pc)) {
35
+ */
35
qemu_log_lock();
36
+ binfo.board_setup_addr = BOARDSETUP_ADDR;
36
+ int flags = 0;
37
+ binfo.write_board_setup = write_board_setup;
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
38
+ binfo.secure_board_setup = true;
38
+ flags |= CPU_DUMP_FPU;
39
+ binfo.secure_boot = true;
39
+ }
40
+ }
40
#if defined(TARGET_I386)
41
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
42
/* Pi2 and Pi3 requires SMP setup */
42
-#else
43
if (version >= 2) {
43
- log_cpu_state(cpu, 0);
44
+ flags |= CPU_DUMP_CCOP;
45
#endif
46
+ log_cpu_state(cpu, flags);
47
qemu_log_unlock();
48
}
49
#endif /* DEBUG_DISAS */
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
44
--
63
--
45
2.16.2
64
2.17.0
46
65
47
66
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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