Arm pullreq for the 2.12 codefreeze...

The following changes since commit b39b61e410022f96ceb53d4381d25cba5126ac44:

memory: fix flatview_access_valid RCU read lock/unlock imbalance (2018-03-09 15:55:20 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180309

for you to fetch changes up to 076a0fc32a73a9b960e0f73f04a531bc1bd94308:

MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard) (2018-03-09 17:09:45 +0000)

* i.MX: Add i.MX7 SOC implementation and i.MX7 Sabre board

* Report the correct core count in A53 L2CTLR on the ZynqMP board

* linux-user: preliminary SVE support work (signal handling)

* hw/arm/boot: fix memory leak in case of error loading ELF file

* hw/arm/boot: avoid reading off end of buffer if passed very

small image file

* hw/arm: Use more CONFIG switches for the object files

* target/arm: Add "-cpu max" support

* hw/arm/virt: Support -machine gic-version=max

* hw/sd: improve debug tracing

* hw/sd: sdcard: Add the Tuning Command (CMD 19)

* MAINTAINERS: add Philippe as odd-fixes maintainer for SD

Alistair Francis (2):

target/arm: Add a core count property

hw/arm: Set the core count for Xilinx's ZynqMP

Andrey Smirnov (3):

pci: Add support for Designware IP block

i.MX: Add i.MX7 SOC implementation.

Implement support for i.MX7 Sabre board

Marc-André Lureau (2):

arm: fix load ELF error leak

arm: avoid heap-buffer-overflow in load_aarch64_image

Peter Maydell (6):

target/arm: Query host CPU features on-demand at instance init

target/arm: Move definition of 'host' cpu type into cpu.c

target/arm: Add "-cpu max" support

target/arm: Make 'any' CPU just an alias for 'max'

hw/arm/virt: Add "max" to the list of CPU types "virt" supports

hw/arm/virt: Support -machine gic-version=max

Philippe Mathieu-Daudé (6):

sdcard: Do not trace CMD55, except when we already expect an ACMD

sdcard: Display command name when tracing CMD/ACMD

sdcard: Display which protocol is used when tracing (SD or SPI)

sdcard: Add the Tuning Command (CMD19)

sdhci: Fix a typo in comment

MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

After spending months studying all the different SD Specifications

from the SD Association, voluntarily add myself as maintainer

for the SD code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20180309153654.13518-9-f4bug@amsat.org

MAINTAINERS | 8 ++++++++

1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

S: Maintained

F: hw/ssi/xilinx_*

+SD (Secure Card)

+M: Philippe Mathieu-Daudé <f4bug@amsat.org>

+S: Odd Fixes

+F: include/hw/sd/sd*

+F: hw/sd/core.c

+F: hw/sd/sd*

+F: tests/sd*

+

USB

M: Gerd Hoffmann <kraxel@redhat.com>

S: Maintained

2.16.2

Now we have a working '-cpu max', the linux-user-only

'any' CPU is pretty much the same thing, so implement it

that way.

For the moment we don't add any of the extra feature bits

to the system-emulation "max", because we don't set the

ID register bits we would need to to advertise those

features as present.

Message-id: 20180308130626.12393-5-peter.maydell@linaro.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

target/arm/cpu.c | 52 +++++++++++++++++++++++++----------------------

target/arm/cpu64.c | 59 ++++++++++++++++++++++++++----------------------------

2 files changed, 56 insertions(+), 55 deletions(-)

@@ -XXX,XX +XXX,XX @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)

ObjectClass *oc;

char *typename;

char **cpuname;

+ const char *cpunamestr;

cpuname = g_strsplit(cpu_model, ",", 1);

- typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]);

+ cpunamestr = cpuname[0];

+#ifdef CONFIG_USER_ONLY

+ /* For backwards compatibility usermode emulation allows "-cpu any",

+ * which has the same semantics as "-cpu max".

+ */

+ if (!strcmp(cpunamestr, "any")) {

+ cpunamestr = "max";

+ }

+ typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);

oc = object_class_by_name(typename);

g_strfreev(cpuname);

g_free(typename);

@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)

kvm_arm_set_cpu_features_from_host(cpu);

} else {

cortex_a15_initfn(obj);

- /* In future we might add feature bits here even if the

- * real-world A15 doesn't implement them.

- */

- }

-}

-#endif

-

#ifdef CONFIG_USER_ONLY

-static void arm_any_initfn(Object *obj)

-{

- ARMCPU *cpu = ARM_CPU(obj);

- set_feature(&cpu->env, ARM_FEATURE_V8);

- set_feature(&cpu->env, ARM_FEATURE_VFP4);

- set_feature(&cpu->env, ARM_FEATURE_NEON);

- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);

- set_feature(&cpu->env, ARM_FEATURE_V8_AES);

- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

- set_feature(&cpu->env, ARM_FEATURE_CRC);

- set_feature(&cpu->env, ARM_FEATURE_V8_RDM);

- set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);

- cpu->midr = 0xffffffff;

+ /* We don't set these in system emulation mode for the moment,

+ * since we don't correctly set the ID registers to advertise them,

+ set_feature(&cpu->env, ARM_FEATURE_V8);

+ set_feature(&cpu->env, ARM_FEATURE_VFP4);

+ set_feature(&cpu->env, ARM_FEATURE_NEON);

+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);

+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

+ set_feature(&cpu->env, ARM_FEATURE_CRC);

+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);

+ set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);

+#endif

+ }

}

#endif

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {

{ .name = "max", .initfn = arm_max_initfn },

#endif

#ifdef CONFIG_USER_ONLY

- { .name = "any", .initfn = arm_any_initfn },

+ { .name = "any", .initfn = arm_max_initfn },

#endif

#endif

{ .name = NULL }

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

kvm_arm_set_cpu_features_from_host(cpu);

} else {

aarch64_a57_initfn(obj);

- /* In future we might add feature bits here even if the

- * real-world A57 doesn't implement them.

+#ifdef CONFIG_USER_ONLY

+ /* We don't set these in system emulation mode for the moment,

+ * since we don't correctly set the ID registers to advertise them,

+ * and in some cases they're only available in AArch64 and not AArch32,

+ * whereas the architecture requires them to be present in both if

+ * present in either.

*/

+ set_feature(&cpu->env, ARM_FEATURE_V8);

+ set_feature(&cpu->env, ARM_FEATURE_VFP4);

+ set_feature(&cpu->env, ARM_FEATURE_NEON);

+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);

+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SM3);

+ set_feature(&cpu->env, ARM_FEATURE_V8_SM4);

+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

+ set_feature(&cpu->env, ARM_FEATURE_CRC);

+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);

+ set_feature(&cpu->env, ARM_FEATURE_V8_FP16);

+ set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);

+ /* For usermode -cpu max we can use a larger and more efficient DCZ

+ * blocksize since we don't have to follow what the hardware does.

+ */

+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */

+ cpu->dcz_blocksize = 7; /* 512 bytes */

}

-#ifdef CONFIG_USER_ONLY

-static void aarch64_any_initfn(Object *obj)

-{

- ARMCPU *cpu = ARM_CPU(obj);

-

- set_feature(&cpu->env, ARM_FEATURE_V8);

- set_feature(&cpu->env, ARM_FEATURE_VFP4);

- set_feature(&cpu->env, ARM_FEATURE_NEON);

- set_feature(&cpu->env, ARM_FEATURE_AARCH64);

- set_feature(&cpu->env, ARM_FEATURE_V8_AES);

- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

- set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);

- set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);

- set_feature(&cpu->env, ARM_FEATURE_V8_SM3);

- set_feature(&cpu->env, ARM_FEATURE_V8_SM4);

- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

- set_feature(&cpu->env, ARM_FEATURE_CRC);

- set_feature(&cpu->env, ARM_FEATURE_V8_RDM);

- set_feature(&cpu->env, ARM_FEATURE_V8_FP16);

- set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);

- cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */

- cpu->dcz_blocksize = 7; /* 512 bytes */

-}

-#endif

-

typedef struct ARMCPUInfo {

const char *name;

void (*initfn)(Object *obj);

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {

{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },

{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },

{ .name = "max", .initfn = aarch64_max_initfn },

-#ifdef CONFIG_USER_ONLY

- { .name = "any", .initfn = aarch64_any_initfn },

-#endif

{ .name = NULL }

};

2.16.2

Add support for "-cpu max" for ARM guests. This CPU type behaves

like "-cpu host" when KVM is enabled, and like a system CPU with

the maximum possible feature set otherwise. (Note that this means

it won't be migratable across versions, as we will likely add

features to it in future.)

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180308130626.12393-4-peter.maydell@linaro.org

target/arm/cpu-qom.h | 2 ++

target/arm/cpu.c | 24 ++++++++++++++++++++++++

target/arm/cpu64.c | 21 +++++++++++++++++++++

3 files changed, 47 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)

cpu->reset_sctlr = 0x00000078;

}

+#ifndef TARGET_AARCH64

+/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);

+ * otherwise, a CPU with as many features enabled as our emulation supports.

+ * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;

+ * this only needs to handle 32 bits.

+ */

+static void arm_max_initfn(Object *obj)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+

+ if (kvm_enabled()) {

+ kvm_arm_set_cpu_features_from_host(cpu);

+ } else {

+ cortex_a15_initfn(obj);

+ /* In future we might add feature bits here even if the

+ * real-world A15 doesn't implement them.

+ */

+ }

+}

#ifdef CONFIG_USER_ONLY

static void arm_any_initfn(Object *obj)

{

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {

{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },

{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },

{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },

+#ifndef TARGET_AARCH64

+ { .name = "max", .initfn = arm_max_initfn },

+#endif

#ifdef CONFIG_USER_ONLY

{ .name = "any", .initfn = arm_any_initfn },

#endif

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/arm.h"

#include "sysemu/sysemu.h"

#include "sysemu/kvm.h"

+#include "kvm_arm.h"

static inline void set_feature(CPUARMState *env, int feature)

{

@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)

define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);

}

+/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);

+ * otherwise, a CPU with as many features enabled as our emulation supports.

+ * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;

+ * this only needs to handle 64 bits.

+ */

+static void aarch64_max_initfn(Object *obj)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+

+ if (kvm_enabled()) {

+ kvm_arm_set_cpu_features_from_host(cpu);

+ } else {

+ aarch64_a57_initfn(obj);

+ /* In future we might add feature bits here even if the

+ * real-world A57 doesn't implement them.

+ */

+ }

+}

+

#ifdef CONFIG_USER_ONLY

static void aarch64_any_initfn(Object *obj)

{

@@ -XXX,XX +XXX,XX @@ typedef struct ARMCPUInfo {

static const ARMCPUInfo aarch64_cpus[] = {

{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },

{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },

+ { .name = "max", .initfn = aarch64_max_initfn },

#ifdef CONFIG_USER_ONLY

{ .name = "any", .initfn = aarch64_any_initfn },

#endif

2.16.2

From: Alistair Francis <alistair.francis@xilinx.com>

The cortex A53 TRM specifies that bits 24 and 25 of the L2CTLR register

specify the number of cores in the processor, not the total number of

cores in the system. To report this correctly on machines with multiple

CPU clusters (ARM's big.LITTLE or Xilinx's ZynqMP) we need to allow

the machine to overwrite this value. To do this let's add an optional

property.

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

cs->num_ases = 1;

cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);

+ /* No core_count specified, default to smp_cpus. */

+ if (cpu->core_count == -1) {

+ cpu->core_count = smp_cpus;

qemu_init_vcpu(cs);

@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {

DEFINE_PROP_UINT64("mp-affinity", ARMCPU,

mp_affinity, ARM64_AFFINITY_INVALID),

DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),

+ DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),

DEFINE_PROP_END_OF_LIST()

};

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static inline void unset_feature(CPUARMState *env, int feature)

#ifndef CONFIG_USER_ONLY

static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)

{

- /* Number of processors is in [25:24]; otherwise we RAZ */

- return (smp_cpus - 1) << 24;

+ ARMCPU *cpu = arm_env_get_cpu(env);

+

+ /* Number of cores is in [25:24]; otherwise we RAZ */

+ return (cpu->core_count - 1) << 24;

}

2.16.2

From: Marc-André Lureau <marcandre.lureau@redhat.com>

Spotted by ASAN:

elmarco@boraha:~/src/qemu/build (master *%)$ QTEST_QEMU_BINARY=aarch64-softmmu/qemu-system-aarch64 tests/boot-serial-test

/aarch64/boot-serial/virt: ** (process:19740): DEBUG: 18:39:30.275: foo /tmp/qtest-boot-serial-cXaS94D

=================================================================

==19740==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x603000069648 at pc 0x7f1d2201cc54 bp 0x7fff331f6a40 sp 0x7fff331f61e8

READ of size 4 at 0x603000069648 thread T0

#0 0x7f1d2201cc53 (/lib64/libasan.so.4+0xafc53)

#1 0x55bc86685ee3 in load_aarch64_image /home/elmarco/src/qemu/hw/arm/boot.c:894

#2 0x55bc86687217 in arm_load_kernel_notify /home/elmarco/src/qemu/hw/arm/boot.c:1047

#3 0x55bc877363b5 in notifier_list_notify /home/elmarco/src/qemu/util/notify.c:40

#4 0x55bc869331ea in qemu_run_machine_init_done_notifiers /home/elmarco/src/qemu/vl.c:2716

#5 0x55bc8693bc39 in main /home/elmarco/src/qemu/vl.c:4679

#6 0x7f1d1652c009 in __libc_start_main (/lib64/libc.so.6+0x21009)

#7 0x55bc86255cc9 in _start (/home/elmarco/src/qemu/build/aarch64-softmmu/qemu-system-aarch64+0x1ae5cc9)

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>

hw/arm/boot.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c

--- a/hw/arm/boot.c

+++ b/hw/arm/boot.c

@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,

/* check the arm64 magic header value -- very old kernels may not have it */

- if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {

+ if (size > ARM64_MAGIC_OFFSET + 4 &&

+ memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {

uint64_t hdrvals[2];

/* The arm64 Image header has text_offset and image_size fields at 8 and

2.16.2

From: Richard Henderson <richard.henderson@linaro.org>

Split out helpers from target_setup_frame and target_restore_sigframe

for dealing with general registers, fpsimd registers, and the end record.

When we add support for sve registers, the relative positions of

these will change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180303143823.27055-3-richard.henderson@linaro.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

linux-user/signal.c | 120 ++++++++++++++++++++++++++++++----------------------

1 file changed, 69 insertions(+), 51 deletions(-)

diff --git a/linux-user/signal.c b/linux-user/signal.c

--- a/linux-user/signal.c

+++ b/linux-user/signal.c

@@ -XXX,XX +XXX,XX @@ struct target_rt_sigframe {

uint32_t tramp[2];

-static int target_setup_sigframe(struct target_rt_sigframe *sf,

- CPUARMState *env, target_sigset_t *set)

+static void target_setup_general_frame(struct target_rt_sigframe *sf,

+ CPUARMState *env, target_sigset_t *set)

{

int i;

- struct target_aux_context *aux =

- (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved;

- /* set up the stack frame for unwinding */

- __put_user(env->xregs[29], &sf->fp);

- __put_user(env->xregs[30], &sf->lr);

+ __put_user(0, &sf->uc.tuc_flags);

+ __put_user(0, &sf->uc.tuc_link);

+ __put_user(target_sigaltstack_used.ss_sp, &sf->uc.tuc_stack.ss_sp);

+ __put_user(sas_ss_flags(env->xregs[31]), &sf->uc.tuc_stack.ss_flags);

+ __put_user(target_sigaltstack_used.ss_size, &sf->uc.tuc_stack.ss_size);

for (i = 0; i < 31; i++) {

__put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);

@@ -XXX,XX +XXX,XX @@ static int target_setup_sigframe(struct target_rt_sigframe *sf,

for (i = 0; i < TARGET_NSIG_WORDS; i++) {

__put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]);

}

+static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsimd,

+ CPUARMState *env)

+ int i;

+

+ __put_user(TARGET_FPSIMD_MAGIC, &fpsimd->head.magic);

+ __put_user(sizeof(struct target_fpsimd_context), &fpsimd->head.size);

+ __put_user(vfp_get_fpsr(env), &fpsimd->fpsr);

+ __put_user(vfp_get_fpcr(env), &fpsimd->fpcr);

for (i = 0; i < 32; i++) {

uint64_t *q = aa64_vfp_qreg(env, i);

#ifdef TARGET_WORDS_BIGENDIAN

- __put_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]);

- __put_user(q[1], &aux->fpsimd.vregs[i * 2]);

+ __put_user(q[0], &fpsimd->vregs[i * 2 + 1]);

+ __put_user(q[1], &fpsimd->vregs[i * 2]);

#else

- __put_user(q[0], &aux->fpsimd.vregs[i * 2]);

- __put_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]);

+ __put_user(q[0], &fpsimd->vregs[i * 2]);

+ __put_user(q[1], &fpsimd->vregs[i * 2 + 1]);

#endif

}

- __put_user(vfp_get_fpsr(env), &aux->fpsimd.fpsr);

- __put_user(vfp_get_fpcr(env), &aux->fpsimd.fpcr);

- __put_user(TARGET_FPSIMD_MAGIC, &aux->fpsimd.head.magic);

- __put_user(sizeof(struct target_fpsimd_context),

- &aux->fpsimd.head.size);

-

- /* set the "end" magic */

- __put_user(0, &aux->end.magic);

- __put_user(0, &aux->end.size);

-

- return 0;

}

-static int target_restore_sigframe(CPUARMState *env,

- struct target_rt_sigframe *sf)

+static void target_setup_end_record(struct target_aarch64_ctx *end)

+{

+ __put_user(0, &end->magic);

+ __put_user(0, &end->size);

}

- __get_user(fpsr, &aux->fpsimd.fpsr);

- vfp_set_fpsr(env, fpsr);

- __get_user(fpcr, &aux->fpsimd.fpcr);

- vfp_set_fpcr(env, fpcr);

+}

+static int target_restore_sigframe(CPUARMState *env,

+ struct target_rt_sigframe *sf)

+{

+ struct target_aux_context *aux

+ = (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved;

+ uint32_t magic, size;

+

+ target_restore_general_frame(env, sf);

+

+ __get_user(magic, &aux->fpsimd.head.magic);

+ __get_user(size, &aux->fpsimd.head.size);

+ if (magic == TARGET_FPSIMD_MAGIC

+ && size == sizeof(struct target_fpsimd_context)) {

+ target_restore_fpsimd_record(env, &aux->fpsimd);

+ } else {

+ return 1;

+ }

return 0;

}

@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,

CPUARMState *env)

{

struct target_rt_sigframe *frame;

+ struct target_aux_context *aux;

abi_ulong frame_addr, return_addr;

frame_addr = get_sigframe(ka, env);

@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,

if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {

goto give_sigsegv;

}

+ aux = (struct target_aux_context *)frame->uc.tuc_mcontext.__reserved;

- __put_user(0, &frame->uc.tuc_flags);

- __put_user(0, &frame->uc.tuc_link);

+ target_setup_general_frame(frame, env, set);

+ target_setup_fpsimd_record(&aux->fpsimd, env);

+ target_setup_end_record(&aux->end);

- __put_user(target_sigaltstack_used.ss_sp,

- &frame->uc.tuc_stack.ss_sp);

- __put_user(sas_ss_flags(env->xregs[31]),

- &frame->uc.tuc_stack.ss_flags);

- __put_user(target_sigaltstack_used.ss_size,

- &frame->uc.tuc_stack.ss_size);

- target_setup_sigframe(frame, env, set);

if (ka->sa_flags & TARGET_SA_RESTORER) {

return_addr = ka->sa_restorer;

} else {

2.16.2

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

From the "Physical Layer Simplified Specification Version 3.01":

A known data block ("Tuning block") can be used to tune sampling

point for tuning required hosts. [...]

This procedure gives the system optimal timing for each specific

host and card combination and compensates for static delays in

the timing budget including process, voltage and different PCB

loads and skews. [...]

Data block, carried by DAT[3:0], contains a pattern for tuning

sampling position to receive data on the CMD and DAT[3:0] line.

[based on a patch from Alistair Francis <alistair.francis@xilinx.com>

from qemu/xilinx tag xilinx-v2015.2]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Message-id: 20180309153654.13518-5-f4bug@amsat.org

hw/sd/sd.c | 29 +++++++++++++++++++++++++++++

1 file changed, 29 insertions(+)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c

--- a/hw/sd/sd.c

+++ b/hw/sd/sd.c

@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)

}

break;

+ case 19: /* CMD19: SEND_TUNING_BLOCK (SD) */

+ if (sd->state == sd_transfer_state) {

+ sd->state = sd_sendingdata_state;

+ sd->data_offset = 0;

+ return sd_r1;

+ }

+ break;

+

case 23: /* CMD23: SET_BLOCK_COUNT */

switch (sd->state) {

case sd_transfer_state:

@@ -XXX,XX +XXX,XX @@ void sd_write_data(SDState *sd, uint8_t value)

2.16.2

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Acked-by: Alistair Francis <alistair.francis@xilinx.com>

Message-id: 20180309153654.13518-2-f4bug@amsat.org

hw/sd/sd.c | 11 ++++++++---

1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c

--- a/hw/sd/sd.c

+++ b/hw/sd/sd.c

@@ -XXX,XX +XXX,XX @@ static void sd_lock_command(SDState *sd)

sd->card_status &= ~CARD_IS_LOCKED;

-static sd_rsp_type_t sd_normal_command(SDState *sd,

- SDRequest req)

+static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)

uint32_t rca = 0x0000;

uint64_t addr = (sd->ocr & (1 << 30)) ? (uint64_t) req.arg << 9 : req.arg;

- trace_sdcard_normal_command(req.cmd, req.arg, sd_state_name(sd->state));

+ /* CMD55 precedes an ACMD, so we are not interested in tracing it.

+ * However there is no ACMD55, so we want to trace this particular case.

+ */

+ if (req.cmd != 55 || sd->expecting_acmd) {

+ trace_sdcard_normal_command(req.cmd, req.arg,

+ sd_state_name(sd->state));

+ }

/* Not interpreting this as an app command */

sd->card_status &= ~APP_CMD;

2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

The following interfaces are partially or fully emulated:

* up to 2 Cortex A9 cores (SMP works with PSCI)

* A7 MPCORE (identical to A15 MPCORE)

* 4 GPTs modules

* 7 GPIO controllers

* 2 IOMUXC controllers

* 1 CCM module

* 1 SVNS module

* 1 SRC module

* 1 GPCv2 controller

* 4 eCSPI controllers

* 4 I2C controllers

* 7 i.MX UART controllers

* 2 FlexCAN controllers

* 2 Ethernet controllers (FEC)

* 3 SD controllers (USDHC)

* 4 WDT modules

* 1 SDMA module

* 1 GPR module

* 2 USBMISC modules

* 2 ADC modules

* 1 PCIe controller

Tested to boot and work with upstream Linux (4.13+) guest.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

[PMM: folded a couple of long lines]

hw/arm/Makefile.objs | 1 +

include/hw/arm/fsl-imx7.h | 222 +++++++++++++++

hw/arm/fsl-imx7.c | 582 ++++++++++++++++++++++++++++++++++++++++

default-configs/arm-softmmu.mak | 1 +

4 files changed, 806 insertions(+)

create mode 100644 include/hw/arm/fsl-imx7.h

create mode 100644 hw/arm/fsl-imx7.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MPS2) += mps2.o

obj-$(CONFIG_MPS2) += mps2-tz.o

obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

obj-$(CONFIG_IOTKIT) += iotkit.o

+obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h