1 | Second pull request of the week; mostly RTH's support for some | 1 | The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87: |
---|---|---|---|
2 | new-in-v8.1/v8.3 instructions, and my v8M board model. | ||
3 | 2 | ||
4 | thanks | 3 | Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000) |
5 | -- PMM | ||
6 | |||
7 | The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f: | ||
8 | |||
9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000) | ||
10 | 4 | ||
11 | are available in the Git repository at: | 5 | are available in the Git repository at: |
12 | 6 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308 |
14 | 8 | ||
15 | for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078: | 9 | for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9: |
16 | 10 | ||
17 | target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000) | 11 | target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000) |
18 | 12 | ||
19 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
20 | target-arm queue: | 14 | target-arm queue: |
21 | * implement FCMA and RDM v8.1 and v8.3 instructions | 15 | * Implement FEAT_ECV |
22 | * enable Cortex-M33 v8M core, and provide new mps2-an505 board model | 16 | * STM32L4x5: Implement GPIO device |
23 | that uses it | 17 | * Fix 32-bit SMOPA |
24 | * decodetree: Propagate return value from translate subroutines | 18 | * Refactor v7m related code from cpu32.c into its own file |
25 | * xlnx-zynqmp: Implement the RTC device | 19 | * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later |
26 | 20 | ||
27 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
28 | Alistair Francis (3): | 22 | Inès Varhol (3): |
29 | xlnx-zynqmp-rtc: Initial commit | 23 | hw/gpio: Implement STM32L4x5 GPIO |
30 | xlnx-zynqmp-rtc: Add basic time support | 24 | hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC |
31 | xlnx-zynqmp: Connect the RTC device | 25 | tests/qtest: Add STM32L4x5 GPIO QTest testcase |
32 | 26 | ||
33 | Peter Maydell (19): | 27 | Peter Maydell (9): |
34 | loader: Add new load_ramdisk_as() | 28 | target/arm: Move some register related defines to internals.h |
35 | hw/arm/boot: Honour CPU's address space for image loads | 29 | target/arm: Timer _EL02 registers UNDEF for E2H == 0 |
36 | hw/arm/armv7m: Honour CPU's address space for image loads | 30 | target/arm: use FIELD macro for CNTHCTL bit definitions |
37 | target/arm: Define an IDAU interface | 31 | target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written |
38 | armv7m: Forward idau property to CPU object | 32 | target/arm: Implement new FEAT_ECV trap bits |
39 | target/arm: Define init-svtor property for the reset secure VTOR value | 33 | target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 |
40 | armv7m: Forward init-svtor property to CPU object | 34 | target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling |
41 | target/arm: Add Cortex-M33 | 35 | target/arm: Enable FEAT_ECV for 'max' CPU |
42 | hw/misc/unimp: Move struct to header file | 36 | hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later |
43 | include/hw/or-irq.h: Add missing include guard | ||
44 | qdev: Add new qdev_init_gpio_in_named_with_opaque() | ||
45 | hw/core/split-irq: Device that splits IRQ lines | ||
46 | hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505 | ||
47 | hw/misc/tz-ppc: Model TrustZone peripheral protection controller | ||
48 | hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton | ||
49 | hw/misc/iotkit-secctl: Add handling for PPCs | ||
50 | hw/misc/iotkit-secctl: Add remaining simple registers | ||
51 | hw/arm/iotkit: Model Arm IOT Kit | ||
52 | mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image | ||
53 | 37 | ||
54 | Richard Henderson (17): | 38 | Richard Henderson (1): |
55 | decodetree: Propagate return value from translate subroutines | 39 | target/arm: Fix 32-bit SMOPA |
56 | target/arm: Add ARM_FEATURE_V8_RDM | ||
57 | target/arm: Refactor disas_simd_indexed decode | ||
58 | target/arm: Refactor disas_simd_indexed size checks | ||
59 | target/arm: Decode aa64 armv8.1 scalar three same extra | ||
60 | target/arm: Decode aa64 armv8.1 three same extra | ||
61 | target/arm: Decode aa64 armv8.1 scalar/vector x indexed element | ||
62 | target/arm: Decode aa32 armv8.1 three same | ||
63 | target/arm: Decode aa32 armv8.1 two reg and a scalar | ||
64 | target/arm: Enable ARM_FEATURE_V8_RDM | ||
65 | target/arm: Add ARM_FEATURE_V8_FCMA | ||
66 | target/arm: Decode aa64 armv8.3 fcadd | ||
67 | target/arm: Decode aa64 armv8.3 fcmla | ||
68 | target/arm: Decode aa32 armv8.3 3-same | ||
69 | target/arm: Decode aa32 armv8.3 2-reg-index | ||
70 | target/arm: Decode t32 simd 3reg and 2reg_scalar extension | ||
71 | target/arm: Enable ARM_FEATURE_V8_FCMA | ||
72 | 40 | ||
73 | hw/arm/Makefile.objs | 2 + | 41 | Thomas Huth (1): |
74 | hw/core/Makefile.objs | 1 + | 42 | target/arm: Move v7m-related code from cpu32.c into a separate file |
75 | hw/misc/Makefile.objs | 4 + | ||
76 | hw/timer/Makefile.objs | 1 + | ||
77 | target/arm/Makefile.objs | 2 +- | ||
78 | include/hw/arm/armv7m.h | 5 + | ||
79 | include/hw/arm/iotkit.h | 109 ++++++ | ||
80 | include/hw/arm/xlnx-zynqmp.h | 2 + | ||
81 | include/hw/core/split-irq.h | 57 +++ | ||
82 | include/hw/irq.h | 4 +- | ||
83 | include/hw/loader.h | 12 +- | ||
84 | include/hw/misc/iotkit-secctl.h | 103 ++++++ | ||
85 | include/hw/misc/mps2-fpgaio.h | 43 +++ | ||
86 | include/hw/misc/tz-ppc.h | 101 ++++++ | ||
87 | include/hw/misc/unimp.h | 10 + | ||
88 | include/hw/or-irq.h | 5 + | ||
89 | include/hw/qdev-core.h | 30 +- | ||
90 | include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++ | ||
91 | target/arm/cpu.h | 8 + | ||
92 | target/arm/helper.h | 31 ++ | ||
93 | target/arm/idau.h | 61 ++++ | ||
94 | hw/arm/armv7m.c | 35 +- | ||
95 | hw/arm/boot.c | 119 ++++--- | ||
96 | hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++ | ||
97 | hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++ | ||
98 | hw/arm/xlnx-zynqmp.c | 14 + | ||
99 | hw/core/loader.c | 8 +- | ||
100 | hw/core/qdev.c | 8 +- | ||
101 | hw/core/split-irq.c | 89 +++++ | ||
102 | hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++ | ||
103 | hw/misc/mps2-fpgaio.c | 176 ++++++++++ | ||
104 | hw/misc/tz-ppc.c | 302 ++++++++++++++++ | ||
105 | hw/misc/unimp.c | 10 - | ||
106 | hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++ | ||
107 | linux-user/elfload.c | 2 + | ||
108 | target/arm/cpu.c | 66 +++- | ||
109 | target/arm/cpu64.c | 2 + | ||
110 | target/arm/helper.c | 28 +- | ||
111 | target/arm/translate-a64.c | 514 +++++++++++++++++++++------ | ||
112 | target/arm/translate.c | 275 +++++++++++++-- | ||
113 | target/arm/vec_helper.c | 429 ++++++++++++++++++++++ | ||
114 | default-configs/arm-softmmu.mak | 5 + | ||
115 | hw/misc/trace-events | 24 ++ | ||
116 | hw/timer/trace-events | 3 + | ||
117 | scripts/decodetree.py | 5 +- | ||
118 | 45 files changed, 4668 insertions(+), 200 deletions(-) | ||
119 | create mode 100644 include/hw/arm/iotkit.h | ||
120 | create mode 100644 include/hw/core/split-irq.h | ||
121 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
122 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
123 | create mode 100644 include/hw/misc/tz-ppc.h | ||
124 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
125 | create mode 100644 target/arm/idau.h | ||
126 | create mode 100644 hw/arm/iotkit.c | ||
127 | create mode 100644 hw/arm/mps2-tz.c | ||
128 | create mode 100644 hw/core/split-irq.c | ||
129 | create mode 100644 hw/misc/iotkit-secctl.c | ||
130 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
131 | create mode 100644 hw/misc/tz-ppc.c | ||
132 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
133 | create mode 100644 target/arm/vec_helper.c | ||
134 | 43 | ||
44 | MAINTAINERS | 1 + | ||
45 | docs/system/arm/b-l475e-iot01a.rst | 2 +- | ||
46 | docs/system/arm/emulation.rst | 1 + | ||
47 | include/hw/arm/stm32l4x5_soc.h | 2 + | ||
48 | include/hw/gpio/stm32l4x5_gpio.h | 71 +++++ | ||
49 | include/hw/misc/stm32l4x5_syscfg.h | 3 +- | ||
50 | include/hw/rtc/sun4v-rtc.h | 2 +- | ||
51 | target/arm/cpu-features.h | 10 + | ||
52 | target/arm/cpu.h | 129 +-------- | ||
53 | target/arm/internals.h | 151 ++++++++++ | ||
54 | hw/arm/stm32l4x5_soc.c | 71 ++++- | ||
55 | hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++ | ||
56 | hw/misc/stm32l4x5_syscfg.c | 1 + | ||
57 | hw/rtc/sun4v-rtc.c | 2 +- | ||
58 | target/arm/helper.c | 189 ++++++++++++- | ||
59 | target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++ | ||
60 | target/arm/tcg/cpu32.c | 261 ------------------ | ||
61 | target/arm/tcg/cpu64.c | 1 + | ||
62 | target/arm/tcg/sme_helper.c | 77 +++--- | ||
63 | tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++ | ||
64 | tests/tcg/aarch64/sme-smopa-1.c | 47 ++++ | ||
65 | tests/tcg/aarch64/sme-smopa-2.c | 54 ++++ | ||
66 | hw/arm/Kconfig | 3 +- | ||
67 | hw/gpio/Kconfig | 3 + | ||
68 | hw/gpio/meson.build | 1 + | ||
69 | hw/gpio/trace-events | 6 + | ||
70 | target/arm/meson.build | 3 + | ||
71 | target/arm/tcg/meson.build | 3 + | ||
72 | target/arm/trace-events | 1 + | ||
73 | tests/qtest/meson.build | 3 +- | ||
74 | tests/tcg/aarch64/Makefile.target | 2 +- | ||
75 | 31 files changed, 1962 insertions(+), 456 deletions(-) | ||
76 | create mode 100644 include/hw/gpio/stm32l4x5_gpio.h | ||
77 | create mode 100644 hw/gpio/stm32l4x5_gpio.c | ||
78 | create mode 100644 target/arm/tcg/cpu-v7m.c | ||
79 | create mode 100644 tests/qtest/stm32l4x5_gpio-test.c | ||
80 | create mode 100644 tests/tcg/aarch64/sme-smopa-1.c | ||
81 | create mode 100644 tests/tcg/aarch64/sme-smopa-2.c | ||
82 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Initial commit of the ZynqMP RTC device. | ||
4 | |||
5 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/timer/Makefile.objs | 1 + | ||
10 | include/hw/timer/xlnx-zynqmp-rtc.h | 84 +++++++++++++++ | ||
11 | hw/timer/xlnx-zynqmp-rtc.c | 214 +++++++++++++++++++++++++++++++++++++ | ||
12 | 3 files changed, 299 insertions(+) | ||
13 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
14 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
15 | |||
16 | diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/timer/Makefile.objs | ||
19 | +++ b/hw/timer/Makefile.objs | ||
20 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx_epit.o | ||
21 | common-obj-$(CONFIG_IMX) += imx_gpt.o | ||
22 | common-obj-$(CONFIG_LM32) += lm32_timer.o | ||
23 | common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o | ||
24 | +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o | ||
25 | |||
26 | obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o | ||
27 | obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o | ||
28 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Xilinx Inc. | ||
38 | + * | ||
39 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
40 | + * | ||
41 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
42 | + * of this software and associated documentation files (the "Software"), to deal | ||
43 | + * in the Software without restriction, including without limitation the rights | ||
44 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
45 | + * copies of the Software, and to permit persons to whom the Software is | ||
46 | + * furnished to do so, subject to the following conditions: | ||
47 | + * | ||
48 | + * The above copyright notice and this permission notice shall be included in | ||
49 | + * all copies or substantial portions of the Software. | ||
50 | + * | ||
51 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
52 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
53 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
54 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
55 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
56 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
57 | + * THE SOFTWARE. | ||
58 | + */ | ||
59 | + | ||
60 | +#include "hw/register.h" | ||
61 | + | ||
62 | +#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc" | ||
63 | + | ||
64 | +#define XLNX_ZYNQMP_RTC(obj) \ | ||
65 | + OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC) | ||
66 | + | ||
67 | +REG32(SET_TIME_WRITE, 0x0) | ||
68 | +REG32(SET_TIME_READ, 0x4) | ||
69 | +REG32(CALIB_WRITE, 0x8) | ||
70 | + FIELD(CALIB_WRITE, FRACTION_EN, 20, 1) | ||
71 | + FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4) | ||
72 | + FIELD(CALIB_WRITE, MAX_TICK, 0, 16) | ||
73 | +REG32(CALIB_READ, 0xc) | ||
74 | + FIELD(CALIB_READ, FRACTION_EN, 20, 1) | ||
75 | + FIELD(CALIB_READ, FRACTION_DATA, 16, 4) | ||
76 | + FIELD(CALIB_READ, MAX_TICK, 0, 16) | ||
77 | +REG32(CURRENT_TIME, 0x10) | ||
78 | +REG32(CURRENT_TICK, 0x14) | ||
79 | + FIELD(CURRENT_TICK, VALUE, 0, 16) | ||
80 | +REG32(ALARM, 0x18) | ||
81 | +REG32(RTC_INT_STATUS, 0x20) | ||
82 | + FIELD(RTC_INT_STATUS, ALARM, 1, 1) | ||
83 | + FIELD(RTC_INT_STATUS, SECONDS, 0, 1) | ||
84 | +REG32(RTC_INT_MASK, 0x24) | ||
85 | + FIELD(RTC_INT_MASK, ALARM, 1, 1) | ||
86 | + FIELD(RTC_INT_MASK, SECONDS, 0, 1) | ||
87 | +REG32(RTC_INT_EN, 0x28) | ||
88 | + FIELD(RTC_INT_EN, ALARM, 1, 1) | ||
89 | + FIELD(RTC_INT_EN, SECONDS, 0, 1) | ||
90 | +REG32(RTC_INT_DIS, 0x2c) | ||
91 | + FIELD(RTC_INT_DIS, ALARM, 1, 1) | ||
92 | + FIELD(RTC_INT_DIS, SECONDS, 0, 1) | ||
93 | +REG32(ADDR_ERROR, 0x30) | ||
94 | + FIELD(ADDR_ERROR, STATUS, 0, 1) | ||
95 | +REG32(ADDR_ERROR_INT_MASK, 0x34) | ||
96 | + FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1) | ||
97 | +REG32(ADDR_ERROR_INT_EN, 0x38) | ||
98 | + FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1) | ||
99 | +REG32(ADDR_ERROR_INT_DIS, 0x3c) | ||
100 | + FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1) | ||
101 | +REG32(CONTROL, 0x40) | ||
102 | + FIELD(CONTROL, BATTERY_DISABLE, 31, 1) | ||
103 | + FIELD(CONTROL, OSC_CNTRL, 24, 4) | ||
104 | + FIELD(CONTROL, SLVERR_ENABLE, 0, 1) | ||
105 | +REG32(SAFETY_CHK, 0x50) | ||
106 | + | ||
107 | +#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1) | ||
108 | + | ||
109 | +typedef struct XlnxZynqMPRTC { | ||
110 | + SysBusDevice parent_obj; | ||
111 | + MemoryRegion iomem; | ||
112 | + qemu_irq irq_rtc_int; | ||
113 | + qemu_irq irq_addr_error_int; | ||
114 | + | ||
115 | + uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
116 | + RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
117 | +} XlnxZynqMPRTC; | ||
118 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
119 | new file mode 100644 | ||
120 | index XXXXXXX..XXXXXXX | ||
121 | --- /dev/null | ||
122 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | ||
123 | @@ -XXX,XX +XXX,XX @@ | ||
124 | +/* | ||
125 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
126 | + * | ||
127 | + * Copyright (c) 2017 Xilinx Inc. | ||
128 | + * | ||
129 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
130 | + * | ||
131 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
132 | + * of this software and associated documentation files (the "Software"), to deal | ||
133 | + * in the Software without restriction, including without limitation the rights | ||
134 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
135 | + * copies of the Software, and to permit persons to whom the Software is | ||
136 | + * furnished to do so, subject to the following conditions: | ||
137 | + * | ||
138 | + * The above copyright notice and this permission notice shall be included in | ||
139 | + * all copies or substantial portions of the Software. | ||
140 | + * | ||
141 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
142 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
143 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
144 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
145 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
146 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
147 | + * THE SOFTWARE. | ||
148 | + */ | ||
149 | + | ||
150 | +#include "qemu/osdep.h" | ||
151 | +#include "hw/sysbus.h" | ||
152 | +#include "hw/register.h" | ||
153 | +#include "qemu/bitops.h" | ||
154 | +#include "qemu/log.h" | ||
155 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
156 | + | ||
157 | +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
158 | +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0 | ||
159 | +#endif | ||
160 | + | ||
161 | +static void rtc_int_update_irq(XlnxZynqMPRTC *s) | ||
162 | +{ | ||
163 | + bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; | ||
164 | + qemu_set_irq(s->irq_rtc_int, pending); | ||
165 | +} | ||
166 | + | ||
167 | +static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
168 | +{ | ||
169 | + bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; | ||
170 | + qemu_set_irq(s->irq_addr_error_int, pending); | ||
171 | +} | ||
172 | + | ||
173 | +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
174 | +{ | ||
175 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
176 | + rtc_int_update_irq(s); | ||
177 | +} | ||
178 | + | ||
179 | +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
180 | +{ | ||
181 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
182 | + | ||
183 | + s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64; | ||
184 | + rtc_int_update_irq(s); | ||
185 | + return 0; | ||
186 | +} | ||
187 | + | ||
188 | +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
189 | +{ | ||
190 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
191 | + | ||
192 | + s->regs[R_RTC_INT_MASK] |= (uint32_t) val64; | ||
193 | + rtc_int_update_irq(s); | ||
194 | + return 0; | ||
195 | +} | ||
196 | + | ||
197 | +static void addr_error_postw(RegisterInfo *reg, uint64_t val64) | ||
198 | +{ | ||
199 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
200 | + addr_error_int_update_irq(s); | ||
201 | +} | ||
202 | + | ||
203 | +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
204 | +{ | ||
205 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
206 | + | ||
207 | + s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64; | ||
208 | + addr_error_int_update_irq(s); | ||
209 | + return 0; | ||
210 | +} | ||
211 | + | ||
212 | +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
213 | +{ | ||
214 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
215 | + | ||
216 | + s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64; | ||
217 | + addr_error_int_update_irq(s); | ||
218 | + return 0; | ||
219 | +} | ||
220 | + | ||
221 | +static const RegisterAccessInfo rtc_regs_info[] = { | ||
222 | + { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
223 | + },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
224 | + .ro = 0xffffffff, | ||
225 | + },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
226 | + },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
227 | + .ro = 0x1fffff, | ||
228 | + },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
229 | + .ro = 0xffffffff, | ||
230 | + },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
231 | + .ro = 0xffff, | ||
232 | + },{ .name = "ALARM", .addr = A_ALARM, | ||
233 | + },{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS, | ||
234 | + .w1c = 0x3, | ||
235 | + .post_write = rtc_int_status_postw, | ||
236 | + },{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK, | ||
237 | + .reset = 0x3, | ||
238 | + .ro = 0x3, | ||
239 | + },{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN, | ||
240 | + .pre_write = rtc_int_en_prew, | ||
241 | + },{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS, | ||
242 | + .pre_write = rtc_int_dis_prew, | ||
243 | + },{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR, | ||
244 | + .w1c = 0x1, | ||
245 | + .post_write = addr_error_postw, | ||
246 | + },{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK, | ||
247 | + .reset = 0x1, | ||
248 | + .ro = 0x1, | ||
249 | + },{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN, | ||
250 | + .pre_write = addr_error_int_en_prew, | ||
251 | + },{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS, | ||
252 | + .pre_write = addr_error_int_dis_prew, | ||
253 | + },{ .name = "CONTROL", .addr = A_CONTROL, | ||
254 | + .reset = 0x1000000, | ||
255 | + .rsvd = 0x70fffffe, | ||
256 | + },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK, | ||
257 | + } | ||
258 | +}; | ||
259 | + | ||
260 | +static void rtc_reset(DeviceState *dev) | ||
261 | +{ | ||
262 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev); | ||
263 | + unsigned int i; | ||
264 | + | ||
265 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
266 | + register_reset(&s->regs_info[i]); | ||
267 | + } | ||
268 | + | ||
269 | + rtc_int_update_irq(s); | ||
270 | + addr_error_int_update_irq(s); | ||
271 | +} | ||
272 | + | ||
273 | +static const MemoryRegionOps rtc_ops = { | ||
274 | + .read = register_read_memory, | ||
275 | + .write = register_write_memory, | ||
276 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
277 | + .valid = { | ||
278 | + .min_access_size = 4, | ||
279 | + .max_access_size = 4, | ||
280 | + }, | ||
281 | +}; | ||
282 | + | ||
283 | +static void rtc_init(Object *obj) | ||
284 | +{ | ||
285 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
286 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
287 | + RegisterInfoArray *reg_array; | ||
288 | + | ||
289 | + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
290 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
291 | + reg_array = | ||
292 | + register_init_block32(DEVICE(obj), rtc_regs_info, | ||
293 | + ARRAY_SIZE(rtc_regs_info), | ||
294 | + s->regs_info, s->regs, | ||
295 | + &rtc_ops, | ||
296 | + XLNX_ZYNQMP_RTC_ERR_DEBUG, | ||
297 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
298 | + memory_region_add_subregion(&s->iomem, | ||
299 | + 0x0, | ||
300 | + ®_array->mem); | ||
301 | + sysbus_init_mmio(sbd, &s->iomem); | ||
302 | + sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
303 | + sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
304 | +} | ||
305 | + | ||
306 | +static const VMStateDescription vmstate_rtc = { | ||
307 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
308 | + .version_id = 1, | ||
309 | + .minimum_version_id = 1, | ||
310 | + .fields = (VMStateField[]) { | ||
311 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
312 | + VMSTATE_END_OF_LIST(), | ||
313 | + } | ||
314 | +}; | ||
315 | + | ||
316 | +static void rtc_class_init(ObjectClass *klass, void *data) | ||
317 | +{ | ||
318 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
319 | + | ||
320 | + dc->reset = rtc_reset; | ||
321 | + dc->vmsd = &vmstate_rtc; | ||
322 | +} | ||
323 | + | ||
324 | +static const TypeInfo rtc_info = { | ||
325 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
326 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
327 | + .instance_size = sizeof(XlnxZynqMPRTC), | ||
328 | + .class_init = rtc_class_init, | ||
329 | + .instance_init = rtc_init, | ||
330 | +}; | ||
331 | + | ||
332 | +static void rtc_register_types(void) | ||
333 | +{ | ||
334 | + type_register_static(&rtc_info); | ||
335 | +} | ||
336 | + | ||
337 | +type_init(rtc_register_types) | ||
338 | -- | ||
339 | 2.16.2 | ||
340 | |||
341 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Allow the guest to determine the time set from the QEMU command line. | ||
4 | |||
5 | This includes adding a trace event to debug the new time. | ||
6 | |||
7 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/timer/xlnx-zynqmp-rtc.h | 2 ++ | ||
13 | hw/timer/xlnx-zynqmp-rtc.c | 58 ++++++++++++++++++++++++++++++++++++++ | ||
14 | hw/timer/trace-events | 3 ++ | ||
15 | 3 files changed, 63 insertions(+) | ||
16 | |||
17 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/timer/xlnx-zynqmp-rtc.h | ||
20 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPRTC { | ||
22 | qemu_irq irq_rtc_int; | ||
23 | qemu_irq irq_addr_error_int; | ||
24 | |||
25 | + uint32_t tick_offset; | ||
26 | + | ||
27 | uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
28 | RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
29 | } XlnxZynqMPRTC; | ||
30 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/timer/xlnx-zynqmp-rtc.c | ||
33 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #include "hw/register.h" | ||
36 | #include "qemu/bitops.h" | ||
37 | #include "qemu/log.h" | ||
38 | +#include "hw/ptimer.h" | ||
39 | +#include "qemu/cutils.h" | ||
40 | +#include "sysemu/sysemu.h" | ||
41 | +#include "trace.h" | ||
42 | #include "hw/timer/xlnx-zynqmp-rtc.h" | ||
43 | |||
44 | #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
45 | @@ -XXX,XX +XXX,XX @@ static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
46 | qemu_set_irq(s->irq_addr_error_int, pending); | ||
47 | } | ||
48 | |||
49 | +static uint32_t rtc_get_count(XlnxZynqMPRTC *s) | ||
50 | +{ | ||
51 | + int64_t now = qemu_clock_get_ns(rtc_clock); | ||
52 | + return s->tick_offset + now / NANOSECONDS_PER_SECOND; | ||
53 | +} | ||
54 | + | ||
55 | +static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64) | ||
56 | +{ | ||
57 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
58 | + | ||
59 | + return rtc_get_count(s); | ||
60 | +} | ||
61 | + | ||
62 | static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
63 | { | ||
64 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
65 | @@ -XXX,XX +XXX,XX @@ static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
66 | |||
67 | static const RegisterAccessInfo rtc_regs_info[] = { | ||
68 | { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
69 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
70 | },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
71 | .ro = 0xffffffff, | ||
72 | + .post_read = current_time_postr, | ||
73 | },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
74 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
75 | },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
76 | .ro = 0x1fffff, | ||
77 | },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
78 | .ro = 0xffffffff, | ||
79 | + .post_read = current_time_postr, | ||
80 | },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
81 | .ro = 0xffff, | ||
82 | },{ .name = "ALARM", .addr = A_ALARM, | ||
83 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
84 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
85 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
86 | RegisterInfoArray *reg_array; | ||
87 | + struct tm current_tm; | ||
88 | |||
89 | memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
90 | XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
91 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
92 | sysbus_init_mmio(sbd, &s->iomem); | ||
93 | sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
94 | sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
95 | + | ||
96 | + qemu_get_timedate(¤t_tm, 0); | ||
97 | + s->tick_offset = mktimegm(¤t_tm) - | ||
98 | + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
99 | + | ||
100 | + trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon, | ||
101 | + current_tm.tm_mday, current_tm.tm_hour, | ||
102 | + current_tm.tm_min, current_tm.tm_sec); | ||
103 | +} | ||
104 | + | ||
105 | +static int rtc_pre_save(void *opaque) | ||
106 | +{ | ||
107 | + XlnxZynqMPRTC *s = opaque; | ||
108 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
109 | + | ||
110 | + /* Add the time at migration */ | ||
111 | + s->tick_offset = s->tick_offset + now; | ||
112 | + | ||
113 | + return 0; | ||
114 | +} | ||
115 | + | ||
116 | +static int rtc_post_load(void *opaque, int version_id) | ||
117 | +{ | ||
118 | + XlnxZynqMPRTC *s = opaque; | ||
119 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
120 | + | ||
121 | + /* Subtract the time after migration. This combined with the pre_save | ||
122 | + * action results in us having subtracted the time that the guest was | ||
123 | + * stopped to the offset. | ||
124 | + */ | ||
125 | + s->tick_offset = s->tick_offset - now; | ||
126 | + | ||
127 | + return 0; | ||
128 | } | ||
129 | |||
130 | static const VMStateDescription vmstate_rtc = { | ||
131 | .name = TYPE_XLNX_ZYNQMP_RTC, | ||
132 | .version_id = 1, | ||
133 | .minimum_version_id = 1, | ||
134 | + .pre_save = rtc_pre_save, | ||
135 | + .post_load = rtc_post_load, | ||
136 | .fields = (VMStateField[]) { | ||
137 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
138 | + VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC), | ||
139 | VMSTATE_END_OF_LIST(), | ||
140 | } | ||
141 | }; | ||
142 | diff --git a/hw/timer/trace-events b/hw/timer/trace-events | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/hw/timer/trace-events | ||
145 | +++ b/hw/timer/trace-events | ||
146 | @@ -XXX,XX +XXX,XX @@ systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr | ||
147 | cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
148 | cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
149 | cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" | ||
150 | + | ||
151 | +# hw/timer/xlnx-zynqmp-rtc.c | ||
152 | +xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" | ||
153 | -- | ||
154 | 2.16.2 | ||
155 | |||
156 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | ||
9 | hw/arm/xlnx-zynqmp.c | 14 ++++++++++++++ | ||
10 | 2 files changed, 16 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
15 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | #include "hw/dma/xlnx_dpdma.h" | ||
18 | #include "hw/display/xlnx_dp.h" | ||
19 | #include "hw/intc/xlnx-zynqmp-ipi.h" | ||
20 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
21 | |||
22 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | ||
23 | #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState { | ||
25 | XlnxDPState dp; | ||
26 | XlnxDPDMAState dpdma; | ||
27 | XlnxZynqMPIPI ipi; | ||
28 | + XlnxZynqMPRTC rtc; | ||
29 | |||
30 | char *boot_cpu; | ||
31 | ARMCPU *boot_cpu_ptr; | ||
32 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/xlnx-zynqmp.c | ||
35 | +++ b/hw/arm/xlnx-zynqmp.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #define IPI_ADDR 0xFF300000 | ||
38 | #define IPI_IRQ 64 | ||
39 | |||
40 | +#define RTC_ADDR 0xffa60000 | ||
41 | +#define RTC_IRQ 26 | ||
42 | + | ||
43 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | ||
44 | |||
45 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | ||
46 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | ||
47 | |||
48 | object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); | ||
49 | qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); | ||
50 | + | ||
51 | + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); | ||
52 | + qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); | ||
53 | } | ||
54 | |||
55 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
56 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
57 | } | ||
58 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | ||
59 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | ||
60 | + | ||
61 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | ||
62 | + if (err) { | ||
63 | + error_propagate(errp, err); | ||
64 | + return; | ||
65 | + } | ||
66 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | ||
67 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | ||
68 | } | ||
69 | |||
70 | static Property xlnx_zynqmp_props[] = { | ||
71 | -- | ||
72 | 2.16.2 | ||
73 | |||
74 | diff view generated by jsdifflib |
1 | The Cortex-M33 allows the system to specify the reset value of the | 1 | cpu.h has a lot of #defines relating to CPU register fields. |
---|---|---|---|
2 | secure Vector Table Offset Register (VTOR) by asserting config | 2 | Most of these aren't actually used outside target/arm code, |
3 | signals. In particular, guest images for the MPS2 AN505 board rely | 3 | so there's no point in cluttering up the cpu.h file with them. |
4 | on the MPS2's initial VTOR being correct for that board. | 4 | Move some easy ones to internals.h. |
5 | Implement a QEMU property so board and SoC code can set the reset | ||
6 | value to the correct value. | ||
7 | 5 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-7-peter.maydell@linaro.org | 9 | Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org |
11 | --- | 10 | --- |
12 | target/arm/cpu.h | 3 +++ | 11 | target/arm/cpu.h | 128 ----------------------------------------- |
13 | target/arm/cpu.c | 18 ++++++++++++++---- | 12 | target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++ |
14 | 2 files changed, 17 insertions(+), 4 deletions(-) | 13 | 2 files changed, 128 insertions(+), 128 deletions(-) |
15 | 14 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/cpu.h |
19 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/cpu.h |
20 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMGenericTimer { |
21 | */ | 20 | uint64_t ctl; /* Timer Control register */ |
22 | uint32_t psci_conduit; | 21 | } ARMGenericTimer; |
23 | 22 | ||
24 | + /* For v8M, initial value of the Secure VTOR */ | 23 | -#define VTCR_NSW (1u << 29) |
25 | + uint32_t init_svtor; | 24 | -#define VTCR_NSA (1u << 30) |
26 | + | 25 | -#define VSTCR_SW VTCR_NSW |
27 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or | 26 | -#define VSTCR_SA VTCR_NSA |
28 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | 27 | - |
29 | */ | 28 | /* Define a maximum sized vector register. |
30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 29 | * For 32-bit, this is a 128-bit NEON/AdvSIMD register. |
30 | * For 64-bit, this is a 2048-bit SVE register. | ||
31 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
32 | #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ | ||
33 | #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ | ||
34 | |||
35 | -/* Bit definitions for CPACR (AArch32 only) */ | ||
36 | -FIELD(CPACR, CP10, 20, 2) | ||
37 | -FIELD(CPACR, CP11, 22, 2) | ||
38 | -FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ | ||
39 | -FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ | ||
40 | -FIELD(CPACR, ASEDIS, 31, 1) | ||
41 | - | ||
42 | -/* Bit definitions for CPACR_EL1 (AArch64 only) */ | ||
43 | -FIELD(CPACR_EL1, ZEN, 16, 2) | ||
44 | -FIELD(CPACR_EL1, FPEN, 20, 2) | ||
45 | -FIELD(CPACR_EL1, SMEN, 24, 2) | ||
46 | -FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ | ||
47 | - | ||
48 | -/* Bit definitions for HCPTR (AArch32 only) */ | ||
49 | -FIELD(HCPTR, TCP10, 10, 1) | ||
50 | -FIELD(HCPTR, TCP11, 11, 1) | ||
51 | -FIELD(HCPTR, TASE, 15, 1) | ||
52 | -FIELD(HCPTR, TTA, 20, 1) | ||
53 | -FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ | ||
54 | -FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ | ||
55 | - | ||
56 | -/* Bit definitions for CPTR_EL2 (AArch64 only) */ | ||
57 | -FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ | ||
58 | -FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ | ||
59 | -FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ | ||
60 | -FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ | ||
61 | -FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ | ||
62 | -FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ | ||
63 | -FIELD(CPTR_EL2, TTA, 28, 1) | ||
64 | -FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ | ||
65 | -FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ | ||
66 | - | ||
67 | -/* Bit definitions for CPTR_EL3 (AArch64 only) */ | ||
68 | -FIELD(CPTR_EL3, EZ, 8, 1) | ||
69 | -FIELD(CPTR_EL3, TFP, 10, 1) | ||
70 | -FIELD(CPTR_EL3, ESM, 12, 1) | ||
71 | -FIELD(CPTR_EL3, TTA, 20, 1) | ||
72 | -FIELD(CPTR_EL3, TAM, 30, 1) | ||
73 | -FIELD(CPTR_EL3, TCPAC, 31, 1) | ||
74 | - | ||
75 | -#define MDCR_MTPME (1U << 28) | ||
76 | -#define MDCR_TDCC (1U << 27) | ||
77 | -#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ | ||
78 | -#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ | ||
79 | -#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ | ||
80 | -#define MDCR_EPMAD (1U << 21) | ||
81 | -#define MDCR_EDAD (1U << 20) | ||
82 | -#define MDCR_TTRF (1U << 19) | ||
83 | -#define MDCR_STE (1U << 18) /* MDCR_EL3 */ | ||
84 | -#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ | ||
85 | -#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ | ||
86 | -#define MDCR_SDD (1U << 16) | ||
87 | -#define MDCR_SPD (3U << 14) | ||
88 | -#define MDCR_TDRA (1U << 11) | ||
89 | -#define MDCR_TDOSA (1U << 10) | ||
90 | -#define MDCR_TDA (1U << 9) | ||
91 | -#define MDCR_TDE (1U << 8) | ||
92 | -#define MDCR_HPME (1U << 7) | ||
93 | -#define MDCR_TPM (1U << 6) | ||
94 | -#define MDCR_TPMCR (1U << 5) | ||
95 | -#define MDCR_HPMN (0x1fU) | ||
96 | - | ||
97 | -/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ | ||
98 | -#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ | ||
99 | - MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ | ||
100 | - MDCR_STE | MDCR_SPME | MDCR_SPD) | ||
101 | - | ||
102 | #define CPSR_M (0x1fU) | ||
103 | #define CPSR_T (1U << 5) | ||
104 | #define CPSR_F (1U << 6) | ||
105 | @@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1) | ||
106 | #define XPSR_NZCV CPSR_NZCV | ||
107 | #define XPSR_IT CPSR_IT | ||
108 | |||
109 | -#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ | ||
110 | -#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ | ||
111 | -#define TTBCR_PD0 (1U << 4) | ||
112 | -#define TTBCR_PD1 (1U << 5) | ||
113 | -#define TTBCR_EPD0 (1U << 7) | ||
114 | -#define TTBCR_IRGN0 (3U << 8) | ||
115 | -#define TTBCR_ORGN0 (3U << 10) | ||
116 | -#define TTBCR_SH0 (3U << 12) | ||
117 | -#define TTBCR_T1SZ (3U << 16) | ||
118 | -#define TTBCR_A1 (1U << 22) | ||
119 | -#define TTBCR_EPD1 (1U << 23) | ||
120 | -#define TTBCR_IRGN1 (3U << 24) | ||
121 | -#define TTBCR_ORGN1 (3U << 26) | ||
122 | -#define TTBCR_SH1 (1U << 28) | ||
123 | -#define TTBCR_EAE (1U << 31) | ||
124 | - | ||
125 | -FIELD(VTCR, T0SZ, 0, 6) | ||
126 | -FIELD(VTCR, SL0, 6, 2) | ||
127 | -FIELD(VTCR, IRGN0, 8, 2) | ||
128 | -FIELD(VTCR, ORGN0, 10, 2) | ||
129 | -FIELD(VTCR, SH0, 12, 2) | ||
130 | -FIELD(VTCR, TG0, 14, 2) | ||
131 | -FIELD(VTCR, PS, 16, 3) | ||
132 | -FIELD(VTCR, VS, 19, 1) | ||
133 | -FIELD(VTCR, HA, 21, 1) | ||
134 | -FIELD(VTCR, HD, 22, 1) | ||
135 | -FIELD(VTCR, HWU59, 25, 1) | ||
136 | -FIELD(VTCR, HWU60, 26, 1) | ||
137 | -FIELD(VTCR, HWU61, 27, 1) | ||
138 | -FIELD(VTCR, HWU62, 28, 1) | ||
139 | -FIELD(VTCR, NSW, 29, 1) | ||
140 | -FIELD(VTCR, NSA, 30, 1) | ||
141 | -FIELD(VTCR, DS, 32, 1) | ||
142 | -FIELD(VTCR, SL2, 33, 1) | ||
143 | - | ||
144 | /* Bit definitions for ARMv8 SPSR (PSTATE) format. | ||
145 | * Only these are valid when in AArch64 mode; in | ||
146 | * AArch32 mode SPSRs are basically CPSR-format. | ||
147 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | ||
148 | #define HCR_TWEDEN (1ULL << 59) | ||
149 | #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) | ||
150 | |||
151 | -#define HCRX_ENAS0 (1ULL << 0) | ||
152 | -#define HCRX_ENALS (1ULL << 1) | ||
153 | -#define HCRX_ENASR (1ULL << 2) | ||
154 | -#define HCRX_FNXS (1ULL << 3) | ||
155 | -#define HCRX_FGTNXS (1ULL << 4) | ||
156 | -#define HCRX_SMPME (1ULL << 5) | ||
157 | -#define HCRX_TALLINT (1ULL << 6) | ||
158 | -#define HCRX_VINMI (1ULL << 7) | ||
159 | -#define HCRX_VFNMI (1ULL << 8) | ||
160 | -#define HCRX_CMOW (1ULL << 9) | ||
161 | -#define HCRX_MCE2 (1ULL << 10) | ||
162 | -#define HCRX_MSCEN (1ULL << 11) | ||
163 | - | ||
164 | -#define HPFAR_NS (1ULL << 63) | ||
165 | - | ||
166 | #define SCR_NS (1ULL << 0) | ||
167 | #define SCR_IRQ (1ULL << 1) | ||
168 | #define SCR_FIQ (1ULL << 2) | ||
169 | @@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | ||
170 | #define SCR_GPF (1ULL << 48) | ||
171 | #define SCR_NSE (1ULL << 62) | ||
172 | |||
173 | -#define HSTR_TTEE (1 << 16) | ||
174 | -#define HSTR_TJDBX (1 << 17) | ||
175 | - | ||
176 | -#define CNTHCTL_CNTVMASK (1 << 18) | ||
177 | -#define CNTHCTL_CNTPMASK (1 << 19) | ||
178 | - | ||
179 | /* Return the current FPSCR value. */ | ||
180 | uint32_t vfp_get_fpscr(CPUARMState *env); | ||
181 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | ||
182 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | 183 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/cpu.c | 184 | --- a/target/arm/internals.h |
33 | +++ b/target/arm/cpu.c | 185 | +++ b/target/arm/internals.h |
34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 186 | @@ -XXX,XX +XXX,XX @@ FIELD(DBGWCR, WT, 20, 1) |
35 | uint32_t initial_msp; /* Loaded from 0x0 */ | 187 | FIELD(DBGWCR, MASK, 24, 5) |
36 | uint32_t initial_pc; /* Loaded from 0x4 */ | 188 | FIELD(DBGWCR, SSCE, 29, 1) |
37 | uint8_t *rom; | 189 | |
38 | + uint32_t vecbase; | 190 | +#define VTCR_NSW (1u << 29) |
39 | 191 | +#define VTCR_NSA (1u << 30) | |
40 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 192 | +#define VSTCR_SW VTCR_NSW |
41 | env->v7m.secure = true; | 193 | +#define VSTCR_SA VTCR_NSA |
42 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 194 | + |
43 | /* Unlike A/R profile, M profile defines the reset LR value */ | 195 | +/* Bit definitions for CPACR (AArch32 only) */ |
44 | env->regs[14] = 0xffffffff; | 196 | +FIELD(CPACR, CP10, 20, 2) |
45 | 197 | +FIELD(CPACR, CP11, 22, 2) | |
46 | - /* Load the initial SP and PC from the vector table at address 0 */ | 198 | +FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ |
47 | - rom = rom_ptr(0); | 199 | +FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ |
48 | + env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; | 200 | +FIELD(CPACR, ASEDIS, 31, 1) |
49 | + | 201 | + |
50 | + /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | 202 | +/* Bit definitions for CPACR_EL1 (AArch64 only) */ |
51 | + vecbase = env->v7m.vecbase[env->v7m.secure]; | 203 | +FIELD(CPACR_EL1, ZEN, 16, 2) |
52 | + rom = rom_ptr(vecbase); | 204 | +FIELD(CPACR_EL1, FPEN, 20, 2) |
53 | if (rom) { | 205 | +FIELD(CPACR_EL1, SMEN, 24, 2) |
54 | /* Address zero is covered by ROM which hasn't yet been | 206 | +FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ |
55 | * copied into physical memory. | 207 | + |
56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 208 | +/* Bit definitions for HCPTR (AArch32 only) */ |
57 | * it got copied into memory. In the latter case, rom_ptr | 209 | +FIELD(HCPTR, TCP10, 10, 1) |
58 | * will return a NULL pointer and we should use ldl_phys instead. | 210 | +FIELD(HCPTR, TCP11, 11, 1) |
59 | */ | 211 | +FIELD(HCPTR, TASE, 15, 1) |
60 | - initial_msp = ldl_phys(s->as, 0); | 212 | +FIELD(HCPTR, TTA, 20, 1) |
61 | - initial_pc = ldl_phys(s->as, 4); | 213 | +FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ |
62 | + initial_msp = ldl_phys(s->as, vecbase); | 214 | +FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ |
63 | + initial_pc = ldl_phys(s->as, vecbase + 4); | 215 | + |
64 | } | 216 | +/* Bit definitions for CPTR_EL2 (AArch64 only) */ |
65 | 217 | +FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ | |
66 | env->regs[13] = initial_msp & 0xFFFFFFFC; | 218 | +FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ |
67 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property = | 219 | +FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ |
68 | pmsav7_dregion, | 220 | +FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ |
69 | qdev_prop_uint32, uint32_t); | 221 | +FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ |
70 | 222 | +FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ | |
71 | +/* M profile: initial value of the Secure VTOR */ | 223 | +FIELD(CPTR_EL2, TTA, 28, 1) |
72 | +static Property arm_cpu_initsvtor_property = | 224 | +FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ |
73 | + DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | 225 | +FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ |
74 | + | 226 | + |
75 | static void arm_cpu_post_init(Object *obj) | 227 | +/* Bit definitions for CPTR_EL3 (AArch64 only) */ |
76 | { | 228 | +FIELD(CPTR_EL3, EZ, 8, 1) |
77 | ARMCPU *cpu = ARM_CPU(obj); | 229 | +FIELD(CPTR_EL3, TFP, 10, 1) |
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | 230 | +FIELD(CPTR_EL3, ESM, 12, 1) |
79 | qdev_prop_allow_set_link_before_realize, | 231 | +FIELD(CPTR_EL3, TTA, 20, 1) |
80 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | 232 | +FIELD(CPTR_EL3, TAM, 30, 1) |
81 | &error_abort); | 233 | +FIELD(CPTR_EL3, TCPAC, 31, 1) |
82 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, | 234 | + |
83 | + &error_abort); | 235 | +#define MDCR_MTPME (1U << 28) |
84 | } | 236 | +#define MDCR_TDCC (1U << 27) |
85 | 237 | +#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ | |
86 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | 238 | +#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ |
239 | +#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ | ||
240 | +#define MDCR_EPMAD (1U << 21) | ||
241 | +#define MDCR_EDAD (1U << 20) | ||
242 | +#define MDCR_TTRF (1U << 19) | ||
243 | +#define MDCR_STE (1U << 18) /* MDCR_EL3 */ | ||
244 | +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ | ||
245 | +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ | ||
246 | +#define MDCR_SDD (1U << 16) | ||
247 | +#define MDCR_SPD (3U << 14) | ||
248 | +#define MDCR_TDRA (1U << 11) | ||
249 | +#define MDCR_TDOSA (1U << 10) | ||
250 | +#define MDCR_TDA (1U << 9) | ||
251 | +#define MDCR_TDE (1U << 8) | ||
252 | +#define MDCR_HPME (1U << 7) | ||
253 | +#define MDCR_TPM (1U << 6) | ||
254 | +#define MDCR_TPMCR (1U << 5) | ||
255 | +#define MDCR_HPMN (0x1fU) | ||
256 | + | ||
257 | +/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ | ||
258 | +#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ | ||
259 | + MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ | ||
260 | + MDCR_STE | MDCR_SPME | MDCR_SPD) | ||
261 | + | ||
262 | +#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ | ||
263 | +#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ | ||
264 | +#define TTBCR_PD0 (1U << 4) | ||
265 | +#define TTBCR_PD1 (1U << 5) | ||
266 | +#define TTBCR_EPD0 (1U << 7) | ||
267 | +#define TTBCR_IRGN0 (3U << 8) | ||
268 | +#define TTBCR_ORGN0 (3U << 10) | ||
269 | +#define TTBCR_SH0 (3U << 12) | ||
270 | +#define TTBCR_T1SZ (3U << 16) | ||
271 | +#define TTBCR_A1 (1U << 22) | ||
272 | +#define TTBCR_EPD1 (1U << 23) | ||
273 | +#define TTBCR_IRGN1 (3U << 24) | ||
274 | +#define TTBCR_ORGN1 (3U << 26) | ||
275 | +#define TTBCR_SH1 (1U << 28) | ||
276 | +#define TTBCR_EAE (1U << 31) | ||
277 | + | ||
278 | +FIELD(VTCR, T0SZ, 0, 6) | ||
279 | +FIELD(VTCR, SL0, 6, 2) | ||
280 | +FIELD(VTCR, IRGN0, 8, 2) | ||
281 | +FIELD(VTCR, ORGN0, 10, 2) | ||
282 | +FIELD(VTCR, SH0, 12, 2) | ||
283 | +FIELD(VTCR, TG0, 14, 2) | ||
284 | +FIELD(VTCR, PS, 16, 3) | ||
285 | +FIELD(VTCR, VS, 19, 1) | ||
286 | +FIELD(VTCR, HA, 21, 1) | ||
287 | +FIELD(VTCR, HD, 22, 1) | ||
288 | +FIELD(VTCR, HWU59, 25, 1) | ||
289 | +FIELD(VTCR, HWU60, 26, 1) | ||
290 | +FIELD(VTCR, HWU61, 27, 1) | ||
291 | +FIELD(VTCR, HWU62, 28, 1) | ||
292 | +FIELD(VTCR, NSW, 29, 1) | ||
293 | +FIELD(VTCR, NSA, 30, 1) | ||
294 | +FIELD(VTCR, DS, 32, 1) | ||
295 | +FIELD(VTCR, SL2, 33, 1) | ||
296 | + | ||
297 | +#define HCRX_ENAS0 (1ULL << 0) | ||
298 | +#define HCRX_ENALS (1ULL << 1) | ||
299 | +#define HCRX_ENASR (1ULL << 2) | ||
300 | +#define HCRX_FNXS (1ULL << 3) | ||
301 | +#define HCRX_FGTNXS (1ULL << 4) | ||
302 | +#define HCRX_SMPME (1ULL << 5) | ||
303 | +#define HCRX_TALLINT (1ULL << 6) | ||
304 | +#define HCRX_VINMI (1ULL << 7) | ||
305 | +#define HCRX_VFNMI (1ULL << 8) | ||
306 | +#define HCRX_CMOW (1ULL << 9) | ||
307 | +#define HCRX_MCE2 (1ULL << 10) | ||
308 | +#define HCRX_MSCEN (1ULL << 11) | ||
309 | + | ||
310 | +#define HPFAR_NS (1ULL << 63) | ||
311 | + | ||
312 | +#define HSTR_TTEE (1 << 16) | ||
313 | +#define HSTR_TJDBX (1 << 17) | ||
314 | + | ||
315 | +#define CNTHCTL_CNTVMASK (1 << 18) | ||
316 | +#define CNTHCTL_CNTPMASK (1 << 19) | ||
317 | + | ||
318 | /* We use a few fake FSR values for internal purposes in M profile. | ||
319 | * M profile cores don't have A/R format FSRs, but currently our | ||
320 | * get_phys_addr() code assumes A/R profile and reports failures via | ||
87 | -- | 321 | -- |
88 | 2.16.2 | 322 | 2.34.1 |
89 | 323 | ||
90 | 324 | diff view generated by jsdifflib |
1 | Create an "idau" property on the armv7m container object which | 1 | The timer _EL02 registers should UNDEF for invalid accesses from EL2 |
---|---|---|---|
2 | we can forward to the CPU object. Annoyingly, we can't use | 2 | or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were |
3 | object_property_add_alias() because the CPU object we want to | 3 | delivering the exception to EL2 with the wrong syndrome. |
4 | forward to doesn't exist until the armv7m container is realized. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-6-peter.maydell@linaro.org | 7 | Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org |
9 | --- | 8 | --- |
10 | include/hw/arm/armv7m.h | 3 +++ | 9 | target/arm/helper.c | 2 +- |
11 | hw/arm/armv7m.c | 9 +++++++++ | 10 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 2 files changed, 12 insertions(+) | ||
13 | 11 | ||
14 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/armv7m.h | 14 | --- a/target/arm/helper.c |
17 | +++ b/include/hw/arm/armv7m.h | 15 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
19 | 17 | return CP_ACCESS_OK; | |
20 | #include "hw/sysbus.h" | 18 | } |
21 | #include "hw/intc/armv7m_nvic.h" | 19 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { |
22 | +#include "target/arm/idau.h" | 20 | - return CP_ACCESS_TRAP; |
23 | 21 | + return CP_ACCESS_TRAP_UNCATEGORIZED; | |
24 | #define TYPE_BITBAND "ARM,bitband-memory" | 22 | } |
25 | #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | 23 | return CP_ACCESS_OK; |
26 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 24 | } |
27 | * + Property "memory": MemoryRegion defining the physical address space | ||
28 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
29 | * devices will be automatically layered on top of this view.) | ||
30 | + * + Property "idau": IDAU interface (forwarded to CPU object) | ||
31 | */ | ||
32 | typedef struct ARMv7MState { | ||
33 | /*< private >*/ | ||
34 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
35 | char *cpu_type; | ||
36 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
37 | MemoryRegion *board_memory; | ||
38 | + Object *idau; | ||
39 | } ARMv7MState; | ||
40 | |||
41 | #endif | ||
42 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/armv7m.c | ||
45 | +++ b/hw/arm/armv7m.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #include "sysemu/qtest.h" | ||
48 | #include "qemu/error-report.h" | ||
49 | #include "exec/address-spaces.h" | ||
50 | +#include "target/arm/idau.h" | ||
51 | |||
52 | /* Bitbanded IO. Each word corresponds to a single bit. */ | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
55 | |||
56 | object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", | ||
57 | &error_abort); | ||
58 | + if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { | ||
59 | + object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); | ||
60 | + if (err != NULL) { | ||
61 | + error_propagate(errp, err); | ||
62 | + return; | ||
63 | + } | ||
64 | + } | ||
65 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
66 | if (err != NULL) { | ||
67 | error_propagate(errp, err); | ||
68 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
69 | DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), | ||
70 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
71 | MemoryRegion *), | ||
72 | + DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
73 | DEFINE_PROP_END_OF_LIST(), | ||
74 | }; | ||
75 | |||
76 | -- | 25 | -- |
77 | 2.16.2 | 26 | 2.34.1 |
78 | |||
79 | diff view generated by jsdifflib |
1 | In v8M, the Implementation Defined Attribution Unit (IDAU) is | 1 | We prefer the FIELD macro over ad-hoc #defines for register bits; |
---|---|---|---|
2 | a small piece of hardware typically implemented in the SoC | 2 | switch CNTHCTL to that style before we add any more bits. |
3 | which provides board or SoC specific security attribution | ||
4 | information for each address that the CPU performs MPU/SAU | ||
5 | checks on. For QEMU, we model this with a QOM interface which | ||
6 | is implemented by the board or SoC object and connected to | ||
7 | the CPU using a link property. | ||
8 | |||
9 | This commit defines the new interface class, adds the link | ||
10 | property to the CPU object, and makes the SAU checking | ||
11 | code call the IDAU interface if one is present. | ||
12 | 3 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20180220180325.29818-5-peter.maydell@linaro.org | 7 | Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org |
16 | --- | 8 | --- |
17 | target/arm/cpu.h | 3 +++ | 9 | target/arm/internals.h | 27 +++++++++++++++++++++++++-- |
18 | target/arm/idau.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/helper.c | 9 ++++----- |
19 | target/arm/cpu.c | 15 +++++++++++++ | 11 | 2 files changed, 29 insertions(+), 7 deletions(-) |
20 | target/arm/helper.c | 28 +++++++++++++++++++++--- | ||
21 | 4 files changed, 104 insertions(+), 3 deletions(-) | ||
22 | create mode 100644 target/arm/idau.h | ||
23 | 12 | ||
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
25 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/internals.h |
27 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/internals.h |
28 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 17 | @@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1) |
29 | /* MemoryRegion to use for secure physical accesses */ | 18 | #define HSTR_TTEE (1 << 16) |
30 | MemoryRegion *secure_memory; | 19 | #define HSTR_TJDBX (1 << 17) |
31 | 20 | ||
32 | + /* For v8M, pointer to the IDAU interface provided by board/SoC */ | 21 | -#define CNTHCTL_CNTVMASK (1 << 18) |
33 | + Object *idau; | 22 | -#define CNTHCTL_CNTPMASK (1 << 19) |
34 | + | ||
35 | /* 'compatible' string for this CPU for Linux device trees */ | ||
36 | const char *dtb_compatible; | ||
37 | |||
38 | diff --git a/target/arm/idau.h b/target/arm/idau.h | ||
39 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | ||
41 | --- /dev/null | ||
42 | +++ b/target/arm/idau.h | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +/* | 23 | +/* |
45 | + * QEMU ARM CPU -- interface for the Arm v8M IDAU | 24 | + * Depending on the value of HCR_EL2.E2H, bits 0 and 1 |
46 | + * | 25 | + * have different bit definitions, and EL1PCTEN might be |
47 | + * Copyright (c) 2018 Linaro Ltd | 26 | + * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to |
48 | + * | 27 | + * disambiguate if necessary. |
49 | + * This program is free software; you can redistribute it and/or | ||
50 | + * modify it under the terms of the GNU General Public License | ||
51 | + * as published by the Free Software Foundation; either version 2 | ||
52 | + * of the License, or (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program; if not, see | ||
61 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
62 | + * | ||
63 | + * In the v8M architecture, the IDAU is a small piece of hardware | ||
64 | + * typically implemented in the SoC which provides board or SoC | ||
65 | + * specific security attribution information for each address that | ||
66 | + * the CPU performs MPU/SAU checks on. For QEMU, we model this with a | ||
67 | + * QOM interface which is implemented by the board or SoC object and | ||
68 | + * connected to the CPU using a link property. | ||
69 | + */ | 28 | + */ |
70 | + | 29 | +FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) |
71 | +#ifndef TARGET_ARM_IDAU_H | 30 | +FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) |
72 | +#define TARGET_ARM_IDAU_H | 31 | +FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) |
73 | + | 32 | +FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) |
74 | +#include "qom/object.h" | 33 | +FIELD(CNTHCTL, EVNTEN, 2, 1) |
75 | + | 34 | +FIELD(CNTHCTL, EVNTDIR, 3, 1) |
76 | +#define TYPE_IDAU_INTERFACE "idau-interface" | 35 | +FIELD(CNTHCTL, EVNTI, 4, 4) |
77 | +#define IDAU_INTERFACE(obj) \ | 36 | +FIELD(CNTHCTL, EL0VTEN, 8, 1) |
78 | + INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE) | 37 | +FIELD(CNTHCTL, EL0PTEN, 9, 1) |
79 | +#define IDAU_INTERFACE_CLASS(class) \ | 38 | +FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) |
80 | + OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE) | 39 | +FIELD(CNTHCTL, EL1PTEN, 11, 1) |
81 | +#define IDAU_INTERFACE_GET_CLASS(obj) \ | 40 | +FIELD(CNTHCTL, ECV, 12, 1) |
82 | + OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE) | 41 | +FIELD(CNTHCTL, EL1TVT, 13, 1) |
83 | + | 42 | +FIELD(CNTHCTL, EL1TVCT, 14, 1) |
84 | +typedef struct IDAUInterface { | 43 | +FIELD(CNTHCTL, EL1NVPCT, 15, 1) |
85 | + Object parent; | 44 | +FIELD(CNTHCTL, EL1NVVCT, 16, 1) |
86 | +} IDAUInterface; | 45 | +FIELD(CNTHCTL, EVNTIS, 17, 1) |
87 | + | 46 | +FIELD(CNTHCTL, CNTVMASK, 18, 1) |
88 | +#define IREGION_NOTVALID -1 | 47 | +FIELD(CNTHCTL, CNTPMASK, 19, 1) |
89 | + | 48 | |
90 | +typedef struct IDAUInterfaceClass { | 49 | /* We use a few fake FSR values for internal purposes in M profile. |
91 | + InterfaceClass parent; | 50 | * M profile cores don't have A/R format FSRs, but currently our |
92 | + | ||
93 | + /* Check the specified address and return the IDAU security information | ||
94 | + * for it by filling in iregion, exempt, ns and nsc: | ||
95 | + * iregion: IDAU region number, or IREGION_NOTVALID if not valid | ||
96 | + * exempt: true if address is exempt from security attribution | ||
97 | + * ns: true if the address is NonSecure | ||
98 | + * nsc: true if the address is NonSecure-callable | ||
99 | + */ | ||
100 | + void (*check)(IDAUInterface *ii, uint32_t address, int *iregion, | ||
101 | + bool *exempt, bool *ns, bool *nsc); | ||
102 | +} IDAUInterfaceClass; | ||
103 | + | ||
104 | +#endif | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/cpu.c | ||
108 | +++ b/target/arm/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ | ||
110 | */ | ||
111 | |||
112 | #include "qemu/osdep.h" | ||
113 | +#include "target/arm/idau.h" | ||
114 | #include "qemu/error-report.h" | ||
115 | #include "qapi/error.h" | ||
116 | #include "cpu.h" | ||
117 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | ||
118 | } | ||
119 | } | ||
120 | |||
121 | + if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { | ||
122 | + object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | ||
123 | + qdev_prop_allow_set_link_before_realize, | ||
124 | + OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
125 | + &error_abort); | ||
126 | + } | ||
127 | + | ||
128 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
129 | &error_abort); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { | ||
132 | .class_init = arm_cpu_class_init, | ||
133 | }; | ||
134 | |||
135 | +static const TypeInfo idau_interface_type_info = { | ||
136 | + .name = TYPE_IDAU_INTERFACE, | ||
137 | + .parent = TYPE_INTERFACE, | ||
138 | + .class_size = sizeof(IDAUInterfaceClass), | ||
139 | +}; | ||
140 | + | ||
141 | static void arm_cpu_register_types(void) | ||
142 | { | ||
143 | const ARMCPUInfo *info = arm_cpus; | ||
144 | |||
145 | type_register_static(&arm_cpu_type_info); | ||
146 | + type_register_static(&idau_interface_type_info); | ||
147 | |||
148 | while (info->name) { | ||
149 | cpu_register(info); | ||
150 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 51 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
151 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
152 | --- a/target/arm/helper.c | 53 | --- a/target/arm/helper.c |
153 | +++ b/target/arm/helper.c | 54 | +++ b/target/arm/helper.c |
154 | @@ -XXX,XX +XXX,XX @@ | 55 | @@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx) |
155 | #include "qemu/osdep.h" | 56 | * It is RES0 in Secure and NonSecure state. |
156 | +#include "target/arm/idau.h" | ||
157 | #include "trace.h" | ||
158 | #include "cpu.h" | ||
159 | #include "internals.h" | ||
160 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | ||
161 | */ | 57 | */ |
162 | ARMCPU *cpu = arm_env_get_cpu(env); | 58 | if ((ss == ARMSS_Root || ss == ARMSS_Realm) && |
163 | int r; | 59 | - ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || |
164 | + bool idau_exempt = false, idau_ns = true, idau_nsc = true; | 60 | - (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { |
165 | + int idau_region = IREGION_NOTVALID; | 61 | + ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) || |
166 | 62 | + (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) { | |
167 | - /* TODO: implement IDAU */ | 63 | irqstate = 0; |
168 | + if (cpu->idau) { | ||
169 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | ||
170 | + IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | ||
171 | + | ||
172 | + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | ||
173 | + &idau_nsc); | ||
174 | + } | ||
175 | |||
176 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | ||
177 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | ||
178 | return; | ||
179 | } | 64 | } |
180 | 65 | ||
181 | - if (v8m_is_sau_exempt(env, address, access_type)) { | 66 | @@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
182 | + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { | 67 | { |
183 | sattrs->ns = !regime_is_secure(env, mmu_idx); | 68 | ARMCPU *cpu = env_archcpu(env); |
184 | return; | 69 | uint32_t oldval = env->cp15.cnthctl_el2; |
185 | } | 70 | - |
186 | 71 | raw_write(env, ri, value); | |
187 | + if (idau_region != IREGION_NOTVALID) { | 72 | |
188 | + sattrs->irvalid = true; | 73 | - if ((oldval ^ value) & CNTHCTL_CNTVMASK) { |
189 | + sattrs->iregion = idau_region; | 74 | + if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { |
190 | + } | 75 | gt_update_irq(cpu, GTIMER_VIRT); |
191 | + | 76 | - } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { |
192 | switch (env->sau.ctrl & 3) { | 77 | + } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { |
193 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | 78 | gt_update_irq(cpu, GTIMER_PHYS); |
194 | break; | ||
195 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | ||
196 | } | ||
197 | } | ||
198 | |||
199 | - /* TODO when we support the IDAU then it may override the result here */ | ||
200 | + /* The IDAU will override the SAU lookup results if it specifies | ||
201 | + * higher security than the SAU does. | ||
202 | + */ | ||
203 | + if (!idau_ns) { | ||
204 | + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | ||
205 | + sattrs->ns = false; | ||
206 | + sattrs->nsc = idau_nsc; | ||
207 | + } | ||
208 | + } | ||
209 | break; | ||
210 | } | 79 | } |
211 | } | 80 | } |
212 | -- | 81 | -- |
213 | 2.16.2 | 82 | 2.34.1 |
214 | 83 | ||
215 | 84 | diff view generated by jsdifflib |
1 | Add a model of the TrustZone peripheral protection controller (PPC), | 1 | Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. |
---|---|---|---|
2 | which is used to gate transactions to non-TZ-aware peripherals so | 2 | This is not strictly architecturally required, but it is how we've |
3 | that secure software can configure them to not be accessible to | 3 | tended to implement registers more recently. |
4 | non-secure software. | 4 | |
5 | In particular, bits [19:18] are only present with FEAT_RME, | ||
6 | and bits [17:12] will only be present with FEAT_ECV. | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-15-peter.maydell@linaro.org | 10 | Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org |
9 | --- | 11 | --- |
10 | hw/misc/Makefile.objs | 2 + | 12 | target/arm/helper.c | 18 ++++++++++++++++++ |
11 | include/hw/misc/tz-ppc.h | 101 ++++++++++++++ | 13 | 1 file changed, 18 insertions(+) |
12 | hw/misc/tz-ppc.c | 302 ++++++++++++++++++++++++++++++++++++++++ | ||
13 | default-configs/arm-softmmu.mak | 2 + | ||
14 | hw/misc/trace-events | 11 ++ | ||
15 | 5 files changed, 418 insertions(+) | ||
16 | create mode 100644 include/hw/misc/tz-ppc.h | ||
17 | create mode 100644 hw/misc/tz-ppc.c | ||
18 | 14 | ||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/Makefile.objs | 17 | --- a/target/arm/helper.c |
22 | +++ b/hw/misc/Makefile.objs | 18 | +++ b/target/arm/helper.c |
23 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 19 | @@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
24 | obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 20 | { |
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 21 | ARMCPU *cpu = env_archcpu(env); |
26 | 22 | uint32_t oldval = env->cp15.cnthctl_el2; | |
27 | +obj-$(CONFIG_TZ_PPC) += tz-ppc.o | 23 | + uint32_t valid_mask = |
24 | + R_CNTHCTL_EL0PCTEN_E2H1_MASK | | ||
25 | + R_CNTHCTL_EL0VCTEN_E2H1_MASK | | ||
26 | + R_CNTHCTL_EVNTEN_MASK | | ||
27 | + R_CNTHCTL_EVNTDIR_MASK | | ||
28 | + R_CNTHCTL_EVNTI_MASK | | ||
29 | + R_CNTHCTL_EL0VTEN_MASK | | ||
30 | + R_CNTHCTL_EL0PTEN_MASK | | ||
31 | + R_CNTHCTL_EL1PCTEN_E2H1_MASK | | ||
32 | + R_CNTHCTL_EL1PTEN_MASK; | ||
28 | + | 33 | + |
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 34 | + if (cpu_isar_feature(aa64_rme, cpu)) { |
30 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | 35 | + valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; |
31 | obj-$(CONFIG_AUX) += auxbus.o | ||
32 | diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h | ||
33 | new file mode 100644 | ||
34 | index XXXXXXX..XXXXXXX | ||
35 | --- /dev/null | ||
36 | +++ b/include/hw/misc/tz-ppc.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | +/* | ||
39 | + * ARM TrustZone peripheral protection controller emulation | ||
40 | + * | ||
41 | + * Copyright (c) 2018 Linaro Limited | ||
42 | + * Written by Peter Maydell | ||
43 | + * | ||
44 | + * This program is free software; you can redistribute it and/or modify | ||
45 | + * it under the terms of the GNU General Public License version 2 or | ||
46 | + * (at your option) any later version. | ||
47 | + */ | ||
48 | + | ||
49 | +/* This is a model of the TrustZone peripheral protection controller (PPC). | ||
50 | + * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM | ||
51 | + * (DDI 0571G): | ||
52 | + * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g | ||
53 | + * | ||
54 | + * The PPC sits in front of peripherals and allows secure software to | ||
55 | + * configure it to either pass through or reject transactions. | ||
56 | + * Rejected transactions may be configured to either be aborted, or to | ||
57 | + * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. | ||
58 | + * | ||
59 | + * The PPC has no register interface -- it is configured purely by a | ||
60 | + * collection of input signals from other hardware in the system. Typically | ||
61 | + * they are either hardwired or exposed in an ad-hoc register interface by | ||
62 | + * the SoC that uses the PPC. | ||
63 | + * | ||
64 | + * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC, | ||
65 | + * since the only difference between them is that the AHB version has a | ||
66 | + * "default" port which has no security checks applied. In QEMU the default | ||
67 | + * port can be emulated simply by wiring its downstream devices directly | ||
68 | + * into the parent address space, since the PPC does not need to intercept | ||
69 | + * transactions there. | ||
70 | + * | ||
71 | + * In the hardware, selection of which downstream port to use is done by | ||
72 | + * the user's decode logic asserting one of the hsel[] signals. In QEMU, | ||
73 | + * we provide 16 MMIO regions, one per port, and the user maps these into | ||
74 | + * the desired addresses to implement the address decode. | ||
75 | + * | ||
76 | + * QEMU interface: | ||
77 | + * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end | ||
78 | + * of each of the 16 ports of the PPC | ||
79 | + * + Property "port[0..15]": MemoryRegion defining the downstream device(s) | ||
80 | + * for each of the 16 ports of the PPC | ||
81 | + * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be | ||
82 | + * accessible to NonSecure transactions | ||
83 | + * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be | ||
84 | + * accessible to non-privileged transactions | ||
85 | + * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should | ||
86 | + * result in a transaction error, or 0 for the transaction to RAZ/WI | ||
87 | + * + Named GPIO input "irq_enable": set to 1 to enable interrupts | ||
88 | + * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt | ||
89 | + * + Named GPIO output "irq": set for a transaction-failed interrupt | ||
90 | + * + Property "NONSEC_MASK": if a bit is set in this mask then accesses to | ||
91 | + * the associated port do not have the TZ security check performed. (This | ||
92 | + * corresponds to the hardware allowing this to be set as a Verilog | ||
93 | + * parameter.) | ||
94 | + */ | ||
95 | + | ||
96 | +#ifndef TZ_PPC_H | ||
97 | +#define TZ_PPC_H | ||
98 | + | ||
99 | +#include "hw/sysbus.h" | ||
100 | + | ||
101 | +#define TYPE_TZ_PPC "tz-ppc" | ||
102 | +#define TZ_PPC(obj) OBJECT_CHECK(TZPPC, (obj), TYPE_TZ_PPC) | ||
103 | + | ||
104 | +#define TZ_NUM_PORTS 16 | ||
105 | + | ||
106 | +typedef struct TZPPC TZPPC; | ||
107 | + | ||
108 | +typedef struct TZPPCPort { | ||
109 | + TZPPC *ppc; | ||
110 | + MemoryRegion upstream; | ||
111 | + AddressSpace downstream_as; | ||
112 | + MemoryRegion *downstream; | ||
113 | +} TZPPCPort; | ||
114 | + | ||
115 | +struct TZPPC { | ||
116 | + /*< private >*/ | ||
117 | + SysBusDevice parent_obj; | ||
118 | + | ||
119 | + /*< public >*/ | ||
120 | + | ||
121 | + /* State: these just track the values of our input signals */ | ||
122 | + bool cfg_nonsec[TZ_NUM_PORTS]; | ||
123 | + bool cfg_ap[TZ_NUM_PORTS]; | ||
124 | + bool cfg_sec_resp; | ||
125 | + bool irq_enable; | ||
126 | + bool irq_clear; | ||
127 | + /* State: are we asserting irq ? */ | ||
128 | + bool irq_status; | ||
129 | + | ||
130 | + qemu_irq irq; | ||
131 | + | ||
132 | + /* Properties */ | ||
133 | + uint32_t nonsec_mask; | ||
134 | + | ||
135 | + TZPPCPort port[TZ_NUM_PORTS]; | ||
136 | +}; | ||
137 | + | ||
138 | +#endif | ||
139 | diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c | ||
140 | new file mode 100644 | ||
141 | index XXXXXXX..XXXXXXX | ||
142 | --- /dev/null | ||
143 | +++ b/hw/misc/tz-ppc.c | ||
144 | @@ -XXX,XX +XXX,XX @@ | ||
145 | +/* | ||
146 | + * ARM TrustZone peripheral protection controller emulation | ||
147 | + * | ||
148 | + * Copyright (c) 2018 Linaro Limited | ||
149 | + * Written by Peter Maydell | ||
150 | + * | ||
151 | + * This program is free software; you can redistribute it and/or modify | ||
152 | + * it under the terms of the GNU General Public License version 2 or | ||
153 | + * (at your option) any later version. | ||
154 | + */ | ||
155 | + | ||
156 | +#include "qemu/osdep.h" | ||
157 | +#include "qemu/log.h" | ||
158 | +#include "qapi/error.h" | ||
159 | +#include "trace.h" | ||
160 | +#include "hw/sysbus.h" | ||
161 | +#include "hw/registerfields.h" | ||
162 | +#include "hw/misc/tz-ppc.h" | ||
163 | + | ||
164 | +static void tz_ppc_update_irq(TZPPC *s) | ||
165 | +{ | ||
166 | + bool level = s->irq_status && s->irq_enable; | ||
167 | + | ||
168 | + trace_tz_ppc_update_irq(level); | ||
169 | + qemu_set_irq(s->irq, level); | ||
170 | +} | ||
171 | + | ||
172 | +static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) | ||
173 | +{ | ||
174 | + TZPPC *s = TZ_PPC(opaque); | ||
175 | + | ||
176 | + assert(n < TZ_NUM_PORTS); | ||
177 | + trace_tz_ppc_cfg_nonsec(n, level); | ||
178 | + s->cfg_nonsec[n] = level; | ||
179 | +} | ||
180 | + | ||
181 | +static void tz_ppc_cfg_ap(void *opaque, int n, int level) | ||
182 | +{ | ||
183 | + TZPPC *s = TZ_PPC(opaque); | ||
184 | + | ||
185 | + assert(n < TZ_NUM_PORTS); | ||
186 | + trace_tz_ppc_cfg_ap(n, level); | ||
187 | + s->cfg_ap[n] = level; | ||
188 | +} | ||
189 | + | ||
190 | +static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) | ||
191 | +{ | ||
192 | + TZPPC *s = TZ_PPC(opaque); | ||
193 | + | ||
194 | + trace_tz_ppc_cfg_sec_resp(level); | ||
195 | + s->cfg_sec_resp = level; | ||
196 | +} | ||
197 | + | ||
198 | +static void tz_ppc_irq_enable(void *opaque, int n, int level) | ||
199 | +{ | ||
200 | + TZPPC *s = TZ_PPC(opaque); | ||
201 | + | ||
202 | + trace_tz_ppc_irq_enable(level); | ||
203 | + s->irq_enable = level; | ||
204 | + tz_ppc_update_irq(s); | ||
205 | +} | ||
206 | + | ||
207 | +static void tz_ppc_irq_clear(void *opaque, int n, int level) | ||
208 | +{ | ||
209 | + TZPPC *s = TZ_PPC(opaque); | ||
210 | + | ||
211 | + trace_tz_ppc_irq_clear(level); | ||
212 | + | ||
213 | + s->irq_clear = level; | ||
214 | + if (level) { | ||
215 | + s->irq_status = false; | ||
216 | + tz_ppc_update_irq(s); | ||
217 | + } | ||
218 | +} | ||
219 | + | ||
220 | +static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) | ||
221 | +{ | ||
222 | + /* Check whether to allow an access to port n; return true if | ||
223 | + * the check passes, and false if the transaction must be blocked. | ||
224 | + * If the latter, the caller must check cfg_sec_resp to determine | ||
225 | + * whether to abort or RAZ/WI the transaction. | ||
226 | + * The checks are: | ||
227 | + * + nonsec_mask suppresses any check of the secure attribute | ||
228 | + * + otherwise, block if cfg_nonsec is 1 and transaction is secure, | ||
229 | + * or if cfg_nonsec is 0 and transaction is non-secure | ||
230 | + * + block if transaction is usermode and cfg_ap is 0 | ||
231 | + */ | ||
232 | + if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || | ||
233 | + (attrs.user && !s->cfg_ap[n])) { | ||
234 | + /* Block the transaction. */ | ||
235 | + if (!s->irq_clear) { | ||
236 | + /* Note that holding irq_clear high suppresses interrupts */ | ||
237 | + s->irq_status = true; | ||
238 | + tz_ppc_update_irq(s); | ||
239 | + } | ||
240 | + return false; | ||
241 | + } | ||
242 | + return true; | ||
243 | +} | ||
244 | + | ||
245 | +static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, | ||
246 | + unsigned size, MemTxAttrs attrs) | ||
247 | +{ | ||
248 | + TZPPCPort *p = opaque; | ||
249 | + TZPPC *s = p->ppc; | ||
250 | + int n = p - s->port; | ||
251 | + AddressSpace *as = &p->downstream_as; | ||
252 | + uint64_t data; | ||
253 | + MemTxResult res; | ||
254 | + | ||
255 | + if (!tz_ppc_check(s, n, attrs)) { | ||
256 | + trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); | ||
257 | + if (s->cfg_sec_resp) { | ||
258 | + return MEMTX_ERROR; | ||
259 | + } else { | ||
260 | + *pdata = 0; | ||
261 | + return MEMTX_OK; | ||
262 | + } | ||
263 | + } | 36 | + } |
264 | + | 37 | + |
265 | + switch (size) { | 38 | + /* Clear RES0 bits */ |
266 | + case 1: | 39 | + value &= valid_mask; |
267 | + data = address_space_ldub(as, addr, attrs, &res); | ||
268 | + break; | ||
269 | + case 2: | ||
270 | + data = address_space_lduw_le(as, addr, attrs, &res); | ||
271 | + break; | ||
272 | + case 4: | ||
273 | + data = address_space_ldl_le(as, addr, attrs, &res); | ||
274 | + break; | ||
275 | + case 8: | ||
276 | + data = address_space_ldq_le(as, addr, attrs, &res); | ||
277 | + break; | ||
278 | + default: | ||
279 | + g_assert_not_reached(); | ||
280 | + } | ||
281 | + *pdata = data; | ||
282 | + return res; | ||
283 | +} | ||
284 | + | 40 | + |
285 | +static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, | 41 | raw_write(env, ri, value); |
286 | + unsigned size, MemTxAttrs attrs) | 42 | |
287 | +{ | 43 | if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { |
288 | + TZPPCPort *p = opaque; | ||
289 | + TZPPC *s = p->ppc; | ||
290 | + AddressSpace *as = &p->downstream_as; | ||
291 | + int n = p - s->port; | ||
292 | + MemTxResult res; | ||
293 | + | ||
294 | + if (!tz_ppc_check(s, n, attrs)) { | ||
295 | + trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); | ||
296 | + if (s->cfg_sec_resp) { | ||
297 | + return MEMTX_ERROR; | ||
298 | + } else { | ||
299 | + return MEMTX_OK; | ||
300 | + } | ||
301 | + } | ||
302 | + | ||
303 | + switch (size) { | ||
304 | + case 1: | ||
305 | + address_space_stb(as, addr, val, attrs, &res); | ||
306 | + break; | ||
307 | + case 2: | ||
308 | + address_space_stw_le(as, addr, val, attrs, &res); | ||
309 | + break; | ||
310 | + case 4: | ||
311 | + address_space_stl_le(as, addr, val, attrs, &res); | ||
312 | + break; | ||
313 | + case 8: | ||
314 | + address_space_stq_le(as, addr, val, attrs, &res); | ||
315 | + break; | ||
316 | + default: | ||
317 | + g_assert_not_reached(); | ||
318 | + } | ||
319 | + return res; | ||
320 | +} | ||
321 | + | ||
322 | +static const MemoryRegionOps tz_ppc_ops = { | ||
323 | + .read_with_attrs = tz_ppc_read, | ||
324 | + .write_with_attrs = tz_ppc_write, | ||
325 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
326 | +}; | ||
327 | + | ||
328 | +static void tz_ppc_reset(DeviceState *dev) | ||
329 | +{ | ||
330 | + TZPPC *s = TZ_PPC(dev); | ||
331 | + | ||
332 | + trace_tz_ppc_reset(); | ||
333 | + s->cfg_sec_resp = false; | ||
334 | + memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); | ||
335 | + memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); | ||
336 | +} | ||
337 | + | ||
338 | +static void tz_ppc_init(Object *obj) | ||
339 | +{ | ||
340 | + DeviceState *dev = DEVICE(obj); | ||
341 | + TZPPC *s = TZ_PPC(obj); | ||
342 | + | ||
343 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); | ||
344 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); | ||
345 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); | ||
346 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); | ||
347 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); | ||
348 | + qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); | ||
349 | +} | ||
350 | + | ||
351 | +static void tz_ppc_realize(DeviceState *dev, Error **errp) | ||
352 | +{ | ||
353 | + Object *obj = OBJECT(dev); | ||
354 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
355 | + TZPPC *s = TZ_PPC(dev); | ||
356 | + int i; | ||
357 | + | ||
358 | + /* We can't create the upstream end of the port until realize, | ||
359 | + * as we don't know the size of the MR used as the downstream until then. | ||
360 | + */ | ||
361 | + for (i = 0; i < TZ_NUM_PORTS; i++) { | ||
362 | + TZPPCPort *port = &s->port[i]; | ||
363 | + char *name; | ||
364 | + uint64_t size; | ||
365 | + | ||
366 | + if (!port->downstream) { | ||
367 | + continue; | ||
368 | + } | ||
369 | + | ||
370 | + name = g_strdup_printf("tz-ppc-port[%d]", i); | ||
371 | + | ||
372 | + port->ppc = s; | ||
373 | + address_space_init(&port->downstream_as, port->downstream, name); | ||
374 | + | ||
375 | + size = memory_region_size(port->downstream); | ||
376 | + memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, | ||
377 | + port, name, size); | ||
378 | + sysbus_init_mmio(sbd, &port->upstream); | ||
379 | + g_free(name); | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +static const VMStateDescription tz_ppc_vmstate = { | ||
384 | + .name = "tz-ppc", | ||
385 | + .version_id = 1, | ||
386 | + .minimum_version_id = 1, | ||
387 | + .fields = (VMStateField[]) { | ||
388 | + VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), | ||
389 | + VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), | ||
390 | + VMSTATE_BOOL(cfg_sec_resp, TZPPC), | ||
391 | + VMSTATE_BOOL(irq_enable, TZPPC), | ||
392 | + VMSTATE_BOOL(irq_clear, TZPPC), | ||
393 | + VMSTATE_BOOL(irq_status, TZPPC), | ||
394 | + VMSTATE_END_OF_LIST() | ||
395 | + } | ||
396 | +}; | ||
397 | + | ||
398 | +#define DEFINE_PORT(N) \ | ||
399 | + DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ | ||
400 | + TYPE_MEMORY_REGION, MemoryRegion *) | ||
401 | + | ||
402 | +static Property tz_ppc_properties[] = { | ||
403 | + DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), | ||
404 | + DEFINE_PORT(0), | ||
405 | + DEFINE_PORT(1), | ||
406 | + DEFINE_PORT(2), | ||
407 | + DEFINE_PORT(3), | ||
408 | + DEFINE_PORT(4), | ||
409 | + DEFINE_PORT(5), | ||
410 | + DEFINE_PORT(6), | ||
411 | + DEFINE_PORT(7), | ||
412 | + DEFINE_PORT(8), | ||
413 | + DEFINE_PORT(9), | ||
414 | + DEFINE_PORT(10), | ||
415 | + DEFINE_PORT(11), | ||
416 | + DEFINE_PORT(12), | ||
417 | + DEFINE_PORT(13), | ||
418 | + DEFINE_PORT(14), | ||
419 | + DEFINE_PORT(15), | ||
420 | + DEFINE_PROP_END_OF_LIST(), | ||
421 | +}; | ||
422 | + | ||
423 | +static void tz_ppc_class_init(ObjectClass *klass, void *data) | ||
424 | +{ | ||
425 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
426 | + | ||
427 | + dc->realize = tz_ppc_realize; | ||
428 | + dc->vmsd = &tz_ppc_vmstate; | ||
429 | + dc->reset = tz_ppc_reset; | ||
430 | + dc->props = tz_ppc_properties; | ||
431 | +} | ||
432 | + | ||
433 | +static const TypeInfo tz_ppc_info = { | ||
434 | + .name = TYPE_TZ_PPC, | ||
435 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
436 | + .instance_size = sizeof(TZPPC), | ||
437 | + .instance_init = tz_ppc_init, | ||
438 | + .class_init = tz_ppc_class_init, | ||
439 | +}; | ||
440 | + | ||
441 | +static void tz_ppc_register_types(void) | ||
442 | +{ | ||
443 | + type_register_static(&tz_ppc_info); | ||
444 | +} | ||
445 | + | ||
446 | +type_init(tz_ppc_register_types); | ||
447 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
448 | index XXXXXXX..XXXXXXX 100644 | ||
449 | --- a/default-configs/arm-softmmu.mak | ||
450 | +++ b/default-configs/arm-softmmu.mak | ||
451 | @@ -XXX,XX +XXX,XX @@ CONFIG_CMSDK_APB_UART=y | ||
452 | CONFIG_MPS2_FPGAIO=y | ||
453 | CONFIG_MPS2_SCC=y | ||
454 | |||
455 | +CONFIG_TZ_PPC=y | ||
456 | + | ||
457 | CONFIG_VERSATILE_PCI=y | ||
458 | CONFIG_VERSATILE_I2C=y | ||
459 | |||
460 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
461 | index XXXXXXX..XXXXXXX 100644 | ||
462 | --- a/hw/misc/trace-events | ||
463 | +++ b/hw/misc/trace-events | ||
464 | @@ -XXX,XX +XXX,XX @@ mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d co | ||
465 | mos6522_set_sr_int(void) "set sr_int" | ||
466 | mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 | ||
467 | mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" | ||
468 | + | ||
469 | +# hw/misc/tz-ppc.c | ||
470 | +tz_ppc_reset(void) "TZ PPC: reset" | ||
471 | +tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" | ||
472 | +tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" | ||
473 | +tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" | ||
474 | +tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" | ||
475 | +tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
476 | +tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
477 | +tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
478 | +tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
479 | -- | 44 | -- |
480 | 2.16.2 | 45 | 2.34.1 |
481 | |||
482 | diff view generated by jsdifflib |
1 | The IoTKit Security Controller includes various registers | 1 | The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is: |
---|---|---|---|
2 | that expose to software the controls for the Peripheral | 2 | * four new trap bits for various counter and timer registers |
3 | Protection Controllers in the system. Implement these. | 3 | * the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control |
4 | scaling of the event stream. This is a no-op for us, because we don't | ||
5 | implement the event stream (our WFE is a NOP): all we need to do is | ||
6 | allow CNTHCTL_EL2.ENVTIS to be read and written. | ||
7 | * extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and | ||
8 | TRFCR_EL2.TS: these are all no-ops for us, because we don't implement | ||
9 | FEAT_SPE or FEAT_TRF. | ||
10 | * new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are | ||
11 | "self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning | ||
12 | that no barriers are needed around their accesses. For us these | ||
13 | are just the same as the normal views, because all our sysregs are | ||
14 | inherently self-sychronizing. | ||
15 | |||
16 | In this commit we implement the trap handling and permit the new | ||
17 | CNTHCTL_EL2 bits to be written. | ||
4 | 18 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-17-peter.maydell@linaro.org | 21 | Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org |
8 | --- | 22 | --- |
9 | include/hw/misc/iotkit-secctl.h | 64 +++++++++- | 23 | target/arm/cpu-features.h | 5 ++++ |
10 | hw/misc/iotkit-secctl.c | 270 +++++++++++++++++++++++++++++++++++++--- | 24 | target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++---- |
11 | 2 files changed, 315 insertions(+), 19 deletions(-) | 25 | 2 files changed, 51 insertions(+), 5 deletions(-) |
12 | 26 | ||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 27 | diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h |
14 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/misc/iotkit-secctl.h | 29 | --- a/target/arm/cpu-features.h |
16 | +++ b/include/hw/misc/iotkit-secctl.h | 30 | +++ b/target/arm/cpu-features.h |
17 | @@ -XXX,XX +XXX,XX @@ | 31 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) |
18 | * QEMU interface: | 32 | return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; |
19 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | 33 | } |
20 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 34 | |
21 | + * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | 35 | +static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) |
22 | + * should RAZ/WI or bus error | ||
23 | + * Controlling the 2 APB PPCs in the IoTKit: | ||
24 | + * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
25 | + * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
26 | + * + named GPIO outputs apb_ppc{0,1}_irq_enable | ||
27 | + * + named GPIO outputs apb_ppc{0,1}_irq_clear | ||
28 | + * + named GPIO inputs apb_ppc{0,1}_irq_status | ||
29 | + * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit | ||
30 | + * might provide: | ||
31 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
32 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
33 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
34 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
35 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
36 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
37 | + * might provide: | ||
38 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
39 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
40 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
41 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
42 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
43 | */ | ||
44 | |||
45 | #ifndef IOTKIT_SECCTL_H | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
48 | #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
49 | |||
50 | -typedef struct IoTKitSecCtl { | ||
51 | +#define IOTS_APB_PPC0_NUM_PORTS 3 | ||
52 | +#define IOTS_APB_PPC1_NUM_PORTS 1 | ||
53 | +#define IOTS_PPC_NUM_PORTS 16 | ||
54 | +#define IOTS_NUM_APB_PPC 2 | ||
55 | +#define IOTS_NUM_APB_EXP_PPC 4 | ||
56 | +#define IOTS_NUM_AHB_EXP_PPC 4 | ||
57 | + | ||
58 | +typedef struct IoTKitSecCtl IoTKitSecCtl; | ||
59 | + | ||
60 | +/* State and IRQ lines relating to a PPC. For the | ||
61 | + * PPCs in the IoTKit not all the IRQ lines are used. | ||
62 | + */ | ||
63 | +typedef struct IoTKitSecCtlPPC { | ||
64 | + qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; | ||
65 | + qemu_irq ap[IOTS_PPC_NUM_PORTS]; | ||
66 | + qemu_irq irq_enable; | ||
67 | + qemu_irq irq_clear; | ||
68 | + | ||
69 | + uint32_t ns; | ||
70 | + uint32_t sp; | ||
71 | + uint32_t nsp; | ||
72 | + | ||
73 | + /* Number of ports actually present */ | ||
74 | + int numports; | ||
75 | + /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ | ||
76 | + int irq_bit_offset; | ||
77 | + IoTKitSecCtl *parent; | ||
78 | +} IoTKitSecCtlPPC; | ||
79 | + | ||
80 | +struct IoTKitSecCtl { | ||
81 | /*< private >*/ | ||
82 | SysBusDevice parent_obj; | ||
83 | |||
84 | /*< public >*/ | ||
85 | + qemu_irq sec_resp_cfg; | ||
86 | |||
87 | MemoryRegion s_regs; | ||
88 | MemoryRegion ns_regs; | ||
89 | -} IoTKitSecCtl; | ||
90 | + | ||
91 | + uint32_t secppcintstat; | ||
92 | + uint32_t secppcinten; | ||
93 | + uint32_t secrespcfg; | ||
94 | + | ||
95 | + IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
96 | + IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
97 | + IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; | ||
98 | +}; | ||
99 | |||
100 | #endif | ||
101 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/hw/misc/iotkit-secctl.c | ||
104 | +++ b/hw/misc/iotkit-secctl.c | ||
105 | @@ -XXX,XX +XXX,XX @@ static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
106 | 0x0d, 0xf0, 0x05, 0xb1, | ||
107 | }; | ||
108 | |||
109 | +/* The register sets for the various PPCs (AHB internal, APB internal, | ||
110 | + * AHB expansion, APB expansion) are all set up so that they are | ||
111 | + * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs | ||
112 | + * 0, 1, 2, 3 of that type, so we can convert a register address offset | ||
113 | + * into an an index into a PPC array easily. | ||
114 | + */ | ||
115 | +static inline int offset_to_ppc_idx(uint32_t offset) | ||
116 | +{ | 36 | +{ |
117 | + return extract32(offset, 2, 2); | 37 | + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; |
118 | +} | 38 | +} |
119 | + | 39 | + |
120 | +typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc); | 40 | static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) |
121 | + | 41 | { |
122 | +static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn) | 42 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; |
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/helper.c | ||
46 | +++ b/target/arm/helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, | ||
48 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | ||
49 | return CP_ACCESS_TRAP_EL2; | ||
50 | } | ||
51 | + if (has_el2 && timeridx == GTIMER_VIRT) { | ||
52 | + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) { | ||
53 | + return CP_ACCESS_TRAP_EL2; | ||
54 | + } | ||
55 | + } | ||
56 | break; | ||
57 | } | ||
58 | return CP_ACCESS_OK; | ||
59 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, | ||
60 | } | ||
61 | } | ||
62 | } | ||
63 | + if (has_el2 && timeridx == GTIMER_VIRT) { | ||
64 | + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) { | ||
65 | + return CP_ACCESS_TRAP_EL2; | ||
66 | + } | ||
67 | + } | ||
68 | break; | ||
69 | } | ||
70 | return CP_ACCESS_OK; | ||
71 | @@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
72 | if (cpu_isar_feature(aa64_rme, cpu)) { | ||
73 | valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK; | ||
74 | } | ||
75 | + if (cpu_isar_feature(aa64_ecv_traps, cpu)) { | ||
76 | + valid_mask |= | ||
77 | + R_CNTHCTL_EL1TVT_MASK | | ||
78 | + R_CNTHCTL_EL1TVCT_MASK | | ||
79 | + R_CNTHCTL_EL1NVPCT_MASK | | ||
80 | + R_CNTHCTL_EL1NVVCT_MASK | | ||
81 | + R_CNTHCTL_EVNTIS_MASK; | ||
82 | + } | ||
83 | |||
84 | /* Clear RES0 bits */ | ||
85 | value &= valid_mask; | ||
86 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
87 | { | ||
88 | if (arm_current_el(env) == 1) { | ||
89 | /* This must be a FEAT_NV access */ | ||
90 | - /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ | ||
91 | return CP_ACCESS_OK; | ||
92 | } | ||
93 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | ||
94 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
95 | return CP_ACCESS_OK; | ||
96 | } | ||
97 | |||
98 | +static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri, | ||
99 | + bool isread) | ||
123 | +{ | 100 | +{ |
124 | + int i; | 101 | + if (arm_current_el(env) == 1) { |
125 | + | 102 | + /* This must be a FEAT_NV access with NVx == 101 */ |
126 | + for (i = 0; i < IOTS_NUM_APB_PPC; i++) { | 103 | + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) { |
127 | + fn(&s->apb[i]); | 104 | + return CP_ACCESS_TRAP_EL2; |
105 | + } | ||
128 | + } | 106 | + } |
129 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | 107 | + return e2h_access(env, ri, isread); |
130 | + fn(&s->apbexp[i]); | ||
131 | + } | ||
132 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
133 | + fn(&s->ahbexp[i]); | ||
134 | + } | ||
135 | +} | 108 | +} |
136 | + | 109 | + |
137 | static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | 110 | +static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri, |
138 | uint64_t *pdata, | 111 | + bool isread) |
139 | unsigned size, MemTxAttrs attrs) | ||
140 | { | ||
141 | uint64_t r; | ||
142 | uint32_t offset = addr & ~0x3; | ||
143 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
144 | |||
145 | switch (offset) { | ||
146 | case A_AHBNSPPC0: | ||
147 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
148 | r = 0; | ||
149 | break; | ||
150 | case A_SECRESPCFG: | ||
151 | - case A_NSCCFG: | ||
152 | - case A_SECMPCINTSTATUS: | ||
153 | + r = s->secrespcfg; | ||
154 | + break; | ||
155 | case A_SECPPCINTSTAT: | ||
156 | + r = s->secppcintstat; | ||
157 | + break; | ||
158 | case A_SECPPCINTEN: | ||
159 | - case A_SECMSCINTSTAT: | ||
160 | - case A_SECMSCINTEN: | ||
161 | - case A_BRGINTSTAT: | ||
162 | - case A_BRGINTEN: | ||
163 | + r = s->secppcinten; | ||
164 | + break; | ||
165 | case A_AHBNSPPCEXP0: | ||
166 | case A_AHBNSPPCEXP1: | ||
167 | case A_AHBNSPPCEXP2: | ||
168 | case A_AHBNSPPCEXP3: | ||
169 | + r = s->ahbexp[offset_to_ppc_idx(offset)].ns; | ||
170 | + break; | ||
171 | case A_APBNSPPC0: | ||
172 | case A_APBNSPPC1: | ||
173 | + r = s->apb[offset_to_ppc_idx(offset)].ns; | ||
174 | + break; | ||
175 | case A_APBNSPPCEXP0: | ||
176 | case A_APBNSPPCEXP1: | ||
177 | case A_APBNSPPCEXP2: | ||
178 | case A_APBNSPPCEXP3: | ||
179 | + r = s->apbexp[offset_to_ppc_idx(offset)].ns; | ||
180 | + break; | ||
181 | case A_AHBSPPPCEXP0: | ||
182 | case A_AHBSPPPCEXP1: | ||
183 | case A_AHBSPPPCEXP2: | ||
184 | case A_AHBSPPPCEXP3: | ||
185 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
186 | + break; | ||
187 | case A_APBSPPPC0: | ||
188 | case A_APBSPPPC1: | ||
189 | + r = s->apb[offset_to_ppc_idx(offset)].sp; | ||
190 | + break; | ||
191 | case A_APBSPPPCEXP0: | ||
192 | case A_APBSPPPCEXP1: | ||
193 | case A_APBSPPPCEXP2: | ||
194 | case A_APBSPPPCEXP3: | ||
195 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
196 | + break; | ||
197 | + case A_NSCCFG: | ||
198 | + case A_SECMPCINTSTATUS: | ||
199 | + case A_SECMSCINTSTAT: | ||
200 | + case A_SECMSCINTEN: | ||
201 | + case A_BRGINTSTAT: | ||
202 | + case A_BRGINTEN: | ||
203 | case A_NSMSCEXP: | ||
204 | qemu_log_mask(LOG_UNIMP, | ||
205 | "IoTKit SecCtl S block read: " | ||
206 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
207 | return MEMTX_OK; | ||
208 | } | ||
209 | |||
210 | +static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc) | ||
211 | +{ | 112 | +{ |
212 | + int i; | 113 | + if (arm_current_el(env) == 1) { |
213 | + | 114 | + /* This must be a FEAT_NV access with NVx == 101 */ |
214 | + for (i = 0; i < ppc->numports; i++) { | 115 | + if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) { |
215 | + bool v; | 116 | + return CP_ACCESS_TRAP_EL2; |
216 | + | ||
217 | + if (extract32(ppc->ns, i, 1)) { | ||
218 | + v = extract32(ppc->nsp, i, 1); | ||
219 | + } else { | ||
220 | + v = extract32(ppc->sp, i, 1); | ||
221 | + } | 117 | + } |
222 | + qemu_set_irq(ppc->ap[i], v); | ||
223 | + } | 118 | + } |
119 | + return e2h_access(env, ri, isread); | ||
224 | +} | 120 | +} |
225 | + | 121 | + |
226 | +static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t value) | 122 | /* Test if system register redirection is to occur in the current state. */ |
227 | +{ | 123 | static bool redirect_for_e2h(CPUARMState *env) |
228 | + int i; | ||
229 | + | ||
230 | + ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
231 | + for (i = 0; i < ppc->numports; i++) { | ||
232 | + qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); | ||
233 | + } | ||
234 | + iotkit_secctl_update_ppc_ap(ppc); | ||
235 | +} | ||
236 | + | ||
237 | +static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
238 | +{ | ||
239 | + ppc->sp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
240 | + iotkit_secctl_update_ppc_ap(ppc); | ||
241 | +} | ||
242 | + | ||
243 | +static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
244 | +{ | ||
245 | + ppc->nsp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
246 | + iotkit_secctl_update_ppc_ap(ppc); | ||
247 | +} | ||
248 | + | ||
249 | +static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc) | ||
250 | +{ | ||
251 | + uint32_t value = ppc->parent->secppcintstat; | ||
252 | + | ||
253 | + qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1)); | ||
254 | +} | ||
255 | + | ||
256 | +static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc) | ||
257 | +{ | ||
258 | + uint32_t value = ppc->parent->secppcinten; | ||
259 | + | ||
260 | + qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)); | ||
261 | +} | ||
262 | + | ||
263 | static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
264 | uint64_t value, | ||
265 | unsigned size, MemTxAttrs attrs) | ||
266 | { | 124 | { |
267 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | 125 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = { |
268 | uint32_t offset = addr; | 126 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
269 | + IoTKitSecCtlPPC *ppc; | 127 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, |
270 | 128 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
271 | trace_iotkit_secctl_s_write(offset, value, size); | 129 | - .access = PL2_RW, .accessfn = e2h_access, |
272 | 130 | + .access = PL2_RW, .accessfn = access_el1nvpct, | |
273 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | 131 | .nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1, |
274 | 132 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
275 | switch (offset) { | 133 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, |
276 | case A_SECRESPCFG: | 134 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, |
277 | - case A_NSCCFG: | 135 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, |
278 | + value &= 1; | 136 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
279 | + s->secrespcfg = value; | 137 | - .access = PL2_RW, .accessfn = e2h_access, |
280 | + qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); | 138 | + .access = PL2_RW, .accessfn = access_el1nvvct, |
281 | + break; | 139 | .nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1, |
282 | case A_SECPPCINTCLR: | 140 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
283 | + value &= 0x00f000f3; | 141 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, |
284 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear); | 142 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = { |
285 | + break; | 143 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
286 | case A_SECPPCINTEN: | 144 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
287 | - case A_SECMSCINTCLR: | 145 | .nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1, |
288 | - case A_SECMSCINTEN: | 146 | - .access = PL2_RW, .accessfn = e2h_access, |
289 | - case A_BRGINTCLR: | 147 | + .access = PL2_RW, .accessfn = access_el1nvpct, |
290 | - case A_BRGINTEN: | 148 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, |
291 | + s->secppcinten = value & 0x00f000f3; | 149 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, |
292 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | 150 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, |
293 | + break; | 151 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
294 | case A_AHBNSPPCEXP0: | 152 | .nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1, |
295 | case A_AHBNSPPCEXP1: | 153 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
296 | case A_AHBNSPPCEXP2: | 154 | - .access = PL2_RW, .accessfn = e2h_access, |
297 | case A_AHBNSPPCEXP3: | 155 | + .access = PL2_RW, .accessfn = access_el1nvvct, |
298 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | 156 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, |
299 | + iotkit_secctl_ppc_ns_write(ppc, value); | 157 | #endif |
300 | + break; | ||
301 | case A_APBNSPPC0: | ||
302 | case A_APBNSPPC1: | ||
303 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
304 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
305 | + break; | ||
306 | case A_APBNSPPCEXP0: | ||
307 | case A_APBNSPPCEXP1: | ||
308 | case A_APBNSPPCEXP2: | ||
309 | case A_APBNSPPCEXP3: | ||
310 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
311 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
312 | + break; | ||
313 | case A_AHBSPPPCEXP0: | ||
314 | case A_AHBSPPPCEXP1: | ||
315 | case A_AHBSPPPCEXP2: | ||
316 | case A_AHBSPPPCEXP3: | ||
317 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
318 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
319 | + break; | ||
320 | case A_APBSPPPC0: | ||
321 | case A_APBSPPPC1: | ||
322 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
323 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
324 | + break; | ||
325 | case A_APBSPPPCEXP0: | ||
326 | case A_APBSPPPCEXP1: | ||
327 | case A_APBSPPPCEXP2: | ||
328 | case A_APBSPPPCEXP3: | ||
329 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
330 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
331 | + break; | ||
332 | + case A_NSCCFG: | ||
333 | + case A_SECMSCINTCLR: | ||
334 | + case A_SECMSCINTEN: | ||
335 | + case A_BRGINTCLR: | ||
336 | + case A_BRGINTEN: | ||
337 | qemu_log_mask(LOG_UNIMP, | ||
338 | "IoTKit SecCtl S block write: " | ||
339 | "unimplemented offset 0x%x\n", offset); | ||
340 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
341 | uint64_t *pdata, | ||
342 | unsigned size, MemTxAttrs attrs) | ||
343 | { | ||
344 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
345 | uint64_t r; | ||
346 | uint32_t offset = addr & ~0x3; | ||
347 | |||
348 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
349 | case A_AHBNSPPPCEXP1: | ||
350 | case A_AHBNSPPPCEXP2: | ||
351 | case A_AHBNSPPPCEXP3: | ||
352 | + r = s->ahbexp[offset_to_ppc_idx(offset)].nsp; | ||
353 | + break; | ||
354 | case A_APBNSPPPC0: | ||
355 | case A_APBNSPPPC1: | ||
356 | + r = s->apb[offset_to_ppc_idx(offset)].nsp; | ||
357 | + break; | ||
358 | case A_APBNSPPPCEXP0: | ||
359 | case A_APBNSPPPCEXP1: | ||
360 | case A_APBNSPPPCEXP2: | ||
361 | case A_APBNSPPPCEXP3: | ||
362 | - qemu_log_mask(LOG_UNIMP, | ||
363 | - "IoTKit SecCtl NS block read: " | ||
364 | - "unimplemented offset 0x%x\n", offset); | ||
365 | + r = s->apbexp[offset_to_ppc_idx(offset)].nsp; | ||
366 | break; | ||
367 | case A_PID4: | ||
368 | case A_PID5: | ||
369 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
370 | uint64_t value, | ||
371 | unsigned size, MemTxAttrs attrs) | ||
372 | { | ||
373 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
374 | uint32_t offset = addr; | ||
375 | + IoTKitSecCtlPPC *ppc; | ||
376 | |||
377 | trace_iotkit_secctl_ns_write(offset, value, size); | ||
378 | |||
379 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
380 | case A_AHBNSPPPCEXP1: | ||
381 | case A_AHBNSPPPCEXP2: | ||
382 | case A_AHBNSPPPCEXP3: | ||
383 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
384 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
385 | + break; | ||
386 | case A_APBNSPPPC0: | ||
387 | case A_APBNSPPPC1: | ||
388 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
389 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
390 | + break; | ||
391 | case A_APBNSPPPCEXP0: | ||
392 | case A_APBNSPPPCEXP1: | ||
393 | case A_APBNSPPPCEXP2: | ||
394 | case A_APBNSPPPCEXP3: | ||
395 | - qemu_log_mask(LOG_UNIMP, | ||
396 | - "IoTKit SecCtl NS block write: " | ||
397 | - "unimplemented offset 0x%x\n", offset); | ||
398 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
399 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
400 | break; | ||
401 | case A_AHBNSPPPC0: | ||
402 | case A_PID4: | ||
403 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
404 | .impl.max_access_size = 4, | ||
405 | }; | ||
406 | |||
407 | +static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc) | ||
408 | +{ | ||
409 | + ppc->ns = 0; | ||
410 | + ppc->sp = 0; | ||
411 | + ppc->nsp = 0; | ||
412 | +} | ||
413 | + | ||
414 | static void iotkit_secctl_reset(DeviceState *dev) | ||
415 | { | ||
416 | + IoTKitSecCtl *s = IOTKIT_SECCTL(dev); | ||
417 | |||
418 | + s->secppcintstat = 0; | ||
419 | + s->secppcinten = 0; | ||
420 | + s->secrespcfg = 0; | ||
421 | + | ||
422 | + foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
423 | +} | ||
424 | + | ||
425 | +static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level) | ||
426 | +{ | ||
427 | + IoTKitSecCtlPPC *ppc = opaque; | ||
428 | + IoTKitSecCtl *s = IOTKIT_SECCTL(ppc->parent); | ||
429 | + int irqbit = ppc->irq_bit_offset + n; | ||
430 | + | ||
431 | + s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level); | ||
432 | +} | ||
433 | + | ||
434 | +static void iotkit_secctl_init_ppc(IoTKitSecCtl *s, | ||
435 | + IoTKitSecCtlPPC *ppc, | ||
436 | + const char *name, | ||
437 | + int numports, | ||
438 | + int irq_bit_offset) | ||
439 | +{ | ||
440 | + char *gpioname; | ||
441 | + DeviceState *dev = DEVICE(s); | ||
442 | + | ||
443 | + ppc->numports = numports; | ||
444 | + ppc->irq_bit_offset = irq_bit_offset; | ||
445 | + ppc->parent = s; | ||
446 | + | ||
447 | + gpioname = g_strdup_printf("%s_nonsec", name); | ||
448 | + qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports); | ||
449 | + g_free(gpioname); | ||
450 | + gpioname = g_strdup_printf("%s_ap", name); | ||
451 | + qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports); | ||
452 | + g_free(gpioname); | ||
453 | + gpioname = g_strdup_printf("%s_irq_enable", name); | ||
454 | + qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_irq_clear", name); | ||
457 | + qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1); | ||
458 | + g_free(gpioname); | ||
459 | + gpioname = g_strdup_printf("%s_irq_status", name); | ||
460 | + qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus, | ||
461 | + ppc, gpioname, 1); | ||
462 | + g_free(gpioname); | ||
463 | } | ||
464 | |||
465 | static void iotkit_secctl_init(Object *obj) | ||
466 | { | ||
467 | IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
468 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
469 | + DeviceState *dev = DEVICE(obj); | ||
470 | + int i; | ||
471 | + | ||
472 | + iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0", | ||
473 | + IOTS_APB_PPC0_NUM_PORTS, 0); | ||
474 | + iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1", | ||
475 | + IOTS_APB_PPC1_NUM_PORTS, 1); | ||
476 | + | ||
477 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
478 | + IoTKitSecCtlPPC *ppc = &s->apbexp[i]; | ||
479 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
480 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i); | ||
481 | + g_free(ppcname); | ||
482 | + } | ||
483 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
484 | + IoTKitSecCtlPPC *ppc = &s->ahbexp[i]; | ||
485 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
486 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i); | ||
487 | + g_free(ppcname); | ||
488 | + } | ||
489 | + | ||
490 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
491 | |||
492 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
495 | sysbus_init_mmio(sbd, &s->ns_regs); | ||
496 | } | ||
497 | |||
498 | +static const VMStateDescription iotkit_secctl_ppc_vmstate = { | ||
499 | + .name = "iotkit-secctl-ppc", | ||
500 | + .version_id = 1, | ||
501 | + .minimum_version_id = 1, | ||
502 | + .fields = (VMStateField[]) { | ||
503 | + VMSTATE_UINT32(ns, IoTKitSecCtlPPC), | ||
504 | + VMSTATE_UINT32(sp, IoTKitSecCtlPPC), | ||
505 | + VMSTATE_UINT32(nsp, IoTKitSecCtlPPC), | ||
506 | + VMSTATE_END_OF_LIST() | ||
507 | + } | ||
508 | +}; | ||
509 | + | ||
510 | static const VMStateDescription iotkit_secctl_vmstate = { | ||
511 | .name = "iotkit-secctl", | ||
512 | .version_id = 1, | ||
513 | .minimum_version_id = 1, | ||
514 | .fields = (VMStateField[]) { | ||
515 | + VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
516 | + VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
517 | + VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
518 | + VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
519 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
520 | + VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
521 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
522 | + VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1, | ||
523 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
524 | VMSTATE_END_OF_LIST() | ||
525 | } | ||
526 | }; | 158 | }; |
527 | -- | 159 | -- |
528 | 2.16.2 | 160 | 2.34.1 |
529 | |||
530 | diff view generated by jsdifflib |
1 | In some board or SoC models it is necessary to split a qemu_irq line | 1 | For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are |
---|---|---|---|
2 | so that one input can feed multiple outputs. We currently have | 2 | defined, which are "self-synchronized" views of the physical and |
3 | qemu_irq_split() for this, but that has several deficiencies: | 3 | virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers |
4 | * it can only handle splitting a line into two | 4 | (meaning that no barriers are needed around accesses to them to |
5 | * it unavoidably leaks memory, so it can't be used | 5 | ensure that reads of them do not occur speculatively and out-of-order |
6 | in a device that can be deleted | 6 | with other instructions). |
7 | 7 | ||
8 | Implement a qdev device that encapsulates splitting of IRQs, with a | 8 | For QEMU, all our system registers are self-synchronized, so we can |
9 | configurable number of outputs. (This is in some ways the inverse of | 9 | simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0 |
10 | the TYPE_OR_IRQ device.) | 10 | to the new register encodings. |
11 | |||
12 | This means we now implement all the functionality required for | ||
13 | ID_AA64MMFR0_EL1.ECV == 0b0001. | ||
11 | 14 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20180220180325.29818-13-peter.maydell@linaro.org | 17 | Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org |
15 | --- | 18 | --- |
16 | hw/core/Makefile.objs | 1 + | 19 | target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ |
17 | include/hw/core/split-irq.h | 57 +++++++++++++++++++++++++++++ | 20 | 1 file changed, 43 insertions(+) |
18 | include/hw/irq.h | 4 +- | ||
19 | hw/core/split-irq.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ | ||
20 | 4 files changed, 150 insertions(+), 1 deletion(-) | ||
21 | create mode 100644 include/hw/core/split-irq.h | ||
22 | create mode 100644 hw/core/split-irq.c | ||
23 | 21 | ||
24 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | 22 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
25 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/core/Makefile.objs | 24 | --- a/target/arm/helper.c |
27 | +++ b/hw/core/Makefile.objs | 25 | +++ b/target/arm/helper.c |
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_FITLOADER) += loader-fit.o | 26 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
29 | common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o | 27 | }, |
30 | common-obj-$(CONFIG_SOFTMMU) += register.o | 28 | }; |
31 | common-obj-$(CONFIG_SOFTMMU) += or-irq.o | 29 | |
32 | +common-obj-$(CONFIG_SOFTMMU) += split-irq.o | ||
33 | common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o | ||
34 | |||
35 | obj-$(CONFIG_SOFTMMU) += generic-loader.o | ||
36 | diff --git a/include/hw/core/split-irq.h b/include/hw/core/split-irq.h | ||
37 | new file mode 100644 | ||
38 | index XXXXXXX..XXXXXXX | ||
39 | --- /dev/null | ||
40 | +++ b/include/hw/core/split-irq.h | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | +/* | 30 | +/* |
43 | + * IRQ splitter device. | 31 | + * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which |
44 | + * | 32 | + * are "self-synchronizing". For QEMU all sysregs are self-synchronizing, |
45 | + * Copyright (c) 2018 Linaro Limited. | 33 | + * so our implementations here are identical to the normal registers. |
46 | + * Written by Peter Maydell | ||
47 | + * | ||
48 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
49 | + * of this software and associated documentation files (the "Software"), to deal | ||
50 | + * in the Software without restriction, including without limitation the rights | ||
51 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
52 | + * copies of the Software, and to permit persons to whom the Software is | ||
53 | + * furnished to do so, subject to the following conditions: | ||
54 | + * | ||
55 | + * The above copyright notice and this permission notice shall be included in | ||
56 | + * all copies or substantial portions of the Software. | ||
57 | + * | ||
58 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
59 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
60 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
61 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
62 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
63 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
64 | + * THE SOFTWARE. | ||
65 | + */ | 34 | + */ |
66 | + | 35 | +static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = { |
67 | +/* This is a simple device which has one GPIO input line and multiple | 36 | + { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9, |
68 | + * GPIO output lines. Any change on the input line is forwarded to all | 37 | + .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
69 | + * of the outputs. | 38 | + .accessfn = gt_vct_access, |
70 | + * | 39 | + .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
71 | + * QEMU interface: | 40 | + }, |
72 | + * + one unnamed GPIO input: the input line | 41 | + { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64, |
73 | + * + N unnamed GPIO outputs: the output lines | 42 | + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6, |
74 | + * + QOM property "num-lines": sets the number of output lines | 43 | + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
75 | + */ | 44 | + .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
76 | +#ifndef HW_SPLIT_IRQ_H | 45 | + }, |
77 | +#define HW_SPLIT_IRQ_H | 46 | + { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8, |
78 | + | 47 | + .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
79 | +#include "hw/irq.h" | 48 | + .accessfn = gt_pct_access, |
80 | +#include "hw/sysbus.h" | 49 | + .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
81 | +#include "qom/object.h" | 50 | + }, |
82 | + | 51 | + { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64, |
83 | +#define TYPE_SPLIT_IRQ "split-irq" | 52 | + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5, |
84 | + | 53 | + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
85 | +#define MAX_SPLIT_LINES 16 | 54 | + .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
86 | + | 55 | + }, |
87 | +typedef struct SplitIRQ SplitIRQ; | ||
88 | + | ||
89 | +#define SPLIT_IRQ(obj) OBJECT_CHECK(SplitIRQ, (obj), TYPE_SPLIT_IRQ) | ||
90 | + | ||
91 | +struct SplitIRQ { | ||
92 | + DeviceState parent_obj; | ||
93 | + | ||
94 | + qemu_irq out_irq[MAX_SPLIT_LINES]; | ||
95 | + uint16_t num_lines; | ||
96 | +}; | 56 | +}; |
97 | + | 57 | + |
98 | +#endif | 58 | #else |
99 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 59 | |
100 | index XXXXXXX..XXXXXXX 100644 | 60 | /* |
101 | --- a/include/hw/irq.h | 61 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
102 | +++ b/include/hw/irq.h | 62 | }, |
103 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | 63 | }; |
104 | /* Returns a new IRQ with opposite polarity. */ | 64 | |
105 | qemu_irq qemu_irq_invert(qemu_irq irq); | 65 | +/* |
106 | 66 | + * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also | |
107 | -/* Returns a new IRQ which feeds into both the passed IRQs */ | 67 | + * is exposed to userspace by Linux. |
108 | +/* Returns a new IRQ which feeds into both the passed IRQs. | ||
109 | + * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
110 | + */ | 68 | + */ |
111 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | 69 | +static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = { |
112 | 70 | + { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64, | |
113 | /* Returns a new IRQ set which connects 1:1 to another IRQ set, which | 71 | + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6, |
114 | diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c | 72 | + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
115 | new file mode 100644 | 73 | + .readfn = gt_virt_cnt_read, |
116 | index XXXXXXX..XXXXXXX | 74 | + }, |
117 | --- /dev/null | ||
118 | +++ b/hw/core/split-irq.c | ||
119 | @@ -XXX,XX +XXX,XX @@ | ||
120 | +/* | ||
121 | + * IRQ splitter device. | ||
122 | + * | ||
123 | + * Copyright (c) 2018 Linaro Limited. | ||
124 | + * Written by Peter Maydell | ||
125 | + * | ||
126 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
127 | + * of this software and associated documentation files (the "Software"), to deal | ||
128 | + * in the Software without restriction, including without limitation the rights | ||
129 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
130 | + * copies of the Software, and to permit persons to whom the Software is | ||
131 | + * furnished to do so, subject to the following conditions: | ||
132 | + * | ||
133 | + * The above copyright notice and this permission notice shall be included in | ||
134 | + * all copies or substantial portions of the Software. | ||
135 | + * | ||
136 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
137 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
138 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
139 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
140 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
141 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
142 | + * THE SOFTWARE. | ||
143 | + */ | ||
144 | + | ||
145 | +#include "qemu/osdep.h" | ||
146 | +#include "hw/core/split-irq.h" | ||
147 | +#include "qapi/error.h" | ||
148 | + | ||
149 | +static void split_irq_handler(void *opaque, int n, int level) | ||
150 | +{ | ||
151 | + SplitIRQ *s = SPLIT_IRQ(opaque); | ||
152 | + int i; | ||
153 | + | ||
154 | + for (i = 0; i < s->num_lines; i++) { | ||
155 | + qemu_set_irq(s->out_irq[i], level); | ||
156 | + } | ||
157 | +} | ||
158 | + | ||
159 | +static void split_irq_init(Object *obj) | ||
160 | +{ | ||
161 | + qdev_init_gpio_in(DEVICE(obj), split_irq_handler, 1); | ||
162 | +} | ||
163 | + | ||
164 | +static void split_irq_realize(DeviceState *dev, Error **errp) | ||
165 | +{ | ||
166 | + SplitIRQ *s = SPLIT_IRQ(dev); | ||
167 | + | ||
168 | + if (s->num_lines < 1 || s->num_lines >= MAX_SPLIT_LINES) { | ||
169 | + error_setg(errp, | ||
170 | + "IRQ splitter number of lines %d is not between 1 and %d", | ||
171 | + s->num_lines, MAX_SPLIT_LINES); | ||
172 | + return; | ||
173 | + } | ||
174 | + | ||
175 | + qdev_init_gpio_out(dev, s->out_irq, s->num_lines); | ||
176 | +} | ||
177 | + | ||
178 | +static Property split_irq_properties[] = { | ||
179 | + DEFINE_PROP_UINT16("num-lines", SplitIRQ, num_lines, 1), | ||
180 | + DEFINE_PROP_END_OF_LIST(), | ||
181 | +}; | 75 | +}; |
182 | + | 76 | + |
183 | +static void split_irq_class_init(ObjectClass *klass, void *data) | 77 | #endif |
184 | +{ | 78 | |
185 | + DeviceClass *dc = DEVICE_CLASS(klass); | 79 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
186 | + | 80 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
187 | + /* No state to reset or migrate */ | 81 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
188 | + dc->props = split_irq_properties; | 82 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); |
189 | + dc->realize = split_irq_realize; | 83 | } |
190 | + | 84 | + if (cpu_isar_feature(aa64_ecv_traps, cpu)) { |
191 | + /* Reason: Needs to be wired up to work */ | 85 | + define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo); |
192 | + dc->user_creatable = false; | 86 | + } |
193 | +} | 87 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
194 | + | 88 | ARMCPRegInfo vapa_cp_reginfo[] = { |
195 | +static const TypeInfo split_irq_type_info = { | 89 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, |
196 | + .name = TYPE_SPLIT_IRQ, | ||
197 | + .parent = TYPE_DEVICE, | ||
198 | + .instance_size = sizeof(SplitIRQ), | ||
199 | + .instance_init = split_irq_init, | ||
200 | + .class_init = split_irq_class_init, | ||
201 | +}; | ||
202 | + | ||
203 | +static void split_irq_register_types(void) | ||
204 | +{ | ||
205 | + type_register_static(&split_irq_type_info); | ||
206 | +} | ||
207 | + | ||
208 | +type_init(split_irq_register_types) | ||
209 | -- | 90 | -- |
210 | 2.16.2 | 91 | 2.34.1 |
211 | |||
212 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is |
---|---|---|---|
2 | implemented. This is similar to the existing CNTVOFF_EL2, except | ||
3 | that it controls a hypervisor-adjustable offset made to the physical | ||
4 | counter and timer. | ||
2 | 5 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Implement the handling for this register, which includes control/trap |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | bits in SCR_EL3 and CNTHCTL_EL2. |
5 | Message-id: 20180228193125.20577-6-richard.henderson@linaro.org | 8 | |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org | ||
7 | --- | 12 | --- |
8 | target/arm/helper.h | 9 +++++ | 13 | target/arm/cpu-features.h | 5 +++ |
9 | target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ | 14 | target/arm/cpu.h | 1 + |
10 | target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++ | 15 | target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++-- |
11 | 3 files changed, 166 insertions(+) | 16 | target/arm/trace-events | 1 + |
17 | 4 files changed, 73 insertions(+), 2 deletions(-) | ||
12 | 18 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 19 | diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h |
14 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 21 | --- a/target/arm/cpu-features.h |
16 | +++ b/target/arm/helper.h | 22 | +++ b/target/arm/cpu-features.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(dc_zva, void, env, i64) | 23 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) |
18 | DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 24 | return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; |
19 | DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) | ||
20 | |||
21 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, | ||
22 | + void, ptr, ptr, ptr, ptr, i32) | ||
23 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | ||
28 | + void, ptr, ptr, ptr, ptr, i32) | ||
29 | + | ||
30 | #ifdef TARGET_AARCH64 | ||
31 | #include "helper-a64.h" | ||
32 | #endif | ||
33 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/translate-a64.c | ||
36 | +++ b/target/arm/translate-a64.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, | ||
38 | vec_full_reg_size(s), gvec_op); | ||
39 | } | 25 | } |
40 | 26 | ||
41 | +/* Expand a 3-operand + env pointer operation using | 27 | +static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) |
42 | + * an out-of-line helper. | ||
43 | + */ | ||
44 | +static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
45 | + int rn, int rm, gen_helper_gvec_3_ptr *fn) | ||
46 | +{ | 28 | +{ |
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | 29 | + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; |
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), cpu_env, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
51 | +} | 30 | +} |
52 | + | 31 | + |
53 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | 32 | static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) |
54 | * than the 32 bit equivalent. | 33 | { |
55 | */ | 34 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; |
56 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | 35 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
57 | clear_vec_high(s, is_q, rd); | 36 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/cpu.h | ||
38 | +++ b/target/arm/cpu.h | ||
39 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
40 | uint64_t c14_cntkctl; /* Timer Control register */ | ||
41 | uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ | ||
42 | uint64_t cntvoff_el2; /* Counter Virtual Offset register */ | ||
43 | + uint64_t cntpoff_el2; /* Counter Physical Offset register */ | ||
44 | ARMGenericTimer c14_timer[NUM_GTIMERS]; | ||
45 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ | ||
46 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ | ||
47 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/helper.c | ||
50 | +++ b/target/arm/helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
52 | if (cpu_isar_feature(aa64_rme, cpu)) { | ||
53 | valid_mask |= SCR_NSE | SCR_GPF; | ||
54 | } | ||
55 | + if (cpu_isar_feature(aa64_ecv, cpu)) { | ||
56 | + valid_mask |= SCR_ECVEN; | ||
57 | + } | ||
58 | } else { | ||
59 | valid_mask &= ~(SCR_RW | SCR_ST); | ||
60 | if (cpu_isar_feature(aa32_ras, cpu)) { | ||
61 | @@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored) | ||
62 | gt_update_irq(cpu, GTIMER_PHYS); | ||
58 | } | 63 | } |
59 | 64 | ||
60 | +/* AdvSIMD three same extra | 65 | +static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) |
61 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
62 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
63 | + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
64 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
65 | + */ | ||
66 | +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | +{ | 66 | +{ |
68 | + int rd = extract32(insn, 0, 5); | 67 | + if ((env->cp15.scr_el3 & SCR_ECVEN) && |
69 | + int rn = extract32(insn, 5, 5); | 68 | + FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) && |
70 | + int opcode = extract32(insn, 11, 4); | 69 | + arm_is_el2_enabled(env) && |
71 | + int rm = extract32(insn, 16, 5); | 70 | + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
72 | + int size = extract32(insn, 22, 2); | 71 | + return env->cp15.cntpoff_el2; |
73 | + bool u = extract32(insn, 29, 1); | ||
74 | + bool is_q = extract32(insn, 30, 1); | ||
75 | + int feature; | ||
76 | + | ||
77 | + switch (u * 16 + opcode) { | ||
78 | + case 0x10: /* SQRDMLAH (vector) */ | ||
79 | + case 0x11: /* SQRDMLSH (vector) */ | ||
80 | + if (size != 1 && size != 2) { | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + feature = ARM_FEATURE_V8_RDM; | ||
85 | + break; | ||
86 | + default: | ||
87 | + unallocated_encoding(s); | ||
88 | + return; | ||
89 | + } | 72 | + } |
90 | + if (!arm_dc_feature(s, feature)) { | 73 | + return 0; |
91 | + unallocated_encoding(s); | ||
92 | + return; | ||
93 | + } | ||
94 | + if (!fp_access_check(s)) { | ||
95 | + return; | ||
96 | + } | ||
97 | + | ||
98 | + switch (opcode) { | ||
99 | + case 0x0: /* SQRDMLAH (vector) */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); | ||
103 | + break; | ||
104 | + case 2: | ||
105 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); | ||
106 | + break; | ||
107 | + default: | ||
108 | + g_assert_not_reached(); | ||
109 | + } | ||
110 | + return; | ||
111 | + | ||
112 | + case 0x1: /* SQRDMLSH (vector) */ | ||
113 | + switch (size) { | ||
114 | + case 1: | ||
115 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); | ||
116 | + break; | ||
117 | + case 2: | ||
118 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); | ||
119 | + break; | ||
120 | + default: | ||
121 | + g_assert_not_reached(); | ||
122 | + } | ||
123 | + return; | ||
124 | + | ||
125 | + default: | ||
126 | + g_assert_not_reached(); | ||
127 | + } | ||
128 | +} | 74 | +} |
129 | + | 75 | + |
130 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, | 76 | +static uint64_t gt_phys_cnt_offset(CPUARMState *env) |
131 | int size, int rn, int rd) | ||
132 | { | ||
133 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | ||
134 | static const AArch64DecodeTable data_proc_simd[] = { | ||
135 | /* pattern , mask , fn */ | ||
136 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | ||
137 | + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, | ||
138 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | ||
139 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | ||
140 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | ||
141 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/vec_helper.c | ||
144 | +++ b/target/arm/vec_helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ | ||
146 | |||
147 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
148 | |||
149 | +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
150 | +{ | 77 | +{ |
151 | + uint64_t *d = vd + opr_sz; | 78 | + if (arm_current_el(env) >= 2) { |
152 | + uintptr_t i; | 79 | + return 0; |
153 | + | ||
154 | + for (i = opr_sz; i < max_sz; i += 8) { | ||
155 | + *d++ = 0; | ||
156 | + } | 80 | + } |
81 | + return gt_phys_raw_cnt_offset(env); | ||
157 | +} | 82 | +} |
158 | + | 83 | + |
159 | /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | 84 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
160 | static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | 85 | { |
161 | int16_t src2, int16_t src3) | 86 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; |
162 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | 87 | @@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
163 | return deposit32(e1, 16, 16, e2); | 88 | * reset timer to when ISTATUS next has to change |
89 | */ | ||
90 | uint64_t offset = timeridx == GTIMER_VIRT ? | ||
91 | - cpu->env.cp15.cntvoff_el2 : 0; | ||
92 | + cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); | ||
93 | uint64_t count = gt_get_countervalue(&cpu->env); | ||
94 | /* Note that this must be unsigned 64 bit arithmetic: */ | ||
95 | int istatus = count - offset >= gt->cval; | ||
96 | @@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, | ||
97 | |||
98 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
99 | { | ||
100 | - return gt_get_countervalue(env); | ||
101 | + return gt_get_countervalue(env) - gt_phys_cnt_offset(env); | ||
164 | } | 102 | } |
165 | 103 | ||
166 | +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, | 104 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
167 | + void *ve, uint32_t desc) | 105 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
106 | case GTIMER_HYPVIRT: | ||
107 | offset = gt_virt_cnt_offset(env); | ||
108 | break; | ||
109 | + case GTIMER_PHYS: | ||
110 | + offset = gt_phys_cnt_offset(env); | ||
111 | + break; | ||
112 | } | ||
113 | |||
114 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - | ||
115 | @@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
116 | case GTIMER_HYPVIRT: | ||
117 | offset = gt_virt_cnt_offset(env); | ||
118 | break; | ||
119 | + case GTIMER_PHYS: | ||
120 | + offset = gt_phys_cnt_offset(env); | ||
121 | + break; | ||
122 | } | ||
123 | |||
124 | trace_arm_gt_tval_write(timeridx, value); | ||
125 | @@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
126 | R_CNTHCTL_EL1NVVCT_MASK | | ||
127 | R_CNTHCTL_EVNTIS_MASK; | ||
128 | } | ||
129 | + if (cpu_isar_feature(aa64_ecv, cpu)) { | ||
130 | + valid_mask |= R_CNTHCTL_ECV_MASK; | ||
131 | + } | ||
132 | |||
133 | /* Clear RES0 bits */ | ||
134 | value &= valid_mask; | ||
135 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = { | ||
136 | }, | ||
137 | }; | ||
138 | |||
139 | +static CPAccessResult gt_cntpoff_access(CPUARMState *env, | ||
140 | + const ARMCPRegInfo *ri, | ||
141 | + bool isread) | ||
168 | +{ | 142 | +{ |
169 | + uintptr_t opr_sz = simd_oprsz(desc); | 143 | + if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) { |
170 | + int16_t *d = vd; | 144 | + return CP_ACCESS_TRAP_EL3; |
171 | + int16_t *n = vn; | ||
172 | + int16_t *m = vm; | ||
173 | + CPUARMState *env = ve; | ||
174 | + uintptr_t i; | ||
175 | + | ||
176 | + for (i = 0; i < opr_sz / 2; ++i) { | ||
177 | + d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); | ||
178 | + } | 145 | + } |
179 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 146 | + return CP_ACCESS_OK; |
180 | +} | 147 | +} |
181 | + | 148 | + |
182 | /* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | 149 | +static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
183 | static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | 150 | + uint64_t value) |
184 | int16_t src2, int16_t src3) | ||
185 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
186 | return deposit32(e1, 16, 16, e2); | ||
187 | } | ||
188 | |||
189 | +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, | ||
190 | + void *ve, uint32_t desc) | ||
191 | +{ | 151 | +{ |
192 | + uintptr_t opr_sz = simd_oprsz(desc); | 152 | + ARMCPU *cpu = env_archcpu(env); |
193 | + int16_t *d = vd; | ||
194 | + int16_t *n = vn; | ||
195 | + int16_t *m = vm; | ||
196 | + CPUARMState *env = ve; | ||
197 | + uintptr_t i; | ||
198 | + | 153 | + |
199 | + for (i = 0; i < opr_sz / 2; ++i) { | 154 | + trace_arm_gt_cntpoff_write(value); |
200 | + d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]); | 155 | + raw_write(env, ri, value); |
201 | + } | 156 | + gt_recalc_timer(cpu, GTIMER_PHYS); |
202 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
203 | +} | 157 | +} |
204 | + | 158 | + |
205 | /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | 159 | +static const ARMCPRegInfo gen_timer_cntpoff_reginfo = { |
206 | uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | 160 | + .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64, |
207 | int32_t src2, int32_t src3) | 161 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6, |
208 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | 162 | + .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, |
209 | return ret; | 163 | + .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write, |
210 | } | 164 | + .nv2_redirect_offset = 0x1a8, |
211 | 165 | + .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2), | |
212 | +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, | 166 | +}; |
213 | + void *ve, uint32_t desc) | 167 | #else |
214 | +{ | 168 | |
215 | + uintptr_t opr_sz = simd_oprsz(desc); | 169 | /* |
216 | + int32_t *d = vd; | 170 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
217 | + int32_t *n = vn; | 171 | if (cpu_isar_feature(aa64_ecv_traps, cpu)) { |
218 | + int32_t *m = vm; | 172 | define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo); |
219 | + CPUARMState *env = ve; | 173 | } |
220 | + uintptr_t i; | 174 | +#ifndef CONFIG_USER_ONLY |
221 | + | 175 | + if (cpu_isar_feature(aa64_ecv, cpu)) { |
222 | + for (i = 0; i < opr_sz / 4; ++i) { | 176 | + define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo); |
223 | + d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); | ||
224 | + } | 177 | + } |
225 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 178 | +#endif |
226 | +} | 179 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
227 | + | 180 | ARMCPRegInfo vapa_cp_reginfo[] = { |
228 | /* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | 181 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, |
229 | uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | 182 | diff --git a/target/arm/trace-events b/target/arm/trace-events |
230 | int32_t src2, int32_t src3) | 183 | index XXXXXXX..XXXXXXX 100644 |
231 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | 184 | --- a/target/arm/trace-events |
232 | } | 185 | +++ b/target/arm/trace-events |
233 | return ret; | 186 | @@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%" |
234 | } | 187 | arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64 |
235 | + | 188 | arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle" |
236 | +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | 189 | arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 |
237 | + void *ve, uint32_t desc) | 190 | +arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64 |
238 | +{ | 191 | arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" |
239 | + uintptr_t opr_sz = simd_oprsz(desc); | 192 | |
240 | + int32_t *d = vd; | 193 | # kvm.c |
241 | + int32_t *n = vn; | ||
242 | + int32_t *m = vm; | ||
243 | + CPUARMState *env = ve; | ||
244 | + uintptr_t i; | ||
245 | + | ||
246 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
247 | + d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); | ||
248 | + } | ||
249 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
250 | +} | ||
251 | -- | 194 | -- |
252 | 2.16.2 | 195 | 2.34.1 |
253 | |||
254 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Enable all FEAT_ECV features on the 'max' CPU. |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-17-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org | ||
9 | --- | 7 | --- |
10 | target/arm/cpu.c | 1 + | 8 | docs/system/arm/emulation.rst | 1 + |
11 | target/arm/cpu64.c | 1 + | 9 | target/arm/tcg/cpu64.c | 1 + |
12 | 2 files changed, 2 insertions(+) | 10 | 2 files changed, 2 insertions(+) |
13 | 11 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 12 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 14 | --- a/docs/system/arm/emulation.rst |
17 | +++ b/target/arm/cpu.c | 15 | +++ b/docs/system/arm/emulation.rst |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 16 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 17 | - FEAT_DotProd (Advanced SIMD dot product instructions) |
20 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 18 | - FEAT_DoubleFault (Double Fault Extension) |
21 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 19 | - FEAT_E0PD (Preventing EL0 access to halves of address maps) |
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 20 | +- FEAT_ECV (Enhanced Counter Virtualization) |
23 | cpu->midr = 0xffffffff; | 21 | - FEAT_EPAC (Enhanced pointer authentication) |
24 | } | 22 | - FEAT_ETS (Enhanced Translation Synchronization) |
25 | #endif | 23 | - FEAT_EVT (Enhanced Virtualization Traps) |
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 24 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
27 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/cpu64.c | 26 | --- a/target/arm/tcg/cpu64.c |
29 | +++ b/target/arm/cpu64.c | 27 | +++ b/target/arm/tcg/cpu64.c |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 28 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) |
31 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 29 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 30 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ |
33 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 31 | t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 32 | + t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ |
35 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 33 | cpu->isar.id_aa64mmfr0 = t; |
36 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 34 | |
37 | } | 35 | t = cpu->isar.id_aa64mmfr1; |
38 | -- | 36 | -- |
39 | 2.16.2 | 37 | 2.34.1 |
40 | 38 | ||
41 | 39 | diff view generated by jsdifflib |
1 | The MPS2 AN505 FPGA image includes a "FPGA control block" | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | which is a small set of registers handling LEDs, buttons | ||
3 | and some counters. | ||
4 | 2 | ||
3 | Features supported : | ||
4 | - the 8 STM32L4x5 GPIOs are initialized with their reset values | ||
5 | (except IDR, see below) | ||
6 | - input mode : setting a pin in input mode "externally" (using input | ||
7 | irqs) results in an out irq (transmitted to SYSCFG) | ||
8 | - output mode : setting a bit in ODR sets the corresponding out irq | ||
9 | (if this line is configured in output mode) | ||
10 | - pull-up, pull-down | ||
11 | - push-pull, open-drain | ||
12 | |||
13 | Difference with the real GPIOs : | ||
14 | - Alternate Function and Analog mode aren't implemented : | ||
15 | pins in AF/Analog behave like pins in input mode | ||
16 | - floating pins stay at their last value | ||
17 | - register IDR reset values differ from the real one : | ||
18 | values are coherent with the other registers reset values | ||
19 | and the fact that AF/Analog modes aren't implemented | ||
20 | - setting I/O output speed isn't supported | ||
21 | - locking port bits isn't supported | ||
22 | - ADC function isn't supported | ||
23 | - GPIOH has 16 pins instead of 2 pins | ||
24 | - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective | ||
25 | |||
26 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
27 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | ||
28 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
29 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
30 | Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-14-peter.maydell@linaro.org | ||
8 | --- | 32 | --- |
9 | hw/misc/Makefile.objs | 1 + | 33 | MAINTAINERS | 1 + |
10 | include/hw/misc/mps2-fpgaio.h | 43 ++++++++++ | 34 | docs/system/arm/b-l475e-iot01a.rst | 2 +- |
11 | hw/misc/mps2-fpgaio.c | 176 ++++++++++++++++++++++++++++++++++++++++ | 35 | include/hw/gpio/stm32l4x5_gpio.h | 70 +++++ |
12 | default-configs/arm-softmmu.mak | 1 + | 36 | hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++ |
13 | hw/misc/trace-events | 6 ++ | 37 | hw/gpio/Kconfig | 3 + |
14 | 5 files changed, 227 insertions(+) | 38 | hw/gpio/meson.build | 1 + |
15 | create mode 100644 include/hw/misc/mps2-fpgaio.h | 39 | hw/gpio/trace-events | 6 + |
16 | create mode 100644 hw/misc/mps2-fpgaio.c | 40 | 7 files changed, 559 insertions(+), 1 deletion(-) |
41 | create mode 100644 include/hw/gpio/stm32l4x5_gpio.h | ||
42 | create mode 100644 hw/gpio/stm32l4x5_gpio.c | ||
17 | 43 | ||
18 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 44 | diff --git a/MAINTAINERS b/MAINTAINERS |
19 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/misc/Makefile.objs | 46 | --- a/MAINTAINERS |
21 | +++ b/hw/misc/Makefile.objs | 47 | +++ b/MAINTAINERS |
22 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | 48 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c |
23 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | 49 | F: hw/misc/stm32l4x5_exti.c |
24 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | 50 | F: hw/misc/stm32l4x5_syscfg.c |
25 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 51 | F: hw/misc/stm32l4x5_rcc.c |
26 | +obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 52 | +F: hw/gpio/stm32l4x5_gpio.c |
27 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 53 | F: include/hw/*/stm32l4x5_*.h |
28 | 54 | ||
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 55 | B-L475E-IOT01A IoT Node |
30 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h | 56 | diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst |
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/docs/system/arm/b-l475e-iot01a.rst | ||
59 | +++ b/docs/system/arm/b-l475e-iot01a.rst | ||
60 | @@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices: | ||
61 | - STM32L4x5 EXTI (Extended interrupts and events controller) | ||
62 | - STM32L4x5 SYSCFG (System configuration controller) | ||
63 | - STM32L4x5 RCC (Reset and clock control) | ||
64 | +- STM32L4x5 GPIOs (General-purpose I/Os) | ||
65 | |||
66 | Missing devices | ||
67 | """"""""""""""" | ||
68 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
69 | The B-L475E-IOT01A does *not* support the following devices: | ||
70 | |||
71 | - Serial ports (UART) | ||
72 | -- General-purpose I/Os (GPIO) | ||
73 | - Analog to Digital Converter (ADC) | ||
74 | - SPI controller | ||
75 | - Timer controller (TIMER) | ||
76 | diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h | ||
31 | new file mode 100644 | 77 | new file mode 100644 |
32 | index XXXXXXX..XXXXXXX | 78 | index XXXXXXX..XXXXXXX |
33 | --- /dev/null | 79 | --- /dev/null |
34 | +++ b/include/hw/misc/mps2-fpgaio.h | 80 | +++ b/include/hw/gpio/stm32l4x5_gpio.h |
35 | @@ -XXX,XX +XXX,XX @@ | 81 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 82 | +/* |
37 | + * ARM MPS2 FPGAIO emulation | 83 | + * STM32L4x5 GPIO (General Purpose Input/Ouput) |
38 | + * | 84 | + * |
39 | + * Copyright (c) 2018 Linaro Limited | 85 | + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
40 | + * Written by Peter Maydell | 86 | + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> |
41 | + * | 87 | + * |
42 | + * This program is free software; you can redistribute it and/or modify | 88 | + * SPDX-License-Identifier: GPL-2.0-or-later |
43 | + * it under the terms of the GNU General Public License version 2 or | 89 | + * |
44 | + * (at your option) any later version. | 90 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
91 | + * See the COPYING file in the top-level directory. | ||
45 | + */ | 92 | + */ |
46 | + | 93 | + |
47 | +/* This is a model of the FPGAIO register block in the AN505 | 94 | +/* |
48 | + * FPGA image for the MPS2 dev board; it is documented in the | 95 | + * The reference used is the STMicroElectronics RM0351 Reference manual |
49 | + * application note: | 96 | + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. |
50 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | 97 | + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html |
51 | + * | ||
52 | + * QEMU interface: | ||
53 | + * + sysbus MMIO region 0: the register bank | ||
54 | + */ | 98 | + */ |
55 | + | 99 | + |
56 | +#ifndef MPS2_FPGAIO_H | 100 | +#ifndef HW_STM32L4X5_GPIO_H |
57 | +#define MPS2_FPGAIO_H | 101 | +#define HW_STM32L4X5_GPIO_H |
58 | + | 102 | + |
59 | +#include "hw/sysbus.h" | 103 | +#include "hw/sysbus.h" |
60 | + | 104 | +#include "qom/object.h" |
61 | +#define TYPE_MPS2_FPGAIO "mps2-fpgaio" | 105 | + |
62 | +#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO) | 106 | +#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio" |
63 | + | 107 | +OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO) |
64 | +typedef struct { | 108 | + |
65 | + /*< private >*/ | 109 | +#define GPIO_NUM_PINS 16 |
110 | + | ||
111 | +struct Stm32l4x5GpioState { | ||
66 | + SysBusDevice parent_obj; | 112 | + SysBusDevice parent_obj; |
67 | + | 113 | + |
68 | + /*< public >*/ | 114 | + MemoryRegion mmio; |
69 | + MemoryRegion iomem; | 115 | + |
70 | + | 116 | + /* GPIO registers */ |
71 | + uint32_t led0; | 117 | + uint32_t moder; |
72 | + uint32_t prescale; | 118 | + uint32_t otyper; |
73 | + uint32_t misc; | 119 | + uint32_t ospeedr; |
74 | + | 120 | + uint32_t pupdr; |
75 | + uint32_t prescale_clk; | 121 | + uint32_t idr; |
76 | +} MPS2FPGAIO; | 122 | + uint32_t odr; |
123 | + uint32_t lckr; | ||
124 | + uint32_t afrl; | ||
125 | + uint32_t afrh; | ||
126 | + uint32_t ascr; | ||
127 | + | ||
128 | + /* GPIO registers reset values */ | ||
129 | + uint32_t moder_reset; | ||
130 | + uint32_t ospeedr_reset; | ||
131 | + uint32_t pupdr_reset; | ||
132 | + | ||
133 | + /* | ||
134 | + * External driving of pins. | ||
135 | + * The pins can be set externally through the device | ||
136 | + * anonymous input GPIOs lines under certain conditions. | ||
137 | + * The pin must not be in push-pull output mode, | ||
138 | + * and can't be set high in open-drain mode. | ||
139 | + * Pins driven externally and configured to | ||
140 | + * output mode will in general be "disconnected" | ||
141 | + * (see `get_gpio_pinmask_to_disconnect()`) | ||
142 | + */ | ||
143 | + uint16_t disconnected_pins; | ||
144 | + uint16_t pins_connected_high; | ||
145 | + | ||
146 | + char *name; | ||
147 | + Clock *clk; | ||
148 | + qemu_irq pin[GPIO_NUM_PINS]; | ||
149 | +}; | ||
77 | + | 150 | + |
78 | +#endif | 151 | +#endif |
79 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | 152 | diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c |
80 | new file mode 100644 | 153 | new file mode 100644 |
81 | index XXXXXXX..XXXXXXX | 154 | index XXXXXXX..XXXXXXX |
82 | --- /dev/null | 155 | --- /dev/null |
83 | +++ b/hw/misc/mps2-fpgaio.c | 156 | +++ b/hw/gpio/stm32l4x5_gpio.c |
84 | @@ -XXX,XX +XXX,XX @@ | 157 | @@ -XXX,XX +XXX,XX @@ |
85 | +/* | 158 | +/* |
86 | + * ARM MPS2 AN505 FPGAIO emulation | 159 | + * STM32L4x5 GPIO (General Purpose Input/Ouput) |
87 | + * | 160 | + * |
88 | + * Copyright (c) 2018 Linaro Limited | 161 | + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
89 | + * Written by Peter Maydell | 162 | + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> |
90 | + * | 163 | + * |
91 | + * This program is free software; you can redistribute it and/or modify | 164 | + * SPDX-License-Identifier: GPL-2.0-or-later |
92 | + * it under the terms of the GNU General Public License version 2 or | 165 | + * |
93 | + * (at your option) any later version. | 166 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
167 | + * See the COPYING file in the top-level directory. | ||
94 | + */ | 168 | + */ |
95 | + | 169 | + |
96 | +/* This is a model of the "FPGA system control and I/O" block found | 170 | +/* |
97 | + * in the AN505 FPGA image for the MPS2 devboard. | 171 | + * The reference used is the STMicroElectronics RM0351 Reference manual |
98 | + * It is documented in AN505: | 172 | + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. |
99 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | 173 | + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html |
100 | + */ | 174 | + */ |
101 | + | 175 | + |
102 | +#include "qemu/osdep.h" | 176 | +#include "qemu/osdep.h" |
103 | +#include "qemu/log.h" | 177 | +#include "qemu/log.h" |
178 | +#include "hw/gpio/stm32l4x5_gpio.h" | ||
179 | +#include "hw/irq.h" | ||
180 | +#include "hw/qdev-clock.h" | ||
181 | +#include "hw/qdev-properties.h" | ||
182 | +#include "qapi/visitor.h" | ||
104 | +#include "qapi/error.h" | 183 | +#include "qapi/error.h" |
184 | +#include "migration/vmstate.h" | ||
105 | +#include "trace.h" | 185 | +#include "trace.h" |
106 | +#include "hw/sysbus.h" | 186 | + |
107 | +#include "hw/registerfields.h" | 187 | +#define GPIO_MODER 0x00 |
108 | +#include "hw/misc/mps2-fpgaio.h" | 188 | +#define GPIO_OTYPER 0x04 |
109 | + | 189 | +#define GPIO_OSPEEDR 0x08 |
110 | +REG32(LED0, 0) | 190 | +#define GPIO_PUPDR 0x0C |
111 | +REG32(BUTTON, 8) | 191 | +#define GPIO_IDR 0x10 |
112 | +REG32(CLK1HZ, 0x10) | 192 | +#define GPIO_ODR 0x14 |
113 | +REG32(CLK100HZ, 0x14) | 193 | +#define GPIO_BSRR 0x18 |
114 | +REG32(COUNTER, 0x18) | 194 | +#define GPIO_LCKR 0x1C |
115 | +REG32(PRESCALE, 0x1c) | 195 | +#define GPIO_AFRL 0x20 |
116 | +REG32(PSCNTR, 0x20) | 196 | +#define GPIO_AFRH 0x24 |
117 | +REG32(MISC, 0x4c) | 197 | +#define GPIO_BRR 0x28 |
118 | + | 198 | +#define GPIO_ASCR 0x2C |
119 | +static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) | 199 | + |
120 | +{ | 200 | +/* 0b11111111_11111111_00000000_00000000 */ |
121 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | 201 | +#define RESERVED_BITS_MASK 0xFFFF0000 |
122 | + uint64_t r; | 202 | + |
123 | + | 203 | +static void update_gpio_idr(Stm32l4x5GpioState *s); |
124 | + switch (offset) { | 204 | + |
125 | + case A_LED0: | 205 | +static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin) |
126 | + r = s->led0; | 206 | +{ |
127 | + break; | 207 | + return extract32(s->pupdr, 2 * pin, 2) == 1; |
128 | + case A_BUTTON: | 208 | +} |
129 | + /* User-pressable board buttons. We don't model that, so just return | 209 | + |
130 | + * zeroes. | 210 | +static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin) |
131 | + */ | 211 | +{ |
132 | + r = 0; | 212 | + return extract32(s->pupdr, 2 * pin, 2) == 2; |
133 | + break; | 213 | +} |
134 | + case A_PRESCALE: | 214 | + |
135 | + r = s->prescale; | 215 | +static bool is_output(Stm32l4x5GpioState *s, unsigned pin) |
136 | + break; | 216 | +{ |
137 | + case A_MISC: | 217 | + return extract32(s->moder, 2 * pin, 2) == 1; |
138 | + r = s->misc; | 218 | +} |
139 | + break; | 219 | + |
140 | + case A_CLK1HZ: | 220 | +static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin) |
141 | + case A_CLK100HZ: | 221 | +{ |
142 | + case A_COUNTER: | 222 | + return extract32(s->otyper, pin, 1) == 1; |
143 | + case A_PSCNTR: | 223 | +} |
144 | + /* These are all upcounters of various frequencies. */ | 224 | + |
145 | + qemu_log_mask(LOG_UNIMP, "MPS2 FPGAIO: counters unimplemented\n"); | 225 | +static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin) |
146 | + r = 0; | 226 | +{ |
147 | + break; | 227 | + return extract32(s->otyper, pin, 1) == 0; |
228 | +} | ||
229 | + | ||
230 | +static void stm32l4x5_gpio_reset_hold(Object *obj) | ||
231 | +{ | ||
232 | + Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj); | ||
233 | + | ||
234 | + s->moder = s->moder_reset; | ||
235 | + s->otyper = 0x00000000; | ||
236 | + s->ospeedr = s->ospeedr_reset; | ||
237 | + s->pupdr = s->pupdr_reset; | ||
238 | + s->idr = 0x00000000; | ||
239 | + s->odr = 0x00000000; | ||
240 | + s->lckr = 0x00000000; | ||
241 | + s->afrl = 0x00000000; | ||
242 | + s->afrh = 0x00000000; | ||
243 | + s->ascr = 0x00000000; | ||
244 | + | ||
245 | + s->disconnected_pins = 0xFFFF; | ||
246 | + s->pins_connected_high = 0x0000; | ||
247 | + update_gpio_idr(s); | ||
248 | +} | ||
249 | + | ||
250 | +static void stm32l4x5_gpio_set(void *opaque, int line, int level) | ||
251 | +{ | ||
252 | + Stm32l4x5GpioState *s = opaque; | ||
253 | + /* | ||
254 | + * The pin isn't set if line is configured in output mode | ||
255 | + * except if level is 0 and the output is open-drain. | ||
256 | + * This way there will be no short-circuit prone situations. | ||
257 | + */ | ||
258 | + if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) { | ||
259 | + qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n", | ||
260 | + line); | ||
261 | + return; | ||
262 | + } | ||
263 | + | ||
264 | + s->disconnected_pins &= ~(1 << line); | ||
265 | + if (level) { | ||
266 | + s->pins_connected_high |= (1 << line); | ||
267 | + } else { | ||
268 | + s->pins_connected_high &= ~(1 << line); | ||
269 | + } | ||
270 | + trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins, | ||
271 | + s->pins_connected_high); | ||
272 | + update_gpio_idr(s); | ||
273 | +} | ||
274 | + | ||
275 | + | ||
276 | +static void update_gpio_idr(Stm32l4x5GpioState *s) | ||
277 | +{ | ||
278 | + uint32_t new_idr_mask = 0; | ||
279 | + uint32_t new_idr = s->odr; | ||
280 | + uint32_t old_idr = s->idr; | ||
281 | + int new_pin_state, old_pin_state; | ||
282 | + | ||
283 | + for (int i = 0; i < GPIO_NUM_PINS; i++) { | ||
284 | + if (is_output(s, i)) { | ||
285 | + if (is_push_pull(s, i)) { | ||
286 | + new_idr_mask |= (1 << i); | ||
287 | + } else if (!(s->odr & (1 << i))) { | ||
288 | + /* open-drain ODR 0 */ | ||
289 | + new_idr_mask |= (1 << i); | ||
290 | + /* open-drain ODR 1 */ | ||
291 | + } else if (!(s->disconnected_pins & (1 << i)) && | ||
292 | + !(s->pins_connected_high & (1 << i))) { | ||
293 | + /* open-drain ODR 1 with pin connected low */ | ||
294 | + new_idr_mask |= (1 << i); | ||
295 | + new_idr &= ~(1 << i); | ||
296 | + /* open-drain ODR 1 with unactive pin */ | ||
297 | + } else if (is_pull_up(s, i)) { | ||
298 | + new_idr_mask |= (1 << i); | ||
299 | + } else if (is_pull_down(s, i)) { | ||
300 | + new_idr_mask |= (1 << i); | ||
301 | + new_idr &= ~(1 << i); | ||
302 | + } | ||
303 | + /* | ||
304 | + * The only case left is for open-drain ODR 1 | ||
305 | + * with unactive pin without pull-up or pull-down : | ||
306 | + * the value is floating. | ||
307 | + */ | ||
308 | + /* input or analog mode with connected pin */ | ||
309 | + } else if (!(s->disconnected_pins & (1 << i))) { | ||
310 | + if (s->pins_connected_high & (1 << i)) { | ||
311 | + /* pin high */ | ||
312 | + new_idr_mask |= (1 << i); | ||
313 | + new_idr |= (1 << i); | ||
314 | + } else { | ||
315 | + /* pin low */ | ||
316 | + new_idr_mask |= (1 << i); | ||
317 | + new_idr &= ~(1 << i); | ||
318 | + } | ||
319 | + /* input or analog mode with disconnected pin */ | ||
320 | + } else { | ||
321 | + if (is_pull_up(s, i)) { | ||
322 | + /* pull-up */ | ||
323 | + new_idr_mask |= (1 << i); | ||
324 | + new_idr |= (1 << i); | ||
325 | + } else if (is_pull_down(s, i)) { | ||
326 | + /* pull-down */ | ||
327 | + new_idr_mask |= (1 << i); | ||
328 | + new_idr &= ~(1 << i); | ||
329 | + } | ||
330 | + /* | ||
331 | + * The only case left is for a disconnected pin | ||
332 | + * without pull-up or pull-down : | ||
333 | + * the value is floating. | ||
334 | + */ | ||
335 | + } | ||
336 | + } | ||
337 | + | ||
338 | + s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask); | ||
339 | + trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr); | ||
340 | + | ||
341 | + for (int i = 0; i < GPIO_NUM_PINS; i++) { | ||
342 | + if (new_idr_mask & (1 << i)) { | ||
343 | + new_pin_state = (new_idr & (1 << i)) > 0; | ||
344 | + old_pin_state = (old_idr & (1 << i)) > 0; | ||
345 | + if (new_pin_state > old_pin_state) { | ||
346 | + qemu_irq_raise(s->pin[i]); | ||
347 | + } else if (new_pin_state < old_pin_state) { | ||
348 | + qemu_irq_lower(s->pin[i]); | ||
349 | + } | ||
350 | + } | ||
351 | + } | ||
352 | +} | ||
353 | + | ||
354 | +/* | ||
355 | + * Return mask of pins that are both configured in output | ||
356 | + * mode and externally driven (except pins in open-drain | ||
357 | + * mode externally set to 0). | ||
358 | + */ | ||
359 | +static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s) | ||
360 | +{ | ||
361 | + uint32_t pins_to_disconnect = 0; | ||
362 | + for (int i = 0; i < GPIO_NUM_PINS; i++) { | ||
363 | + /* for each connected pin in output mode */ | ||
364 | + if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) { | ||
365 | + /* if either push-pull or high level */ | ||
366 | + if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) { | ||
367 | + pins_to_disconnect |= (1 << i); | ||
368 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
369 | + "Line %d can't be driven externally\n", | ||
370 | + i); | ||
371 | + } | ||
372 | + } | ||
373 | + } | ||
374 | + return pins_to_disconnect; | ||
375 | +} | ||
376 | + | ||
377 | +/* | ||
378 | + * Set field `disconnected_pins` and call `update_gpio_idr()` | ||
379 | + */ | ||
380 | +static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines) | ||
381 | +{ | ||
382 | + s->disconnected_pins |= lines; | ||
383 | + trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins, | ||
384 | + s->pins_connected_high); | ||
385 | + update_gpio_idr(s); | ||
386 | +} | ||
387 | + | ||
388 | +static void disconnected_pins_set(Object *obj, Visitor *v, | ||
389 | + const char *name, void *opaque, Error **errp) | ||
390 | +{ | ||
391 | + Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj); | ||
392 | + uint16_t value; | ||
393 | + if (!visit_type_uint16(v, name, &value, errp)) { | ||
394 | + return; | ||
395 | + } | ||
396 | + disconnect_gpio_pins(s, value); | ||
397 | +} | ||
398 | + | ||
399 | +static void disconnected_pins_get(Object *obj, Visitor *v, | ||
400 | + const char *name, void *opaque, Error **errp) | ||
401 | +{ | ||
402 | + visit_type_uint16(v, name, (uint16_t *)opaque, errp); | ||
403 | +} | ||
404 | + | ||
405 | +static void clock_freq_get(Object *obj, Visitor *v, | ||
406 | + const char *name, void *opaque, Error **errp) | ||
407 | +{ | ||
408 | + Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj); | ||
409 | + uint32_t clock_freq_hz = clock_get_hz(s->clk); | ||
410 | + visit_type_uint32(v, name, &clock_freq_hz, errp); | ||
411 | +} | ||
412 | + | ||
413 | +static void stm32l4x5_gpio_write(void *opaque, hwaddr addr, | ||
414 | + uint64_t val64, unsigned int size) | ||
415 | +{ | ||
416 | + Stm32l4x5GpioState *s = opaque; | ||
417 | + | ||
418 | + uint32_t value = val64; | ||
419 | + trace_stm32l4x5_gpio_write(s->name, addr, val64); | ||
420 | + | ||
421 | + switch (addr) { | ||
422 | + case GPIO_MODER: | ||
423 | + s->moder = value; | ||
424 | + disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s)); | ||
425 | + qemu_log_mask(LOG_UNIMP, | ||
426 | + "%s: Analog and AF modes aren't supported\n\ | ||
427 | + Analog and AF mode behave like input mode\n", | ||
428 | + __func__); | ||
429 | + return; | ||
430 | + case GPIO_OTYPER: | ||
431 | + s->otyper = value & ~RESERVED_BITS_MASK; | ||
432 | + disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s)); | ||
433 | + return; | ||
434 | + case GPIO_OSPEEDR: | ||
435 | + qemu_log_mask(LOG_UNIMP, | ||
436 | + "%s: Changing I/O output speed isn't supported\n\ | ||
437 | + I/O speed is already maximal\n", | ||
438 | + __func__); | ||
439 | + s->ospeedr = value; | ||
440 | + return; | ||
441 | + case GPIO_PUPDR: | ||
442 | + s->pupdr = value; | ||
443 | + update_gpio_idr(s); | ||
444 | + return; | ||
445 | + case GPIO_IDR: | ||
446 | + qemu_log_mask(LOG_UNIMP, | ||
447 | + "%s: GPIO->IDR is read-only\n", | ||
448 | + __func__); | ||
449 | + return; | ||
450 | + case GPIO_ODR: | ||
451 | + s->odr = value & ~RESERVED_BITS_MASK; | ||
452 | + update_gpio_idr(s); | ||
453 | + return; | ||
454 | + case GPIO_BSRR: { | ||
455 | + uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS; | ||
456 | + uint32_t bits_to_set = value & ~RESERVED_BITS_MASK; | ||
457 | + /* If both BSx and BRx are set, BSx has priority.*/ | ||
458 | + s->odr &= ~bits_to_reset; | ||
459 | + s->odr |= bits_to_set; | ||
460 | + update_gpio_idr(s); | ||
461 | + return; | ||
462 | + } | ||
463 | + case GPIO_LCKR: | ||
464 | + qemu_log_mask(LOG_UNIMP, | ||
465 | + "%s: Locking port bits configuration isn't supported\n", | ||
466 | + __func__); | ||
467 | + s->lckr = value & ~RESERVED_BITS_MASK; | ||
468 | + return; | ||
469 | + case GPIO_AFRL: | ||
470 | + qemu_log_mask(LOG_UNIMP, | ||
471 | + "%s: Alternate functions aren't supported\n", | ||
472 | + __func__); | ||
473 | + s->afrl = value; | ||
474 | + return; | ||
475 | + case GPIO_AFRH: | ||
476 | + qemu_log_mask(LOG_UNIMP, | ||
477 | + "%s: Alternate functions aren't supported\n", | ||
478 | + __func__); | ||
479 | + s->afrh = value; | ||
480 | + return; | ||
481 | + case GPIO_BRR: { | ||
482 | + uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK; | ||
483 | + s->odr &= ~bits_to_reset; | ||
484 | + update_gpio_idr(s); | ||
485 | + return; | ||
486 | + } | ||
487 | + case GPIO_ASCR: | ||
488 | + qemu_log_mask(LOG_UNIMP, | ||
489 | + "%s: ADC function isn't supported\n", | ||
490 | + __func__); | ||
491 | + s->ascr = value & ~RESERVED_BITS_MASK; | ||
492 | + return; | ||
148 | + default: | 493 | + default: |
149 | + qemu_log_mask(LOG_GUEST_ERROR, | 494 | + qemu_log_mask(LOG_GUEST_ERROR, |
150 | + "MPS2 FPGAIO read: bad offset %x\n", (int) offset); | 495 | + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); |
151 | + r = 0; | 496 | + } |
152 | + break; | 497 | +} |
153 | + } | 498 | + |
154 | + | 499 | +static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr, |
155 | + trace_mps2_fpgaio_read(offset, r, size); | 500 | + unsigned int size) |
156 | + return r; | 501 | +{ |
157 | +} | 502 | + Stm32l4x5GpioState *s = opaque; |
158 | + | 503 | + |
159 | +static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, | 504 | + trace_stm32l4x5_gpio_read(s->name, addr); |
160 | + unsigned size) | 505 | + |
161 | +{ | 506 | + switch (addr) { |
162 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | 507 | + case GPIO_MODER: |
163 | + | 508 | + return s->moder; |
164 | + trace_mps2_fpgaio_write(offset, value, size); | 509 | + case GPIO_OTYPER: |
165 | + | 510 | + return s->otyper; |
166 | + switch (offset) { | 511 | + case GPIO_OSPEEDR: |
167 | + case A_LED0: | 512 | + return s->ospeedr; |
168 | + /* LED bits [1:0] control board LEDs. We don't currently have | 513 | + case GPIO_PUPDR: |
169 | + * a mechanism for displaying this graphically, so use a trace event. | 514 | + return s->pupdr; |
170 | + */ | 515 | + case GPIO_IDR: |
171 | + trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', | 516 | + return s->idr; |
172 | + value & 0x01 ? '*' : '.'); | 517 | + case GPIO_ODR: |
173 | + s->led0 = value & 0x3; | 518 | + return s->odr; |
174 | + break; | 519 | + case GPIO_BSRR: |
175 | + case A_PRESCALE: | 520 | + return 0; |
176 | + s->prescale = value; | 521 | + case GPIO_LCKR: |
177 | + break; | 522 | + return s->lckr; |
178 | + case A_MISC: | 523 | + case GPIO_AFRL: |
179 | + /* These are control bits for some of the other devices on the | 524 | + return s->afrl; |
180 | + * board (SPI, CLCD, etc). We don't implement that yet, so just | 525 | + case GPIO_AFRH: |
181 | + * make the bits read as written. | 526 | + return s->afrh; |
182 | + */ | 527 | + case GPIO_BRR: |
183 | + qemu_log_mask(LOG_UNIMP, | 528 | + return 0; |
184 | + "MPS2 FPGAIO: MISC control bits unimplemented\n"); | 529 | + case GPIO_ASCR: |
185 | + s->misc = value; | 530 | + return s->ascr; |
186 | + break; | ||
187 | + default: | 531 | + default: |
188 | + qemu_log_mask(LOG_GUEST_ERROR, | 532 | + qemu_log_mask(LOG_GUEST_ERROR, |
189 | + "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); | 533 | + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); |
190 | + break; | 534 | + return 0; |
191 | + } | 535 | + } |
192 | +} | 536 | +} |
193 | + | 537 | + |
194 | +static const MemoryRegionOps mps2_fpgaio_ops = { | 538 | +static const MemoryRegionOps stm32l4x5_gpio_ops = { |
195 | + .read = mps2_fpgaio_read, | 539 | + .read = stm32l4x5_gpio_read, |
196 | + .write = mps2_fpgaio_write, | 540 | + .write = stm32l4x5_gpio_write, |
197 | + .endianness = DEVICE_LITTLE_ENDIAN, | 541 | + .endianness = DEVICE_NATIVE_ENDIAN, |
542 | + .impl = { | ||
543 | + .min_access_size = 4, | ||
544 | + .max_access_size = 4, | ||
545 | + .unaligned = false, | ||
546 | + }, | ||
547 | + .valid = { | ||
548 | + .min_access_size = 4, | ||
549 | + .max_access_size = 4, | ||
550 | + .unaligned = false, | ||
551 | + }, | ||
198 | +}; | 552 | +}; |
199 | + | 553 | + |
200 | +static void mps2_fpgaio_reset(DeviceState *dev) | 554 | +static void stm32l4x5_gpio_init(Object *obj) |
201 | +{ | 555 | +{ |
202 | + MPS2FPGAIO *s = MPS2_FPGAIO(dev); | 556 | + Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj); |
203 | + | 557 | + |
204 | + trace_mps2_fpgaio_reset(); | 558 | + memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s, |
205 | + s->led0 = 0; | 559 | + TYPE_STM32L4X5_GPIO, 0x400); |
206 | + s->prescale = 0; | 560 | + |
207 | + s->misc = 0; | 561 | + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); |
208 | +} | 562 | + |
209 | + | 563 | + qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS); |
210 | +static void mps2_fpgaio_init(Object *obj) | 564 | + qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS); |
211 | +{ | 565 | + |
212 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 566 | + s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); |
213 | + MPS2FPGAIO *s = MPS2_FPGAIO(obj); | 567 | + |
214 | + | 568 | + object_property_add(obj, "disconnected-pins", "uint16", |
215 | + memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, | 569 | + disconnected_pins_get, disconnected_pins_set, |
216 | + "mps2-fpgaio", 0x1000); | 570 | + NULL, &s->disconnected_pins); |
217 | + sysbus_init_mmio(sbd, &s->iomem); | 571 | + object_property_add(obj, "clock-freq-hz", "uint32", |
218 | +} | 572 | + clock_freq_get, NULL, NULL, NULL); |
219 | + | 573 | +} |
220 | +static const VMStateDescription mps2_fpgaio_vmstate = { | 574 | + |
221 | + .name = "mps2-fpgaio", | 575 | +static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp) |
576 | +{ | ||
577 | + Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev); | ||
578 | + if (!clock_has_source(s->clk)) { | ||
579 | + error_setg(errp, "GPIO: clk input must be connected"); | ||
580 | + return; | ||
581 | + } | ||
582 | +} | ||
583 | + | ||
584 | +static const VMStateDescription vmstate_stm32l4x5_gpio = { | ||
585 | + .name = TYPE_STM32L4X5_GPIO, | ||
222 | + .version_id = 1, | 586 | + .version_id = 1, |
223 | + .minimum_version_id = 1, | 587 | + .minimum_version_id = 1, |
224 | + .fields = (VMStateField[]) { | 588 | + .fields = (VMStateField[]){ |
225 | + VMSTATE_UINT32(led0, MPS2FPGAIO), | 589 | + VMSTATE_UINT32(moder, Stm32l4x5GpioState), |
226 | + VMSTATE_UINT32(prescale, MPS2FPGAIO), | 590 | + VMSTATE_UINT32(otyper, Stm32l4x5GpioState), |
227 | + VMSTATE_UINT32(misc, MPS2FPGAIO), | 591 | + VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState), |
592 | + VMSTATE_UINT32(pupdr, Stm32l4x5GpioState), | ||
593 | + VMSTATE_UINT32(idr, Stm32l4x5GpioState), | ||
594 | + VMSTATE_UINT32(odr, Stm32l4x5GpioState), | ||
595 | + VMSTATE_UINT32(lckr, Stm32l4x5GpioState), | ||
596 | + VMSTATE_UINT32(afrl, Stm32l4x5GpioState), | ||
597 | + VMSTATE_UINT32(afrh, Stm32l4x5GpioState), | ||
598 | + VMSTATE_UINT32(ascr, Stm32l4x5GpioState), | ||
599 | + VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState), | ||
600 | + VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState), | ||
228 | + VMSTATE_END_OF_LIST() | 601 | + VMSTATE_END_OF_LIST() |
229 | + } | 602 | + } |
230 | +}; | 603 | +}; |
231 | + | 604 | + |
232 | +static Property mps2_fpgaio_properties[] = { | 605 | +static Property stm32l4x5_gpio_properties[] = { |
233 | + /* Frequency of the prescale counter */ | 606 | + DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name), |
234 | + DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), | 607 | + DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0), |
608 | + DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0), | ||
609 | + DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0), | ||
235 | + DEFINE_PROP_END_OF_LIST(), | 610 | + DEFINE_PROP_END_OF_LIST(), |
236 | +}; | 611 | +}; |
237 | + | 612 | + |
238 | +static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) | 613 | +static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data) |
239 | +{ | 614 | +{ |
240 | + DeviceClass *dc = DEVICE_CLASS(klass); | 615 | + DeviceClass *dc = DEVICE_CLASS(klass); |
241 | + | 616 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
242 | + dc->vmsd = &mps2_fpgaio_vmstate; | 617 | + |
243 | + dc->reset = mps2_fpgaio_reset; | 618 | + device_class_set_props(dc, stm32l4x5_gpio_properties); |
244 | + dc->props = mps2_fpgaio_properties; | 619 | + dc->vmsd = &vmstate_stm32l4x5_gpio; |
245 | +} | 620 | + dc->realize = stm32l4x5_gpio_realize; |
246 | + | 621 | + rc->phases.hold = stm32l4x5_gpio_reset_hold; |
247 | +static const TypeInfo mps2_fpgaio_info = { | 622 | +} |
248 | + .name = TYPE_MPS2_FPGAIO, | 623 | + |
249 | + .parent = TYPE_SYS_BUS_DEVICE, | 624 | +static const TypeInfo stm32l4x5_gpio_types[] = { |
250 | + .instance_size = sizeof(MPS2FPGAIO), | 625 | + { |
251 | + .instance_init = mps2_fpgaio_init, | 626 | + .name = TYPE_STM32L4X5_GPIO, |
252 | + .class_init = mps2_fpgaio_class_init, | 627 | + .parent = TYPE_SYS_BUS_DEVICE, |
628 | + .instance_size = sizeof(Stm32l4x5GpioState), | ||
629 | + .instance_init = stm32l4x5_gpio_init, | ||
630 | + .class_init = stm32l4x5_gpio_class_init, | ||
631 | + }, | ||
253 | +}; | 632 | +}; |
254 | + | 633 | + |
255 | +static void mps2_fpgaio_register_types(void) | 634 | +DEFINE_TYPES(stm32l4x5_gpio_types) |
256 | +{ | 635 | diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig |
257 | + type_register_static(&mps2_fpgaio_info); | ||
258 | +} | ||
259 | + | ||
260 | +type_init(mps2_fpgaio_register_types); | ||
261 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
262 | index XXXXXXX..XXXXXXX 100644 | 636 | index XXXXXXX..XXXXXXX 100644 |
263 | --- a/default-configs/arm-softmmu.mak | 637 | --- a/hw/gpio/Kconfig |
264 | +++ b/default-configs/arm-softmmu.mak | 638 | +++ b/hw/gpio/Kconfig |
265 | @@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y | 639 | @@ -XXX,XX +XXX,XX @@ config GPIO_PWR |
266 | CONFIG_CMSDK_APB_TIMER=y | 640 | |
267 | CONFIG_CMSDK_APB_UART=y | 641 | config SIFIVE_GPIO |
268 | 642 | bool | |
269 | +CONFIG_MPS2_FPGAIO=y | 643 | + |
270 | CONFIG_MPS2_SCC=y | 644 | +config STM32L4X5_GPIO |
271 | 645 | + bool | |
272 | CONFIG_VERSATILE_PCI=y | 646 | diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build |
273 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
274 | index XXXXXXX..XXXXXXX 100644 | 647 | index XXXXXXX..XXXXXXX 100644 |
275 | --- a/hw/misc/trace-events | 648 | --- a/hw/gpio/meson.build |
276 | +++ b/hw/misc/trace-events | 649 | +++ b/hw/gpio/meson.build |
277 | @@ -XXX,XX +XXX,XX @@ mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, | 650 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( |
278 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 | 651 | 'bcm2835_gpio.c', |
279 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 | 652 | 'bcm2838_gpio.c' |
280 | 653 | )) | |
281 | +# hw/misc/mps2_fpgaio.c | 654 | +system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c')) |
282 | +mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | 655 | system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) |
283 | +mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | 656 | system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) |
284 | +mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" | 657 | diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events |
285 | +mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c" | 658 | index XXXXXXX..XXXXXXX 100644 |
286 | + | 659 | --- a/hw/gpio/trace-events |
287 | # hw/misc/msf2-sysreg.c | 660 | +++ b/hw/gpio/trace-events |
288 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 | 661 | @@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val |
289 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32 | 662 | # aspeed_gpio.c |
663 | aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 | ||
664 | aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 | ||
665 | + | ||
666 | +# stm32l4x5_gpio.c | ||
667 | +stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " " | ||
668 | +stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | ||
669 | +stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x" | ||
670 | +stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x" | ||
290 | -- | 671 | -- |
291 | 2.16.2 | 672 | 2.34.1 |
292 | 673 | ||
293 | 674 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
4 | Message-id: 20180228193125.20577-15-richard.henderson@linaro.org | 4 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
6 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 10 | include/hw/arm/stm32l4x5_soc.h | 2 + |
9 | 1 file changed, 61 insertions(+) | 11 | include/hw/gpio/stm32l4x5_gpio.h | 1 + |
10 | 12 | include/hw/misc/stm32l4x5_syscfg.h | 3 +- | |
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++------- |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | hw/misc/stm32l4x5_syscfg.c | 1 + |
13 | --- a/target/arm/translate.c | 15 | hw/arm/Kconfig | 3 +- |
14 | +++ b/target/arm/translate.c | 16 | 6 files changed, 63 insertions(+), 18 deletions(-) |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 17 | |
16 | return 0; | 18 | diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h |
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/arm/stm32l4x5_soc.h | ||
21 | +++ b/include/hw/arm/stm32l4x5_soc.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | #include "hw/misc/stm32l4x5_syscfg.h" | ||
24 | #include "hw/misc/stm32l4x5_exti.h" | ||
25 | #include "hw/misc/stm32l4x5_rcc.h" | ||
26 | +#include "hw/gpio/stm32l4x5_gpio.h" | ||
27 | #include "qom/object.h" | ||
28 | |||
29 | #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" | ||
30 | @@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState { | ||
31 | OrIRQState exti_or_gates[NUM_EXTI_OR_GATES]; | ||
32 | Stm32l4x5SyscfgState syscfg; | ||
33 | Stm32l4x5RccState rcc; | ||
34 | + Stm32l4x5GpioState gpio[NUM_GPIOS]; | ||
35 | |||
36 | MemoryRegion sram1; | ||
37 | MemoryRegion sram2; | ||
38 | diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/include/hw/gpio/stm32l4x5_gpio.h | ||
41 | +++ b/include/hw/gpio/stm32l4x5_gpio.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio" | ||
44 | OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO) | ||
45 | |||
46 | +#define NUM_GPIOS 8 | ||
47 | #define GPIO_NUM_PINS 16 | ||
48 | |||
49 | struct Stm32l4x5GpioState { | ||
50 | diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/include/hw/misc/stm32l4x5_syscfg.h | ||
53 | +++ b/include/hw/misc/stm32l4x5_syscfg.h | ||
54 | @@ -XXX,XX +XXX,XX @@ | ||
55 | |||
56 | #include "hw/sysbus.h" | ||
57 | #include "qom/object.h" | ||
58 | +#include "hw/gpio/stm32l4x5_gpio.h" | ||
59 | |||
60 | #define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg" | ||
61 | OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG) | ||
62 | |||
63 | -#define NUM_GPIOS 8 | ||
64 | -#define GPIO_NUM_PINS 16 | ||
65 | #define SYSCFG_NUM_EXTICR 4 | ||
66 | |||
67 | struct Stm32l4x5SyscfgState { | ||
68 | diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/arm/stm32l4x5_soc.c | ||
71 | +++ b/hw/arm/stm32l4x5_soc.c | ||
72 | @@ -XXX,XX +XXX,XX @@ | ||
73 | #include "sysemu/sysemu.h" | ||
74 | #include "hw/or-irq.h" | ||
75 | #include "hw/arm/stm32l4x5_soc.h" | ||
76 | +#include "hw/gpio/stm32l4x5_gpio.h" | ||
77 | #include "hw/qdev-clock.h" | ||
78 | #include "hw/misc/unimp.h" | ||
79 | |||
80 | @@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = { | ||
81 | 16, 35, 36, 37, 38, | ||
82 | }; | ||
83 | |||
84 | +static const struct { | ||
85 | + uint32_t addr; | ||
86 | + uint32_t moder_reset; | ||
87 | + uint32_t ospeedr_reset; | ||
88 | + uint32_t pupdr_reset; | ||
89 | +} stm32l4x5_gpio_cfg[NUM_GPIOS] = { | ||
90 | + { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 }, | ||
91 | + { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 }, | ||
92 | + { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 }, | ||
93 | + { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 }, | ||
94 | + { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 }, | ||
95 | + { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 }, | ||
96 | + { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 }, | ||
97 | + { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 }, | ||
98 | +}; | ||
99 | + | ||
100 | static void stm32l4x5_soc_initfn(Object *obj) | ||
101 | { | ||
102 | Stm32l4x5SocState *s = STM32L4X5_SOC(obj); | ||
103 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj) | ||
104 | } | ||
105 | object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG); | ||
106 | object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC); | ||
107 | + | ||
108 | + for (unsigned i = 0; i < NUM_GPIOS; i++) { | ||
109 | + g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i); | ||
110 | + object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO); | ||
111 | + } | ||
17 | } | 112 | } |
18 | 113 | ||
19 | +/* Advanced SIMD two registers and a scalar extension. | 114 | static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
20 | + * 31 24 23 22 20 16 12 11 10 9 8 3 0 | 115 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
21 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | 116 | Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc); |
22 | + * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | 117 | const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc); |
23 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | 118 | MemoryRegion *system_memory = get_system_memory(); |
24 | + * | 119 | - DeviceState *armv7m; |
25 | + */ | 120 | + DeviceState *armv7m, *dev; |
26 | + | 121 | SysBusDevice *busdev; |
27 | +static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | 122 | + uint32_t pin_index; |
28 | +{ | 123 | |
29 | + int rd, rn, rm, rot, size, opr_sz; | 124 | if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash", |
30 | + TCGv_ptr fpst; | 125 | sc->flash_size, errp)) { |
31 | + bool q; | 126 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
32 | + | 127 | return; |
33 | + q = extract32(insn, 6, 1); | 128 | } |
34 | + VFP_DREG_D(rd, insn); | 129 | |
35 | + VFP_DREG_N(rn, insn); | 130 | + /* GPIOs */ |
36 | + VFP_DREG_M(rm, insn); | 131 | + for (unsigned i = 0; i < NUM_GPIOS; i++) { |
37 | + if ((rd | rn) & q) { | 132 | + g_autofree char *name = g_strdup_printf("%c", 'A' + i); |
38 | + return 1; | 133 | + dev = DEVICE(&s->gpio[i]); |
134 | + qdev_prop_set_string(dev, "name", name); | ||
135 | + qdev_prop_set_uint32(dev, "mode-reset", | ||
136 | + stm32l4x5_gpio_cfg[i].moder_reset); | ||
137 | + qdev_prop_set_uint32(dev, "ospeed-reset", | ||
138 | + stm32l4x5_gpio_cfg[i].ospeedr_reset); | ||
139 | + qdev_prop_set_uint32(dev, "pupd-reset", | ||
140 | + stm32l4x5_gpio_cfg[i].pupdr_reset); | ||
141 | + busdev = SYS_BUS_DEVICE(&s->gpio[i]); | ||
142 | + g_free(name); | ||
143 | + name = g_strdup_printf("gpio%c-out", 'a' + i); | ||
144 | + qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk", | ||
145 | + qdev_get_clock_out(DEVICE(&(s->rcc)), name)); | ||
146 | + if (!sysbus_realize(busdev, errp)) { | ||
147 | + return; | ||
148 | + } | ||
149 | + sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr); | ||
39 | + } | 150 | + } |
40 | + | 151 | + |
41 | + if ((insn & 0xff000f10) == 0xfe000800) { | 152 | /* System configuration controller */ |
42 | + /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ | 153 | busdev = SYS_BUS_DEVICE(&s->syscfg); |
43 | + rot = extract32(insn, 20, 2); | 154 | if (!sysbus_realize(busdev, errp)) { |
44 | + size = extract32(insn, 23, 1); | 155 | return; |
45 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | 156 | } |
46 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | 157 | sysbus_mmio_map(busdev, 0, SYSCFG_ADDR); |
47 | + return 1; | 158 | - /* |
159 | - * TODO: when the GPIO device is implemented, connect it | ||
160 | - * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and | ||
161 | - * GPIO_NUM_PINS. | ||
162 | - */ | ||
163 | + | ||
164 | + for (unsigned i = 0; i < NUM_GPIOS; i++) { | ||
165 | + for (unsigned j = 0; j < GPIO_NUM_PINS; j++) { | ||
166 | + pin_index = GPIO_NUM_PINS * i + j; | ||
167 | + qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j, | ||
168 | + qdev_get_gpio_in(DEVICE(&s->syscfg), | ||
169 | + pin_index)); | ||
48 | + } | 170 | + } |
49 | + } else { | ||
50 | + return 1; | ||
51 | + } | 171 | + } |
52 | + | 172 | |
53 | + if (s->fp_excp_el) { | 173 | /* EXTI device */ |
54 | + gen_exception_insn(s, 4, EXCP_UDEF, | 174 | busdev = SYS_BUS_DEVICE(&s->exti); |
55 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | 175 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
56 | + return 0; | 176 | } |
57 | + } | 177 | } |
58 | + if (!s->vfp_enabled) { | 178 | |
59 | + return 1; | 179 | - for (unsigned i = 0; i < 16; i++) { |
60 | + } | 180 | + for (unsigned i = 0; i < GPIO_NUM_PINS; i++) { |
61 | + | 181 | qdev_connect_gpio_out(DEVICE(&s->syscfg), i, |
62 | + opr_sz = (1 + q) * 8; | 182 | qdev_get_gpio_in(DEVICE(&s->exti), i)); |
63 | + fpst = get_fpstatus_ptr(1); | 183 | } |
64 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | 184 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
65 | + vfp_reg_offset(1, rn), | 185 | /* RESERVED: 0x40024400, 0x7FDBC00 */ |
66 | + vfp_reg_offset(1, rm), fpst, | 186 | |
67 | + opr_sz, opr_sz, rot, | 187 | /* AHB2 BUS */ |
68 | + size ? gen_helper_gvec_fcmlas_idx | 188 | - create_unimplemented_device("GPIOA", 0x48000000, 0x400); |
69 | + : gen_helper_gvec_fcmlah_idx); | 189 | - create_unimplemented_device("GPIOB", 0x48000400, 0x400); |
70 | + tcg_temp_free_ptr(fpst); | 190 | - create_unimplemented_device("GPIOC", 0x48000800, 0x400); |
71 | + return 0; | 191 | - create_unimplemented_device("GPIOD", 0x48000C00, 0x400); |
72 | +} | 192 | - create_unimplemented_device("GPIOE", 0x48001000, 0x400); |
73 | + | 193 | - create_unimplemented_device("GPIOF", 0x48001400, 0x400); |
74 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 194 | - create_unimplemented_device("GPIOG", 0x48001800, 0x400); |
75 | { | 195 | - create_unimplemented_device("GPIOH", 0x48001C00, 0x400); |
76 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | 196 | /* RESERVED: 0x48002000, 0x7FDBC00 */ |
77 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 197 | create_unimplemented_device("OTG_FS", 0x50000000, 0x40000); |
78 | goto illegal_op; | 198 | create_unimplemented_device("ADC", 0x50040000, 0x400); |
79 | } | 199 | diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c |
80 | return; | 200 | index XXXXXXX..XXXXXXX 100644 |
81 | + } else if ((insn & 0x0f000a00) == 0x0e000800 | 201 | --- a/hw/misc/stm32l4x5_syscfg.c |
82 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 202 | +++ b/hw/misc/stm32l4x5_syscfg.c |
83 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | 203 | @@ -XXX,XX +XXX,XX @@ |
84 | + goto illegal_op; | 204 | #include "hw/irq.h" |
85 | + } | 205 | #include "migration/vmstate.h" |
86 | + return; | 206 | #include "hw/misc/stm32l4x5_syscfg.h" |
87 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | 207 | +#include "hw/gpio/stm32l4x5_gpio.h" |
88 | /* Coprocessor double register transfer. */ | 208 | |
89 | ARCH(5TE); | 209 | #define SYSCFG_MEMRMP 0x00 |
210 | #define SYSCFG_CFGR1 0x04 | ||
211 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/hw/arm/Kconfig | ||
214 | +++ b/hw/arm/Kconfig | ||
215 | @@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC | ||
216 | bool | ||
217 | select ARM_V7M | ||
218 | select OR_IRQ | ||
219 | - select STM32L4X5_SYSCFG | ||
220 | select STM32L4X5_EXTI | ||
221 | + select STM32L4X5_SYSCFG | ||
222 | select STM32L4X5_RCC | ||
223 | + select STM32L4X5_GPIO | ||
224 | |||
225 | config XLNX_ZYNQMP_ARM | ||
226 | bool | ||
90 | -- | 227 | -- |
91 | 2.16.2 | 228 | 2.34.1 |
92 | 229 | ||
93 | 230 | diff view generated by jsdifflib |
1 | The Arm IoT Kit includes a "security controller" which is largely a | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | collection of registers for controlling the PPCs and other bits of | ||
3 | glue in the system. This commit provides the initial skeleton of the | ||
4 | device, implementing just the ID registers, and a couple of read-only | ||
5 | read-as-zero registers. | ||
6 | 2 | ||
3 | The testcase contains : | ||
4 | - `test_idr_reset_value()` : | ||
5 | Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR. | ||
6 | - `test_gpio_output_mode()` : | ||
7 | Checks that writing a bit in register ODR results in the corresponding | ||
8 | pin rising or lowering, if this pin is configured in output mode. | ||
9 | - `test_gpio_input_mode()` : | ||
10 | Checks that a input pin set high or low externally results | ||
11 | in the pin rising and lowering. | ||
12 | - `test_pull_up_pull_down()` : | ||
13 | Checks that a floating pin in pull-up/down mode is actually high/down. | ||
14 | - `test_push_pull()` : | ||
15 | Checks that a pin set externally is disconnected when configured in | ||
16 | push-pull output mode, and can't be set externally while in this mode. | ||
17 | - `test_open_drain()` : | ||
18 | Checks that a pin set externally high is disconnected when configured | ||
19 | in open-drain output mode, and can't be set high while in this mode. | ||
20 | - `test_bsrr_brr()` : | ||
21 | Checks that writing to BSRR and BRR has the desired result in ODR. | ||
22 | - `test_clock_enable()` : | ||
23 | Checks that GPIO clock is at the right frequency after enabling it. | ||
24 | |||
25 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
26 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
27 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | ||
28 | Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-16-peter.maydell@linaro.org | ||
10 | --- | 30 | --- |
11 | hw/misc/Makefile.objs | 1 + | 31 | tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++ |
12 | include/hw/misc/iotkit-secctl.h | 39 ++++ | 32 | tests/qtest/meson.build | 3 +- |
13 | hw/misc/iotkit-secctl.c | 448 ++++++++++++++++++++++++++++++++++++++++ | 33 | 2 files changed, 553 insertions(+), 1 deletion(-) |
14 | default-configs/arm-softmmu.mak | 1 + | 34 | create mode 100644 tests/qtest/stm32l4x5_gpio-test.c |
15 | hw/misc/trace-events | 7 + | ||
16 | 5 files changed, 496 insertions(+) | ||
17 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
18 | create mode 100644 hw/misc/iotkit-secctl.c | ||
19 | 35 | ||
20 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 36 | diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c |
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/misc/Makefile.objs | ||
23 | +++ b/hw/misc/Makefile.objs | ||
24 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | ||
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | ||
26 | |||
27 | obj-$(CONFIG_TZ_PPC) += tz-ppc.o | ||
28 | +obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o | ||
29 | |||
30 | obj-$(CONFIG_PVPANIC) += pvpanic.o | ||
31 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | ||
32 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
33 | new file mode 100644 | 37 | new file mode 100644 |
34 | index XXXXXXX..XXXXXXX | 38 | index XXXXXXX..XXXXXXX |
35 | --- /dev/null | 39 | --- /dev/null |
36 | +++ b/include/hw/misc/iotkit-secctl.h | 40 | +++ b/tests/qtest/stm32l4x5_gpio-test.c |
37 | @@ -XXX,XX +XXX,XX @@ | 41 | @@ -XXX,XX +XXX,XX @@ |
38 | +/* | 42 | +/* |
39 | + * ARM IoT Kit security controller | 43 | + * QTest testcase for STM32L4x5_GPIO |
40 | + * | 44 | + * |
41 | + * Copyright (c) 2018 Linaro Limited | 45 | + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
42 | + * Written by Peter Maydell | 46 | + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> |
43 | + * | 47 | + * |
44 | + * This program is free software; you can redistribute it and/or modify | 48 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
45 | + * it under the terms of the GNU General Public License version 2 or | 49 | + * See the COPYING file in the top-level directory. |
46 | + * (at your option) any later version. | ||
47 | + */ | 50 | + */ |
48 | + | 51 | + |
49 | +/* This is a model of the security controller which is part of the | ||
50 | + * Arm IoT Kit and documented in | ||
51 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
52 | + * | ||
53 | + * QEMU interface: | ||
54 | + * + sysbus MMIO region 0 is the "secure privilege control block" registers | ||
55 | + * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
56 | + */ | ||
57 | + | ||
58 | +#ifndef IOTKIT_SECCTL_H | ||
59 | +#define IOTKIT_SECCTL_H | ||
60 | + | ||
61 | +#include "hw/sysbus.h" | ||
62 | + | ||
63 | +#define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
64 | +#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
65 | + | ||
66 | +typedef struct IoTKitSecCtl { | ||
67 | + /*< private >*/ | ||
68 | + SysBusDevice parent_obj; | ||
69 | + | ||
70 | + /*< public >*/ | ||
71 | + | ||
72 | + MemoryRegion s_regs; | ||
73 | + MemoryRegion ns_regs; | ||
74 | +} IoTKitSecCtl; | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
78 | new file mode 100644 | ||
79 | index XXXXXXX..XXXXXXX | ||
80 | --- /dev/null | ||
81 | +++ b/hw/misc/iotkit-secctl.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | ||
83 | +/* | ||
84 | + * Arm IoT Kit security controller | ||
85 | + * | ||
86 | + * Copyright (c) 2018 Linaro Limited | ||
87 | + * Written by Peter Maydell | ||
88 | + * | ||
89 | + * This program is free software; you can redistribute it and/or modify | ||
90 | + * it under the terms of the GNU General Public License version 2 or | ||
91 | + * (at your option) any later version. | ||
92 | + */ | ||
93 | + | ||
94 | +#include "qemu/osdep.h" | 52 | +#include "qemu/osdep.h" |
95 | +#include "qemu/log.h" | 53 | +#include "libqtest-single.h" |
96 | +#include "qapi/error.h" | 54 | + |
97 | +#include "trace.h" | 55 | +#define GPIO_BASE_ADDR 0x48000000 |
98 | +#include "hw/sysbus.h" | 56 | +#define GPIO_SIZE 0x400 |
99 | +#include "hw/registerfields.h" | 57 | +#define NUM_GPIOS 8 |
100 | +#include "hw/misc/iotkit-secctl.h" | 58 | +#define NUM_GPIO_PINS 16 |
101 | + | 59 | + |
102 | +/* Registers in the secure privilege control block */ | 60 | +#define GPIO_A 0x48000000 |
103 | +REG32(SECRESPCFG, 0x10) | 61 | +#define GPIO_B 0x48000400 |
104 | +REG32(NSCCFG, 0x14) | 62 | +#define GPIO_C 0x48000800 |
105 | +REG32(SECMPCINTSTATUS, 0x1c) | 63 | +#define GPIO_D 0x48000C00 |
106 | +REG32(SECPPCINTSTAT, 0x20) | 64 | +#define GPIO_E 0x48001000 |
107 | +REG32(SECPPCINTCLR, 0x24) | 65 | +#define GPIO_F 0x48001400 |
108 | +REG32(SECPPCINTEN, 0x28) | 66 | +#define GPIO_G 0x48001800 |
109 | +REG32(SECMSCINTSTAT, 0x30) | 67 | +#define GPIO_H 0x48001C00 |
110 | +REG32(SECMSCINTCLR, 0x34) | 68 | + |
111 | +REG32(SECMSCINTEN, 0x38) | 69 | +#define MODER 0x00 |
112 | +REG32(BRGINTSTAT, 0x40) | 70 | +#define OTYPER 0x04 |
113 | +REG32(BRGINTCLR, 0x44) | 71 | +#define PUPDR 0x0C |
114 | +REG32(BRGINTEN, 0x48) | 72 | +#define IDR 0x10 |
115 | +REG32(AHBNSPPC0, 0x50) | 73 | +#define ODR 0x14 |
116 | +REG32(AHBNSPPCEXP0, 0x60) | 74 | +#define BSRR 0x18 |
117 | +REG32(AHBNSPPCEXP1, 0x64) | 75 | +#define BRR 0x28 |
118 | +REG32(AHBNSPPCEXP2, 0x68) | 76 | + |
119 | +REG32(AHBNSPPCEXP3, 0x6c) | 77 | +#define MODER_INPUT 0 |
120 | +REG32(APBNSPPC0, 0x70) | 78 | +#define MODER_OUTPUT 1 |
121 | +REG32(APBNSPPC1, 0x74) | 79 | + |
122 | +REG32(APBNSPPCEXP0, 0x80) | 80 | +#define PUPDR_NONE 0 |
123 | +REG32(APBNSPPCEXP1, 0x84) | 81 | +#define PUPDR_PULLUP 1 |
124 | +REG32(APBNSPPCEXP2, 0x88) | 82 | +#define PUPDR_PULLDOWN 2 |
125 | +REG32(APBNSPPCEXP3, 0x8c) | 83 | + |
126 | +REG32(AHBSPPPC0, 0x90) | 84 | +#define OTYPER_PUSH_PULL 0 |
127 | +REG32(AHBSPPPCEXP0, 0xa0) | 85 | +#define OTYPER_OPEN_DRAIN 1 |
128 | +REG32(AHBSPPPCEXP1, 0xa4) | 86 | + |
129 | +REG32(AHBSPPPCEXP2, 0xa8) | 87 | +const uint32_t moder_reset[NUM_GPIOS] = { |
130 | +REG32(AHBSPPPCEXP3, 0xac) | 88 | + 0xABFFFFFF, |
131 | +REG32(APBSPPPC0, 0xb0) | 89 | + 0xFFFFFEBF, |
132 | +REG32(APBSPPPC1, 0xb4) | 90 | + 0xFFFFFFFF, |
133 | +REG32(APBSPPPCEXP0, 0xc0) | 91 | + 0xFFFFFFFF, |
134 | +REG32(APBSPPPCEXP1, 0xc4) | 92 | + 0xFFFFFFFF, |
135 | +REG32(APBSPPPCEXP2, 0xc8) | 93 | + 0xFFFFFFFF, |
136 | +REG32(APBSPPPCEXP3, 0xcc) | 94 | + 0xFFFFFFFF, |
137 | +REG32(NSMSCEXP, 0xd0) | 95 | + 0x0000000F |
138 | +REG32(PID4, 0xfd0) | ||
139 | +REG32(PID5, 0xfd4) | ||
140 | +REG32(PID6, 0xfd8) | ||
141 | +REG32(PID7, 0xfdc) | ||
142 | +REG32(PID0, 0xfe0) | ||
143 | +REG32(PID1, 0xfe4) | ||
144 | +REG32(PID2, 0xfe8) | ||
145 | +REG32(PID3, 0xfec) | ||
146 | +REG32(CID0, 0xff0) | ||
147 | +REG32(CID1, 0xff4) | ||
148 | +REG32(CID2, 0xff8) | ||
149 | +REG32(CID3, 0xffc) | ||
150 | + | ||
151 | +/* Registers in the non-secure privilege control block */ | ||
152 | +REG32(AHBNSPPPC0, 0x90) | ||
153 | +REG32(AHBNSPPPCEXP0, 0xa0) | ||
154 | +REG32(AHBNSPPPCEXP1, 0xa4) | ||
155 | +REG32(AHBNSPPPCEXP2, 0xa8) | ||
156 | +REG32(AHBNSPPPCEXP3, 0xac) | ||
157 | +REG32(APBNSPPPC0, 0xb0) | ||
158 | +REG32(APBNSPPPC1, 0xb4) | ||
159 | +REG32(APBNSPPPCEXP0, 0xc0) | ||
160 | +REG32(APBNSPPPCEXP1, 0xc4) | ||
161 | +REG32(APBNSPPPCEXP2, 0xc8) | ||
162 | +REG32(APBNSPPPCEXP3, 0xcc) | ||
163 | +/* PID and CID registers are also present in the NS block */ | ||
164 | + | ||
165 | +static const uint8_t iotkit_secctl_s_idregs[] = { | ||
166 | + 0x04, 0x00, 0x00, 0x00, | ||
167 | + 0x52, 0xb8, 0x0b, 0x00, | ||
168 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
169 | +}; | 96 | +}; |
170 | + | 97 | + |
171 | +static const uint8_t iotkit_secctl_ns_idregs[] = { | 98 | +const uint32_t pupdr_reset[NUM_GPIOS] = { |
172 | + 0x04, 0x00, 0x00, 0x00, | 99 | + 0x64000000, |
173 | + 0x53, 0xb8, 0x0b, 0x00, | 100 | + 0x00000100, |
174 | + 0x0d, 0xf0, 0x05, 0xb1, | 101 | + 0x00000000, |
102 | + 0x00000000, | ||
103 | + 0x00000000, | ||
104 | + 0x00000000, | ||
105 | + 0x00000000, | ||
106 | + 0x00000000 | ||
175 | +}; | 107 | +}; |
176 | + | 108 | + |
177 | +static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | 109 | +const uint32_t idr_reset[NUM_GPIOS] = { |
178 | + uint64_t *pdata, | 110 | + 0x0000A000, |
179 | + unsigned size, MemTxAttrs attrs) | 111 | + 0x00000010, |
180 | +{ | 112 | + 0x00000000, |
181 | + uint64_t r; | 113 | + 0x00000000, |
182 | + uint32_t offset = addr & ~0x3; | 114 | + 0x00000000, |
183 | + | 115 | + 0x00000000, |
116 | + 0x00000000, | ||
117 | + 0x00000000 | ||
118 | +}; | ||
119 | + | ||
120 | +static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) | ||
121 | +{ | ||
122 | + return readl(gpio + offset); | ||
123 | +} | ||
124 | + | ||
125 | +static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value) | ||
126 | +{ | ||
127 | + writel(gpio + offset, value); | ||
128 | +} | ||
129 | + | ||
130 | +static void gpio_set_bit(unsigned int gpio, unsigned int reg, | ||
131 | + unsigned int pin, uint32_t value) | ||
132 | +{ | ||
133 | + uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin); | ||
134 | + gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin); | ||
135 | +} | ||
136 | + | ||
137 | +static void gpio_set_2bits(unsigned int gpio, unsigned int reg, | ||
138 | + unsigned int pin, uint32_t value) | ||
139 | +{ | ||
140 | + uint32_t offset = 2 * pin; | ||
141 | + uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset); | ||
142 | + gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset); | ||
143 | +} | ||
144 | + | ||
145 | +static unsigned int get_gpio_id(uint32_t gpio_addr) | ||
146 | +{ | ||
147 | + return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE; | ||
148 | +} | ||
149 | + | ||
150 | +static void gpio_set_irq(unsigned int gpio, int num, int level) | ||
151 | +{ | ||
152 | + g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c", | ||
153 | + get_gpio_id(gpio) + 'a'); | ||
154 | + qtest_set_irq_in(global_qtest, name, NULL, num, level); | ||
155 | +} | ||
156 | + | ||
157 | +static void disconnect_all_pins(unsigned int gpio) | ||
158 | +{ | ||
159 | + g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c", | ||
160 | + get_gpio_id(gpio) + 'a'); | ||
161 | + QDict *r; | ||
162 | + | ||
163 | + r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': " | ||
164 | + "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }", | ||
165 | + path, 0xFFFF); | ||
166 | + g_assert_false(qdict_haskey(r, "error")); | ||
167 | + qobject_unref(r); | ||
168 | +} | ||
169 | + | ||
170 | +static uint32_t get_disconnected_pins(unsigned int gpio) | ||
171 | +{ | ||
172 | + g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c", | ||
173 | + get_gpio_id(gpio) + 'a'); | ||
174 | + uint32_t disconnected_pins = 0; | ||
175 | + QDict *r; | ||
176 | + | ||
177 | + r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':" | ||
178 | + " { 'path': %s, 'property': 'disconnected-pins'} }", path); | ||
179 | + g_assert_false(qdict_haskey(r, "error")); | ||
180 | + disconnected_pins = qdict_get_int(r, "return"); | ||
181 | + qobject_unref(r); | ||
182 | + return disconnected_pins; | ||
183 | +} | ||
184 | + | ||
185 | +static uint32_t reset(uint32_t gpio, unsigned int offset) | ||
186 | +{ | ||
184 | + switch (offset) { | 187 | + switch (offset) { |
185 | + case A_AHBNSPPC0: | 188 | + case MODER: |
186 | + case A_AHBSPPPC0: | 189 | + return moder_reset[get_gpio_id(gpio)]; |
187 | + r = 0; | 190 | + case PUPDR: |
188 | + break; | 191 | + return pupdr_reset[get_gpio_id(gpio)]; |
189 | + case A_SECRESPCFG: | 192 | + case IDR: |
190 | + case A_NSCCFG: | 193 | + return idr_reset[get_gpio_id(gpio)]; |
191 | + case A_SECMPCINTSTATUS: | ||
192 | + case A_SECPPCINTSTAT: | ||
193 | + case A_SECPPCINTEN: | ||
194 | + case A_SECMSCINTSTAT: | ||
195 | + case A_SECMSCINTEN: | ||
196 | + case A_BRGINTSTAT: | ||
197 | + case A_BRGINTEN: | ||
198 | + case A_AHBNSPPCEXP0: | ||
199 | + case A_AHBNSPPCEXP1: | ||
200 | + case A_AHBNSPPCEXP2: | ||
201 | + case A_AHBNSPPCEXP3: | ||
202 | + case A_APBNSPPC0: | ||
203 | + case A_APBNSPPC1: | ||
204 | + case A_APBNSPPCEXP0: | ||
205 | + case A_APBNSPPCEXP1: | ||
206 | + case A_APBNSPPCEXP2: | ||
207 | + case A_APBNSPPCEXP3: | ||
208 | + case A_AHBSPPPCEXP0: | ||
209 | + case A_AHBSPPPCEXP1: | ||
210 | + case A_AHBSPPPCEXP2: | ||
211 | + case A_AHBSPPPCEXP3: | ||
212 | + case A_APBSPPPC0: | ||
213 | + case A_APBSPPPC1: | ||
214 | + case A_APBSPPPCEXP0: | ||
215 | + case A_APBSPPPCEXP1: | ||
216 | + case A_APBSPPPCEXP2: | ||
217 | + case A_APBSPPPCEXP3: | ||
218 | + case A_NSMSCEXP: | ||
219 | + qemu_log_mask(LOG_UNIMP, | ||
220 | + "IoTKit SecCtl S block read: " | ||
221 | + "unimplemented offset 0x%x\n", offset); | ||
222 | + r = 0; | ||
223 | + break; | ||
224 | + case A_PID4: | ||
225 | + case A_PID5: | ||
226 | + case A_PID6: | ||
227 | + case A_PID7: | ||
228 | + case A_PID0: | ||
229 | + case A_PID1: | ||
230 | + case A_PID2: | ||
231 | + case A_PID3: | ||
232 | + case A_CID0: | ||
233 | + case A_CID1: | ||
234 | + case A_CID2: | ||
235 | + case A_CID3: | ||
236 | + r = iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; | ||
237 | + break; | ||
238 | + case A_SECPPCINTCLR: | ||
239 | + case A_SECMSCINTCLR: | ||
240 | + case A_BRGINTCLR: | ||
241 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
242 | + "IotKit SecCtl S block read: write-only offset 0x%x\n", | ||
243 | + offset); | ||
244 | + r = 0; | ||
245 | + break; | ||
246 | + default: | ||
247 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
248 | + "IotKit SecCtl S block read: bad offset 0x%x\n", offset); | ||
249 | + r = 0; | ||
250 | + break; | ||
251 | + } | 194 | + } |
252 | + | 195 | + return 0x0; |
253 | + if (size != 4) { | 196 | +} |
254 | + /* None of our registers are access-sensitive, so just pull the right | 197 | + |
255 | + * byte out of the word read result. | 198 | +static void system_reset(void) |
256 | + */ | 199 | +{ |
257 | + r = extract32(r, (addr & 3) * 8, size * 8); | 200 | + QDict *r; |
258 | + } | 201 | + r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}"); |
259 | + | 202 | + g_assert_false(qdict_haskey(r, "error")); |
260 | + trace_iotkit_secctl_s_read(offset, r, size); | 203 | + qobject_unref(r); |
261 | + *pdata = r; | 204 | +} |
262 | + return MEMTX_OK; | 205 | + |
263 | +} | 206 | +static void test_idr_reset_value(void) |
264 | + | 207 | +{ |
265 | +static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | 208 | + /* |
266 | + uint64_t value, | 209 | + * Checks that the values in MODER, OTYPER, PUPDR and ODR |
267 | + unsigned size, MemTxAttrs attrs) | 210 | + * after reset are correct, and that the value in IDR is |
268 | +{ | 211 | + * coherent. |
269 | + uint32_t offset = addr; | 212 | + * Since AF and analog modes aren't implemented, IDR reset |
270 | + | 213 | + * values aren't the same as with a real board. |
271 | + trace_iotkit_secctl_s_write(offset, value, size); | 214 | + * |
272 | + | 215 | + * Register IDR contains the actual values of all GPIO pins. |
273 | + if (size != 4) { | 216 | + * Its value depends on the pins' configuration |
274 | + /* Byte and halfword writes are ignored */ | 217 | + * (intput/output/analog : register MODER, push-pull/open-drain : |
275 | + qemu_log_mask(LOG_GUEST_ERROR, | 218 | + * register OTYPER, pull-up/pull-down/none : register PUPDR) |
276 | + "IotKit SecCtl S block write: bad size, ignored\n"); | 219 | + * and on the values stored in register ODR |
277 | + return MEMTX_OK; | 220 | + * (in case the pin is in output mode). |
278 | + } | 221 | + */ |
279 | + | 222 | + |
280 | + switch (offset) { | 223 | + gpio_writel(GPIO_A, MODER, 0xDEADBEEF); |
281 | + case A_SECRESPCFG: | 224 | + gpio_writel(GPIO_A, ODR, 0xDEADBEEF); |
282 | + case A_NSCCFG: | 225 | + gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF); |
283 | + case A_SECPPCINTCLR: | 226 | + gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF); |
284 | + case A_SECPPCINTEN: | 227 | + |
285 | + case A_SECMSCINTCLR: | 228 | + gpio_writel(GPIO_B, MODER, 0xDEADBEEF); |
286 | + case A_SECMSCINTEN: | 229 | + gpio_writel(GPIO_B, ODR, 0xDEADBEEF); |
287 | + case A_BRGINTCLR: | 230 | + gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF); |
288 | + case A_BRGINTEN: | 231 | + gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF); |
289 | + case A_AHBNSPPCEXP0: | 232 | + |
290 | + case A_AHBNSPPCEXP1: | 233 | + gpio_writel(GPIO_C, MODER, 0xDEADBEEF); |
291 | + case A_AHBNSPPCEXP2: | 234 | + gpio_writel(GPIO_C, ODR, 0xDEADBEEF); |
292 | + case A_AHBNSPPCEXP3: | 235 | + gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF); |
293 | + case A_APBNSPPC0: | 236 | + gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF); |
294 | + case A_APBNSPPC1: | 237 | + |
295 | + case A_APBNSPPCEXP0: | 238 | + gpio_writel(GPIO_H, MODER, 0xDEADBEEF); |
296 | + case A_APBNSPPCEXP1: | 239 | + gpio_writel(GPIO_H, ODR, 0xDEADBEEF); |
297 | + case A_APBNSPPCEXP2: | 240 | + gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF); |
298 | + case A_APBNSPPCEXP3: | 241 | + gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF); |
299 | + case A_AHBSPPPCEXP0: | 242 | + |
300 | + case A_AHBSPPPCEXP1: | 243 | + system_reset(); |
301 | + case A_AHBSPPPCEXP2: | 244 | + |
302 | + case A_AHBSPPPCEXP3: | 245 | + uint32_t moder = gpio_readl(GPIO_A, MODER); |
303 | + case A_APBSPPPC0: | 246 | + uint32_t odr = gpio_readl(GPIO_A, ODR); |
304 | + case A_APBSPPPC1: | 247 | + uint32_t otyper = gpio_readl(GPIO_A, OTYPER); |
305 | + case A_APBSPPPCEXP0: | 248 | + uint32_t pupdr = gpio_readl(GPIO_A, PUPDR); |
306 | + case A_APBSPPPCEXP1: | 249 | + uint32_t idr = gpio_readl(GPIO_A, IDR); |
307 | + case A_APBSPPPCEXP2: | 250 | + /* 15: AF, 14: AF, 13: AF, 12: Analog ... */ |
308 | + case A_APBSPPPCEXP3: | 251 | + /* here AF is the same as Analog and Input mode */ |
309 | + qemu_log_mask(LOG_UNIMP, | 252 | + g_assert_cmphex(moder, ==, reset(GPIO_A, MODER)); |
310 | + "IoTKit SecCtl S block write: " | 253 | + g_assert_cmphex(odr, ==, reset(GPIO_A, ODR)); |
311 | + "unimplemented offset 0x%x\n", offset); | 254 | + g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER)); |
312 | + break; | 255 | + /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */ |
313 | + case A_SECMPCINTSTATUS: | 256 | + g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR)); |
314 | + case A_SECPPCINTSTAT: | 257 | + /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */ |
315 | + case A_SECMSCINTSTAT: | 258 | + g_assert_cmphex(idr, ==, reset(GPIO_A, IDR)); |
316 | + case A_BRGINTSTAT: | 259 | + |
317 | + case A_AHBNSPPC0: | 260 | + moder = gpio_readl(GPIO_B, MODER); |
318 | + case A_AHBSPPPC0: | 261 | + odr = gpio_readl(GPIO_B, ODR); |
319 | + case A_NSMSCEXP: | 262 | + otyper = gpio_readl(GPIO_B, OTYPER); |
320 | + case A_PID4: | 263 | + pupdr = gpio_readl(GPIO_B, PUPDR); |
321 | + case A_PID5: | 264 | + idr = gpio_readl(GPIO_B, IDR); |
322 | + case A_PID6: | 265 | + /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */ |
323 | + case A_PID7: | 266 | + /* here AF is the same as Analog and Input mode */ |
324 | + case A_PID0: | 267 | + g_assert_cmphex(moder, ==, reset(GPIO_B, MODER)); |
325 | + case A_PID1: | 268 | + g_assert_cmphex(odr, ==, reset(GPIO_B, ODR)); |
326 | + case A_PID2: | 269 | + g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER)); |
327 | + case A_PID3: | 270 | + /* ... 5: neither, 4: pull-up, 3: neither ... */ |
328 | + case A_CID0: | 271 | + g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR)); |
329 | + case A_CID1: | 272 | + /* ... 5 : reset value, 4 : 1, 3 : reset value ... */ |
330 | + case A_CID2: | 273 | + g_assert_cmphex(idr, ==, reset(GPIO_B, IDR)); |
331 | + case A_CID3: | 274 | + |
332 | + qemu_log_mask(LOG_GUEST_ERROR, | 275 | + moder = gpio_readl(GPIO_C, MODER); |
333 | + "IoTKit SecCtl S block write: " | 276 | + odr = gpio_readl(GPIO_C, ODR); |
334 | + "read-only offset 0x%x\n", offset); | 277 | + otyper = gpio_readl(GPIO_C, OTYPER); |
335 | + break; | 278 | + pupdr = gpio_readl(GPIO_C, PUPDR); |
336 | + default: | 279 | + idr = gpio_readl(GPIO_C, IDR); |
337 | + qemu_log_mask(LOG_GUEST_ERROR, | 280 | + /* Analog, same as Input mode*/ |
338 | + "IotKit SecCtl S block write: bad offset 0x%x\n", | 281 | + g_assert_cmphex(moder, ==, reset(GPIO_C, MODER)); |
339 | + offset); | 282 | + g_assert_cmphex(odr, ==, reset(GPIO_C, ODR)); |
340 | + break; | 283 | + g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER)); |
341 | + } | 284 | + /* no pull-up or pull-down */ |
342 | + | 285 | + g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR)); |
343 | + return MEMTX_OK; | 286 | + /* reset value */ |
344 | +} | 287 | + g_assert_cmphex(idr, ==, reset(GPIO_C, IDR)); |
345 | + | 288 | + |
346 | +static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | 289 | + moder = gpio_readl(GPIO_H, MODER); |
347 | + uint64_t *pdata, | 290 | + odr = gpio_readl(GPIO_H, ODR); |
348 | + unsigned size, MemTxAttrs attrs) | 291 | + otyper = gpio_readl(GPIO_H, OTYPER); |
349 | +{ | 292 | + pupdr = gpio_readl(GPIO_H, PUPDR); |
350 | + uint64_t r; | 293 | + idr = gpio_readl(GPIO_H, IDR); |
351 | + uint32_t offset = addr & ~0x3; | 294 | + /* Analog, same as Input mode */ |
352 | + | 295 | + g_assert_cmphex(moder, ==, reset(GPIO_H, MODER)); |
353 | + switch (offset) { | 296 | + g_assert_cmphex(odr, ==, reset(GPIO_H, ODR)); |
354 | + case A_AHBNSPPPC0: | 297 | + g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER)); |
355 | + r = 0; | 298 | + /* no pull-up or pull-down */ |
356 | + break; | 299 | + g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR)); |
357 | + case A_AHBNSPPPCEXP0: | 300 | + /* reset value */ |
358 | + case A_AHBNSPPPCEXP1: | 301 | + g_assert_cmphex(idr, ==, reset(GPIO_H, IDR)); |
359 | + case A_AHBNSPPPCEXP2: | 302 | +} |
360 | + case A_AHBNSPPPCEXP3: | 303 | + |
361 | + case A_APBNSPPPC0: | 304 | +static void test_gpio_output_mode(const void *data) |
362 | + case A_APBNSPPPC1: | 305 | +{ |
363 | + case A_APBNSPPPCEXP0: | 306 | + /* |
364 | + case A_APBNSPPPCEXP1: | 307 | + * Checks that setting a bit in ODR sets the corresponding |
365 | + case A_APBNSPPPCEXP2: | 308 | + * GPIO line high : it should set the right bit in IDR |
366 | + case A_APBNSPPPCEXP3: | 309 | + * and send an irq to syscfg. |
367 | + qemu_log_mask(LOG_UNIMP, | 310 | + * Additionally, it checks that values written to ODR |
368 | + "IoTKit SecCtl NS block read: " | 311 | + * when not in output mode are stored and not discarded. |
369 | + "unimplemented offset 0x%x\n", offset); | 312 | + */ |
370 | + break; | 313 | + unsigned int pin = ((uint64_t)data) & 0xF; |
371 | + case A_PID4: | 314 | + uint32_t gpio = ((uint64_t)data) >> 32; |
372 | + case A_PID5: | 315 | + unsigned int gpio_id = get_gpio_id(gpio); |
373 | + case A_PID6: | 316 | + |
374 | + case A_PID7: | 317 | + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); |
375 | + case A_PID0: | 318 | + |
376 | + case A_PID1: | 319 | + /* Set a bit in ODR and check nothing happens */ |
377 | + case A_PID2: | 320 | + gpio_set_bit(gpio, ODR, pin, 1); |
378 | + case A_PID3: | 321 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR)); |
379 | + case A_CID0: | 322 | + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
380 | + case A_CID1: | 323 | + |
381 | + case A_CID2: | 324 | + /* Configure the relevant line as output and check the pin is high */ |
382 | + case A_CID3: | 325 | + gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT); |
383 | + r = iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; | 326 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin)); |
384 | + break; | 327 | + g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
385 | + default: | 328 | + |
386 | + qemu_log_mask(LOG_GUEST_ERROR, | 329 | + /* Reset the bit in ODR and check the pin is low */ |
387 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | 330 | + gpio_set_bit(gpio, ODR, pin, 0); |
388 | + offset); | 331 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); |
389 | + r = 0; | 332 | + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
390 | + break; | 333 | + |
391 | + } | 334 | + /* Clean the test */ |
392 | + | 335 | + gpio_writel(gpio, ODR, reset(gpio, ODR)); |
393 | + if (size != 4) { | 336 | + gpio_writel(gpio, MODER, reset(gpio, MODER)); |
394 | + /* None of our registers are access-sensitive, so just pull the right | 337 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR)); |
395 | + * byte out of the word read result. | 338 | + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
396 | + */ | 339 | +} |
397 | + r = extract32(r, (addr & 3) * 8, size * 8); | 340 | + |
398 | + } | 341 | +static void test_gpio_input_mode(const void *data) |
399 | + | 342 | +{ |
400 | + trace_iotkit_secctl_ns_read(offset, r, size); | 343 | + /* |
401 | + *pdata = r; | 344 | + * Test that setting a line high/low externally sets the |
402 | + return MEMTX_OK; | 345 | + * corresponding GPIO line high/low : it should set the |
403 | +} | 346 | + * right bit in IDR and send an irq to syscfg. |
404 | + | 347 | + */ |
405 | +static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | 348 | + unsigned int pin = ((uint64_t)data) & 0xF; |
406 | + uint64_t value, | 349 | + uint32_t gpio = ((uint64_t)data) >> 32; |
407 | + unsigned size, MemTxAttrs attrs) | 350 | + unsigned int gpio_id = get_gpio_id(gpio); |
408 | +{ | 351 | + |
409 | + uint32_t offset = addr; | 352 | + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); |
410 | + | 353 | + |
411 | + trace_iotkit_secctl_ns_write(offset, value, size); | 354 | + /* Configure a line as input, raise it, and check that the pin is high */ |
412 | + | 355 | + gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); |
413 | + if (size != 4) { | 356 | + gpio_set_irq(gpio, pin, 1); |
414 | + /* Byte and halfword writes are ignored */ | 357 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin)); |
415 | + qemu_log_mask(LOG_GUEST_ERROR, | 358 | + g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
416 | + "IotKit SecCtl NS block write: bad size, ignored\n"); | 359 | + |
417 | + return MEMTX_OK; | 360 | + /* Lower the line and check that the pin is low */ |
418 | + } | 361 | + gpio_set_irq(gpio, pin, 0); |
419 | + | 362 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); |
420 | + switch (offset) { | 363 | + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
421 | + case A_AHBNSPPPCEXP0: | 364 | + |
422 | + case A_AHBNSPPPCEXP1: | 365 | + /* Clean the test */ |
423 | + case A_AHBNSPPPCEXP2: | 366 | + gpio_writel(gpio, MODER, reset(gpio, MODER)); |
424 | + case A_AHBNSPPPCEXP3: | 367 | + disconnect_all_pins(gpio); |
425 | + case A_APBNSPPPC0: | 368 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR)); |
426 | + case A_APBNSPPPC1: | 369 | +} |
427 | + case A_APBNSPPPCEXP0: | 370 | + |
428 | + case A_APBNSPPPCEXP1: | 371 | +static void test_pull_up_pull_down(const void *data) |
429 | + case A_APBNSPPPCEXP2: | 372 | +{ |
430 | + case A_APBNSPPPCEXP3: | 373 | + /* |
431 | + qemu_log_mask(LOG_UNIMP, | 374 | + * Test that a floating pin with pull-up sets the pin |
432 | + "IoTKit SecCtl NS block write: " | 375 | + * high and vice-versa. |
433 | + "unimplemented offset 0x%x\n", offset); | 376 | + */ |
434 | + break; | 377 | + unsigned int pin = ((uint64_t)data) & 0xF; |
435 | + case A_AHBNSPPPC0: | 378 | + uint32_t gpio = ((uint64_t)data) >> 32; |
436 | + case A_PID4: | 379 | + unsigned int gpio_id = get_gpio_id(gpio); |
437 | + case A_PID5: | 380 | + |
438 | + case A_PID6: | 381 | + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); |
439 | + case A_PID7: | 382 | + |
440 | + case A_PID0: | 383 | + /* Configure a line as input with pull-up, check the line is set high */ |
441 | + case A_PID1: | 384 | + gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); |
442 | + case A_PID2: | 385 | + gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP); |
443 | + case A_PID3: | 386 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin)); |
444 | + case A_CID0: | 387 | + g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
445 | + case A_CID1: | 388 | + |
446 | + case A_CID2: | 389 | + /* Configure the line with pull-down, check the line is low */ |
447 | + case A_CID3: | 390 | + gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN); |
448 | + qemu_log_mask(LOG_GUEST_ERROR, | 391 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); |
449 | + "IoTKit SecCtl NS block write: " | 392 | + g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); |
450 | + "read-only offset 0x%x\n", offset); | 393 | + |
451 | + break; | 394 | + /* Clean the test */ |
452 | + default: | 395 | + gpio_writel(gpio, MODER, reset(gpio, MODER)); |
453 | + qemu_log_mask(LOG_GUEST_ERROR, | 396 | + gpio_writel(gpio, PUPDR, reset(gpio, PUPDR)); |
454 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | 397 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR)); |
455 | + offset); | 398 | +} |
456 | + break; | 399 | + |
457 | + } | 400 | +static void test_push_pull(const void *data) |
458 | + | 401 | +{ |
459 | + return MEMTX_OK; | 402 | + /* |
460 | +} | 403 | + * Test that configuring a line in push-pull output mode |
461 | + | 404 | + * disconnects the pin, that the pin can't be set or reset |
462 | +static const MemoryRegionOps iotkit_secctl_s_ops = { | 405 | + * externally afterwards. |
463 | + .read_with_attrs = iotkit_secctl_s_read, | 406 | + */ |
464 | + .write_with_attrs = iotkit_secctl_s_write, | 407 | + unsigned int pin = ((uint64_t)data) & 0xF; |
465 | + .endianness = DEVICE_LITTLE_ENDIAN, | 408 | + uint32_t gpio = ((uint64_t)data) >> 32; |
466 | + .valid.min_access_size = 1, | 409 | + uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); |
467 | + .valid.max_access_size = 4, | 410 | + |
468 | + .impl.min_access_size = 1, | 411 | + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); |
469 | + .impl.max_access_size = 4, | 412 | + |
470 | +}; | 413 | + /* Setting a line high externally, configuring it in push-pull output */ |
471 | + | 414 | + /* And checking the pin was disconnected */ |
472 | +static const MemoryRegionOps iotkit_secctl_ns_ops = { | 415 | + gpio_set_irq(gpio, pin, 1); |
473 | + .read_with_attrs = iotkit_secctl_ns_read, | 416 | + gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT); |
474 | + .write_with_attrs = iotkit_secctl_ns_write, | 417 | + g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF); |
475 | + .endianness = DEVICE_LITTLE_ENDIAN, | 418 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); |
476 | + .valid.min_access_size = 1, | 419 | + |
477 | + .valid.max_access_size = 4, | 420 | + /* Setting a line low externally, configuring it in push-pull output */ |
478 | + .impl.min_access_size = 1, | 421 | + /* And checking the pin was disconnected */ |
479 | + .impl.max_access_size = 4, | 422 | + gpio_set_irq(gpio2, pin, 0); |
480 | +}; | 423 | + gpio_set_bit(gpio2, ODR, pin, 1); |
481 | + | 424 | + gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT); |
482 | +static void iotkit_secctl_reset(DeviceState *dev) | 425 | + g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF); |
483 | +{ | 426 | + g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin)); |
484 | + | 427 | + |
485 | +} | 428 | + /* Trying to set a push-pull output pin, checking it doesn't work */ |
486 | + | 429 | + gpio_set_irq(gpio, pin, 1); |
487 | +static void iotkit_secctl_init(Object *obj) | 430 | + g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF); |
488 | +{ | 431 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); |
489 | + IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | 432 | + |
490 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 433 | + /* Trying to reset a push-pull output pin, checking it doesn't work */ |
491 | + | 434 | + gpio_set_irq(gpio2, pin, 0); |
492 | + memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | 435 | + g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF); |
493 | + s, "iotkit-secctl-s-regs", 0x1000); | 436 | + g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin)); |
494 | + memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops, | 437 | + |
495 | + s, "iotkit-secctl-ns-regs", 0x1000); | 438 | + /* Clean the test */ |
496 | + sysbus_init_mmio(sbd, &s->s_regs); | 439 | + gpio_writel(gpio, MODER, reset(gpio, MODER)); |
497 | + sysbus_init_mmio(sbd, &s->ns_regs); | 440 | + gpio_writel(gpio2, ODR, reset(gpio2, ODR)); |
498 | +} | 441 | + gpio_writel(gpio2, MODER, reset(gpio2, MODER)); |
499 | + | 442 | +} |
500 | +static const VMStateDescription iotkit_secctl_vmstate = { | 443 | + |
501 | + .name = "iotkit-secctl", | 444 | +static void test_open_drain(const void *data) |
502 | + .version_id = 1, | 445 | +{ |
503 | + .minimum_version_id = 1, | 446 | + /* |
504 | + .fields = (VMStateField[]) { | 447 | + * Test that configuring a line in open-drain output mode |
505 | + VMSTATE_END_OF_LIST() | 448 | + * disconnects a pin set high externally and that the pin |
506 | + } | 449 | + * can't be set high externally while configured in open-drain. |
507 | +}; | 450 | + * |
508 | + | 451 | + * However a pin set low externally shouldn't be disconnected, |
509 | +static void iotkit_secctl_class_init(ObjectClass *klass, void *data) | 452 | + * and it can be set low externally when in open-drain mode. |
510 | +{ | 453 | + */ |
511 | + DeviceClass *dc = DEVICE_CLASS(klass); | 454 | + unsigned int pin = ((uint64_t)data) & 0xF; |
512 | + | 455 | + uint32_t gpio = ((uint64_t)data) >> 32; |
513 | + dc->vmsd = &iotkit_secctl_vmstate; | 456 | + uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); |
514 | + dc->reset = iotkit_secctl_reset; | 457 | + |
515 | +} | 458 | + qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); |
516 | + | 459 | + |
517 | +static const TypeInfo iotkit_secctl_info = { | 460 | + /* Setting a line high externally, configuring it in open-drain output */ |
518 | + .name = TYPE_IOTKIT_SECCTL, | 461 | + /* And checking the pin was disconnected */ |
519 | + .parent = TYPE_SYS_BUS_DEVICE, | 462 | + gpio_set_irq(gpio, pin, 1); |
520 | + .instance_size = sizeof(IoTKitSecCtl), | 463 | + gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN); |
521 | + .instance_init = iotkit_secctl_init, | 464 | + gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT); |
522 | + .class_init = iotkit_secctl_class_init, | 465 | + g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF); |
523 | +}; | 466 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); |
524 | + | 467 | + |
525 | +static void iotkit_secctl_register_types(void) | 468 | + /* Setting a line low externally, configuring it in open-drain output */ |
526 | +{ | 469 | + /* And checking the pin wasn't disconnected */ |
527 | + type_register_static(&iotkit_secctl_info); | 470 | + gpio_set_irq(gpio2, pin, 0); |
528 | +} | 471 | + gpio_set_bit(gpio2, ODR, pin, 1); |
529 | + | 472 | + gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN); |
530 | +type_init(iotkit_secctl_register_types); | 473 | + gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT); |
531 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | 474 | + g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin)); |
475 | + g_assert_cmphex(gpio_readl(gpio2, IDR), ==, | ||
476 | + reset(gpio2, IDR) & ~(1 << pin)); | ||
477 | + | ||
478 | + /* Trying to set a open-drain output pin, checking it doesn't work */ | ||
479 | + gpio_set_irq(gpio, pin, 1); | ||
480 | + g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF); | ||
481 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin)); | ||
482 | + | ||
483 | + /* Trying to reset a open-drain output pin, checking it works */ | ||
484 | + gpio_set_bit(gpio, ODR, pin, 1); | ||
485 | + gpio_set_irq(gpio, pin, 0); | ||
486 | + g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin)); | ||
487 | + g_assert_cmphex(gpio_readl(gpio2, IDR), ==, | ||
488 | + reset(gpio2, IDR) & ~(1 << pin)); | ||
489 | + | ||
490 | + /* Clean the test */ | ||
491 | + disconnect_all_pins(gpio2); | ||
492 | + gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER)); | ||
493 | + gpio_writel(gpio2, ODR, reset(gpio2, ODR)); | ||
494 | + gpio_writel(gpio2, MODER, reset(gpio2, MODER)); | ||
495 | + g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR)); | ||
496 | + disconnect_all_pins(gpio); | ||
497 | + gpio_writel(gpio, OTYPER, reset(gpio, OTYPER)); | ||
498 | + gpio_writel(gpio, ODR, reset(gpio, ODR)); | ||
499 | + gpio_writel(gpio, MODER, reset(gpio, MODER)); | ||
500 | + g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR)); | ||
501 | +} | ||
502 | + | ||
503 | +static void test_bsrr_brr(const void *data) | ||
504 | +{ | ||
505 | + /* | ||
506 | + * Test that writing a '1' in BSS and BSRR | ||
507 | + * has the desired effect on ODR. | ||
508 | + * In BSRR, BSx has priority over BRx. | ||
509 | + */ | ||
510 | + unsigned int pin = ((uint64_t)data) & 0xF; | ||
511 | + uint32_t gpio = ((uint64_t)data) >> 32; | ||
512 | + | ||
513 | + gpio_writel(gpio, BSRR, (1 << pin)); | ||
514 | + g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin)); | ||
515 | + | ||
516 | + gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS))); | ||
517 | + g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR)); | ||
518 | + | ||
519 | + gpio_writel(gpio, BSRR, (1 << pin)); | ||
520 | + g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin)); | ||
521 | + | ||
522 | + gpio_writel(gpio, BRR, (1 << pin)); | ||
523 | + g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR)); | ||
524 | + | ||
525 | + /* BSx should have priority over BRx */ | ||
526 | + gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS))); | ||
527 | + g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin)); | ||
528 | + | ||
529 | + gpio_writel(gpio, BRR, (1 << pin)); | ||
530 | + g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR)); | ||
531 | + | ||
532 | + gpio_writel(gpio, ODR, reset(gpio, ODR)); | ||
533 | +} | ||
534 | + | ||
535 | +int main(int argc, char **argv) | ||
536 | +{ | ||
537 | + int ret; | ||
538 | + | ||
539 | + g_test_init(&argc, &argv, NULL); | ||
540 | + g_test_set_nonfatal_assertions(); | ||
541 | + qtest_add_func("stm32l4x5/gpio/test_idr_reset_value", | ||
542 | + test_idr_reset_value); | ||
543 | + /* | ||
544 | + * The inputs for the tests (gpio and pin) can be changed, | ||
545 | + * but the tests don't work for pins that are high at reset | ||
546 | + * (GPIOA15, GPIO13 and GPIOB5). | ||
547 | + * Specifically, rising the pin then checking `get_irq()` | ||
548 | + * is problematic since the pin was already high. | ||
549 | + */ | ||
550 | + qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode", | ||
551 | + (void *)((uint64_t)GPIO_C << 32 | 5), | ||
552 | + test_gpio_output_mode); | ||
553 | + qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode", | ||
554 | + (void *)((uint64_t)GPIO_H << 32 | 3), | ||
555 | + test_gpio_output_mode); | ||
556 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1", | ||
557 | + (void *)((uint64_t)GPIO_D << 32 | 6), | ||
558 | + test_gpio_input_mode); | ||
559 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2", | ||
560 | + (void *)((uint64_t)GPIO_C << 32 | 10), | ||
561 | + test_gpio_input_mode); | ||
562 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1", | ||
563 | + (void *)((uint64_t)GPIO_B << 32 | 5), | ||
564 | + test_pull_up_pull_down); | ||
565 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2", | ||
566 | + (void *)((uint64_t)GPIO_F << 32 | 1), | ||
567 | + test_pull_up_pull_down); | ||
568 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1", | ||
569 | + (void *)((uint64_t)GPIO_G << 32 | 6), | ||
570 | + test_push_pull); | ||
571 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2", | ||
572 | + (void *)((uint64_t)GPIO_H << 32 | 3), | ||
573 | + test_push_pull); | ||
574 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1", | ||
575 | + (void *)((uint64_t)GPIO_C << 32 | 4), | ||
576 | + test_open_drain); | ||
577 | + qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2", | ||
578 | + (void *)((uint64_t)GPIO_E << 32 | 11), | ||
579 | + test_open_drain); | ||
580 | + qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1", | ||
581 | + (void *)((uint64_t)GPIO_A << 32 | 12), | ||
582 | + test_bsrr_brr); | ||
583 | + qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2", | ||
584 | + (void *)((uint64_t)GPIO_D << 32 | 0), | ||
585 | + test_bsrr_brr); | ||
586 | + | ||
587 | + qtest_start("-machine b-l475e-iot01a"); | ||
588 | + ret = g_test_run(); | ||
589 | + qtest_end(); | ||
590 | + | ||
591 | + return ret; | ||
592 | +} | ||
593 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
532 | index XXXXXXX..XXXXXXX 100644 | 594 | index XXXXXXX..XXXXXXX 100644 |
533 | --- a/default-configs/arm-softmmu.mak | 595 | --- a/tests/qtest/meson.build |
534 | +++ b/default-configs/arm-softmmu.mak | 596 | +++ b/tests/qtest/meson.build |
535 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | 597 | @@ -XXX,XX +XXX,XX @@ qtests_aspeed = \ |
536 | CONFIG_MPS2_SCC=y | 598 | qtests_stm32l4x5 = \ |
537 | 599 | ['stm32l4x5_exti-test', | |
538 | CONFIG_TZ_PPC=y | 600 | 'stm32l4x5_syscfg-test', |
539 | +CONFIG_IOTKIT_SECCTL=y | 601 | - 'stm32l4x5_rcc-test'] |
540 | 602 | + 'stm32l4x5_rcc-test', | |
541 | CONFIG_VERSATILE_PCI=y | 603 | + 'stm32l4x5_gpio-test'] |
542 | CONFIG_VERSATILE_I2C=y | 604 | |
543 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | 605 | qtests_arm = \ |
544 | index XXXXXXX..XXXXXXX 100644 | 606 | (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ |
545 | --- a/hw/misc/trace-events | ||
546 | +++ b/hw/misc/trace-events | ||
547 | @@ -XXX,XX +XXX,XX @@ tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
548 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
549 | tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
550 | tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
551 | + | ||
552 | +# hw/misc/iotkit-secctl.c | ||
553 | +iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
554 | +iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
555 | +iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
556 | +iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
557 | +iotkit_secctl_reset(void) "IoTKit SecCtl: reset" | ||
558 | -- | 607 | -- |
559 | 2.16.2 | 608 | 2.34.1 |
560 | 609 | ||
561 | 610 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | While the 8-bit input elements are sequential in the input vector, |
4 | the 32-bit output elements are not sequential in the output matrix. | ||
5 | Do not attempt to compute 2 32-bit outputs at the same time. | ||
6 | |||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product") | ||
9 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083 | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180228193125.20577-5-richard.henderson@linaro.org | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Message-id: 20240305163931.242795-1-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 14 | --- |
8 | target/arm/Makefile.objs | 2 +- | 15 | target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++------------- |
9 | target/arm/helper.h | 4 ++ | 16 | tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++ |
10 | target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++ | 17 | tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++ |
11 | target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ | 18 | tests/tcg/aarch64/Makefile.target | 2 +- |
12 | 4 files changed, 198 insertions(+), 1 deletion(-) | 19 | 4 files changed, 147 insertions(+), 33 deletions(-) |
13 | create mode 100644 target/arm/vec_helper.c | 20 | create mode 100644 tests/tcg/aarch64/sme-smopa-1.c |
14 | 21 | create mode 100644 tests/tcg/aarch64/sme-smopa-2.c | |
15 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | 22 | |
23 | diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/Makefile.objs | 25 | --- a/target/arm/tcg/sme_helper.c |
18 | +++ b/target/arm/Makefile.objs | 26 | +++ b/target/arm/tcg/sme_helper.c |
19 | @@ -XXX,XX +XXX,XX @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o | 27 | @@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, |
20 | obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o | 28 | } |
21 | obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o | ||
22 | obj-y += translate.o op_helper.o helper.o cpu.o | ||
23 | -obj-y += neon_helper.o iwmmxt_helper.o | ||
24 | +obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o | ||
25 | obj-y += gdbstub.o | ||
26 | obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o | ||
27 | obj-y += crypto_helper.o | ||
28 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/helper.h | ||
31 | +++ b/target/arm/helper.h | ||
32 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) | ||
33 | |||
34 | DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) | ||
36 | +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) | ||
37 | +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) | ||
38 | DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) | ||
39 | DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) | ||
40 | +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) | ||
41 | +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) | ||
42 | |||
43 | DEF_HELPER_1(neon_narrow_u8, i32, i64) | ||
44 | DEF_HELPER_1(neon_narrow_u16, i32, i64) | ||
45 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-a64.c | ||
48 | +++ b/target/arm/translate-a64.c | ||
49 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | ||
50 | tcg_temp_free_ptr(fpst); | ||
51 | } | 29 | } |
52 | 30 | ||
53 | +/* AdvSIMD scalar three same extra | 31 | -typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); |
54 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | 32 | +typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool); |
55 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | 33 | +static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm, |
56 | + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | 34 | + uint8_t *pn, uint8_t *pm, |
57 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | 35 | + uint32_t desc, IMOPFn32 *fn) |
58 | + */ | ||
59 | +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | ||
60 | + uint32_t insn) | ||
61 | +{ | 36 | +{ |
62 | + int rd = extract32(insn, 0, 5); | 37 | + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; |
63 | + int rn = extract32(insn, 5, 5); | 38 | + bool neg = simd_data(desc); |
64 | + int opcode = extract32(insn, 11, 4); | 39 | |
65 | + int rm = extract32(insn, 16, 5); | 40 | -static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, |
66 | + int size = extract32(insn, 22, 2); | 41 | - uint8_t *pn, uint8_t *pm, |
67 | + bool u = extract32(insn, 29, 1); | 42 | - uint32_t desc, IMOPFn *fn) |
68 | + TCGv_i32 ele1, ele2, ele3; | 43 | + for (row = 0; row < oprsz; ++row) { |
69 | + TCGv_i64 res; | 44 | + uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf; |
70 | + int feature; | 45 | + uint32_t *za_row = &za[tile_vslice_index(row)]; |
71 | + | 46 | + uint32_t n = zn[H4(row)]; |
72 | + switch (u * 16 + opcode) { | 47 | + |
73 | + case 0x10: /* SQRDMLAH (vector) */ | 48 | + for (col = 0; col < oprsz; ++col) { |
74 | + case 0x11: /* SQRDMLSH (vector) */ | 49 | + uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4); |
75 | + if (size != 1 && size != 2) { | 50 | + uint32_t *a = &za_row[H4(col)]; |
76 | + unallocated_encoding(s); | 51 | + |
77 | + return; | 52 | + *a = fn(n, zm[H4(col)], *a, pa & pb, neg); |
78 | + } | 53 | + } |
79 | + feature = ARM_FEATURE_V8_RDM; | 54 | + } |
80 | + break; | ||
81 | + default: | ||
82 | + unallocated_encoding(s); | ||
83 | + return; | ||
84 | + } | ||
85 | + if (!arm_dc_feature(s, feature)) { | ||
86 | + unallocated_encoding(s); | ||
87 | + return; | ||
88 | + } | ||
89 | + if (!fp_access_check(s)) { | ||
90 | + return; | ||
91 | + } | ||
92 | + | ||
93 | + /* Do a single operation on the lowest element in the vector. | ||
94 | + * We use the standard Neon helpers and rely on 0 OP 0 == 0 | ||
95 | + * with no side effects for all these operations. | ||
96 | + * OPTME: special-purpose helpers would avoid doing some | ||
97 | + * unnecessary work in the helper for the 16 bit cases. | ||
98 | + */ | ||
99 | + ele1 = tcg_temp_new_i32(); | ||
100 | + ele2 = tcg_temp_new_i32(); | ||
101 | + ele3 = tcg_temp_new_i32(); | ||
102 | + | ||
103 | + read_vec_element_i32(s, ele1, rn, 0, size); | ||
104 | + read_vec_element_i32(s, ele2, rm, 0, size); | ||
105 | + read_vec_element_i32(s, ele3, rd, 0, size); | ||
106 | + | ||
107 | + switch (opcode) { | ||
108 | + case 0x0: /* SQRDMLAH */ | ||
109 | + if (size == 1) { | ||
110 | + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
111 | + } else { | ||
112 | + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
113 | + } | ||
114 | + break; | ||
115 | + case 0x1: /* SQRDMLSH */ | ||
116 | + if (size == 1) { | ||
117 | + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
118 | + } else { | ||
119 | + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
120 | + } | ||
121 | + break; | ||
122 | + default: | ||
123 | + g_assert_not_reached(); | ||
124 | + } | ||
125 | + tcg_temp_free_i32(ele1); | ||
126 | + tcg_temp_free_i32(ele2); | ||
127 | + | ||
128 | + res = tcg_temp_new_i64(); | ||
129 | + tcg_gen_extu_i32_i64(res, ele3); | ||
130 | + tcg_temp_free_i32(ele3); | ||
131 | + | ||
132 | + write_fp_dreg(s, rd, res); | ||
133 | + tcg_temp_free_i64(res); | ||
134 | +} | 55 | +} |
135 | + | 56 | + |
136 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, | 57 | +typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool); |
137 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, | 58 | +static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm, |
138 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | 59 | + uint8_t *pn, uint8_t *pm, |
139 | @@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = { | 60 | + uint32_t desc, IMOPFn64 *fn) |
140 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | 61 | { |
141 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | 62 | intptr_t row, col, oprsz = simd_oprsz(desc) / 8; |
142 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | 63 | bool neg = simd_data(desc); |
143 | + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, | 64 | @@ -XXX,XX +XXX,XX @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, |
144 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | 65 | } |
145 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | 66 | |
146 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | 67 | #define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ |
147 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | 68 | -static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ |
69 | +static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \ | ||
70 | { \ | ||
71 | - uint32_t sum0 = 0, sum1 = 0; \ | ||
72 | + uint32_t sum = 0; \ | ||
73 | /* Apply P to N as a mask, making the inactive elements 0. */ \ | ||
74 | n &= expand_pred_b(p); \ | ||
75 | - sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ | ||
76 | - sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ | ||
77 | - sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ | ||
78 | - sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ | ||
79 | - sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ | ||
80 | - sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \ | ||
81 | - sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ | ||
82 | - sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \ | ||
83 | - if (neg) { \ | ||
84 | - sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \ | ||
85 | - } else { \ | ||
86 | - sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \ | ||
87 | - } \ | ||
88 | - return ((uint64_t)sum1 << 32) | sum0; \ | ||
89 | + sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ | ||
90 | + sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ | ||
91 | + sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ | ||
92 | + sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ | ||
93 | + return neg ? a - sum : a + sum; \ | ||
94 | } | ||
95 | |||
96 | #define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ | ||
97 | @@ -XXX,XX +XXX,XX @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t) | ||
98 | DEF_IMOP_64(sumopa_d, int16_t, uint16_t) | ||
99 | DEF_IMOP_64(usmopa_d, uint16_t, int16_t) | ||
100 | |||
101 | -#define DEF_IMOPH(NAME) \ | ||
102 | - void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \ | ||
103 | - void *vpm, uint32_t desc) \ | ||
104 | - { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } | ||
105 | +#define DEF_IMOPH(NAME, S) \ | ||
106 | + void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \ | ||
107 | + void *vpn, void *vpm, uint32_t desc) \ | ||
108 | + { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); } | ||
109 | |||
110 | -DEF_IMOPH(smopa_s) | ||
111 | -DEF_IMOPH(umopa_s) | ||
112 | -DEF_IMOPH(sumopa_s) | ||
113 | -DEF_IMOPH(usmopa_s) | ||
114 | -DEF_IMOPH(smopa_d) | ||
115 | -DEF_IMOPH(umopa_d) | ||
116 | -DEF_IMOPH(sumopa_d) | ||
117 | -DEF_IMOPH(usmopa_d) | ||
118 | +DEF_IMOPH(smopa, s) | ||
119 | +DEF_IMOPH(umopa, s) | ||
120 | +DEF_IMOPH(sumopa, s) | ||
121 | +DEF_IMOPH(usmopa, s) | ||
122 | + | ||
123 | +DEF_IMOPH(smopa, d) | ||
124 | +DEF_IMOPH(umopa, d) | ||
125 | +DEF_IMOPH(sumopa, d) | ||
126 | +DEF_IMOPH(usmopa, d) | ||
127 | diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c | ||
148 | new file mode 100644 | 128 | new file mode 100644 |
149 | index XXXXXXX..XXXXXXX | 129 | index XXXXXXX..XXXXXXX |
150 | --- /dev/null | 130 | --- /dev/null |
151 | +++ b/target/arm/vec_helper.c | 131 | +++ b/tests/tcg/aarch64/sme-smopa-1.c |
152 | @@ -XXX,XX +XXX,XX @@ | 132 | @@ -XXX,XX +XXX,XX @@ |
153 | +/* | 133 | +#include <stdio.h> |
154 | + * ARM AdvSIMD / SVE Vector Operations | 134 | +#include <string.h> |
155 | + * | 135 | + |
156 | + * Copyright (c) 2018 Linaro | 136 | +int main() |
157 | + * | ||
158 | + * This library is free software; you can redistribute it and/or | ||
159 | + * modify it under the terms of the GNU Lesser General Public | ||
160 | + * License as published by the Free Software Foundation; either | ||
161 | + * version 2 of the License, or (at your option) any later version. | ||
162 | + * | ||
163 | + * This library is distributed in the hope that it will be useful, | ||
164 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
165 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
166 | + * Lesser General Public License for more details. | ||
167 | + * | ||
168 | + * You should have received a copy of the GNU Lesser General Public | ||
169 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
170 | + */ | ||
171 | + | ||
172 | +#include "qemu/osdep.h" | ||
173 | +#include "cpu.h" | ||
174 | +#include "exec/exec-all.h" | ||
175 | +#include "exec/helper-proto.h" | ||
176 | +#include "tcg/tcg-gvec-desc.h" | ||
177 | + | ||
178 | + | ||
179 | +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
180 | + | ||
181 | +/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
182 | +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
183 | + int16_t src2, int16_t src3) | ||
184 | +{ | 137 | +{ |
185 | + /* Simplify: | 138 | + static const int cmp[4][4] = { |
186 | + * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 | 139 | + { 110, 134, 158, 182 }, |
187 | + * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 | 140 | + { 390, 478, 566, 654 }, |
188 | + */ | 141 | + { 670, 822, 974, 1126 }, |
189 | + int32_t ret = (int32_t)src1 * src2; | 142 | + { 950, 1166, 1382, 1598 } |
190 | + ret = ((int32_t)src3 << 15) + ret + (1 << 14); | 143 | + }; |
191 | + ret >>= 15; | 144 | + int dst[4][4]; |
192 | + if (ret != (int16_t)ret) { | 145 | + int *tmp = &dst[0][0]; |
193 | + SET_QC(); | 146 | + |
194 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | 147 | + asm volatile( |
195 | + } | 148 | + ".arch armv8-r+sme\n\t" |
196 | + return ret; | 149 | + "smstart\n\t" |
150 | + "index z0.b, #0, #1\n\t" | ||
151 | + "movprfx z1, z0\n\t" | ||
152 | + "add z1.b, z1.b, #16\n\t" | ||
153 | + "ptrue p0.b\n\t" | ||
154 | + "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t" | ||
155 | + "ptrue p0.s, vl4\n\t" | ||
156 | + "mov w12, #0\n\t" | ||
157 | + "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t" | ||
158 | + "add %0, %0, #16\n\t" | ||
159 | + "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t" | ||
160 | + "add %0, %0, #16\n\t" | ||
161 | + "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t" | ||
162 | + "add %0, %0, #16\n\t" | ||
163 | + "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t" | ||
164 | + "smstop" | ||
165 | + : "+r"(tmp) : : "memory"); | ||
166 | + | ||
167 | + if (memcmp(cmp, dst, sizeof(dst)) == 0) { | ||
168 | + return 0; | ||
169 | + } | ||
170 | + | ||
171 | + /* See above for correct results. */ | ||
172 | + for (int i = 0; i < 4; ++i) { | ||
173 | + for (int j = 0; j < 4; ++j) { | ||
174 | + printf("%6d", dst[i][j]); | ||
175 | + } | ||
176 | + printf("\n"); | ||
177 | + } | ||
178 | + return 1; | ||
197 | +} | 179 | +} |
198 | + | 180 | diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c |
199 | +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | 181 | new file mode 100644 |
200 | + uint32_t src2, uint32_t src3) | 182 | index XXXXXXX..XXXXXXX |
183 | --- /dev/null | ||
184 | +++ b/tests/tcg/aarch64/sme-smopa-2.c | ||
185 | @@ -XXX,XX +XXX,XX @@ | ||
186 | +#include <stdio.h> | ||
187 | +#include <string.h> | ||
188 | + | ||
189 | +int main() | ||
201 | +{ | 190 | +{ |
202 | + uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3); | 191 | + static const long cmp[4][4] = { |
203 | + uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | 192 | + { 110, 134, 158, 182 }, |
204 | + return deposit32(e1, 16, 16, e2); | 193 | + { 390, 478, 566, 654 }, |
194 | + { 670, 822, 974, 1126 }, | ||
195 | + { 950, 1166, 1382, 1598 } | ||
196 | + }; | ||
197 | + long dst[4][4]; | ||
198 | + long *tmp = &dst[0][0]; | ||
199 | + long svl; | ||
200 | + | ||
201 | + /* Validate that we have a wide enough vector for 4 elements. */ | ||
202 | + asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl)); | ||
203 | + if (svl < 32) { | ||
204 | + return 0; | ||
205 | + } | ||
206 | + | ||
207 | + asm volatile( | ||
208 | + "smstart\n\t" | ||
209 | + "index z0.h, #0, #1\n\t" | ||
210 | + "movprfx z1, z0\n\t" | ||
211 | + "add z1.h, z1.h, #16\n\t" | ||
212 | + "ptrue p0.b\n\t" | ||
213 | + "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t" | ||
214 | + "ptrue p0.d, vl4\n\t" | ||
215 | + "mov w12, #0\n\t" | ||
216 | + "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t" | ||
217 | + "add %0, %0, #32\n\t" | ||
218 | + "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t" | ||
219 | + "mov w12, #2\n\t" | ||
220 | + "add %0, %0, #32\n\t" | ||
221 | + "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t" | ||
222 | + "add %0, %0, #32\n\t" | ||
223 | + "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t" | ||
224 | + "smstop" | ||
225 | + : "+r"(tmp) : : "memory"); | ||
226 | + | ||
227 | + if (memcmp(cmp, dst, sizeof(dst)) == 0) { | ||
228 | + return 0; | ||
229 | + } | ||
230 | + | ||
231 | + /* See above for correct results. */ | ||
232 | + for (int i = 0; i < 4; ++i) { | ||
233 | + for (int j = 0; j < 4; ++j) { | ||
234 | + printf("%6ld", dst[i][j]); | ||
235 | + } | ||
236 | + printf("\n"); | ||
237 | + } | ||
238 | + return 1; | ||
205 | +} | 239 | +} |
206 | + | 240 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target |
207 | +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | 241 | index XXXXXXX..XXXXXXX 100644 |
208 | +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | 242 | --- a/tests/tcg/aarch64/Makefile.target |
209 | + int16_t src2, int16_t src3) | 243 | +++ b/tests/tcg/aarch64/Makefile.target |
210 | +{ | 244 | @@ -XXX,XX +XXX,XX @@ endif |
211 | + /* Similarly, using subtraction: | 245 | |
212 | + * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 | 246 | # SME Tests |
213 | + * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 | 247 | ifneq ($(CROSS_AS_HAS_ARMV9_SME),) |
214 | + */ | 248 | -AARCH64_TESTS += sme-outprod1 |
215 | + int32_t ret = (int32_t)src1 * src2; | 249 | +AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2 |
216 | + ret = ((int32_t)src3 << 15) - ret + (1 << 14); | 250 | endif |
217 | + ret >>= 15; | 251 | |
218 | + if (ret != (int16_t)ret) { | 252 | # System Registers Tests |
219 | + SET_QC(); | ||
220 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
221 | + } | ||
222 | + return ret; | ||
223 | +} | ||
224 | + | ||
225 | +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
226 | + uint32_t src2, uint32_t src3) | ||
227 | +{ | ||
228 | + uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3); | ||
229 | + uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
230 | + return deposit32(e1, 16, 16, e2); | ||
231 | +} | ||
232 | + | ||
233 | +/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
234 | +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
235 | + int32_t src2, int32_t src3) | ||
236 | +{ | ||
237 | + /* Simplify similarly to int_qrdmlah_s16 above. */ | ||
238 | + int64_t ret = (int64_t)src1 * src2; | ||
239 | + ret = ((int64_t)src3 << 31) + ret + (1 << 30); | ||
240 | + ret >>= 31; | ||
241 | + if (ret != (int32_t)ret) { | ||
242 | + SET_QC(); | ||
243 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
244 | + } | ||
245 | + return ret; | ||
246 | +} | ||
247 | + | ||
248 | +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
249 | +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
250 | + int32_t src2, int32_t src3) | ||
251 | +{ | ||
252 | + /* Simplify similarly to int_qrdmlsh_s16 above. */ | ||
253 | + int64_t ret = (int64_t)src1 * src2; | ||
254 | + ret = ((int64_t)src3 << 31) - ret + (1 << 30); | ||
255 | + ret >>= 31; | ||
256 | + if (ret != (int32_t)ret) { | ||
257 | + SET_QC(); | ||
258 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
259 | + } | ||
260 | + return ret; | ||
261 | +} | ||
262 | -- | 253 | -- |
263 | 2.16.2 | 254 | 2.34.1 |
264 | 255 | ||
265 | 256 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016 |
---|---|---|---|
2 | was unfortunately added with a license of GPL-v3-or-later, which is | ||
3 | not compatible with other QEMU code which has a GPL-v2-only license. | ||
2 | 4 | ||
3 | Allow the translate subroutines to return false for invalid insns. | 5 | Relicense the code in the .c and the .h file to GPL-v2-or-later, |
6 | to make it compatible with the rest of QEMU. | ||
4 | 7 | ||
5 | At present we can of course invoke an invalid insn exception from within | 8 | Cc: qemu-stable@nongnu.org |
6 | the translate subroutine, but in the short term this consolidates code. | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | In the long term it would allow the decodetree language to support | 10 | Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com> |
8 | overlapping patterns for ISA extensions. | 11 | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> |
9 | 12 | Signed-off-by: Markus Armbruster <armbru@redhat.com> | |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
11 | Message-id: 20180227232618.2908-1-richard.henderson@linaro.org | 14 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> |
16 | Acked-by: Alex Bennée <alex.bennee@linaro.org> | ||
17 | Message-id: 20240223161300.938542-1-peter.maydell@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 19 | --- |
15 | scripts/decodetree.py | 5 ++--- | 20 | include/hw/rtc/sun4v-rtc.h | 2 +- |
16 | 1 file changed, 2 insertions(+), 3 deletions(-) | 21 | hw/rtc/sun4v-rtc.c | 2 +- |
22 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
17 | 23 | ||
18 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py | 24 | diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h |
19 | index XXXXXXX..XXXXXXX 100755 | 25 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/scripts/decodetree.py | 26 | --- a/include/hw/rtc/sun4v-rtc.h |
21 | +++ b/scripts/decodetree.py | 27 | +++ b/include/hw/rtc/sun4v-rtc.h |
22 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | 28 | @@ -XXX,XX +XXX,XX @@ |
23 | global translate_prefix | 29 | * |
24 | output('typedef ', self.base.base.struct_name(), | 30 | * Copyright (c) 2016 Artyom Tarasenko |
25 | ' arg_', self.name, ';\n') | 31 | * |
26 | - output(translate_scope, 'void ', translate_prefix, '_', self.name, | 32 | - * This code is licensed under the GNU GPL v3 or (at your option) any later |
27 | + output(translate_scope, 'bool ', translate_prefix, '_', self.name, | 33 | + * This code is licensed under the GNU GPL v2 or (at your option) any later |
28 | '(DisasContext *ctx, arg_', self.name, | 34 | * version. |
29 | ' *a, ', insntype, ' insn);\n') | 35 | */ |
30 | 36 | ||
31 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | 37 | diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c |
32 | output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n') | 38 | index XXXXXXX..XXXXXXX 100644 |
33 | for n, f in self.fields.items(): | 39 | --- a/hw/rtc/sun4v-rtc.c |
34 | output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') | 40 | +++ b/hw/rtc/sun4v-rtc.c |
35 | - output(ind, translate_prefix, '_', self.name, | 41 | @@ -XXX,XX +XXX,XX @@ |
36 | + output(ind, 'return ', translate_prefix, '_', self.name, | 42 | * |
37 | '(ctx, &u.f_', arg, ', insn);\n') | 43 | * Copyright (c) 2016 Artyom Tarasenko |
38 | - output(ind, 'return true;\n') | 44 | * |
39 | # end Pattern | 45 | - * This code is licensed under the GNU GPL v3 or (at your option) any later |
40 | 46 | + * This code is licensed under the GNU GPL v2 or (at your option) any later | |
47 | * version. | ||
48 | */ | ||
41 | 49 | ||
42 | -- | 50 | -- |
43 | 2.16.2 | 51 | 2.34.1 |
44 | 52 | ||
45 | 53 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add a function load_ramdisk_as() which behaves like the existing | ||
2 | load_ramdisk() but allows the caller to specify the AddressSpace | ||
3 | to use. This matches the pattern we have already for various | ||
4 | other loader functions. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/hw/loader.h | 12 +++++++++++- | ||
12 | hw/core/loader.c | 8 +++++++- | ||
13 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/loader.h b/include/hw/loader.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/loader.h | ||
18 | +++ b/include/hw/loader.h | ||
19 | @@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep, | ||
20 | void *translate_opaque); | ||
21 | |||
22 | /** | ||
23 | - * load_ramdisk: | ||
24 | + * load_ramdisk_as: | ||
25 | * @filename: Path to the ramdisk image | ||
26 | * @addr: Memory address to load the ramdisk to | ||
27 | * @max_sz: Maximum allowed ramdisk size (for non-u-boot ramdisks) | ||
28 | + * @as: The AddressSpace to load the ELF to. The value of address_space_memory | ||
29 | + * is used if nothing is supplied here. | ||
30 | * | ||
31 | * Load a ramdisk image with U-Boot header to the specified memory | ||
32 | * address. | ||
33 | * | ||
34 | * Returns the size of the loaded image on success, -1 otherwise. | ||
35 | */ | ||
36 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
37 | + AddressSpace *as); | ||
38 | + | ||
39 | +/** | ||
40 | + * load_ramdisk: | ||
41 | + * Same as load_ramdisk_as(), but doesn't allow the caller to specify | ||
42 | + * an AddressSpace. | ||
43 | + */ | ||
44 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz); | ||
45 | |||
46 | ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen); | ||
47 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/core/loader.c | ||
50 | +++ b/hw/core/loader.c | ||
51 | @@ -XXX,XX +XXX,XX @@ int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr, | ||
52 | |||
53 | /* Load a ramdisk. */ | ||
54 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz) | ||
55 | +{ | ||
56 | + return load_ramdisk_as(filename, addr, max_sz, NULL); | ||
57 | +} | ||
58 | + | ||
59 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
60 | + AddressSpace *as) | ||
61 | { | ||
62 | return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK, | ||
63 | - NULL, NULL, NULL); | ||
64 | + NULL, NULL, as); | ||
65 | } | ||
66 | |||
67 | /* Load a gzip-compressed kernel to a dynamically allocated buffer. */ | ||
68 | -- | ||
69 | 2.16.2 | ||
70 | |||
71 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Instead of loading kernels, device trees, and the like to | ||
2 | the system address space, use the CPU's address space. This | ||
3 | is important if we're trying to load the file to memory or | ||
4 | via an alias memory region that is provided by an SoC | ||
5 | object and thus not mapped into the system address space. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-3-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/arm/boot.c | 119 +++++++++++++++++++++++++++++++++++++--------------------- | ||
13 | 1 file changed, 76 insertions(+), 43 deletions(-) | ||
14 | |||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/boot.c | ||
18 | +++ b/hw/arm/boot.c | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #define ARM64_TEXT_OFFSET_OFFSET 8 | ||
21 | #define ARM64_MAGIC_OFFSET 56 | ||
22 | |||
23 | +static AddressSpace *arm_boot_address_space(ARMCPU *cpu, | ||
24 | + const struct arm_boot_info *info) | ||
25 | +{ | ||
26 | + /* Return the address space to use for bootloader reads and writes. | ||
27 | + * We prefer the secure address space if the CPU has it and we're | ||
28 | + * going to boot the guest into it. | ||
29 | + */ | ||
30 | + int asidx; | ||
31 | + CPUState *cs = CPU(cpu); | ||
32 | + | ||
33 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { | ||
34 | + asidx = ARMASIdx_S; | ||
35 | + } else { | ||
36 | + asidx = ARMASIdx_NS; | ||
37 | + } | ||
38 | + | ||
39 | + return cpu_get_address_space(cs, asidx); | ||
40 | +} | ||
41 | + | ||
42 | typedef enum { | ||
43 | FIXUP_NONE = 0, /* do nothing */ | ||
44 | FIXUP_TERMINATOR, /* end of insns */ | ||
45 | @@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup smpboot[] = { | ||
46 | }; | ||
47 | |||
48 | static void write_bootloader(const char *name, hwaddr addr, | ||
49 | - const ARMInsnFixup *insns, uint32_t *fixupcontext) | ||
50 | + const ARMInsnFixup *insns, uint32_t *fixupcontext, | ||
51 | + AddressSpace *as) | ||
52 | { | ||
53 | /* Fix up the specified bootloader fragment and write it into | ||
54 | * guest memory using rom_add_blob_fixed(). fixupcontext is | ||
55 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr, | ||
56 | code[i] = tswap32(insn); | ||
57 | } | ||
58 | |||
59 | - rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); | ||
60 | + rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); | ||
61 | |||
62 | g_free(code); | ||
63 | } | ||
64 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
65 | const struct arm_boot_info *info) | ||
66 | { | ||
67 | uint32_t fixupcontext[FIXUP_MAX]; | ||
68 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
69 | |||
70 | fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; | ||
71 | fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; | ||
72 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
73 | } | ||
74 | |||
75 | write_bootloader("smpboot", info->smp_loader_start, | ||
76 | - smpboot, fixupcontext); | ||
77 | + smpboot, fixupcontext, as); | ||
78 | } | ||
79 | |||
80 | void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
81 | const struct arm_boot_info *info, | ||
82 | hwaddr mvbar_addr) | ||
83 | { | ||
84 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
85 | int n; | ||
86 | uint32_t mvbar_blob[] = { | ||
87 | /* mvbar_addr: secure monitor vectors | ||
88 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
89 | for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { | ||
90 | mvbar_blob[n] = tswap32(mvbar_blob[n]); | ||
91 | } | ||
92 | - rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
93 | - mvbar_addr); | ||
94 | + rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
95 | + mvbar_addr, as); | ||
96 | |||
97 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | ||
98 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | ||
99 | } | ||
100 | - rom_add_blob_fixed("board-setup", board_setup_blob, | ||
101 | - sizeof(board_setup_blob), info->board_setup_addr); | ||
102 | + rom_add_blob_fixed_as("board-setup", board_setup_blob, | ||
103 | + sizeof(board_setup_blob), info->board_setup_addr, as); | ||
104 | } | ||
105 | |||
106 | static void default_reset_secondary(ARMCPU *cpu, | ||
107 | const struct arm_boot_info *info) | ||
108 | { | ||
109 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
110 | CPUState *cs = CPU(cpu); | ||
111 | |||
112 | - address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, | ||
113 | + address_space_stl_notdirty(as, info->smp_bootreg_addr, | ||
114 | 0, MEMTXATTRS_UNSPECIFIED, NULL); | ||
115 | cpu_set_pc(cs, info->smp_loader_start); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static inline bool have_dtb(const struct arm_boot_info *info) | ||
118 | } | ||
119 | |||
120 | #define WRITE_WORD(p, value) do { \ | ||
121 | - address_space_stl_notdirty(&address_space_memory, p, value, \ | ||
122 | + address_space_stl_notdirty(as, p, value, \ | ||
123 | MEMTXATTRS_UNSPECIFIED, NULL); \ | ||
124 | p += 4; \ | ||
125 | } while (0) | ||
126 | |||
127 | -static void set_kernel_args(const struct arm_boot_info *info) | ||
128 | +static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) | ||
129 | { | ||
130 | int initrd_size = info->initrd_size; | ||
131 | hwaddr base = info->loader_start; | ||
132 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
133 | int cmdline_size; | ||
134 | |||
135 | cmdline_size = strlen(info->kernel_cmdline); | ||
136 | - cpu_physical_memory_write(p + 8, info->kernel_cmdline, | ||
137 | - cmdline_size + 1); | ||
138 | + address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, | ||
139 | + (const uint8_t *)info->kernel_cmdline, | ||
140 | + cmdline_size + 1); | ||
141 | cmdline_size = (cmdline_size >> 2) + 1; | ||
142 | WRITE_WORD(p, cmdline_size + 2); | ||
143 | WRITE_WORD(p, 0x54410009); | ||
144 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
145 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; | ||
146 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | ||
147 | WRITE_WORD(p, 0x414f4d50); | ||
148 | - cpu_physical_memory_write(p, atag_board_buf, atag_board_len); | ||
149 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
150 | + atag_board_buf, atag_board_len); | ||
151 | p += atag_board_len; | ||
152 | } | ||
153 | /* ATAG_END */ | ||
154 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
155 | WRITE_WORD(p, 0); | ||
156 | } | ||
157 | |||
158 | -static void set_kernel_args_old(const struct arm_boot_info *info) | ||
159 | +static void set_kernel_args_old(const struct arm_boot_info *info, | ||
160 | + AddressSpace *as) | ||
161 | { | ||
162 | hwaddr p; | ||
163 | const char *s; | ||
164 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info) | ||
165 | } | ||
166 | s = info->kernel_cmdline; | ||
167 | if (s) { | ||
168 | - cpu_physical_memory_write(p, s, strlen(s) + 1); | ||
169 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
170 | + (const uint8_t *)s, strlen(s) + 1); | ||
171 | } else { | ||
172 | WRITE_WORD(p, 0); | ||
173 | } | ||
174 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
175 | * @addr: the address to load the image at | ||
176 | * @binfo: struct describing the boot environment | ||
177 | * @addr_limit: upper limit of the available memory area at @addr | ||
178 | + * @as: address space to load image to | ||
179 | * | ||
180 | * Load a device tree supplied by the machine or by the user with the | ||
181 | * '-dtb' command line option, and put it at offset @addr in target | ||
182 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
183 | * Note: Must not be called unless have_dtb(binfo) is true. | ||
184 | */ | ||
185 | static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
186 | - hwaddr addr_limit) | ||
187 | + hwaddr addr_limit, AddressSpace *as) | ||
188 | { | ||
189 | void *fdt = NULL; | ||
190 | int size, rc; | ||
191 | @@ -XXX,XX +XXX,XX @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
192 | /* Put the DTB into the memory map as a ROM image: this will ensure | ||
193 | * the DTB is copied again upon reset, even if addr points into RAM. | ||
194 | */ | ||
195 | - rom_add_blob_fixed("dtb", fdt, size, addr); | ||
196 | + rom_add_blob_fixed_as("dtb", fdt, size, addr, as); | ||
197 | |||
198 | g_free(fdt); | ||
199 | |||
200 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
201 | } | ||
202 | |||
203 | if (cs == first_cpu) { | ||
204 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
205 | + | ||
206 | cpu_set_pc(cs, info->loader_start); | ||
207 | |||
208 | if (!have_dtb(info)) { | ||
209 | if (old_param) { | ||
210 | - set_kernel_args_old(info); | ||
211 | + set_kernel_args_old(info, as); | ||
212 | } else { | ||
213 | - set_kernel_args(info); | ||
214 | + set_kernel_args(info, as); | ||
215 | } | ||
216 | } | ||
217 | } else { | ||
218 | @@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque) | ||
219 | |||
220 | static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
221 | uint64_t *lowaddr, uint64_t *highaddr, | ||
222 | - int elf_machine) | ||
223 | + int elf_machine, AddressSpace *as) | ||
224 | { | ||
225 | bool elf_is64; | ||
226 | union { | ||
227 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
228 | } | ||
229 | } | ||
230 | |||
231 | - ret = load_elf(info->kernel_filename, NULL, NULL, | ||
232 | - pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
233 | - 1, data_swab); | ||
234 | + ret = load_elf_as(info->kernel_filename, NULL, NULL, | ||
235 | + pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
236 | + 1, data_swab, as); | ||
237 | if (ret <= 0) { | ||
238 | /* The header loaded but the image didn't */ | ||
239 | exit(1); | ||
240 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
241 | } | ||
242 | |||
243 | static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
244 | - hwaddr *entry) | ||
245 | + hwaddr *entry, AddressSpace *as) | ||
246 | { | ||
247 | hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; | ||
248 | uint8_t *buffer; | ||
249 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
250 | } | ||
251 | |||
252 | *entry = mem_base + kernel_load_offset; | ||
253 | - rom_add_blob_fixed(filename, buffer, size, *entry); | ||
254 | + rom_add_blob_fixed_as(filename, buffer, size, *entry, as); | ||
255 | |||
256 | g_free(buffer); | ||
257 | |||
258 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
259 | ARMCPU *cpu = n->cpu; | ||
260 | struct arm_boot_info *info = | ||
261 | container_of(n, struct arm_boot_info, load_kernel_notifier); | ||
262 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
263 | |||
264 | /* The board code is not supposed to set secure_board_setup unless | ||
265 | * running its code in secure mode is actually possible, and KVM | ||
266 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
267 | * the kernel is supposed to be loaded by the bootloader), copy the | ||
268 | * DTB to the base of RAM for the bootloader to pick up. | ||
269 | */ | ||
270 | - if (load_dtb(info->loader_start, info, 0) < 0) { | ||
271 | + if (load_dtb(info->loader_start, info, 0, as) < 0) { | ||
272 | exit(1); | ||
273 | } | ||
274 | } | ||
275 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
276 | |||
277 | /* Assume that raw images are linux kernels, and ELF images are not. */ | ||
278 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | ||
279 | - &elf_high_addr, elf_machine); | ||
280 | + &elf_high_addr, elf_machine, as); | ||
281 | if (kernel_size > 0 && have_dtb(info)) { | ||
282 | /* If there is still some room left at the base of RAM, try and put | ||
283 | * the DTB there like we do for images loaded with -bios or -pflash. | ||
284 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
285 | if (elf_low_addr < info->loader_start) { | ||
286 | elf_low_addr = 0; | ||
287 | } | ||
288 | - if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { | ||
289 | + if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) { | ||
290 | exit(1); | ||
291 | } | ||
292 | } | ||
293 | } | ||
294 | entry = elf_entry; | ||
295 | if (kernel_size < 0) { | ||
296 | - kernel_size = load_uimage(info->kernel_filename, &entry, NULL, | ||
297 | - &is_linux, NULL, NULL); | ||
298 | + kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, | ||
299 | + &is_linux, NULL, NULL, as); | ||
300 | } | ||
301 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { | ||
302 | kernel_size = load_aarch64_image(info->kernel_filename, | ||
303 | - info->loader_start, &entry); | ||
304 | + info->loader_start, &entry, as); | ||
305 | is_linux = 1; | ||
306 | } else if (kernel_size < 0) { | ||
307 | /* 32-bit ARM */ | ||
308 | entry = info->loader_start + KERNEL_LOAD_ADDR; | ||
309 | - kernel_size = load_image_targphys(info->kernel_filename, entry, | ||
310 | - info->ram_size - KERNEL_LOAD_ADDR); | ||
311 | + kernel_size = load_image_targphys_as(info->kernel_filename, entry, | ||
312 | + info->ram_size - KERNEL_LOAD_ADDR, | ||
313 | + as); | ||
314 | is_linux = 1; | ||
315 | } | ||
316 | if (kernel_size < 0) { | ||
317 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
318 | uint32_t fixupcontext[FIXUP_MAX]; | ||
319 | |||
320 | if (info->initrd_filename) { | ||
321 | - initrd_size = load_ramdisk(info->initrd_filename, | ||
322 | - info->initrd_start, | ||
323 | - info->ram_size - | ||
324 | - info->initrd_start); | ||
325 | + initrd_size = load_ramdisk_as(info->initrd_filename, | ||
326 | + info->initrd_start, | ||
327 | + info->ram_size - info->initrd_start, | ||
328 | + as); | ||
329 | if (initrd_size < 0) { | ||
330 | - initrd_size = load_image_targphys(info->initrd_filename, | ||
331 | - info->initrd_start, | ||
332 | - info->ram_size - | ||
333 | - info->initrd_start); | ||
334 | + initrd_size = load_image_targphys_as(info->initrd_filename, | ||
335 | + info->initrd_start, | ||
336 | + info->ram_size - | ||
337 | + info->initrd_start, | ||
338 | + as); | ||
339 | } | ||
340 | if (initrd_size < 0) { | ||
341 | error_report("could not load initrd '%s'", | ||
342 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
343 | |||
344 | /* Place the DTB after the initrd in memory with alignment. */ | ||
345 | dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); | ||
346 | - if (load_dtb(dtb_start, info, 0) < 0) { | ||
347 | + if (load_dtb(dtb_start, info, 0, as) < 0) { | ||
348 | exit(1); | ||
349 | } | ||
350 | fixupcontext[FIXUP_ARGPTR] = dtb_start; | ||
351 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
352 | fixupcontext[FIXUP_ENTRYPOINT] = entry; | ||
353 | |||
354 | write_bootloader("bootloader", info->loader_start, | ||
355 | - primary_loader, fixupcontext); | ||
356 | + primary_loader, fixupcontext, as); | ||
357 | |||
358 | if (info->nb_cpus > 1) { | ||
359 | info->write_secondary_boot(cpu, info); | ||
360 | -- | ||
361 | 2.16.2 | ||
362 | |||
363 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Instead of loading guest images to the system address space, use the | ||
2 | CPU's address space. This is important if we're trying to load the | ||
3 | file to memory or via an alias memory region that is provided by an | ||
4 | SoC object and thus not mapped into the system address space. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/arm/armv7m.c | 17 ++++++++++++++--- | ||
12 | 1 file changed, 14 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/armv7m.c | ||
17 | +++ b/hw/arm/armv7m.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
19 | uint64_t entry; | ||
20 | uint64_t lowaddr; | ||
21 | int big_endian; | ||
22 | + AddressSpace *as; | ||
23 | + int asidx; | ||
24 | + CPUState *cs = CPU(cpu); | ||
25 | |||
26 | #ifdef TARGET_WORDS_BIGENDIAN | ||
27 | big_endian = 1; | ||
28 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
29 | exit(1); | ||
30 | } | ||
31 | |||
32 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | ||
33 | + asidx = ARMASIdx_S; | ||
34 | + } else { | ||
35 | + asidx = ARMASIdx_NS; | ||
36 | + } | ||
37 | + as = cpu_get_address_space(cs, asidx); | ||
38 | + | ||
39 | if (kernel_filename) { | ||
40 | - image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
41 | - NULL, big_endian, EM_ARM, 1, 0); | ||
42 | + image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
43 | + NULL, big_endian, EM_ARM, 1, 0, as); | ||
44 | if (image_size < 0) { | ||
45 | - image_size = load_image_targphys(kernel_filename, 0, mem_size); | ||
46 | + image_size = load_image_targphys_as(kernel_filename, 0, | ||
47 | + mem_size, as); | ||
48 | lowaddr = 0; | ||
49 | } | ||
50 | if (image_size < 0) { | ||
51 | -- | ||
52 | 2.16.2 | ||
53 | |||
54 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Create an "init-svtor" property on the armv7m container | ||
2 | object which we can forward to the CPU object. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20180220180325.29818-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | include/hw/arm/armv7m.h | 2 ++ | ||
9 | hw/arm/armv7m.c | 9 +++++++++ | ||
10 | 2 files changed, 11 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/armv7m.h | ||
15 | +++ b/include/hw/arm/armv7m.h | ||
16 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
17 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
18 | * devices will be automatically layered on top of this view.) | ||
19 | * + Property "idau": IDAU interface (forwarded to CPU object) | ||
20 | + * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) | ||
21 | */ | ||
22 | typedef struct ARMv7MState { | ||
23 | /*< private >*/ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
25 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
26 | MemoryRegion *board_memory; | ||
27 | Object *idau; | ||
28 | + uint32_t init_svtor; | ||
29 | } ARMv7MState; | ||
30 | |||
31 | #endif | ||
32 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/armv7m.c | ||
35 | +++ b/hw/arm/armv7m.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
37 | return; | ||
38 | } | ||
39 | } | ||
40 | + if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { | ||
41 | + object_property_set_uint(OBJECT(s->cpu), s->init_svtor, | ||
42 | + "init-svtor", &err); | ||
43 | + if (err != NULL) { | ||
44 | + error_propagate(errp, err); | ||
45 | + return; | ||
46 | + } | ||
47 | + } | ||
48 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
49 | if (err != NULL) { | ||
50 | error_propagate(errp, err); | ||
51 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
52 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
53 | MemoryRegion *), | ||
54 | DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
55 | + DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), | ||
56 | DEFINE_PROP_END_OF_LIST(), | ||
57 | }; | ||
58 | |||
59 | -- | ||
60 | 2.16.2 | ||
61 | |||
62 | diff view generated by jsdifflib |
1 | Add a Cortex-M33 definition. The M33 is an M profile CPU | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | which implements the ARM v8M architecture, including the | ||
3 | M profile Security Extension. | ||
4 | 2 | ||
3 | Move the code to a separate file so that we do not have to compile | ||
4 | it anymore if CONFIG_ARM_V7M is not set. | ||
5 | |||
6 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
7 | Message-id: 20240308141051.536599-2-thuth@redhat.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-9-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++ | 11 | target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++ |
10 | 1 file changed, 31 insertions(+) | 12 | target/arm/tcg/cpu32.c | 261 --------------------------------- |
13 | target/arm/meson.build | 3 + | ||
14 | target/arm/tcg/meson.build | 3 + | ||
15 | 4 files changed, 296 insertions(+), 261 deletions(-) | ||
16 | create mode 100644 target/arm/tcg/cpu-v7m.c | ||
11 | 17 | ||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 18 | diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | new file mode 100644 |
14 | --- a/target/arm/cpu.c | 20 | index XXXXXXX..XXXXXXX |
15 | +++ b/target/arm/cpu.c | 21 | --- /dev/null |
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | 22 | +++ b/target/arm/tcg/cpu-v7m.c |
17 | cpu->id_isar5 = 0x00000000; | 23 | @@ -XXX,XX +XXX,XX @@ |
18 | } | 24 | +/* |
19 | 25 | + * QEMU ARMv7-M TCG-only CPUs. | |
26 | + * | ||
27 | + * Copyright (c) 2012 SUSE LINUX Products GmbH | ||
28 | + * | ||
29 | + * This code is licensed under the GNU GPL v2 or later. | ||
30 | + * | ||
31 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
32 | + */ | ||
33 | + | ||
34 | +#include "qemu/osdep.h" | ||
35 | +#include "cpu.h" | ||
36 | +#include "hw/core/tcg-cpu-ops.h" | ||
37 | +#include "internals.h" | ||
38 | + | ||
39 | +#if !defined(CONFIG_USER_ONLY) | ||
40 | + | ||
41 | +#include "hw/intc/armv7m_nvic.h" | ||
42 | + | ||
43 | +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | ||
44 | +{ | ||
45 | + CPUClass *cc = CPU_GET_CLASS(cs); | ||
46 | + ARMCPU *cpu = ARM_CPU(cs); | ||
47 | + CPUARMState *env = &cpu->env; | ||
48 | + bool ret = false; | ||
49 | + | ||
50 | + /* | ||
51 | + * ARMv7-M interrupt masking works differently than -A or -R. | ||
52 | + * There is no FIQ/IRQ distinction. Instead of I and F bits | ||
53 | + * masking FIQ and IRQ interrupts, an exception is taken only | ||
54 | + * if it is higher priority than the current execution priority | ||
55 | + * (which depends on state like BASEPRI, FAULTMASK and the | ||
56 | + * currently active exception). | ||
57 | + */ | ||
58 | + if (interrupt_request & CPU_INTERRUPT_HARD | ||
59 | + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { | ||
60 | + cs->exception_index = EXCP_IRQ; | ||
61 | + cc->tcg_ops->do_interrupt(cs); | ||
62 | + ret = true; | ||
63 | + } | ||
64 | + return ret; | ||
65 | +} | ||
66 | + | ||
67 | +#endif /* !CONFIG_USER_ONLY */ | ||
68 | + | ||
69 | +static void cortex_m0_initfn(Object *obj) | ||
70 | +{ | ||
71 | + ARMCPU *cpu = ARM_CPU(obj); | ||
72 | + set_feature(&cpu->env, ARM_FEATURE_V6); | ||
73 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
74 | + | ||
75 | + cpu->midr = 0x410cc200; | ||
76 | + | ||
77 | + /* | ||
78 | + * These ID register values are not guest visible, because | ||
79 | + * we do not implement the Main Extension. They must be set | ||
80 | + * to values corresponding to the Cortex-M0's implemented | ||
81 | + * features, because QEMU generally controls its emulation | ||
82 | + * by looking at ID register fields. We use the same values as | ||
83 | + * for the M3. | ||
84 | + */ | ||
85 | + cpu->isar.id_pfr0 = 0x00000030; | ||
86 | + cpu->isar.id_pfr1 = 0x00000200; | ||
87 | + cpu->isar.id_dfr0 = 0x00100000; | ||
88 | + cpu->id_afr0 = 0x00000000; | ||
89 | + cpu->isar.id_mmfr0 = 0x00000030; | ||
90 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
91 | + cpu->isar.id_mmfr2 = 0x00000000; | ||
92 | + cpu->isar.id_mmfr3 = 0x00000000; | ||
93 | + cpu->isar.id_isar0 = 0x01141110; | ||
94 | + cpu->isar.id_isar1 = 0x02111000; | ||
95 | + cpu->isar.id_isar2 = 0x21112231; | ||
96 | + cpu->isar.id_isar3 = 0x01111110; | ||
97 | + cpu->isar.id_isar4 = 0x01310102; | ||
98 | + cpu->isar.id_isar5 = 0x00000000; | ||
99 | + cpu->isar.id_isar6 = 0x00000000; | ||
100 | +} | ||
101 | + | ||
102 | +static void cortex_m3_initfn(Object *obj) | ||
103 | +{ | ||
104 | + ARMCPU *cpu = ARM_CPU(obj); | ||
105 | + set_feature(&cpu->env, ARM_FEATURE_V7); | ||
106 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
107 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
108 | + cpu->midr = 0x410fc231; | ||
109 | + cpu->pmsav7_dregion = 8; | ||
110 | + cpu->isar.id_pfr0 = 0x00000030; | ||
111 | + cpu->isar.id_pfr1 = 0x00000200; | ||
112 | + cpu->isar.id_dfr0 = 0x00100000; | ||
113 | + cpu->id_afr0 = 0x00000000; | ||
114 | + cpu->isar.id_mmfr0 = 0x00000030; | ||
115 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
116 | + cpu->isar.id_mmfr2 = 0x00000000; | ||
117 | + cpu->isar.id_mmfr3 = 0x00000000; | ||
118 | + cpu->isar.id_isar0 = 0x01141110; | ||
119 | + cpu->isar.id_isar1 = 0x02111000; | ||
120 | + cpu->isar.id_isar2 = 0x21112231; | ||
121 | + cpu->isar.id_isar3 = 0x01111110; | ||
122 | + cpu->isar.id_isar4 = 0x01310102; | ||
123 | + cpu->isar.id_isar5 = 0x00000000; | ||
124 | + cpu->isar.id_isar6 = 0x00000000; | ||
125 | +} | ||
126 | + | ||
127 | +static void cortex_m4_initfn(Object *obj) | ||
128 | +{ | ||
129 | + ARMCPU *cpu = ARM_CPU(obj); | ||
130 | + | ||
131 | + set_feature(&cpu->env, ARM_FEATURE_V7); | ||
132 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
133 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
134 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
135 | + cpu->midr = 0x410fc240; /* r0p0 */ | ||
136 | + cpu->pmsav7_dregion = 8; | ||
137 | + cpu->isar.mvfr0 = 0x10110021; | ||
138 | + cpu->isar.mvfr1 = 0x11000011; | ||
139 | + cpu->isar.mvfr2 = 0x00000000; | ||
140 | + cpu->isar.id_pfr0 = 0x00000030; | ||
141 | + cpu->isar.id_pfr1 = 0x00000200; | ||
142 | + cpu->isar.id_dfr0 = 0x00100000; | ||
143 | + cpu->id_afr0 = 0x00000000; | ||
144 | + cpu->isar.id_mmfr0 = 0x00000030; | ||
145 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
146 | + cpu->isar.id_mmfr2 = 0x00000000; | ||
147 | + cpu->isar.id_mmfr3 = 0x00000000; | ||
148 | + cpu->isar.id_isar0 = 0x01141110; | ||
149 | + cpu->isar.id_isar1 = 0x02111000; | ||
150 | + cpu->isar.id_isar2 = 0x21112231; | ||
151 | + cpu->isar.id_isar3 = 0x01111110; | ||
152 | + cpu->isar.id_isar4 = 0x01310102; | ||
153 | + cpu->isar.id_isar5 = 0x00000000; | ||
154 | + cpu->isar.id_isar6 = 0x00000000; | ||
155 | +} | ||
156 | + | ||
157 | +static void cortex_m7_initfn(Object *obj) | ||
158 | +{ | ||
159 | + ARMCPU *cpu = ARM_CPU(obj); | ||
160 | + | ||
161 | + set_feature(&cpu->env, ARM_FEATURE_V7); | ||
162 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
163 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
164 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
165 | + cpu->midr = 0x411fc272; /* r1p2 */ | ||
166 | + cpu->pmsav7_dregion = 8; | ||
167 | + cpu->isar.mvfr0 = 0x10110221; | ||
168 | + cpu->isar.mvfr1 = 0x12000011; | ||
169 | + cpu->isar.mvfr2 = 0x00000040; | ||
170 | + cpu->isar.id_pfr0 = 0x00000030; | ||
171 | + cpu->isar.id_pfr1 = 0x00000200; | ||
172 | + cpu->isar.id_dfr0 = 0x00100000; | ||
173 | + cpu->id_afr0 = 0x00000000; | ||
174 | + cpu->isar.id_mmfr0 = 0x00100030; | ||
175 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
176 | + cpu->isar.id_mmfr2 = 0x01000000; | ||
177 | + cpu->isar.id_mmfr3 = 0x00000000; | ||
178 | + cpu->isar.id_isar0 = 0x01101110; | ||
179 | + cpu->isar.id_isar1 = 0x02112000; | ||
180 | + cpu->isar.id_isar2 = 0x20232231; | ||
181 | + cpu->isar.id_isar3 = 0x01111131; | ||
182 | + cpu->isar.id_isar4 = 0x01310132; | ||
183 | + cpu->isar.id_isar5 = 0x00000000; | ||
184 | + cpu->isar.id_isar6 = 0x00000000; | ||
185 | +} | ||
186 | + | ||
20 | +static void cortex_m33_initfn(Object *obj) | 187 | +static void cortex_m33_initfn(Object *obj) |
21 | +{ | 188 | +{ |
22 | + ARMCPU *cpu = ARM_CPU(obj); | 189 | + ARMCPU *cpu = ARM_CPU(obj); |
23 | + | 190 | + |
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 191 | + set_feature(&cpu->env, ARM_FEATURE_V8); |
25 | + set_feature(&cpu->env, ARM_FEATURE_M); | 192 | + set_feature(&cpu->env, ARM_FEATURE_M); |
193 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
26 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | 194 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); |
27 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 195 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); |
28 | + cpu->midr = 0x410fd213; /* r0p3 */ | 196 | + cpu->midr = 0x410fd213; /* r0p3 */ |
29 | + cpu->pmsav7_dregion = 16; | 197 | + cpu->pmsav7_dregion = 16; |
30 | + cpu->sau_sregion = 8; | 198 | + cpu->sau_sregion = 8; |
31 | + cpu->id_pfr0 = 0x00000030; | 199 | + cpu->isar.mvfr0 = 0x10110021; |
32 | + cpu->id_pfr1 = 0x00000210; | 200 | + cpu->isar.mvfr1 = 0x11000011; |
33 | + cpu->id_dfr0 = 0x00200000; | 201 | + cpu->isar.mvfr2 = 0x00000040; |
202 | + cpu->isar.id_pfr0 = 0x00000030; | ||
203 | + cpu->isar.id_pfr1 = 0x00000210; | ||
204 | + cpu->isar.id_dfr0 = 0x00200000; | ||
34 | + cpu->id_afr0 = 0x00000000; | 205 | + cpu->id_afr0 = 0x00000000; |
35 | + cpu->id_mmfr0 = 0x00101F40; | 206 | + cpu->isar.id_mmfr0 = 0x00101F40; |
36 | + cpu->id_mmfr1 = 0x00000000; | 207 | + cpu->isar.id_mmfr1 = 0x00000000; |
37 | + cpu->id_mmfr2 = 0x01000000; | 208 | + cpu->isar.id_mmfr2 = 0x01000000; |
38 | + cpu->id_mmfr3 = 0x00000000; | 209 | + cpu->isar.id_mmfr3 = 0x00000000; |
39 | + cpu->id_isar0 = 0x01101110; | 210 | + cpu->isar.id_isar0 = 0x01101110; |
40 | + cpu->id_isar1 = 0x02212000; | 211 | + cpu->isar.id_isar1 = 0x02212000; |
41 | + cpu->id_isar2 = 0x20232232; | 212 | + cpu->isar.id_isar2 = 0x20232232; |
42 | + cpu->id_isar3 = 0x01111131; | 213 | + cpu->isar.id_isar3 = 0x01111131; |
43 | + cpu->id_isar4 = 0x01310132; | 214 | + cpu->isar.id_isar4 = 0x01310132; |
44 | + cpu->id_isar5 = 0x00000000; | 215 | + cpu->isar.id_isar5 = 0x00000000; |
216 | + cpu->isar.id_isar6 = 0x00000000; | ||
45 | + cpu->clidr = 0x00000000; | 217 | + cpu->clidr = 0x00000000; |
46 | + cpu->ctr = 0x8000c000; | 218 | + cpu->ctr = 0x8000c000; |
47 | +} | 219 | +} |
48 | + | 220 | + |
49 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | 221 | +static void cortex_m55_initfn(Object *obj) |
50 | { | 222 | +{ |
51 | CPUClass *cc = CPU_CLASS(oc); | 223 | + ARMCPU *cpu = ARM_CPU(obj); |
52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | 224 | + |
53 | .class_init = arm_v7m_class_init }, | 225 | + set_feature(&cpu->env, ARM_FEATURE_V8); |
54 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, | 226 | + set_feature(&cpu->env, ARM_FEATURE_V8_1M); |
55 | .class_init = arm_v7m_class_init }, | 227 | + set_feature(&cpu->env, ARM_FEATURE_M); |
228 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
229 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
230 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
231 | + cpu->midr = 0x410fd221; /* r0p1 */ | ||
232 | + cpu->revidr = 0; | ||
233 | + cpu->pmsav7_dregion = 16; | ||
234 | + cpu->sau_sregion = 8; | ||
235 | + /* These are the MVFR* values for the FPU + full MVE configuration */ | ||
236 | + cpu->isar.mvfr0 = 0x10110221; | ||
237 | + cpu->isar.mvfr1 = 0x12100211; | ||
238 | + cpu->isar.mvfr2 = 0x00000040; | ||
239 | + cpu->isar.id_pfr0 = 0x20000030; | ||
240 | + cpu->isar.id_pfr1 = 0x00000230; | ||
241 | + cpu->isar.id_dfr0 = 0x10200000; | ||
242 | + cpu->id_afr0 = 0x00000000; | ||
243 | + cpu->isar.id_mmfr0 = 0x00111040; | ||
244 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
245 | + cpu->isar.id_mmfr2 = 0x01000000; | ||
246 | + cpu->isar.id_mmfr3 = 0x00000011; | ||
247 | + cpu->isar.id_isar0 = 0x01103110; | ||
248 | + cpu->isar.id_isar1 = 0x02212000; | ||
249 | + cpu->isar.id_isar2 = 0x20232232; | ||
250 | + cpu->isar.id_isar3 = 0x01111131; | ||
251 | + cpu->isar.id_isar4 = 0x01310132; | ||
252 | + cpu->isar.id_isar5 = 0x00000000; | ||
253 | + cpu->isar.id_isar6 = 0x00000000; | ||
254 | + cpu->clidr = 0x00000000; /* caches not implemented */ | ||
255 | + cpu->ctr = 0x8303c003; | ||
256 | +} | ||
257 | + | ||
258 | +static const TCGCPUOps arm_v7m_tcg_ops = { | ||
259 | + .initialize = arm_translate_init, | ||
260 | + .synchronize_from_tb = arm_cpu_synchronize_from_tb, | ||
261 | + .debug_excp_handler = arm_debug_excp_handler, | ||
262 | + .restore_state_to_opc = arm_restore_state_to_opc, | ||
263 | + | ||
264 | +#ifdef CONFIG_USER_ONLY | ||
265 | + .record_sigsegv = arm_cpu_record_sigsegv, | ||
266 | + .record_sigbus = arm_cpu_record_sigbus, | ||
267 | +#else | ||
268 | + .tlb_fill = arm_cpu_tlb_fill, | ||
269 | + .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, | ||
270 | + .do_interrupt = arm_v7m_cpu_do_interrupt, | ||
271 | + .do_transaction_failed = arm_cpu_do_transaction_failed, | ||
272 | + .do_unaligned_access = arm_cpu_do_unaligned_access, | ||
273 | + .adjust_watchpoint_address = arm_adjust_watchpoint_address, | ||
274 | + .debug_check_watchpoint = arm_debug_check_watchpoint, | ||
275 | + .debug_check_breakpoint = arm_debug_check_breakpoint, | ||
276 | +#endif /* !CONFIG_USER_ONLY */ | ||
277 | +}; | ||
278 | + | ||
279 | +static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
280 | +{ | ||
281 | + ARMCPUClass *acc = ARM_CPU_CLASS(oc); | ||
282 | + CPUClass *cc = CPU_CLASS(oc); | ||
283 | + | ||
284 | + acc->info = data; | ||
285 | + cc->tcg_ops = &arm_v7m_tcg_ops; | ||
286 | + cc->gdb_core_xml_file = "arm-m-profile.xml"; | ||
287 | +} | ||
288 | + | ||
289 | +static const ARMCPUInfo arm_v7m_cpus[] = { | ||
290 | + { .name = "cortex-m0", .initfn = cortex_m0_initfn, | ||
291 | + .class_init = arm_v7m_class_init }, | ||
292 | + { .name = "cortex-m3", .initfn = cortex_m3_initfn, | ||
293 | + .class_init = arm_v7m_class_init }, | ||
294 | + { .name = "cortex-m4", .initfn = cortex_m4_initfn, | ||
295 | + .class_init = arm_v7m_class_init }, | ||
296 | + { .name = "cortex-m7", .initfn = cortex_m7_initfn, | ||
297 | + .class_init = arm_v7m_class_init }, | ||
56 | + { .name = "cortex-m33", .initfn = cortex_m33_initfn, | 298 | + { .name = "cortex-m33", .initfn = cortex_m33_initfn, |
57 | + .class_init = arm_v7m_class_init }, | 299 | + .class_init = arm_v7m_class_init }, |
300 | + { .name = "cortex-m55", .initfn = cortex_m55_initfn, | ||
301 | + .class_init = arm_v7m_class_init }, | ||
302 | +}; | ||
303 | + | ||
304 | +static void arm_v7m_cpu_register_types(void) | ||
305 | +{ | ||
306 | + size_t i; | ||
307 | + | ||
308 | + for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) { | ||
309 | + arm_cpu_register(&arm_v7m_cpus[i]); | ||
310 | + } | ||
311 | +} | ||
312 | + | ||
313 | +type_init(arm_v7m_cpu_register_types) | ||
314 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/tcg/cpu32.c | ||
317 | +++ b/target/arm/tcg/cpu32.c | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | #include "hw/boards.h" | ||
320 | #endif | ||
321 | #include "cpregs.h" | ||
322 | -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) | ||
323 | -#include "hw/intc/armv7m_nvic.h" | ||
324 | -#endif | ||
325 | |||
326 | |||
327 | /* Share AArch32 -cpu max features with AArch64. */ | ||
328 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
329 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | ||
330 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
331 | |||
332 | -#if !defined(CONFIG_USER_ONLY) | ||
333 | -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | ||
334 | -{ | ||
335 | - CPUClass *cc = CPU_GET_CLASS(cs); | ||
336 | - ARMCPU *cpu = ARM_CPU(cs); | ||
337 | - CPUARMState *env = &cpu->env; | ||
338 | - bool ret = false; | ||
339 | - | ||
340 | - /* | ||
341 | - * ARMv7-M interrupt masking works differently than -A or -R. | ||
342 | - * There is no FIQ/IRQ distinction. Instead of I and F bits | ||
343 | - * masking FIQ and IRQ interrupts, an exception is taken only | ||
344 | - * if it is higher priority than the current execution priority | ||
345 | - * (which depends on state like BASEPRI, FAULTMASK and the | ||
346 | - * currently active exception). | ||
347 | - */ | ||
348 | - if (interrupt_request & CPU_INTERRUPT_HARD | ||
349 | - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { | ||
350 | - cs->exception_index = EXCP_IRQ; | ||
351 | - cc->tcg_ops->do_interrupt(cs); | ||
352 | - ret = true; | ||
353 | - } | ||
354 | - return ret; | ||
355 | -} | ||
356 | -#endif /* !CONFIG_USER_ONLY */ | ||
357 | - | ||
358 | static void arm926_initfn(Object *obj) | ||
359 | { | ||
360 | ARMCPU *cpu = ARM_CPU(obj); | ||
361 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) | ||
362 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); | ||
363 | } | ||
364 | |||
365 | -static void cortex_m0_initfn(Object *obj) | ||
366 | -{ | ||
367 | - ARMCPU *cpu = ARM_CPU(obj); | ||
368 | - set_feature(&cpu->env, ARM_FEATURE_V6); | ||
369 | - set_feature(&cpu->env, ARM_FEATURE_M); | ||
370 | - | ||
371 | - cpu->midr = 0x410cc200; | ||
372 | - | ||
373 | - /* | ||
374 | - * These ID register values are not guest visible, because | ||
375 | - * we do not implement the Main Extension. They must be set | ||
376 | - * to values corresponding to the Cortex-M0's implemented | ||
377 | - * features, because QEMU generally controls its emulation | ||
378 | - * by looking at ID register fields. We use the same values as | ||
379 | - * for the M3. | ||
380 | - */ | ||
381 | - cpu->isar.id_pfr0 = 0x00000030; | ||
382 | - cpu->isar.id_pfr1 = 0x00000200; | ||
383 | - cpu->isar.id_dfr0 = 0x00100000; | ||
384 | - cpu->id_afr0 = 0x00000000; | ||
385 | - cpu->isar.id_mmfr0 = 0x00000030; | ||
386 | - cpu->isar.id_mmfr1 = 0x00000000; | ||
387 | - cpu->isar.id_mmfr2 = 0x00000000; | ||
388 | - cpu->isar.id_mmfr3 = 0x00000000; | ||
389 | - cpu->isar.id_isar0 = 0x01141110; | ||
390 | - cpu->isar.id_isar1 = 0x02111000; | ||
391 | - cpu->isar.id_isar2 = 0x21112231; | ||
392 | - cpu->isar.id_isar3 = 0x01111110; | ||
393 | - cpu->isar.id_isar4 = 0x01310102; | ||
394 | - cpu->isar.id_isar5 = 0x00000000; | ||
395 | - cpu->isar.id_isar6 = 0x00000000; | ||
396 | -} | ||
397 | - | ||
398 | -static void cortex_m3_initfn(Object *obj) | ||
399 | -{ | ||
400 | - ARMCPU *cpu = ARM_CPU(obj); | ||
401 | - set_feature(&cpu->env, ARM_FEATURE_V7); | ||
402 | - set_feature(&cpu->env, ARM_FEATURE_M); | ||
403 | - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
404 | - cpu->midr = 0x410fc231; | ||
405 | - cpu->pmsav7_dregion = 8; | ||
406 | - cpu->isar.id_pfr0 = 0x00000030; | ||
407 | - cpu->isar.id_pfr1 = 0x00000200; | ||
408 | - cpu->isar.id_dfr0 = 0x00100000; | ||
409 | - cpu->id_afr0 = 0x00000000; | ||
410 | - cpu->isar.id_mmfr0 = 0x00000030; | ||
411 | - cpu->isar.id_mmfr1 = 0x00000000; | ||
412 | - cpu->isar.id_mmfr2 = 0x00000000; | ||
413 | - cpu->isar.id_mmfr3 = 0x00000000; | ||
414 | - cpu->isar.id_isar0 = 0x01141110; | ||
415 | - cpu->isar.id_isar1 = 0x02111000; | ||
416 | - cpu->isar.id_isar2 = 0x21112231; | ||
417 | - cpu->isar.id_isar3 = 0x01111110; | ||
418 | - cpu->isar.id_isar4 = 0x01310102; | ||
419 | - cpu->isar.id_isar5 = 0x00000000; | ||
420 | - cpu->isar.id_isar6 = 0x00000000; | ||
421 | -} | ||
422 | - | ||
423 | -static void cortex_m4_initfn(Object *obj) | ||
424 | -{ | ||
425 | - ARMCPU *cpu = ARM_CPU(obj); | ||
426 | - | ||
427 | - set_feature(&cpu->env, ARM_FEATURE_V7); | ||
428 | - set_feature(&cpu->env, ARM_FEATURE_M); | ||
429 | - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
430 | - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
431 | - cpu->midr = 0x410fc240; /* r0p0 */ | ||
432 | - cpu->pmsav7_dregion = 8; | ||
433 | - cpu->isar.mvfr0 = 0x10110021; | ||
434 | - cpu->isar.mvfr1 = 0x11000011; | ||
435 | - cpu->isar.mvfr2 = 0x00000000; | ||
436 | - cpu->isar.id_pfr0 = 0x00000030; | ||
437 | - cpu->isar.id_pfr1 = 0x00000200; | ||
438 | - cpu->isar.id_dfr0 = 0x00100000; | ||
439 | - cpu->id_afr0 = 0x00000000; | ||
440 | - cpu->isar.id_mmfr0 = 0x00000030; | ||
441 | - cpu->isar.id_mmfr1 = 0x00000000; | ||
442 | - cpu->isar.id_mmfr2 = 0x00000000; | ||
443 | - cpu->isar.id_mmfr3 = 0x00000000; | ||
444 | - cpu->isar.id_isar0 = 0x01141110; | ||
445 | - cpu->isar.id_isar1 = 0x02111000; | ||
446 | - cpu->isar.id_isar2 = 0x21112231; | ||
447 | - cpu->isar.id_isar3 = 0x01111110; | ||
448 | - cpu->isar.id_isar4 = 0x01310102; | ||
449 | - cpu->isar.id_isar5 = 0x00000000; | ||
450 | - cpu->isar.id_isar6 = 0x00000000; | ||
451 | -} | ||
452 | - | ||
453 | -static void cortex_m7_initfn(Object *obj) | ||
454 | -{ | ||
455 | - ARMCPU *cpu = ARM_CPU(obj); | ||
456 | - | ||
457 | - set_feature(&cpu->env, ARM_FEATURE_V7); | ||
458 | - set_feature(&cpu->env, ARM_FEATURE_M); | ||
459 | - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
460 | - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
461 | - cpu->midr = 0x411fc272; /* r1p2 */ | ||
462 | - cpu->pmsav7_dregion = 8; | ||
463 | - cpu->isar.mvfr0 = 0x10110221; | ||
464 | - cpu->isar.mvfr1 = 0x12000011; | ||
465 | - cpu->isar.mvfr2 = 0x00000040; | ||
466 | - cpu->isar.id_pfr0 = 0x00000030; | ||
467 | - cpu->isar.id_pfr1 = 0x00000200; | ||
468 | - cpu->isar.id_dfr0 = 0x00100000; | ||
469 | - cpu->id_afr0 = 0x00000000; | ||
470 | - cpu->isar.id_mmfr0 = 0x00100030; | ||
471 | - cpu->isar.id_mmfr1 = 0x00000000; | ||
472 | - cpu->isar.id_mmfr2 = 0x01000000; | ||
473 | - cpu->isar.id_mmfr3 = 0x00000000; | ||
474 | - cpu->isar.id_isar0 = 0x01101110; | ||
475 | - cpu->isar.id_isar1 = 0x02112000; | ||
476 | - cpu->isar.id_isar2 = 0x20232231; | ||
477 | - cpu->isar.id_isar3 = 0x01111131; | ||
478 | - cpu->isar.id_isar4 = 0x01310132; | ||
479 | - cpu->isar.id_isar5 = 0x00000000; | ||
480 | - cpu->isar.id_isar6 = 0x00000000; | ||
481 | -} | ||
482 | - | ||
483 | -static void cortex_m33_initfn(Object *obj) | ||
484 | -{ | ||
485 | - ARMCPU *cpu = ARM_CPU(obj); | ||
486 | - | ||
487 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
488 | - set_feature(&cpu->env, ARM_FEATURE_M); | ||
489 | - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
490 | - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
491 | - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
492 | - cpu->midr = 0x410fd213; /* r0p3 */ | ||
493 | - cpu->pmsav7_dregion = 16; | ||
494 | - cpu->sau_sregion = 8; | ||
495 | - cpu->isar.mvfr0 = 0x10110021; | ||
496 | - cpu->isar.mvfr1 = 0x11000011; | ||
497 | - cpu->isar.mvfr2 = 0x00000040; | ||
498 | - cpu->isar.id_pfr0 = 0x00000030; | ||
499 | - cpu->isar.id_pfr1 = 0x00000210; | ||
500 | - cpu->isar.id_dfr0 = 0x00200000; | ||
501 | - cpu->id_afr0 = 0x00000000; | ||
502 | - cpu->isar.id_mmfr0 = 0x00101F40; | ||
503 | - cpu->isar.id_mmfr1 = 0x00000000; | ||
504 | - cpu->isar.id_mmfr2 = 0x01000000; | ||
505 | - cpu->isar.id_mmfr3 = 0x00000000; | ||
506 | - cpu->isar.id_isar0 = 0x01101110; | ||
507 | - cpu->isar.id_isar1 = 0x02212000; | ||
508 | - cpu->isar.id_isar2 = 0x20232232; | ||
509 | - cpu->isar.id_isar3 = 0x01111131; | ||
510 | - cpu->isar.id_isar4 = 0x01310132; | ||
511 | - cpu->isar.id_isar5 = 0x00000000; | ||
512 | - cpu->isar.id_isar6 = 0x00000000; | ||
513 | - cpu->clidr = 0x00000000; | ||
514 | - cpu->ctr = 0x8000c000; | ||
515 | -} | ||
516 | - | ||
517 | -static void cortex_m55_initfn(Object *obj) | ||
518 | -{ | ||
519 | - ARMCPU *cpu = ARM_CPU(obj); | ||
520 | - | ||
521 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
522 | - set_feature(&cpu->env, ARM_FEATURE_V8_1M); | ||
523 | - set_feature(&cpu->env, ARM_FEATURE_M); | ||
524 | - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
525 | - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
526 | - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
527 | - cpu->midr = 0x410fd221; /* r0p1 */ | ||
528 | - cpu->revidr = 0; | ||
529 | - cpu->pmsav7_dregion = 16; | ||
530 | - cpu->sau_sregion = 8; | ||
531 | - /* These are the MVFR* values for the FPU + full MVE configuration */ | ||
532 | - cpu->isar.mvfr0 = 0x10110221; | ||
533 | - cpu->isar.mvfr1 = 0x12100211; | ||
534 | - cpu->isar.mvfr2 = 0x00000040; | ||
535 | - cpu->isar.id_pfr0 = 0x20000030; | ||
536 | - cpu->isar.id_pfr1 = 0x00000230; | ||
537 | - cpu->isar.id_dfr0 = 0x10200000; | ||
538 | - cpu->id_afr0 = 0x00000000; | ||
539 | - cpu->isar.id_mmfr0 = 0x00111040; | ||
540 | - cpu->isar.id_mmfr1 = 0x00000000; | ||
541 | - cpu->isar.id_mmfr2 = 0x01000000; | ||
542 | - cpu->isar.id_mmfr3 = 0x00000011; | ||
543 | - cpu->isar.id_isar0 = 0x01103110; | ||
544 | - cpu->isar.id_isar1 = 0x02212000; | ||
545 | - cpu->isar.id_isar2 = 0x20232232; | ||
546 | - cpu->isar.id_isar3 = 0x01111131; | ||
547 | - cpu->isar.id_isar4 = 0x01310132; | ||
548 | - cpu->isar.id_isar5 = 0x00000000; | ||
549 | - cpu->isar.id_isar6 = 0x00000000; | ||
550 | - cpu->clidr = 0x00000000; /* caches not implemented */ | ||
551 | - cpu->ctr = 0x8303c003; | ||
552 | -} | ||
553 | - | ||
554 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { | ||
555 | /* Dummy the TCM region regs for the moment */ | ||
556 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | ||
557 | @@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj) | ||
558 | cpu->reset_sctlr = 0x00000078; | ||
559 | } | ||
560 | |||
561 | -static const TCGCPUOps arm_v7m_tcg_ops = { | ||
562 | - .initialize = arm_translate_init, | ||
563 | - .synchronize_from_tb = arm_cpu_synchronize_from_tb, | ||
564 | - .debug_excp_handler = arm_debug_excp_handler, | ||
565 | - .restore_state_to_opc = arm_restore_state_to_opc, | ||
566 | - | ||
567 | -#ifdef CONFIG_USER_ONLY | ||
568 | - .record_sigsegv = arm_cpu_record_sigsegv, | ||
569 | - .record_sigbus = arm_cpu_record_sigbus, | ||
570 | -#else | ||
571 | - .tlb_fill = arm_cpu_tlb_fill, | ||
572 | - .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, | ||
573 | - .do_interrupt = arm_v7m_cpu_do_interrupt, | ||
574 | - .do_transaction_failed = arm_cpu_do_transaction_failed, | ||
575 | - .do_unaligned_access = arm_cpu_do_unaligned_access, | ||
576 | - .adjust_watchpoint_address = arm_adjust_watchpoint_address, | ||
577 | - .debug_check_watchpoint = arm_debug_check_watchpoint, | ||
578 | - .debug_check_breakpoint = arm_debug_check_breakpoint, | ||
579 | -#endif /* !CONFIG_USER_ONLY */ | ||
580 | -}; | ||
581 | - | ||
582 | -static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
583 | -{ | ||
584 | - ARMCPUClass *acc = ARM_CPU_CLASS(oc); | ||
585 | - CPUClass *cc = CPU_CLASS(oc); | ||
586 | - | ||
587 | - acc->info = data; | ||
588 | - cc->tcg_ops = &arm_v7m_tcg_ops; | ||
589 | - cc->gdb_core_xml_file = "arm-m-profile.xml"; | ||
590 | -} | ||
591 | - | ||
592 | #ifndef TARGET_AARCH64 | ||
593 | /* | ||
594 | * -cpu max: a CPU with as many features enabled as our emulation supports. | ||
595 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = { | ||
596 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | ||
597 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | ||
598 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | ||
599 | - { .name = "cortex-m0", .initfn = cortex_m0_initfn, | ||
600 | - .class_init = arm_v7m_class_init }, | ||
601 | - { .name = "cortex-m3", .initfn = cortex_m3_initfn, | ||
602 | - .class_init = arm_v7m_class_init }, | ||
603 | - { .name = "cortex-m4", .initfn = cortex_m4_initfn, | ||
604 | - .class_init = arm_v7m_class_init }, | ||
605 | - { .name = "cortex-m7", .initfn = cortex_m7_initfn, | ||
606 | - .class_init = arm_v7m_class_init }, | ||
607 | - { .name = "cortex-m33", .initfn = cortex_m33_initfn, | ||
608 | - .class_init = arm_v7m_class_init }, | ||
609 | - { .name = "cortex-m55", .initfn = cortex_m55_initfn, | ||
610 | - .class_init = arm_v7m_class_init }, | ||
58 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | 611 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
59 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, | 612 | { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, |
60 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | 613 | { .name = "cortex-r52", .initfn = cortex_r52_initfn }, |
614 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
615 | index XXXXXXX..XXXXXXX 100644 | ||
616 | --- a/target/arm/meson.build | ||
617 | +++ b/target/arm/meson.build | ||
618 | @@ -XXX,XX +XXX,XX @@ arm_system_ss.add(files( | ||
619 | 'ptw.c', | ||
620 | )) | ||
621 | |||
622 | +arm_user_ss = ss.source_set() | ||
623 | + | ||
624 | subdir('hvf') | ||
625 | |||
626 | if 'CONFIG_TCG' in config_all_accel | ||
627 | @@ -XXX,XX +XXX,XX @@ endif | ||
628 | |||
629 | target_arch += {'arm': arm_ss} | ||
630 | target_system_arch += {'arm': arm_system_ss} | ||
631 | +target_user_arch += {'arm': arm_user_ss} | ||
632 | diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build | ||
633 | index XXXXXXX..XXXXXXX 100644 | ||
634 | --- a/target/arm/tcg/meson.build | ||
635 | +++ b/target/arm/tcg/meson.build | ||
636 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( | ||
637 | arm_system_ss.add(files( | ||
638 | 'psci.c', | ||
639 | )) | ||
640 | + | ||
641 | +arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) | ||
642 | +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) | ||
61 | -- | 643 | -- |
62 | 2.16.2 | 644 | 2.34.1 |
63 | |||
64 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the definition of the struct for the unimplemented-device | ||
2 | from unimp.c to unimp.h, so that users can embed the struct | ||
3 | in their own device structs if they prefer. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-10-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/misc/unimp.h | 10 ++++++++++ | ||
11 | hw/misc/unimp.c | 10 ---------- | ||
12 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/misc/unimp.h | ||
17 | +++ b/include/hw/misc/unimp.h | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" | ||
21 | |||
22 | +#define UNIMPLEMENTED_DEVICE(obj) \ | ||
23 | + OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
24 | + | ||
25 | +typedef struct { | ||
26 | + SysBusDevice parent_obj; | ||
27 | + MemoryRegion iomem; | ||
28 | + char *name; | ||
29 | + uint64_t size; | ||
30 | +} UnimplementedDeviceState; | ||
31 | + | ||
32 | /** | ||
33 | * create_unimplemented_device: create and map a dummy device | ||
34 | * @name: name of the device for debug logging | ||
35 | diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/misc/unimp.c | ||
38 | +++ b/hw/misc/unimp.c | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | #include "qemu/log.h" | ||
41 | #include "qapi/error.h" | ||
42 | |||
43 | -#define UNIMPLEMENTED_DEVICE(obj) \ | ||
44 | - OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
45 | - | ||
46 | -typedef struct { | ||
47 | - SysBusDevice parent_obj; | ||
48 | - MemoryRegion iomem; | ||
49 | - char *name; | ||
50 | - uint64_t size; | ||
51 | -} UnimplementedDeviceState; | ||
52 | - | ||
53 | static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size) | ||
54 | { | ||
55 | UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
56 | -- | ||
57 | 2.16.2 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The or-irq.h header file is missing the customary guard against | ||
2 | multiple inclusion, which means compilation fails if it gets | ||
3 | included twice. Fix the omission. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-11-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/or-irq.h | 5 +++++ | ||
11 | 1 file changed, 5 insertions(+) | ||
12 | |||
13 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/or-irq.h | ||
16 | +++ b/include/hw/or-irq.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * THE SOFTWARE. | ||
19 | */ | ||
20 | |||
21 | +#ifndef HW_OR_IRQ_H | ||
22 | +#define HW_OR_IRQ_H | ||
23 | + | ||
24 | #include "hw/irq.h" | ||
25 | #include "hw/sysbus.h" | ||
26 | #include "qom/object.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct OrIRQState { | ||
28 | bool levels[MAX_OR_LINES]; | ||
29 | uint16_t num_lines; | ||
30 | }; | ||
31 | + | ||
32 | +#endif | ||
33 | -- | ||
34 | 2.16.2 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The function qdev_init_gpio_in_named() passes the DeviceState pointer | ||
2 | as the opaque data pointor for the irq handler function. Usually | ||
3 | this is what you want, but in some cases it would be helpful to use | ||
4 | some other data pointer. | ||
5 | 1 | ||
6 | Add a new function qdev_init_gpio_in_named_with_opaque() which allows | ||
7 | the caller to specify the data pointer they want. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180220180325.29818-12-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/hw/qdev-core.h | 30 ++++++++++++++++++++++++++++-- | ||
15 | hw/core/qdev.c | 8 +++++--- | ||
16 | 2 files changed, 33 insertions(+), 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/qdev-core.h | ||
21 | +++ b/include/hw/qdev-core.h | ||
22 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
23 | /* GPIO inputs also double as IRQ sinks. */ | ||
24 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
25 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
26 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
27 | - const char *name, int n); | ||
28 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
29 | const char *name, int n); | ||
30 | +/** | ||
31 | + * qdev_init_gpio_in_named_with_opaque: create an array of input GPIO lines | ||
32 | + * for the specified device | ||
33 | + * | ||
34 | + * @dev: Device to create input GPIOs for | ||
35 | + * @handler: Function to call when GPIO line value is set | ||
36 | + * @opaque: Opaque data pointer to pass to @handler | ||
37 | + * @name: Name of the GPIO input (must be unique for this device) | ||
38 | + * @n: Number of GPIO lines in this input set | ||
39 | + */ | ||
40 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
41 | + qemu_irq_handler handler, | ||
42 | + void *opaque, | ||
43 | + const char *name, int n); | ||
44 | + | ||
45 | +/** | ||
46 | + * qdev_init_gpio_in_named: create an array of input GPIO lines | ||
47 | + * for the specified device | ||
48 | + * | ||
49 | + * Like qdev_init_gpio_in_named_with_opaque(), but the opaque pointer | ||
50 | + * passed to the handler is @dev (which is the most commonly desired behaviour). | ||
51 | + */ | ||
52 | +static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
53 | + qemu_irq_handler handler, | ||
54 | + const char *name, int n) | ||
55 | +{ | ||
56 | + qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
57 | +} | ||
58 | |||
59 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
60 | const char *name); | ||
61 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/core/qdev.c | ||
64 | +++ b/hw/core/qdev.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, | ||
66 | return ngl; | ||
67 | } | ||
68 | |||
69 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
70 | - const char *name, int n) | ||
71 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
72 | + qemu_irq_handler handler, | ||
73 | + void *opaque, | ||
74 | + const char *name, int n) | ||
75 | { | ||
76 | int i; | ||
77 | NamedGPIOList *gpio_list = qdev_get_named_gpio_list(dev, name); | ||
78 | |||
79 | assert(gpio_list->num_out == 0 || !name); | ||
80 | gpio_list->in = qemu_extend_irqs(gpio_list->in, gpio_list->num_in, handler, | ||
81 | - dev, n); | ||
82 | + opaque, n); | ||
83 | |||
84 | if (!name) { | ||
85 | name = "unnamed-gpio-in"; | ||
86 | -- | ||
87 | 2.16.2 | ||
88 | |||
89 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add remaining easy registers to iotkit-secctl: | ||
2 | * NSCCFG just routes its two bits out to external GPIO lines | ||
3 | * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's | ||
4 | bus fabric can never report errors | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180220180325.29818-18-peter.maydell@linaro.org | ||
8 | --- | ||
9 | include/hw/misc/iotkit-secctl.h | 4 ++++ | ||
10 | hw/misc/iotkit-secctl.c | 32 ++++++++++++++++++++++++++------ | ||
11 | 2 files changed, 30 insertions(+), 6 deletions(-) | ||
12 | |||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/misc/iotkit-secctl.h | ||
16 | +++ b/include/hw/misc/iotkit-secctl.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
19 | * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | ||
20 | * should RAZ/WI or bus error | ||
21 | + * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value | ||
22 | * Controlling the 2 APB PPCs in the IoTKit: | ||
23 | * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
24 | * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
25 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
26 | |||
27 | /*< public >*/ | ||
28 | qemu_irq sec_resp_cfg; | ||
29 | + qemu_irq nsc_cfg_irq; | ||
30 | |||
31 | MemoryRegion s_regs; | ||
32 | MemoryRegion ns_regs; | ||
33 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
34 | uint32_t secppcintstat; | ||
35 | uint32_t secppcinten; | ||
36 | uint32_t secrespcfg; | ||
37 | + uint32_t nsccfg; | ||
38 | + uint32_t brginten; | ||
39 | |||
40 | IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
41 | IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
42 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/misc/iotkit-secctl.c | ||
45 | +++ b/hw/misc/iotkit-secctl.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
47 | case A_SECRESPCFG: | ||
48 | r = s->secrespcfg; | ||
49 | break; | ||
50 | + case A_NSCCFG: | ||
51 | + r = s->nsccfg; | ||
52 | + break; | ||
53 | case A_SECPPCINTSTAT: | ||
54 | r = s->secppcintstat; | ||
55 | break; | ||
56 | case A_SECPPCINTEN: | ||
57 | r = s->secppcinten; | ||
58 | break; | ||
59 | + case A_BRGINTSTAT: | ||
60 | + /* QEMU's bus fabric can never report errors as it doesn't buffer | ||
61 | + * writes, so we never report bridge interrupts. | ||
62 | + */ | ||
63 | + r = 0; | ||
64 | + break; | ||
65 | + case A_BRGINTEN: | ||
66 | + r = s->brginten; | ||
67 | + break; | ||
68 | case A_AHBNSPPCEXP0: | ||
69 | case A_AHBNSPPCEXP1: | ||
70 | case A_AHBNSPPCEXP2: | ||
71 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
72 | case A_APBSPPPCEXP3: | ||
73 | r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
74 | break; | ||
75 | - case A_NSCCFG: | ||
76 | case A_SECMPCINTSTATUS: | ||
77 | case A_SECMSCINTSTAT: | ||
78 | case A_SECMSCINTEN: | ||
79 | - case A_BRGINTSTAT: | ||
80 | - case A_BRGINTEN: | ||
81 | case A_NSMSCEXP: | ||
82 | qemu_log_mask(LOG_UNIMP, | ||
83 | "IoTKit SecCtl S block read: " | ||
84 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
85 | } | ||
86 | |||
87 | switch (offset) { | ||
88 | + case A_NSCCFG: | ||
89 | + s->nsccfg = value & 3; | ||
90 | + qemu_set_irq(s->nsc_cfg_irq, s->nsccfg); | ||
91 | + break; | ||
92 | case A_SECRESPCFG: | ||
93 | value &= 1; | ||
94 | s->secrespcfg = value; | ||
95 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
96 | s->secppcinten = value & 0x00f000f3; | ||
97 | foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
98 | break; | ||
99 | + case A_BRGINTCLR: | ||
100 | + break; | ||
101 | + case A_BRGINTEN: | ||
102 | + s->brginten = value & 0xffff0000; | ||
103 | + break; | ||
104 | case A_AHBNSPPCEXP0: | ||
105 | case A_AHBNSPPCEXP1: | ||
106 | case A_AHBNSPPCEXP2: | ||
107 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
108 | ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
109 | iotkit_secctl_ppc_sp_write(ppc, value); | ||
110 | break; | ||
111 | - case A_NSCCFG: | ||
112 | case A_SECMSCINTCLR: | ||
113 | case A_SECMSCINTEN: | ||
114 | - case A_BRGINTCLR: | ||
115 | - case A_BRGINTEN: | ||
116 | qemu_log_mask(LOG_UNIMP, | ||
117 | "IoTKit SecCtl S block write: " | ||
118 | "unimplemented offset 0x%x\n", offset); | ||
119 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_reset(DeviceState *dev) | ||
120 | s->secppcintstat = 0; | ||
121 | s->secppcinten = 0; | ||
122 | s->secrespcfg = 0; | ||
123 | + s->nsccfg = 0; | ||
124 | + s->brginten = 0; | ||
125 | |||
126 | foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
127 | } | ||
128 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
129 | } | ||
130 | |||
131 | qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
132 | + qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); | ||
133 | |||
134 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
135 | s, "iotkit-secctl-s-regs", 0x1000); | ||
136 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_vmstate = { | ||
137 | VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
138 | VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
139 | VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
140 | + VMSTATE_UINT32(nsccfg, IoTKitSecCtl), | ||
141 | + VMSTATE_UINT32(brginten, IoTKitSecCtl), | ||
142 | VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
143 | iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
144 | VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
145 | -- | ||
146 | 2.16.2 | ||
147 | |||
148 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Model the Arm IoT Kit documented in | ||
2 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
3 | 1 | ||
4 | The Arm IoT Kit is a subsystem which includes a CPU and some devices, | ||
5 | and is intended be extended by adding extra devices to form a | ||
6 | complete system. It is used in the MPS2 board's AN505 image for the | ||
7 | Cortex-M33. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20180220180325.29818-19-peter.maydell@linaro.org | ||
12 | --- | ||
13 | hw/arm/Makefile.objs | 1 + | ||
14 | include/hw/arm/iotkit.h | 109 ++++++++ | ||
15 | hw/arm/iotkit.c | 598 ++++++++++++++++++++++++++++++++++++++++ | ||
16 | default-configs/arm-softmmu.mak | 1 + | ||
17 | 4 files changed, 709 insertions(+) | ||
18 | create mode 100644 include/hw/arm/iotkit.h | ||
19 | create mode 100644 hw/arm/iotkit.c | ||
20 | |||
21 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/arm/Makefile.objs | ||
24 | +++ b/hw/arm/Makefile.objs | ||
25 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | ||
26 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | ||
27 | obj-$(CONFIG_MPS2) += mps2.o | ||
28 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | ||
29 | +obj-$(CONFIG_IOTKIT) += iotkit.o | ||
30 | diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h | ||
31 | new file mode 100644 | ||
32 | index XXXXXXX..XXXXXXX | ||
33 | --- /dev/null | ||
34 | +++ b/include/hw/arm/iotkit.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | +/* | ||
37 | + * ARM IoT Kit | ||
38 | + * | ||
39 | + * Copyright (c) 2018 Linaro Limited | ||
40 | + * Written by Peter Maydell | ||
41 | + * | ||
42 | + * This program is free software; you can redistribute it and/or modify | ||
43 | + * it under the terms of the GNU General Public License version 2 or | ||
44 | + * (at your option) any later version. | ||
45 | + */ | ||
46 | + | ||
47 | +/* This is a model of the Arm IoT Kit which is documented in | ||
48 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
49 | + * It contains: | ||
50 | + * a Cortex-M33 | ||
51 | + * the IDAU | ||
52 | + * some timers and watchdogs | ||
53 | + * two peripheral protection controllers | ||
54 | + * a memory protection controller | ||
55 | + * a security controller | ||
56 | + * a bus fabric which arranges that some parts of the address | ||
57 | + * space are secure and non-secure aliases of each other | ||
58 | + * | ||
59 | + * QEMU interface: | ||
60 | + * + QOM property "memory" is a MemoryRegion containing the devices provided | ||
61 | + * by the board model. | ||
62 | + * + QOM property "MAINCLK" is the frequency of the main system clock | ||
63 | + * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts | ||
64 | + * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which | ||
65 | + * are wired to the NVIC lines 32 .. n+32 | ||
66 | + * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit | ||
67 | + * might provide: | ||
68 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
69 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
70 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
71 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
72 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
73 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
74 | + * might provide: | ||
75 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
76 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
77 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
78 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
79 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
80 | + */ | ||
81 | + | ||
82 | +#ifndef IOTKIT_H | ||
83 | +#define IOTKIT_H | ||
84 | + | ||
85 | +#include "hw/sysbus.h" | ||
86 | +#include "hw/arm/armv7m.h" | ||
87 | +#include "hw/misc/iotkit-secctl.h" | ||
88 | +#include "hw/misc/tz-ppc.h" | ||
89 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
90 | +#include "hw/misc/unimp.h" | ||
91 | +#include "hw/or-irq.h" | ||
92 | +#include "hw/core/split-irq.h" | ||
93 | + | ||
94 | +#define TYPE_IOTKIT "iotkit" | ||
95 | +#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) | ||
96 | + | ||
97 | +/* We have an IRQ splitter and an OR gate input for each external PPC | ||
98 | + * and the 2 internal PPCs | ||
99 | + */ | ||
100 | +#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) | ||
101 | +#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) | ||
102 | + | ||
103 | +typedef struct IoTKit { | ||
104 | + /*< private >*/ | ||
105 | + SysBusDevice parent_obj; | ||
106 | + | ||
107 | + /*< public >*/ | ||
108 | + ARMv7MState armv7m; | ||
109 | + IoTKitSecCtl secctl; | ||
110 | + TZPPC apb_ppc0; | ||
111 | + TZPPC apb_ppc1; | ||
112 | + CMSDKAPBTIMER timer0; | ||
113 | + CMSDKAPBTIMER timer1; | ||
114 | + qemu_or_irq ppc_irq_orgate; | ||
115 | + SplitIRQ sec_resp_splitter; | ||
116 | + SplitIRQ ppc_irq_splitter[NUM_PPCS]; | ||
117 | + | ||
118 | + UnimplementedDeviceState dualtimer; | ||
119 | + UnimplementedDeviceState s32ktimer; | ||
120 | + | ||
121 | + MemoryRegion container; | ||
122 | + MemoryRegion alias1; | ||
123 | + MemoryRegion alias2; | ||
124 | + MemoryRegion alias3; | ||
125 | + MemoryRegion sram0; | ||
126 | + | ||
127 | + qemu_irq *exp_irqs; | ||
128 | + qemu_irq ppc0_irq; | ||
129 | + qemu_irq ppc1_irq; | ||
130 | + qemu_irq sec_resp_cfg; | ||
131 | + qemu_irq sec_resp_cfg_in; | ||
132 | + qemu_irq nsc_cfg_in; | ||
133 | + | ||
134 | + qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; | ||
135 | + | ||
136 | + uint32_t nsccfg; | ||
137 | + | ||
138 | + /* Properties */ | ||
139 | + MemoryRegion *board_memory; | ||
140 | + uint32_t exp_numirq; | ||
141 | + uint32_t mainclk_frq; | ||
142 | +} IoTKit; | ||
143 | + | ||
144 | +#endif | ||
145 | diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c | ||
146 | new file mode 100644 | ||
147 | index XXXXXXX..XXXXXXX | ||
148 | --- /dev/null | ||
149 | +++ b/hw/arm/iotkit.c | ||
150 | @@ -XXX,XX +XXX,XX @@ | ||
151 | +/* | ||
152 | + * Arm IoT Kit | ||
153 | + * | ||
154 | + * Copyright (c) 2018 Linaro Limited | ||
155 | + * Written by Peter Maydell | ||
156 | + * | ||
157 | + * This program is free software; you can redistribute it and/or modify | ||
158 | + * it under the terms of the GNU General Public License version 2 or | ||
159 | + * (at your option) any later version. | ||
160 | + */ | ||
161 | + | ||
162 | +#include "qemu/osdep.h" | ||
163 | +#include "qemu/log.h" | ||
164 | +#include "qapi/error.h" | ||
165 | +#include "trace.h" | ||
166 | +#include "hw/sysbus.h" | ||
167 | +#include "hw/registerfields.h" | ||
168 | +#include "hw/arm/iotkit.h" | ||
169 | +#include "hw/misc/unimp.h" | ||
170 | +#include "hw/arm/arm.h" | ||
171 | + | ||
172 | +/* Create an alias region of @size bytes starting at @base | ||
173 | + * which mirrors the memory starting at @orig. | ||
174 | + */ | ||
175 | +static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, | ||
176 | + hwaddr base, hwaddr size, hwaddr orig) | ||
177 | +{ | ||
178 | + memory_region_init_alias(mr, NULL, name, &s->container, orig, size); | ||
179 | + /* The alias is even lower priority than unimplemented_device regions */ | ||
180 | + memory_region_add_subregion_overlap(&s->container, base, mr, -1500); | ||
181 | +} | ||
182 | + | ||
183 | +static void init_sysbus_child(Object *parent, const char *childname, | ||
184 | + void *child, size_t childsize, | ||
185 | + const char *childtype) | ||
186 | +{ | ||
187 | + object_initialize(child, childsize, childtype); | ||
188 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | ||
189 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
190 | +} | ||
191 | + | ||
192 | +static void irq_status_forwarder(void *opaque, int n, int level) | ||
193 | +{ | ||
194 | + qemu_irq destirq = opaque; | ||
195 | + | ||
196 | + qemu_set_irq(destirq, level); | ||
197 | +} | ||
198 | + | ||
199 | +static void nsccfg_handler(void *opaque, int n, int level) | ||
200 | +{ | ||
201 | + IoTKit *s = IOTKIT(opaque); | ||
202 | + | ||
203 | + s->nsccfg = level; | ||
204 | +} | ||
205 | + | ||
206 | +static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) | ||
207 | +{ | ||
208 | + /* Each of the 4 AHB and 4 APB PPCs that might be present in a | ||
209 | + * system using the IoTKit has a collection of control lines which | ||
210 | + * are provided by the security controller and which we want to | ||
211 | + * expose as control lines on the IoTKit device itself, so the | ||
212 | + * code using the IoTKit can wire them up to the PPCs. | ||
213 | + */ | ||
214 | + SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; | ||
215 | + DeviceState *iotkitdev = DEVICE(s); | ||
216 | + DeviceState *dev_secctl = DEVICE(&s->secctl); | ||
217 | + DeviceState *dev_splitter = DEVICE(splitter); | ||
218 | + char *name; | ||
219 | + | ||
220 | + name = g_strdup_printf("%s_nonsec", ppcname); | ||
221 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
222 | + g_free(name); | ||
223 | + name = g_strdup_printf("%s_ap", ppcname); | ||
224 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
225 | + g_free(name); | ||
226 | + name = g_strdup_printf("%s_irq_enable", ppcname); | ||
227 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
228 | + g_free(name); | ||
229 | + name = g_strdup_printf("%s_irq_clear", ppcname); | ||
230 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
231 | + g_free(name); | ||
232 | + | ||
233 | + /* irq_status is a little more tricky, because we need to | ||
234 | + * split it so we can send it both to the security controller | ||
235 | + * and to our OR gate for the NVIC interrupt line. | ||
236 | + * Connect up the splitter's outputs, and create a GPIO input | ||
237 | + * which will pass the line state to the input splitter. | ||
238 | + */ | ||
239 | + name = g_strdup_printf("%s_irq_status", ppcname); | ||
240 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
241 | + qdev_get_gpio_in_named(dev_secctl, | ||
242 | + name, 0)); | ||
243 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
244 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); | ||
245 | + s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); | ||
246 | + qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, | ||
247 | + s->irq_status_in[ppcnum], name, 1); | ||
248 | + g_free(name); | ||
249 | +} | ||
250 | + | ||
251 | +static void iotkit_forward_sec_resp_cfg(IoTKit *s) | ||
252 | +{ | ||
253 | + /* Forward the 3rd output from the splitter device as a | ||
254 | + * named GPIO output of the iotkit object. | ||
255 | + */ | ||
256 | + DeviceState *dev = DEVICE(s); | ||
257 | + DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
258 | + | ||
259 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
260 | + s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, | ||
261 | + s->sec_resp_cfg, 1); | ||
262 | + qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); | ||
263 | +} | ||
264 | + | ||
265 | +static void iotkit_init(Object *obj) | ||
266 | +{ | ||
267 | + IoTKit *s = IOTKIT(obj); | ||
268 | + int i; | ||
269 | + | ||
270 | + memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); | ||
271 | + | ||
272 | + init_sysbus_child(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), | ||
273 | + TYPE_ARMV7M); | ||
274 | + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", | ||
275 | + ARM_CPU_TYPE_NAME("cortex-m33")); | ||
276 | + | ||
277 | + init_sysbus_child(obj, "secctl", &s->secctl, sizeof(s->secctl), | ||
278 | + TYPE_IOTKIT_SECCTL); | ||
279 | + init_sysbus_child(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), | ||
280 | + TYPE_TZ_PPC); | ||
281 | + init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), | ||
282 | + TYPE_TZ_PPC); | ||
283 | + init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0), | ||
284 | + TYPE_CMSDK_APB_TIMER); | ||
285 | + init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1), | ||
286 | + TYPE_CMSDK_APB_TIMER); | ||
287 | + init_sysbus_child(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), | ||
288 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
289 | + object_initialize(&s->ppc_irq_orgate, sizeof(s->ppc_irq_orgate), | ||
290 | + TYPE_OR_IRQ); | ||
291 | + object_property_add_child(obj, "ppc-irq-orgate", | ||
292 | + OBJECT(&s->ppc_irq_orgate), &error_abort); | ||
293 | + object_initialize(&s->sec_resp_splitter, sizeof(s->sec_resp_splitter), | ||
294 | + TYPE_SPLIT_IRQ); | ||
295 | + object_property_add_child(obj, "sec-resp-splitter", | ||
296 | + OBJECT(&s->sec_resp_splitter), &error_abort); | ||
297 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
298 | + char *name = g_strdup_printf("ppc-irq-splitter-%d", i); | ||
299 | + SplitIRQ *splitter = &s->ppc_irq_splitter[i]; | ||
300 | + | ||
301 | + object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ); | ||
302 | + object_property_add_child(obj, name, OBJECT(splitter), &error_abort); | ||
303 | + } | ||
304 | + init_sysbus_child(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), | ||
305 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
306 | +} | ||
307 | + | ||
308 | +static void iotkit_exp_irq(void *opaque, int n, int level) | ||
309 | +{ | ||
310 | + IoTKit *s = IOTKIT(opaque); | ||
311 | + | ||
312 | + qemu_set_irq(s->exp_irqs[n], level); | ||
313 | +} | ||
314 | + | ||
315 | +static void iotkit_realize(DeviceState *dev, Error **errp) | ||
316 | +{ | ||
317 | + IoTKit *s = IOTKIT(dev); | ||
318 | + int i; | ||
319 | + MemoryRegion *mr; | ||
320 | + Error *err = NULL; | ||
321 | + SysBusDevice *sbd_apb_ppc0; | ||
322 | + SysBusDevice *sbd_secctl; | ||
323 | + DeviceState *dev_apb_ppc0; | ||
324 | + DeviceState *dev_apb_ppc1; | ||
325 | + DeviceState *dev_secctl; | ||
326 | + DeviceState *dev_splitter; | ||
327 | + | ||
328 | + if (!s->board_memory) { | ||
329 | + error_setg(errp, "memory property was not set"); | ||
330 | + return; | ||
331 | + } | ||
332 | + | ||
333 | + if (!s->mainclk_frq) { | ||
334 | + error_setg(errp, "MAINCLK property was not set"); | ||
335 | + return; | ||
336 | + } | ||
337 | + | ||
338 | + /* Handling of which devices should be available only to secure | ||
339 | + * code is usually done differently for M profile than for A profile. | ||
340 | + * Instead of putting some devices only into the secure address space, | ||
341 | + * devices exist in both address spaces but with hard-wired security | ||
342 | + * permissions that will cause the CPU to fault for non-secure accesses. | ||
343 | + * | ||
344 | + * The IoTKit has an IDAU (Implementation Defined Access Unit), | ||
345 | + * which specifies hard-wired security permissions for different | ||
346 | + * areas of the physical address space. For the IoTKit IDAU, the | ||
347 | + * top 4 bits of the physical address are the IDAU region ID, and | ||
348 | + * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS | ||
349 | + * region, otherwise it is an S region. | ||
350 | + * | ||
351 | + * The various devices and RAMs are generally all mapped twice, | ||
352 | + * once into a region that the IDAU defines as secure and once | ||
353 | + * into a non-secure region. They sit behind either a Memory | ||
354 | + * Protection Controller (for RAM) or a Peripheral Protection | ||
355 | + * Controller (for devices), which allow a more fine grained | ||
356 | + * configuration of whether non-secure accesses are permitted. | ||
357 | + * | ||
358 | + * (The other place that guest software can configure security | ||
359 | + * permissions is in the architected SAU (Security Attribution | ||
360 | + * Unit), which is entirely inside the CPU. The IDAU can upgrade | ||
361 | + * the security attributes for a region to more restrictive than | ||
362 | + * the SAU specifies, but cannot downgrade them.) | ||
363 | + * | ||
364 | + * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff | ||
365 | + * 0x20000000..0x2007ffff 32KB FPGA block RAM | ||
366 | + * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff | ||
367 | + * 0x40000000..0x4000ffff base peripheral region 1 | ||
368 | + * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) | ||
369 | + * 0x40020000..0x4002ffff system control element peripherals | ||
370 | + * 0x40080000..0x400fffff base peripheral region 2 | ||
371 | + * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff | ||
372 | + */ | ||
373 | + | ||
374 | + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | ||
375 | + | ||
376 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32); | ||
377 | + /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 | ||
378 | + * register in the IoT Kit System Control Register block, and the | ||
379 | + * initial value of that is in turn specifiable by the FPGA that | ||
380 | + * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, | ||
381 | + * and simply set the CPU's init-svtor to the IoT Kit default value. | ||
382 | + */ | ||
383 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); | ||
384 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), | ||
385 | + "memory", &err); | ||
386 | + if (err) { | ||
387 | + error_propagate(errp, err); | ||
388 | + return; | ||
389 | + } | ||
390 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); | ||
391 | + if (err) { | ||
392 | + error_propagate(errp, err); | ||
393 | + return; | ||
394 | + } | ||
395 | + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | ||
396 | + if (err) { | ||
397 | + error_propagate(errp, err); | ||
398 | + return; | ||
399 | + } | ||
400 | + | ||
401 | + /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ | ||
402 | + s->exp_irqs = g_new(qemu_irq, s->exp_numirq); | ||
403 | + for (i = 0; i < s->exp_numirq; i++) { | ||
404 | + s->exp_irqs[i] = qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); | ||
405 | + } | ||
406 | + qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); | ||
407 | + | ||
408 | + /* Set up the big aliases first */ | ||
409 | + make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); | ||
410 | + make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); | ||
411 | + /* The 0x50000000..0x5fffffff region is not a pure alias: it has | ||
412 | + * a few extra devices that only appear there (generally the | ||
413 | + * control interfaces for the protection controllers). | ||
414 | + * We implement this by mapping those devices over the top of this | ||
415 | + * alias MR at a higher priority. | ||
416 | + */ | ||
417 | + make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); | ||
418 | + | ||
419 | + /* This RAM should be behind a Memory Protection Controller, but we | ||
420 | + * don't implement that yet. | ||
421 | + */ | ||
422 | + memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err); | ||
423 | + if (err) { | ||
424 | + error_propagate(errp, err); | ||
425 | + return; | ||
426 | + } | ||
427 | + memory_region_add_subregion(&s->container, 0x20000000, &s->sram0); | ||
428 | + | ||
429 | + /* Security controller */ | ||
430 | + object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); | ||
431 | + if (err) { | ||
432 | + error_propagate(errp, err); | ||
433 | + return; | ||
434 | + } | ||
435 | + sbd_secctl = SYS_BUS_DEVICE(&s->secctl); | ||
436 | + dev_secctl = DEVICE(&s->secctl); | ||
437 | + sysbus_mmio_map(sbd_secctl, 0, 0x50080000); | ||
438 | + sysbus_mmio_map(sbd_secctl, 1, 0x40080000); | ||
439 | + | ||
440 | + s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); | ||
441 | + qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); | ||
442 | + | ||
443 | + /* The sec_resp_cfg output from the security controller must be split into | ||
444 | + * multiple lines, one for each of the PPCs within the IoTKit and one | ||
445 | + * that will be an output from the IoTKit to the system. | ||
446 | + */ | ||
447 | + object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, | ||
448 | + "num-lines", &err); | ||
449 | + if (err) { | ||
450 | + error_propagate(errp, err); | ||
451 | + return; | ||
452 | + } | ||
453 | + object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, | ||
454 | + "realized", &err); | ||
455 | + if (err) { | ||
456 | + error_propagate(errp, err); | ||
457 | + return; | ||
458 | + } | ||
459 | + dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
460 | + qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, | ||
461 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
462 | + | ||
463 | + /* Devices behind APB PPC0: | ||
464 | + * 0x40000000: timer0 | ||
465 | + * 0x40001000: timer1 | ||
466 | + * 0x40002000: dual timer | ||
467 | + * We must configure and realize each downstream device and connect | ||
468 | + * it to the appropriate PPC port; then we can realize the PPC and | ||
469 | + * map its upstream ends to the right place in the container. | ||
470 | + */ | ||
471 | + qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); | ||
472 | + object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); | ||
473 | + if (err) { | ||
474 | + error_propagate(errp, err); | ||
475 | + return; | ||
476 | + } | ||
477 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, | ||
478 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
479 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); | ||
480 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); | ||
481 | + if (err) { | ||
482 | + error_propagate(errp, err); | ||
483 | + return; | ||
484 | + } | ||
485 | + | ||
486 | + qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); | ||
487 | + object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); | ||
488 | + if (err) { | ||
489 | + error_propagate(errp, err); | ||
490 | + return; | ||
491 | + } | ||
492 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, | ||
493 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
494 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); | ||
495 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); | ||
496 | + if (err) { | ||
497 | + error_propagate(errp, err); | ||
498 | + return; | ||
499 | + } | ||
500 | + | ||
501 | + qdev_prop_set_string(DEVICE(&s->dualtimer), "name", "Dual timer"); | ||
502 | + qdev_prop_set_uint64(DEVICE(&s->dualtimer), "size", 0x1000); | ||
503 | + object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); | ||
504 | + if (err) { | ||
505 | + error_propagate(errp, err); | ||
506 | + return; | ||
507 | + } | ||
508 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); | ||
509 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); | ||
510 | + if (err) { | ||
511 | + error_propagate(errp, err); | ||
512 | + return; | ||
513 | + } | ||
514 | + | ||
515 | + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); | ||
516 | + if (err) { | ||
517 | + error_propagate(errp, err); | ||
518 | + return; | ||
519 | + } | ||
520 | + | ||
521 | + sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); | ||
522 | + dev_apb_ppc0 = DEVICE(&s->apb_ppc0); | ||
523 | + | ||
524 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); | ||
525 | + memory_region_add_subregion(&s->container, 0x40000000, mr); | ||
526 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); | ||
527 | + memory_region_add_subregion(&s->container, 0x40001000, mr); | ||
528 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); | ||
529 | + memory_region_add_subregion(&s->container, 0x40002000, mr); | ||
530 | + for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { | ||
531 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, | ||
532 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
533 | + "cfg_nonsec", i)); | ||
534 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, | ||
535 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
536 | + "cfg_ap", i)); | ||
537 | + } | ||
538 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, | ||
539 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
540 | + "irq_enable", 0)); | ||
541 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, | ||
542 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
543 | + "irq_clear", 0)); | ||
544 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
545 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
546 | + "cfg_sec_resp", 0)); | ||
547 | + | ||
548 | + /* All the PPC irq lines (from the 2 internal PPCs and the 8 external | ||
549 | + * ones) are sent individually to the security controller, and also | ||
550 | + * ORed together to give a single combined PPC interrupt to the NVIC. | ||
551 | + */ | ||
552 | + object_property_set_int(OBJECT(&s->ppc_irq_orgate), | ||
553 | + NUM_PPCS, "num-lines", &err); | ||
554 | + if (err) { | ||
555 | + error_propagate(errp, err); | ||
556 | + return; | ||
557 | + } | ||
558 | + object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, | ||
559 | + "realized", &err); | ||
560 | + if (err) { | ||
561 | + error_propagate(errp, err); | ||
562 | + return; | ||
563 | + } | ||
564 | + qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, | ||
565 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); | ||
566 | + | ||
567 | + /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ | ||
568 | + | ||
569 | + /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */ | ||
570 | + /* Devices behind APB PPC1: | ||
571 | + * 0x4002f000: S32K timer | ||
572 | + */ | ||
573 | + qdev_prop_set_string(DEVICE(&s->s32ktimer), "name", "S32KTIMER"); | ||
574 | + qdev_prop_set_uint64(DEVICE(&s->s32ktimer), "size", 0x1000); | ||
575 | + object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); | ||
576 | + if (err) { | ||
577 | + error_propagate(errp, err); | ||
578 | + return; | ||
579 | + } | ||
580 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); | ||
581 | + object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); | ||
582 | + if (err) { | ||
583 | + error_propagate(errp, err); | ||
584 | + return; | ||
585 | + } | ||
586 | + | ||
587 | + object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); | ||
588 | + if (err) { | ||
589 | + error_propagate(errp, err); | ||
590 | + return; | ||
591 | + } | ||
592 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); | ||
593 | + memory_region_add_subregion(&s->container, 0x4002f000, mr); | ||
594 | + | ||
595 | + dev_apb_ppc1 = DEVICE(&s->apb_ppc1); | ||
596 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, | ||
597 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
598 | + "cfg_nonsec", 0)); | ||
599 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, | ||
600 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
601 | + "cfg_ap", 0)); | ||
602 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, | ||
603 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
604 | + "irq_enable", 0)); | ||
605 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, | ||
606 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
607 | + "irq_clear", 0)); | ||
608 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
609 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
610 | + "cfg_sec_resp", 0)); | ||
611 | + | ||
612 | + /* Using create_unimplemented_device() maps the stub into the | ||
613 | + * system address space rather than into our container, but the | ||
614 | + * overall effect to the guest is the same. | ||
615 | + */ | ||
616 | + create_unimplemented_device("SYSINFO", 0x40020000, 0x1000); | ||
617 | + | ||
618 | + create_unimplemented_device("SYSCONTROL", 0x50021000, 0x1000); | ||
619 | + create_unimplemented_device("S32KWATCHDOG", 0x5002e000, 0x1000); | ||
620 | + | ||
621 | + /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ | ||
622 | + | ||
623 | + create_unimplemented_device("NS watchdog", 0x40081000, 0x1000); | ||
624 | + create_unimplemented_device("S watchdog", 0x50081000, 0x1000); | ||
625 | + | ||
626 | + create_unimplemented_device("SRAM0 MPC", 0x50083000, 0x1000); | ||
627 | + | ||
628 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
629 | + Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); | ||
630 | + | ||
631 | + object_property_set_int(splitter, 2, "num-lines", &err); | ||
632 | + if (err) { | ||
633 | + error_propagate(errp, err); | ||
634 | + return; | ||
635 | + } | ||
636 | + object_property_set_bool(splitter, true, "realized", &err); | ||
637 | + if (err) { | ||
638 | + error_propagate(errp, err); | ||
639 | + return; | ||
640 | + } | ||
641 | + } | ||
642 | + | ||
643 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
644 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
645 | + | ||
646 | + iotkit_forward_ppc(s, ppcname, i); | ||
647 | + g_free(ppcname); | ||
648 | + } | ||
649 | + | ||
650 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
651 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
652 | + | ||
653 | + iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); | ||
654 | + g_free(ppcname); | ||
655 | + } | ||
656 | + | ||
657 | + for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { | ||
658 | + /* Wire up IRQ splitter for internal PPCs */ | ||
659 | + DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); | ||
660 | + char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", | ||
661 | + i - NUM_EXTERNAL_PPCS); | ||
662 | + TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; | ||
663 | + | ||
664 | + qdev_connect_gpio_out(devs, 0, | ||
665 | + qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); | ||
666 | + qdev_connect_gpio_out(devs, 1, | ||
667 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); | ||
668 | + qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, | ||
669 | + qdev_get_gpio_in(devs, 0)); | ||
670 | + } | ||
671 | + | ||
672 | + iotkit_forward_sec_resp_cfg(s); | ||
673 | + | ||
674 | + system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; | ||
675 | +} | ||
676 | + | ||
677 | +static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, | ||
678 | + int *iregion, bool *exempt, bool *ns, bool *nsc) | ||
679 | +{ | ||
680 | + /* For IoTKit systems the IDAU responses are simple logical functions | ||
681 | + * of the address bits. The NSC attribute is guest-adjustable via the | ||
682 | + * NSCCFG register in the security controller. | ||
683 | + */ | ||
684 | + IoTKit *s = IOTKIT(ii); | ||
685 | + int region = extract32(address, 28, 4); | ||
686 | + | ||
687 | + *ns = !(region & 1); | ||
688 | + *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); | ||
689 | + /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | ||
690 | + *exempt = (address & 0xeff00000) == 0xe0000000; | ||
691 | + *iregion = region; | ||
692 | +} | ||
693 | + | ||
694 | +static const VMStateDescription iotkit_vmstate = { | ||
695 | + .name = "iotkit", | ||
696 | + .version_id = 1, | ||
697 | + .minimum_version_id = 1, | ||
698 | + .fields = (VMStateField[]) { | ||
699 | + VMSTATE_UINT32(nsccfg, IoTKit), | ||
700 | + VMSTATE_END_OF_LIST() | ||
701 | + } | ||
702 | +}; | ||
703 | + | ||
704 | +static Property iotkit_properties[] = { | ||
705 | + DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, | ||
706 | + MemoryRegion *), | ||
707 | + DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), | ||
708 | + DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), | ||
709 | + DEFINE_PROP_END_OF_LIST() | ||
710 | +}; | ||
711 | + | ||
712 | +static void iotkit_reset(DeviceState *dev) | ||
713 | +{ | ||
714 | + IoTKit *s = IOTKIT(dev); | ||
715 | + | ||
716 | + s->nsccfg = 0; | ||
717 | +} | ||
718 | + | ||
719 | +static void iotkit_class_init(ObjectClass *klass, void *data) | ||
720 | +{ | ||
721 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
722 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); | ||
723 | + | ||
724 | + dc->realize = iotkit_realize; | ||
725 | + dc->vmsd = &iotkit_vmstate; | ||
726 | + dc->props = iotkit_properties; | ||
727 | + dc->reset = iotkit_reset; | ||
728 | + iic->check = iotkit_idau_check; | ||
729 | +} | ||
730 | + | ||
731 | +static const TypeInfo iotkit_info = { | ||
732 | + .name = TYPE_IOTKIT, | ||
733 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
734 | + .instance_size = sizeof(IoTKit), | ||
735 | + .instance_init = iotkit_init, | ||
736 | + .class_init = iotkit_class_init, | ||
737 | + .interfaces = (InterfaceInfo[]) { | ||
738 | + { TYPE_IDAU_INTERFACE }, | ||
739 | + { } | ||
740 | + } | ||
741 | +}; | ||
742 | + | ||
743 | +static void iotkit_register_types(void) | ||
744 | +{ | ||
745 | + type_register_static(&iotkit_info); | ||
746 | +} | ||
747 | + | ||
748 | +type_init(iotkit_register_types); | ||
749 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
750 | index XXXXXXX..XXXXXXX 100644 | ||
751 | --- a/default-configs/arm-softmmu.mak | ||
752 | +++ b/default-configs/arm-softmmu.mak | ||
753 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
754 | CONFIG_MPS2_SCC=y | ||
755 | |||
756 | CONFIG_TZ_PPC=y | ||
757 | +CONFIG_IOTKIT=y | ||
758 | CONFIG_IOTKIT_SECCTL=y | ||
759 | |||
760 | CONFIG_VERSATILE_PCI=y | ||
761 | -- | ||
762 | 2.16.2 | ||
763 | |||
764 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Define a new board model for the MPS2 with an AN505 FPGA image | ||
2 | containing a Cortex-M33. Since the FPGA images for TrustZone | ||
3 | cores (AN505, and the similar AN519 for Cortex-M23) have a | ||
4 | significantly different layout of devices to the non-TrustZone | ||
5 | images, we use a new source file rather than shoehorning them | ||
6 | into the existing mps2.c. | ||
7 | 1 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-20-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/arm/Makefile.objs | 1 + | ||
13 | hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
14 | 2 files changed, 504 insertions(+) | ||
15 | create mode 100644 hw/arm/mps2-tz.c | ||
16 | |||
17 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/Makefile.objs | ||
20 | +++ b/hw/arm/Makefile.objs | ||
21 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | ||
22 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | ||
23 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | ||
24 | obj-$(CONFIG_MPS2) += mps2.o | ||
25 | +obj-$(CONFIG_MPS2) += mps2-tz.o | ||
26 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | ||
27 | obj-$(CONFIG_IOTKIT) += iotkit.o | ||
28 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/hw/arm/mps2-tz.c | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * ARM V2M MPS2 board emulation, trustzone aware FPGA images | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Linaro Limited | ||
38 | + * Written by Peter Maydell | ||
39 | + * | ||
40 | + * This program is free software; you can redistribute it and/or modify | ||
41 | + * it under the terms of the GNU General Public License version 2 or | ||
42 | + * (at your option) any later version. | ||
43 | + */ | ||
44 | + | ||
45 | +/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | ||
46 | + * FPGA but is otherwise the same as the 2). Since the CPU itself | ||
47 | + * and most of the devices are in the FPGA, the details of the board | ||
48 | + * as seen by the guest depend significantly on the FPGA image. | ||
49 | + * This source file covers the following FPGA images, for TrustZone cores: | ||
50 | + * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 | ||
51 | + * | ||
52 | + * Links to the TRM for the board itself and to the various Application | ||
53 | + * Notes which document the FPGA images can be found here: | ||
54 | + * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | ||
55 | + * | ||
56 | + * Board TRM: | ||
57 | + * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | ||
58 | + * Application Note AN505: | ||
59 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
60 | + * | ||
61 | + * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | ||
62 | + * (ARM ECM0601256) for the details of some of the device layout: | ||
63 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
64 | + */ | ||
65 | + | ||
66 | +#include "qemu/osdep.h" | ||
67 | +#include "qapi/error.h" | ||
68 | +#include "qemu/error-report.h" | ||
69 | +#include "hw/arm/arm.h" | ||
70 | +#include "hw/arm/armv7m.h" | ||
71 | +#include "hw/or-irq.h" | ||
72 | +#include "hw/boards.h" | ||
73 | +#include "exec/address-spaces.h" | ||
74 | +#include "sysemu/sysemu.h" | ||
75 | +#include "hw/misc/unimp.h" | ||
76 | +#include "hw/char/cmsdk-apb-uart.h" | ||
77 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
78 | +#include "hw/misc/mps2-scc.h" | ||
79 | +#include "hw/misc/mps2-fpgaio.h" | ||
80 | +#include "hw/arm/iotkit.h" | ||
81 | +#include "hw/devices.h" | ||
82 | +#include "net/net.h" | ||
83 | +#include "hw/core/split-irq.h" | ||
84 | + | ||
85 | +typedef enum MPS2TZFPGAType { | ||
86 | + FPGA_AN505, | ||
87 | +} MPS2TZFPGAType; | ||
88 | + | ||
89 | +typedef struct { | ||
90 | + MachineClass parent; | ||
91 | + MPS2TZFPGAType fpga_type; | ||
92 | + uint32_t scc_id; | ||
93 | +} MPS2TZMachineClass; | ||
94 | + | ||
95 | +typedef struct { | ||
96 | + MachineState parent; | ||
97 | + | ||
98 | + IoTKit iotkit; | ||
99 | + MemoryRegion psram; | ||
100 | + MemoryRegion ssram1; | ||
101 | + MemoryRegion ssram1_m; | ||
102 | + MemoryRegion ssram23; | ||
103 | + MPS2SCC scc; | ||
104 | + MPS2FPGAIO fpgaio; | ||
105 | + TZPPC ppc[5]; | ||
106 | + UnimplementedDeviceState ssram_mpc[3]; | ||
107 | + UnimplementedDeviceState spi[5]; | ||
108 | + UnimplementedDeviceState i2c[4]; | ||
109 | + UnimplementedDeviceState i2s_audio; | ||
110 | + UnimplementedDeviceState gpio[5]; | ||
111 | + UnimplementedDeviceState dma[4]; | ||
112 | + UnimplementedDeviceState gfx; | ||
113 | + CMSDKAPBUART uart[5]; | ||
114 | + SplitIRQ sec_resp_splitter; | ||
115 | + qemu_or_irq uart_irq_orgate; | ||
116 | +} MPS2TZMachineState; | ||
117 | + | ||
118 | +#define TYPE_MPS2TZ_MACHINE "mps2tz" | ||
119 | +#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") | ||
120 | + | ||
121 | +#define MPS2TZ_MACHINE(obj) \ | ||
122 | + OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) | ||
123 | +#define MPS2TZ_MACHINE_GET_CLASS(obj) \ | ||
124 | + OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) | ||
125 | +#define MPS2TZ_MACHINE_CLASS(klass) \ | ||
126 | + OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) | ||
127 | + | ||
128 | +/* Main SYSCLK frequency in Hz */ | ||
129 | +#define SYSCLK_FRQ 20000000 | ||
130 | + | ||
131 | +/* Initialize the auxiliary RAM region @mr and map it into | ||
132 | + * the memory map at @base. | ||
133 | + */ | ||
134 | +static void make_ram(MemoryRegion *mr, const char *name, | ||
135 | + hwaddr base, hwaddr size) | ||
136 | +{ | ||
137 | + memory_region_init_ram(mr, NULL, name, size, &error_fatal); | ||
138 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
139 | +} | ||
140 | + | ||
141 | +/* Create an alias of an entire original MemoryRegion @orig | ||
142 | + * located at @base in the memory map. | ||
143 | + */ | ||
144 | +static void make_ram_alias(MemoryRegion *mr, const char *name, | ||
145 | + MemoryRegion *orig, hwaddr base) | ||
146 | +{ | ||
147 | + memory_region_init_alias(mr, NULL, name, orig, 0, | ||
148 | + memory_region_size(orig)); | ||
149 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
150 | +} | ||
151 | + | ||
152 | +static void init_sysbus_child(Object *parent, const char *childname, | ||
153 | + void *child, size_t childsize, | ||
154 | + const char *childtype) | ||
155 | +{ | ||
156 | + object_initialize(child, childsize, childtype); | ||
157 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | ||
158 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
159 | + | ||
160 | +} | ||
161 | + | ||
162 | +/* Most of the devices in the AN505 FPGA image sit behind | ||
163 | + * Peripheral Protection Controllers. These data structures | ||
164 | + * define the layout of which devices sit behind which PPCs. | ||
165 | + * The devfn for each port is a function which creates, configures | ||
166 | + * and initializes the device, returning the MemoryRegion which | ||
167 | + * needs to be plugged into the downstream end of the PPC port. | ||
168 | + */ | ||
169 | +typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, | ||
170 | + const char *name, hwaddr size); | ||
171 | + | ||
172 | +typedef struct PPCPortInfo { | ||
173 | + const char *name; | ||
174 | + MakeDevFn *devfn; | ||
175 | + void *opaque; | ||
176 | + hwaddr addr; | ||
177 | + hwaddr size; | ||
178 | +} PPCPortInfo; | ||
179 | + | ||
180 | +typedef struct PPCInfo { | ||
181 | + const char *name; | ||
182 | + PPCPortInfo ports[TZ_NUM_PORTS]; | ||
183 | +} PPCInfo; | ||
184 | + | ||
185 | +static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | ||
186 | + void *opaque, | ||
187 | + const char *name, hwaddr size) | ||
188 | +{ | ||
189 | + /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | ||
190 | + * and return a pointer to its MemoryRegion. | ||
191 | + */ | ||
192 | + UnimplementedDeviceState *uds = opaque; | ||
193 | + | ||
194 | + init_sysbus_child(OBJECT(mms), name, uds, | ||
195 | + sizeof(UnimplementedDeviceState), | ||
196 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
197 | + qdev_prop_set_string(DEVICE(uds), "name", name); | ||
198 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | ||
199 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | ||
200 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); | ||
201 | +} | ||
202 | + | ||
203 | +static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | ||
204 | + const char *name, hwaddr size) | ||
205 | +{ | ||
206 | + CMSDKAPBUART *uart = opaque; | ||
207 | + int i = uart - &mms->uart[0]; | ||
208 | + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; | ||
209 | + int rxirqno = i * 2; | ||
210 | + int txirqno = i * 2 + 1; | ||
211 | + int combirqno = i + 10; | ||
212 | + SysBusDevice *s; | ||
213 | + DeviceState *iotkitdev = DEVICE(&mms->iotkit); | ||
214 | + DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | ||
215 | + | ||
216 | + init_sysbus_child(OBJECT(mms), name, uart, | ||
217 | + sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); | ||
218 | + qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); | ||
219 | + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); | ||
220 | + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | ||
221 | + s = SYS_BUS_DEVICE(uart); | ||
222 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, | ||
223 | + "EXP_IRQ", txirqno)); | ||
224 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, | ||
225 | + "EXP_IRQ", rxirqno)); | ||
226 | + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); | ||
227 | + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | ||
228 | + sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, | ||
229 | + "EXP_IRQ", combirqno)); | ||
230 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); | ||
231 | +} | ||
232 | + | ||
233 | +static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | ||
234 | + const char *name, hwaddr size) | ||
235 | +{ | ||
236 | + MPS2SCC *scc = opaque; | ||
237 | + DeviceState *sccdev; | ||
238 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
239 | + | ||
240 | + object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); | ||
241 | + sccdev = DEVICE(scc); | ||
242 | + qdev_set_parent_bus(sccdev, sysbus_get_default()); | ||
243 | + qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | ||
244 | + qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); | ||
245 | + qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | ||
246 | + object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); | ||
247 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); | ||
248 | +} | ||
249 | + | ||
250 | +static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | ||
251 | + const char *name, hwaddr size) | ||
252 | +{ | ||
253 | + MPS2FPGAIO *fpgaio = opaque; | ||
254 | + | ||
255 | + object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); | ||
256 | + qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); | ||
257 | + object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); | ||
258 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
259 | +} | ||
260 | + | ||
261 | +static void mps2tz_common_init(MachineState *machine) | ||
262 | +{ | ||
263 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
264 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
265 | + MemoryRegion *system_memory = get_system_memory(); | ||
266 | + DeviceState *iotkitdev; | ||
267 | + DeviceState *dev_splitter; | ||
268 | + int i; | ||
269 | + | ||
270 | + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | ||
271 | + error_report("This board can only be used with CPU %s", | ||
272 | + mc->default_cpu_type); | ||
273 | + exit(1); | ||
274 | + } | ||
275 | + | ||
276 | + init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, | ||
277 | + sizeof(mms->iotkit), TYPE_IOTKIT); | ||
278 | + iotkitdev = DEVICE(&mms->iotkit); | ||
279 | + object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | ||
280 | + "memory", &error_abort); | ||
281 | + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); | ||
282 | + qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); | ||
283 | + object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", | ||
284 | + &error_fatal); | ||
285 | + | ||
286 | + /* The sec_resp_cfg output from the IoTKit must be split into multiple | ||
287 | + * lines, one for each of the PPCs we create here. | ||
288 | + */ | ||
289 | + object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), | ||
290 | + TYPE_SPLIT_IRQ); | ||
291 | + object_property_add_child(OBJECT(machine), "sec-resp-splitter", | ||
292 | + OBJECT(&mms->sec_resp_splitter), &error_abort); | ||
293 | + object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, | ||
294 | + "num-lines", &error_fatal); | ||
295 | + object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, | ||
296 | + "realized", &error_fatal); | ||
297 | + dev_splitter = DEVICE(&mms->sec_resp_splitter); | ||
298 | + qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, | ||
299 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
300 | + | ||
301 | + /* The IoTKit sets up much of the memory layout, including | ||
302 | + * the aliases between secure and non-secure regions in the | ||
303 | + * address space. The FPGA itself contains: | ||
304 | + * | ||
305 | + * 0x00000000..0x003fffff SSRAM1 | ||
306 | + * 0x00400000..0x007fffff alias of SSRAM1 | ||
307 | + * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 | ||
308 | + * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices | ||
309 | + * 0x80000000..0x80ffffff 16MB PSRAM | ||
310 | + */ | ||
311 | + | ||
312 | + /* The FPGA images have an odd combination of different RAMs, | ||
313 | + * because in hardware they are different implementations and | ||
314 | + * connected to different buses, giving varying performance/size | ||
315 | + * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | ||
316 | + * call the 16MB our "system memory", as it's the largest lump. | ||
317 | + */ | ||
318 | + memory_region_allocate_system_memory(&mms->psram, | ||
319 | + NULL, "mps.ram", 0x01000000); | ||
320 | + memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); | ||
321 | + | ||
322 | + /* The SSRAM memories should all be behind Memory Protection Controllers, | ||
323 | + * but we don't implement that yet. | ||
324 | + */ | ||
325 | + make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000); | ||
326 | + make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000); | ||
327 | + | ||
328 | + make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000); | ||
329 | + | ||
330 | + /* The overflow IRQs for all UARTs are ORed together. | ||
331 | + * Tx, Rx and "combined" IRQs are sent to the NVIC separately. | ||
332 | + * Create the OR gate for this. | ||
333 | + */ | ||
334 | + object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), | ||
335 | + TYPE_OR_IRQ); | ||
336 | + object_property_add_child(OBJECT(mms), "uart-irq-orgate", | ||
337 | + OBJECT(&mms->uart_irq_orgate), &error_abort); | ||
338 | + object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", | ||
339 | + &error_fatal); | ||
340 | + object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, | ||
341 | + "realized", &error_fatal); | ||
342 | + qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | ||
343 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); | ||
344 | + | ||
345 | + /* Most of the devices in the FPGA are behind Peripheral Protection | ||
346 | + * Controllers. The required order for initializing things is: | ||
347 | + * + initialize the PPC | ||
348 | + * + initialize, configure and realize downstream devices | ||
349 | + * + connect downstream device MemoryRegions to the PPC | ||
350 | + * + realize the PPC | ||
351 | + * + map the PPC's MemoryRegions to the places in the address map | ||
352 | + * where the downstream devices should appear | ||
353 | + * + wire up the PPC's control lines to the IoTKit object | ||
354 | + */ | ||
355 | + | ||
356 | + const PPCInfo ppcs[] = { { | ||
357 | + .name = "apb_ppcexp0", | ||
358 | + .ports = { | ||
359 | + { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0], | ||
360 | + 0x58007000, 0x1000 }, | ||
361 | + { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1], | ||
362 | + 0x58008000, 0x1000 }, | ||
363 | + { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2], | ||
364 | + 0x58009000, 0x1000 }, | ||
365 | + }, | ||
366 | + }, { | ||
367 | + .name = "apb_ppcexp1", | ||
368 | + .ports = { | ||
369 | + { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, | ||
370 | + { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, | ||
371 | + { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, | ||
372 | + { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, | ||
373 | + { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, | ||
374 | + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, | ||
375 | + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | ||
376 | + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | ||
377 | + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | ||
378 | + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | ||
379 | + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
380 | + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
381 | + { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
382 | + { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | ||
383 | + }, | ||
384 | + }, { | ||
385 | + .name = "apb_ppcexp2", | ||
386 | + .ports = { | ||
387 | + { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, | ||
388 | + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, | ||
389 | + 0x40301000, 0x1000 }, | ||
390 | + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, | ||
391 | + }, | ||
392 | + }, { | ||
393 | + .name = "ahb_ppcexp0", | ||
394 | + .ports = { | ||
395 | + { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, | ||
396 | + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, | ||
397 | + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
398 | + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
399 | + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
400 | + { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, | ||
401 | + }, | ||
402 | + }, { | ||
403 | + .name = "ahb_ppcexp1", | ||
404 | + .ports = { | ||
405 | + { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, | ||
406 | + { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, | ||
407 | + { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, | ||
408 | + { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, | ||
409 | + }, | ||
410 | + }, | ||
411 | + }; | ||
412 | + | ||
413 | + for (i = 0; i < ARRAY_SIZE(ppcs); i++) { | ||
414 | + const PPCInfo *ppcinfo = &ppcs[i]; | ||
415 | + TZPPC *ppc = &mms->ppc[i]; | ||
416 | + DeviceState *ppcdev; | ||
417 | + int port; | ||
418 | + char *gpioname; | ||
419 | + | ||
420 | + init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, | ||
421 | + sizeof(TZPPC), TYPE_TZ_PPC); | ||
422 | + ppcdev = DEVICE(ppc); | ||
423 | + | ||
424 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
425 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
426 | + MemoryRegion *mr; | ||
427 | + char *portname; | ||
428 | + | ||
429 | + if (!pinfo->devfn) { | ||
430 | + continue; | ||
431 | + } | ||
432 | + | ||
433 | + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | ||
434 | + portname = g_strdup_printf("port[%d]", port); | ||
435 | + object_property_set_link(OBJECT(ppc), OBJECT(mr), | ||
436 | + portname, &error_fatal); | ||
437 | + g_free(portname); | ||
438 | + } | ||
439 | + | ||
440 | + object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); | ||
441 | + | ||
442 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
443 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
444 | + | ||
445 | + if (!pinfo->devfn) { | ||
446 | + continue; | ||
447 | + } | ||
448 | + sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); | ||
449 | + | ||
450 | + gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); | ||
451 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
452 | + qdev_get_gpio_in_named(ppcdev, | ||
453 | + "cfg_nonsec", | ||
454 | + port)); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_ap", ppcinfo->name); | ||
457 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
458 | + qdev_get_gpio_in_named(ppcdev, | ||
459 | + "cfg_ap", port)); | ||
460 | + g_free(gpioname); | ||
461 | + } | ||
462 | + | ||
463 | + gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); | ||
464 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | ||
465 | + qdev_get_gpio_in_named(ppcdev, | ||
466 | + "irq_enable", 0)); | ||
467 | + g_free(gpioname); | ||
468 | + gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); | ||
469 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | ||
470 | + qdev_get_gpio_in_named(ppcdev, | ||
471 | + "irq_clear", 0)); | ||
472 | + g_free(gpioname); | ||
473 | + gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); | ||
474 | + qdev_connect_gpio_out_named(ppcdev, "irq", 0, | ||
475 | + qdev_get_gpio_in_named(iotkitdev, | ||
476 | + gpioname, 0)); | ||
477 | + g_free(gpioname); | ||
478 | + | ||
479 | + qdev_connect_gpio_out(dev_splitter, i, | ||
480 | + qdev_get_gpio_in_named(ppcdev, | ||
481 | + "cfg_sec_resp", 0)); | ||
482 | + } | ||
483 | + | ||
484 | + /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
485 | + * except that it doesn't support the checksum-offload feature. | ||
486 | + * The ethernet controller is not behind a PPC. | ||
487 | + */ | ||
488 | + lan9118_init(&nd_table[0], 0x42000000, | ||
489 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | ||
490 | + | ||
491 | + create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); | ||
492 | + | ||
493 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | ||
494 | +} | ||
495 | + | ||
496 | +static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
497 | +{ | ||
498 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
499 | + | ||
500 | + mc->init = mps2tz_common_init; | ||
501 | + mc->max_cpus = 1; | ||
502 | +} | ||
503 | + | ||
504 | +static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | ||
505 | +{ | ||
506 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
507 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
508 | + | ||
509 | + mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; | ||
510 | + mmc->fpga_type = FPGA_AN505; | ||
511 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | ||
512 | + mmc->scc_id = 0x41040000 | (505 << 4); | ||
513 | +} | ||
514 | + | ||
515 | +static const TypeInfo mps2tz_info = { | ||
516 | + .name = TYPE_MPS2TZ_MACHINE, | ||
517 | + .parent = TYPE_MACHINE, | ||
518 | + .abstract = true, | ||
519 | + .instance_size = sizeof(MPS2TZMachineState), | ||
520 | + .class_size = sizeof(MPS2TZMachineClass), | ||
521 | + .class_init = mps2tz_class_init, | ||
522 | +}; | ||
523 | + | ||
524 | +static const TypeInfo mps2tz_an505_info = { | ||
525 | + .name = TYPE_MPS2TZ_AN505_MACHINE, | ||
526 | + .parent = TYPE_MPS2TZ_MACHINE, | ||
527 | + .class_init = mps2tz_an505_class_init, | ||
528 | +}; | ||
529 | + | ||
530 | +static void mps2tz_machine_init(void) | ||
531 | +{ | ||
532 | + type_register_static(&mps2tz_info); | ||
533 | + type_register_static(&mps2tz_an505_info); | ||
534 | +} | ||
535 | + | ||
536 | +type_init(mps2tz_machine_init); | ||
537 | -- | ||
538 | 2.16.2 | ||
539 | |||
540 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Not enabled anywhere yet. | ||
4 | |||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180228193125.20577-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 1 + | ||
12 | linux-user/elfload.c | 1 + | ||
13 | 2 files changed, 2 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
20 | ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ | ||
21 | ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ | ||
22 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | ||
23 | + ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | ||
24 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | ||
25 | }; | ||
26 | |||
27 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/linux-user/elfload.c | ||
30 | +++ b/linux-user/elfload.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
32 | GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); | ||
33 | GET_FEATURE(ARM_FEATURE_V8_FP16, | ||
34 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | ||
35 | + GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | ||
36 | #undef GET_FEATURE | ||
37 | |||
38 | return hwcaps; | ||
39 | -- | ||
40 | 2.16.2 | ||
41 | |||
42 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Include the U bit in the switches rather than testing separately. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-3-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------ | ||
11 | 1 file changed, 61 insertions(+), 68 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-a64.c | ||
16 | +++ b/target/arm/translate-a64.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
18 | int index; | ||
19 | TCGv_ptr fpst; | ||
20 | |||
21 | - switch (opcode) { | ||
22 | - case 0x0: /* MLA */ | ||
23 | - case 0x4: /* MLS */ | ||
24 | - if (!u || is_scalar) { | ||
25 | + switch (16 * u + opcode) { | ||
26 | + case 0x08: /* MUL */ | ||
27 | + case 0x10: /* MLA */ | ||
28 | + case 0x14: /* MLS */ | ||
29 | + if (is_scalar) { | ||
30 | unallocated_encoding(s); | ||
31 | return; | ||
32 | } | ||
33 | break; | ||
34 | - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | ||
35 | - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | ||
36 | - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | ||
37 | + case 0x02: /* SMLAL, SMLAL2 */ | ||
38 | + case 0x12: /* UMLAL, UMLAL2 */ | ||
39 | + case 0x06: /* SMLSL, SMLSL2 */ | ||
40 | + case 0x16: /* UMLSL, UMLSL2 */ | ||
41 | + case 0x0a: /* SMULL, SMULL2 */ | ||
42 | + case 0x1a: /* UMULL, UMULL2 */ | ||
43 | if (is_scalar) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | is_long = true; | ||
48 | break; | ||
49 | - case 0x3: /* SQDMLAL, SQDMLAL2 */ | ||
50 | - case 0x7: /* SQDMLSL, SQDMLSL2 */ | ||
51 | - case 0xb: /* SQDMULL, SQDMULL2 */ | ||
52 | + case 0x03: /* SQDMLAL, SQDMLAL2 */ | ||
53 | + case 0x07: /* SQDMLSL, SQDMLSL2 */ | ||
54 | + case 0x0b: /* SQDMULL, SQDMULL2 */ | ||
55 | is_long = true; | ||
56 | - /* fall through */ | ||
57 | - case 0xc: /* SQDMULH */ | ||
58 | - case 0xd: /* SQRDMULH */ | ||
59 | - if (u) { | ||
60 | - unallocated_encoding(s); | ||
61 | - return; | ||
62 | - } | ||
63 | break; | ||
64 | - case 0x8: /* MUL */ | ||
65 | - if (u || is_scalar) { | ||
66 | - unallocated_encoding(s); | ||
67 | - return; | ||
68 | - } | ||
69 | + case 0x0c: /* SQDMULH */ | ||
70 | + case 0x0d: /* SQRDMULH */ | ||
71 | break; | ||
72 | - case 0x1: /* FMLA */ | ||
73 | - case 0x5: /* FMLS */ | ||
74 | - if (u) { | ||
75 | - unallocated_encoding(s); | ||
76 | - return; | ||
77 | - } | ||
78 | - /* fall through */ | ||
79 | - case 0x9: /* FMUL, FMULX */ | ||
80 | + case 0x01: /* FMLA */ | ||
81 | + case 0x05: /* FMLS */ | ||
82 | + case 0x09: /* FMUL */ | ||
83 | + case 0x19: /* FMULX */ | ||
84 | if (size == 1) { | ||
85 | unallocated_encoding(s); | ||
86 | return; | ||
87 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
88 | |||
89 | read_vec_element(s, tcg_op, rn, pass, MO_64); | ||
90 | |||
91 | - switch (opcode) { | ||
92 | - case 0x5: /* FMLS */ | ||
93 | + switch (16 * u + opcode) { | ||
94 | + case 0x05: /* FMLS */ | ||
95 | /* As usual for ARM, separate negation for fused multiply-add */ | ||
96 | gen_helper_vfp_negd(tcg_op, tcg_op); | ||
97 | /* fall through */ | ||
98 | - case 0x1: /* FMLA */ | ||
99 | + case 0x01: /* FMLA */ | ||
100 | read_vec_element(s, tcg_res, rd, pass, MO_64); | ||
101 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | ||
102 | break; | ||
103 | - case 0x9: /* FMUL, FMULX */ | ||
104 | - if (u) { | ||
105 | - gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
106 | - } else { | ||
107 | - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
108 | - } | ||
109 | + case 0x09: /* FMUL */ | ||
110 | + gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
111 | + break; | ||
112 | + case 0x19: /* FMULX */ | ||
113 | + gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
114 | break; | ||
115 | default: | ||
116 | g_assert_not_reached(); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
118 | |||
119 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); | ||
120 | |||
121 | - switch (opcode) { | ||
122 | - case 0x0: /* MLA */ | ||
123 | - case 0x4: /* MLS */ | ||
124 | - case 0x8: /* MUL */ | ||
125 | + switch (16 * u + opcode) { | ||
126 | + case 0x08: /* MUL */ | ||
127 | + case 0x10: /* MLA */ | ||
128 | + case 0x14: /* MLS */ | ||
129 | { | ||
130 | static NeonGenTwoOpFn * const fns[2][2] = { | ||
131 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | ||
132 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
133 | genfn(tcg_res, tcg_op, tcg_res); | ||
134 | break; | ||
135 | } | ||
136 | - case 0x5: /* FMLS */ | ||
137 | - case 0x1: /* FMLA */ | ||
138 | + case 0x05: /* FMLS */ | ||
139 | + case 0x01: /* FMLA */ | ||
140 | read_vec_element_i32(s, tcg_res, rd, pass, | ||
141 | is_scalar ? size : MO_32); | ||
142 | switch (size) { | ||
143 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
144 | g_assert_not_reached(); | ||
145 | } | ||
146 | break; | ||
147 | - case 0x9: /* FMUL, FMULX */ | ||
148 | + case 0x09: /* FMUL */ | ||
149 | switch (size) { | ||
150 | case 1: | ||
151 | - if (u) { | ||
152 | - if (is_scalar) { | ||
153 | - gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
154 | - tcg_idx, fpst); | ||
155 | - } else { | ||
156 | - gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
157 | - tcg_idx, fpst); | ||
158 | - } | ||
159 | + if (is_scalar) { | ||
160 | + gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
161 | + tcg_idx, fpst); | ||
162 | } else { | ||
163 | - if (is_scalar) { | ||
164 | - gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
165 | - tcg_idx, fpst); | ||
166 | - } else { | ||
167 | - gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
168 | - tcg_idx, fpst); | ||
169 | - } | ||
170 | + gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
171 | + tcg_idx, fpst); | ||
172 | } | ||
173 | break; | ||
174 | case 2: | ||
175 | - if (u) { | ||
176 | - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
177 | - } else { | ||
178 | - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
179 | - } | ||
180 | + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
181 | break; | ||
182 | default: | ||
183 | g_assert_not_reached(); | ||
184 | } | ||
185 | break; | ||
186 | - case 0xc: /* SQDMULH */ | ||
187 | + case 0x19: /* FMULX */ | ||
188 | + switch (size) { | ||
189 | + case 1: | ||
190 | + if (is_scalar) { | ||
191 | + gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
192 | + tcg_idx, fpst); | ||
193 | + } else { | ||
194 | + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
195 | + tcg_idx, fpst); | ||
196 | + } | ||
197 | + break; | ||
198 | + case 2: | ||
199 | + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
200 | + break; | ||
201 | + default: | ||
202 | + g_assert_not_reached(); | ||
203 | + } | ||
204 | + break; | ||
205 | + case 0x0c: /* SQDMULH */ | ||
206 | if (size == 1) { | ||
207 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | ||
208 | tcg_op, tcg_idx); | ||
209 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
210 | tcg_op, tcg_idx); | ||
211 | } | ||
212 | break; | ||
213 | - case 0xd: /* SQRDMULH */ | ||
214 | + case 0x0d: /* SQRDMULH */ | ||
215 | if (size == 1) { | ||
216 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | ||
217 | tcg_op, tcg_idx); | ||
218 | -- | ||
219 | 2.16.2 | ||
220 | |||
221 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The integer size check was already outside of the opcode switch; | ||
4 | move the floating-point size check outside as well. Unify the | ||
5 | size vs index adjustment between fp and integer paths. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20180228193125.20577-4-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate-a64.c | 65 +++++++++++++++++++++++----------------------- | ||
13 | 1 file changed, 32 insertions(+), 33 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-a64.c | ||
18 | +++ b/target/arm/translate-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
20 | case 0x05: /* FMLS */ | ||
21 | case 0x09: /* FMUL */ | ||
22 | case 0x19: /* FMULX */ | ||
23 | - if (size == 1) { | ||
24 | - unallocated_encoding(s); | ||
25 | - return; | ||
26 | - } | ||
27 | is_fp = true; | ||
28 | break; | ||
29 | default: | ||
30 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
31 | if (is_fp) { | ||
32 | /* convert insn encoded size to TCGMemOp size */ | ||
33 | switch (size) { | ||
34 | - case 2: /* single precision */ | ||
35 | - size = MO_32; | ||
36 | - index = h << 1 | l; | ||
37 | - rm |= (m << 4); | ||
38 | - break; | ||
39 | - case 3: /* double precision */ | ||
40 | - size = MO_64; | ||
41 | - if (l || !is_q) { | ||
42 | + case 0: /* half-precision */ | ||
43 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | - index = h; | ||
48 | - rm |= (m << 4); | ||
49 | - break; | ||
50 | - case 0: /* half precision */ | ||
51 | size = MO_16; | ||
52 | - index = h << 2 | l << 1 | m; | ||
53 | - is_fp16 = true; | ||
54 | - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
55 | - break; | ||
56 | - } | ||
57 | - /* fallthru */ | ||
58 | - default: /* unallocated */ | ||
59 | - unallocated_encoding(s); | ||
60 | - return; | ||
61 | - } | ||
62 | - } else { | ||
63 | - switch (size) { | ||
64 | - case 1: | ||
65 | - index = h << 2 | l << 1 | m; | ||
66 | break; | ||
67 | - case 2: | ||
68 | - index = h << 1 | l; | ||
69 | - rm |= (m << 4); | ||
70 | + case MO_32: /* single precision */ | ||
71 | + case MO_64: /* double precision */ | ||
72 | break; | ||
73 | default: | ||
74 | unallocated_encoding(s); | ||
75 | return; | ||
76 | } | ||
77 | + } else { | ||
78 | + switch (size) { | ||
79 | + case MO_8: | ||
80 | + case MO_64: | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + } | ||
85 | + | ||
86 | + /* Given TCGMemOp size, adjust register and indexing. */ | ||
87 | + switch (size) { | ||
88 | + case MO_16: | ||
89 | + index = h << 2 | l << 1 | m; | ||
90 | + break; | ||
91 | + case MO_32: | ||
92 | + index = h << 1 | l; | ||
93 | + rm |= m << 4; | ||
94 | + break; | ||
95 | + case MO_64: | ||
96 | + if (l || !is_q) { | ||
97 | + unallocated_encoding(s); | ||
98 | + return; | ||
99 | + } | ||
100 | + index = h; | ||
101 | + rm |= m << 4; | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | } | ||
106 | |||
107 | if (!fp_access_check(s)) { | ||
108 | -- | ||
109 | 2.16.2 | ||
110 | |||
111 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-7-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 29 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
16 | case 0x19: /* FMULX */ | ||
17 | is_fp = true; | ||
18 | break; | ||
19 | + case 0x1d: /* SQRDMLAH */ | ||
20 | + case 0x1f: /* SQRDMLSH */ | ||
21 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
22 | + unallocated_encoding(s); | ||
23 | + return; | ||
24 | + } | ||
25 | + break; | ||
26 | default: | ||
27 | unallocated_encoding(s); | ||
28 | return; | ||
29 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
30 | tcg_op, tcg_idx); | ||
31 | } | ||
32 | break; | ||
33 | + case 0x1d: /* SQRDMLAH */ | ||
34 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
35 | + is_scalar ? size : MO_32); | ||
36 | + if (size == 1) { | ||
37 | + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | ||
38 | + tcg_op, tcg_idx, tcg_res); | ||
39 | + } else { | ||
40 | + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | ||
41 | + tcg_op, tcg_idx, tcg_res); | ||
42 | + } | ||
43 | + break; | ||
44 | + case 0x1f: /* SQRDMLSH */ | ||
45 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
46 | + is_scalar ? size : MO_32); | ||
47 | + if (size == 1) { | ||
48 | + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | ||
49 | + tcg_op, tcg_idx, tcg_res); | ||
50 | + } else { | ||
51 | + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | ||
52 | + tcg_op, tcg_idx, tcg_res); | ||
53 | + } | ||
54 | + break; | ||
55 | default: | ||
56 | g_assert_not_reached(); | ||
57 | } | ||
58 | -- | ||
59 | 2.16.2 | ||
60 | |||
61 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-8-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++----------- | ||
9 | 1 file changed, 67 insertions(+), 19 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #include "disas/disas.h" | ||
17 | #include "exec/exec-all.h" | ||
18 | #include "tcg-op.h" | ||
19 | +#include "tcg-op-gvec.h" | ||
20 | #include "qemu/log.h" | ||
21 | #include "qemu/bitops.h" | ||
22 | #include "arm_ldst.h" | ||
23 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_narrow_op(int op, int u, int size, | ||
24 | #define NEON_3R_VPMAX 20 | ||
25 | #define NEON_3R_VPMIN 21 | ||
26 | #define NEON_3R_VQDMULH_VQRDMULH 22 | ||
27 | -#define NEON_3R_VPADD 23 | ||
28 | +#define NEON_3R_VPADD_VQRDMLAH 23 | ||
29 | #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ | ||
30 | -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ | ||
31 | +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ | ||
32 | #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ | ||
33 | #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ | ||
34 | #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ | ||
35 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_3r_sizes[] = { | ||
36 | [NEON_3R_VPMAX] = 0x7, | ||
37 | [NEON_3R_VPMIN] = 0x7, | ||
38 | [NEON_3R_VQDMULH_VQRDMULH] = 0x6, | ||
39 | - [NEON_3R_VPADD] = 0x7, | ||
40 | + [NEON_3R_VPADD_VQRDMLAH] = 0x7, | ||
41 | [NEON_3R_SHA] = 0xf, /* size field encodes op type */ | ||
42 | - [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */ | ||
43 | + [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ | ||
44 | [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ | ||
45 | [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ | ||
46 | [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ | ||
47 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_2rm_sizes[] = { | ||
48 | [NEON_2RM_VCVT_UF] = 0x4, | ||
49 | }; | ||
50 | |||
51 | + | ||
52 | +/* Expand v8.1 simd helper. */ | ||
53 | +static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, | ||
54 | + int q, int rd, int rn, int rm) | ||
55 | +{ | ||
56 | + if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
57 | + int opr_sz = (1 + q) * 8; | ||
58 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
59 | + vfp_reg_offset(1, rn), | ||
60 | + vfp_reg_offset(1, rm), cpu_env, | ||
61 | + opr_sz, opr_sz, 0, fn); | ||
62 | + return 0; | ||
63 | + } | ||
64 | + return 1; | ||
65 | +} | ||
66 | + | ||
67 | /* Translate a NEON data processing instruction. Return nonzero if the | ||
68 | instruction is invalid. | ||
69 | We process data in a mixture of 32-bit and 64-bit chunks. | ||
70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
71 | if (q && ((rd | rn | rm) & 1)) { | ||
72 | return 1; | ||
73 | } | ||
74 | - /* | ||
75 | - * The SHA-1/SHA-256 3-register instructions require special treatment | ||
76 | - * here, as their size field is overloaded as an op type selector, and | ||
77 | - * they all consume their input in a single pass. | ||
78 | - */ | ||
79 | - if (op == NEON_3R_SHA) { | ||
80 | + switch (op) { | ||
81 | + case NEON_3R_SHA: | ||
82 | + /* The SHA-1/SHA-256 3-register instructions require special | ||
83 | + * treatment here, as their size field is overloaded as an | ||
84 | + * op type selector, and they all consume their input in a | ||
85 | + * single pass. | ||
86 | + */ | ||
87 | if (!q) { | ||
88 | return 1; | ||
89 | } | ||
90 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
91 | tcg_temp_free_ptr(ptr2); | ||
92 | tcg_temp_free_ptr(ptr3); | ||
93 | return 0; | ||
94 | + | ||
95 | + case NEON_3R_VPADD_VQRDMLAH: | ||
96 | + if (!u) { | ||
97 | + break; /* VPADD */ | ||
98 | + } | ||
99 | + /* VQRDMLAH */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16, | ||
103 | + q, rd, rn, rm); | ||
104 | + case 2: | ||
105 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32, | ||
106 | + q, rd, rn, rm); | ||
107 | + } | ||
108 | + return 1; | ||
109 | + | ||
110 | + case NEON_3R_VFM_VQRDMLSH: | ||
111 | + if (!u) { | ||
112 | + /* VFM, VFMS */ | ||
113 | + if (size == 1) { | ||
114 | + return 1; | ||
115 | + } | ||
116 | + break; | ||
117 | + } | ||
118 | + /* VQRDMLSH */ | ||
119 | + switch (size) { | ||
120 | + case 1: | ||
121 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16, | ||
122 | + q, rd, rn, rm); | ||
123 | + case 2: | ||
124 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32, | ||
125 | + q, rd, rn, rm); | ||
126 | + } | ||
127 | + return 1; | ||
128 | } | ||
129 | if (size == 3 && op != NEON_3R_LOGIC) { | ||
130 | /* 64-bit element instructions. */ | ||
131 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
132 | rm = rtmp; | ||
133 | } | ||
134 | break; | ||
135 | - case NEON_3R_VPADD: | ||
136 | - if (u) { | ||
137 | - return 1; | ||
138 | - } | ||
139 | - /* Fall through */ | ||
140 | + case NEON_3R_VPADD_VQRDMLAH: | ||
141 | case NEON_3R_VPMAX: | ||
142 | case NEON_3R_VPMIN: | ||
143 | pairwise = 1; | ||
144 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
145 | return 1; | ||
146 | } | ||
147 | break; | ||
148 | - case NEON_3R_VFM: | ||
149 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { | ||
150 | + case NEON_3R_VFM_VQRDMLSH: | ||
151 | + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { | ||
152 | return 1; | ||
153 | } | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
156 | } | ||
157 | } | ||
158 | break; | ||
159 | - case NEON_3R_VPADD: | ||
160 | + case NEON_3R_VPADD_VQRDMLAH: | ||
161 | switch (size) { | ||
162 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; | ||
163 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | ||
164 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
165 | } | ||
166 | } | ||
167 | break; | ||
168 | - case NEON_3R_VFM: | ||
169 | + case NEON_3R_VFM_VQRDMLSH: | ||
170 | { | ||
171 | /* VFMA, VFMS: fused multiply-add */ | ||
172 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
173 | -- | ||
174 | 2.16.2 | ||
175 | |||
176 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-9-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- | ||
9 | 1 file changed, 42 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static const char *regnames[] = | ||
16 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | ||
17 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | ||
18 | |||
19 | +/* Function prototypes for gen_ functions calling Neon helpers. */ | ||
20 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
21 | + TCGv_i32, TCGv_i32); | ||
22 | + | ||
23 | /* initialize TCG globals. */ | ||
24 | void arm_translate_init(void) | ||
25 | { | ||
26 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
27 | } | ||
28 | neon_store_reg64(cpu_V0, rd + pass); | ||
29 | } | ||
30 | - | ||
31 | - | ||
32 | break; | ||
33 | - default: /* 14 and 15 are RESERVED */ | ||
34 | - return 1; | ||
35 | + case 14: /* VQRDMLAH scalar */ | ||
36 | + case 15: /* VQRDMLSH scalar */ | ||
37 | + { | ||
38 | + NeonGenThreeOpEnvFn *fn; | ||
39 | + | ||
40 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
41 | + return 1; | ||
42 | + } | ||
43 | + if (u && ((rd | rn) & 1)) { | ||
44 | + return 1; | ||
45 | + } | ||
46 | + if (op == 14) { | ||
47 | + if (size == 1) { | ||
48 | + fn = gen_helper_neon_qrdmlah_s16; | ||
49 | + } else { | ||
50 | + fn = gen_helper_neon_qrdmlah_s32; | ||
51 | + } | ||
52 | + } else { | ||
53 | + if (size == 1) { | ||
54 | + fn = gen_helper_neon_qrdmlsh_s16; | ||
55 | + } else { | ||
56 | + fn = gen_helper_neon_qrdmlsh_s32; | ||
57 | + } | ||
58 | + } | ||
59 | + | ||
60 | + tmp2 = neon_get_scalar(size, rm); | ||
61 | + for (pass = 0; pass < (u ? 4 : 2); pass++) { | ||
62 | + tmp = neon_load_reg(rn, pass); | ||
63 | + tmp3 = neon_load_reg(rd, pass); | ||
64 | + fn(tmp, cpu_env, tmp, tmp2, tmp3); | ||
65 | + tcg_temp_free_i32(tmp3); | ||
66 | + neon_store_reg(rd, pass, tmp); | ||
67 | + } | ||
68 | + tcg_temp_free_i32(tmp2); | ||
69 | + } | ||
70 | + break; | ||
71 | + default: | ||
72 | + g_assert_not_reached(); | ||
73 | } | ||
74 | } | ||
75 | } else { /* size == 3 */ | ||
76 | -- | ||
77 | 2.16.2 | ||
78 | |||
79 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-10-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.c | 1 + | ||
11 | target/arm/cpu64.c | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | ||
19 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | ||
20 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
21 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
23 | cpu->midr = 0xffffffff; | ||
24 | } | ||
25 | #endif | ||
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/cpu64.c | ||
29 | +++ b/target/arm/cpu64.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | ||
31 | set_feature(&cpu->env, ARM_FEATURE_V8_SM4); | ||
32 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
33 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
35 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | ||
36 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
37 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Not enabled anywhere yet. | ||
4 | |||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180228193125.20577-11-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.h | 1 + | ||
11 | linux-user/elfload.c | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
19 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | ||
20 | ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | ||
21 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | ||
22 | + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ | ||
23 | }; | ||
24 | |||
25 | static inline int arm_feature(CPUARMState *env, int feature) | ||
26 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/linux-user/elfload.c | ||
29 | +++ b/linux-user/elfload.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
31 | GET_FEATURE(ARM_FEATURE_V8_FP16, | ||
32 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | ||
33 | GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | ||
34 | + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); | ||
35 | #undef GET_FEATURE | ||
36 | |||
37 | return hwcaps; | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-12-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/helper.h | 7 ++++ | ||
9 | target/arm/translate-a64.c | 48 ++++++++++++++++++++++- | ||
10 | target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ | ||
11 | 3 files changed, 151 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/helper.h | ||
16 | +++ b/target/arm/helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | ||
18 | DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | ||
19 | void, ptr, ptr, ptr, ptr, i32) | ||
20 | |||
21 | +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, | ||
22 | + void, ptr, ptr, ptr, ptr, i32) | ||
23 | +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | + | ||
28 | #ifdef TARGET_AARCH64 | ||
29 | #include "helper-a64.h" | ||
30 | #endif | ||
31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate-a64.c | ||
34 | +++ b/target/arm/translate-a64.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
36 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
37 | } | ||
38 | |||
39 | +/* Expand a 3-operand + fpstatus pointer + simd data value operation using | ||
40 | + * an out-of-line helper. | ||
41 | + */ | ||
42 | +static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | ||
43 | + int rm, bool is_fp16, int data, | ||
44 | + gen_helper_gvec_3_ptr *fn) | ||
45 | +{ | ||
46 | + TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | ||
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), fpst, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | ||
51 | + tcg_temp_free_ptr(fpst); | ||
52 | +} | ||
53 | + | ||
54 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | ||
55 | * than the 32 bit equivalent. | ||
56 | */ | ||
57 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
58 | int size = extract32(insn, 22, 2); | ||
59 | bool u = extract32(insn, 29, 1); | ||
60 | bool is_q = extract32(insn, 30, 1); | ||
61 | - int feature; | ||
62 | + int feature, rot; | ||
63 | |||
64 | switch (u * 16 + opcode) { | ||
65 | case 0x10: /* SQRDMLAH (vector) */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | } | ||
68 | feature = ARM_FEATURE_V8_RDM; | ||
69 | break; | ||
70 | + case 0xc: /* FCADD, #90 */ | ||
71 | + case 0xe: /* FCADD, #270 */ | ||
72 | + if (size == 0 | ||
73 | + || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) | ||
74 | + || (size == 3 && !is_q)) { | ||
75 | + unallocated_encoding(s); | ||
76 | + return; | ||
77 | + } | ||
78 | + feature = ARM_FEATURE_V8_FCMA; | ||
79 | + break; | ||
80 | default: | ||
81 | unallocated_encoding(s); | ||
82 | return; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
84 | } | ||
85 | return; | ||
86 | |||
87 | + case 0xc: /* FCADD, #90 */ | ||
88 | + case 0xe: /* FCADD, #270 */ | ||
89 | + rot = extract32(opcode, 1, 1); | ||
90 | + switch (size) { | ||
91 | + case 1: | ||
92 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
93 | + gen_helper_gvec_fcaddh); | ||
94 | + break; | ||
95 | + case 2: | ||
96 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
97 | + gen_helper_gvec_fcadds); | ||
98 | + break; | ||
99 | + case 3: | ||
100 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
101 | + gen_helper_gvec_fcaddd); | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | + } | ||
106 | + return; | ||
107 | + | ||
108 | default: | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/vec_helper.c | ||
114 | +++ b/target/arm/vec_helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | #include "exec/exec-all.h" | ||
117 | #include "exec/helper-proto.h" | ||
118 | #include "tcg/tcg-gvec-desc.h" | ||
119 | +#include "fpu/softfloat.h" | ||
120 | |||
121 | |||
122 | +/* Note that vector data is stored in host-endian 64-bit chunks, | ||
123 | + so addressing units smaller than that needs a host-endian fixup. */ | ||
124 | +#ifdef HOST_WORDS_BIGENDIAN | ||
125 | +#define H1(x) ((x) ^ 7) | ||
126 | +#define H2(x) ((x) ^ 3) | ||
127 | +#define H4(x) ((x) ^ 1) | ||
128 | +#else | ||
129 | +#define H1(x) (x) | ||
130 | +#define H2(x) (x) | ||
131 | +#define H4(x) (x) | ||
132 | +#endif | ||
133 | + | ||
134 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
135 | |||
136 | static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
137 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
138 | } | ||
139 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
140 | } | ||
141 | + | ||
142 | +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, | ||
143 | + void *vfpst, uint32_t desc) | ||
144 | +{ | ||
145 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
146 | + float16 *d = vd; | ||
147 | + float16 *n = vn; | ||
148 | + float16 *m = vm; | ||
149 | + float_status *fpst = vfpst; | ||
150 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
151 | + uint32_t neg_imag = neg_real ^ 1; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
155 | + neg_real <<= 15; | ||
156 | + neg_imag <<= 15; | ||
157 | + | ||
158 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
159 | + float16 e0 = n[H2(i)]; | ||
160 | + float16 e1 = m[H2(i + 1)] ^ neg_imag; | ||
161 | + float16 e2 = n[H2(i + 1)]; | ||
162 | + float16 e3 = m[H2(i)] ^ neg_real; | ||
163 | + | ||
164 | + d[H2(i)] = float16_add(e0, e1, fpst); | ||
165 | + d[H2(i + 1)] = float16_add(e2, e3, fpst); | ||
166 | + } | ||
167 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
168 | +} | ||
169 | + | ||
170 | +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, | ||
171 | + void *vfpst, uint32_t desc) | ||
172 | +{ | ||
173 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
174 | + float32 *d = vd; | ||
175 | + float32 *n = vn; | ||
176 | + float32 *m = vm; | ||
177 | + float_status *fpst = vfpst; | ||
178 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
179 | + uint32_t neg_imag = neg_real ^ 1; | ||
180 | + uintptr_t i; | ||
181 | + | ||
182 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
183 | + neg_real <<= 31; | ||
184 | + neg_imag <<= 31; | ||
185 | + | ||
186 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
187 | + float32 e0 = n[H4(i)]; | ||
188 | + float32 e1 = m[H4(i + 1)] ^ neg_imag; | ||
189 | + float32 e2 = n[H4(i + 1)]; | ||
190 | + float32 e3 = m[H4(i)] ^ neg_real; | ||
191 | + | ||
192 | + d[H4(i)] = float32_add(e0, e1, fpst); | ||
193 | + d[H4(i + 1)] = float32_add(e2, e3, fpst); | ||
194 | + } | ||
195 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
196 | +} | ||
197 | + | ||
198 | +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
199 | + void *vfpst, uint32_t desc) | ||
200 | +{ | ||
201 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
202 | + float64 *d = vd; | ||
203 | + float64 *n = vn; | ||
204 | + float64 *m = vm; | ||
205 | + float_status *fpst = vfpst; | ||
206 | + uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); | ||
207 | + uint64_t neg_imag = neg_real ^ 1; | ||
208 | + uintptr_t i; | ||
209 | + | ||
210 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
211 | + neg_real <<= 63; | ||
212 | + neg_imag <<= 63; | ||
213 | + | ||
214 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
215 | + float64 e0 = n[i]; | ||
216 | + float64 e1 = m[i + 1] ^ neg_imag; | ||
217 | + float64 e2 = n[i + 1]; | ||
218 | + float64 e3 = m[i] ^ neg_real; | ||
219 | + | ||
220 | + d[i] = float64_add(e0, e1, fpst); | ||
221 | + d[i + 1] = float64_add(e2, e3, fpst); | ||
222 | + } | ||
223 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
224 | +} | ||
225 | -- | ||
226 | 2.16.2 | ||
227 | |||
228 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20180228193125.20577-13-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | [PMM: renamed e1/e2/e3/e4 to use the same naming as the version | ||
7 | of the pseudocode in the Arm ARM] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/helper.h | 11 ++++ | ||
11 | target/arm/translate-a64.c | 94 +++++++++++++++++++++++++--- | ||
12 | target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 246 insertions(+), 8 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.h | ||
18 | +++ b/target/arm/helper.h | ||
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | ||
20 | DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | ||
21 | void, ptr, ptr, ptr, ptr, i32) | ||
22 | |||
23 | +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, | ||
28 | + void, ptr, ptr, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, | ||
30 | + void, ptr, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, | ||
32 | + void, ptr, ptr, ptr, ptr, i32) | ||
33 | + | ||
34 | #ifdef TARGET_AARCH64 | ||
35 | #include "helper-a64.h" | ||
36 | #endif | ||
37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/translate-a64.c | ||
40 | +++ b/target/arm/translate-a64.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
42 | } | ||
43 | feature = ARM_FEATURE_V8_RDM; | ||
44 | break; | ||
45 | + case 0x8: /* FCMLA, #0 */ | ||
46 | + case 0x9: /* FCMLA, #90 */ | ||
47 | + case 0xa: /* FCMLA, #180 */ | ||
48 | + case 0xb: /* FCMLA, #270 */ | ||
49 | case 0xc: /* FCADD, #90 */ | ||
50 | case 0xe: /* FCADD, #270 */ | ||
51 | if (size == 0 | ||
52 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
53 | } | ||
54 | return; | ||
55 | |||
56 | + case 0x8: /* FCMLA, #0 */ | ||
57 | + case 0x9: /* FCMLA, #90 */ | ||
58 | + case 0xa: /* FCMLA, #180 */ | ||
59 | + case 0xb: /* FCMLA, #270 */ | ||
60 | + rot = extract32(opcode, 0, 2); | ||
61 | + switch (size) { | ||
62 | + case 1: | ||
63 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | ||
64 | + gen_helper_gvec_fcmlah); | ||
65 | + break; | ||
66 | + case 2: | ||
67 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
68 | + gen_helper_gvec_fcmlas); | ||
69 | + break; | ||
70 | + case 3: | ||
71 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
72 | + gen_helper_gvec_fcmlad); | ||
73 | + break; | ||
74 | + default: | ||
75 | + g_assert_not_reached(); | ||
76 | + } | ||
77 | + return; | ||
78 | + | ||
79 | case 0xc: /* FCADD, #90 */ | ||
80 | case 0xe: /* FCADD, #270 */ | ||
81 | rot = extract32(opcode, 1, 1); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
83 | int rn = extract32(insn, 5, 5); | ||
84 | int rd = extract32(insn, 0, 5); | ||
85 | bool is_long = false; | ||
86 | - bool is_fp = false; | ||
87 | + int is_fp = 0; | ||
88 | bool is_fp16 = false; | ||
89 | int index; | ||
90 | TCGv_ptr fpst; | ||
91 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
92 | case 0x05: /* FMLS */ | ||
93 | case 0x09: /* FMUL */ | ||
94 | case 0x19: /* FMULX */ | ||
95 | - is_fp = true; | ||
96 | + is_fp = 1; | ||
97 | break; | ||
98 | case 0x1d: /* SQRDMLAH */ | ||
99 | case 0x1f: /* SQRDMLSH */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
101 | return; | ||
102 | } | ||
103 | break; | ||
104 | + case 0x11: /* FCMLA #0 */ | ||
105 | + case 0x13: /* FCMLA #90 */ | ||
106 | + case 0x15: /* FCMLA #180 */ | ||
107 | + case 0x17: /* FCMLA #270 */ | ||
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { | ||
109 | + unallocated_encoding(s); | ||
110 | + return; | ||
111 | + } | ||
112 | + is_fp = 2; | ||
113 | + break; | ||
114 | default: | ||
115 | unallocated_encoding(s); | ||
116 | return; | ||
117 | } | ||
118 | |||
119 | - if (is_fp) { | ||
120 | + switch (is_fp) { | ||
121 | + case 1: /* normal fp */ | ||
122 | /* convert insn encoded size to TCGMemOp size */ | ||
123 | switch (size) { | ||
124 | case 0: /* half-precision */ | ||
125 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
126 | - unallocated_encoding(s); | ||
127 | - return; | ||
128 | - } | ||
129 | size = MO_16; | ||
130 | + is_fp16 = true; | ||
131 | break; | ||
132 | case MO_32: /* single precision */ | ||
133 | case MO_64: /* double precision */ | ||
134 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
135 | unallocated_encoding(s); | ||
136 | return; | ||
137 | } | ||
138 | - } else { | ||
139 | + break; | ||
140 | + | ||
141 | + case 2: /* complex fp */ | ||
142 | + /* Each indexable element is a complex pair. */ | ||
143 | + size <<= 1; | ||
144 | + switch (size) { | ||
145 | + case MO_32: | ||
146 | + if (h && !is_q) { | ||
147 | + unallocated_encoding(s); | ||
148 | + return; | ||
149 | + } | ||
150 | + is_fp16 = true; | ||
151 | + break; | ||
152 | + case MO_64: | ||
153 | + break; | ||
154 | + default: | ||
155 | + unallocated_encoding(s); | ||
156 | + return; | ||
157 | + } | ||
158 | + break; | ||
159 | + | ||
160 | + default: /* integer */ | ||
161 | switch (size) { | ||
162 | case MO_8: | ||
163 | case MO_64: | ||
164 | unallocated_encoding(s); | ||
165 | return; | ||
166 | } | ||
167 | + break; | ||
168 | + } | ||
169 | + if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
170 | + unallocated_encoding(s); | ||
171 | + return; | ||
172 | } | ||
173 | |||
174 | /* Given TCGMemOp size, adjust register and indexing. */ | ||
175 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
176 | fpst = NULL; | ||
177 | } | ||
178 | |||
179 | + switch (16 * u + opcode) { | ||
180 | + case 0x11: /* FCMLA #0 */ | ||
181 | + case 0x13: /* FCMLA #90 */ | ||
182 | + case 0x15: /* FCMLA #180 */ | ||
183 | + case 0x17: /* FCMLA #270 */ | ||
184 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
185 | + vec_full_reg_offset(s, rn), | ||
186 | + vec_reg_offset(s, rm, index, size), fpst, | ||
187 | + is_q ? 16 : 8, vec_full_reg_size(s), | ||
188 | + extract32(insn, 13, 2), /* rot */ | ||
189 | + size == MO_64 | ||
190 | + ? gen_helper_gvec_fcmlas_idx | ||
191 | + : gen_helper_gvec_fcmlah_idx); | ||
192 | + tcg_temp_free_ptr(fpst); | ||
193 | + return; | ||
194 | + } | ||
195 | + | ||
196 | if (size == 3) { | ||
197 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | ||
198 | int pass; | ||
199 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/target/arm/vec_helper.c | ||
202 | +++ b/target/arm/vec_helper.c | ||
203 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
204 | } | ||
205 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
206 | } | ||
207 | + | ||
208 | +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, | ||
209 | + void *vfpst, uint32_t desc) | ||
210 | +{ | ||
211 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
212 | + float16 *d = vd; | ||
213 | + float16 *n = vn; | ||
214 | + float16 *m = vm; | ||
215 | + float_status *fpst = vfpst; | ||
216 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
217 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
218 | + uint32_t neg_real = flip ^ neg_imag; | ||
219 | + uintptr_t i; | ||
220 | + | ||
221 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
222 | + neg_real <<= 15; | ||
223 | + neg_imag <<= 15; | ||
224 | + | ||
225 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
226 | + float16 e2 = n[H2(i + flip)]; | ||
227 | + float16 e1 = m[H2(i + flip)] ^ neg_real; | ||
228 | + float16 e4 = e2; | ||
229 | + float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; | ||
230 | + | ||
231 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
232 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
233 | + } | ||
234 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
235 | +} | ||
236 | + | ||
237 | +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, | ||
238 | + void *vfpst, uint32_t desc) | ||
239 | +{ | ||
240 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
241 | + float16 *d = vd; | ||
242 | + float16 *n = vn; | ||
243 | + float16 *m = vm; | ||
244 | + float_status *fpst = vfpst; | ||
245 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
246 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
247 | + uint32_t neg_real = flip ^ neg_imag; | ||
248 | + uintptr_t i; | ||
249 | + float16 e1 = m[H2(flip)]; | ||
250 | + float16 e3 = m[H2(1 - flip)]; | ||
251 | + | ||
252 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
253 | + neg_real <<= 15; | ||
254 | + neg_imag <<= 15; | ||
255 | + e1 ^= neg_real; | ||
256 | + e3 ^= neg_imag; | ||
257 | + | ||
258 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
259 | + float16 e2 = n[H2(i + flip)]; | ||
260 | + float16 e4 = e2; | ||
261 | + | ||
262 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
263 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
264 | + } | ||
265 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
266 | +} | ||
267 | + | ||
268 | +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, | ||
269 | + void *vfpst, uint32_t desc) | ||
270 | +{ | ||
271 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
272 | + float32 *d = vd; | ||
273 | + float32 *n = vn; | ||
274 | + float32 *m = vm; | ||
275 | + float_status *fpst = vfpst; | ||
276 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
277 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
278 | + uint32_t neg_real = flip ^ neg_imag; | ||
279 | + uintptr_t i; | ||
280 | + | ||
281 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
282 | + neg_real <<= 31; | ||
283 | + neg_imag <<= 31; | ||
284 | + | ||
285 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
286 | + float32 e2 = n[H4(i + flip)]; | ||
287 | + float32 e1 = m[H4(i + flip)] ^ neg_real; | ||
288 | + float32 e4 = e2; | ||
289 | + float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; | ||
290 | + | ||
291 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
292 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
293 | + } | ||
294 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
295 | +} | ||
296 | + | ||
297 | +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, | ||
298 | + void *vfpst, uint32_t desc) | ||
299 | +{ | ||
300 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
301 | + float32 *d = vd; | ||
302 | + float32 *n = vn; | ||
303 | + float32 *m = vm; | ||
304 | + float_status *fpst = vfpst; | ||
305 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
306 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
307 | + uint32_t neg_real = flip ^ neg_imag; | ||
308 | + uintptr_t i; | ||
309 | + float32 e1 = m[H4(flip)]; | ||
310 | + float32 e3 = m[H4(1 - flip)]; | ||
311 | + | ||
312 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
313 | + neg_real <<= 31; | ||
314 | + neg_imag <<= 31; | ||
315 | + e1 ^= neg_real; | ||
316 | + e3 ^= neg_imag; | ||
317 | + | ||
318 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
319 | + float32 e2 = n[H4(i + flip)]; | ||
320 | + float32 e4 = e2; | ||
321 | + | ||
322 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
323 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
324 | + } | ||
325 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
326 | +} | ||
327 | + | ||
328 | +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, | ||
329 | + void *vfpst, uint32_t desc) | ||
330 | +{ | ||
331 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
332 | + float64 *d = vd; | ||
333 | + float64 *n = vn; | ||
334 | + float64 *m = vm; | ||
335 | + float_status *fpst = vfpst; | ||
336 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
337 | + uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
338 | + uint64_t neg_real = flip ^ neg_imag; | ||
339 | + uintptr_t i; | ||
340 | + | ||
341 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
342 | + neg_real <<= 63; | ||
343 | + neg_imag <<= 63; | ||
344 | + | ||
345 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
346 | + float64 e2 = n[i + flip]; | ||
347 | + float64 e1 = m[i + flip] ^ neg_real; | ||
348 | + float64 e4 = e2; | ||
349 | + float64 e3 = m[i + 1 - flip] ^ neg_imag; | ||
350 | + | ||
351 | + d[i] = float64_muladd(e2, e1, d[i], 0, fpst); | ||
352 | + d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); | ||
353 | + } | ||
354 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
355 | +} | ||
356 | -- | ||
357 | 2.16.2 | ||
358 | |||
359 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20180228193125.20577-14-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 68 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
16 | return 0; | ||
17 | } | ||
18 | |||
19 | +/* Advanced SIMD three registers of the same length extension. | ||
20 | + * 31 25 23 22 20 16 12 11 10 9 8 3 0 | ||
21 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
22 | + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
23 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
24 | + */ | ||
25 | +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
26 | +{ | ||
27 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | ||
28 | + int rd, rn, rm, rot, size, opr_sz; | ||
29 | + TCGv_ptr fpst; | ||
30 | + bool q; | ||
31 | + | ||
32 | + q = extract32(insn, 6, 1); | ||
33 | + VFP_DREG_D(rd, insn); | ||
34 | + VFP_DREG_N(rn, insn); | ||
35 | + VFP_DREG_M(rm, insn); | ||
36 | + if ((rd | rn | rm) & q) { | ||
37 | + return 1; | ||
38 | + } | ||
39 | + | ||
40 | + if ((insn & 0xfe200f10) == 0xfc200800) { | ||
41 | + /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ | ||
42 | + size = extract32(insn, 20, 1); | ||
43 | + rot = extract32(insn, 23, 2); | ||
44 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
45 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
46 | + return 1; | ||
47 | + } | ||
48 | + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | ||
49 | + } else if ((insn & 0xfea00f10) == 0xfc800800) { | ||
50 | + /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | ||
51 | + size = extract32(insn, 20, 1); | ||
52 | + rot = extract32(insn, 24, 1); | ||
53 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
54 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
55 | + return 1; | ||
56 | + } | ||
57 | + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
58 | + } else { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + if (s->fp_excp_el) { | ||
63 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
64 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
65 | + return 0; | ||
66 | + } | ||
67 | + if (!s->vfp_enabled) { | ||
68 | + return 1; | ||
69 | + } | ||
70 | + | ||
71 | + opr_sz = (1 + q) * 8; | ||
72 | + fpst = get_fpstatus_ptr(1); | ||
73 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
74 | + vfp_reg_offset(1, rn), | ||
75 | + vfp_reg_offset(1, rm), fpst, | ||
76 | + opr_sz, opr_sz, rot, fn_gvec_ptr); | ||
77 | + tcg_temp_free_ptr(fpst); | ||
78 | + return 0; | ||
79 | +} | ||
80 | + | ||
81 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | ||
82 | { | ||
83 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
84 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
85 | } | ||
86 | } | ||
87 | } | ||
88 | + } else if ((insn & 0x0e000a00) == 0x0c000800 | ||
89 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
90 | + if (disas_neon_insn_3same_ext(s, insn)) { | ||
91 | + goto illegal_op; | ||
92 | + } | ||
93 | + return; | ||
94 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
95 | /* Coprocessor double register transfer. */ | ||
96 | ARCH(5TE); | ||
97 | -- | ||
98 | 2.16.2 | ||
99 | |||
100 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Happily, the bits are in the same places compared to a32. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20180228193125.20577-16-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate.c | 14 +++++++++++++- | ||
11 | 1 file changed, 13 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate.c | ||
16 | +++ b/target/arm/translate.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
18 | default_exception_el(s)); | ||
19 | break; | ||
20 | } | ||
21 | - if (((insn >> 24) & 3) == 3) { | ||
22 | + if ((insn & 0xfe000a00) == 0xfc000800 | ||
23 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
24 | + /* The Thumb2 and ARM encodings are identical. */ | ||
25 | + if (disas_neon_insn_3same_ext(s, insn)) { | ||
26 | + goto illegal_op; | ||
27 | + } | ||
28 | + } else if ((insn & 0xff000a00) == 0xfe000800 | ||
29 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
30 | + /* The Thumb2 and ARM encodings are identical. */ | ||
31 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
32 | + goto illegal_op; | ||
33 | + } | ||
34 | + } else if (((insn >> 24) & 3) == 3) { | ||
35 | /* Translate into the equivalent ARM encoding. */ | ||
36 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | ||
37 | if (disas_neon_data_insn(s, insn)) { | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |