1 | Second pull request of the week; mostly RTH's support for some | 1 | arm queue: big stuff here is my MVE codegen optimisation, |
---|---|---|---|
2 | new-in-v8.1/v8.3 instructions, and my v8M board model. | 2 | and Alex's Apple Silicon hvf support. |
3 | 3 | ||
4 | thanks | ||
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f: | 6 | The following changes since commit 7adb961995a3744f51396502b33ad04a56a317c3: |
8 | 7 | ||
9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000) | 8 | Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210916' into staging (2021-09-19 18:53:29 +0100) |
10 | 9 | ||
11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210920 |
14 | 13 | ||
15 | for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078: | 14 | for you to fetch changes up to 1dc5a60bfe406bc1122d68cbdefda38d23134b27: |
16 | 15 | ||
17 | target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000) | 16 | target/arm: Optimize MVE 1op-immediate insns (2021-09-20 14:18:01 +0100) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | target-arm queue: | 19 | target-arm queue: |
21 | * implement FCMA and RDM v8.1 and v8.3 instructions | 20 | * Optimize codegen for MVE when predication not active |
22 | * enable Cortex-M33 v8M core, and provide new mps2-an505 board model | 21 | * hvf: Add Apple Silicon support |
23 | that uses it | 22 | * hw/intc: Set GIC maintenance interrupt level to only 0 or 1 |
24 | * decodetree: Propagate return value from translate subroutines | 23 | * Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator |
25 | * xlnx-zynqmp: Implement the RTC device | 24 | * elf2dmp: Fix coverity nits |
26 | 25 | ||
27 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
28 | Alistair Francis (3): | 27 | Alexander Graf (7): |
29 | xlnx-zynqmp-rtc: Initial commit | 28 | arm: Move PMC register definitions to internals.h |
30 | xlnx-zynqmp-rtc: Add basic time support | 29 | hvf: Add execute to dirty log permission bitmap |
31 | xlnx-zynqmp: Connect the RTC device | 30 | hvf: Introduce hvf_arch_init() callback |
31 | hvf: Add Apple Silicon support | ||
32 | hvf: arm: Implement PSCI handling | ||
33 | arm: Add Hypervisor.framework build target | ||
34 | hvf: arm: Add rudimentary PMC support | ||
32 | 35 | ||
33 | Peter Maydell (19): | 36 | Peter Collingbourne (1): |
34 | loader: Add new load_ramdisk_as() | 37 | arm/hvf: Add a WFI handler |
35 | hw/arm/boot: Honour CPU's address space for image loads | ||
36 | hw/arm/armv7m: Honour CPU's address space for image loads | ||
37 | target/arm: Define an IDAU interface | ||
38 | armv7m: Forward idau property to CPU object | ||
39 | target/arm: Define init-svtor property for the reset secure VTOR value | ||
40 | armv7m: Forward init-svtor property to CPU object | ||
41 | target/arm: Add Cortex-M33 | ||
42 | hw/misc/unimp: Move struct to header file | ||
43 | include/hw/or-irq.h: Add missing include guard | ||
44 | qdev: Add new qdev_init_gpio_in_named_with_opaque() | ||
45 | hw/core/split-irq: Device that splits IRQ lines | ||
46 | hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505 | ||
47 | hw/misc/tz-ppc: Model TrustZone peripheral protection controller | ||
48 | hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton | ||
49 | hw/misc/iotkit-secctl: Add handling for PPCs | ||
50 | hw/misc/iotkit-secctl: Add remaining simple registers | ||
51 | hw/arm/iotkit: Model Arm IOT Kit | ||
52 | mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image | ||
53 | 38 | ||
54 | Richard Henderson (17): | 39 | Peter Maydell (18): |
55 | decodetree: Propagate return value from translate subroutines | 40 | elf2dmp: Check curl_easy_setopt() return value |
56 | target/arm: Add ARM_FEATURE_V8_RDM | 41 | elf2dmp: Fail cleanly if PDB file specifies zero block_size |
57 | target/arm: Refactor disas_simd_indexed decode | 42 | target/arm: Don't skip M-profile reset entirely in user mode |
58 | target/arm: Refactor disas_simd_indexed size checks | 43 | target/arm: Always clear exclusive monitor on reset |
59 | target/arm: Decode aa64 armv8.1 scalar three same extra | 44 | target/arm: Consolidate ifdef blocks in reset |
60 | target/arm: Decode aa64 armv8.1 three same extra | 45 | hvf: arm: Implement -cpu host |
61 | target/arm: Decode aa64 armv8.1 scalar/vector x indexed element | 46 | target/arm: Avoid goto_tb if we're trying to exit to the main loop |
62 | target/arm: Decode aa32 armv8.1 three same | 47 | target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration |
63 | target/arm: Decode aa32 armv8.1 two reg and a scalar | 48 | target/arm: Add TB flag for "MVE insns not predicated" |
64 | target/arm: Enable ARM_FEATURE_V8_RDM | 49 | target/arm: Optimize MVE logic ops |
65 | target/arm: Add ARM_FEATURE_V8_FCMA | 50 | target/arm: Optimize MVE arithmetic ops |
66 | target/arm: Decode aa64 armv8.3 fcadd | 51 | target/arm: Optimize MVE VNEG, VABS |
67 | target/arm: Decode aa64 armv8.3 fcmla | 52 | target/arm: Optimize MVE VDUP |
68 | target/arm: Decode aa32 armv8.3 3-same | 53 | target/arm: Optimize MVE VMVN |
69 | target/arm: Decode aa32 armv8.3 2-reg-index | 54 | target/arm: Optimize MVE VSHL, VSHR immediate forms |
70 | target/arm: Decode t32 simd 3reg and 2reg_scalar extension | 55 | target/arm: Optimize MVE VSHLL and VMOVL |
71 | target/arm: Enable ARM_FEATURE_V8_FCMA | 56 | target/arm: Optimize MVE VSLI and VSRI |
57 | target/arm: Optimize MVE 1op-immediate insns | ||
72 | 58 | ||
73 | hw/arm/Makefile.objs | 2 + | 59 | Shashi Mallela (1): |
74 | hw/core/Makefile.objs | 1 + | 60 | hw/intc: Set GIC maintenance interrupt level to only 0 or 1 |
75 | hw/misc/Makefile.objs | 4 + | ||
76 | hw/timer/Makefile.objs | 1 + | ||
77 | target/arm/Makefile.objs | 2 +- | ||
78 | include/hw/arm/armv7m.h | 5 + | ||
79 | include/hw/arm/iotkit.h | 109 ++++++ | ||
80 | include/hw/arm/xlnx-zynqmp.h | 2 + | ||
81 | include/hw/core/split-irq.h | 57 +++ | ||
82 | include/hw/irq.h | 4 +- | ||
83 | include/hw/loader.h | 12 +- | ||
84 | include/hw/misc/iotkit-secctl.h | 103 ++++++ | ||
85 | include/hw/misc/mps2-fpgaio.h | 43 +++ | ||
86 | include/hw/misc/tz-ppc.h | 101 ++++++ | ||
87 | include/hw/misc/unimp.h | 10 + | ||
88 | include/hw/or-irq.h | 5 + | ||
89 | include/hw/qdev-core.h | 30 +- | ||
90 | include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++ | ||
91 | target/arm/cpu.h | 8 + | ||
92 | target/arm/helper.h | 31 ++ | ||
93 | target/arm/idau.h | 61 ++++ | ||
94 | hw/arm/armv7m.c | 35 +- | ||
95 | hw/arm/boot.c | 119 ++++--- | ||
96 | hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++ | ||
97 | hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++ | ||
98 | hw/arm/xlnx-zynqmp.c | 14 + | ||
99 | hw/core/loader.c | 8 +- | ||
100 | hw/core/qdev.c | 8 +- | ||
101 | hw/core/split-irq.c | 89 +++++ | ||
102 | hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++ | ||
103 | hw/misc/mps2-fpgaio.c | 176 ++++++++++ | ||
104 | hw/misc/tz-ppc.c | 302 ++++++++++++++++ | ||
105 | hw/misc/unimp.c | 10 - | ||
106 | hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++ | ||
107 | linux-user/elfload.c | 2 + | ||
108 | target/arm/cpu.c | 66 +++- | ||
109 | target/arm/cpu64.c | 2 + | ||
110 | target/arm/helper.c | 28 +- | ||
111 | target/arm/translate-a64.c | 514 +++++++++++++++++++++------ | ||
112 | target/arm/translate.c | 275 +++++++++++++-- | ||
113 | target/arm/vec_helper.c | 429 ++++++++++++++++++++++ | ||
114 | default-configs/arm-softmmu.mak | 5 + | ||
115 | hw/misc/trace-events | 24 ++ | ||
116 | hw/timer/trace-events | 3 + | ||
117 | scripts/decodetree.py | 5 +- | ||
118 | 45 files changed, 4668 insertions(+), 200 deletions(-) | ||
119 | create mode 100644 include/hw/arm/iotkit.h | ||
120 | create mode 100644 include/hw/core/split-irq.h | ||
121 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
122 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
123 | create mode 100644 include/hw/misc/tz-ppc.h | ||
124 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
125 | create mode 100644 target/arm/idau.h | ||
126 | create mode 100644 hw/arm/iotkit.c | ||
127 | create mode 100644 hw/arm/mps2-tz.c | ||
128 | create mode 100644 hw/core/split-irq.c | ||
129 | create mode 100644 hw/misc/iotkit-secctl.c | ||
130 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
131 | create mode 100644 hw/misc/tz-ppc.c | ||
132 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
133 | create mode 100644 target/arm/vec_helper.c | ||
134 | 61 | ||
62 | meson.build | 8 + | ||
63 | include/sysemu/hvf_int.h | 12 +- | ||
64 | target/arm/cpu.h | 6 +- | ||
65 | target/arm/hvf_arm.h | 18 + | ||
66 | target/arm/internals.h | 44 ++ | ||
67 | target/arm/kvm_arm.h | 2 - | ||
68 | target/arm/translate.h | 2 + | ||
69 | accel/hvf/hvf-accel-ops.c | 21 +- | ||
70 | contrib/elf2dmp/download.c | 22 +- | ||
71 | contrib/elf2dmp/pdb.c | 4 + | ||
72 | hw/intc/arm_gicv3_cpuif.c | 5 +- | ||
73 | target/arm/cpu.c | 56 +- | ||
74 | target/arm/helper.c | 77 ++- | ||
75 | target/arm/hvf/hvf.c | 1278 +++++++++++++++++++++++++++++++++++++++++ | ||
76 | target/arm/machine.c | 13 + | ||
77 | target/arm/translate-m-nocp.c | 8 +- | ||
78 | target/arm/translate-mve.c | 310 +++++++--- | ||
79 | target/arm/translate-vfp.c | 33 +- | ||
80 | target/arm/translate.c | 42 +- | ||
81 | target/i386/hvf/hvf.c | 10 + | ||
82 | MAINTAINERS | 5 + | ||
83 | target/arm/hvf/meson.build | 3 + | ||
84 | target/arm/hvf/trace-events | 11 + | ||
85 | target/arm/meson.build | 2 + | ||
86 | 24 files changed, 1824 insertions(+), 168 deletions(-) | ||
87 | create mode 100644 target/arm/hvf_arm.h | ||
88 | create mode 100644 target/arm/hvf/hvf.c | ||
89 | create mode 100644 target/arm/hvf/meson.build | ||
90 | create mode 100644 target/arm/hvf/trace-events | ||
91 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Initial commit of the ZynqMP RTC device. | ||
4 | |||
5 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/timer/Makefile.objs | 1 + | ||
10 | include/hw/timer/xlnx-zynqmp-rtc.h | 84 +++++++++++++++ | ||
11 | hw/timer/xlnx-zynqmp-rtc.c | 214 +++++++++++++++++++++++++++++++++++++ | ||
12 | 3 files changed, 299 insertions(+) | ||
13 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
14 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
15 | |||
16 | diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/timer/Makefile.objs | ||
19 | +++ b/hw/timer/Makefile.objs | ||
20 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx_epit.o | ||
21 | common-obj-$(CONFIG_IMX) += imx_gpt.o | ||
22 | common-obj-$(CONFIG_LM32) += lm32_timer.o | ||
23 | common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o | ||
24 | +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o | ||
25 | |||
26 | obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o | ||
27 | obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o | ||
28 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Xilinx Inc. | ||
38 | + * | ||
39 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
40 | + * | ||
41 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
42 | + * of this software and associated documentation files (the "Software"), to deal | ||
43 | + * in the Software without restriction, including without limitation the rights | ||
44 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
45 | + * copies of the Software, and to permit persons to whom the Software is | ||
46 | + * furnished to do so, subject to the following conditions: | ||
47 | + * | ||
48 | + * The above copyright notice and this permission notice shall be included in | ||
49 | + * all copies or substantial portions of the Software. | ||
50 | + * | ||
51 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
52 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
53 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
54 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
55 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
56 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
57 | + * THE SOFTWARE. | ||
58 | + */ | ||
59 | + | ||
60 | +#include "hw/register.h" | ||
61 | + | ||
62 | +#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc" | ||
63 | + | ||
64 | +#define XLNX_ZYNQMP_RTC(obj) \ | ||
65 | + OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC) | ||
66 | + | ||
67 | +REG32(SET_TIME_WRITE, 0x0) | ||
68 | +REG32(SET_TIME_READ, 0x4) | ||
69 | +REG32(CALIB_WRITE, 0x8) | ||
70 | + FIELD(CALIB_WRITE, FRACTION_EN, 20, 1) | ||
71 | + FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4) | ||
72 | + FIELD(CALIB_WRITE, MAX_TICK, 0, 16) | ||
73 | +REG32(CALIB_READ, 0xc) | ||
74 | + FIELD(CALIB_READ, FRACTION_EN, 20, 1) | ||
75 | + FIELD(CALIB_READ, FRACTION_DATA, 16, 4) | ||
76 | + FIELD(CALIB_READ, MAX_TICK, 0, 16) | ||
77 | +REG32(CURRENT_TIME, 0x10) | ||
78 | +REG32(CURRENT_TICK, 0x14) | ||
79 | + FIELD(CURRENT_TICK, VALUE, 0, 16) | ||
80 | +REG32(ALARM, 0x18) | ||
81 | +REG32(RTC_INT_STATUS, 0x20) | ||
82 | + FIELD(RTC_INT_STATUS, ALARM, 1, 1) | ||
83 | + FIELD(RTC_INT_STATUS, SECONDS, 0, 1) | ||
84 | +REG32(RTC_INT_MASK, 0x24) | ||
85 | + FIELD(RTC_INT_MASK, ALARM, 1, 1) | ||
86 | + FIELD(RTC_INT_MASK, SECONDS, 0, 1) | ||
87 | +REG32(RTC_INT_EN, 0x28) | ||
88 | + FIELD(RTC_INT_EN, ALARM, 1, 1) | ||
89 | + FIELD(RTC_INT_EN, SECONDS, 0, 1) | ||
90 | +REG32(RTC_INT_DIS, 0x2c) | ||
91 | + FIELD(RTC_INT_DIS, ALARM, 1, 1) | ||
92 | + FIELD(RTC_INT_DIS, SECONDS, 0, 1) | ||
93 | +REG32(ADDR_ERROR, 0x30) | ||
94 | + FIELD(ADDR_ERROR, STATUS, 0, 1) | ||
95 | +REG32(ADDR_ERROR_INT_MASK, 0x34) | ||
96 | + FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1) | ||
97 | +REG32(ADDR_ERROR_INT_EN, 0x38) | ||
98 | + FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1) | ||
99 | +REG32(ADDR_ERROR_INT_DIS, 0x3c) | ||
100 | + FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1) | ||
101 | +REG32(CONTROL, 0x40) | ||
102 | + FIELD(CONTROL, BATTERY_DISABLE, 31, 1) | ||
103 | + FIELD(CONTROL, OSC_CNTRL, 24, 4) | ||
104 | + FIELD(CONTROL, SLVERR_ENABLE, 0, 1) | ||
105 | +REG32(SAFETY_CHK, 0x50) | ||
106 | + | ||
107 | +#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1) | ||
108 | + | ||
109 | +typedef struct XlnxZynqMPRTC { | ||
110 | + SysBusDevice parent_obj; | ||
111 | + MemoryRegion iomem; | ||
112 | + qemu_irq irq_rtc_int; | ||
113 | + qemu_irq irq_addr_error_int; | ||
114 | + | ||
115 | + uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
116 | + RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
117 | +} XlnxZynqMPRTC; | ||
118 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
119 | new file mode 100644 | ||
120 | index XXXXXXX..XXXXXXX | ||
121 | --- /dev/null | ||
122 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | ||
123 | @@ -XXX,XX +XXX,XX @@ | ||
124 | +/* | ||
125 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
126 | + * | ||
127 | + * Copyright (c) 2017 Xilinx Inc. | ||
128 | + * | ||
129 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
130 | + * | ||
131 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
132 | + * of this software and associated documentation files (the "Software"), to deal | ||
133 | + * in the Software without restriction, including without limitation the rights | ||
134 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
135 | + * copies of the Software, and to permit persons to whom the Software is | ||
136 | + * furnished to do so, subject to the following conditions: | ||
137 | + * | ||
138 | + * The above copyright notice and this permission notice shall be included in | ||
139 | + * all copies or substantial portions of the Software. | ||
140 | + * | ||
141 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
142 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
143 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
144 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
145 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
146 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
147 | + * THE SOFTWARE. | ||
148 | + */ | ||
149 | + | ||
150 | +#include "qemu/osdep.h" | ||
151 | +#include "hw/sysbus.h" | ||
152 | +#include "hw/register.h" | ||
153 | +#include "qemu/bitops.h" | ||
154 | +#include "qemu/log.h" | ||
155 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
156 | + | ||
157 | +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
158 | +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0 | ||
159 | +#endif | ||
160 | + | ||
161 | +static void rtc_int_update_irq(XlnxZynqMPRTC *s) | ||
162 | +{ | ||
163 | + bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; | ||
164 | + qemu_set_irq(s->irq_rtc_int, pending); | ||
165 | +} | ||
166 | + | ||
167 | +static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
168 | +{ | ||
169 | + bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; | ||
170 | + qemu_set_irq(s->irq_addr_error_int, pending); | ||
171 | +} | ||
172 | + | ||
173 | +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
174 | +{ | ||
175 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
176 | + rtc_int_update_irq(s); | ||
177 | +} | ||
178 | + | ||
179 | +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
180 | +{ | ||
181 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
182 | + | ||
183 | + s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64; | ||
184 | + rtc_int_update_irq(s); | ||
185 | + return 0; | ||
186 | +} | ||
187 | + | ||
188 | +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
189 | +{ | ||
190 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
191 | + | ||
192 | + s->regs[R_RTC_INT_MASK] |= (uint32_t) val64; | ||
193 | + rtc_int_update_irq(s); | ||
194 | + return 0; | ||
195 | +} | ||
196 | + | ||
197 | +static void addr_error_postw(RegisterInfo *reg, uint64_t val64) | ||
198 | +{ | ||
199 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
200 | + addr_error_int_update_irq(s); | ||
201 | +} | ||
202 | + | ||
203 | +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
204 | +{ | ||
205 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
206 | + | ||
207 | + s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64; | ||
208 | + addr_error_int_update_irq(s); | ||
209 | + return 0; | ||
210 | +} | ||
211 | + | ||
212 | +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
213 | +{ | ||
214 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
215 | + | ||
216 | + s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64; | ||
217 | + addr_error_int_update_irq(s); | ||
218 | + return 0; | ||
219 | +} | ||
220 | + | ||
221 | +static const RegisterAccessInfo rtc_regs_info[] = { | ||
222 | + { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
223 | + },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
224 | + .ro = 0xffffffff, | ||
225 | + },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
226 | + },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
227 | + .ro = 0x1fffff, | ||
228 | + },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
229 | + .ro = 0xffffffff, | ||
230 | + },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
231 | + .ro = 0xffff, | ||
232 | + },{ .name = "ALARM", .addr = A_ALARM, | ||
233 | + },{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS, | ||
234 | + .w1c = 0x3, | ||
235 | + .post_write = rtc_int_status_postw, | ||
236 | + },{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK, | ||
237 | + .reset = 0x3, | ||
238 | + .ro = 0x3, | ||
239 | + },{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN, | ||
240 | + .pre_write = rtc_int_en_prew, | ||
241 | + },{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS, | ||
242 | + .pre_write = rtc_int_dis_prew, | ||
243 | + },{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR, | ||
244 | + .w1c = 0x1, | ||
245 | + .post_write = addr_error_postw, | ||
246 | + },{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK, | ||
247 | + .reset = 0x1, | ||
248 | + .ro = 0x1, | ||
249 | + },{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN, | ||
250 | + .pre_write = addr_error_int_en_prew, | ||
251 | + },{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS, | ||
252 | + .pre_write = addr_error_int_dis_prew, | ||
253 | + },{ .name = "CONTROL", .addr = A_CONTROL, | ||
254 | + .reset = 0x1000000, | ||
255 | + .rsvd = 0x70fffffe, | ||
256 | + },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK, | ||
257 | + } | ||
258 | +}; | ||
259 | + | ||
260 | +static void rtc_reset(DeviceState *dev) | ||
261 | +{ | ||
262 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev); | ||
263 | + unsigned int i; | ||
264 | + | ||
265 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
266 | + register_reset(&s->regs_info[i]); | ||
267 | + } | ||
268 | + | ||
269 | + rtc_int_update_irq(s); | ||
270 | + addr_error_int_update_irq(s); | ||
271 | +} | ||
272 | + | ||
273 | +static const MemoryRegionOps rtc_ops = { | ||
274 | + .read = register_read_memory, | ||
275 | + .write = register_write_memory, | ||
276 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
277 | + .valid = { | ||
278 | + .min_access_size = 4, | ||
279 | + .max_access_size = 4, | ||
280 | + }, | ||
281 | +}; | ||
282 | + | ||
283 | +static void rtc_init(Object *obj) | ||
284 | +{ | ||
285 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
286 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
287 | + RegisterInfoArray *reg_array; | ||
288 | + | ||
289 | + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
290 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
291 | + reg_array = | ||
292 | + register_init_block32(DEVICE(obj), rtc_regs_info, | ||
293 | + ARRAY_SIZE(rtc_regs_info), | ||
294 | + s->regs_info, s->regs, | ||
295 | + &rtc_ops, | ||
296 | + XLNX_ZYNQMP_RTC_ERR_DEBUG, | ||
297 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
298 | + memory_region_add_subregion(&s->iomem, | ||
299 | + 0x0, | ||
300 | + ®_array->mem); | ||
301 | + sysbus_init_mmio(sbd, &s->iomem); | ||
302 | + sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
303 | + sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
304 | +} | ||
305 | + | ||
306 | +static const VMStateDescription vmstate_rtc = { | ||
307 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
308 | + .version_id = 1, | ||
309 | + .minimum_version_id = 1, | ||
310 | + .fields = (VMStateField[]) { | ||
311 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
312 | + VMSTATE_END_OF_LIST(), | ||
313 | + } | ||
314 | +}; | ||
315 | + | ||
316 | +static void rtc_class_init(ObjectClass *klass, void *data) | ||
317 | +{ | ||
318 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
319 | + | ||
320 | + dc->reset = rtc_reset; | ||
321 | + dc->vmsd = &vmstate_rtc; | ||
322 | +} | ||
323 | + | ||
324 | +static const TypeInfo rtc_info = { | ||
325 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
326 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
327 | + .instance_size = sizeof(XlnxZynqMPRTC), | ||
328 | + .class_init = rtc_class_init, | ||
329 | + .instance_init = rtc_init, | ||
330 | +}; | ||
331 | + | ||
332 | +static void rtc_register_types(void) | ||
333 | +{ | ||
334 | + type_register_static(&rtc_info); | ||
335 | +} | ||
336 | + | ||
337 | +type_init(rtc_register_types) | ||
338 | -- | ||
339 | 2.16.2 | ||
340 | |||
341 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Coverity points out that we aren't checking the return value |
---|---|---|---|
2 | from curl_easy_setopt(). | ||
2 | 3 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Fixes: Coverity CID 1458895 |
4 | Message-id: 20180228193125.20577-13-richard.henderson@linaro.org | 5 | Inspired-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu> | ||
8 | Tested-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu> | ||
9 | Message-id: 20210910170656.366592-2-philmd@redhat.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | [PMM: renamed e1/e2/e3/e4 to use the same naming as the version | ||
7 | of the pseudocode in the Arm ARM] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | 11 | --- |
10 | target/arm/helper.h | 11 ++++ | 12 | contrib/elf2dmp/download.c | 22 ++++++++++------------ |
11 | target/arm/translate-a64.c | 94 +++++++++++++++++++++++++--- | 13 | 1 file changed, 10 insertions(+), 12 deletions(-) |
12 | target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 246 insertions(+), 8 deletions(-) | ||
14 | 14 | ||
15 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 15 | diff --git a/contrib/elf2dmp/download.c b/contrib/elf2dmp/download.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.h | 17 | --- a/contrib/elf2dmp/download.c |
18 | +++ b/target/arm/helper.h | 18 | +++ b/contrib/elf2dmp/download.c |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | 19 | @@ -XXX,XX +XXX,XX @@ int download_url(const char *name, const char *url) |
20 | DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | 20 | goto out_curl; |
21 | void, ptr, ptr, ptr, ptr, i32) | ||
22 | |||
23 | +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, | ||
28 | + void, ptr, ptr, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, | ||
30 | + void, ptr, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, | ||
32 | + void, ptr, ptr, ptr, ptr, i32) | ||
33 | + | ||
34 | #ifdef TARGET_AARCH64 | ||
35 | #include "helper-a64.h" | ||
36 | #endif | ||
37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/translate-a64.c | ||
40 | +++ b/target/arm/translate-a64.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
42 | } | ||
43 | feature = ARM_FEATURE_V8_RDM; | ||
44 | break; | ||
45 | + case 0x8: /* FCMLA, #0 */ | ||
46 | + case 0x9: /* FCMLA, #90 */ | ||
47 | + case 0xa: /* FCMLA, #180 */ | ||
48 | + case 0xb: /* FCMLA, #270 */ | ||
49 | case 0xc: /* FCADD, #90 */ | ||
50 | case 0xe: /* FCADD, #270 */ | ||
51 | if (size == 0 | ||
52 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
53 | } | ||
54 | return; | ||
55 | |||
56 | + case 0x8: /* FCMLA, #0 */ | ||
57 | + case 0x9: /* FCMLA, #90 */ | ||
58 | + case 0xa: /* FCMLA, #180 */ | ||
59 | + case 0xb: /* FCMLA, #270 */ | ||
60 | + rot = extract32(opcode, 0, 2); | ||
61 | + switch (size) { | ||
62 | + case 1: | ||
63 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | ||
64 | + gen_helper_gvec_fcmlah); | ||
65 | + break; | ||
66 | + case 2: | ||
67 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
68 | + gen_helper_gvec_fcmlas); | ||
69 | + break; | ||
70 | + case 3: | ||
71 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
72 | + gen_helper_gvec_fcmlad); | ||
73 | + break; | ||
74 | + default: | ||
75 | + g_assert_not_reached(); | ||
76 | + } | ||
77 | + return; | ||
78 | + | ||
79 | case 0xc: /* FCADD, #90 */ | ||
80 | case 0xe: /* FCADD, #270 */ | ||
81 | rot = extract32(opcode, 1, 1); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
83 | int rn = extract32(insn, 5, 5); | ||
84 | int rd = extract32(insn, 0, 5); | ||
85 | bool is_long = false; | ||
86 | - bool is_fp = false; | ||
87 | + int is_fp = 0; | ||
88 | bool is_fp16 = false; | ||
89 | int index; | ||
90 | TCGv_ptr fpst; | ||
91 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
92 | case 0x05: /* FMLS */ | ||
93 | case 0x09: /* FMUL */ | ||
94 | case 0x19: /* FMULX */ | ||
95 | - is_fp = true; | ||
96 | + is_fp = 1; | ||
97 | break; | ||
98 | case 0x1d: /* SQRDMLAH */ | ||
99 | case 0x1f: /* SQRDMLSH */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
101 | return; | ||
102 | } | ||
103 | break; | ||
104 | + case 0x11: /* FCMLA #0 */ | ||
105 | + case 0x13: /* FCMLA #90 */ | ||
106 | + case 0x15: /* FCMLA #180 */ | ||
107 | + case 0x17: /* FCMLA #270 */ | ||
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { | ||
109 | + unallocated_encoding(s); | ||
110 | + return; | ||
111 | + } | ||
112 | + is_fp = 2; | ||
113 | + break; | ||
114 | default: | ||
115 | unallocated_encoding(s); | ||
116 | return; | ||
117 | } | 21 | } |
118 | 22 | ||
119 | - if (is_fp) { | 23 | - curl_easy_setopt(curl, CURLOPT_URL, url); |
120 | + switch (is_fp) { | 24 | - curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL); |
121 | + case 1: /* normal fp */ | 25 | - curl_easy_setopt(curl, CURLOPT_WRITEDATA, file); |
122 | /* convert insn encoded size to TCGMemOp size */ | 26 | - curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1); |
123 | switch (size) { | 27 | - curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0); |
124 | case 0: /* half-precision */ | 28 | - |
125 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | 29 | - if (curl_easy_perform(curl) != CURLE_OK) { |
126 | - unallocated_encoding(s); | 30 | - err = 1; |
127 | - return; | 31 | - fclose(file); |
128 | - } | 32 | + if (curl_easy_setopt(curl, CURLOPT_URL, url) != CURLE_OK |
129 | size = MO_16; | 33 | + || curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, NULL) != CURLE_OK |
130 | + is_fp16 = true; | 34 | + || curl_easy_setopt(curl, CURLOPT_WRITEDATA, file) != CURLE_OK |
131 | break; | 35 | + || curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1) != CURLE_OK |
132 | case MO_32: /* single precision */ | 36 | + || curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0) != CURLE_OK |
133 | case MO_64: /* double precision */ | 37 | + || curl_easy_perform(curl) != CURLE_OK) { |
134 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 38 | unlink(name); |
135 | unallocated_encoding(s); | 39 | - goto out_curl; |
136 | return; | 40 | + fclose(file); |
137 | } | 41 | + err = 1; |
138 | - } else { | 42 | + } else { |
139 | + break; | 43 | + err = fclose(file); |
140 | + | ||
141 | + case 2: /* complex fp */ | ||
142 | + /* Each indexable element is a complex pair. */ | ||
143 | + size <<= 1; | ||
144 | + switch (size) { | ||
145 | + case MO_32: | ||
146 | + if (h && !is_q) { | ||
147 | + unallocated_encoding(s); | ||
148 | + return; | ||
149 | + } | ||
150 | + is_fp16 = true; | ||
151 | + break; | ||
152 | + case MO_64: | ||
153 | + break; | ||
154 | + default: | ||
155 | + unallocated_encoding(s); | ||
156 | + return; | ||
157 | + } | ||
158 | + break; | ||
159 | + | ||
160 | + default: /* integer */ | ||
161 | switch (size) { | ||
162 | case MO_8: | ||
163 | case MO_64: | ||
164 | unallocated_encoding(s); | ||
165 | return; | ||
166 | } | ||
167 | + break; | ||
168 | + } | ||
169 | + if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
170 | + unallocated_encoding(s); | ||
171 | + return; | ||
172 | } | 44 | } |
173 | 45 | ||
174 | /* Given TCGMemOp size, adjust register and indexing. */ | 46 | - err = fclose(file); |
175 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 47 | - |
176 | fpst = NULL; | 48 | out_curl: |
177 | } | 49 | curl_easy_cleanup(curl); |
178 | 50 | ||
179 | + switch (16 * u + opcode) { | ||
180 | + case 0x11: /* FCMLA #0 */ | ||
181 | + case 0x13: /* FCMLA #90 */ | ||
182 | + case 0x15: /* FCMLA #180 */ | ||
183 | + case 0x17: /* FCMLA #270 */ | ||
184 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
185 | + vec_full_reg_offset(s, rn), | ||
186 | + vec_reg_offset(s, rm, index, size), fpst, | ||
187 | + is_q ? 16 : 8, vec_full_reg_size(s), | ||
188 | + extract32(insn, 13, 2), /* rot */ | ||
189 | + size == MO_64 | ||
190 | + ? gen_helper_gvec_fcmlas_idx | ||
191 | + : gen_helper_gvec_fcmlah_idx); | ||
192 | + tcg_temp_free_ptr(fpst); | ||
193 | + return; | ||
194 | + } | ||
195 | + | ||
196 | if (size == 3) { | ||
197 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | ||
198 | int pass; | ||
199 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/target/arm/vec_helper.c | ||
202 | +++ b/target/arm/vec_helper.c | ||
203 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
204 | } | ||
205 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
206 | } | ||
207 | + | ||
208 | +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, | ||
209 | + void *vfpst, uint32_t desc) | ||
210 | +{ | ||
211 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
212 | + float16 *d = vd; | ||
213 | + float16 *n = vn; | ||
214 | + float16 *m = vm; | ||
215 | + float_status *fpst = vfpst; | ||
216 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
217 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
218 | + uint32_t neg_real = flip ^ neg_imag; | ||
219 | + uintptr_t i; | ||
220 | + | ||
221 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
222 | + neg_real <<= 15; | ||
223 | + neg_imag <<= 15; | ||
224 | + | ||
225 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
226 | + float16 e2 = n[H2(i + flip)]; | ||
227 | + float16 e1 = m[H2(i + flip)] ^ neg_real; | ||
228 | + float16 e4 = e2; | ||
229 | + float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; | ||
230 | + | ||
231 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
232 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
233 | + } | ||
234 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
235 | +} | ||
236 | + | ||
237 | +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, | ||
238 | + void *vfpst, uint32_t desc) | ||
239 | +{ | ||
240 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
241 | + float16 *d = vd; | ||
242 | + float16 *n = vn; | ||
243 | + float16 *m = vm; | ||
244 | + float_status *fpst = vfpst; | ||
245 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
246 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
247 | + uint32_t neg_real = flip ^ neg_imag; | ||
248 | + uintptr_t i; | ||
249 | + float16 e1 = m[H2(flip)]; | ||
250 | + float16 e3 = m[H2(1 - flip)]; | ||
251 | + | ||
252 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
253 | + neg_real <<= 15; | ||
254 | + neg_imag <<= 15; | ||
255 | + e1 ^= neg_real; | ||
256 | + e3 ^= neg_imag; | ||
257 | + | ||
258 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
259 | + float16 e2 = n[H2(i + flip)]; | ||
260 | + float16 e4 = e2; | ||
261 | + | ||
262 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
263 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
264 | + } | ||
265 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
266 | +} | ||
267 | + | ||
268 | +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, | ||
269 | + void *vfpst, uint32_t desc) | ||
270 | +{ | ||
271 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
272 | + float32 *d = vd; | ||
273 | + float32 *n = vn; | ||
274 | + float32 *m = vm; | ||
275 | + float_status *fpst = vfpst; | ||
276 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
277 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
278 | + uint32_t neg_real = flip ^ neg_imag; | ||
279 | + uintptr_t i; | ||
280 | + | ||
281 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
282 | + neg_real <<= 31; | ||
283 | + neg_imag <<= 31; | ||
284 | + | ||
285 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
286 | + float32 e2 = n[H4(i + flip)]; | ||
287 | + float32 e1 = m[H4(i + flip)] ^ neg_real; | ||
288 | + float32 e4 = e2; | ||
289 | + float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; | ||
290 | + | ||
291 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
292 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
293 | + } | ||
294 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
295 | +} | ||
296 | + | ||
297 | +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, | ||
298 | + void *vfpst, uint32_t desc) | ||
299 | +{ | ||
300 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
301 | + float32 *d = vd; | ||
302 | + float32 *n = vn; | ||
303 | + float32 *m = vm; | ||
304 | + float_status *fpst = vfpst; | ||
305 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
306 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
307 | + uint32_t neg_real = flip ^ neg_imag; | ||
308 | + uintptr_t i; | ||
309 | + float32 e1 = m[H4(flip)]; | ||
310 | + float32 e3 = m[H4(1 - flip)]; | ||
311 | + | ||
312 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
313 | + neg_real <<= 31; | ||
314 | + neg_imag <<= 31; | ||
315 | + e1 ^= neg_real; | ||
316 | + e3 ^= neg_imag; | ||
317 | + | ||
318 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
319 | + float32 e2 = n[H4(i + flip)]; | ||
320 | + float32 e4 = e2; | ||
321 | + | ||
322 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
323 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
324 | + } | ||
325 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
326 | +} | ||
327 | + | ||
328 | +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, | ||
329 | + void *vfpst, uint32_t desc) | ||
330 | +{ | ||
331 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
332 | + float64 *d = vd; | ||
333 | + float64 *n = vn; | ||
334 | + float64 *m = vm; | ||
335 | + float_status *fpst = vfpst; | ||
336 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
337 | + uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
338 | + uint64_t neg_real = flip ^ neg_imag; | ||
339 | + uintptr_t i; | ||
340 | + | ||
341 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
342 | + neg_real <<= 63; | ||
343 | + neg_imag <<= 63; | ||
344 | + | ||
345 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
346 | + float64 e2 = n[i + flip]; | ||
347 | + float64 e1 = m[i + flip] ^ neg_real; | ||
348 | + float64 e4 = e2; | ||
349 | + float64 e3 = m[i + 1 - flip] ^ neg_imag; | ||
350 | + | ||
351 | + d[i] = float64_muladd(e2, e1, d[i], 0, fpst); | ||
352 | + d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); | ||
353 | + } | ||
354 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
355 | +} | ||
356 | -- | 51 | -- |
357 | 2.16.2 | 52 | 2.20.1 |
358 | 53 | ||
359 | 54 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Coverity points out that if the PDB file we're trying to read |
---|---|---|---|
2 | has a header specifying a block_size of zero then we will | ||
3 | end up trying to divide by zero in pdb_ds_read_file(). | ||
4 | Check for this and fail cleanly instead. | ||
2 | 5 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Fixes: Coverity CID 1458869 |
4 | Message-id: 20180228193125.20577-15-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu> | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Tested-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu> | ||
11 | Message-id: 20210910170656.366592-3-philmd@redhat.com | ||
12 | Message-Id: <20210901143910.17112-3-peter.maydell@linaro.org> | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | --- | 14 | --- |
8 | target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 15 | contrib/elf2dmp/pdb.c | 4 ++++ |
9 | 1 file changed, 61 insertions(+) | 16 | 1 file changed, 4 insertions(+) |
10 | 17 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 18 | diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 20 | --- a/contrib/elf2dmp/pdb.c |
14 | +++ b/target/arm/translate.c | 21 | +++ b/contrib/elf2dmp/pdb.c |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 22 | @@ -XXX,XX +XXX,XX @@ out_symbols: |
16 | return 0; | 23 | |
17 | } | 24 | static int pdb_reader_ds_init(struct pdb_reader *r, PDB_DS_HEADER *hdr) |
18 | 25 | { | |
19 | +/* Advanced SIMD two registers and a scalar extension. | 26 | + if (hdr->block_size == 0) { |
20 | + * 31 24 23 22 20 16 12 11 10 9 8 3 0 | ||
21 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
22 | + * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
23 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
24 | + * | ||
25 | + */ | ||
26 | + | ||
27 | +static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | ||
28 | +{ | ||
29 | + int rd, rn, rm, rot, size, opr_sz; | ||
30 | + TCGv_ptr fpst; | ||
31 | + bool q; | ||
32 | + | ||
33 | + q = extract32(insn, 6, 1); | ||
34 | + VFP_DREG_D(rd, insn); | ||
35 | + VFP_DREG_N(rn, insn); | ||
36 | + VFP_DREG_M(rm, insn); | ||
37 | + if ((rd | rn) & q) { | ||
38 | + return 1; | 27 | + return 1; |
39 | + } | 28 | + } |
40 | + | 29 | + |
41 | + if ((insn & 0xff000f10) == 0xfe000800) { | 30 | memset(r->file_used, 0, sizeof(r->file_used)); |
42 | + /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ | 31 | r->ds.header = hdr; |
43 | + rot = extract32(insn, 20, 2); | 32 | r->ds.toc = pdb_ds_read(hdr, (uint32_t *)((uint8_t *)hdr + |
44 | + size = extract32(insn, 23, 1); | ||
45 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
46 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
47 | + return 1; | ||
48 | + } | ||
49 | + } else { | ||
50 | + return 1; | ||
51 | + } | ||
52 | + | ||
53 | + if (s->fp_excp_el) { | ||
54 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
55 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
56 | + return 0; | ||
57 | + } | ||
58 | + if (!s->vfp_enabled) { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + opr_sz = (1 + q) * 8; | ||
63 | + fpst = get_fpstatus_ptr(1); | ||
64 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
65 | + vfp_reg_offset(1, rn), | ||
66 | + vfp_reg_offset(1, rm), fpst, | ||
67 | + opr_sz, opr_sz, rot, | ||
68 | + size ? gen_helper_gvec_fcmlas_idx | ||
69 | + : gen_helper_gvec_fcmlah_idx); | ||
70 | + tcg_temp_free_ptr(fpst); | ||
71 | + return 0; | ||
72 | +} | ||
73 | + | ||
74 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | ||
75 | { | ||
76 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
77 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
78 | goto illegal_op; | ||
79 | } | ||
80 | return; | ||
81 | + } else if ((insn & 0x0f000a00) == 0x0e000800 | ||
82 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
83 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
84 | + goto illegal_op; | ||
85 | + } | ||
86 | + return; | ||
87 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
88 | /* Coprocessor double register transfer. */ | ||
89 | ARCH(5TE); | ||
90 | -- | 33 | -- |
91 | 2.16.2 | 34 | 2.20.1 |
92 | 35 | ||
93 | 36 | diff view generated by jsdifflib |
1 | The Cortex-M33 allows the system to specify the reset value of the | 1 | Currently all of the M-profile specific code in arm_cpu_reset() is |
---|---|---|---|
2 | secure Vector Table Offset Register (VTOR) by asserting config | 2 | inside a !defined(CONFIG_USER_ONLY) ifdef block. This is |
3 | signals. In particular, guest images for the MPS2 AN505 board rely | 3 | unintentional: it happened because originally the only |
4 | on the MPS2's initial VTOR being correct for that board. | 4 | M-profile-specific handling was the setup of the initial SP and PC |
5 | Implement a QEMU property so board and SoC code can set the reset | 5 | from the vector table, which is system-emulation only. But then we |
6 | value to the correct value. | 6 | added a lot of other M-profile setup to the same "if (ARM_FEATURE_M)" |
7 | code block without noticing that it was all inside a not-user-mode | ||
8 | ifdef. This has generally been harmless, but with the addition of | ||
9 | v8.1M low-overhead-loop support we ran into a problem: the reset of | ||
10 | FPSCR.LTPSIZE to 4 was only being done for system emulation mode, so | ||
11 | if a user-mode guest tried to execute the LE instruction it would | ||
12 | incorrectly take a UsageFault. | ||
7 | 13 | ||
14 | Adjust the ifdefs so only the really system-emulation specific parts | ||
15 | are covered. Because this means we now run some reset code that sets | ||
16 | up initial values in the FPCCR and similar FPU related registers, | ||
17 | explicitly set up the registers controlling FPU context handling in | ||
18 | user-emulation mode so that the FPU works by design and not by | ||
19 | chance. | ||
20 | |||
21 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/613 | ||
22 | Cc: qemu-stable@nongnu.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-7-peter.maydell@linaro.org | 25 | Message-id: 20210914120725.24992-2-peter.maydell@linaro.org |
11 | --- | 26 | --- |
12 | target/arm/cpu.h | 3 +++ | 27 | target/arm/cpu.c | 19 +++++++++++++++++++ |
13 | target/arm/cpu.c | 18 ++++++++++++++---- | 28 | 1 file changed, 19 insertions(+) |
14 | 2 files changed, 17 insertions(+), 4 deletions(-) | ||
15 | 29 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu.h | ||
19 | +++ b/target/arm/cpu.h | ||
20 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
21 | */ | ||
22 | uint32_t psci_conduit; | ||
23 | |||
24 | + /* For v8M, initial value of the Secure VTOR */ | ||
25 | + uint32_t init_svtor; | ||
26 | + | ||
27 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or | ||
28 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | ||
29 | */ | ||
30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
31 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/cpu.c | 32 | --- a/target/arm/cpu.c |
33 | +++ b/target/arm/cpu.c | 33 | +++ b/target/arm/cpu.c |
34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
35 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | ||
36 | } | ||
37 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | ||
38 | +#endif | ||
39 | |||
40 | if (arm_feature(env, ARM_FEATURE_M)) { | ||
41 | +#ifndef CONFIG_USER_ONLY | ||
35 | uint32_t initial_msp; /* Loaded from 0x0 */ | 42 | uint32_t initial_msp; /* Loaded from 0x0 */ |
36 | uint32_t initial_pc; /* Loaded from 0x4 */ | 43 | uint32_t initial_pc; /* Loaded from 0x4 */ |
37 | uint8_t *rom; | 44 | uint8_t *rom; |
38 | + uint32_t vecbase; | 45 | uint32_t vecbase; |
39 | 46 | +#endif | |
40 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 47 | |
41 | env->v7m.secure = true; | 48 | if (cpu_isar_feature(aa32_lob, cpu)) { |
42 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 49 | /* |
50 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | ||
51 | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | | ||
52 | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; | ||
53 | } | ||
54 | + | ||
55 | +#ifndef CONFIG_USER_ONLY | ||
43 | /* Unlike A/R profile, M profile defines the reset LR value */ | 56 | /* Unlike A/R profile, M profile defines the reset LR value */ |
44 | env->regs[14] = 0xffffffff; | 57 | env->regs[14] = 0xffffffff; |
45 | 58 | ||
46 | - /* Load the initial SP and PC from the vector table at address 0 */ | 59 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
47 | - rom = rom_ptr(0); | ||
48 | + env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; | ||
49 | + | ||
50 | + /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | ||
51 | + vecbase = env->v7m.vecbase[env->v7m.secure]; | ||
52 | + rom = rom_ptr(vecbase); | ||
53 | if (rom) { | ||
54 | /* Address zero is covered by ROM which hasn't yet been | ||
55 | * copied into physical memory. | ||
56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
57 | * it got copied into memory. In the latter case, rom_ptr | ||
58 | * will return a NULL pointer and we should use ldl_phys instead. | ||
59 | */ | ||
60 | - initial_msp = ldl_phys(s->as, 0); | ||
61 | - initial_pc = ldl_phys(s->as, 4); | ||
62 | + initial_msp = ldl_phys(s->as, vecbase); | ||
63 | + initial_pc = ldl_phys(s->as, vecbase + 4); | ||
64 | } | ||
65 | |||
66 | env->regs[13] = initial_msp & 0xFFFFFFFC; | 60 | env->regs[13] = initial_msp & 0xFFFFFFFC; |
67 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property = | 61 | env->regs[15] = initial_pc & ~1; |
68 | pmsav7_dregion, | 62 | env->thumb = initial_pc & 1; |
69 | qdev_prop_uint32, uint32_t); | 63 | +#else |
70 | 64 | + /* | |
71 | +/* M profile: initial value of the Secure VTOR */ | 65 | + * For user mode we run non-secure and with access to the FPU. |
72 | +static Property arm_cpu_initsvtor_property = | 66 | + * The FPU context is active (ie does not need further setup) |
73 | + DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | 67 | + * and is owned by non-secure. |
74 | + | 68 | + */ |
75 | static void arm_cpu_post_init(Object *obj) | 69 | + env->v7m.secure = false; |
76 | { | 70 | + env->v7m.nsacr = 0xcff; |
77 | ARMCPU *cpu = ARM_CPU(obj); | 71 | + env->v7m.cpacr[M_REG_NS] = 0xf0ffff; |
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | 72 | + env->v7m.fpccr[M_REG_S] &= |
79 | qdev_prop_allow_set_link_before_realize, | 73 | + ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); |
80 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | 74 | + env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; |
81 | &error_abort); | 75 | +#endif |
82 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, | ||
83 | + &error_abort); | ||
84 | } | 76 | } |
85 | 77 | ||
86 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | 78 | +#ifndef CONFIG_USER_ONLY |
79 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently | ||
80 | * executing as AArch32 then check if highvecs are enabled and | ||
81 | * adjust the PC accordingly. | ||
87 | -- | 82 | -- |
88 | 2.16.2 | 83 | 2.20.1 |
89 | 84 | ||
90 | 85 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | There's no particular reason why the exclusive monitor should |
---|---|---|---|
2 | be only cleared on reset in system emulation mode. It doesn't | ||
3 | hurt if it isn't cleared in user mode, but we might as well | ||
4 | reduce the amount of code we have that's inside an ifdef. | ||
2 | 5 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-17-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210914120725.24992-3-peter.maydell@linaro.org | ||
9 | --- | 9 | --- |
10 | target/arm/cpu.c | 1 + | 10 | target/arm/cpu.c | 6 +++--- |
11 | target/arm/cpu64.c | 1 + | 11 | 1 file changed, 3 insertions(+), 3 deletions(-) |
12 | 2 files changed, 2 insertions(+) | ||
13 | 12 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 15 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 16 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 17 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 18 | env->regs[15] = 0xFFFF0000; |
20 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 19 | } |
21 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 20 | |
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 21 | + env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
23 | cpu->midr = 0xffffffff; | 22 | +#endif |
24 | } | 23 | + |
25 | #endif | 24 | /* M profile requires that reset clears the exclusive monitor; |
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 25 | * A profile does not, but clearing it makes more sense than having it |
27 | index XXXXXXX..XXXXXXX 100644 | 26 | * set with an exclusive access on address zero. |
28 | --- a/target/arm/cpu64.c | 27 | */ |
29 | +++ b/target/arm/cpu64.c | 28 | arm_clear_exclusive(env); |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 29 | |
31 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 30 | - env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 31 | -#endif |
33 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 32 | - |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 33 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
35 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 34 | if (cpu->pmsav7_dregion > 0) { |
36 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 35 | if (arm_feature(env, ARM_FEATURE_V8)) { |
37 | } | ||
38 | -- | 36 | -- |
39 | 2.16.2 | 37 | 2.20.1 |
40 | 38 | ||
41 | 39 | diff view generated by jsdifflib |
1 | Add a Cortex-M33 definition. The M33 is an M profile CPU | 1 | Move an ifndef CONFIG_USER_ONLY code block up in arm_cpu_reset() so |
---|---|---|---|
2 | which implements the ARM v8M architecture, including the | 2 | it can be merged with another earlier one. |
3 | M profile Security Extension. | ||
4 | 3 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-9-peter.maydell@linaro.org | 6 | Message-id: 20210914120725.24992-4-peter.maydell@linaro.org |
8 | --- | 7 | --- |
9 | target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++ | 8 | target/arm/cpu.c | 22 ++++++++++------------ |
10 | 1 file changed, 31 insertions(+) | 9 | 1 file changed, 10 insertions(+), 12 deletions(-) |
11 | 10 | ||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 11 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/cpu.c | 13 | --- a/target/arm/cpu.c |
15 | +++ b/target/arm/cpu.c | 14 | +++ b/target/arm/cpu.c |
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | 15 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
17 | cpu->id_isar5 = 0x00000000; | 16 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
18 | } | 17 | } |
19 | 18 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
20 | +static void cortex_m33_initfn(Object *obj) | ||
21 | +{ | ||
22 | + ARMCPU *cpu = ARM_CPU(obj); | ||
23 | + | 19 | + |
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 20 | + /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
25 | + set_feature(&cpu->env, ARM_FEATURE_M); | 21 | + * executing as AArch32 then check if highvecs are enabled and |
26 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | 22 | + * adjust the PC accordingly. |
27 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 23 | + */ |
28 | + cpu->midr = 0x410fd213; /* r0p3 */ | 24 | + if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
29 | + cpu->pmsav7_dregion = 16; | 25 | + env->regs[15] = 0xFFFF0000; |
30 | + cpu->sau_sregion = 8; | 26 | + } |
31 | + cpu->id_pfr0 = 0x00000030; | ||
32 | + cpu->id_pfr1 = 0x00000210; | ||
33 | + cpu->id_dfr0 = 0x00200000; | ||
34 | + cpu->id_afr0 = 0x00000000; | ||
35 | + cpu->id_mmfr0 = 0x00101F40; | ||
36 | + cpu->id_mmfr1 = 0x00000000; | ||
37 | + cpu->id_mmfr2 = 0x01000000; | ||
38 | + cpu->id_mmfr3 = 0x00000000; | ||
39 | + cpu->id_isar0 = 0x01101110; | ||
40 | + cpu->id_isar1 = 0x02212000; | ||
41 | + cpu->id_isar2 = 0x20232232; | ||
42 | + cpu->id_isar3 = 0x01111131; | ||
43 | + cpu->id_isar4 = 0x01310132; | ||
44 | + cpu->id_isar5 = 0x00000000; | ||
45 | + cpu->clidr = 0x00000000; | ||
46 | + cpu->ctr = 0x8000c000; | ||
47 | +} | ||
48 | + | 27 | + |
49 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | 28 | + env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
50 | { | 29 | #endif |
51 | CPUClass *cc = CPU_CLASS(oc); | 30 | |
52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | 31 | if (arm_feature(env, ARM_FEATURE_M)) { |
53 | .class_init = arm_v7m_class_init }, | 32 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
54 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, | 33 | #endif |
55 | .class_init = arm_v7m_class_init }, | 34 | } |
56 | + { .name = "cortex-m33", .initfn = cortex_m33_initfn, | 35 | |
57 | + .class_init = arm_v7m_class_init }, | 36 | -#ifndef CONFIG_USER_ONLY |
58 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | 37 | - /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
59 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, | 38 | - * executing as AArch32 then check if highvecs are enabled and |
60 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | 39 | - * adjust the PC accordingly. |
40 | - */ | ||
41 | - if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | ||
42 | - env->regs[15] = 0xFFFF0000; | ||
43 | - } | ||
44 | - | ||
45 | - env->vfp.xregs[ARM_VFP_FPEXC] = 0; | ||
46 | -#endif | ||
47 | - | ||
48 | /* M profile requires that reset clears the exclusive monitor; | ||
49 | * A profile does not, but clearing it makes more sense than having it | ||
50 | * set with an exclusive access on address zero. | ||
61 | -- | 51 | -- |
62 | 2.16.2 | 52 | 2.20.1 |
63 | 53 | ||
64 | 54 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Shashi Mallela <shashi.mallela@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Happily, the bits are in the same places compared to a32. | 3 | During sbsa acs level 3 testing, it is seen that the GIC maintenance |
4 | interrupts are not triggered and the related test cases fail. This | ||
5 | is because we were incorrectly passing the value of the MISR register | ||
6 | (from maintenance_interrupt_state()) to qemu_set_irq() as the level | ||
7 | argument, whereas the device on the other end of this irq line | ||
8 | expects a 0/1 value. | ||
4 | 9 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Fix the logic to pass a 0/1 level indication, rather than a |
6 | Message-id: 20180228193125.20577-16-richard.henderson@linaro.org | 11 | 0/not-0 value. |
12 | |||
13 | Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()") | ||
14 | Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
16 | Message-id: 20210915205809.59068-1-shashi.mallela@linaro.org | ||
17 | [PMM: tweaked commit message; collapsed nested if()s into one] | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 20 | --- |
10 | target/arm/translate.c | 14 +++++++++++++- | 21 | hw/intc/arm_gicv3_cpuif.c | 5 +++-- |
11 | 1 file changed, 13 insertions(+), 1 deletion(-) | 22 | 1 file changed, 3 insertions(+), 2 deletions(-) |
12 | 23 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 24 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
14 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 26 | --- a/hw/intc/arm_gicv3_cpuif.c |
16 | +++ b/target/arm/translate.c | 27 | +++ b/hw/intc/arm_gicv3_cpuif.c |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 28 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) |
18 | default_exception_el(s)); | ||
19 | break; | ||
20 | } | 29 | } |
21 | - if (((insn >> 24) & 3) == 3) { | 30 | } |
22 | + if ((insn & 0xfe000a00) == 0xfc000800 | 31 | |
23 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 32 | - if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { |
24 | + /* The Thumb2 and ARM encodings are identical. */ | 33 | - maintlevel = maintenance_interrupt_state(cs); |
25 | + if (disas_neon_insn_3same_ext(s, insn)) { | 34 | + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && |
26 | + goto illegal_op; | 35 | + maintenance_interrupt_state(cs) != 0) { |
27 | + } | 36 | + maintlevel = 1; |
28 | + } else if ((insn & 0xff000a00) == 0xfe000800 | 37 | } |
29 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 38 | |
30 | + /* The Thumb2 and ARM encodings are identical. */ | 39 | trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, |
31 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
32 | + goto illegal_op; | ||
33 | + } | ||
34 | + } else if (((insn >> 24) & 3) == 3) { | ||
35 | /* Translate into the equivalent ARM encoding. */ | ||
36 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | ||
37 | if (disas_neon_data_insn(s, insn)) { | ||
38 | -- | 40 | -- |
39 | 2.16.2 | 41 | 2.20.1 |
40 | 42 | ||
41 | 43 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | We will need PMC register definitions in accel specific code later. |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Move all constant definitions to common arm headers so we can reuse |
5 | Message-id: 20180228193125.20577-12-richard.henderson@linaro.org | 5 | them. |
6 | |||
7 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20210916155404.86958-2-agraf@csgraf.de | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/helper.h | 7 ++++ | 12 | target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++ |
9 | target/arm/translate-a64.c | 48 ++++++++++++++++++++++- | 13 | target/arm/helper.c | 44 ------------------------------------------ |
10 | target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ | 14 | 2 files changed, 44 insertions(+), 44 deletions(-) |
11 | 3 files changed, 151 insertions(+), 1 deletion(-) | ||
12 | 15 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 18 | --- a/target/arm/internals.h |
16 | +++ b/target/arm/helper.h | 19 | +++ b/target/arm/internals.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 20 | @@ -XXX,XX +XXX,XX @@ enum MVEECIState { |
18 | DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 21 | /* All other values reserved */ |
19 | void, ptr, ptr, ptr, ptr, i32) | 22 | }; |
20 | 23 | ||
21 | +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, | 24 | +/* Definitions for the PMU registers */ |
22 | + void, ptr, ptr, ptr, ptr, i32) | 25 | +#define PMCRN_MASK 0xf800 |
23 | +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | 26 | +#define PMCRN_SHIFT 11 |
24 | + void, ptr, ptr, ptr, ptr, i32) | 27 | +#define PMCRLC 0x40 |
25 | +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | 28 | +#define PMCRDP 0x20 |
26 | + void, ptr, ptr, ptr, ptr, i32) | 29 | +#define PMCRX 0x10 |
30 | +#define PMCRD 0x8 | ||
31 | +#define PMCRC 0x4 | ||
32 | +#define PMCRP 0x2 | ||
33 | +#define PMCRE 0x1 | ||
34 | +/* | ||
35 | + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, | ||
36 | + * which can be written as 1 to trigger behaviour but which stay RAZ). | ||
37 | + */ | ||
38 | +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) | ||
27 | + | 39 | + |
28 | #ifdef TARGET_AARCH64 | 40 | +#define PMXEVTYPER_P 0x80000000 |
29 | #include "helper-a64.h" | 41 | +#define PMXEVTYPER_U 0x40000000 |
30 | #endif | 42 | +#define PMXEVTYPER_NSK 0x20000000 |
31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 43 | +#define PMXEVTYPER_NSU 0x10000000 |
32 | index XXXXXXX..XXXXXXX 100644 | 44 | +#define PMXEVTYPER_NSH 0x08000000 |
33 | --- a/target/arm/translate-a64.c | 45 | +#define PMXEVTYPER_M 0x04000000 |
34 | +++ b/target/arm/translate-a64.c | 46 | +#define PMXEVTYPER_MT 0x02000000 |
35 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | 47 | +#define PMXEVTYPER_EVTCOUNT 0x0000ffff |
36 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | 48 | +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ |
37 | } | 49 | + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ |
38 | 50 | + PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
39 | +/* Expand a 3-operand + fpstatus pointer + simd data value operation using | 51 | + PMXEVTYPER_EVTCOUNT) |
40 | + * an out-of-line helper. | 52 | + |
41 | + */ | 53 | +#define PMCCFILTR 0xf8000000 |
42 | +static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | 54 | +#define PMCCFILTR_M PMXEVTYPER_M |
43 | + int rm, bool is_fp16, int data, | 55 | +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) |
44 | + gen_helper_gvec_3_ptr *fn) | 56 | + |
57 | +static inline uint32_t pmu_num_counters(CPUARMState *env) | ||
45 | +{ | 58 | +{ |
46 | + TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | 59 | + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; |
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), fpst, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | ||
51 | + tcg_temp_free_ptr(fpst); | ||
52 | +} | 60 | +} |
53 | + | 61 | + |
54 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | 62 | +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ |
55 | * than the 32 bit equivalent. | 63 | +static inline uint64_t pmu_counter_mask(CPUARMState *env) |
56 | */ | ||
57 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
58 | int size = extract32(insn, 22, 2); | ||
59 | bool u = extract32(insn, 29, 1); | ||
60 | bool is_q = extract32(insn, 30, 1); | ||
61 | - int feature; | ||
62 | + int feature, rot; | ||
63 | |||
64 | switch (u * 16 + opcode) { | ||
65 | case 0x10: /* SQRDMLAH (vector) */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | } | ||
68 | feature = ARM_FEATURE_V8_RDM; | ||
69 | break; | ||
70 | + case 0xc: /* FCADD, #90 */ | ||
71 | + case 0xe: /* FCADD, #270 */ | ||
72 | + if (size == 0 | ||
73 | + || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) | ||
74 | + || (size == 3 && !is_q)) { | ||
75 | + unallocated_encoding(s); | ||
76 | + return; | ||
77 | + } | ||
78 | + feature = ARM_FEATURE_V8_FCMA; | ||
79 | + break; | ||
80 | default: | ||
81 | unallocated_encoding(s); | ||
82 | return; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
84 | } | ||
85 | return; | ||
86 | |||
87 | + case 0xc: /* FCADD, #90 */ | ||
88 | + case 0xe: /* FCADD, #270 */ | ||
89 | + rot = extract32(opcode, 1, 1); | ||
90 | + switch (size) { | ||
91 | + case 1: | ||
92 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
93 | + gen_helper_gvec_fcaddh); | ||
94 | + break; | ||
95 | + case 2: | ||
96 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
97 | + gen_helper_gvec_fcadds); | ||
98 | + break; | ||
99 | + case 3: | ||
100 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
101 | + gen_helper_gvec_fcaddd); | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | + } | ||
106 | + return; | ||
107 | + | ||
108 | default: | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/vec_helper.c | ||
114 | +++ b/target/arm/vec_helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | #include "exec/exec-all.h" | ||
117 | #include "exec/helper-proto.h" | ||
118 | #include "tcg/tcg-gvec-desc.h" | ||
119 | +#include "fpu/softfloat.h" | ||
120 | |||
121 | |||
122 | +/* Note that vector data is stored in host-endian 64-bit chunks, | ||
123 | + so addressing units smaller than that needs a host-endian fixup. */ | ||
124 | +#ifdef HOST_WORDS_BIGENDIAN | ||
125 | +#define H1(x) ((x) ^ 7) | ||
126 | +#define H2(x) ((x) ^ 3) | ||
127 | +#define H4(x) ((x) ^ 1) | ||
128 | +#else | ||
129 | +#define H1(x) (x) | ||
130 | +#define H2(x) (x) | ||
131 | +#define H4(x) (x) | ||
132 | +#endif | ||
133 | + | ||
134 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
135 | |||
136 | static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
137 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
138 | } | ||
139 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
140 | } | ||
141 | + | ||
142 | +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, | ||
143 | + void *vfpst, uint32_t desc) | ||
144 | +{ | 64 | +{ |
145 | + uintptr_t opr_sz = simd_oprsz(desc); | 65 | + return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); |
146 | + float16 *d = vd; | ||
147 | + float16 *n = vn; | ||
148 | + float16 *m = vm; | ||
149 | + float_status *fpst = vfpst; | ||
150 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
151 | + uint32_t neg_imag = neg_real ^ 1; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
155 | + neg_real <<= 15; | ||
156 | + neg_imag <<= 15; | ||
157 | + | ||
158 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
159 | + float16 e0 = n[H2(i)]; | ||
160 | + float16 e1 = m[H2(i + 1)] ^ neg_imag; | ||
161 | + float16 e2 = n[H2(i + 1)]; | ||
162 | + float16 e3 = m[H2(i)] ^ neg_real; | ||
163 | + | ||
164 | + d[H2(i)] = float16_add(e0, e1, fpst); | ||
165 | + d[H2(i + 1)] = float16_add(e2, e3, fpst); | ||
166 | + } | ||
167 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
168 | +} | 66 | +} |
169 | + | 67 | + |
170 | +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, | 68 | #endif |
171 | + void *vfpst, uint32_t desc) | 69 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
172 | +{ | 70 | index XXXXXXX..XXXXXXX 100644 |
173 | + uintptr_t opr_sz = simd_oprsz(desc); | 71 | --- a/target/arm/helper.c |
174 | + float32 *d = vd; | 72 | +++ b/target/arm/helper.c |
175 | + float32 *n = vn; | 73 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { |
176 | + float32 *m = vm; | 74 | REGINFO_SENTINEL |
177 | + float_status *fpst = vfpst; | 75 | }; |
178 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | 76 | |
179 | + uint32_t neg_imag = neg_real ^ 1; | 77 | -/* Definitions for the PMU registers */ |
180 | + uintptr_t i; | 78 | -#define PMCRN_MASK 0xf800 |
181 | + | 79 | -#define PMCRN_SHIFT 11 |
182 | + /* Shift boolean to the sign bit so we can xor to negate. */ | 80 | -#define PMCRLC 0x40 |
183 | + neg_real <<= 31; | 81 | -#define PMCRDP 0x20 |
184 | + neg_imag <<= 31; | 82 | -#define PMCRX 0x10 |
185 | + | 83 | -#define PMCRD 0x8 |
186 | + for (i = 0; i < opr_sz / 4; i += 2) { | 84 | -#define PMCRC 0x4 |
187 | + float32 e0 = n[H4(i)]; | 85 | -#define PMCRP 0x2 |
188 | + float32 e1 = m[H4(i + 1)] ^ neg_imag; | 86 | -#define PMCRE 0x1 |
189 | + float32 e2 = n[H4(i + 1)]; | 87 | -/* |
190 | + float32 e3 = m[H4(i)] ^ neg_real; | 88 | - * Mask of PMCR bits writeable by guest (not including WO bits like C, P, |
191 | + | 89 | - * which can be written as 1 to trigger behaviour but which stay RAZ). |
192 | + d[H4(i)] = float32_add(e0, e1, fpst); | 90 | - */ |
193 | + d[H4(i + 1)] = float32_add(e2, e3, fpst); | 91 | -#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) |
194 | + } | 92 | - |
195 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 93 | -#define PMXEVTYPER_P 0x80000000 |
196 | +} | 94 | -#define PMXEVTYPER_U 0x40000000 |
197 | + | 95 | -#define PMXEVTYPER_NSK 0x20000000 |
198 | +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | 96 | -#define PMXEVTYPER_NSU 0x10000000 |
199 | + void *vfpst, uint32_t desc) | 97 | -#define PMXEVTYPER_NSH 0x08000000 |
200 | +{ | 98 | -#define PMXEVTYPER_M 0x04000000 |
201 | + uintptr_t opr_sz = simd_oprsz(desc); | 99 | -#define PMXEVTYPER_MT 0x02000000 |
202 | + float64 *d = vd; | 100 | -#define PMXEVTYPER_EVTCOUNT 0x0000ffff |
203 | + float64 *n = vn; | 101 | -#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ |
204 | + float64 *m = vm; | 102 | - PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ |
205 | + float_status *fpst = vfpst; | 103 | - PMXEVTYPER_M | PMXEVTYPER_MT | \ |
206 | + uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); | 104 | - PMXEVTYPER_EVTCOUNT) |
207 | + uint64_t neg_imag = neg_real ^ 1; | 105 | - |
208 | + uintptr_t i; | 106 | -#define PMCCFILTR 0xf8000000 |
209 | + | 107 | -#define PMCCFILTR_M PMXEVTYPER_M |
210 | + /* Shift boolean to the sign bit so we can xor to negate. */ | 108 | -#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) |
211 | + neg_real <<= 63; | 109 | - |
212 | + neg_imag <<= 63; | 110 | -static inline uint32_t pmu_num_counters(CPUARMState *env) |
213 | + | 111 | -{ |
214 | + for (i = 0; i < opr_sz / 8; i += 2) { | 112 | - return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; |
215 | + float64 e0 = n[i]; | 113 | -} |
216 | + float64 e1 = m[i + 1] ^ neg_imag; | 114 | - |
217 | + float64 e2 = n[i + 1]; | 115 | -/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ |
218 | + float64 e3 = m[i] ^ neg_real; | 116 | -static inline uint64_t pmu_counter_mask(CPUARMState *env) |
219 | + | 117 | -{ |
220 | + d[i] = float64_add(e0, e1, fpst); | 118 | - return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); |
221 | + d[i + 1] = float64_add(e2, e3, fpst); | 119 | -} |
222 | + } | 120 | - |
223 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 121 | typedef struct pm_event { |
224 | +} | 122 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ |
123 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | ||
225 | -- | 124 | -- |
226 | 2.16.2 | 125 | 2.20.1 |
227 | 126 | ||
228 | 127 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Hvf's permission bitmap during and after dirty logging does not include | ||
4 | the HV_MEMORY_EXEC permission. At least on Apple Silicon, this leads to | ||
5 | instruction faults once dirty logging was enabled. | ||
6 | |||
7 | Add the bit to make it work properly. | ||
8 | |||
9 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20210916155404.86958-3-agraf@csgraf.de |
5 | Message-id: 20180228193125.20577-6-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/helper.h | 9 +++++ | 14 | accel/hvf/hvf-accel-ops.c | 4 ++-- |
9 | target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ | 15 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++ | ||
11 | 3 files changed, 166 insertions(+) | ||
12 | 16 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 17 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 19 | --- a/accel/hvf/hvf-accel-ops.c |
16 | +++ b/target/arm/helper.h | 20 | +++ b/accel/hvf/hvf-accel-ops.c |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(dc_zva, void, env, i64) | 21 | @@ -XXX,XX +XXX,XX @@ static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) |
18 | DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 22 | if (on) { |
19 | DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 23 | slot->flags |= HVF_SLOT_LOG; |
20 | 24 | hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, | |
21 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, | 25 | - HV_MEMORY_READ); |
22 | + void, ptr, ptr, ptr, ptr, i32) | 26 | + HV_MEMORY_READ | HV_MEMORY_EXEC); |
23 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, | 27 | /* stop tracking region*/ |
24 | + void, ptr, ptr, ptr, ptr, i32) | 28 | } else { |
25 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 29 | slot->flags &= ~HVF_SLOT_LOG; |
26 | + void, ptr, ptr, ptr, ptr, i32) | 30 | hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, |
27 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 31 | - HV_MEMORY_READ | HV_MEMORY_WRITE); |
28 | + void, ptr, ptr, ptr, ptr, i32) | 32 | + HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC); |
29 | + | 33 | } |
30 | #ifdef TARGET_AARCH64 | ||
31 | #include "helper-a64.h" | ||
32 | #endif | ||
33 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/translate-a64.c | ||
36 | +++ b/target/arm/translate-a64.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, | ||
38 | vec_full_reg_size(s), gvec_op); | ||
39 | } | 34 | } |
40 | 35 | ||
41 | +/* Expand a 3-operand + env pointer operation using | ||
42 | + * an out-of-line helper. | ||
43 | + */ | ||
44 | +static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
45 | + int rn, int rm, gen_helper_gvec_3_ptr *fn) | ||
46 | +{ | ||
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), cpu_env, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
51 | +} | ||
52 | + | ||
53 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | ||
54 | * than the 32 bit equivalent. | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | ||
57 | clear_vec_high(s, is_q, rd); | ||
58 | } | ||
59 | |||
60 | +/* AdvSIMD three same extra | ||
61 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
62 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
63 | + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
64 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
65 | + */ | ||
66 | +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | +{ | ||
68 | + int rd = extract32(insn, 0, 5); | ||
69 | + int rn = extract32(insn, 5, 5); | ||
70 | + int opcode = extract32(insn, 11, 4); | ||
71 | + int rm = extract32(insn, 16, 5); | ||
72 | + int size = extract32(insn, 22, 2); | ||
73 | + bool u = extract32(insn, 29, 1); | ||
74 | + bool is_q = extract32(insn, 30, 1); | ||
75 | + int feature; | ||
76 | + | ||
77 | + switch (u * 16 + opcode) { | ||
78 | + case 0x10: /* SQRDMLAH (vector) */ | ||
79 | + case 0x11: /* SQRDMLSH (vector) */ | ||
80 | + if (size != 1 && size != 2) { | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + feature = ARM_FEATURE_V8_RDM; | ||
85 | + break; | ||
86 | + default: | ||
87 | + unallocated_encoding(s); | ||
88 | + return; | ||
89 | + } | ||
90 | + if (!arm_dc_feature(s, feature)) { | ||
91 | + unallocated_encoding(s); | ||
92 | + return; | ||
93 | + } | ||
94 | + if (!fp_access_check(s)) { | ||
95 | + return; | ||
96 | + } | ||
97 | + | ||
98 | + switch (opcode) { | ||
99 | + case 0x0: /* SQRDMLAH (vector) */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); | ||
103 | + break; | ||
104 | + case 2: | ||
105 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); | ||
106 | + break; | ||
107 | + default: | ||
108 | + g_assert_not_reached(); | ||
109 | + } | ||
110 | + return; | ||
111 | + | ||
112 | + case 0x1: /* SQRDMLSH (vector) */ | ||
113 | + switch (size) { | ||
114 | + case 1: | ||
115 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); | ||
116 | + break; | ||
117 | + case 2: | ||
118 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); | ||
119 | + break; | ||
120 | + default: | ||
121 | + g_assert_not_reached(); | ||
122 | + } | ||
123 | + return; | ||
124 | + | ||
125 | + default: | ||
126 | + g_assert_not_reached(); | ||
127 | + } | ||
128 | +} | ||
129 | + | ||
130 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, | ||
131 | int size, int rn, int rd) | ||
132 | { | ||
133 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | ||
134 | static const AArch64DecodeTable data_proc_simd[] = { | ||
135 | /* pattern , mask , fn */ | ||
136 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | ||
137 | + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, | ||
138 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | ||
139 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | ||
140 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | ||
141 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/vec_helper.c | ||
144 | +++ b/target/arm/vec_helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ | ||
146 | |||
147 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
148 | |||
149 | +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
150 | +{ | ||
151 | + uint64_t *d = vd + opr_sz; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + for (i = opr_sz; i < max_sz; i += 8) { | ||
155 | + *d++ = 0; | ||
156 | + } | ||
157 | +} | ||
158 | + | ||
159 | /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
160 | static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
161 | int16_t src2, int16_t src3) | ||
162 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
163 | return deposit32(e1, 16, 16, e2); | ||
164 | } | ||
165 | |||
166 | +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, | ||
167 | + void *ve, uint32_t desc) | ||
168 | +{ | ||
169 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
170 | + int16_t *d = vd; | ||
171 | + int16_t *n = vn; | ||
172 | + int16_t *m = vm; | ||
173 | + CPUARMState *env = ve; | ||
174 | + uintptr_t i; | ||
175 | + | ||
176 | + for (i = 0; i < opr_sz / 2; ++i) { | ||
177 | + d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); | ||
178 | + } | ||
179 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
180 | +} | ||
181 | + | ||
182 | /* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | ||
183 | static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | ||
184 | int16_t src2, int16_t src3) | ||
185 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
186 | return deposit32(e1, 16, 16, e2); | ||
187 | } | ||
188 | |||
189 | +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, | ||
190 | + void *ve, uint32_t desc) | ||
191 | +{ | ||
192 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
193 | + int16_t *d = vd; | ||
194 | + int16_t *n = vn; | ||
195 | + int16_t *m = vm; | ||
196 | + CPUARMState *env = ve; | ||
197 | + uintptr_t i; | ||
198 | + | ||
199 | + for (i = 0; i < opr_sz / 2; ++i) { | ||
200 | + d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]); | ||
201 | + } | ||
202 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
203 | +} | ||
204 | + | ||
205 | /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
206 | uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
207 | int32_t src2, int32_t src3) | ||
208 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
209 | return ret; | ||
210 | } | ||
211 | |||
212 | +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, | ||
213 | + void *ve, uint32_t desc) | ||
214 | +{ | ||
215 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
216 | + int32_t *d = vd; | ||
217 | + int32_t *n = vn; | ||
218 | + int32_t *m = vm; | ||
219 | + CPUARMState *env = ve; | ||
220 | + uintptr_t i; | ||
221 | + | ||
222 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
223 | + d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); | ||
224 | + } | ||
225 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
226 | +} | ||
227 | + | ||
228 | /* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
229 | uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
230 | int32_t src2, int32_t src3) | ||
231 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
232 | } | ||
233 | return ret; | ||
234 | } | ||
235 | + | ||
236 | +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
237 | + void *ve, uint32_t desc) | ||
238 | +{ | ||
239 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
240 | + int32_t *d = vd; | ||
241 | + int32_t *n = vn; | ||
242 | + int32_t *m = vm; | ||
243 | + CPUARMState *env = ve; | ||
244 | + uintptr_t i; | ||
245 | + | ||
246 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
247 | + d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); | ||
248 | + } | ||
249 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
250 | +} | ||
251 | -- | 36 | -- |
252 | 2.16.2 | 37 | 2.20.1 |
253 | 38 | ||
254 | 39 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@xilinx.com> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Allow the guest to determine the time set from the QEMU command line. | 3 | We will need to install a migration helper for the ARM hvf backend. |
4 | Let's introduce an arch callback for the overall hvf init chain to | ||
5 | do so. | ||
4 | 6 | ||
5 | This includes adding a trace event to debug the new time. | 7 | Signed-off-by: Alexander Graf <agraf@csgraf.de> |
6 | |||
7 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20210916155404.86958-4-agraf@csgraf.de | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | include/hw/timer/xlnx-zynqmp-rtc.h | 2 ++ | 12 | include/sysemu/hvf_int.h | 1 + |
13 | hw/timer/xlnx-zynqmp-rtc.c | 58 ++++++++++++++++++++++++++++++++++++++ | 13 | accel/hvf/hvf-accel-ops.c | 3 ++- |
14 | hw/timer/trace-events | 3 ++ | 14 | target/i386/hvf/hvf.c | 5 +++++ |
15 | 3 files changed, 63 insertions(+) | 15 | 3 files changed, 8 insertions(+), 1 deletion(-) |
16 | 16 | ||
17 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | 17 | diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/timer/xlnx-zynqmp-rtc.h | 19 | --- a/include/sysemu/hvf_int.h |
20 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | 20 | +++ b/include/sysemu/hvf_int.h |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPRTC { | 21 | @@ -XXX,XX +XXX,XX @@ struct hvf_vcpu_state { |
22 | qemu_irq irq_rtc_int; | 22 | }; |
23 | qemu_irq irq_addr_error_int; | 23 | |
24 | 24 | void assert_hvf_ok(hv_return_t ret); | |
25 | + uint32_t tick_offset; | 25 | +int hvf_arch_init(void); |
26 | int hvf_arch_init_vcpu(CPUState *cpu); | ||
27 | void hvf_arch_vcpu_destroy(CPUState *cpu); | ||
28 | int hvf_vcpu_exec(CPUState *); | ||
29 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/accel/hvf/hvf-accel-ops.c | ||
32 | +++ b/accel/hvf/hvf-accel-ops.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static int hvf_accel_init(MachineState *ms) | ||
34 | |||
35 | hvf_state = s; | ||
36 | memory_listener_register(&hvf_memory_listener, &address_space_memory); | ||
37 | - return 0; | ||
26 | + | 38 | + |
27 | uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | 39 | + return hvf_arch_init(); |
28 | RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | 40 | } |
29 | } XlnxZynqMPRTC; | 41 | |
30 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | 42 | static void hvf_accel_class_init(ObjectClass *oc, void *data) |
43 | diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/timer/xlnx-zynqmp-rtc.c | 45 | --- a/target/i386/hvf/hvf.c |
33 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | 46 | +++ b/target/i386/hvf/hvf.c |
34 | @@ -XXX,XX +XXX,XX @@ | 47 | @@ -XXX,XX +XXX,XX @@ static inline bool apic_bus_freq_is_known(CPUX86State *env) |
35 | #include "hw/register.h" | 48 | return env->apic_bus_freq != 0; |
36 | #include "qemu/bitops.h" | ||
37 | #include "qemu/log.h" | ||
38 | +#include "hw/ptimer.h" | ||
39 | +#include "qemu/cutils.h" | ||
40 | +#include "sysemu/sysemu.h" | ||
41 | +#include "trace.h" | ||
42 | #include "hw/timer/xlnx-zynqmp-rtc.h" | ||
43 | |||
44 | #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
45 | @@ -XXX,XX +XXX,XX @@ static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
46 | qemu_set_irq(s->irq_addr_error_int, pending); | ||
47 | } | 49 | } |
48 | 50 | ||
49 | +static uint32_t rtc_get_count(XlnxZynqMPRTC *s) | 51 | +int hvf_arch_init(void) |
50 | +{ | 52 | +{ |
51 | + int64_t now = qemu_clock_get_ns(rtc_clock); | ||
52 | + return s->tick_offset + now / NANOSECONDS_PER_SECOND; | ||
53 | +} | ||
54 | + | ||
55 | +static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64) | ||
56 | +{ | ||
57 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
58 | + | ||
59 | + return rtc_get_count(s); | ||
60 | +} | ||
61 | + | ||
62 | static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
63 | { | ||
64 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
65 | @@ -XXX,XX +XXX,XX @@ static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
66 | |||
67 | static const RegisterAccessInfo rtc_regs_info[] = { | ||
68 | { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
69 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
70 | },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
71 | .ro = 0xffffffff, | ||
72 | + .post_read = current_time_postr, | ||
73 | },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
74 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
75 | },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
76 | .ro = 0x1fffff, | ||
77 | },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
78 | .ro = 0xffffffff, | ||
79 | + .post_read = current_time_postr, | ||
80 | },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
81 | .ro = 0xffff, | ||
82 | },{ .name = "ALARM", .addr = A_ALARM, | ||
83 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
84 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
85 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
86 | RegisterInfoArray *reg_array; | ||
87 | + struct tm current_tm; | ||
88 | |||
89 | memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
90 | XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
91 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
92 | sysbus_init_mmio(sbd, &s->iomem); | ||
93 | sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
94 | sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
95 | + | ||
96 | + qemu_get_timedate(¤t_tm, 0); | ||
97 | + s->tick_offset = mktimegm(¤t_tm) - | ||
98 | + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
99 | + | ||
100 | + trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon, | ||
101 | + current_tm.tm_mday, current_tm.tm_hour, | ||
102 | + current_tm.tm_min, current_tm.tm_sec); | ||
103 | +} | ||
104 | + | ||
105 | +static int rtc_pre_save(void *opaque) | ||
106 | +{ | ||
107 | + XlnxZynqMPRTC *s = opaque; | ||
108 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
109 | + | ||
110 | + /* Add the time at migration */ | ||
111 | + s->tick_offset = s->tick_offset + now; | ||
112 | + | ||
113 | + return 0; | 53 | + return 0; |
114 | +} | 54 | +} |
115 | + | 55 | + |
116 | +static int rtc_post_load(void *opaque, int version_id) | 56 | int hvf_arch_init_vcpu(CPUState *cpu) |
117 | +{ | 57 | { |
118 | + XlnxZynqMPRTC *s = opaque; | 58 | X86CPU *x86cpu = X86_CPU(cpu); |
119 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
120 | + | ||
121 | + /* Subtract the time after migration. This combined with the pre_save | ||
122 | + * action results in us having subtracted the time that the guest was | ||
123 | + * stopped to the offset. | ||
124 | + */ | ||
125 | + s->tick_offset = s->tick_offset - now; | ||
126 | + | ||
127 | + return 0; | ||
128 | } | ||
129 | |||
130 | static const VMStateDescription vmstate_rtc = { | ||
131 | .name = TYPE_XLNX_ZYNQMP_RTC, | ||
132 | .version_id = 1, | ||
133 | .minimum_version_id = 1, | ||
134 | + .pre_save = rtc_pre_save, | ||
135 | + .post_load = rtc_post_load, | ||
136 | .fields = (VMStateField[]) { | ||
137 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
138 | + VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC), | ||
139 | VMSTATE_END_OF_LIST(), | ||
140 | } | ||
141 | }; | ||
142 | diff --git a/hw/timer/trace-events b/hw/timer/trace-events | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/hw/timer/trace-events | ||
145 | +++ b/hw/timer/trace-events | ||
146 | @@ -XXX,XX +XXX,XX @@ systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr | ||
147 | cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
148 | cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
149 | cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" | ||
150 | + | ||
151 | +# hw/timer/xlnx-zynqmp-rtc.c | ||
152 | +xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" | ||
153 | -- | 59 | -- |
154 | 2.16.2 | 60 | 2.20.1 |
155 | 61 | ||
156 | 62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | ||
9 | hw/arm/xlnx-zynqmp.c | 14 ++++++++++++++ | ||
10 | 2 files changed, 16 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
15 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | #include "hw/dma/xlnx_dpdma.h" | ||
18 | #include "hw/display/xlnx_dp.h" | ||
19 | #include "hw/intc/xlnx-zynqmp-ipi.h" | ||
20 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
21 | |||
22 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | ||
23 | #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState { | ||
25 | XlnxDPState dp; | ||
26 | XlnxDPDMAState dpdma; | ||
27 | XlnxZynqMPIPI ipi; | ||
28 | + XlnxZynqMPRTC rtc; | ||
29 | |||
30 | char *boot_cpu; | ||
31 | ARMCPU *boot_cpu_ptr; | ||
32 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/xlnx-zynqmp.c | ||
35 | +++ b/hw/arm/xlnx-zynqmp.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #define IPI_ADDR 0xFF300000 | ||
38 | #define IPI_IRQ 64 | ||
39 | |||
40 | +#define RTC_ADDR 0xffa60000 | ||
41 | +#define RTC_IRQ 26 | ||
42 | + | ||
43 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | ||
44 | |||
45 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | ||
46 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | ||
47 | |||
48 | object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); | ||
49 | qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); | ||
50 | + | ||
51 | + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); | ||
52 | + qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); | ||
53 | } | ||
54 | |||
55 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
56 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
57 | } | ||
58 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | ||
59 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | ||
60 | + | ||
61 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | ||
62 | + if (err) { | ||
63 | + error_propagate(errp, err); | ||
64 | + return; | ||
65 | + } | ||
66 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | ||
67 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | ||
68 | } | ||
69 | |||
70 | static Property xlnx_zynqmp_props[] = { | ||
71 | -- | ||
72 | 2.16.2 | ||
73 | |||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Allow the translate subroutines to return false for invalid insns. | ||
4 | |||
5 | At present we can of course invoke an invalid insn exception from within | ||
6 | the translate subroutine, but in the short term this consolidates code. | ||
7 | In the long term it would allow the decodetree language to support | ||
8 | overlapping patterns for ISA extensions. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20180227232618.2908-1-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | scripts/decodetree.py | 5 ++--- | ||
16 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
17 | |||
18 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py | ||
19 | index XXXXXXX..XXXXXXX 100755 | ||
20 | --- a/scripts/decodetree.py | ||
21 | +++ b/scripts/decodetree.py | ||
22 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | ||
23 | global translate_prefix | ||
24 | output('typedef ', self.base.base.struct_name(), | ||
25 | ' arg_', self.name, ';\n') | ||
26 | - output(translate_scope, 'void ', translate_prefix, '_', self.name, | ||
27 | + output(translate_scope, 'bool ', translate_prefix, '_', self.name, | ||
28 | '(DisasContext *ctx, arg_', self.name, | ||
29 | ' *a, ', insntype, ' insn);\n') | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | ||
32 | output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n') | ||
33 | for n, f in self.fields.items(): | ||
34 | output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') | ||
35 | - output(ind, translate_prefix, '_', self.name, | ||
36 | + output(ind, 'return ', translate_prefix, '_', self.name, | ||
37 | '(ctx, &u.f_', arg, ', insn);\n') | ||
38 | - output(ind, 'return true;\n') | ||
39 | # end Pattern | ||
40 | |||
41 | |||
42 | -- | ||
43 | 2.16.2 | ||
44 | |||
45 | diff view generated by jsdifflib |
1 | Define a new board model for the MPS2 with an AN505 FPGA image | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | containing a Cortex-M33. Since the FPGA images for TrustZone | ||
3 | cores (AN505, and the similar AN519 for Cortex-M23) have a | ||
4 | significantly different layout of devices to the non-TrustZone | ||
5 | images, we use a new source file rather than shoehorning them | ||
6 | into the existing mps2.c. | ||
7 | 2 | ||
3 | With Apple Silicon available to the masses, it's a good time to add support | ||
4 | for driving its virtualization extensions from QEMU. | ||
5 | |||
6 | This patch adds all necessary architecture specific code to get basic VMs | ||
7 | working, including save/restore. | ||
8 | |||
9 | Known limitations: | ||
10 | |||
11 | - WFI handling is missing (follows in later patch) | ||
12 | - No watchpoint/breakpoint support | ||
13 | |||
14 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
15 | Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> | ||
16 | Reviewed-by: Sergio Lopez <slp@redhat.com> | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Message-id: 20210916155404.86958-5-agraf@csgraf.de | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-20-peter.maydell@linaro.org | ||
11 | --- | 20 | --- |
12 | hw/arm/Makefile.objs | 1 + | 21 | meson.build | 1 + |
13 | hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++ | 22 | include/sysemu/hvf_int.h | 10 +- |
14 | 2 files changed, 504 insertions(+) | 23 | accel/hvf/hvf-accel-ops.c | 9 + |
15 | create mode 100644 hw/arm/mps2-tz.c | 24 | target/arm/hvf/hvf.c | 794 ++++++++++++++++++++++++++++++++++++ |
25 | target/i386/hvf/hvf.c | 5 + | ||
26 | MAINTAINERS | 5 + | ||
27 | target/arm/hvf/trace-events | 10 + | ||
28 | 7 files changed, 833 insertions(+), 1 deletion(-) | ||
29 | create mode 100644 target/arm/hvf/hvf.c | ||
30 | create mode 100644 target/arm/hvf/trace-events | ||
16 | 31 | ||
17 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 32 | diff --git a/meson.build b/meson.build |
18 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/Makefile.objs | 34 | --- a/meson.build |
20 | +++ b/hw/arm/Makefile.objs | 35 | +++ b/meson.build |
21 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | 36 | @@ -XXX,XX +XXX,XX @@ if have_system or have_user |
22 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 37 | 'accel/tcg', |
23 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 38 | 'hw/core', |
24 | obj-$(CONFIG_MPS2) += mps2.o | 39 | 'target/arm', |
25 | +obj-$(CONFIG_MPS2) += mps2-tz.o | 40 | + 'target/arm/hvf', |
26 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 41 | 'target/hppa', |
27 | obj-$(CONFIG_IOTKIT) += iotkit.o | 42 | 'target/i386', |
28 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 43 | 'target/i386/kvm', |
44 | diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/include/sysemu/hvf_int.h | ||
47 | +++ b/include/sysemu/hvf_int.h | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | #ifndef HVF_INT_H | ||
50 | #define HVF_INT_H | ||
51 | |||
52 | +#ifdef __aarch64__ | ||
53 | +#include <Hypervisor/Hypervisor.h> | ||
54 | +#else | ||
55 | #include <Hypervisor/hv.h> | ||
56 | +#endif | ||
57 | |||
58 | /* hvf_slot flags */ | ||
59 | #define HVF_SLOT_LOG (1 << 0) | ||
60 | @@ -XXX,XX +XXX,XX @@ struct HVFState { | ||
61 | int num_slots; | ||
62 | |||
63 | hvf_vcpu_caps *hvf_caps; | ||
64 | + uint64_t vtimer_offset; | ||
65 | }; | ||
66 | extern HVFState *hvf_state; | ||
67 | |||
68 | struct hvf_vcpu_state { | ||
69 | - int fd; | ||
70 | + uint64_t fd; | ||
71 | + void *exit; | ||
72 | + bool vtimer_masked; | ||
73 | }; | ||
74 | |||
75 | void assert_hvf_ok(hv_return_t ret); | ||
76 | @@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *); | ||
77 | hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); | ||
78 | int hvf_put_registers(CPUState *); | ||
79 | int hvf_get_registers(CPUState *); | ||
80 | +void hvf_kick_vcpu_thread(CPUState *cpu); | ||
81 | |||
82 | #endif | ||
83 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/accel/hvf/hvf-accel-ops.c | ||
86 | +++ b/accel/hvf/hvf-accel-ops.c | ||
87 | @@ -XXX,XX +XXX,XX @@ | ||
88 | |||
89 | HVFState *hvf_state; | ||
90 | |||
91 | +#ifdef __aarch64__ | ||
92 | +#define HV_VM_DEFAULT NULL | ||
93 | +#endif | ||
94 | + | ||
95 | /* Memory slots */ | ||
96 | |||
97 | hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) | ||
98 | @@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu) | ||
99 | pthread_sigmask(SIG_BLOCK, NULL, &set); | ||
100 | sigdelset(&set, SIG_IPI); | ||
101 | |||
102 | +#ifdef __aarch64__ | ||
103 | + r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); | ||
104 | +#else | ||
105 | r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); | ||
106 | +#endif | ||
107 | cpu->vcpu_dirty = 1; | ||
108 | assert_hvf_ok(r); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) | ||
111 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
112 | |||
113 | ops->create_vcpu_thread = hvf_start_vcpu_thread; | ||
114 | + ops->kick_vcpu_thread = hvf_kick_vcpu_thread; | ||
115 | |||
116 | ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset; | ||
117 | ops->synchronize_post_init = hvf_cpu_synchronize_post_init; | ||
118 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
29 | new file mode 100644 | 119 | new file mode 100644 |
30 | index XXXXXXX..XXXXXXX | 120 | index XXXXXXX..XXXXXXX |
31 | --- /dev/null | 121 | --- /dev/null |
32 | +++ b/hw/arm/mps2-tz.c | 122 | +++ b/target/arm/hvf/hvf.c |
33 | @@ -XXX,XX +XXX,XX @@ | 123 | @@ -XXX,XX +XXX,XX @@ |
34 | +/* | 124 | +/* |
35 | + * ARM V2M MPS2 board emulation, trustzone aware FPGA images | 125 | + * QEMU Hypervisor.framework support for Apple Silicon |
126 | + | ||
127 | + * Copyright 2020 Alexander Graf <agraf@csgraf.de> | ||
36 | + * | 128 | + * |
37 | + * Copyright (c) 2017 Linaro Limited | 129 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
38 | + * Written by Peter Maydell | 130 | + * See the COPYING file in the top-level directory. |
39 | + * | 131 | + * |
40 | + * This program is free software; you can redistribute it and/or modify | ||
41 | + * it under the terms of the GNU General Public License version 2 or | ||
42 | + * (at your option) any later version. | ||
43 | + */ | 132 | + */ |
44 | + | 133 | + |
45 | +/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | ||
46 | + * FPGA but is otherwise the same as the 2). Since the CPU itself | ||
47 | + * and most of the devices are in the FPGA, the details of the board | ||
48 | + * as seen by the guest depend significantly on the FPGA image. | ||
49 | + * This source file covers the following FPGA images, for TrustZone cores: | ||
50 | + * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 | ||
51 | + * | ||
52 | + * Links to the TRM for the board itself and to the various Application | ||
53 | + * Notes which document the FPGA images can be found here: | ||
54 | + * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | ||
55 | + * | ||
56 | + * Board TRM: | ||
57 | + * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | ||
58 | + * Application Note AN505: | ||
59 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
60 | + * | ||
61 | + * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | ||
62 | + * (ARM ECM0601256) for the details of some of the device layout: | ||
63 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
64 | + */ | ||
65 | + | ||
66 | +#include "qemu/osdep.h" | 134 | +#include "qemu/osdep.h" |
67 | +#include "qapi/error.h" | 135 | +#include "qemu-common.h" |
68 | +#include "qemu/error-report.h" | 136 | +#include "qemu/error-report.h" |
69 | +#include "hw/arm/arm.h" | 137 | + |
70 | +#include "hw/arm/armv7m.h" | 138 | +#include "sysemu/runstate.h" |
71 | +#include "hw/or-irq.h" | 139 | +#include "sysemu/hvf.h" |
72 | +#include "hw/boards.h" | 140 | +#include "sysemu/hvf_int.h" |
141 | +#include "sysemu/hw_accel.h" | ||
142 | + | ||
143 | +#include <mach/mach_time.h> | ||
144 | + | ||
73 | +#include "exec/address-spaces.h" | 145 | +#include "exec/address-spaces.h" |
74 | +#include "sysemu/sysemu.h" | 146 | +#include "hw/irq.h" |
75 | +#include "hw/misc/unimp.h" | 147 | +#include "qemu/main-loop.h" |
76 | +#include "hw/char/cmsdk-apb-uart.h" | 148 | +#include "sysemu/cpus.h" |
77 | +#include "hw/timer/cmsdk-apb-timer.h" | 149 | +#include "target/arm/cpu.h" |
78 | +#include "hw/misc/mps2-scc.h" | 150 | +#include "target/arm/internals.h" |
79 | +#include "hw/misc/mps2-fpgaio.h" | 151 | +#include "trace/trace-target_arm_hvf.h" |
80 | +#include "hw/arm/iotkit.h" | 152 | +#include "migration/vmstate.h" |
81 | +#include "hw/devices.h" | 153 | + |
82 | +#include "net/net.h" | 154 | +#define HVF_SYSREG(crn, crm, op0, op1, op2) \ |
83 | +#include "hw/core/split-irq.h" | 155 | + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) |
84 | + | 156 | +#define PL1_WRITE_MASK 0x4 |
85 | +typedef enum MPS2TZFPGAType { | 157 | + |
86 | + FPGA_AN505, | 158 | +#define SYSREG(op0, op1, crn, crm, op2) \ |
87 | +} MPS2TZFPGAType; | 159 | + ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1)) |
88 | + | 160 | +#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7) |
89 | +typedef struct { | 161 | +#define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) |
90 | + MachineClass parent; | 162 | +#define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) |
91 | + MPS2TZFPGAType fpga_type; | 163 | +#define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) |
92 | + uint32_t scc_id; | 164 | +#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) |
93 | +} MPS2TZMachineClass; | 165 | + |
94 | + | 166 | +#define WFX_IS_WFE (1 << 0) |
95 | +typedef struct { | 167 | + |
96 | + MachineState parent; | 168 | +#define TMR_CTL_ENABLE (1 << 0) |
97 | + | 169 | +#define TMR_CTL_IMASK (1 << 1) |
98 | + IoTKit iotkit; | 170 | +#define TMR_CTL_ISTATUS (1 << 2) |
99 | + MemoryRegion psram; | 171 | + |
100 | + MemoryRegion ssram1; | 172 | +typedef struct HVFVTimer { |
101 | + MemoryRegion ssram1_m; | 173 | + /* Vtimer value during migration and paused state */ |
102 | + MemoryRegion ssram23; | 174 | + uint64_t vtimer_val; |
103 | + MPS2SCC scc; | 175 | +} HVFVTimer; |
104 | + MPS2FPGAIO fpgaio; | 176 | + |
105 | + TZPPC ppc[5]; | 177 | +static HVFVTimer vtimer; |
106 | + UnimplementedDeviceState ssram_mpc[3]; | 178 | + |
107 | + UnimplementedDeviceState spi[5]; | 179 | +struct hvf_reg_match { |
108 | + UnimplementedDeviceState i2c[4]; | 180 | + int reg; |
109 | + UnimplementedDeviceState i2s_audio; | 181 | + uint64_t offset; |
110 | + UnimplementedDeviceState gpio[5]; | 182 | +}; |
111 | + UnimplementedDeviceState dma[4]; | 183 | + |
112 | + UnimplementedDeviceState gfx; | 184 | +static const struct hvf_reg_match hvf_reg_match[] = { |
113 | + CMSDKAPBUART uart[5]; | 185 | + { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, |
114 | + SplitIRQ sec_resp_splitter; | 186 | + { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, |
115 | + qemu_or_irq uart_irq_orgate; | 187 | + { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, |
116 | +} MPS2TZMachineState; | 188 | + { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, |
117 | + | 189 | + { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, |
118 | +#define TYPE_MPS2TZ_MACHINE "mps2tz" | 190 | + { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, |
119 | +#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") | 191 | + { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, |
120 | + | 192 | + { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, |
121 | +#define MPS2TZ_MACHINE(obj) \ | 193 | + { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, |
122 | + OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) | 194 | + { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, |
123 | +#define MPS2TZ_MACHINE_GET_CLASS(obj) \ | 195 | + { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, |
124 | + OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) | 196 | + { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, |
125 | +#define MPS2TZ_MACHINE_CLASS(klass) \ | 197 | + { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, |
126 | + OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) | 198 | + { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, |
127 | + | 199 | + { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, |
128 | +/* Main SYSCLK frequency in Hz */ | 200 | + { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, |
129 | +#define SYSCLK_FRQ 20000000 | 201 | + { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, |
130 | + | 202 | + { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, |
131 | +/* Initialize the auxiliary RAM region @mr and map it into | 203 | + { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, |
132 | + * the memory map at @base. | 204 | + { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, |
133 | + */ | 205 | + { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, |
134 | +static void make_ram(MemoryRegion *mr, const char *name, | 206 | + { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, |
135 | + hwaddr base, hwaddr size) | 207 | + { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, |
136 | +{ | 208 | + { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, |
137 | + memory_region_init_ram(mr, NULL, name, size, &error_fatal); | 209 | + { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, |
138 | + memory_region_add_subregion(get_system_memory(), base, mr); | 210 | + { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, |
139 | +} | 211 | + { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, |
140 | + | 212 | + { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, |
141 | +/* Create an alias of an entire original MemoryRegion @orig | 213 | + { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, |
142 | + * located at @base in the memory map. | 214 | + { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, |
143 | + */ | 215 | + { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, |
144 | +static void make_ram_alias(MemoryRegion *mr, const char *name, | 216 | + { HV_REG_PC, offsetof(CPUARMState, pc) }, |
145 | + MemoryRegion *orig, hwaddr base) | 217 | +}; |
146 | +{ | 218 | + |
147 | + memory_region_init_alias(mr, NULL, name, orig, 0, | 219 | +static const struct hvf_reg_match hvf_fpreg_match[] = { |
148 | + memory_region_size(orig)); | 220 | + { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, |
149 | + memory_region_add_subregion(get_system_memory(), base, mr); | 221 | + { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, |
150 | +} | 222 | + { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, |
151 | + | 223 | + { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, |
152 | +static void init_sysbus_child(Object *parent, const char *childname, | 224 | + { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, |
153 | + void *child, size_t childsize, | 225 | + { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, |
154 | + const char *childtype) | 226 | + { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, |
155 | +{ | 227 | + { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, |
156 | + object_initialize(child, childsize, childtype); | 228 | + { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, |
157 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | 229 | + { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, |
158 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | 230 | + { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, |
159 | + | 231 | + { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, |
160 | +} | 232 | + { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, |
161 | + | 233 | + { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, |
162 | +/* Most of the devices in the AN505 FPGA image sit behind | 234 | + { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, |
163 | + * Peripheral Protection Controllers. These data structures | 235 | + { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, |
164 | + * define the layout of which devices sit behind which PPCs. | 236 | + { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, |
165 | + * The devfn for each port is a function which creates, configures | 237 | + { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, |
166 | + * and initializes the device, returning the MemoryRegion which | 238 | + { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, |
167 | + * needs to be plugged into the downstream end of the PPC port. | 239 | + { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, |
168 | + */ | 240 | + { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, |
169 | +typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, | 241 | + { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, |
170 | + const char *name, hwaddr size); | 242 | + { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, |
171 | + | 243 | + { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, |
172 | +typedef struct PPCPortInfo { | 244 | + { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, |
173 | + const char *name; | 245 | + { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, |
174 | + MakeDevFn *devfn; | 246 | + { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, |
175 | + void *opaque; | 247 | + { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, |
176 | + hwaddr addr; | 248 | + { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, |
177 | + hwaddr size; | 249 | + { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, |
178 | +} PPCPortInfo; | 250 | + { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, |
179 | + | 251 | + { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, |
180 | +typedef struct PPCInfo { | 252 | +}; |
181 | + const char *name; | 253 | + |
182 | + PPCPortInfo ports[TZ_NUM_PORTS]; | 254 | +struct hvf_sreg_match { |
183 | +} PPCInfo; | 255 | + int reg; |
184 | + | 256 | + uint32_t key; |
185 | +static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | 257 | + uint32_t cp_idx; |
186 | + void *opaque, | 258 | +}; |
187 | + const char *name, hwaddr size) | 259 | + |
188 | +{ | 260 | +static struct hvf_sreg_match hvf_sreg_match[] = { |
189 | + /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | 261 | + { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, |
190 | + * and return a pointer to its MemoryRegion. | 262 | + { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, |
263 | + { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, | ||
264 | + { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, | ||
265 | + | ||
266 | + { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, | ||
267 | + { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, | ||
268 | + { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, | ||
269 | + { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, | ||
270 | + | ||
271 | + { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, | ||
272 | + { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, | ||
273 | + { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, | ||
274 | + { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, | ||
275 | + | ||
276 | + { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, | ||
277 | + { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, | ||
278 | + { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, | ||
279 | + { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, | ||
280 | + | ||
281 | + { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, | ||
282 | + { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, | ||
283 | + { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, | ||
284 | + { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, | ||
285 | + | ||
286 | + { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, | ||
287 | + { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, | ||
288 | + { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, | ||
289 | + { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, | ||
290 | + | ||
291 | + { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, | ||
292 | + { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, | ||
293 | + { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, | ||
294 | + { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, | ||
295 | + | ||
296 | + { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, | ||
297 | + { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, | ||
298 | + { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, | ||
299 | + { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, | ||
300 | + | ||
301 | + { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, | ||
302 | + { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, | ||
303 | + { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, | ||
304 | + { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, | ||
305 | + | ||
306 | + { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, | ||
307 | + { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, | ||
308 | + { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, | ||
309 | + { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, | ||
310 | + | ||
311 | + { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, | ||
312 | + { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, | ||
313 | + { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, | ||
314 | + { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, | ||
315 | + | ||
316 | + { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, | ||
317 | + { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, | ||
318 | + { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, | ||
319 | + { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, | ||
320 | + | ||
321 | + { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, | ||
322 | + { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, | ||
323 | + { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, | ||
324 | + { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, | ||
325 | + | ||
326 | + { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, | ||
327 | + { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, | ||
328 | + { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, | ||
329 | + { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, | ||
330 | + | ||
331 | + { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, | ||
332 | + { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, | ||
333 | + { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, | ||
334 | + { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, | ||
335 | + | ||
336 | + { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, | ||
337 | + { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, | ||
338 | + { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, | ||
339 | + { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, | ||
340 | + | ||
341 | +#ifdef SYNC_NO_RAW_REGS | ||
342 | + /* | ||
343 | + * The registers below are manually synced on init because they are | ||
344 | + * marked as NO_RAW. We still list them to make number space sync easier. | ||
191 | + */ | 345 | + */ |
192 | + UnimplementedDeviceState *uds = opaque; | 346 | + { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, |
193 | + | 347 | + { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, |
194 | + init_sysbus_child(OBJECT(mms), name, uds, | 348 | + { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, |
195 | + sizeof(UnimplementedDeviceState), | 349 | + { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, |
196 | + TYPE_UNIMPLEMENTED_DEVICE); | 350 | +#endif |
197 | + qdev_prop_set_string(DEVICE(uds), "name", name); | 351 | + { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, |
198 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | 352 | + { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, |
199 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | 353 | + { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, |
200 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); | 354 | + { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, |
201 | +} | 355 | + { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, |
202 | + | 356 | +#ifdef SYNC_NO_MMFR0 |
203 | +static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | 357 | + /* We keep the hardware MMFR0 around. HW limits are there anyway */ |
204 | + const char *name, hwaddr size) | 358 | + { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, |
205 | +{ | 359 | +#endif |
206 | + CMSDKAPBUART *uart = opaque; | 360 | + { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, |
207 | + int i = uart - &mms->uart[0]; | 361 | + { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, |
208 | + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; | 362 | + |
209 | + int rxirqno = i * 2; | 363 | + { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, |
210 | + int txirqno = i * 2 + 1; | 364 | + { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, |
211 | + int combirqno = i + 10; | 365 | + { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, |
212 | + SysBusDevice *s; | 366 | + { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, |
213 | + DeviceState *iotkitdev = DEVICE(&mms->iotkit); | 367 | + { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, |
214 | + DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | 368 | + { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, |
215 | + | 369 | + |
216 | + init_sysbus_child(OBJECT(mms), name, uart, | 370 | + { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, |
217 | + sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); | 371 | + { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, |
218 | + qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); | 372 | + { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, |
219 | + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); | 373 | + { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, |
220 | + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | 374 | + { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, |
221 | + s = SYS_BUS_DEVICE(uart); | 375 | + { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, |
222 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, | 376 | + { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, |
223 | + "EXP_IRQ", txirqno)); | 377 | + { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, |
224 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, | 378 | + { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, |
225 | + "EXP_IRQ", rxirqno)); | 379 | + { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, |
226 | + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); | 380 | + |
227 | + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | 381 | + { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, |
228 | + sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, | 382 | + { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, |
229 | + "EXP_IRQ", combirqno)); | 383 | + { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, |
230 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); | 384 | + { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, |
231 | +} | 385 | + { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, |
232 | + | 386 | + { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, |
233 | +static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | 387 | + { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, |
234 | + const char *name, hwaddr size) | 388 | + { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, |
235 | +{ | 389 | + { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, |
236 | + MPS2SCC *scc = opaque; | 390 | + { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, |
237 | + DeviceState *sccdev; | 391 | + { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, |
238 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | 392 | + { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, |
239 | + | 393 | + { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, |
240 | + object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); | 394 | + { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, |
241 | + sccdev = DEVICE(scc); | 395 | + { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, |
242 | + qdev_set_parent_bus(sccdev, sysbus_get_default()); | 396 | + { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, |
243 | + qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | 397 | + { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, |
244 | + qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); | 398 | + { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, |
245 | + qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | 399 | + { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, |
246 | + object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); | 400 | + { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, |
247 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); | 401 | +}; |
248 | +} | 402 | + |
249 | + | 403 | +int hvf_get_registers(CPUState *cpu) |
250 | +static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | 404 | +{ |
251 | + const char *name, hwaddr size) | 405 | + ARMCPU *arm_cpu = ARM_CPU(cpu); |
252 | +{ | 406 | + CPUARMState *env = &arm_cpu->env; |
253 | + MPS2FPGAIO *fpgaio = opaque; | 407 | + hv_return_t ret; |
254 | + | 408 | + uint64_t val; |
255 | + object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); | 409 | + hv_simd_fp_uchar16_t fpval; |
256 | + qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); | ||
257 | + object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); | ||
258 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
259 | +} | ||
260 | + | ||
261 | +static void mps2tz_common_init(MachineState *machine) | ||
262 | +{ | ||
263 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
264 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
265 | + MemoryRegion *system_memory = get_system_memory(); | ||
266 | + DeviceState *iotkitdev; | ||
267 | + DeviceState *dev_splitter; | ||
268 | + int i; | 410 | + int i; |
269 | + | 411 | + |
270 | + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | 412 | + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { |
271 | + error_report("This board can only be used with CPU %s", | 413 | + ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); |
272 | + mc->default_cpu_type); | 414 | + *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; |
273 | + exit(1); | 415 | + assert_hvf_ok(ret); |
274 | + } | 416 | + } |
275 | + | 417 | + |
276 | + init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, | 418 | + for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { |
277 | + sizeof(mms->iotkit), TYPE_IOTKIT); | 419 | + ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, |
278 | + iotkitdev = DEVICE(&mms->iotkit); | 420 | + &fpval); |
279 | + object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | 421 | + memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); |
280 | + "memory", &error_abort); | 422 | + assert_hvf_ok(ret); |
281 | + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); | 423 | + } |
282 | + qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); | 424 | + |
283 | + object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", | 425 | + val = 0; |
284 | + &error_fatal); | 426 | + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); |
285 | + | 427 | + assert_hvf_ok(ret); |
286 | + /* The sec_resp_cfg output from the IoTKit must be split into multiple | 428 | + vfp_set_fpcr(env, val); |
287 | + * lines, one for each of the PPCs we create here. | 429 | + |
430 | + val = 0; | ||
431 | + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); | ||
432 | + assert_hvf_ok(ret); | ||
433 | + vfp_set_fpsr(env, val); | ||
434 | + | ||
435 | + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); | ||
436 | + assert_hvf_ok(ret); | ||
437 | + pstate_write(env, val); | ||
438 | + | ||
439 | + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { | ||
440 | + if (hvf_sreg_match[i].cp_idx == -1) { | ||
441 | + continue; | ||
442 | + } | ||
443 | + | ||
444 | + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val); | ||
445 | + assert_hvf_ok(ret); | ||
446 | + | ||
447 | + arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; | ||
448 | + } | ||
449 | + assert(write_list_to_cpustate(arm_cpu)); | ||
450 | + | ||
451 | + aarch64_restore_sp(env, arm_current_el(env)); | ||
452 | + | ||
453 | + return 0; | ||
454 | +} | ||
455 | + | ||
456 | +int hvf_put_registers(CPUState *cpu) | ||
457 | +{ | ||
458 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
459 | + CPUARMState *env = &arm_cpu->env; | ||
460 | + hv_return_t ret; | ||
461 | + uint64_t val; | ||
462 | + hv_simd_fp_uchar16_t fpval; | ||
463 | + int i; | ||
464 | + | ||
465 | + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { | ||
466 | + val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); | ||
467 | + ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); | ||
468 | + assert_hvf_ok(ret); | ||
469 | + } | ||
470 | + | ||
471 | + for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { | ||
472 | + memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); | ||
473 | + ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, | ||
474 | + fpval); | ||
475 | + assert_hvf_ok(ret); | ||
476 | + } | ||
477 | + | ||
478 | + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); | ||
479 | + assert_hvf_ok(ret); | ||
480 | + | ||
481 | + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); | ||
482 | + assert_hvf_ok(ret); | ||
483 | + | ||
484 | + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); | ||
485 | + assert_hvf_ok(ret); | ||
486 | + | ||
487 | + aarch64_save_sp(env, arm_current_el(env)); | ||
488 | + | ||
489 | + assert(write_cpustate_to_list(arm_cpu, false)); | ||
490 | + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { | ||
491 | + if (hvf_sreg_match[i].cp_idx == -1) { | ||
492 | + continue; | ||
493 | + } | ||
494 | + | ||
495 | + val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; | ||
496 | + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val); | ||
497 | + assert_hvf_ok(ret); | ||
498 | + } | ||
499 | + | ||
500 | + ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset); | ||
501 | + assert_hvf_ok(ret); | ||
502 | + | ||
503 | + return 0; | ||
504 | +} | ||
505 | + | ||
506 | +static void flush_cpu_state(CPUState *cpu) | ||
507 | +{ | ||
508 | + if (cpu->vcpu_dirty) { | ||
509 | + hvf_put_registers(cpu); | ||
510 | + cpu->vcpu_dirty = false; | ||
511 | + } | ||
512 | +} | ||
513 | + | ||
514 | +static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) | ||
515 | +{ | ||
516 | + hv_return_t r; | ||
517 | + | ||
518 | + flush_cpu_state(cpu); | ||
519 | + | ||
520 | + if (rt < 31) { | ||
521 | + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); | ||
522 | + assert_hvf_ok(r); | ||
523 | + } | ||
524 | +} | ||
525 | + | ||
526 | +static uint64_t hvf_get_reg(CPUState *cpu, int rt) | ||
527 | +{ | ||
528 | + uint64_t val = 0; | ||
529 | + hv_return_t r; | ||
530 | + | ||
531 | + flush_cpu_state(cpu); | ||
532 | + | ||
533 | + if (rt < 31) { | ||
534 | + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); | ||
535 | + assert_hvf_ok(r); | ||
536 | + } | ||
537 | + | ||
538 | + return val; | ||
539 | +} | ||
540 | + | ||
541 | +void hvf_arch_vcpu_destroy(CPUState *cpu) | ||
542 | +{ | ||
543 | +} | ||
544 | + | ||
545 | +int hvf_arch_init_vcpu(CPUState *cpu) | ||
546 | +{ | ||
547 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
548 | + CPUARMState *env = &arm_cpu->env; | ||
549 | + uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); | ||
550 | + uint32_t sregs_cnt = 0; | ||
551 | + uint64_t pfr; | ||
552 | + hv_return_t ret; | ||
553 | + int i; | ||
554 | + | ||
555 | + env->aarch64 = 1; | ||
556 | + asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); | ||
557 | + | ||
558 | + /* Allocate enough space for our sysreg sync */ | ||
559 | + arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, | ||
560 | + sregs_match_len); | ||
561 | + arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, | ||
562 | + sregs_match_len); | ||
563 | + arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, | ||
564 | + arm_cpu->cpreg_vmstate_indexes, | ||
565 | + sregs_match_len); | ||
566 | + arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, | ||
567 | + arm_cpu->cpreg_vmstate_values, | ||
568 | + sregs_match_len); | ||
569 | + | ||
570 | + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); | ||
571 | + | ||
572 | + /* Populate cp list for all known sysregs */ | ||
573 | + for (i = 0; i < sregs_match_len; i++) { | ||
574 | + const ARMCPRegInfo *ri; | ||
575 | + uint32_t key = hvf_sreg_match[i].key; | ||
576 | + | ||
577 | + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); | ||
578 | + if (ri) { | ||
579 | + assert(!(ri->type & ARM_CP_NO_RAW)); | ||
580 | + hvf_sreg_match[i].cp_idx = sregs_cnt; | ||
581 | + arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); | ||
582 | + } else { | ||
583 | + hvf_sreg_match[i].cp_idx = -1; | ||
584 | + } | ||
585 | + } | ||
586 | + arm_cpu->cpreg_array_len = sregs_cnt; | ||
587 | + arm_cpu->cpreg_vmstate_array_len = sregs_cnt; | ||
588 | + | ||
589 | + assert(write_cpustate_to_list(arm_cpu, false)); | ||
590 | + | ||
591 | + /* Set CP_NO_RAW system registers on init */ | ||
592 | + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, | ||
593 | + arm_cpu->midr); | ||
594 | + assert_hvf_ok(ret); | ||
595 | + | ||
596 | + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, | ||
597 | + arm_cpu->mp_affinity); | ||
598 | + assert_hvf_ok(ret); | ||
599 | + | ||
600 | + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); | ||
601 | + assert_hvf_ok(ret); | ||
602 | + pfr |= env->gicv3state ? (1 << 24) : 0; | ||
603 | + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); | ||
604 | + assert_hvf_ok(ret); | ||
605 | + | ||
606 | + /* We're limited to underlying hardware caps, override internal versions */ | ||
607 | + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, | ||
608 | + &arm_cpu->isar.id_aa64mmfr0); | ||
609 | + assert_hvf_ok(ret); | ||
610 | + | ||
611 | + return 0; | ||
612 | +} | ||
613 | + | ||
614 | +void hvf_kick_vcpu_thread(CPUState *cpu) | ||
615 | +{ | ||
616 | + hv_vcpus_exit(&cpu->hvf->fd, 1); | ||
617 | +} | ||
618 | + | ||
619 | +static void hvf_raise_exception(CPUState *cpu, uint32_t excp, | ||
620 | + uint32_t syndrome) | ||
621 | +{ | ||
622 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
623 | + CPUARMState *env = &arm_cpu->env; | ||
624 | + | ||
625 | + cpu->exception_index = excp; | ||
626 | + env->exception.target_el = 1; | ||
627 | + env->exception.syndrome = syndrome; | ||
628 | + | ||
629 | + arm_cpu_do_interrupt(cpu); | ||
630 | +} | ||
631 | + | ||
632 | +static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) | ||
633 | +{ | ||
634 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
635 | + CPUARMState *env = &arm_cpu->env; | ||
636 | + uint64_t val = 0; | ||
637 | + | ||
638 | + switch (reg) { | ||
639 | + case SYSREG_CNTPCT_EL0: | ||
640 | + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / | ||
641 | + gt_cntfrq_period_ns(arm_cpu); | ||
642 | + break; | ||
643 | + case SYSREG_OSLSR_EL1: | ||
644 | + val = env->cp15.oslsr_el1; | ||
645 | + break; | ||
646 | + case SYSREG_OSDLR_EL1: | ||
647 | + /* Dummy register */ | ||
648 | + break; | ||
649 | + default: | ||
650 | + cpu_synchronize_state(cpu); | ||
651 | + trace_hvf_unhandled_sysreg_read(env->pc, reg, | ||
652 | + (reg >> 20) & 0x3, | ||
653 | + (reg >> 14) & 0x7, | ||
654 | + (reg >> 10) & 0xf, | ||
655 | + (reg >> 1) & 0xf, | ||
656 | + (reg >> 17) & 0x7); | ||
657 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); | ||
658 | + return 1; | ||
659 | + } | ||
660 | + | ||
661 | + trace_hvf_sysreg_read(reg, | ||
662 | + (reg >> 20) & 0x3, | ||
663 | + (reg >> 14) & 0x7, | ||
664 | + (reg >> 10) & 0xf, | ||
665 | + (reg >> 1) & 0xf, | ||
666 | + (reg >> 17) & 0x7, | ||
667 | + val); | ||
668 | + hvf_set_reg(cpu, rt, val); | ||
669 | + | ||
670 | + return 0; | ||
671 | +} | ||
672 | + | ||
673 | +static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) | ||
674 | +{ | ||
675 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
676 | + CPUARMState *env = &arm_cpu->env; | ||
677 | + | ||
678 | + trace_hvf_sysreg_write(reg, | ||
679 | + (reg >> 20) & 0x3, | ||
680 | + (reg >> 14) & 0x7, | ||
681 | + (reg >> 10) & 0xf, | ||
682 | + (reg >> 1) & 0xf, | ||
683 | + (reg >> 17) & 0x7, | ||
684 | + val); | ||
685 | + | ||
686 | + switch (reg) { | ||
687 | + case SYSREG_OSLAR_EL1: | ||
688 | + env->cp15.oslsr_el1 = val & 1; | ||
689 | + break; | ||
690 | + case SYSREG_OSDLR_EL1: | ||
691 | + /* Dummy register */ | ||
692 | + break; | ||
693 | + default: | ||
694 | + cpu_synchronize_state(cpu); | ||
695 | + trace_hvf_unhandled_sysreg_write(env->pc, reg, | ||
696 | + (reg >> 20) & 0x3, | ||
697 | + (reg >> 14) & 0x7, | ||
698 | + (reg >> 10) & 0xf, | ||
699 | + (reg >> 1) & 0xf, | ||
700 | + (reg >> 17) & 0x7); | ||
701 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); | ||
702 | + return 1; | ||
703 | + } | ||
704 | + | ||
705 | + return 0; | ||
706 | +} | ||
707 | + | ||
708 | +static int hvf_inject_interrupts(CPUState *cpu) | ||
709 | +{ | ||
710 | + if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { | ||
711 | + trace_hvf_inject_fiq(); | ||
712 | + hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, | ||
713 | + true); | ||
714 | + } | ||
715 | + | ||
716 | + if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { | ||
717 | + trace_hvf_inject_irq(); | ||
718 | + hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, | ||
719 | + true); | ||
720 | + } | ||
721 | + | ||
722 | + return 0; | ||
723 | +} | ||
724 | + | ||
725 | +static uint64_t hvf_vtimer_val_raw(void) | ||
726 | +{ | ||
727 | + /* | ||
728 | + * mach_absolute_time() returns the vtimer value without the VM | ||
729 | + * offset that we define. Add our own offset on top. | ||
288 | + */ | 730 | + */ |
289 | + object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), | 731 | + return mach_absolute_time() - hvf_state->vtimer_offset; |
290 | + TYPE_SPLIT_IRQ); | 732 | +} |
291 | + object_property_add_child(OBJECT(machine), "sec-resp-splitter", | 733 | + |
292 | + OBJECT(&mms->sec_resp_splitter), &error_abort); | 734 | +static void hvf_sync_vtimer(CPUState *cpu) |
293 | + object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, | 735 | +{ |
294 | + "num-lines", &error_fatal); | 736 | + ARMCPU *arm_cpu = ARM_CPU(cpu); |
295 | + object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, | 737 | + hv_return_t r; |
296 | + "realized", &error_fatal); | 738 | + uint64_t ctl; |
297 | + dev_splitter = DEVICE(&mms->sec_resp_splitter); | 739 | + bool irq_state; |
298 | + qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, | 740 | + |
299 | + qdev_get_gpio_in(dev_splitter, 0)); | 741 | + if (!cpu->hvf->vtimer_masked) { |
300 | + | 742 | + /* We will get notified on vtimer changes by hvf, nothing to do */ |
301 | + /* The IoTKit sets up much of the memory layout, including | 743 | + return; |
302 | + * the aliases between secure and non-secure regions in the | 744 | + } |
303 | + * address space. The FPGA itself contains: | 745 | + |
304 | + * | 746 | + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); |
305 | + * 0x00000000..0x003fffff SSRAM1 | 747 | + assert_hvf_ok(r); |
306 | + * 0x00400000..0x007fffff alias of SSRAM1 | 748 | + |
307 | + * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 | 749 | + irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == |
308 | + * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices | 750 | + (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); |
309 | + * 0x80000000..0x80ffffff 16MB PSRAM | 751 | + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); |
310 | + */ | 752 | + |
311 | + | 753 | + if (!irq_state) { |
312 | + /* The FPGA images have an odd combination of different RAMs, | 754 | + /* Timer no longer asserting, we can unmask it */ |
313 | + * because in hardware they are different implementations and | 755 | + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); |
314 | + * connected to different buses, giving varying performance/size | 756 | + cpu->hvf->vtimer_masked = false; |
315 | + * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | 757 | + } |
316 | + * call the 16MB our "system memory", as it's the largest lump. | 758 | +} |
317 | + */ | 759 | + |
318 | + memory_region_allocate_system_memory(&mms->psram, | 760 | +int hvf_vcpu_exec(CPUState *cpu) |
319 | + NULL, "mps.ram", 0x01000000); | 761 | +{ |
320 | + memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); | 762 | + ARMCPU *arm_cpu = ARM_CPU(cpu); |
321 | + | 763 | + CPUARMState *env = &arm_cpu->env; |
322 | + /* The SSRAM memories should all be behind Memory Protection Controllers, | 764 | + hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit; |
323 | + * but we don't implement that yet. | 765 | + hv_return_t r; |
324 | + */ | 766 | + bool advance_pc = false; |
325 | + make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000); | 767 | + |
326 | + make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000); | 768 | + if (hvf_inject_interrupts(cpu)) { |
327 | + | 769 | + return EXCP_INTERRUPT; |
328 | + make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000); | 770 | + } |
329 | + | 771 | + |
330 | + /* The overflow IRQs for all UARTs are ORed together. | 772 | + if (cpu->halted) { |
331 | + * Tx, Rx and "combined" IRQs are sent to the NVIC separately. | 773 | + return EXCP_HLT; |
332 | + * Create the OR gate for this. | 774 | + } |
333 | + */ | 775 | + |
334 | + object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), | 776 | + flush_cpu_state(cpu); |
335 | + TYPE_OR_IRQ); | 777 | + |
336 | + object_property_add_child(OBJECT(mms), "uart-irq-orgate", | 778 | + qemu_mutex_unlock_iothread(); |
337 | + OBJECT(&mms->uart_irq_orgate), &error_abort); | 779 | + assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); |
338 | + object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", | 780 | + |
339 | + &error_fatal); | 781 | + /* handle VMEXIT */ |
340 | + object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, | 782 | + uint64_t exit_reason = hvf_exit->reason; |
341 | + "realized", &error_fatal); | 783 | + uint64_t syndrome = hvf_exit->exception.syndrome; |
342 | + qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | 784 | + uint32_t ec = syn_get_ec(syndrome); |
343 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); | 785 | + |
344 | + | 786 | + qemu_mutex_lock_iothread(); |
345 | + /* Most of the devices in the FPGA are behind Peripheral Protection | 787 | + switch (exit_reason) { |
346 | + * Controllers. The required order for initializing things is: | 788 | + case HV_EXIT_REASON_EXCEPTION: |
347 | + * + initialize the PPC | 789 | + /* This is the main one, handle below. */ |
348 | + * + initialize, configure and realize downstream devices | 790 | + break; |
349 | + * + connect downstream device MemoryRegions to the PPC | 791 | + case HV_EXIT_REASON_VTIMER_ACTIVATED: |
350 | + * + realize the PPC | 792 | + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); |
351 | + * + map the PPC's MemoryRegions to the places in the address map | 793 | + cpu->hvf->vtimer_masked = true; |
352 | + * where the downstream devices should appear | 794 | + return 0; |
353 | + * + wire up the PPC's control lines to the IoTKit object | 795 | + case HV_EXIT_REASON_CANCELED: |
354 | + */ | 796 | + /* we got kicked, no exit to process */ |
355 | + | 797 | + return 0; |
356 | + const PPCInfo ppcs[] = { { | 798 | + default: |
357 | + .name = "apb_ppcexp0", | 799 | + assert(0); |
358 | + .ports = { | 800 | + } |
359 | + { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0], | 801 | + |
360 | + 0x58007000, 0x1000 }, | 802 | + hvf_sync_vtimer(cpu); |
361 | + { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1], | 803 | + |
362 | + 0x58008000, 0x1000 }, | 804 | + switch (ec) { |
363 | + { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2], | 805 | + case EC_DATAABORT: { |
364 | + 0x58009000, 0x1000 }, | 806 | + bool isv = syndrome & ARM_EL_ISV; |
365 | + }, | 807 | + bool iswrite = (syndrome >> 6) & 1; |
366 | + }, { | 808 | + bool s1ptw = (syndrome >> 7) & 1; |
367 | + .name = "apb_ppcexp1", | 809 | + uint32_t sas = (syndrome >> 22) & 3; |
368 | + .ports = { | 810 | + uint32_t len = 1 << sas; |
369 | + { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, | 811 | + uint32_t srt = (syndrome >> 16) & 0x1f; |
370 | + { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, | 812 | + uint64_t val = 0; |
371 | + { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, | 813 | + |
372 | + { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, | 814 | + trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, |
373 | + { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, | 815 | + hvf_exit->exception.physical_address, isv, |
374 | + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, | 816 | + iswrite, s1ptw, len, srt); |
375 | + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | 817 | + |
376 | + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | 818 | + assert(isv); |
377 | + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | 819 | + |
378 | + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | 820 | + if (iswrite) { |
379 | + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | 821 | + val = hvf_get_reg(cpu, srt); |
380 | + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | 822 | + address_space_write(&address_space_memory, |
381 | + { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | 823 | + hvf_exit->exception.physical_address, |
382 | + { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | 824 | + MEMTXATTRS_UNSPECIFIED, &val, len); |
383 | + }, | 825 | + } else { |
384 | + }, { | 826 | + address_space_read(&address_space_memory, |
385 | + .name = "apb_ppcexp2", | 827 | + hvf_exit->exception.physical_address, |
386 | + .ports = { | 828 | + MEMTXATTRS_UNSPECIFIED, &val, len); |
387 | + { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, | 829 | + hvf_set_reg(cpu, srt, val); |
388 | + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, | ||
389 | + 0x40301000, 0x1000 }, | ||
390 | + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, | ||
391 | + }, | ||
392 | + }, { | ||
393 | + .name = "ahb_ppcexp0", | ||
394 | + .ports = { | ||
395 | + { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, | ||
396 | + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, | ||
397 | + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
398 | + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
399 | + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
400 | + { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, | ||
401 | + }, | ||
402 | + }, { | ||
403 | + .name = "ahb_ppcexp1", | ||
404 | + .ports = { | ||
405 | + { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, | ||
406 | + { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, | ||
407 | + { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, | ||
408 | + { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, | ||
409 | + }, | ||
410 | + }, | ||
411 | + }; | ||
412 | + | ||
413 | + for (i = 0; i < ARRAY_SIZE(ppcs); i++) { | ||
414 | + const PPCInfo *ppcinfo = &ppcs[i]; | ||
415 | + TZPPC *ppc = &mms->ppc[i]; | ||
416 | + DeviceState *ppcdev; | ||
417 | + int port; | ||
418 | + char *gpioname; | ||
419 | + | ||
420 | + init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, | ||
421 | + sizeof(TZPPC), TYPE_TZ_PPC); | ||
422 | + ppcdev = DEVICE(ppc); | ||
423 | + | ||
424 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
425 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
426 | + MemoryRegion *mr; | ||
427 | + char *portname; | ||
428 | + | ||
429 | + if (!pinfo->devfn) { | ||
430 | + continue; | ||
431 | + } | ||
432 | + | ||
433 | + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | ||
434 | + portname = g_strdup_printf("port[%d]", port); | ||
435 | + object_property_set_link(OBJECT(ppc), OBJECT(mr), | ||
436 | + portname, &error_fatal); | ||
437 | + g_free(portname); | ||
438 | + } | 830 | + } |
439 | + | 831 | + |
440 | + object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); | 832 | + advance_pc = true; |
441 | + | 833 | + break; |
442 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | 834 | + } |
443 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | 835 | + case EC_SYSTEMREGISTERTRAP: { |
444 | + | 836 | + bool isread = (syndrome >> 0) & 1; |
445 | + if (!pinfo->devfn) { | 837 | + uint32_t rt = (syndrome >> 5) & 0x1f; |
446 | + continue; | 838 | + uint32_t reg = syndrome & SYSREG_MASK; |
447 | + } | 839 | + uint64_t val; |
448 | + sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); | 840 | + int ret = 0; |
449 | + | 841 | + |
450 | + gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); | 842 | + if (isread) { |
451 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | 843 | + ret = hvf_sysreg_read(cpu, reg, rt); |
452 | + qdev_get_gpio_in_named(ppcdev, | 844 | + } else { |
453 | + "cfg_nonsec", | 845 | + val = hvf_get_reg(cpu, rt); |
454 | + port)); | 846 | + ret = hvf_sysreg_write(cpu, reg, val); |
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_ap", ppcinfo->name); | ||
457 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
458 | + qdev_get_gpio_in_named(ppcdev, | ||
459 | + "cfg_ap", port)); | ||
460 | + g_free(gpioname); | ||
461 | + } | 847 | + } |
462 | + | 848 | + |
463 | + gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); | 849 | + advance_pc = !ret; |
464 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | 850 | + break; |
465 | + qdev_get_gpio_in_named(ppcdev, | 851 | + } |
466 | + "irq_enable", 0)); | 852 | + case EC_WFX_TRAP: |
467 | + g_free(gpioname); | 853 | + advance_pc = true; |
468 | + gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); | 854 | + break; |
469 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | 855 | + case EC_AA64_HVC: |
470 | + qdev_get_gpio_in_named(ppcdev, | 856 | + cpu_synchronize_state(cpu); |
471 | + "irq_clear", 0)); | 857 | + trace_hvf_unknown_hvc(env->xregs[0]); |
472 | + g_free(gpioname); | 858 | + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ |
473 | + gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); | 859 | + env->xregs[0] = -1; |
474 | + qdev_connect_gpio_out_named(ppcdev, "irq", 0, | 860 | + break; |
475 | + qdev_get_gpio_in_named(iotkitdev, | 861 | + case EC_AA64_SMC: |
476 | + gpioname, 0)); | 862 | + cpu_synchronize_state(cpu); |
477 | + g_free(gpioname); | 863 | + trace_hvf_unknown_smc(env->xregs[0]); |
478 | + | 864 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); |
479 | + qdev_connect_gpio_out(dev_splitter, i, | 865 | + break; |
480 | + qdev_get_gpio_in_named(ppcdev, | 866 | + default: |
481 | + "cfg_sec_resp", 0)); | 867 | + cpu_synchronize_state(cpu); |
482 | + } | 868 | + trace_hvf_exit(syndrome, ec, env->pc); |
483 | + | 869 | + error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); |
484 | + /* In hardware this is a LAN9220; the LAN9118 is software compatible | 870 | + } |
485 | + * except that it doesn't support the checksum-offload feature. | 871 | + |
486 | + * The ethernet controller is not behind a PPC. | 872 | + if (advance_pc) { |
487 | + */ | 873 | + uint64_t pc; |
488 | + lan9118_init(&nd_table[0], 0x42000000, | 874 | + |
489 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | 875 | + flush_cpu_state(cpu); |
490 | + | 876 | + |
491 | + create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); | 877 | + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); |
492 | + | 878 | + assert_hvf_ok(r); |
493 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | 879 | + pc += 4; |
494 | +} | 880 | + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); |
495 | + | 881 | + assert_hvf_ok(r); |
496 | +static void mps2tz_class_init(ObjectClass *oc, void *data) | 882 | + } |
497 | +{ | 883 | + |
498 | + MachineClass *mc = MACHINE_CLASS(oc); | 884 | + return 0; |
499 | + | 885 | +} |
500 | + mc->init = mps2tz_common_init; | 886 | + |
501 | + mc->max_cpus = 1; | 887 | +static const VMStateDescription vmstate_hvf_vtimer = { |
502 | +} | 888 | + .name = "hvf-vtimer", |
503 | + | 889 | + .version_id = 1, |
504 | +static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | 890 | + .minimum_version_id = 1, |
505 | +{ | 891 | + .fields = (VMStateField[]) { |
506 | + MachineClass *mc = MACHINE_CLASS(oc); | 892 | + VMSTATE_UINT64(vtimer_val, HVFVTimer), |
507 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | 893 | + VMSTATE_END_OF_LIST() |
508 | + | 894 | + }, |
509 | + mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; | ||
510 | + mmc->fpga_type = FPGA_AN505; | ||
511 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | ||
512 | + mmc->scc_id = 0x41040000 | (505 << 4); | ||
513 | +} | ||
514 | + | ||
515 | +static const TypeInfo mps2tz_info = { | ||
516 | + .name = TYPE_MPS2TZ_MACHINE, | ||
517 | + .parent = TYPE_MACHINE, | ||
518 | + .abstract = true, | ||
519 | + .instance_size = sizeof(MPS2TZMachineState), | ||
520 | + .class_size = sizeof(MPS2TZMachineClass), | ||
521 | + .class_init = mps2tz_class_init, | ||
522 | +}; | 895 | +}; |
523 | + | 896 | + |
524 | +static const TypeInfo mps2tz_an505_info = { | 897 | +static void hvf_vm_state_change(void *opaque, bool running, RunState state) |
525 | + .name = TYPE_MPS2TZ_AN505_MACHINE, | 898 | +{ |
526 | + .parent = TYPE_MPS2TZ_MACHINE, | 899 | + HVFVTimer *s = opaque; |
527 | + .class_init = mps2tz_an505_class_init, | 900 | + |
528 | +}; | 901 | + if (running) { |
529 | + | 902 | + /* Update vtimer offset on all CPUs */ |
530 | +static void mps2tz_machine_init(void) | 903 | + hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; |
531 | +{ | 904 | + cpu_synchronize_all_states(); |
532 | + type_register_static(&mps2tz_info); | 905 | + } else { |
533 | + type_register_static(&mps2tz_an505_info); | 906 | + /* Remember vtimer value on every pause */ |
534 | +} | 907 | + s->vtimer_val = hvf_vtimer_val_raw(); |
535 | + | 908 | + } |
536 | +type_init(mps2tz_machine_init); | 909 | +} |
910 | + | ||
911 | +int hvf_arch_init(void) | ||
912 | +{ | ||
913 | + hvf_state->vtimer_offset = mach_absolute_time(); | ||
914 | + vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); | ||
915 | + qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); | ||
916 | + return 0; | ||
917 | +} | ||
918 | diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c | ||
919 | index XXXXXXX..XXXXXXX 100644 | ||
920 | --- a/target/i386/hvf/hvf.c | ||
921 | +++ b/target/i386/hvf/hvf.c | ||
922 | @@ -XXX,XX +XXX,XX @@ static inline bool apic_bus_freq_is_known(CPUX86State *env) | ||
923 | return env->apic_bus_freq != 0; | ||
924 | } | ||
925 | |||
926 | +void hvf_kick_vcpu_thread(CPUState *cpu) | ||
927 | +{ | ||
928 | + cpus_kick_thread(cpu); | ||
929 | +} | ||
930 | + | ||
931 | int hvf_arch_init(void) | ||
932 | { | ||
933 | return 0; | ||
934 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
935 | index XXXXXXX..XXXXXXX 100644 | ||
936 | --- a/MAINTAINERS | ||
937 | +++ b/MAINTAINERS | ||
938 | @@ -XXX,XX +XXX,XX @@ F: accel/accel-*.c | ||
939 | F: accel/Makefile.objs | ||
940 | F: accel/stubs/Makefile.objs | ||
941 | |||
942 | +Apple Silicon HVF CPUs | ||
943 | +M: Alexander Graf <agraf@csgraf.de> | ||
944 | +S: Maintained | ||
945 | +F: target/arm/hvf/ | ||
946 | + | ||
947 | X86 HVF CPUs | ||
948 | M: Cameron Esfahani <dirty@apple.com> | ||
949 | M: Roman Bolshakov <r.bolshakov@yadro.com> | ||
950 | diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events | ||
951 | new file mode 100644 | ||
952 | index XXXXXXX..XXXXXXX | ||
953 | --- /dev/null | ||
954 | +++ b/target/arm/hvf/trace-events | ||
955 | @@ -XXX,XX +XXX,XX @@ | ||
956 | +hvf_unhandled_sysreg_read(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)" | ||
957 | +hvf_unhandled_sysreg_write(uint64_t pc, uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)" | ||
958 | +hvf_inject_fiq(void) "injecting FIQ" | ||
959 | +hvf_inject_irq(void) "injecting IRQ" | ||
960 | +hvf_data_abort(uint64_t pc, uint64_t va, uint64_t pa, bool isv, bool iswrite, bool s1ptw, uint32_t len, uint32_t srt) "data abort: [pc=0x%"PRIx64" va=0x%016"PRIx64" pa=0x%016"PRIx64" isv=%d iswrite=%d s1ptw=%d len=%d srt=%d]" | ||
961 | +hvf_sysreg_read(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d) = 0x%016"PRIx64 | ||
962 | +hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d, val=0x%016"PRIx64")" | ||
963 | +hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 | ||
964 | +hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 | ||
965 | +hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]" | ||
537 | -- | 966 | -- |
538 | 2.16.2 | 967 | 2.20.1 |
539 | 968 | ||
540 | 969 | diff view generated by jsdifflib |
1 | Model the Arm IoT Kit documented in | 1 | From: Peter Collingbourne <pcc@google.com> |
---|---|---|---|
2 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
3 | 2 | ||
4 | The Arm IoT Kit is a subsystem which includes a CPU and some devices, | 3 | Sleep on WFI until the VTIMER is due but allow ourselves to be woken |
5 | and is intended be extended by adding extra devices to form a | 4 | up on IPI. |
6 | complete system. It is used in the MPS2 board's AN505 image for the | ||
7 | Cortex-M33. | ||
8 | 5 | ||
6 | In this implementation IPI is blocked on the CPU thread at startup and | ||
7 | pselect() is used to atomically unblock the signal and begin sleeping. | ||
8 | The signal is sent unconditionally so there's no need to worry about | ||
9 | races between actually sleeping and the "we think we're sleeping" | ||
10 | state. It may lead to an extra wakeup but that's better than missing | ||
11 | it entirely. | ||
12 | |||
13 | Signed-off-by: Peter Collingbourne <pcc@google.com> | ||
14 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
15 | Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> | ||
16 | Reviewed-by: Sergio Lopez <slp@redhat.com> | ||
17 | Message-id: 20210916155404.86958-6-agraf@csgraf.de | ||
18 | [agraf: Remove unused 'set' variable, always advance PC on WFX trap, | ||
19 | support vm stop / continue operations and cntv offsets] | ||
20 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
21 | Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> | ||
22 | Reviewed-by: Sergio Lopez <slp@redhat.com> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20180220180325.29818-19-peter.maydell@linaro.org | ||
12 | --- | 24 | --- |
13 | hw/arm/Makefile.objs | 1 + | 25 | include/sysemu/hvf_int.h | 1 + |
14 | include/hw/arm/iotkit.h | 109 ++++++++ | 26 | accel/hvf/hvf-accel-ops.c | 5 +-- |
15 | hw/arm/iotkit.c | 598 ++++++++++++++++++++++++++++++++++++++++ | 27 | target/arm/hvf/hvf.c | 79 +++++++++++++++++++++++++++++++++++++++ |
16 | default-configs/arm-softmmu.mak | 1 + | 28 | 3 files changed, 82 insertions(+), 3 deletions(-) |
17 | 4 files changed, 709 insertions(+) | ||
18 | create mode 100644 include/hw/arm/iotkit.h | ||
19 | create mode 100644 hw/arm/iotkit.c | ||
20 | 29 | ||
21 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 30 | diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h |
22 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/Makefile.objs | 32 | --- a/include/sysemu/hvf_int.h |
24 | +++ b/hw/arm/Makefile.objs | 33 | +++ b/include/sysemu/hvf_int.h |
25 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 34 | @@ -XXX,XX +XXX,XX @@ struct hvf_vcpu_state { |
26 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 35 | uint64_t fd; |
27 | obj-$(CONFIG_MPS2) += mps2.o | 36 | void *exit; |
28 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 37 | bool vtimer_masked; |
29 | +obj-$(CONFIG_IOTKIT) += iotkit.o | 38 | + sigset_t unblock_ipi_mask; |
30 | diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h | 39 | }; |
31 | new file mode 100644 | 40 | |
32 | index XXXXXXX..XXXXXXX | 41 | void assert_hvf_ok(hv_return_t ret); |
33 | --- /dev/null | 42 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c |
34 | +++ b/include/hw/arm/iotkit.h | 43 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/accel/hvf/hvf-accel-ops.c | ||
45 | +++ b/accel/hvf/hvf-accel-ops.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu) | ||
47 | cpu->hvf = g_malloc0(sizeof(*cpu->hvf)); | ||
48 | |||
49 | /* init cpu signals */ | ||
50 | - sigset_t set; | ||
51 | struct sigaction sigact; | ||
52 | |||
53 | memset(&sigact, 0, sizeof(sigact)); | ||
54 | sigact.sa_handler = dummy_signal; | ||
55 | sigaction(SIG_IPI, &sigact, NULL); | ||
56 | |||
57 | - pthread_sigmask(SIG_BLOCK, NULL, &set); | ||
58 | - sigdelset(&set, SIG_IPI); | ||
59 | + pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); | ||
60 | + sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); | ||
61 | |||
62 | #ifdef __aarch64__ | ||
63 | r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); | ||
64 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/hvf/hvf.c | ||
67 | +++ b/target/arm/hvf/hvf.c | ||
35 | @@ -XXX,XX +XXX,XX @@ | 68 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 69 | * QEMU Hypervisor.framework support for Apple Silicon |
37 | + * ARM IoT Kit | 70 | |
38 | + * | 71 | * Copyright 2020 Alexander Graf <agraf@csgraf.de> |
39 | + * Copyright (c) 2018 Linaro Limited | 72 | + * Copyright 2020 Google LLC |
40 | + * Written by Peter Maydell | 73 | * |
41 | + * | 74 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
42 | + * This program is free software; you can redistribute it and/or modify | 75 | * See the COPYING file in the top-level directory. |
43 | + * it under the terms of the GNU General Public License version 2 or | 76 | @@ -XXX,XX +XXX,XX @@ int hvf_arch_init_vcpu(CPUState *cpu) |
44 | + * (at your option) any later version. | 77 | |
45 | + */ | 78 | void hvf_kick_vcpu_thread(CPUState *cpu) |
79 | { | ||
80 | + cpus_kick_thread(cpu); | ||
81 | hv_vcpus_exit(&cpu->hvf->fd, 1); | ||
82 | } | ||
83 | |||
84 | @@ -XXX,XX +XXX,XX @@ static uint64_t hvf_vtimer_val_raw(void) | ||
85 | return mach_absolute_time() - hvf_state->vtimer_offset; | ||
86 | } | ||
87 | |||
88 | +static uint64_t hvf_vtimer_val(void) | ||
89 | +{ | ||
90 | + if (!runstate_is_running()) { | ||
91 | + /* VM is paused, the vtimer value is in vtimer.vtimer_val */ | ||
92 | + return vtimer.vtimer_val; | ||
93 | + } | ||
46 | + | 94 | + |
47 | +/* This is a model of the Arm IoT Kit which is documented in | 95 | + return hvf_vtimer_val_raw(); |
48 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
49 | + * It contains: | ||
50 | + * a Cortex-M33 | ||
51 | + * the IDAU | ||
52 | + * some timers and watchdogs | ||
53 | + * two peripheral protection controllers | ||
54 | + * a memory protection controller | ||
55 | + * a security controller | ||
56 | + * a bus fabric which arranges that some parts of the address | ||
57 | + * space are secure and non-secure aliases of each other | ||
58 | + * | ||
59 | + * QEMU interface: | ||
60 | + * + QOM property "memory" is a MemoryRegion containing the devices provided | ||
61 | + * by the board model. | ||
62 | + * + QOM property "MAINCLK" is the frequency of the main system clock | ||
63 | + * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts | ||
64 | + * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which | ||
65 | + * are wired to the NVIC lines 32 .. n+32 | ||
66 | + * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit | ||
67 | + * might provide: | ||
68 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
69 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
70 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
71 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
72 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
73 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
74 | + * might provide: | ||
75 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
76 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
77 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
78 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
79 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
80 | + */ | ||
81 | + | ||
82 | +#ifndef IOTKIT_H | ||
83 | +#define IOTKIT_H | ||
84 | + | ||
85 | +#include "hw/sysbus.h" | ||
86 | +#include "hw/arm/armv7m.h" | ||
87 | +#include "hw/misc/iotkit-secctl.h" | ||
88 | +#include "hw/misc/tz-ppc.h" | ||
89 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
90 | +#include "hw/misc/unimp.h" | ||
91 | +#include "hw/or-irq.h" | ||
92 | +#include "hw/core/split-irq.h" | ||
93 | + | ||
94 | +#define TYPE_IOTKIT "iotkit" | ||
95 | +#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) | ||
96 | + | ||
97 | +/* We have an IRQ splitter and an OR gate input for each external PPC | ||
98 | + * and the 2 internal PPCs | ||
99 | + */ | ||
100 | +#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) | ||
101 | +#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) | ||
102 | + | ||
103 | +typedef struct IoTKit { | ||
104 | + /*< private >*/ | ||
105 | + SysBusDevice parent_obj; | ||
106 | + | ||
107 | + /*< public >*/ | ||
108 | + ARMv7MState armv7m; | ||
109 | + IoTKitSecCtl secctl; | ||
110 | + TZPPC apb_ppc0; | ||
111 | + TZPPC apb_ppc1; | ||
112 | + CMSDKAPBTIMER timer0; | ||
113 | + CMSDKAPBTIMER timer1; | ||
114 | + qemu_or_irq ppc_irq_orgate; | ||
115 | + SplitIRQ sec_resp_splitter; | ||
116 | + SplitIRQ ppc_irq_splitter[NUM_PPCS]; | ||
117 | + | ||
118 | + UnimplementedDeviceState dualtimer; | ||
119 | + UnimplementedDeviceState s32ktimer; | ||
120 | + | ||
121 | + MemoryRegion container; | ||
122 | + MemoryRegion alias1; | ||
123 | + MemoryRegion alias2; | ||
124 | + MemoryRegion alias3; | ||
125 | + MemoryRegion sram0; | ||
126 | + | ||
127 | + qemu_irq *exp_irqs; | ||
128 | + qemu_irq ppc0_irq; | ||
129 | + qemu_irq ppc1_irq; | ||
130 | + qemu_irq sec_resp_cfg; | ||
131 | + qemu_irq sec_resp_cfg_in; | ||
132 | + qemu_irq nsc_cfg_in; | ||
133 | + | ||
134 | + qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; | ||
135 | + | ||
136 | + uint32_t nsccfg; | ||
137 | + | ||
138 | + /* Properties */ | ||
139 | + MemoryRegion *board_memory; | ||
140 | + uint32_t exp_numirq; | ||
141 | + uint32_t mainclk_frq; | ||
142 | +} IoTKit; | ||
143 | + | ||
144 | +#endif | ||
145 | diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c | ||
146 | new file mode 100644 | ||
147 | index XXXXXXX..XXXXXXX | ||
148 | --- /dev/null | ||
149 | +++ b/hw/arm/iotkit.c | ||
150 | @@ -XXX,XX +XXX,XX @@ | ||
151 | +/* | ||
152 | + * Arm IoT Kit | ||
153 | + * | ||
154 | + * Copyright (c) 2018 Linaro Limited | ||
155 | + * Written by Peter Maydell | ||
156 | + * | ||
157 | + * This program is free software; you can redistribute it and/or modify | ||
158 | + * it under the terms of the GNU General Public License version 2 or | ||
159 | + * (at your option) any later version. | ||
160 | + */ | ||
161 | + | ||
162 | +#include "qemu/osdep.h" | ||
163 | +#include "qemu/log.h" | ||
164 | +#include "qapi/error.h" | ||
165 | +#include "trace.h" | ||
166 | +#include "hw/sysbus.h" | ||
167 | +#include "hw/registerfields.h" | ||
168 | +#include "hw/arm/iotkit.h" | ||
169 | +#include "hw/misc/unimp.h" | ||
170 | +#include "hw/arm/arm.h" | ||
171 | + | ||
172 | +/* Create an alias region of @size bytes starting at @base | ||
173 | + * which mirrors the memory starting at @orig. | ||
174 | + */ | ||
175 | +static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, | ||
176 | + hwaddr base, hwaddr size, hwaddr orig) | ||
177 | +{ | ||
178 | + memory_region_init_alias(mr, NULL, name, &s->container, orig, size); | ||
179 | + /* The alias is even lower priority than unimplemented_device regions */ | ||
180 | + memory_region_add_subregion_overlap(&s->container, base, mr, -1500); | ||
181 | +} | 96 | +} |
182 | + | 97 | + |
183 | +static void init_sysbus_child(Object *parent, const char *childname, | 98 | +static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) |
184 | + void *child, size_t childsize, | ||
185 | + const char *childtype) | ||
186 | +{ | 99 | +{ |
187 | + object_initialize(child, childsize, childtype); | 100 | + /* |
188 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | 101 | + * Use pselect to sleep so that other threads can IPI us while we're |
189 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | 102 | + * sleeping. |
103 | + */ | ||
104 | + qatomic_mb_set(&cpu->thread_kicked, false); | ||
105 | + qemu_mutex_unlock_iothread(); | ||
106 | + pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); | ||
107 | + qemu_mutex_lock_iothread(); | ||
190 | +} | 108 | +} |
191 | + | 109 | + |
192 | +static void irq_status_forwarder(void *opaque, int n, int level) | 110 | +static void hvf_wfi(CPUState *cpu) |
193 | +{ | 111 | +{ |
194 | + qemu_irq destirq = opaque; | 112 | + ARMCPU *arm_cpu = ARM_CPU(cpu); |
113 | + struct timespec ts; | ||
114 | + hv_return_t r; | ||
115 | + uint64_t ctl; | ||
116 | + uint64_t cval; | ||
117 | + int64_t ticks_to_sleep; | ||
118 | + uint64_t seconds; | ||
119 | + uint64_t nanos; | ||
120 | + uint32_t cntfrq; | ||
195 | + | 121 | + |
196 | + qemu_set_irq(destirq, level); | 122 | + if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { |
197 | +} | 123 | + /* Interrupt pending, no need to wait */ |
198 | + | ||
199 | +static void nsccfg_handler(void *opaque, int n, int level) | ||
200 | +{ | ||
201 | + IoTKit *s = IOTKIT(opaque); | ||
202 | + | ||
203 | + s->nsccfg = level; | ||
204 | +} | ||
205 | + | ||
206 | +static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) | ||
207 | +{ | ||
208 | + /* Each of the 4 AHB and 4 APB PPCs that might be present in a | ||
209 | + * system using the IoTKit has a collection of control lines which | ||
210 | + * are provided by the security controller and which we want to | ||
211 | + * expose as control lines on the IoTKit device itself, so the | ||
212 | + * code using the IoTKit can wire them up to the PPCs. | ||
213 | + */ | ||
214 | + SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; | ||
215 | + DeviceState *iotkitdev = DEVICE(s); | ||
216 | + DeviceState *dev_secctl = DEVICE(&s->secctl); | ||
217 | + DeviceState *dev_splitter = DEVICE(splitter); | ||
218 | + char *name; | ||
219 | + | ||
220 | + name = g_strdup_printf("%s_nonsec", ppcname); | ||
221 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
222 | + g_free(name); | ||
223 | + name = g_strdup_printf("%s_ap", ppcname); | ||
224 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
225 | + g_free(name); | ||
226 | + name = g_strdup_printf("%s_irq_enable", ppcname); | ||
227 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
228 | + g_free(name); | ||
229 | + name = g_strdup_printf("%s_irq_clear", ppcname); | ||
230 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
231 | + g_free(name); | ||
232 | + | ||
233 | + /* irq_status is a little more tricky, because we need to | ||
234 | + * split it so we can send it both to the security controller | ||
235 | + * and to our OR gate for the NVIC interrupt line. | ||
236 | + * Connect up the splitter's outputs, and create a GPIO input | ||
237 | + * which will pass the line state to the input splitter. | ||
238 | + */ | ||
239 | + name = g_strdup_printf("%s_irq_status", ppcname); | ||
240 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
241 | + qdev_get_gpio_in_named(dev_secctl, | ||
242 | + name, 0)); | ||
243 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
244 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); | ||
245 | + s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); | ||
246 | + qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, | ||
247 | + s->irq_status_in[ppcnum], name, 1); | ||
248 | + g_free(name); | ||
249 | +} | ||
250 | + | ||
251 | +static void iotkit_forward_sec_resp_cfg(IoTKit *s) | ||
252 | +{ | ||
253 | + /* Forward the 3rd output from the splitter device as a | ||
254 | + * named GPIO output of the iotkit object. | ||
255 | + */ | ||
256 | + DeviceState *dev = DEVICE(s); | ||
257 | + DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
258 | + | ||
259 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
260 | + s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, | ||
261 | + s->sec_resp_cfg, 1); | ||
262 | + qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); | ||
263 | +} | ||
264 | + | ||
265 | +static void iotkit_init(Object *obj) | ||
266 | +{ | ||
267 | + IoTKit *s = IOTKIT(obj); | ||
268 | + int i; | ||
269 | + | ||
270 | + memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); | ||
271 | + | ||
272 | + init_sysbus_child(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), | ||
273 | + TYPE_ARMV7M); | ||
274 | + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", | ||
275 | + ARM_CPU_TYPE_NAME("cortex-m33")); | ||
276 | + | ||
277 | + init_sysbus_child(obj, "secctl", &s->secctl, sizeof(s->secctl), | ||
278 | + TYPE_IOTKIT_SECCTL); | ||
279 | + init_sysbus_child(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), | ||
280 | + TYPE_TZ_PPC); | ||
281 | + init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), | ||
282 | + TYPE_TZ_PPC); | ||
283 | + init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0), | ||
284 | + TYPE_CMSDK_APB_TIMER); | ||
285 | + init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1), | ||
286 | + TYPE_CMSDK_APB_TIMER); | ||
287 | + init_sysbus_child(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), | ||
288 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
289 | + object_initialize(&s->ppc_irq_orgate, sizeof(s->ppc_irq_orgate), | ||
290 | + TYPE_OR_IRQ); | ||
291 | + object_property_add_child(obj, "ppc-irq-orgate", | ||
292 | + OBJECT(&s->ppc_irq_orgate), &error_abort); | ||
293 | + object_initialize(&s->sec_resp_splitter, sizeof(s->sec_resp_splitter), | ||
294 | + TYPE_SPLIT_IRQ); | ||
295 | + object_property_add_child(obj, "sec-resp-splitter", | ||
296 | + OBJECT(&s->sec_resp_splitter), &error_abort); | ||
297 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
298 | + char *name = g_strdup_printf("ppc-irq-splitter-%d", i); | ||
299 | + SplitIRQ *splitter = &s->ppc_irq_splitter[i]; | ||
300 | + | ||
301 | + object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ); | ||
302 | + object_property_add_child(obj, name, OBJECT(splitter), &error_abort); | ||
303 | + } | ||
304 | + init_sysbus_child(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), | ||
305 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
306 | +} | ||
307 | + | ||
308 | +static void iotkit_exp_irq(void *opaque, int n, int level) | ||
309 | +{ | ||
310 | + IoTKit *s = IOTKIT(opaque); | ||
311 | + | ||
312 | + qemu_set_irq(s->exp_irqs[n], level); | ||
313 | +} | ||
314 | + | ||
315 | +static void iotkit_realize(DeviceState *dev, Error **errp) | ||
316 | +{ | ||
317 | + IoTKit *s = IOTKIT(dev); | ||
318 | + int i; | ||
319 | + MemoryRegion *mr; | ||
320 | + Error *err = NULL; | ||
321 | + SysBusDevice *sbd_apb_ppc0; | ||
322 | + SysBusDevice *sbd_secctl; | ||
323 | + DeviceState *dev_apb_ppc0; | ||
324 | + DeviceState *dev_apb_ppc1; | ||
325 | + DeviceState *dev_secctl; | ||
326 | + DeviceState *dev_splitter; | ||
327 | + | ||
328 | + if (!s->board_memory) { | ||
329 | + error_setg(errp, "memory property was not set"); | ||
330 | + return; | 124 | + return; |
331 | + } | 125 | + } |
332 | + | 126 | + |
333 | + if (!s->mainclk_frq) { | 127 | + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); |
334 | + error_setg(errp, "MAINCLK property was not set"); | 128 | + assert_hvf_ok(r); |
129 | + | ||
130 | + if (!(ctl & 1) || (ctl & 2)) { | ||
131 | + /* Timer disabled or masked, just wait for an IPI. */ | ||
132 | + hvf_wait_for_ipi(cpu, NULL); | ||
335 | + return; | 133 | + return; |
336 | + } | 134 | + } |
337 | + | 135 | + |
338 | + /* Handling of which devices should be available only to secure | 136 | + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); |
339 | + * code is usually done differently for M profile than for A profile. | 137 | + assert_hvf_ok(r); |
340 | + * Instead of putting some devices only into the secure address space, | ||
341 | + * devices exist in both address spaces but with hard-wired security | ||
342 | + * permissions that will cause the CPU to fault for non-secure accesses. | ||
343 | + * | ||
344 | + * The IoTKit has an IDAU (Implementation Defined Access Unit), | ||
345 | + * which specifies hard-wired security permissions for different | ||
346 | + * areas of the physical address space. For the IoTKit IDAU, the | ||
347 | + * top 4 bits of the physical address are the IDAU region ID, and | ||
348 | + * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS | ||
349 | + * region, otherwise it is an S region. | ||
350 | + * | ||
351 | + * The various devices and RAMs are generally all mapped twice, | ||
352 | + * once into a region that the IDAU defines as secure and once | ||
353 | + * into a non-secure region. They sit behind either a Memory | ||
354 | + * Protection Controller (for RAM) or a Peripheral Protection | ||
355 | + * Controller (for devices), which allow a more fine grained | ||
356 | + * configuration of whether non-secure accesses are permitted. | ||
357 | + * | ||
358 | + * (The other place that guest software can configure security | ||
359 | + * permissions is in the architected SAU (Security Attribution | ||
360 | + * Unit), which is entirely inside the CPU. The IDAU can upgrade | ||
361 | + * the security attributes for a region to more restrictive than | ||
362 | + * the SAU specifies, but cannot downgrade them.) | ||
363 | + * | ||
364 | + * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff | ||
365 | + * 0x20000000..0x2007ffff 32KB FPGA block RAM | ||
366 | + * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff | ||
367 | + * 0x40000000..0x4000ffff base peripheral region 1 | ||
368 | + * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) | ||
369 | + * 0x40020000..0x4002ffff system control element peripherals | ||
370 | + * 0x40080000..0x400fffff base peripheral region 2 | ||
371 | + * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff | ||
372 | + */ | ||
373 | + | 138 | + |
374 | + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | 139 | + ticks_to_sleep = cval - hvf_vtimer_val(); |
375 | + | 140 | + if (ticks_to_sleep < 0) { |
376 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32); | ||
377 | + /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 | ||
378 | + * register in the IoT Kit System Control Register block, and the | ||
379 | + * initial value of that is in turn specifiable by the FPGA that | ||
380 | + * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, | ||
381 | + * and simply set the CPU's init-svtor to the IoT Kit default value. | ||
382 | + */ | ||
383 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); | ||
384 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), | ||
385 | + "memory", &err); | ||
386 | + if (err) { | ||
387 | + error_propagate(errp, err); | ||
388 | + return; | ||
389 | + } | ||
390 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); | ||
391 | + if (err) { | ||
392 | + error_propagate(errp, err); | ||
393 | + return; | ||
394 | + } | ||
395 | + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | ||
396 | + if (err) { | ||
397 | + error_propagate(errp, err); | ||
398 | + return; | 141 | + return; |
399 | + } | 142 | + } |
400 | + | 143 | + |
401 | + /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ | 144 | + cntfrq = gt_cntfrq_period_ns(arm_cpu); |
402 | + s->exp_irqs = g_new(qemu_irq, s->exp_numirq); | 145 | + seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); |
403 | + for (i = 0; i < s->exp_numirq; i++) { | 146 | + ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); |
404 | + s->exp_irqs[i] = qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); | 147 | + nanos = ticks_to_sleep * cntfrq; |
405 | + } | ||
406 | + qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); | ||
407 | + | 148 | + |
408 | + /* Set up the big aliases first */ | 149 | + /* |
409 | + make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); | 150 | + * Don't sleep for less than the time a context switch would take, |
410 | + make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); | 151 | + * so that we can satisfy fast timer requests on the same CPU. |
411 | + /* The 0x50000000..0x5fffffff region is not a pure alias: it has | 152 | + * Measurements on M1 show the sweet spot to be ~2ms. |
412 | + * a few extra devices that only appear there (generally the | ||
413 | + * control interfaces for the protection controllers). | ||
414 | + * We implement this by mapping those devices over the top of this | ||
415 | + * alias MR at a higher priority. | ||
416 | + */ | 153 | + */ |
417 | + make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); | 154 | + if (!seconds && nanos < (2 * SCALE_MS)) { |
418 | + | ||
419 | + /* This RAM should be behind a Memory Protection Controller, but we | ||
420 | + * don't implement that yet. | ||
421 | + */ | ||
422 | + memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err); | ||
423 | + if (err) { | ||
424 | + error_propagate(errp, err); | ||
425 | + return; | ||
426 | + } | ||
427 | + memory_region_add_subregion(&s->container, 0x20000000, &s->sram0); | ||
428 | + | ||
429 | + /* Security controller */ | ||
430 | + object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); | ||
431 | + if (err) { | ||
432 | + error_propagate(errp, err); | ||
433 | + return; | ||
434 | + } | ||
435 | + sbd_secctl = SYS_BUS_DEVICE(&s->secctl); | ||
436 | + dev_secctl = DEVICE(&s->secctl); | ||
437 | + sysbus_mmio_map(sbd_secctl, 0, 0x50080000); | ||
438 | + sysbus_mmio_map(sbd_secctl, 1, 0x40080000); | ||
439 | + | ||
440 | + s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); | ||
441 | + qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); | ||
442 | + | ||
443 | + /* The sec_resp_cfg output from the security controller must be split into | ||
444 | + * multiple lines, one for each of the PPCs within the IoTKit and one | ||
445 | + * that will be an output from the IoTKit to the system. | ||
446 | + */ | ||
447 | + object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, | ||
448 | + "num-lines", &err); | ||
449 | + if (err) { | ||
450 | + error_propagate(errp, err); | ||
451 | + return; | ||
452 | + } | ||
453 | + object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, | ||
454 | + "realized", &err); | ||
455 | + if (err) { | ||
456 | + error_propagate(errp, err); | ||
457 | + return; | ||
458 | + } | ||
459 | + dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
460 | + qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, | ||
461 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
462 | + | ||
463 | + /* Devices behind APB PPC0: | ||
464 | + * 0x40000000: timer0 | ||
465 | + * 0x40001000: timer1 | ||
466 | + * 0x40002000: dual timer | ||
467 | + * We must configure and realize each downstream device and connect | ||
468 | + * it to the appropriate PPC port; then we can realize the PPC and | ||
469 | + * map its upstream ends to the right place in the container. | ||
470 | + */ | ||
471 | + qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); | ||
472 | + object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); | ||
473 | + if (err) { | ||
474 | + error_propagate(errp, err); | ||
475 | + return; | ||
476 | + } | ||
477 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, | ||
478 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
479 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); | ||
480 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); | ||
481 | + if (err) { | ||
482 | + error_propagate(errp, err); | ||
483 | + return; | 155 | + return; |
484 | + } | 156 | + } |
485 | + | 157 | + |
486 | + qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); | 158 | + ts = (struct timespec) { seconds, nanos }; |
487 | + object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); | 159 | + hvf_wait_for_ipi(cpu, &ts); |
488 | + if (err) { | ||
489 | + error_propagate(errp, err); | ||
490 | + return; | ||
491 | + } | ||
492 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, | ||
493 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
494 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); | ||
495 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); | ||
496 | + if (err) { | ||
497 | + error_propagate(errp, err); | ||
498 | + return; | ||
499 | + } | ||
500 | + | ||
501 | + qdev_prop_set_string(DEVICE(&s->dualtimer), "name", "Dual timer"); | ||
502 | + qdev_prop_set_uint64(DEVICE(&s->dualtimer), "size", 0x1000); | ||
503 | + object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); | ||
504 | + if (err) { | ||
505 | + error_propagate(errp, err); | ||
506 | + return; | ||
507 | + } | ||
508 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); | ||
509 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); | ||
510 | + if (err) { | ||
511 | + error_propagate(errp, err); | ||
512 | + return; | ||
513 | + } | ||
514 | + | ||
515 | + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); | ||
516 | + if (err) { | ||
517 | + error_propagate(errp, err); | ||
518 | + return; | ||
519 | + } | ||
520 | + | ||
521 | + sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); | ||
522 | + dev_apb_ppc0 = DEVICE(&s->apb_ppc0); | ||
523 | + | ||
524 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); | ||
525 | + memory_region_add_subregion(&s->container, 0x40000000, mr); | ||
526 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); | ||
527 | + memory_region_add_subregion(&s->container, 0x40001000, mr); | ||
528 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); | ||
529 | + memory_region_add_subregion(&s->container, 0x40002000, mr); | ||
530 | + for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { | ||
531 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, | ||
532 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
533 | + "cfg_nonsec", i)); | ||
534 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, | ||
535 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
536 | + "cfg_ap", i)); | ||
537 | + } | ||
538 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, | ||
539 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
540 | + "irq_enable", 0)); | ||
541 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, | ||
542 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
543 | + "irq_clear", 0)); | ||
544 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
545 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
546 | + "cfg_sec_resp", 0)); | ||
547 | + | ||
548 | + /* All the PPC irq lines (from the 2 internal PPCs and the 8 external | ||
549 | + * ones) are sent individually to the security controller, and also | ||
550 | + * ORed together to give a single combined PPC interrupt to the NVIC. | ||
551 | + */ | ||
552 | + object_property_set_int(OBJECT(&s->ppc_irq_orgate), | ||
553 | + NUM_PPCS, "num-lines", &err); | ||
554 | + if (err) { | ||
555 | + error_propagate(errp, err); | ||
556 | + return; | ||
557 | + } | ||
558 | + object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, | ||
559 | + "realized", &err); | ||
560 | + if (err) { | ||
561 | + error_propagate(errp, err); | ||
562 | + return; | ||
563 | + } | ||
564 | + qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, | ||
565 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); | ||
566 | + | ||
567 | + /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ | ||
568 | + | ||
569 | + /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */ | ||
570 | + /* Devices behind APB PPC1: | ||
571 | + * 0x4002f000: S32K timer | ||
572 | + */ | ||
573 | + qdev_prop_set_string(DEVICE(&s->s32ktimer), "name", "S32KTIMER"); | ||
574 | + qdev_prop_set_uint64(DEVICE(&s->s32ktimer), "size", 0x1000); | ||
575 | + object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); | ||
576 | + if (err) { | ||
577 | + error_propagate(errp, err); | ||
578 | + return; | ||
579 | + } | ||
580 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); | ||
581 | + object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); | ||
582 | + if (err) { | ||
583 | + error_propagate(errp, err); | ||
584 | + return; | ||
585 | + } | ||
586 | + | ||
587 | + object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); | ||
588 | + if (err) { | ||
589 | + error_propagate(errp, err); | ||
590 | + return; | ||
591 | + } | ||
592 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); | ||
593 | + memory_region_add_subregion(&s->container, 0x4002f000, mr); | ||
594 | + | ||
595 | + dev_apb_ppc1 = DEVICE(&s->apb_ppc1); | ||
596 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, | ||
597 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
598 | + "cfg_nonsec", 0)); | ||
599 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, | ||
600 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
601 | + "cfg_ap", 0)); | ||
602 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, | ||
603 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
604 | + "irq_enable", 0)); | ||
605 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, | ||
606 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
607 | + "irq_clear", 0)); | ||
608 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
609 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
610 | + "cfg_sec_resp", 0)); | ||
611 | + | ||
612 | + /* Using create_unimplemented_device() maps the stub into the | ||
613 | + * system address space rather than into our container, but the | ||
614 | + * overall effect to the guest is the same. | ||
615 | + */ | ||
616 | + create_unimplemented_device("SYSINFO", 0x40020000, 0x1000); | ||
617 | + | ||
618 | + create_unimplemented_device("SYSCONTROL", 0x50021000, 0x1000); | ||
619 | + create_unimplemented_device("S32KWATCHDOG", 0x5002e000, 0x1000); | ||
620 | + | ||
621 | + /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ | ||
622 | + | ||
623 | + create_unimplemented_device("NS watchdog", 0x40081000, 0x1000); | ||
624 | + create_unimplemented_device("S watchdog", 0x50081000, 0x1000); | ||
625 | + | ||
626 | + create_unimplemented_device("SRAM0 MPC", 0x50083000, 0x1000); | ||
627 | + | ||
628 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
629 | + Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); | ||
630 | + | ||
631 | + object_property_set_int(splitter, 2, "num-lines", &err); | ||
632 | + if (err) { | ||
633 | + error_propagate(errp, err); | ||
634 | + return; | ||
635 | + } | ||
636 | + object_property_set_bool(splitter, true, "realized", &err); | ||
637 | + if (err) { | ||
638 | + error_propagate(errp, err); | ||
639 | + return; | ||
640 | + } | ||
641 | + } | ||
642 | + | ||
643 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
644 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
645 | + | ||
646 | + iotkit_forward_ppc(s, ppcname, i); | ||
647 | + g_free(ppcname); | ||
648 | + } | ||
649 | + | ||
650 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
651 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
652 | + | ||
653 | + iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); | ||
654 | + g_free(ppcname); | ||
655 | + } | ||
656 | + | ||
657 | + for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { | ||
658 | + /* Wire up IRQ splitter for internal PPCs */ | ||
659 | + DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); | ||
660 | + char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", | ||
661 | + i - NUM_EXTERNAL_PPCS); | ||
662 | + TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; | ||
663 | + | ||
664 | + qdev_connect_gpio_out(devs, 0, | ||
665 | + qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); | ||
666 | + qdev_connect_gpio_out(devs, 1, | ||
667 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); | ||
668 | + qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, | ||
669 | + qdev_get_gpio_in(devs, 0)); | ||
670 | + } | ||
671 | + | ||
672 | + iotkit_forward_sec_resp_cfg(s); | ||
673 | + | ||
674 | + system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; | ||
675 | +} | 160 | +} |
676 | + | 161 | + |
677 | +static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, | 162 | static void hvf_sync_vtimer(CPUState *cpu) |
678 | + int *iregion, bool *exempt, bool *ns, bool *nsc) | 163 | { |
679 | +{ | 164 | ARMCPU *arm_cpu = ARM_CPU(cpu); |
680 | + /* For IoTKit systems the IDAU responses are simple logical functions | 165 | @@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu) |
681 | + * of the address bits. The NSC attribute is guest-adjustable via the | 166 | } |
682 | + * NSCCFG register in the security controller. | 167 | case EC_WFX_TRAP: |
683 | + */ | 168 | advance_pc = true; |
684 | + IoTKit *s = IOTKIT(ii); | 169 | + if (!(syndrome & WFX_IS_WFE)) { |
685 | + int region = extract32(address, 28, 4); | 170 | + hvf_wfi(cpu); |
686 | + | 171 | + } |
687 | + *ns = !(region & 1); | 172 | break; |
688 | + *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); | 173 | case EC_AA64_HVC: |
689 | + /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | 174 | cpu_synchronize_state(cpu); |
690 | + *exempt = (address & 0xeff00000) == 0xe0000000; | ||
691 | + *iregion = region; | ||
692 | +} | ||
693 | + | ||
694 | +static const VMStateDescription iotkit_vmstate = { | ||
695 | + .name = "iotkit", | ||
696 | + .version_id = 1, | ||
697 | + .minimum_version_id = 1, | ||
698 | + .fields = (VMStateField[]) { | ||
699 | + VMSTATE_UINT32(nsccfg, IoTKit), | ||
700 | + VMSTATE_END_OF_LIST() | ||
701 | + } | ||
702 | +}; | ||
703 | + | ||
704 | +static Property iotkit_properties[] = { | ||
705 | + DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, | ||
706 | + MemoryRegion *), | ||
707 | + DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), | ||
708 | + DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), | ||
709 | + DEFINE_PROP_END_OF_LIST() | ||
710 | +}; | ||
711 | + | ||
712 | +static void iotkit_reset(DeviceState *dev) | ||
713 | +{ | ||
714 | + IoTKit *s = IOTKIT(dev); | ||
715 | + | ||
716 | + s->nsccfg = 0; | ||
717 | +} | ||
718 | + | ||
719 | +static void iotkit_class_init(ObjectClass *klass, void *data) | ||
720 | +{ | ||
721 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
722 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); | ||
723 | + | ||
724 | + dc->realize = iotkit_realize; | ||
725 | + dc->vmsd = &iotkit_vmstate; | ||
726 | + dc->props = iotkit_properties; | ||
727 | + dc->reset = iotkit_reset; | ||
728 | + iic->check = iotkit_idau_check; | ||
729 | +} | ||
730 | + | ||
731 | +static const TypeInfo iotkit_info = { | ||
732 | + .name = TYPE_IOTKIT, | ||
733 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
734 | + .instance_size = sizeof(IoTKit), | ||
735 | + .instance_init = iotkit_init, | ||
736 | + .class_init = iotkit_class_init, | ||
737 | + .interfaces = (InterfaceInfo[]) { | ||
738 | + { TYPE_IDAU_INTERFACE }, | ||
739 | + { } | ||
740 | + } | ||
741 | +}; | ||
742 | + | ||
743 | +static void iotkit_register_types(void) | ||
744 | +{ | ||
745 | + type_register_static(&iotkit_info); | ||
746 | +} | ||
747 | + | ||
748 | +type_init(iotkit_register_types); | ||
749 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
750 | index XXXXXXX..XXXXXXX 100644 | ||
751 | --- a/default-configs/arm-softmmu.mak | ||
752 | +++ b/default-configs/arm-softmmu.mak | ||
753 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
754 | CONFIG_MPS2_SCC=y | ||
755 | |||
756 | CONFIG_TZ_PPC=y | ||
757 | +CONFIG_IOTKIT=y | ||
758 | CONFIG_IOTKIT_SECCTL=y | ||
759 | |||
760 | CONFIG_VERSATILE_PCI=y | ||
761 | -- | 175 | -- |
762 | 2.16.2 | 176 | 2.20.1 |
763 | 177 | ||
764 | 178 | diff view generated by jsdifflib |
1 | In v8M, the Implementation Defined Attribution Unit (IDAU) is | 1 | Now that we have working system register sync, we push more target CPU |
---|---|---|---|
2 | a small piece of hardware typically implemented in the SoC | 2 | properties into the virtual machine. That might be useful in some |
3 | which provides board or SoC specific security attribution | 3 | situations, but is not the typical case that users want. |
4 | information for each address that the CPU performs MPU/SAU | 4 | |
5 | checks on. For QEMU, we model this with a QOM interface which | 5 | So let's add a -cpu host option that allows them to explicitly pass all |
6 | is implemented by the board or SoC object and connected to | 6 | CPU capabilities of their host CPU into the guest. |
7 | the CPU using a link property. | 7 | |
8 | 8 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | |
9 | This commit defines the new interface class, adds the link | 9 | Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> |
10 | property to the CPU object, and makes the SAU checking | 10 | Reviewed-by: Sergio Lopez <slp@redhat.com> |
11 | code call the IDAU interface if one is present. | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | 12 | Message-id: 20210916155404.86958-7-agraf@csgraf.de | |
13 | [PMM: drop unnecessary #include line from .h file] | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20180220180325.29818-5-peter.maydell@linaro.org | ||
16 | --- | 15 | --- |
17 | target/arm/cpu.h | 3 +++ | 16 | target/arm/cpu.h | 2 + |
18 | target/arm/idau.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++ | 17 | target/arm/hvf_arm.h | 18 +++++++++ |
19 | target/arm/cpu.c | 15 +++++++++++++ | 18 | target/arm/kvm_arm.h | 2 - |
20 | target/arm/helper.c | 28 +++++++++++++++++++++--- | 19 | target/arm/cpu.c | 13 ++++-- |
21 | 4 files changed, 104 insertions(+), 3 deletions(-) | 20 | target/arm/hvf/hvf.c | 95 ++++++++++++++++++++++++++++++++++++++++++++ |
22 | create mode 100644 target/arm/idau.h | 21 | 5 files changed, 124 insertions(+), 6 deletions(-) |
22 | create mode 100644 target/arm/hvf_arm.h | ||
23 | 23 | ||
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
25 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpu.h | 26 | --- a/target/arm/cpu.h |
27 | +++ b/target/arm/cpu.h | 27 | +++ b/target/arm/cpu.h |
28 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 28 | @@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); |
29 | /* MemoryRegion to use for secure physical accesses */ | 29 | #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) |
30 | MemoryRegion *secure_memory; | 30 | #define CPU_RESOLVING_TYPE TYPE_ARM_CPU |
31 | 31 | ||
32 | + /* For v8M, pointer to the IDAU interface provided by board/SoC */ | 32 | +#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU |
33 | + Object *idau; | 33 | + |
34 | + | 34 | #define cpu_signal_handler cpu_arm_signal_handler |
35 | /* 'compatible' string for this CPU for Linux device trees */ | 35 | #define cpu_list arm_cpu_list |
36 | const char *dtb_compatible; | 36 | |
37 | 37 | diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h | |
38 | diff --git a/target/arm/idau.h b/target/arm/idau.h | ||
39 | new file mode 100644 | 38 | new file mode 100644 |
40 | index XXXXXXX..XXXXXXX | 39 | index XXXXXXX..XXXXXXX |
41 | --- /dev/null | 40 | --- /dev/null |
42 | +++ b/target/arm/idau.h | 41 | +++ b/target/arm/hvf_arm.h |
43 | @@ -XXX,XX +XXX,XX @@ | 42 | @@ -XXX,XX +XXX,XX @@ |
44 | +/* | 43 | +/* |
45 | + * QEMU ARM CPU -- interface for the Arm v8M IDAU | 44 | + * QEMU Hypervisor.framework (HVF) support -- ARM specifics |
46 | + * | 45 | + * |
47 | + * Copyright (c) 2018 Linaro Ltd | 46 | + * Copyright (c) 2021 Alexander Graf |
48 | + * | 47 | + * |
49 | + * This program is free software; you can redistribute it and/or | 48 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
50 | + * modify it under the terms of the GNU General Public License | 49 | + * See the COPYING file in the top-level directory. |
51 | + * as published by the Free Software Foundation; either version 2 | ||
52 | + * of the License, or (at your option) any later version. | ||
53 | + * | 50 | + * |
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program; if not, see | ||
61 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
62 | + * | ||
63 | + * In the v8M architecture, the IDAU is a small piece of hardware | ||
64 | + * typically implemented in the SoC which provides board or SoC | ||
65 | + * specific security attribution information for each address that | ||
66 | + * the CPU performs MPU/SAU checks on. For QEMU, we model this with a | ||
67 | + * QOM interface which is implemented by the board or SoC object and | ||
68 | + * connected to the CPU using a link property. | ||
69 | + */ | 51 | + */ |
70 | + | 52 | + |
71 | +#ifndef TARGET_ARM_IDAU_H | 53 | +#ifndef QEMU_HVF_ARM_H |
72 | +#define TARGET_ARM_IDAU_H | 54 | +#define QEMU_HVF_ARM_H |
73 | + | 55 | + |
74 | +#include "qom/object.h" | 56 | +#include "cpu.h" |
75 | + | 57 | + |
76 | +#define TYPE_IDAU_INTERFACE "idau-interface" | 58 | +void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); |
77 | +#define IDAU_INTERFACE(obj) \ | ||
78 | + INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE) | ||
79 | +#define IDAU_INTERFACE_CLASS(class) \ | ||
80 | + OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE) | ||
81 | +#define IDAU_INTERFACE_GET_CLASS(obj) \ | ||
82 | + OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE) | ||
83 | + | ||
84 | +typedef struct IDAUInterface { | ||
85 | + Object parent; | ||
86 | +} IDAUInterface; | ||
87 | + | ||
88 | +#define IREGION_NOTVALID -1 | ||
89 | + | ||
90 | +typedef struct IDAUInterfaceClass { | ||
91 | + InterfaceClass parent; | ||
92 | + | ||
93 | + /* Check the specified address and return the IDAU security information | ||
94 | + * for it by filling in iregion, exempt, ns and nsc: | ||
95 | + * iregion: IDAU region number, or IREGION_NOTVALID if not valid | ||
96 | + * exempt: true if address is exempt from security attribution | ||
97 | + * ns: true if the address is NonSecure | ||
98 | + * nsc: true if the address is NonSecure-callable | ||
99 | + */ | ||
100 | + void (*check)(IDAUInterface *ii, uint32_t address, int *iregion, | ||
101 | + bool *exempt, bool *ns, bool *nsc); | ||
102 | +} IDAUInterfaceClass; | ||
103 | + | 59 | + |
104 | +#endif | 60 | +#endif |
61 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/kvm_arm.h | ||
64 | +++ b/target/arm/kvm_arm.h | ||
65 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, | ||
66 | */ | ||
67 | void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); | ||
68 | |||
69 | -#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU | ||
70 | - | ||
71 | /** | ||
72 | * ARMHostCPUFeatures: information about the host CPU (identified | ||
73 | * by asking the host kernel) | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 74 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
106 | index XXXXXXX..XXXXXXX 100644 | 75 | index XXXXXXX..XXXXXXX 100644 |
107 | --- a/target/arm/cpu.c | 76 | --- a/target/arm/cpu.c |
108 | +++ b/target/arm/cpu.c | 77 | +++ b/target/arm/cpu.c |
109 | @@ -XXX,XX +XXX,XX @@ | 78 | @@ -XXX,XX +XXX,XX @@ |
110 | */ | 79 | #include "sysemu/tcg.h" |
111 | 80 | #include "sysemu/hw_accel.h" | |
112 | #include "qemu/osdep.h" | 81 | #include "kvm_arm.h" |
113 | +#include "target/arm/idau.h" | 82 | +#include "hvf_arm.h" |
114 | #include "qemu/error-report.h" | 83 | #include "disas/capstone.h" |
115 | #include "qapi/error.h" | 84 | #include "fpu/softfloat.h" |
116 | #include "cpu.h" | 85 | |
117 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | 86 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
87 | * this is the first point where we can report it. | ||
88 | */ | ||
89 | if (cpu->host_cpu_probe_failed) { | ||
90 | - if (!kvm_enabled()) { | ||
91 | - error_setg(errp, "The 'host' CPU type can only be used with KVM"); | ||
92 | + if (!kvm_enabled() && !hvf_enabled()) { | ||
93 | + error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); | ||
94 | } else { | ||
95 | error_setg(errp, "Failed to retrieve host CPU features"); | ||
118 | } | 96 | } |
97 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) | ||
98 | #endif /* CONFIG_TCG */ | ||
99 | } | ||
100 | |||
101 | -#ifdef CONFIG_KVM | ||
102 | +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) | ||
103 | static void arm_host_initfn(Object *obj) | ||
104 | { | ||
105 | ARMCPU *cpu = ARM_CPU(obj); | ||
106 | |||
107 | +#ifdef CONFIG_KVM | ||
108 | kvm_arm_set_cpu_features_from_host(cpu); | ||
109 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
110 | aarch64_add_sve_properties(obj); | ||
119 | } | 111 | } |
120 | 112 | +#else | |
121 | + if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { | 113 | + hvf_arm_set_cpu_features_from_host(cpu); |
122 | + object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | 114 | +#endif |
123 | + qdev_prop_allow_set_link_before_realize, | 115 | arm_cpu_post_init(obj); |
124 | + OBJ_PROP_LINK_UNREF_ON_RELEASE, | 116 | } |
125 | + &error_abort); | 117 | |
126 | + } | 118 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void) |
127 | + | ||
128 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
129 | &error_abort); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { | ||
132 | .class_init = arm_cpu_class_init, | ||
133 | }; | ||
134 | |||
135 | +static const TypeInfo idau_interface_type_info = { | ||
136 | + .name = TYPE_IDAU_INTERFACE, | ||
137 | + .parent = TYPE_INTERFACE, | ||
138 | + .class_size = sizeof(IDAUInterfaceClass), | ||
139 | +}; | ||
140 | + | ||
141 | static void arm_cpu_register_types(void) | ||
142 | { | 119 | { |
143 | const ARMCPUInfo *info = arm_cpus; | ||
144 | |||
145 | type_register_static(&arm_cpu_type_info); | 120 | type_register_static(&arm_cpu_type_info); |
146 | + type_register_static(&idau_interface_type_info); | 121 | |
147 | 122 | -#ifdef CONFIG_KVM | |
148 | while (info->name) { | 123 | +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) |
149 | cpu_register(info); | 124 | type_register_static(&host_arm_cpu_type_info); |
150 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 125 | #endif |
151 | index XXXXXXX..XXXXXXX 100644 | 126 | } |
152 | --- a/target/arm/helper.c | 127 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c |
153 | +++ b/target/arm/helper.c | 128 | index XXXXXXX..XXXXXXX 100644 |
129 | --- a/target/arm/hvf/hvf.c | ||
130 | +++ b/target/arm/hvf/hvf.c | ||
154 | @@ -XXX,XX +XXX,XX @@ | 131 | @@ -XXX,XX +XXX,XX @@ |
155 | #include "qemu/osdep.h" | 132 | #include "sysemu/hvf.h" |
156 | +#include "target/arm/idau.h" | 133 | #include "sysemu/hvf_int.h" |
157 | #include "trace.h" | 134 | #include "sysemu/hw_accel.h" |
158 | #include "cpu.h" | 135 | +#include "hvf_arm.h" |
159 | #include "internals.h" | 136 | |
160 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 137 | #include <mach/mach_time.h> |
161 | */ | 138 | |
162 | ARMCPU *cpu = arm_env_get_cpu(env); | 139 | @@ -XXX,XX +XXX,XX @@ typedef struct HVFVTimer { |
163 | int r; | 140 | |
164 | + bool idau_exempt = false, idau_ns = true, idau_nsc = true; | 141 | static HVFVTimer vtimer; |
165 | + int idau_region = IREGION_NOTVALID; | 142 | |
166 | 143 | +typedef struct ARMHostCPUFeatures { | |
167 | - /* TODO: implement IDAU */ | 144 | + ARMISARegisters isar; |
168 | + if (cpu->idau) { | 145 | + uint64_t features; |
169 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | 146 | + uint64_t midr; |
170 | + IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | 147 | + uint32_t reset_sctlr; |
171 | + | 148 | + const char *dtb_compatible; |
172 | + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | 149 | +} ARMHostCPUFeatures; |
173 | + &idau_nsc); | 150 | + |
174 | + } | 151 | +static ARMHostCPUFeatures arm_host_cpu_features; |
175 | 152 | + | |
176 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | 153 | struct hvf_reg_match { |
177 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | 154 | int reg; |
178 | return; | 155 | uint64_t offset; |
179 | } | 156 | @@ -XXX,XX +XXX,XX @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) |
180 | 157 | return val; | |
181 | - if (v8m_is_sau_exempt(env, address, access_type)) { | 158 | } |
182 | + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { | 159 | |
183 | sattrs->ns = !regime_is_secure(env, mmu_idx); | 160 | +static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
184 | return; | 161 | +{ |
185 | } | 162 | + ARMISARegisters host_isar = {}; |
186 | 163 | + const struct isar_regs { | |
187 | + if (idau_region != IREGION_NOTVALID) { | 164 | + int reg; |
188 | + sattrs->irvalid = true; | 165 | + uint64_t *val; |
189 | + sattrs->iregion = idau_region; | 166 | + } regs[] = { |
190 | + } | 167 | + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, |
191 | + | 168 | + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, |
192 | switch (env->sau.ctrl & 3) { | 169 | + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, |
193 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | 170 | + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, |
194 | break; | 171 | + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, |
195 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 172 | + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, |
196 | } | 173 | + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, |
197 | } | 174 | + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, |
198 | 175 | + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, | |
199 | - /* TODO when we support the IDAU then it may override the result here */ | 176 | + }; |
200 | + /* The IDAU will override the SAU lookup results if it specifies | 177 | + hv_vcpu_t fd; |
201 | + * higher security than the SAU does. | 178 | + hv_return_t r = HV_SUCCESS; |
202 | + */ | 179 | + hv_vcpu_exit_t *exit; |
203 | + if (!idau_ns) { | 180 | + int i; |
204 | + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | 181 | + |
205 | + sattrs->ns = false; | 182 | + ahcf->dtb_compatible = "arm,arm-v8"; |
206 | + sattrs->nsc = idau_nsc; | 183 | + ahcf->features = (1ULL << ARM_FEATURE_V8) | |
207 | + } | 184 | + (1ULL << ARM_FEATURE_NEON) | |
185 | + (1ULL << ARM_FEATURE_AARCH64) | | ||
186 | + (1ULL << ARM_FEATURE_PMU) | | ||
187 | + (1ULL << ARM_FEATURE_GENERIC_TIMER); | ||
188 | + | ||
189 | + /* We set up a small vcpu to extract host registers */ | ||
190 | + | ||
191 | + if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { | ||
192 | + return false; | ||
193 | + } | ||
194 | + | ||
195 | + for (i = 0; i < ARRAY_SIZE(regs); i++) { | ||
196 | + r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); | ||
197 | + } | ||
198 | + r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); | ||
199 | + r |= hv_vcpu_destroy(fd); | ||
200 | + | ||
201 | + ahcf->isar = host_isar; | ||
202 | + | ||
203 | + /* | ||
204 | + * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 | ||
205 | + * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 | ||
206 | + */ | ||
207 | + ahcf->reset_sctlr = 0x30100180; | ||
208 | + /* | ||
209 | + * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, | ||
210 | + * let's disable it on boot and then allow guest software to turn it on by | ||
211 | + * setting it to 0. | ||
212 | + */ | ||
213 | + ahcf->reset_sctlr |= 0x00800000; | ||
214 | + | ||
215 | + /* Make sure we don't advertise AArch32 support for EL0/EL1 */ | ||
216 | + if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { | ||
217 | + return false; | ||
218 | + } | ||
219 | + | ||
220 | + return r == HV_SUCCESS; | ||
221 | +} | ||
222 | + | ||
223 | +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
224 | +{ | ||
225 | + if (!arm_host_cpu_features.dtb_compatible) { | ||
226 | + if (!hvf_enabled() || | ||
227 | + !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { | ||
228 | + /* | ||
229 | + * We can't report this error yet, so flag that we need to | ||
230 | + * in arm_cpu_realizefn(). | ||
231 | + */ | ||
232 | + cpu->host_cpu_probe_failed = true; | ||
233 | + return; | ||
208 | + } | 234 | + } |
209 | break; | 235 | + } |
210 | } | 236 | + |
237 | + cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; | ||
238 | + cpu->isar = arm_host_cpu_features.isar; | ||
239 | + cpu->env.features = arm_host_cpu_features.features; | ||
240 | + cpu->midr = arm_host_cpu_features.midr; | ||
241 | + cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; | ||
242 | +} | ||
243 | + | ||
244 | void hvf_arch_vcpu_destroy(CPUState *cpu) | ||
245 | { | ||
211 | } | 246 | } |
212 | -- | 247 | -- |
213 | 2.16.2 | 248 | 2.20.1 |
214 | 249 | ||
215 | 250 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | 3 | We need to handle PSCI calls. Most of the TCG code works for us, |
4 | 4 | but we can simplify it to only handle aa64 mode and we need to | |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | handle SUSPEND differently. |
6 | |||
7 | This patch takes the TCG code as template and duplicates it in HVF. | ||
8 | |||
9 | To tell the guest that we support PSCI 0.2 now, update the check in | ||
10 | arm_cpu_initfn() as well. | ||
11 | |||
12 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
13 | Reviewed-by: Sergio Lopez <slp@redhat.com> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20180228193125.20577-10-richard.henderson@linaro.org | 15 | Message-id: 20210916155404.86958-8-agraf@csgraf.de |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 17 | --- |
10 | target/arm/cpu.c | 1 + | 18 | target/arm/cpu.c | 4 +- |
11 | target/arm/cpu64.c | 1 + | 19 | target/arm/hvf/hvf.c | 141 ++++++++++++++++++++++++++++++++++-- |
12 | 2 files changed, 2 insertions(+) | 20 | target/arm/hvf/trace-events | 1 + |
21 | 3 files changed, 139 insertions(+), 7 deletions(-) | ||
13 | 22 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 23 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 25 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 26 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | 28 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
20 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 29 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
21 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 30 | |
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 31 | - if (tcg_enabled()) { |
23 | cpu->midr = 0xffffffff; | 32 | - cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ |
33 | + if (tcg_enabled() || hvf_enabled()) { | ||
34 | + cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ | ||
35 | } | ||
24 | } | 36 | } |
25 | #endif | 37 | |
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 38 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c |
27 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/cpu64.c | 40 | --- a/target/arm/hvf/hvf.c |
29 | +++ b/target/arm/cpu64.c | 41 | +++ b/target/arm/hvf/hvf.c |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 42 | @@ -XXX,XX +XXX,XX @@ |
31 | set_feature(&cpu->env, ARM_FEATURE_V8_SM4); | 43 | #include "hw/irq.h" |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 44 | #include "qemu/main-loop.h" |
33 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 45 | #include "sysemu/cpus.h" |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 46 | +#include "arm-powerctl.h" |
35 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 47 | #include "target/arm/cpu.h" |
36 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 48 | #include "target/arm/internals.h" |
37 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 49 | #include "trace/trace-target_arm_hvf.h" |
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | #define TMR_CTL_IMASK (1 << 1) | ||
52 | #define TMR_CTL_ISTATUS (1 << 2) | ||
53 | |||
54 | +static void hvf_wfi(CPUState *cpu); | ||
55 | + | ||
56 | typedef struct HVFVTimer { | ||
57 | /* Vtimer value during migration and paused state */ | ||
58 | uint64_t vtimer_val; | ||
59 | @@ -XXX,XX +XXX,XX @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp, | ||
60 | arm_cpu_do_interrupt(cpu); | ||
61 | } | ||
62 | |||
63 | +static void hvf_psci_cpu_off(ARMCPU *arm_cpu) | ||
64 | +{ | ||
65 | + int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity); | ||
66 | + assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); | ||
67 | +} | ||
68 | + | ||
69 | +/* | ||
70 | + * Handle a PSCI call. | ||
71 | + * | ||
72 | + * Returns 0 on success | ||
73 | + * -1 when the PSCI call is unknown, | ||
74 | + */ | ||
75 | +static bool hvf_handle_psci_call(CPUState *cpu) | ||
76 | +{ | ||
77 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
78 | + CPUARMState *env = &arm_cpu->env; | ||
79 | + uint64_t param[4] = { | ||
80 | + env->xregs[0], | ||
81 | + env->xregs[1], | ||
82 | + env->xregs[2], | ||
83 | + env->xregs[3] | ||
84 | + }; | ||
85 | + uint64_t context_id, mpidr; | ||
86 | + bool target_aarch64 = true; | ||
87 | + CPUState *target_cpu_state; | ||
88 | + ARMCPU *target_cpu; | ||
89 | + target_ulong entry; | ||
90 | + int target_el = 1; | ||
91 | + int32_t ret = 0; | ||
92 | + | ||
93 | + trace_hvf_psci_call(param[0], param[1], param[2], param[3], | ||
94 | + arm_cpu->mp_affinity); | ||
95 | + | ||
96 | + switch (param[0]) { | ||
97 | + case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
98 | + ret = QEMU_PSCI_0_2_RET_VERSION_0_2; | ||
99 | + break; | ||
100 | + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
101 | + ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ | ||
102 | + break; | ||
103 | + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: | ||
104 | + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | ||
105 | + mpidr = param[1]; | ||
106 | + | ||
107 | + switch (param[2]) { | ||
108 | + case 0: | ||
109 | + target_cpu_state = arm_get_cpu_by_id(mpidr); | ||
110 | + if (!target_cpu_state) { | ||
111 | + ret = QEMU_PSCI_RET_INVALID_PARAMS; | ||
112 | + break; | ||
113 | + } | ||
114 | + target_cpu = ARM_CPU(target_cpu_state); | ||
115 | + | ||
116 | + ret = target_cpu->power_state; | ||
117 | + break; | ||
118 | + default: | ||
119 | + /* Everything above affinity level 0 is always on. */ | ||
120 | + ret = 0; | ||
121 | + } | ||
122 | + break; | ||
123 | + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: | ||
124 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
125 | + /* | ||
126 | + * QEMU reset and shutdown are async requests, but PSCI | ||
127 | + * mandates that we never return from the reset/shutdown | ||
128 | + * call, so power the CPU off now so it doesn't execute | ||
129 | + * anything further. | ||
130 | + */ | ||
131 | + hvf_psci_cpu_off(arm_cpu); | ||
132 | + break; | ||
133 | + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: | ||
134 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | ||
135 | + hvf_psci_cpu_off(arm_cpu); | ||
136 | + break; | ||
137 | + case QEMU_PSCI_0_1_FN_CPU_ON: | ||
138 | + case QEMU_PSCI_0_2_FN_CPU_ON: | ||
139 | + case QEMU_PSCI_0_2_FN64_CPU_ON: | ||
140 | + mpidr = param[1]; | ||
141 | + entry = param[2]; | ||
142 | + context_id = param[3]; | ||
143 | + ret = arm_set_cpu_on(mpidr, entry, context_id, | ||
144 | + target_el, target_aarch64); | ||
145 | + break; | ||
146 | + case QEMU_PSCI_0_1_FN_CPU_OFF: | ||
147 | + case QEMU_PSCI_0_2_FN_CPU_OFF: | ||
148 | + hvf_psci_cpu_off(arm_cpu); | ||
149 | + break; | ||
150 | + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | ||
151 | + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: | ||
152 | + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: | ||
153 | + /* Affinity levels are not supported in QEMU */ | ||
154 | + if (param[1] & 0xfffe0000) { | ||
155 | + ret = QEMU_PSCI_RET_INVALID_PARAMS; | ||
156 | + break; | ||
157 | + } | ||
158 | + /* Powerdown is not supported, we always go into WFI */ | ||
159 | + env->xregs[0] = 0; | ||
160 | + hvf_wfi(cpu); | ||
161 | + break; | ||
162 | + case QEMU_PSCI_0_1_FN_MIGRATE: | ||
163 | + case QEMU_PSCI_0_2_FN_MIGRATE: | ||
164 | + ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
165 | + break; | ||
166 | + default: | ||
167 | + return false; | ||
168 | + } | ||
169 | + | ||
170 | + env->xregs[0] = ret; | ||
171 | + return true; | ||
172 | +} | ||
173 | + | ||
174 | static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) | ||
175 | { | ||
176 | ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
177 | @@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu) | ||
178 | break; | ||
179 | case EC_AA64_HVC: | ||
180 | cpu_synchronize_state(cpu); | ||
181 | - trace_hvf_unknown_hvc(env->xregs[0]); | ||
182 | - /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ | ||
183 | - env->xregs[0] = -1; | ||
184 | + if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { | ||
185 | + if (!hvf_handle_psci_call(cpu)) { | ||
186 | + trace_hvf_unknown_hvc(env->xregs[0]); | ||
187 | + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ | ||
188 | + env->xregs[0] = -1; | ||
189 | + } | ||
190 | + } else { | ||
191 | + trace_hvf_unknown_hvc(env->xregs[0]); | ||
192 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); | ||
193 | + } | ||
194 | break; | ||
195 | case EC_AA64_SMC: | ||
196 | cpu_synchronize_state(cpu); | ||
197 | - trace_hvf_unknown_smc(env->xregs[0]); | ||
198 | - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); | ||
199 | + if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { | ||
200 | + advance_pc = true; | ||
201 | + | ||
202 | + if (!hvf_handle_psci_call(cpu)) { | ||
203 | + trace_hvf_unknown_smc(env->xregs[0]); | ||
204 | + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ | ||
205 | + env->xregs[0] = -1; | ||
206 | + } | ||
207 | + } else { | ||
208 | + trace_hvf_unknown_smc(env->xregs[0]); | ||
209 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); | ||
210 | + } | ||
211 | break; | ||
212 | default: | ||
213 | cpu_synchronize_state(cpu); | ||
214 | diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events | ||
215 | index XXXXXXX..XXXXXXX 100644 | ||
216 | --- a/target/arm/hvf/trace-events | ||
217 | +++ b/target/arm/hvf/trace-events | ||
218 | @@ -XXX,XX +XXX,XX @@ hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_ | ||
219 | hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 | ||
220 | hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 | ||
221 | hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]" | ||
222 | +hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x" | ||
38 | -- | 223 | -- |
39 | 2.16.2 | 224 | 2.20.1 |
40 | 225 | ||
41 | 226 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Now that we have all logic in place that we need to handle Hypervisor.framework |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we |
5 | Message-id: 20180228193125.20577-5-richard.henderson@linaro.org | 5 | can build it. |
6 | |||
7 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
8 | Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> | ||
9 | Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> (x86 only) | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Sergio Lopez <slp@redhat.com> | ||
12 | Message-id: 20210916155404.86958-9-agraf@csgraf.de | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 14 | --- |
8 | target/arm/Makefile.objs | 2 +- | 15 | meson.build | 7 +++++++ |
9 | target/arm/helper.h | 4 ++ | 16 | target/arm/hvf/meson.build | 3 +++ |
10 | target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++ | 17 | target/arm/meson.build | 2 ++ |
11 | target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ | 18 | 3 files changed, 12 insertions(+) |
12 | 4 files changed, 198 insertions(+), 1 deletion(-) | 19 | create mode 100644 target/arm/hvf/meson.build |
13 | create mode 100644 target/arm/vec_helper.c | ||
14 | 20 | ||
15 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | 21 | diff --git a/meson.build b/meson.build |
16 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/Makefile.objs | 23 | --- a/meson.build |
18 | +++ b/target/arm/Makefile.objs | 24 | +++ b/meson.build |
19 | @@ -XXX,XX +XXX,XX @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o | 25 | @@ -XXX,XX +XXX,XX @@ else |
20 | obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o | 26 | endif |
21 | obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o | 27 | |
22 | obj-y += translate.o op_helper.o helper.o cpu.o | 28 | accelerator_targets = { 'CONFIG_KVM': kvm_targets } |
23 | -obj-y += neon_helper.o iwmmxt_helper.o | ||
24 | +obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o | ||
25 | obj-y += gdbstub.o | ||
26 | obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o | ||
27 | obj-y += crypto_helper.o | ||
28 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/helper.h | ||
31 | +++ b/target/arm/helper.h | ||
32 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) | ||
33 | |||
34 | DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) | ||
36 | +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) | ||
37 | +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) | ||
38 | DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) | ||
39 | DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) | ||
40 | +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) | ||
41 | +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) | ||
42 | |||
43 | DEF_HELPER_1(neon_narrow_u8, i32, i64) | ||
44 | DEF_HELPER_1(neon_narrow_u16, i32, i64) | ||
45 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-a64.c | ||
48 | +++ b/target/arm/translate-a64.c | ||
49 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | ||
50 | tcg_temp_free_ptr(fpst); | ||
51 | } | ||
52 | |||
53 | +/* AdvSIMD scalar three same extra | ||
54 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
55 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
56 | + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
57 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
58 | + */ | ||
59 | +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | ||
60 | + uint32_t insn) | ||
61 | +{ | ||
62 | + int rd = extract32(insn, 0, 5); | ||
63 | + int rn = extract32(insn, 5, 5); | ||
64 | + int opcode = extract32(insn, 11, 4); | ||
65 | + int rm = extract32(insn, 16, 5); | ||
66 | + int size = extract32(insn, 22, 2); | ||
67 | + bool u = extract32(insn, 29, 1); | ||
68 | + TCGv_i32 ele1, ele2, ele3; | ||
69 | + TCGv_i64 res; | ||
70 | + int feature; | ||
71 | + | 29 | + |
72 | + switch (u * 16 + opcode) { | 30 | +if cpu in ['aarch64'] |
73 | + case 0x10: /* SQRDMLAH (vector) */ | 31 | + accelerator_targets += { |
74 | + case 0x11: /* SQRDMLSH (vector) */ | 32 | + 'CONFIG_HVF': ['aarch64-softmmu'] |
75 | + if (size != 1 && size != 2) { | 33 | + } |
76 | + unallocated_encoding(s); | 34 | +endif |
77 | + return; | ||
78 | + } | ||
79 | + feature = ARM_FEATURE_V8_RDM; | ||
80 | + break; | ||
81 | + default: | ||
82 | + unallocated_encoding(s); | ||
83 | + return; | ||
84 | + } | ||
85 | + if (!arm_dc_feature(s, feature)) { | ||
86 | + unallocated_encoding(s); | ||
87 | + return; | ||
88 | + } | ||
89 | + if (!fp_access_check(s)) { | ||
90 | + return; | ||
91 | + } | ||
92 | + | 35 | + |
93 | + /* Do a single operation on the lowest element in the vector. | 36 | if cpu in ['x86', 'x86_64', 'arm', 'aarch64'] |
94 | + * We use the standard Neon helpers and rely on 0 OP 0 == 0 | 37 | # i386 emulator provides xenpv machine type for multiple architectures |
95 | + * with no side effects for all these operations. | 38 | accelerator_targets += { |
96 | + * OPTME: special-purpose helpers would avoid doing some | 39 | diff --git a/target/arm/hvf/meson.build b/target/arm/hvf/meson.build |
97 | + * unnecessary work in the helper for the 16 bit cases. | ||
98 | + */ | ||
99 | + ele1 = tcg_temp_new_i32(); | ||
100 | + ele2 = tcg_temp_new_i32(); | ||
101 | + ele3 = tcg_temp_new_i32(); | ||
102 | + | ||
103 | + read_vec_element_i32(s, ele1, rn, 0, size); | ||
104 | + read_vec_element_i32(s, ele2, rm, 0, size); | ||
105 | + read_vec_element_i32(s, ele3, rd, 0, size); | ||
106 | + | ||
107 | + switch (opcode) { | ||
108 | + case 0x0: /* SQRDMLAH */ | ||
109 | + if (size == 1) { | ||
110 | + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
111 | + } else { | ||
112 | + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
113 | + } | ||
114 | + break; | ||
115 | + case 0x1: /* SQRDMLSH */ | ||
116 | + if (size == 1) { | ||
117 | + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
118 | + } else { | ||
119 | + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
120 | + } | ||
121 | + break; | ||
122 | + default: | ||
123 | + g_assert_not_reached(); | ||
124 | + } | ||
125 | + tcg_temp_free_i32(ele1); | ||
126 | + tcg_temp_free_i32(ele2); | ||
127 | + | ||
128 | + res = tcg_temp_new_i64(); | ||
129 | + tcg_gen_extu_i32_i64(res, ele3); | ||
130 | + tcg_temp_free_i32(ele3); | ||
131 | + | ||
132 | + write_fp_dreg(s, rd, res); | ||
133 | + tcg_temp_free_i64(res); | ||
134 | +} | ||
135 | + | ||
136 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, | ||
137 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, | ||
138 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | ||
139 | @@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = { | ||
140 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | ||
141 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | ||
142 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | ||
143 | + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, | ||
144 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | ||
145 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | ||
146 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | ||
147 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
148 | new file mode 100644 | 40 | new file mode 100644 |
149 | index XXXXXXX..XXXXXXX | 41 | index XXXXXXX..XXXXXXX |
150 | --- /dev/null | 42 | --- /dev/null |
151 | +++ b/target/arm/vec_helper.c | 43 | +++ b/target/arm/hvf/meson.build |
152 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ |
153 | +/* | 45 | +arm_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( |
154 | + * ARM AdvSIMD / SVE Vector Operations | 46 | + 'hvf.c', |
155 | + * | 47 | +)) |
156 | + * Copyright (c) 2018 Linaro | 48 | diff --git a/target/arm/meson.build b/target/arm/meson.build |
157 | + * | 49 | index XXXXXXX..XXXXXXX 100644 |
158 | + * This library is free software; you can redistribute it and/or | 50 | --- a/target/arm/meson.build |
159 | + * modify it under the terms of the GNU Lesser General Public | 51 | +++ b/target/arm/meson.build |
160 | + * License as published by the Free Software Foundation; either | 52 | @@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files( |
161 | + * version 2 of the License, or (at your option) any later version. | 53 | 'psci.c', |
162 | + * | 54 | )) |
163 | + * This library is distributed in the hope that it will be useful, | 55 | |
164 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 56 | +subdir('hvf') |
165 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
166 | + * Lesser General Public License for more details. | ||
167 | + * | ||
168 | + * You should have received a copy of the GNU Lesser General Public | ||
169 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
170 | + */ | ||
171 | + | 57 | + |
172 | +#include "qemu/osdep.h" | 58 | target_arch += {'arm': arm_ss} |
173 | +#include "cpu.h" | 59 | target_softmmu_arch += {'arm': arm_softmmu_ss} |
174 | +#include "exec/exec-all.h" | ||
175 | +#include "exec/helper-proto.h" | ||
176 | +#include "tcg/tcg-gvec-desc.h" | ||
177 | + | ||
178 | + | ||
179 | +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
180 | + | ||
181 | +/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
182 | +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
183 | + int16_t src2, int16_t src3) | ||
184 | +{ | ||
185 | + /* Simplify: | ||
186 | + * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
187 | + * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 | ||
188 | + */ | ||
189 | + int32_t ret = (int32_t)src1 * src2; | ||
190 | + ret = ((int32_t)src3 << 15) + ret + (1 << 14); | ||
191 | + ret >>= 15; | ||
192 | + if (ret != (int16_t)ret) { | ||
193 | + SET_QC(); | ||
194 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
195 | + } | ||
196 | + return ret; | ||
197 | +} | ||
198 | + | ||
199 | +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
200 | + uint32_t src2, uint32_t src3) | ||
201 | +{ | ||
202 | + uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3); | ||
203 | + uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
204 | + return deposit32(e1, 16, 16, e2); | ||
205 | +} | ||
206 | + | ||
207 | +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | ||
208 | +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | ||
209 | + int16_t src2, int16_t src3) | ||
210 | +{ | ||
211 | + /* Similarly, using subtraction: | ||
212 | + * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
213 | + * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 | ||
214 | + */ | ||
215 | + int32_t ret = (int32_t)src1 * src2; | ||
216 | + ret = ((int32_t)src3 << 15) - ret + (1 << 14); | ||
217 | + ret >>= 15; | ||
218 | + if (ret != (int16_t)ret) { | ||
219 | + SET_QC(); | ||
220 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
221 | + } | ||
222 | + return ret; | ||
223 | +} | ||
224 | + | ||
225 | +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
226 | + uint32_t src2, uint32_t src3) | ||
227 | +{ | ||
228 | + uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3); | ||
229 | + uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
230 | + return deposit32(e1, 16, 16, e2); | ||
231 | +} | ||
232 | + | ||
233 | +/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
234 | +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
235 | + int32_t src2, int32_t src3) | ||
236 | +{ | ||
237 | + /* Simplify similarly to int_qrdmlah_s16 above. */ | ||
238 | + int64_t ret = (int64_t)src1 * src2; | ||
239 | + ret = ((int64_t)src3 << 31) + ret + (1 << 30); | ||
240 | + ret >>= 31; | ||
241 | + if (ret != (int32_t)ret) { | ||
242 | + SET_QC(); | ||
243 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
244 | + } | ||
245 | + return ret; | ||
246 | +} | ||
247 | + | ||
248 | +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
249 | +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
250 | + int32_t src2, int32_t src3) | ||
251 | +{ | ||
252 | + /* Simplify similarly to int_qrdmlsh_s16 above. */ | ||
253 | + int64_t ret = (int64_t)src1 * src2; | ||
254 | + ret = ((int64_t)src3 << 31) - ret + (1 << 30); | ||
255 | + ret >>= 31; | ||
256 | + if (ret != (int32_t)ret) { | ||
257 | + SET_QC(); | ||
258 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
259 | + } | ||
260 | + return ret; | ||
261 | +} | ||
262 | -- | 60 | -- |
263 | 2.16.2 | 61 | 2.20.1 |
264 | 62 | ||
265 | 63 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | We can expose cycle counters on the PMU easily. To be as compatible as |
4 | possible, let's do so, but make sure we don't expose any other architectural | ||
5 | counters that we can not model yet. | ||
6 | |||
7 | This allows OSs to work that require PMU support. | ||
8 | |||
9 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20180228193125.20577-14-richard.henderson@linaro.org | 11 | Message-id: 20210916155404.86958-10-agraf@csgraf.de |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 14 | target/arm/hvf/hvf.c | 179 +++++++++++++++++++++++++++++++++++++++++++ |
9 | 1 file changed, 68 insertions(+) | 15 | 1 file changed, 179 insertions(+) |
10 | 16 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 17 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c |
12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 19 | --- a/target/arm/hvf/hvf.c |
14 | +++ b/target/arm/translate.c | 20 | +++ b/target/arm/hvf/hvf.c |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 21 | @@ -XXX,XX +XXX,XX @@ |
22 | #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) | ||
23 | #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) | ||
24 | #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) | ||
25 | +#define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) | ||
26 | +#define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) | ||
27 | +#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) | ||
28 | +#define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) | ||
29 | +#define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) | ||
30 | +#define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) | ||
31 | +#define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) | ||
32 | +#define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) | ||
33 | +#define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) | ||
34 | +#define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) | ||
35 | +#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) | ||
36 | +#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) | ||
37 | |||
38 | #define WFX_IS_WFE (1 << 0) | ||
39 | |||
40 | @@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) | ||
41 | val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / | ||
42 | gt_cntfrq_period_ns(arm_cpu); | ||
43 | break; | ||
44 | + case SYSREG_PMCR_EL0: | ||
45 | + val = env->cp15.c9_pmcr; | ||
46 | + break; | ||
47 | + case SYSREG_PMCCNTR_EL0: | ||
48 | + pmu_op_start(env); | ||
49 | + val = env->cp15.c15_ccnt; | ||
50 | + pmu_op_finish(env); | ||
51 | + break; | ||
52 | + case SYSREG_PMCNTENCLR_EL0: | ||
53 | + val = env->cp15.c9_pmcnten; | ||
54 | + break; | ||
55 | + case SYSREG_PMOVSCLR_EL0: | ||
56 | + val = env->cp15.c9_pmovsr; | ||
57 | + break; | ||
58 | + case SYSREG_PMSELR_EL0: | ||
59 | + val = env->cp15.c9_pmselr; | ||
60 | + break; | ||
61 | + case SYSREG_PMINTENCLR_EL1: | ||
62 | + val = env->cp15.c9_pminten; | ||
63 | + break; | ||
64 | + case SYSREG_PMCCFILTR_EL0: | ||
65 | + val = env->cp15.pmccfiltr_el0; | ||
66 | + break; | ||
67 | + case SYSREG_PMCNTENSET_EL0: | ||
68 | + val = env->cp15.c9_pmcnten; | ||
69 | + break; | ||
70 | + case SYSREG_PMUSERENR_EL0: | ||
71 | + val = env->cp15.c9_pmuserenr; | ||
72 | + break; | ||
73 | + case SYSREG_PMCEID0_EL0: | ||
74 | + case SYSREG_PMCEID1_EL0: | ||
75 | + /* We can't really count anything yet, declare all events invalid */ | ||
76 | + val = 0; | ||
77 | + break; | ||
78 | case SYSREG_OSLSR_EL1: | ||
79 | val = env->cp15.oslsr_el1; | ||
80 | break; | ||
81 | @@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) | ||
16 | return 0; | 82 | return 0; |
17 | } | 83 | } |
18 | 84 | ||
19 | +/* Advanced SIMD three registers of the same length extension. | 85 | +static void pmu_update_irq(CPUARMState *env) |
20 | + * 31 25 23 22 20 16 12 11 10 9 8 3 0 | 86 | +{ |
21 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | 87 | + ARMCPU *cpu = env_archcpu(env); |
22 | + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | 88 | + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
23 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | 89 | + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); |
90 | +} | ||
91 | + | ||
92 | +static bool pmu_event_supported(uint16_t number) | ||
93 | +{ | ||
94 | + return false; | ||
95 | +} | ||
96 | + | ||
97 | +/* Returns true if the counter (pass 31 for PMCCNTR) should count events using | ||
98 | + * the current EL, security state, and register configuration. | ||
24 | + */ | 99 | + */ |
25 | +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 100 | +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) |
26 | +{ | 101 | +{ |
27 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | 102 | + uint64_t filter; |
28 | + int rd, rn, rm, rot, size, opr_sz; | 103 | + bool enabled, filtered = true; |
29 | + TCGv_ptr fpst; | 104 | + int el = arm_current_el(env); |
30 | + bool q; | 105 | + |
31 | + | 106 | + enabled = (env->cp15.c9_pmcr & PMCRE) && |
32 | + q = extract32(insn, 6, 1); | 107 | + (env->cp15.c9_pmcnten & (1 << counter)); |
33 | + VFP_DREG_D(rd, insn); | 108 | + |
34 | + VFP_DREG_N(rn, insn); | 109 | + if (counter == 31) { |
35 | + VFP_DREG_M(rm, insn); | 110 | + filter = env->cp15.pmccfiltr_el0; |
36 | + if ((rd | rn | rm) & q) { | ||
37 | + return 1; | ||
38 | + } | ||
39 | + | ||
40 | + if ((insn & 0xfe200f10) == 0xfc200800) { | ||
41 | + /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ | ||
42 | + size = extract32(insn, 20, 1); | ||
43 | + rot = extract32(insn, 23, 2); | ||
44 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
45 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
46 | + return 1; | ||
47 | + } | ||
48 | + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | ||
49 | + } else if ((insn & 0xfea00f10) == 0xfc800800) { | ||
50 | + /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | ||
51 | + size = extract32(insn, 20, 1); | ||
52 | + rot = extract32(insn, 24, 1); | ||
53 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
54 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
55 | + return 1; | ||
56 | + } | ||
57 | + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
58 | + } else { | 111 | + } else { |
59 | + return 1; | 112 | + filter = env->cp15.c14_pmevtyper[counter]; |
60 | + } | 113 | + } |
61 | + | 114 | + |
62 | + if (s->fp_excp_el) { | 115 | + if (el == 0) { |
63 | + gen_exception_insn(s, 4, EXCP_UDEF, | 116 | + filtered = filter & PMXEVTYPER_U; |
64 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | 117 | + } else if (el == 1) { |
65 | + return 0; | 118 | + filtered = filter & PMXEVTYPER_P; |
66 | + } | 119 | + } |
67 | + if (!s->vfp_enabled) { | 120 | + |
68 | + return 1; | 121 | + if (counter != 31) { |
69 | + } | 122 | + /* |
70 | + | 123 | + * If not checking PMCCNTR, ensure the counter is setup to an event we |
71 | + opr_sz = (1 + q) * 8; | 124 | + * support |
72 | + fpst = get_fpstatus_ptr(1); | 125 | + */ |
73 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | 126 | + uint16_t event = filter & PMXEVTYPER_EVTCOUNT; |
74 | + vfp_reg_offset(1, rn), | 127 | + if (!pmu_event_supported(event)) { |
75 | + vfp_reg_offset(1, rm), fpst, | 128 | + return false; |
76 | + opr_sz, opr_sz, rot, fn_gvec_ptr); | 129 | + } |
77 | + tcg_temp_free_ptr(fpst); | 130 | + } |
78 | + return 0; | 131 | + |
79 | +} | 132 | + return enabled && !filtered; |
80 | + | 133 | +} |
81 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 134 | + |
135 | +static void pmswinc_write(CPUARMState *env, uint64_t value) | ||
136 | +{ | ||
137 | + unsigned int i; | ||
138 | + for (i = 0; i < pmu_num_counters(env); i++) { | ||
139 | + /* Increment a counter's count iff: */ | ||
140 | + if ((value & (1 << i)) && /* counter's bit is set */ | ||
141 | + /* counter is enabled and not filtered */ | ||
142 | + pmu_counter_enabled(env, i) && | ||
143 | + /* counter is SW_INCR */ | ||
144 | + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | ||
145 | + /* | ||
146 | + * Detect if this write causes an overflow since we can't predict | ||
147 | + * PMSWINC overflows like we can for other events | ||
148 | + */ | ||
149 | + uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | ||
150 | + | ||
151 | + if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | ||
152 | + env->cp15.c9_pmovsr |= (1 << i); | ||
153 | + pmu_update_irq(env); | ||
154 | + } | ||
155 | + | ||
156 | + env->cp15.c14_pmevcntr[i] = new_pmswinc; | ||
157 | + } | ||
158 | + } | ||
159 | +} | ||
160 | + | ||
161 | static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) | ||
82 | { | 162 | { |
83 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | 163 | ARMCPU *arm_cpu = ARM_CPU(cpu); |
84 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 164 | @@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) |
85 | } | 165 | val); |
86 | } | 166 | |
87 | } | 167 | switch (reg) { |
88 | + } else if ((insn & 0x0e000a00) == 0x0c000800 | 168 | + case SYSREG_PMCCNTR_EL0: |
89 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 169 | + pmu_op_start(env); |
90 | + if (disas_neon_insn_3same_ext(s, insn)) { | 170 | + env->cp15.c15_ccnt = val; |
91 | + goto illegal_op; | 171 | + pmu_op_finish(env); |
172 | + break; | ||
173 | + case SYSREG_PMCR_EL0: | ||
174 | + pmu_op_start(env); | ||
175 | + | ||
176 | + if (val & PMCRC) { | ||
177 | + /* The counter has been reset */ | ||
178 | + env->cp15.c15_ccnt = 0; | ||
179 | + } | ||
180 | + | ||
181 | + if (val & PMCRP) { | ||
182 | + unsigned int i; | ||
183 | + for (i = 0; i < pmu_num_counters(env); i++) { | ||
184 | + env->cp15.c14_pmevcntr[i] = 0; | ||
92 | + } | 185 | + } |
93 | + return; | 186 | + } |
94 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | 187 | + |
95 | /* Coprocessor double register transfer. */ | 188 | + env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; |
96 | ARCH(5TE); | 189 | + env->cp15.c9_pmcr |= (val & PMCR_WRITEABLE_MASK); |
190 | + | ||
191 | + pmu_op_finish(env); | ||
192 | + break; | ||
193 | + case SYSREG_PMUSERENR_EL0: | ||
194 | + env->cp15.c9_pmuserenr = val & 0xf; | ||
195 | + break; | ||
196 | + case SYSREG_PMCNTENSET_EL0: | ||
197 | + env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); | ||
198 | + break; | ||
199 | + case SYSREG_PMCNTENCLR_EL0: | ||
200 | + env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); | ||
201 | + break; | ||
202 | + case SYSREG_PMINTENCLR_EL1: | ||
203 | + pmu_op_start(env); | ||
204 | + env->cp15.c9_pminten |= val; | ||
205 | + pmu_op_finish(env); | ||
206 | + break; | ||
207 | + case SYSREG_PMOVSCLR_EL0: | ||
208 | + pmu_op_start(env); | ||
209 | + env->cp15.c9_pmovsr &= ~val; | ||
210 | + pmu_op_finish(env); | ||
211 | + break; | ||
212 | + case SYSREG_PMSWINC_EL0: | ||
213 | + pmu_op_start(env); | ||
214 | + pmswinc_write(env, val); | ||
215 | + pmu_op_finish(env); | ||
216 | + break; | ||
217 | + case SYSREG_PMSELR_EL0: | ||
218 | + env->cp15.c9_pmselr = val & 0x1f; | ||
219 | + break; | ||
220 | + case SYSREG_PMCCFILTR_EL0: | ||
221 | + pmu_op_start(env); | ||
222 | + env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; | ||
223 | + pmu_op_finish(env); | ||
224 | + break; | ||
225 | case SYSREG_OSLAR_EL1: | ||
226 | env->cp15.oslsr_el1 = val & 1; | ||
227 | break; | ||
97 | -- | 228 | -- |
98 | 2.16.2 | 229 | 2.20.1 |
99 | 230 | ||
100 | 231 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Currently gen_jmp_tb() assumes that if it is called then the jump it |
---|---|---|---|
2 | is handling is the only reason that we might be trying to end the TB, | ||
3 | so it will use goto_tb if it can. This is usually the case: mostly | ||
4 | "we did something that means we must end the TB" happens on a | ||
5 | non-branch instruction. However, there are cases where we decide | ||
6 | early in handling an instruction that we need to end the TB and | ||
7 | return to the main loop, and then the insn is a complex one that | ||
8 | involves gen_jmp_tb(). For instance, for M-profile FP instructions, | ||
9 | in gen_preserve_fp_state() which is called from vfp_access_check() we | ||
10 | want to force an exit to the main loop if lazy state preservation is | ||
11 | active and we are in icount mode. | ||
2 | 12 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Make gen_jmp_tb() look at the current value of is_jmp, and only use |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY. |
5 | Message-id: 20180228193125.20577-8-richard.henderson@linaro.org | 15 | |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Message-id: 20210913095440.13462-2-peter.maydell@linaro.org | ||
7 | --- | 19 | --- |
8 | target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++----------- | 20 | target/arm/translate.c | 34 +++++++++++++++++++++++++++++++++- |
9 | 1 file changed, 67 insertions(+), 19 deletions(-) | 21 | 1 file changed, 33 insertions(+), 1 deletion(-) |
10 | 22 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 23 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
12 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 25 | --- a/target/arm/translate.c |
14 | +++ b/target/arm/translate.c | 26 | +++ b/target/arm/translate.c |
15 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) |
16 | #include "disas/disas.h" | 28 | /* An indirect jump so that we still trigger the debug exception. */ |
17 | #include "exec/exec-all.h" | 29 | gen_set_pc_im(s, dest); |
18 | #include "tcg-op.h" | 30 | s->base.is_jmp = DISAS_JUMP; |
19 | +#include "tcg-op-gvec.h" | 31 | - } else { |
20 | #include "qemu/log.h" | 32 | + return; |
21 | #include "qemu/bitops.h" | ||
22 | #include "arm_ldst.h" | ||
23 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_narrow_op(int op, int u, int size, | ||
24 | #define NEON_3R_VPMAX 20 | ||
25 | #define NEON_3R_VPMIN 21 | ||
26 | #define NEON_3R_VQDMULH_VQRDMULH 22 | ||
27 | -#define NEON_3R_VPADD 23 | ||
28 | +#define NEON_3R_VPADD_VQRDMLAH 23 | ||
29 | #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ | ||
30 | -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ | ||
31 | +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ | ||
32 | #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ | ||
33 | #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ | ||
34 | #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ | ||
35 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_3r_sizes[] = { | ||
36 | [NEON_3R_VPMAX] = 0x7, | ||
37 | [NEON_3R_VPMIN] = 0x7, | ||
38 | [NEON_3R_VQDMULH_VQRDMULH] = 0x6, | ||
39 | - [NEON_3R_VPADD] = 0x7, | ||
40 | + [NEON_3R_VPADD_VQRDMLAH] = 0x7, | ||
41 | [NEON_3R_SHA] = 0xf, /* size field encodes op type */ | ||
42 | - [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */ | ||
43 | + [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ | ||
44 | [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ | ||
45 | [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ | ||
46 | [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ | ||
47 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_2rm_sizes[] = { | ||
48 | [NEON_2RM_VCVT_UF] = 0x4, | ||
49 | }; | ||
50 | |||
51 | + | ||
52 | +/* Expand v8.1 simd helper. */ | ||
53 | +static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, | ||
54 | + int q, int rd, int rn, int rm) | ||
55 | +{ | ||
56 | + if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
57 | + int opr_sz = (1 + q) * 8; | ||
58 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
59 | + vfp_reg_offset(1, rn), | ||
60 | + vfp_reg_offset(1, rm), cpu_env, | ||
61 | + opr_sz, opr_sz, 0, fn); | ||
62 | + return 0; | ||
63 | + } | 33 | + } |
64 | + return 1; | 34 | + switch (s->base.is_jmp) { |
65 | +} | 35 | + case DISAS_NEXT: |
66 | + | 36 | + case DISAS_TOO_MANY: |
67 | /* Translate a NEON data processing instruction. Return nonzero if the | 37 | + case DISAS_NORETURN: |
68 | instruction is invalid. | 38 | + /* |
69 | We process data in a mixture of 32-bit and 64-bit chunks. | 39 | + * The normal case: just go to the destination TB. |
70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 40 | + * NB: NORETURN happens if we generate code like |
71 | if (q && ((rd | rn | rm) & 1)) { | 41 | + * gen_brcondi(l); |
72 | return 1; | 42 | + * gen_jmp(); |
73 | } | 43 | + * gen_set_label(l); |
74 | - /* | 44 | + * gen_jmp(); |
75 | - * The SHA-1/SHA-256 3-register instructions require special treatment | 45 | + * on the second call to gen_jmp(). |
76 | - * here, as their size field is overloaded as an op type selector, and | 46 | + */ |
77 | - * they all consume their input in a single pass. | 47 | gen_goto_tb(s, tbno, dest); |
78 | - */ | 48 | + break; |
79 | - if (op == NEON_3R_SHA) { | 49 | + case DISAS_UPDATE_NOCHAIN: |
80 | + switch (op) { | 50 | + case DISAS_UPDATE_EXIT: |
81 | + case NEON_3R_SHA: | 51 | + /* |
82 | + /* The SHA-1/SHA-256 3-register instructions require special | 52 | + * We already decided we're leaving the TB for some other reason. |
83 | + * treatment here, as their size field is overloaded as an | 53 | + * Avoid using goto_tb so we really do exit back to the main loop |
84 | + * op type selector, and they all consume their input in a | 54 | + * and don't chain to another TB. |
85 | + * single pass. | 55 | + */ |
86 | + */ | 56 | + gen_set_pc_im(s, dest); |
87 | if (!q) { | 57 | + gen_goto_ptr(); |
88 | return 1; | 58 | + s->base.is_jmp = DISAS_NORETURN; |
89 | } | 59 | + break; |
90 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 60 | + default: |
91 | tcg_temp_free_ptr(ptr2); | 61 | + /* |
92 | tcg_temp_free_ptr(ptr3); | 62 | + * We shouldn't be emitting code for a jump and also have |
93 | return 0; | 63 | + * is_jmp set to one of the special cases like DISAS_SWI. |
94 | + | 64 | + */ |
95 | + case NEON_3R_VPADD_VQRDMLAH: | 65 | + g_assert_not_reached(); |
96 | + if (!u) { | 66 | } |
97 | + break; /* VPADD */ | 67 | } |
98 | + } | 68 | |
99 | + /* VQRDMLAH */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16, | ||
103 | + q, rd, rn, rm); | ||
104 | + case 2: | ||
105 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32, | ||
106 | + q, rd, rn, rm); | ||
107 | + } | ||
108 | + return 1; | ||
109 | + | ||
110 | + case NEON_3R_VFM_VQRDMLSH: | ||
111 | + if (!u) { | ||
112 | + /* VFM, VFMS */ | ||
113 | + if (size == 1) { | ||
114 | + return 1; | ||
115 | + } | ||
116 | + break; | ||
117 | + } | ||
118 | + /* VQRDMLSH */ | ||
119 | + switch (size) { | ||
120 | + case 1: | ||
121 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16, | ||
122 | + q, rd, rn, rm); | ||
123 | + case 2: | ||
124 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32, | ||
125 | + q, rd, rn, rm); | ||
126 | + } | ||
127 | + return 1; | ||
128 | } | ||
129 | if (size == 3 && op != NEON_3R_LOGIC) { | ||
130 | /* 64-bit element instructions. */ | ||
131 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
132 | rm = rtmp; | ||
133 | } | ||
134 | break; | ||
135 | - case NEON_3R_VPADD: | ||
136 | - if (u) { | ||
137 | - return 1; | ||
138 | - } | ||
139 | - /* Fall through */ | ||
140 | + case NEON_3R_VPADD_VQRDMLAH: | ||
141 | case NEON_3R_VPMAX: | ||
142 | case NEON_3R_VPMIN: | ||
143 | pairwise = 1; | ||
144 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
145 | return 1; | ||
146 | } | ||
147 | break; | ||
148 | - case NEON_3R_VFM: | ||
149 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { | ||
150 | + case NEON_3R_VFM_VQRDMLSH: | ||
151 | + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { | ||
152 | return 1; | ||
153 | } | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
156 | } | ||
157 | } | ||
158 | break; | ||
159 | - case NEON_3R_VPADD: | ||
160 | + case NEON_3R_VPADD_VQRDMLAH: | ||
161 | switch (size) { | ||
162 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; | ||
163 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | ||
164 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
165 | } | ||
166 | } | ||
167 | break; | ||
168 | - case NEON_3R_VFM: | ||
169 | + case NEON_3R_VFM_VQRDMLSH: | ||
170 | { | ||
171 | /* VFMA, VFMS: fused multiply-add */ | ||
172 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
173 | -- | 69 | -- |
174 | 2.16.2 | 70 | 2.20.1 |
175 | 71 | ||
176 | 72 | diff view generated by jsdifflib |
1 | Create an "idau" property on the armv7m container object which | 1 | Architecturally, for an M-profile CPU with the LOB feature the |
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2 | we can forward to the CPU object. Annoyingly, we can't use | 2 | LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation |
3 | object_property_add_alias() because the CPU object we want to | 3 | enforces this everywhere, except that we don't check that it is true |
4 | forward to doesn't exist until the armv7m container is realized. | 4 | in incoming migration data. |
5 | |||
6 | We're going to add come in gen_update_fp_context() which relies on | ||
7 | the "always 4" property. Since this is TCG-only, we don't actually | ||
8 | need to be robust to bogus incoming migration data, and the effect of | ||
9 | it being wrong would be wrong code generation rather than a QEMU | ||
10 | crash; but if it did ever happen somehow it would be very difficult | ||
11 | to track down the cause. Add a check so that we fail the inbound | ||
12 | migration if the FPDSCR.LTPSIZE value is incorrect. | ||
5 | 13 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-6-peter.maydell@linaro.org | 16 | Message-id: 20210913095440.13462-3-peter.maydell@linaro.org |
9 | --- | 17 | --- |
10 | include/hw/arm/armv7m.h | 3 +++ | 18 | target/arm/machine.c | 13 +++++++++++++ |
11 | hw/arm/armv7m.c | 9 +++++++++ | 19 | 1 file changed, 13 insertions(+) |
12 | 2 files changed, 12 insertions(+) | ||
13 | 20 | ||
14 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | 21 | diff --git a/target/arm/machine.c b/target/arm/machine.c |
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/armv7m.h | 23 | --- a/target/arm/machine.c |
17 | +++ b/include/hw/arm/armv7m.h | 24 | +++ b/target/arm/machine.c |
18 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
19 | 26 | hw_breakpoint_update_all(cpu); | |
20 | #include "hw/sysbus.h" | 27 | hw_watchpoint_update_all(cpu); |
21 | #include "hw/intc/armv7m_nvic.h" | 28 | |
22 | +#include "target/arm/idau.h" | 29 | + /* |
23 | 30 | + * TCG gen_update_fp_context() relies on the invariant that | |
24 | #define TYPE_BITBAND "ARM,bitband-memory" | 31 | + * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; |
25 | #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | 32 | + * forbid bogus incoming data with some other value. |
26 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 33 | + */ |
27 | * + Property "memory": MemoryRegion defining the physical address space | 34 | + if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { |
28 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | 35 | + if (extract32(env->v7m.fpdscr[M_REG_NS], |
29 | * devices will be automatically layered on top of this view.) | 36 | + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || |
30 | + * + Property "idau": IDAU interface (forwarded to CPU object) | 37 | + extract32(env->v7m.fpdscr[M_REG_S], |
31 | */ | 38 | + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { |
32 | typedef struct ARMv7MState { | 39 | + return -1; |
33 | /*< private >*/ | ||
34 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
35 | char *cpu_type; | ||
36 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
37 | MemoryRegion *board_memory; | ||
38 | + Object *idau; | ||
39 | } ARMv7MState; | ||
40 | |||
41 | #endif | ||
42 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/armv7m.c | ||
45 | +++ b/hw/arm/armv7m.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #include "sysemu/qtest.h" | ||
48 | #include "qemu/error-report.h" | ||
49 | #include "exec/address-spaces.h" | ||
50 | +#include "target/arm/idau.h" | ||
51 | |||
52 | /* Bitbanded IO. Each word corresponds to a single bit. */ | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
55 | |||
56 | object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", | ||
57 | &error_abort); | ||
58 | + if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { | ||
59 | + object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); | ||
60 | + if (err != NULL) { | ||
61 | + error_propagate(errp, err); | ||
62 | + return; | ||
63 | + } | 40 | + } |
64 | + } | 41 | + } |
65 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | 42 | if (!kvm_enabled()) { |
66 | if (err != NULL) { | 43 | pmu_op_finish(&cpu->env); |
67 | error_propagate(errp, err); | 44 | } |
68 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
69 | DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), | ||
70 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
71 | MemoryRegion *), | ||
72 | + DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
73 | DEFINE_PROP_END_OF_LIST(), | ||
74 | }; | ||
75 | |||
76 | -- | 45 | -- |
77 | 2.16.2 | 46 | 2.20.1 |
78 | 47 | ||
79 | 48 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Our current codegen for MVE always calls out to helper functions, |
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2 | 2 | because some byte lanes might be predicated. The common case is that | |
3 | Not enabled anywhere yet. | 3 | in fact there is no predication active and all lanes should be |
4 | 4 | updated together, so we can produce better code by detecting that and | |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | using the TCG generic vector infrastructure. |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Add a TB flag that is set when we can guarantee that there is no |
8 | Message-id: 20180228193125.20577-2-richard.henderson@linaro.org | 8 | active MVE predication, and a bool in the DisasContext. Subsequent |
9 | patches will use this flag to generate improved code for some | ||
10 | instructions. | ||
11 | |||
12 | In most cases when the predication state changes we simply end the TB | ||
13 | after that instruction. For the code called from vfp_access_check() | ||
14 | that handles lazy state preservation and creating a new FP context, | ||
15 | we can usually avoid having to try to end the TB because luckily the | ||
16 | new value of the flag following the register changes in those | ||
17 | sequences doesn't depend on any runtime decisions. We do have to end | ||
18 | the TB if the guest has enabled lazy FP state preservation but not | ||
19 | automatic state preservation, but this is an odd corner case that is | ||
20 | not going to be common in real-world code. | ||
21 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | Message-id: 20210913095440.13462-4-peter.maydell@linaro.org | ||
10 | --- | 25 | --- |
11 | target/arm/cpu.h | 1 + | 26 | target/arm/cpu.h | 4 +++- |
12 | linux-user/elfload.c | 1 + | 27 | target/arm/translate.h | 2 ++ |
13 | 2 files changed, 2 insertions(+) | 28 | target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++ |
29 | target/arm/translate-m-nocp.c | 8 +++++++- | ||
30 | target/arm/translate-mve.c | 13 ++++++++++++- | ||
31 | target/arm/translate-vfp.c | 33 +++++++++++++++++++++++++++------ | ||
32 | target/arm/translate.c | 8 ++++++++ | ||
33 | 7 files changed, 92 insertions(+), 9 deletions(-) | ||
14 | 34 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 35 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
16 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 37 | --- a/target/arm/cpu.h |
18 | +++ b/target/arm/cpu.h | 38 | +++ b/target/arm/cpu.h |
19 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 39 | @@ -XXX,XX +XXX,XX @@ typedef ARMCPU ArchCPU; |
20 | ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ | 40 | * | TBFLAG_AM32 | +-----+----------+ |
21 | ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ | 41 | * | | |TBFLAG_M32| |
22 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | 42 | * +-------------+----------------+----------+ |
23 | + ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | 43 | - * 31 23 5 4 0 |
24 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | 44 | + * 31 23 6 5 0 |
25 | }; | 45 | * |
26 | 46 | * Unless otherwise noted, these bits are cached in env->hflags. | |
27 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 47 | */ |
28 | index XXXXXXX..XXXXXXX 100644 | 48 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ |
29 | --- a/linux-user/elfload.c | 49 | FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ |
30 | +++ b/linux-user/elfload.c | 50 | /* Set if FPCCR.S does not match current security state */ |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | 51 | FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ |
32 | GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); | 52 | +/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ |
33 | GET_FEATURE(ARM_FEATURE_V8_FP16, | 53 | +FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ |
34 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | 54 | |
35 | + GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | 55 | /* |
36 | #undef GET_FEATURE | 56 | * Bit usage when in AArch64 state |
37 | 57 | diff --git a/target/arm/translate.h b/target/arm/translate.h | |
38 | return hwcaps; | 58 | index XXXXXXX..XXXXXXX 100644 |
59 | --- a/target/arm/translate.h | ||
60 | +++ b/target/arm/translate.h | ||
61 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
62 | bool align_mem; | ||
63 | /* True if PSTATE.IL is set */ | ||
64 | bool pstate_il; | ||
65 | + /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ | ||
66 | + bool mve_no_pred; | ||
67 | /* | ||
68 | * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. | ||
69 | * < 0, set by the current instruction. | ||
70 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/helper.c | ||
73 | +++ b/target/arm/helper.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env) | ||
75 | #endif | ||
76 | } | ||
77 | |||
78 | +static bool mve_no_pred(CPUARMState *env) | ||
79 | +{ | ||
80 | + /* | ||
81 | + * Return true if there is definitely no predication of MVE | ||
82 | + * instructions by VPR or LTPSIZE. (Returning false even if there | ||
83 | + * isn't any predication is OK; generated code will just be | ||
84 | + * a little worse.) | ||
85 | + * If the CPU does not implement MVE then this TB flag is always 0. | ||
86 | + * | ||
87 | + * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | ||
88 | + * logic in gen_update_fp_context() needs to be updated to match. | ||
89 | + * | ||
90 | + * We do not include the effect of the ECI bits here -- they are | ||
91 | + * tracked in other TB flags. This simplifies the logic for | ||
92 | + * "when did we emit code that changes the MVE_NO_PRED TB flag | ||
93 | + * and thus need to end the TB?". | ||
94 | + */ | ||
95 | + if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | ||
96 | + return false; | ||
97 | + } | ||
98 | + if (env->v7m.vpr) { | ||
99 | + return false; | ||
100 | + } | ||
101 | + if (env->v7m.ltpsize < 4) { | ||
102 | + return false; | ||
103 | + } | ||
104 | + return true; | ||
105 | +} | ||
106 | + | ||
107 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
108 | target_ulong *cs_base, uint32_t *pflags) | ||
109 | { | ||
110 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
111 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | ||
112 | DP_TBFLAG_M32(flags, LSPACT, 1); | ||
113 | } | ||
114 | + | ||
115 | + if (mve_no_pred(env)) { | ||
116 | + DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | ||
117 | + } | ||
118 | } else { | ||
119 | /* | ||
120 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | ||
121 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/target/arm/translate-m-nocp.c | ||
124 | +++ b/target/arm/translate-m-nocp.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | ||
126 | |||
127 | clear_eci_state(s); | ||
128 | |||
129 | - /* End the TB, because we have updated FP control bits */ | ||
130 | + /* | ||
131 | + * End the TB, because we have updated FP control bits, | ||
132 | + * and possibly VPR or LTPSIZE. | ||
133 | + */ | ||
134 | s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
135 | return true; | ||
136 | } | ||
137 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
138 | store_cpu_field(control, v7m.control[M_REG_S]); | ||
139 | tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
140 | gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
141 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
142 | tcg_temp_free_i32(tmp); | ||
143 | tcg_temp_free_i32(sfpa); | ||
144 | break; | ||
145 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
146 | } | ||
147 | tmp = loadfn(s, opaque, true); | ||
148 | store_cpu_field(tmp, v7m.vpr); | ||
149 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
150 | break; | ||
151 | case ARM_VFP_P0: | ||
152 | { | ||
153 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
154 | tcg_gen_deposit_i32(vpr, vpr, tmp, | ||
155 | R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
156 | store_cpu_field(vpr, v7m.vpr); | ||
157 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
158 | tcg_temp_free_i32(tmp); | ||
159 | break; | ||
160 | } | ||
161 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/target/arm/translate-mve.c | ||
164 | +++ b/target/arm/translate-mve.c | ||
165 | @@ -XXX,XX +XXX,XX @@ DO_LOGIC(VORR, gen_helper_mve_vorr) | ||
166 | DO_LOGIC(VORN, gen_helper_mve_vorn) | ||
167 | DO_LOGIC(VEOR, gen_helper_mve_veor) | ||
168 | |||
169 | -DO_LOGIC(VPSEL, gen_helper_mve_vpsel) | ||
170 | +static bool trans_VPSEL(DisasContext *s, arg_2op *a) | ||
171 | +{ | ||
172 | + /* This insn updates predication bits */ | ||
173 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
174 | + return do_2op(s, a, gen_helper_mve_vpsel); | ||
175 | +} | ||
176 | |||
177 | #define DO_2OP(INSN, FN) \ | ||
178 | static bool trans_##INSN(DisasContext *s, arg_2op *a) \ | ||
179 | @@ -XXX,XX +XXX,XX @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) | ||
180 | } | ||
181 | |||
182 | gen_helper_mve_vpnot(cpu_env); | ||
183 | + /* This insn updates predication bits */ | ||
184 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
185 | mve_update_eci(s); | ||
186 | return true; | ||
187 | } | ||
188 | @@ -XXX,XX +XXX,XX @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) | ||
189 | /* VPT */ | ||
190 | gen_vpst(s, a->mask); | ||
191 | } | ||
192 | + /* This insn updates predication bits */ | ||
193 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
194 | mve_update_eci(s); | ||
195 | return true; | ||
196 | } | ||
197 | @@ -XXX,XX +XXX,XX @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, | ||
198 | /* VPT */ | ||
199 | gen_vpst(s, a->mask); | ||
200 | } | ||
201 | + /* This insn updates predication bits */ | ||
202 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
203 | mve_update_eci(s); | ||
204 | return true; | ||
205 | } | ||
206 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
207 | index XXXXXXX..XXXXXXX 100644 | ||
208 | --- a/target/arm/translate-vfp.c | ||
209 | +++ b/target/arm/translate-vfp.c | ||
210 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top) | ||
211 | * Generate code for M-profile lazy FP state preservation if needed; | ||
212 | * this corresponds to the pseudocode PreserveFPState() function. | ||
213 | */ | ||
214 | -static void gen_preserve_fp_state(DisasContext *s) | ||
215 | +static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update) | ||
216 | { | ||
217 | if (s->v7m_lspact) { | ||
218 | /* | ||
219 | @@ -XXX,XX +XXX,XX @@ static void gen_preserve_fp_state(DisasContext *s) | ||
220 | * any further FP insns in this TB. | ||
221 | */ | ||
222 | s->v7m_lspact = false; | ||
223 | + /* | ||
224 | + * The helper might have zeroed VPR, so we do not know the | ||
225 | + * correct value for the MVE_NO_PRED TB flag any more. | ||
226 | + * If we're about to create a new fp context then that | ||
227 | + * will precisely determine the MVE_NO_PRED value (see | ||
228 | + * gen_update_fp_context()). Otherwise, we must: | ||
229 | + * - set s->mve_no_pred to false, so this instruction | ||
230 | + * is generated to use helper functions | ||
231 | + * - end the TB now, without chaining to the next TB | ||
232 | + */ | ||
233 | + if (skip_context_update || !s->v7m_new_fp_ctxt_needed) { | ||
234 | + s->mve_no_pred = false; | ||
235 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
236 | + } | ||
237 | } | ||
238 | } | ||
239 | |||
240 | @@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s) | ||
241 | TCGv_i32 z32 = tcg_const_i32(0); | ||
242 | store_cpu_field(z32, v7m.vpr); | ||
243 | } | ||
244 | - | ||
245 | /* | ||
246 | - * We don't need to arrange to end the TB, because the only | ||
247 | - * parts of FPSCR which we cache in the TB flags are the VECLEN | ||
248 | - * and VECSTRIDE, and those don't exist for M-profile. | ||
249 | + * We just updated the FPSCR and VPR. Some of this state is cached | ||
250 | + * in the MVE_NO_PRED TB flag. We want to avoid having to end the | ||
251 | + * TB here, which means we need the new value of the MVE_NO_PRED | ||
252 | + * flag to be exactly known here and the same for all executions. | ||
253 | + * Luckily FPDSCR.LTPSIZE is always constant 4 and the VPR is | ||
254 | + * always set to 0, so the new MVE_NO_PRED flag is always 1 | ||
255 | + * if and only if we have MVE. | ||
256 | + * | ||
257 | + * (The other FPSCR state cached in TB flags is VECLEN and VECSTRIDE, | ||
258 | + * but those do not exist for M-profile, so are not relevant here.) | ||
259 | */ | ||
260 | + s->mve_no_pred = dc_isar_feature(aa32_mve, s); | ||
261 | |||
262 | if (s->v8m_secure) { | ||
263 | bits |= R_V7M_CONTROL_SFPA_MASK; | ||
264 | @@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) | ||
265 | /* Handle M-profile lazy FP state mechanics */ | ||
266 | |||
267 | /* Trigger lazy-state preservation if necessary */ | ||
268 | - gen_preserve_fp_state(s); | ||
269 | + gen_preserve_fp_state(s, skip_context_update); | ||
270 | |||
271 | if (!skip_context_update) { | ||
272 | /* Update ownership of FP context and create new FP context if needed */ | ||
273 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
274 | index XXXXXXX..XXXXXXX 100644 | ||
275 | --- a/target/arm/translate.c | ||
276 | +++ b/target/arm/translate.c | ||
277 | @@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) | ||
278 | /* DLSTP: set FPSCR.LTPSIZE */ | ||
279 | tmp = tcg_const_i32(a->size); | ||
280 | store_cpu_field(tmp, v7m.ltpsize); | ||
281 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
282 | } | ||
283 | return true; | ||
284 | } | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) | ||
286 | assert(ok); | ||
287 | tmp = tcg_const_i32(a->size); | ||
288 | store_cpu_field(tmp, v7m.ltpsize); | ||
289 | + /* | ||
290 | + * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0) | ||
291 | + * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK. | ||
292 | + */ | ||
293 | } | ||
294 | gen_jmp_tb(s, s->base.pc_next, 1); | ||
295 | |||
296 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a) | ||
297 | gen_helper_mve_vctp(cpu_env, masklen); | ||
298 | tcg_temp_free_i32(masklen); | ||
299 | tcg_temp_free_i32(rn_shifted); | ||
300 | + /* This insn updates predication bits */ | ||
301 | + s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
302 | mve_update_eci(s); | ||
303 | return true; | ||
304 | } | ||
305 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
306 | dc->v7m_new_fp_ctxt_needed = | ||
307 | EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED); | ||
308 | dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); | ||
309 | + dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); | ||
310 | } else { | ||
311 | dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); | ||
312 | dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); | ||
39 | -- | 313 | -- |
40 | 2.16.2 | 314 | 2.20.1 |
41 | 315 | ||
42 | 316 | diff view generated by jsdifflib |
1 | Add a function load_ramdisk_as() which behaves like the existing | 1 | When not predicating, implement the MVE bitwise logical insns |
---|---|---|---|
2 | load_ramdisk() but allows the caller to specify the AddressSpace | 2 | directly using TCG vector operations. |
3 | to use. This matches the pattern we have already for various | ||
4 | other loader functions. | ||
5 | 3 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20180220180325.29818-2-peter.maydell@linaro.org | 7 | Message-id: 20210913095440.13462-5-peter.maydell@linaro.org |
10 | --- | 8 | --- |
11 | include/hw/loader.h | 12 +++++++++++- | 9 | target/arm/translate-mve.c | 51 +++++++++++++++++++++++++++----------- |
12 | hw/core/loader.c | 8 +++++++- | 10 | 1 file changed, 36 insertions(+), 15 deletions(-) |
13 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
14 | 11 | ||
15 | diff --git a/include/hw/loader.h b/include/hw/loader.h | 12 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/loader.h | 14 | --- a/target/arm/translate-mve.c |
18 | +++ b/include/hw/loader.h | 15 | +++ b/target/arm/translate-mve.c |
19 | @@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep, | 16 | @@ -XXX,XX +XXX,XX @@ static TCGv_ptr mve_qreg_ptr(unsigned reg) |
20 | void *translate_opaque); | 17 | return ret; |
21 | 18 | } | |
22 | /** | 19 | |
23 | - * load_ramdisk: | 20 | +static bool mve_no_predication(DisasContext *s) |
24 | + * load_ramdisk_as: | ||
25 | * @filename: Path to the ramdisk image | ||
26 | * @addr: Memory address to load the ramdisk to | ||
27 | * @max_sz: Maximum allowed ramdisk size (for non-u-boot ramdisks) | ||
28 | + * @as: The AddressSpace to load the ELF to. The value of address_space_memory | ||
29 | + * is used if nothing is supplied here. | ||
30 | * | ||
31 | * Load a ramdisk image with U-Boot header to the specified memory | ||
32 | * address. | ||
33 | * | ||
34 | * Returns the size of the loaded image on success, -1 otherwise. | ||
35 | */ | ||
36 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
37 | + AddressSpace *as); | ||
38 | + | ||
39 | +/** | ||
40 | + * load_ramdisk: | ||
41 | + * Same as load_ramdisk_as(), but doesn't allow the caller to specify | ||
42 | + * an AddressSpace. | ||
43 | + */ | ||
44 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz); | ||
45 | |||
46 | ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen); | ||
47 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/core/loader.c | ||
50 | +++ b/hw/core/loader.c | ||
51 | @@ -XXX,XX +XXX,XX @@ int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr, | ||
52 | |||
53 | /* Load a ramdisk. */ | ||
54 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz) | ||
55 | +{ | 21 | +{ |
56 | + return load_ramdisk_as(filename, addr, max_sz, NULL); | 22 | + /* |
23 | + * Return true if we are executing the entire MVE instruction | ||
24 | + * with no predication or partial-execution, and so we can safely | ||
25 | + * use an inline TCG vector implementation. | ||
26 | + */ | ||
27 | + return s->eci == 0 && s->mve_no_pred; | ||
57 | +} | 28 | +} |
58 | + | 29 | + |
59 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | 30 | static bool mve_check_qreg_bank(DisasContext *s, int qmask) |
60 | + AddressSpace *as) | ||
61 | { | 31 | { |
62 | return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK, | 32 | /* |
63 | - NULL, NULL, NULL); | 33 | @@ -XXX,XX +XXX,XX @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) |
64 | + NULL, NULL, as); | 34 | return do_1op(s, a, fns[a->size]); |
65 | } | 35 | } |
66 | 36 | ||
67 | /* Load a gzip-compressed kernel to a dynamically allocated buffer. */ | 37 | -static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) |
38 | +static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn, | ||
39 | + GVecGen3Fn *vecfn) | ||
40 | { | ||
41 | TCGv_ptr qd, qn, qm; | ||
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) | ||
44 | return true; | ||
45 | } | ||
46 | |||
47 | - qd = mve_qreg_ptr(a->qd); | ||
48 | - qn = mve_qreg_ptr(a->qn); | ||
49 | - qm = mve_qreg_ptr(a->qm); | ||
50 | - fn(cpu_env, qd, qn, qm); | ||
51 | - tcg_temp_free_ptr(qd); | ||
52 | - tcg_temp_free_ptr(qn); | ||
53 | - tcg_temp_free_ptr(qm); | ||
54 | + if (vecfn && mve_no_predication(s)) { | ||
55 | + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qn), | ||
56 | + mve_qreg_offset(a->qm), 16, 16); | ||
57 | + } else { | ||
58 | + qd = mve_qreg_ptr(a->qd); | ||
59 | + qn = mve_qreg_ptr(a->qn); | ||
60 | + qm = mve_qreg_ptr(a->qm); | ||
61 | + fn(cpu_env, qd, qn, qm); | ||
62 | + tcg_temp_free_ptr(qd); | ||
63 | + tcg_temp_free_ptr(qn); | ||
64 | + tcg_temp_free_ptr(qm); | ||
65 | + } | ||
66 | mve_update_eci(s); | ||
67 | return true; | ||
68 | } | ||
69 | |||
70 | -#define DO_LOGIC(INSN, HELPER) \ | ||
71 | +static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn *fn) | ||
72 | +{ | ||
73 | + return do_2op_vec(s, a, fn, NULL); | ||
74 | +} | ||
75 | + | ||
76 | +#define DO_LOGIC(INSN, HELPER, VECFN) \ | ||
77 | static bool trans_##INSN(DisasContext *s, arg_2op *a) \ | ||
78 | { \ | ||
79 | - return do_2op(s, a, HELPER); \ | ||
80 | + return do_2op_vec(s, a, HELPER, VECFN); \ | ||
81 | } | ||
82 | |||
83 | -DO_LOGIC(VAND, gen_helper_mve_vand) | ||
84 | -DO_LOGIC(VBIC, gen_helper_mve_vbic) | ||
85 | -DO_LOGIC(VORR, gen_helper_mve_vorr) | ||
86 | -DO_LOGIC(VORN, gen_helper_mve_vorn) | ||
87 | -DO_LOGIC(VEOR, gen_helper_mve_veor) | ||
88 | +DO_LOGIC(VAND, gen_helper_mve_vand, tcg_gen_gvec_and) | ||
89 | +DO_LOGIC(VBIC, gen_helper_mve_vbic, tcg_gen_gvec_andc) | ||
90 | +DO_LOGIC(VORR, gen_helper_mve_vorr, tcg_gen_gvec_or) | ||
91 | +DO_LOGIC(VORN, gen_helper_mve_vorn, tcg_gen_gvec_orc) | ||
92 | +DO_LOGIC(VEOR, gen_helper_mve_veor, tcg_gen_gvec_xor) | ||
93 | |||
94 | static bool trans_VPSEL(DisasContext *s, arg_2op *a) | ||
95 | { | ||
68 | -- | 96 | -- |
69 | 2.16.2 | 97 | 2.20.1 |
70 | 98 | ||
71 | 99 | diff view generated by jsdifflib |
1 | Instead of loading guest images to the system address space, use the | 1 | Optimize MVE arithmetic ops when we have a TCG |
---|---|---|---|
2 | CPU's address space. This is important if we're trying to load the | 2 | vector operation we can use. |
3 | file to memory or via an alias memory region that is provided by an | ||
4 | SoC object and thus not mapped into the system address space. | ||
5 | 3 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20180220180325.29818-4-peter.maydell@linaro.org | 7 | Message-id: 20210913095440.13462-6-peter.maydell@linaro.org |
10 | --- | 8 | --- |
11 | hw/arm/armv7m.c | 17 ++++++++++++++--- | 9 | target/arm/translate-mve.c | 20 +++++++++++--------- |
12 | 1 file changed, 14 insertions(+), 3 deletions(-) | 10 | 1 file changed, 11 insertions(+), 9 deletions(-) |
13 | 11 | ||
14 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 12 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
15 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/armv7m.c | 14 | --- a/target/arm/translate-mve.c |
17 | +++ b/hw/arm/armv7m.c | 15 | +++ b/target/arm/translate-mve.c |
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | 16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a) |
19 | uint64_t entry; | 17 | return do_2op(s, a, gen_helper_mve_vpsel); |
20 | uint64_t lowaddr; | 18 | } |
21 | int big_endian; | 19 | |
22 | + AddressSpace *as; | 20 | -#define DO_2OP(INSN, FN) \ |
23 | + int asidx; | 21 | +#define DO_2OP_VEC(INSN, FN, VECFN) \ |
24 | + CPUState *cs = CPU(cpu); | 22 | static bool trans_##INSN(DisasContext *s, arg_2op *a) \ |
25 | 23 | { \ | |
26 | #ifdef TARGET_WORDS_BIGENDIAN | 24 | static MVEGenTwoOpFn * const fns[] = { \ |
27 | big_endian = 1; | 25 | @@ -XXX,XX +XXX,XX @@ static bool trans_VPSEL(DisasContext *s, arg_2op *a) |
28 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | 26 | gen_helper_mve_##FN##w, \ |
29 | exit(1); | 27 | NULL, \ |
28 | }; \ | ||
29 | - return do_2op(s, a, fns[a->size]); \ | ||
30 | + return do_2op_vec(s, a, fns[a->size], VECFN); \ | ||
30 | } | 31 | } |
31 | 32 | ||
32 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | 33 | -DO_2OP(VADD, vadd) |
33 | + asidx = ARMASIdx_S; | 34 | -DO_2OP(VSUB, vsub) |
34 | + } else { | 35 | -DO_2OP(VMUL, vmul) |
35 | + asidx = ARMASIdx_NS; | 36 | +#define DO_2OP(INSN, FN) DO_2OP_VEC(INSN, FN, NULL) |
36 | + } | ||
37 | + as = cpu_get_address_space(cs, asidx); | ||
38 | + | 37 | + |
39 | if (kernel_filename) { | 38 | +DO_2OP_VEC(VADD, vadd, tcg_gen_gvec_add) |
40 | - image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr, | 39 | +DO_2OP_VEC(VSUB, vsub, tcg_gen_gvec_sub) |
41 | - NULL, big_endian, EM_ARM, 1, 0); | 40 | +DO_2OP_VEC(VMUL, vmul, tcg_gen_gvec_mul) |
42 | + image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr, | 41 | DO_2OP(VMULH_S, vmulhs) |
43 | + NULL, big_endian, EM_ARM, 1, 0, as); | 42 | DO_2OP(VMULH_U, vmulhu) |
44 | if (image_size < 0) { | 43 | DO_2OP(VRMULH_S, vrmulhs) |
45 | - image_size = load_image_targphys(kernel_filename, 0, mem_size); | 44 | DO_2OP(VRMULH_U, vrmulhu) |
46 | + image_size = load_image_targphys_as(kernel_filename, 0, | 45 | -DO_2OP(VMAX_S, vmaxs) |
47 | + mem_size, as); | 46 | -DO_2OP(VMAX_U, vmaxu) |
48 | lowaddr = 0; | 47 | -DO_2OP(VMIN_S, vmins) |
49 | } | 48 | -DO_2OP(VMIN_U, vminu) |
50 | if (image_size < 0) { | 49 | +DO_2OP_VEC(VMAX_S, vmaxs, tcg_gen_gvec_smax) |
50 | +DO_2OP_VEC(VMAX_U, vmaxu, tcg_gen_gvec_umax) | ||
51 | +DO_2OP_VEC(VMIN_S, vmins, tcg_gen_gvec_smin) | ||
52 | +DO_2OP_VEC(VMIN_U, vminu, tcg_gen_gvec_umin) | ||
53 | DO_2OP(VABD_S, vabds) | ||
54 | DO_2OP(VABD_U, vabdu) | ||
55 | DO_2OP(VHADD_S, vhadds) | ||
51 | -- | 56 | -- |
52 | 2.16.2 | 57 | 2.20.1 |
53 | 58 | ||
54 | 59 | diff view generated by jsdifflib |
1 | Instead of loading kernels, device trees, and the like to | 1 | Optimize the MVE VNEG and VABS insns by using TCG |
---|---|---|---|
2 | the system address space, use the CPU's address space. This | 2 | vector ops when possible. |
3 | is important if we're trying to load the file to memory or | ||
4 | via an alias memory region that is provided by an SoC | ||
5 | object and thus not mapped into the system address space. | ||
6 | 3 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-3-peter.maydell@linaro.org | 7 | Message-id: 20210913095440.13462-7-peter.maydell@linaro.org |
11 | --- | 8 | --- |
12 | hw/arm/boot.c | 119 +++++++++++++++++++++++++++++++++++++--------------------- | 9 | target/arm/translate-mve.c | 32 ++++++++++++++++++++++---------- |
13 | 1 file changed, 76 insertions(+), 43 deletions(-) | 10 | 1 file changed, 22 insertions(+), 10 deletions(-) |
14 | 11 | ||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 12 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/boot.c | 14 | --- a/target/arm/translate-mve.c |
18 | +++ b/hw/arm/boot.c | 15 | +++ b/target/arm/translate-mve.c |
19 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) |
20 | #define ARM64_TEXT_OFFSET_OFFSET 8 | 17 | return true; |
21 | #define ARM64_MAGIC_OFFSET 56 | 18 | } |
22 | 19 | ||
23 | +static AddressSpace *arm_boot_address_space(ARMCPU *cpu, | 20 | -static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) |
24 | + const struct arm_boot_info *info) | 21 | +static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn, |
22 | + GVecGen2Fn vecfn) | ||
23 | { | ||
24 | TCGv_ptr qd, qm; | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) | ||
27 | return true; | ||
28 | } | ||
29 | |||
30 | - qd = mve_qreg_ptr(a->qd); | ||
31 | - qm = mve_qreg_ptr(a->qm); | ||
32 | - fn(cpu_env, qd, qm); | ||
33 | - tcg_temp_free_ptr(qd); | ||
34 | - tcg_temp_free_ptr(qm); | ||
35 | + if (vecfn && mve_no_predication(s)) { | ||
36 | + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), 16, 16); | ||
37 | + } else { | ||
38 | + qd = mve_qreg_ptr(a->qd); | ||
39 | + qm = mve_qreg_ptr(a->qm); | ||
40 | + fn(cpu_env, qd, qm); | ||
41 | + tcg_temp_free_ptr(qd); | ||
42 | + tcg_temp_free_ptr(qm); | ||
43 | + } | ||
44 | mve_update_eci(s); | ||
45 | return true; | ||
46 | } | ||
47 | |||
48 | -#define DO_1OP(INSN, FN) \ | ||
49 | +static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) | ||
25 | +{ | 50 | +{ |
26 | + /* Return the address space to use for bootloader reads and writes. | 51 | + return do_1op_vec(s, a, fn, NULL); |
27 | + * We prefer the secure address space if the CPU has it and we're | ||
28 | + * going to boot the guest into it. | ||
29 | + */ | ||
30 | + int asidx; | ||
31 | + CPUState *cs = CPU(cpu); | ||
32 | + | ||
33 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { | ||
34 | + asidx = ARMASIdx_S; | ||
35 | + } else { | ||
36 | + asidx = ARMASIdx_NS; | ||
37 | + } | ||
38 | + | ||
39 | + return cpu_get_address_space(cs, asidx); | ||
40 | +} | 52 | +} |
41 | + | 53 | + |
42 | typedef enum { | 54 | +#define DO_1OP_VEC(INSN, FN, VECFN) \ |
43 | FIXUP_NONE = 0, /* do nothing */ | 55 | static bool trans_##INSN(DisasContext *s, arg_1op *a) \ |
44 | FIXUP_TERMINATOR, /* end of insns */ | 56 | { \ |
45 | @@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup smpboot[] = { | 57 | static MVEGenOneOpFn * const fns[] = { \ |
46 | }; | 58 | @@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) |
47 | 59 | gen_helper_mve_##FN##w, \ | |
48 | static void write_bootloader(const char *name, hwaddr addr, | 60 | NULL, \ |
49 | - const ARMInsnFixup *insns, uint32_t *fixupcontext) | 61 | }; \ |
50 | + const ARMInsnFixup *insns, uint32_t *fixupcontext, | 62 | - return do_1op(s, a, fns[a->size]); \ |
51 | + AddressSpace *as) | 63 | + return do_1op_vec(s, a, fns[a->size], VECFN); \ |
52 | { | ||
53 | /* Fix up the specified bootloader fragment and write it into | ||
54 | * guest memory using rom_add_blob_fixed(). fixupcontext is | ||
55 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr, | ||
56 | code[i] = tswap32(insn); | ||
57 | } | 64 | } |
58 | 65 | ||
59 | - rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); | 66 | +#define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL) |
60 | + rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); | ||
61 | |||
62 | g_free(code); | ||
63 | } | ||
64 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
65 | const struct arm_boot_info *info) | ||
66 | { | ||
67 | uint32_t fixupcontext[FIXUP_MAX]; | ||
68 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
69 | |||
70 | fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; | ||
71 | fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; | ||
72 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
73 | } | ||
74 | |||
75 | write_bootloader("smpboot", info->smp_loader_start, | ||
76 | - smpboot, fixupcontext); | ||
77 | + smpboot, fixupcontext, as); | ||
78 | } | ||
79 | |||
80 | void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
81 | const struct arm_boot_info *info, | ||
82 | hwaddr mvbar_addr) | ||
83 | { | ||
84 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
85 | int n; | ||
86 | uint32_t mvbar_blob[] = { | ||
87 | /* mvbar_addr: secure monitor vectors | ||
88 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
89 | for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { | ||
90 | mvbar_blob[n] = tswap32(mvbar_blob[n]); | ||
91 | } | ||
92 | - rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
93 | - mvbar_addr); | ||
94 | + rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
95 | + mvbar_addr, as); | ||
96 | |||
97 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | ||
98 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | ||
99 | } | ||
100 | - rom_add_blob_fixed("board-setup", board_setup_blob, | ||
101 | - sizeof(board_setup_blob), info->board_setup_addr); | ||
102 | + rom_add_blob_fixed_as("board-setup", board_setup_blob, | ||
103 | + sizeof(board_setup_blob), info->board_setup_addr, as); | ||
104 | } | ||
105 | |||
106 | static void default_reset_secondary(ARMCPU *cpu, | ||
107 | const struct arm_boot_info *info) | ||
108 | { | ||
109 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
110 | CPUState *cs = CPU(cpu); | ||
111 | |||
112 | - address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, | ||
113 | + address_space_stl_notdirty(as, info->smp_bootreg_addr, | ||
114 | 0, MEMTXATTRS_UNSPECIFIED, NULL); | ||
115 | cpu_set_pc(cs, info->smp_loader_start); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static inline bool have_dtb(const struct arm_boot_info *info) | ||
118 | } | ||
119 | |||
120 | #define WRITE_WORD(p, value) do { \ | ||
121 | - address_space_stl_notdirty(&address_space_memory, p, value, \ | ||
122 | + address_space_stl_notdirty(as, p, value, \ | ||
123 | MEMTXATTRS_UNSPECIFIED, NULL); \ | ||
124 | p += 4; \ | ||
125 | } while (0) | ||
126 | |||
127 | -static void set_kernel_args(const struct arm_boot_info *info) | ||
128 | +static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) | ||
129 | { | ||
130 | int initrd_size = info->initrd_size; | ||
131 | hwaddr base = info->loader_start; | ||
132 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
133 | int cmdline_size; | ||
134 | |||
135 | cmdline_size = strlen(info->kernel_cmdline); | ||
136 | - cpu_physical_memory_write(p + 8, info->kernel_cmdline, | ||
137 | - cmdline_size + 1); | ||
138 | + address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, | ||
139 | + (const uint8_t *)info->kernel_cmdline, | ||
140 | + cmdline_size + 1); | ||
141 | cmdline_size = (cmdline_size >> 2) + 1; | ||
142 | WRITE_WORD(p, cmdline_size + 2); | ||
143 | WRITE_WORD(p, 0x54410009); | ||
144 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
145 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; | ||
146 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | ||
147 | WRITE_WORD(p, 0x414f4d50); | ||
148 | - cpu_physical_memory_write(p, atag_board_buf, atag_board_len); | ||
149 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
150 | + atag_board_buf, atag_board_len); | ||
151 | p += atag_board_len; | ||
152 | } | ||
153 | /* ATAG_END */ | ||
154 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
155 | WRITE_WORD(p, 0); | ||
156 | } | ||
157 | |||
158 | -static void set_kernel_args_old(const struct arm_boot_info *info) | ||
159 | +static void set_kernel_args_old(const struct arm_boot_info *info, | ||
160 | + AddressSpace *as) | ||
161 | { | ||
162 | hwaddr p; | ||
163 | const char *s; | ||
164 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info) | ||
165 | } | ||
166 | s = info->kernel_cmdline; | ||
167 | if (s) { | ||
168 | - cpu_physical_memory_write(p, s, strlen(s) + 1); | ||
169 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
170 | + (const uint8_t *)s, strlen(s) + 1); | ||
171 | } else { | ||
172 | WRITE_WORD(p, 0); | ||
173 | } | ||
174 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
175 | * @addr: the address to load the image at | ||
176 | * @binfo: struct describing the boot environment | ||
177 | * @addr_limit: upper limit of the available memory area at @addr | ||
178 | + * @as: address space to load image to | ||
179 | * | ||
180 | * Load a device tree supplied by the machine or by the user with the | ||
181 | * '-dtb' command line option, and put it at offset @addr in target | ||
182 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
183 | * Note: Must not be called unless have_dtb(binfo) is true. | ||
184 | */ | ||
185 | static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
186 | - hwaddr addr_limit) | ||
187 | + hwaddr addr_limit, AddressSpace *as) | ||
188 | { | ||
189 | void *fdt = NULL; | ||
190 | int size, rc; | ||
191 | @@ -XXX,XX +XXX,XX @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
192 | /* Put the DTB into the memory map as a ROM image: this will ensure | ||
193 | * the DTB is copied again upon reset, even if addr points into RAM. | ||
194 | */ | ||
195 | - rom_add_blob_fixed("dtb", fdt, size, addr); | ||
196 | + rom_add_blob_fixed_as("dtb", fdt, size, addr, as); | ||
197 | |||
198 | g_free(fdt); | ||
199 | |||
200 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
201 | } | ||
202 | |||
203 | if (cs == first_cpu) { | ||
204 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
205 | + | 67 | + |
206 | cpu_set_pc(cs, info->loader_start); | 68 | DO_1OP(VCLZ, vclz) |
207 | 69 | DO_1OP(VCLS, vcls) | |
208 | if (!have_dtb(info)) { | 70 | -DO_1OP(VABS, vabs) |
209 | if (old_param) { | 71 | -DO_1OP(VNEG, vneg) |
210 | - set_kernel_args_old(info); | 72 | +DO_1OP_VEC(VABS, vabs, tcg_gen_gvec_abs) |
211 | + set_kernel_args_old(info, as); | 73 | +DO_1OP_VEC(VNEG, vneg, tcg_gen_gvec_neg) |
212 | } else { | 74 | DO_1OP(VQABS, vqabs) |
213 | - set_kernel_args(info); | 75 | DO_1OP(VQNEG, vqneg) |
214 | + set_kernel_args(info, as); | 76 | DO_1OP(VMAXA, vmaxa) |
215 | } | ||
216 | } | ||
217 | } else { | ||
218 | @@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque) | ||
219 | |||
220 | static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
221 | uint64_t *lowaddr, uint64_t *highaddr, | ||
222 | - int elf_machine) | ||
223 | + int elf_machine, AddressSpace *as) | ||
224 | { | ||
225 | bool elf_is64; | ||
226 | union { | ||
227 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
228 | } | ||
229 | } | ||
230 | |||
231 | - ret = load_elf(info->kernel_filename, NULL, NULL, | ||
232 | - pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
233 | - 1, data_swab); | ||
234 | + ret = load_elf_as(info->kernel_filename, NULL, NULL, | ||
235 | + pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
236 | + 1, data_swab, as); | ||
237 | if (ret <= 0) { | ||
238 | /* The header loaded but the image didn't */ | ||
239 | exit(1); | ||
240 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
241 | } | ||
242 | |||
243 | static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
244 | - hwaddr *entry) | ||
245 | + hwaddr *entry, AddressSpace *as) | ||
246 | { | ||
247 | hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; | ||
248 | uint8_t *buffer; | ||
249 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
250 | } | ||
251 | |||
252 | *entry = mem_base + kernel_load_offset; | ||
253 | - rom_add_blob_fixed(filename, buffer, size, *entry); | ||
254 | + rom_add_blob_fixed_as(filename, buffer, size, *entry, as); | ||
255 | |||
256 | g_free(buffer); | ||
257 | |||
258 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
259 | ARMCPU *cpu = n->cpu; | ||
260 | struct arm_boot_info *info = | ||
261 | container_of(n, struct arm_boot_info, load_kernel_notifier); | ||
262 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
263 | |||
264 | /* The board code is not supposed to set secure_board_setup unless | ||
265 | * running its code in secure mode is actually possible, and KVM | ||
266 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
267 | * the kernel is supposed to be loaded by the bootloader), copy the | ||
268 | * DTB to the base of RAM for the bootloader to pick up. | ||
269 | */ | ||
270 | - if (load_dtb(info->loader_start, info, 0) < 0) { | ||
271 | + if (load_dtb(info->loader_start, info, 0, as) < 0) { | ||
272 | exit(1); | ||
273 | } | ||
274 | } | ||
275 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
276 | |||
277 | /* Assume that raw images are linux kernels, and ELF images are not. */ | ||
278 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | ||
279 | - &elf_high_addr, elf_machine); | ||
280 | + &elf_high_addr, elf_machine, as); | ||
281 | if (kernel_size > 0 && have_dtb(info)) { | ||
282 | /* If there is still some room left at the base of RAM, try and put | ||
283 | * the DTB there like we do for images loaded with -bios or -pflash. | ||
284 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
285 | if (elf_low_addr < info->loader_start) { | ||
286 | elf_low_addr = 0; | ||
287 | } | ||
288 | - if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { | ||
289 | + if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) { | ||
290 | exit(1); | ||
291 | } | ||
292 | } | ||
293 | } | ||
294 | entry = elf_entry; | ||
295 | if (kernel_size < 0) { | ||
296 | - kernel_size = load_uimage(info->kernel_filename, &entry, NULL, | ||
297 | - &is_linux, NULL, NULL); | ||
298 | + kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, | ||
299 | + &is_linux, NULL, NULL, as); | ||
300 | } | ||
301 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { | ||
302 | kernel_size = load_aarch64_image(info->kernel_filename, | ||
303 | - info->loader_start, &entry); | ||
304 | + info->loader_start, &entry, as); | ||
305 | is_linux = 1; | ||
306 | } else if (kernel_size < 0) { | ||
307 | /* 32-bit ARM */ | ||
308 | entry = info->loader_start + KERNEL_LOAD_ADDR; | ||
309 | - kernel_size = load_image_targphys(info->kernel_filename, entry, | ||
310 | - info->ram_size - KERNEL_LOAD_ADDR); | ||
311 | + kernel_size = load_image_targphys_as(info->kernel_filename, entry, | ||
312 | + info->ram_size - KERNEL_LOAD_ADDR, | ||
313 | + as); | ||
314 | is_linux = 1; | ||
315 | } | ||
316 | if (kernel_size < 0) { | ||
317 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
318 | uint32_t fixupcontext[FIXUP_MAX]; | ||
319 | |||
320 | if (info->initrd_filename) { | ||
321 | - initrd_size = load_ramdisk(info->initrd_filename, | ||
322 | - info->initrd_start, | ||
323 | - info->ram_size - | ||
324 | - info->initrd_start); | ||
325 | + initrd_size = load_ramdisk_as(info->initrd_filename, | ||
326 | + info->initrd_start, | ||
327 | + info->ram_size - info->initrd_start, | ||
328 | + as); | ||
329 | if (initrd_size < 0) { | ||
330 | - initrd_size = load_image_targphys(info->initrd_filename, | ||
331 | - info->initrd_start, | ||
332 | - info->ram_size - | ||
333 | - info->initrd_start); | ||
334 | + initrd_size = load_image_targphys_as(info->initrd_filename, | ||
335 | + info->initrd_start, | ||
336 | + info->ram_size - | ||
337 | + info->initrd_start, | ||
338 | + as); | ||
339 | } | ||
340 | if (initrd_size < 0) { | ||
341 | error_report("could not load initrd '%s'", | ||
342 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
343 | |||
344 | /* Place the DTB after the initrd in memory with alignment. */ | ||
345 | dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); | ||
346 | - if (load_dtb(dtb_start, info, 0) < 0) { | ||
347 | + if (load_dtb(dtb_start, info, 0, as) < 0) { | ||
348 | exit(1); | ||
349 | } | ||
350 | fixupcontext[FIXUP_ARGPTR] = dtb_start; | ||
351 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
352 | fixupcontext[FIXUP_ENTRYPOINT] = entry; | ||
353 | |||
354 | write_bootloader("bootloader", info->loader_start, | ||
355 | - primary_loader, fixupcontext); | ||
356 | + primary_loader, fixupcontext, as); | ||
357 | |||
358 | if (info->nb_cpus > 1) { | ||
359 | info->write_secondary_boot(cpu, info); | ||
360 | -- | 77 | -- |
361 | 2.16.2 | 78 | 2.20.1 |
362 | 79 | ||
363 | 80 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Create an "init-svtor" property on the armv7m container | ||
2 | object which we can forward to the CPU object. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20180220180325.29818-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | include/hw/arm/armv7m.h | 2 ++ | ||
9 | hw/arm/armv7m.c | 9 +++++++++ | ||
10 | 2 files changed, 11 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/armv7m.h | ||
15 | +++ b/include/hw/arm/armv7m.h | ||
16 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
17 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
18 | * devices will be automatically layered on top of this view.) | ||
19 | * + Property "idau": IDAU interface (forwarded to CPU object) | ||
20 | + * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) | ||
21 | */ | ||
22 | typedef struct ARMv7MState { | ||
23 | /*< private >*/ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
25 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
26 | MemoryRegion *board_memory; | ||
27 | Object *idau; | ||
28 | + uint32_t init_svtor; | ||
29 | } ARMv7MState; | ||
30 | |||
31 | #endif | ||
32 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/armv7m.c | ||
35 | +++ b/hw/arm/armv7m.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
37 | return; | ||
38 | } | ||
39 | } | ||
40 | + if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { | ||
41 | + object_property_set_uint(OBJECT(s->cpu), s->init_svtor, | ||
42 | + "init-svtor", &err); | ||
43 | + if (err != NULL) { | ||
44 | + error_propagate(errp, err); | ||
45 | + return; | ||
46 | + } | ||
47 | + } | ||
48 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
49 | if (err != NULL) { | ||
50 | error_propagate(errp, err); | ||
51 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
52 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
53 | MemoryRegion *), | ||
54 | DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
55 | + DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), | ||
56 | DEFINE_PROP_END_OF_LIST(), | ||
57 | }; | ||
58 | |||
59 | -- | ||
60 | 2.16.2 | ||
61 | |||
62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the definition of the struct for the unimplemented-device | ||
2 | from unimp.c to unimp.h, so that users can embed the struct | ||
3 | in their own device structs if they prefer. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-10-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/misc/unimp.h | 10 ++++++++++ | ||
11 | hw/misc/unimp.c | 10 ---------- | ||
12 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/misc/unimp.h | ||
17 | +++ b/include/hw/misc/unimp.h | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" | ||
21 | |||
22 | +#define UNIMPLEMENTED_DEVICE(obj) \ | ||
23 | + OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
24 | + | ||
25 | +typedef struct { | ||
26 | + SysBusDevice parent_obj; | ||
27 | + MemoryRegion iomem; | ||
28 | + char *name; | ||
29 | + uint64_t size; | ||
30 | +} UnimplementedDeviceState; | ||
31 | + | ||
32 | /** | ||
33 | * create_unimplemented_device: create and map a dummy device | ||
34 | * @name: name of the device for debug logging | ||
35 | diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/misc/unimp.c | ||
38 | +++ b/hw/misc/unimp.c | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | #include "qemu/log.h" | ||
41 | #include "qapi/error.h" | ||
42 | |||
43 | -#define UNIMPLEMENTED_DEVICE(obj) \ | ||
44 | - OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
45 | - | ||
46 | -typedef struct { | ||
47 | - SysBusDevice parent_obj; | ||
48 | - MemoryRegion iomem; | ||
49 | - char *name; | ||
50 | - uint64_t size; | ||
51 | -} UnimplementedDeviceState; | ||
52 | - | ||
53 | static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size) | ||
54 | { | ||
55 | UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
56 | -- | ||
57 | 2.16.2 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The or-irq.h header file is missing the customary guard against | ||
2 | multiple inclusion, which means compilation fails if it gets | ||
3 | included twice. Fix the omission. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-11-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/or-irq.h | 5 +++++ | ||
11 | 1 file changed, 5 insertions(+) | ||
12 | |||
13 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/or-irq.h | ||
16 | +++ b/include/hw/or-irq.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * THE SOFTWARE. | ||
19 | */ | ||
20 | |||
21 | +#ifndef HW_OR_IRQ_H | ||
22 | +#define HW_OR_IRQ_H | ||
23 | + | ||
24 | #include "hw/irq.h" | ||
25 | #include "hw/sysbus.h" | ||
26 | #include "qom/object.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct OrIRQState { | ||
28 | bool levels[MAX_OR_LINES]; | ||
29 | uint16_t num_lines; | ||
30 | }; | ||
31 | + | ||
32 | +#endif | ||
33 | -- | ||
34 | 2.16.2 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The function qdev_init_gpio_in_named() passes the DeviceState pointer | ||
2 | as the opaque data pointor for the irq handler function. Usually | ||
3 | this is what you want, but in some cases it would be helpful to use | ||
4 | some other data pointer. | ||
5 | 1 | ||
6 | Add a new function qdev_init_gpio_in_named_with_opaque() which allows | ||
7 | the caller to specify the data pointer they want. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180220180325.29818-12-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/hw/qdev-core.h | 30 ++++++++++++++++++++++++++++-- | ||
15 | hw/core/qdev.c | 8 +++++--- | ||
16 | 2 files changed, 33 insertions(+), 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/qdev-core.h | ||
21 | +++ b/include/hw/qdev-core.h | ||
22 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
23 | /* GPIO inputs also double as IRQ sinks. */ | ||
24 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
25 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
26 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
27 | - const char *name, int n); | ||
28 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
29 | const char *name, int n); | ||
30 | +/** | ||
31 | + * qdev_init_gpio_in_named_with_opaque: create an array of input GPIO lines | ||
32 | + * for the specified device | ||
33 | + * | ||
34 | + * @dev: Device to create input GPIOs for | ||
35 | + * @handler: Function to call when GPIO line value is set | ||
36 | + * @opaque: Opaque data pointer to pass to @handler | ||
37 | + * @name: Name of the GPIO input (must be unique for this device) | ||
38 | + * @n: Number of GPIO lines in this input set | ||
39 | + */ | ||
40 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
41 | + qemu_irq_handler handler, | ||
42 | + void *opaque, | ||
43 | + const char *name, int n); | ||
44 | + | ||
45 | +/** | ||
46 | + * qdev_init_gpio_in_named: create an array of input GPIO lines | ||
47 | + * for the specified device | ||
48 | + * | ||
49 | + * Like qdev_init_gpio_in_named_with_opaque(), but the opaque pointer | ||
50 | + * passed to the handler is @dev (which is the most commonly desired behaviour). | ||
51 | + */ | ||
52 | +static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
53 | + qemu_irq_handler handler, | ||
54 | + const char *name, int n) | ||
55 | +{ | ||
56 | + qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
57 | +} | ||
58 | |||
59 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
60 | const char *name); | ||
61 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/core/qdev.c | ||
64 | +++ b/hw/core/qdev.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, | ||
66 | return ngl; | ||
67 | } | ||
68 | |||
69 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
70 | - const char *name, int n) | ||
71 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
72 | + qemu_irq_handler handler, | ||
73 | + void *opaque, | ||
74 | + const char *name, int n) | ||
75 | { | ||
76 | int i; | ||
77 | NamedGPIOList *gpio_list = qdev_get_named_gpio_list(dev, name); | ||
78 | |||
79 | assert(gpio_list->num_out == 0 || !name); | ||
80 | gpio_list->in = qemu_extend_irqs(gpio_list->in, gpio_list->num_in, handler, | ||
81 | - dev, n); | ||
82 | + opaque, n); | ||
83 | |||
84 | if (!name) { | ||
85 | name = "unnamed-gpio-in"; | ||
86 | -- | ||
87 | 2.16.2 | ||
88 | |||
89 | diff view generated by jsdifflib |
1 | Add remaining easy registers to iotkit-secctl: | 1 | Optimize the MVE VDUP insns by using TCG vector ops when possible. |
---|---|---|---|
2 | * NSCCFG just routes its two bits out to external GPIO lines | ||
3 | * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's | ||
4 | bus fabric can never report errors | ||
5 | 2 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20180220180325.29818-18-peter.maydell@linaro.org | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20210913095440.13462-8-peter.maydell@linaro.org | ||
8 | --- | 6 | --- |
9 | include/hw/misc/iotkit-secctl.h | 4 ++++ | 7 | target/arm/translate-mve.c | 12 ++++++++---- |
10 | hw/misc/iotkit-secctl.c | 32 ++++++++++++++++++++++++++------ | 8 | 1 file changed, 8 insertions(+), 4 deletions(-) |
11 | 2 files changed, 30 insertions(+), 6 deletions(-) | ||
12 | 9 | ||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 10 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
14 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/misc/iotkit-secctl.h | 12 | --- a/target/arm/translate-mve.c |
16 | +++ b/include/hw/misc/iotkit-secctl.h | 13 | +++ b/target/arm/translate-mve.c |
17 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) |
18 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 15 | return true; |
19 | * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | ||
20 | * should RAZ/WI or bus error | ||
21 | + * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value | ||
22 | * Controlling the 2 APB PPCs in the IoTKit: | ||
23 | * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
24 | * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
25 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
26 | |||
27 | /*< public >*/ | ||
28 | qemu_irq sec_resp_cfg; | ||
29 | + qemu_irq nsc_cfg_irq; | ||
30 | |||
31 | MemoryRegion s_regs; | ||
32 | MemoryRegion ns_regs; | ||
33 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
34 | uint32_t secppcintstat; | ||
35 | uint32_t secppcinten; | ||
36 | uint32_t secrespcfg; | ||
37 | + uint32_t nsccfg; | ||
38 | + uint32_t brginten; | ||
39 | |||
40 | IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
41 | IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
42 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/misc/iotkit-secctl.c | ||
45 | +++ b/hw/misc/iotkit-secctl.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
47 | case A_SECRESPCFG: | ||
48 | r = s->secrespcfg; | ||
49 | break; | ||
50 | + case A_NSCCFG: | ||
51 | + r = s->nsccfg; | ||
52 | + break; | ||
53 | case A_SECPPCINTSTAT: | ||
54 | r = s->secppcintstat; | ||
55 | break; | ||
56 | case A_SECPPCINTEN: | ||
57 | r = s->secppcinten; | ||
58 | break; | ||
59 | + case A_BRGINTSTAT: | ||
60 | + /* QEMU's bus fabric can never report errors as it doesn't buffer | ||
61 | + * writes, so we never report bridge interrupts. | ||
62 | + */ | ||
63 | + r = 0; | ||
64 | + break; | ||
65 | + case A_BRGINTEN: | ||
66 | + r = s->brginten; | ||
67 | + break; | ||
68 | case A_AHBNSPPCEXP0: | ||
69 | case A_AHBNSPPCEXP1: | ||
70 | case A_AHBNSPPCEXP2: | ||
71 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
72 | case A_APBSPPPCEXP3: | ||
73 | r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
74 | break; | ||
75 | - case A_NSCCFG: | ||
76 | case A_SECMPCINTSTATUS: | ||
77 | case A_SECMSCINTSTAT: | ||
78 | case A_SECMSCINTEN: | ||
79 | - case A_BRGINTSTAT: | ||
80 | - case A_BRGINTEN: | ||
81 | case A_NSMSCEXP: | ||
82 | qemu_log_mask(LOG_UNIMP, | ||
83 | "IoTKit SecCtl S block read: " | ||
84 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
85 | } | 16 | } |
86 | 17 | ||
87 | switch (offset) { | 18 | - qd = mve_qreg_ptr(a->qd); |
88 | + case A_NSCCFG: | 19 | rt = load_reg(s, a->rt); |
89 | + s->nsccfg = value & 3; | 20 | - tcg_gen_dup_i32(a->size, rt, rt); |
90 | + qemu_set_irq(s->nsc_cfg_irq, s->nsccfg); | 21 | - gen_helper_mve_vdup(cpu_env, qd, rt); |
91 | + break; | 22 | - tcg_temp_free_ptr(qd); |
92 | case A_SECRESPCFG: | 23 | + if (mve_no_predication(s)) { |
93 | value &= 1; | 24 | + tcg_gen_gvec_dup_i32(a->size, mve_qreg_offset(a->qd), 16, 16, rt); |
94 | s->secrespcfg = value; | 25 | + } else { |
95 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | 26 | + qd = mve_qreg_ptr(a->qd); |
96 | s->secppcinten = value & 0x00f000f3; | 27 | + tcg_gen_dup_i32(a->size, rt, rt); |
97 | foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | 28 | + gen_helper_mve_vdup(cpu_env, qd, rt); |
98 | break; | 29 | + tcg_temp_free_ptr(qd); |
99 | + case A_BRGINTCLR: | 30 | + } |
100 | + break; | 31 | tcg_temp_free_i32(rt); |
101 | + case A_BRGINTEN: | 32 | mve_update_eci(s); |
102 | + s->brginten = value & 0xffff0000; | 33 | return true; |
103 | + break; | ||
104 | case A_AHBNSPPCEXP0: | ||
105 | case A_AHBNSPPCEXP1: | ||
106 | case A_AHBNSPPCEXP2: | ||
107 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
108 | ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
109 | iotkit_secctl_ppc_sp_write(ppc, value); | ||
110 | break; | ||
111 | - case A_NSCCFG: | ||
112 | case A_SECMSCINTCLR: | ||
113 | case A_SECMSCINTEN: | ||
114 | - case A_BRGINTCLR: | ||
115 | - case A_BRGINTEN: | ||
116 | qemu_log_mask(LOG_UNIMP, | ||
117 | "IoTKit SecCtl S block write: " | ||
118 | "unimplemented offset 0x%x\n", offset); | ||
119 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_reset(DeviceState *dev) | ||
120 | s->secppcintstat = 0; | ||
121 | s->secppcinten = 0; | ||
122 | s->secrespcfg = 0; | ||
123 | + s->nsccfg = 0; | ||
124 | + s->brginten = 0; | ||
125 | |||
126 | foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
127 | } | ||
128 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
129 | } | ||
130 | |||
131 | qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
132 | + qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); | ||
133 | |||
134 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
135 | s, "iotkit-secctl-s-regs", 0x1000); | ||
136 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_vmstate = { | ||
137 | VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
138 | VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
139 | VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
140 | + VMSTATE_UINT32(nsccfg, IoTKitSecCtl), | ||
141 | + VMSTATE_UINT32(brginten, IoTKitSecCtl), | ||
142 | VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
143 | iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
144 | VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
145 | -- | 34 | -- |
146 | 2.16.2 | 35 | 2.20.1 |
147 | 36 | ||
148 | 37 | diff view generated by jsdifflib |
1 | The MPS2 AN505 FPGA image includes a "FPGA control block" | 1 | Optimize the MVE VMVN insn by using TCG vector ops when possible. |
---|---|---|---|
2 | which is a small set of registers handling LEDs, buttons | ||
3 | and some counters. | ||
4 | 2 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-14-peter.maydell@linaro.org | 5 | Message-id: 20210913095440.13462-9-peter.maydell@linaro.org |
8 | --- | 6 | --- |
9 | hw/misc/Makefile.objs | 1 + | 7 | target/arm/translate-mve.c | 2 +- |
10 | include/hw/misc/mps2-fpgaio.h | 43 ++++++++++ | 8 | 1 file changed, 1 insertion(+), 1 deletion(-) |
11 | hw/misc/mps2-fpgaio.c | 176 ++++++++++++++++++++++++++++++++++++++++ | ||
12 | default-configs/arm-softmmu.mak | 1 + | ||
13 | hw/misc/trace-events | 6 ++ | ||
14 | 5 files changed, 227 insertions(+) | ||
15 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
16 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
17 | 9 | ||
18 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 10 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
19 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/misc/Makefile.objs | 12 | --- a/target/arm/translate-mve.c |
21 | +++ b/hw/misc/Makefile.objs | 13 | +++ b/target/arm/translate-mve.c |
22 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | 14 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_1op *a) |
23 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | 15 | |
24 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | 16 | static bool trans_VMVN(DisasContext *s, arg_1op *a) |
25 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 17 | { |
26 | +obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 18 | - return do_1op(s, a, gen_helper_mve_vmvn); |
27 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 19 | + return do_1op_vec(s, a, gen_helper_mve_vmvn, tcg_gen_gvec_not); |
28 | 20 | } | |
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 21 | |
30 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h | 22 | static bool trans_VABS_fp(DisasContext *s, arg_1op *a) |
31 | new file mode 100644 | ||
32 | index XXXXXXX..XXXXXXX | ||
33 | --- /dev/null | ||
34 | +++ b/include/hw/misc/mps2-fpgaio.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | +/* | ||
37 | + * ARM MPS2 FPGAIO emulation | ||
38 | + * | ||
39 | + * Copyright (c) 2018 Linaro Limited | ||
40 | + * Written by Peter Maydell | ||
41 | + * | ||
42 | + * This program is free software; you can redistribute it and/or modify | ||
43 | + * it under the terms of the GNU General Public License version 2 or | ||
44 | + * (at your option) any later version. | ||
45 | + */ | ||
46 | + | ||
47 | +/* This is a model of the FPGAIO register block in the AN505 | ||
48 | + * FPGA image for the MPS2 dev board; it is documented in the | ||
49 | + * application note: | ||
50 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
51 | + * | ||
52 | + * QEMU interface: | ||
53 | + * + sysbus MMIO region 0: the register bank | ||
54 | + */ | ||
55 | + | ||
56 | +#ifndef MPS2_FPGAIO_H | ||
57 | +#define MPS2_FPGAIO_H | ||
58 | + | ||
59 | +#include "hw/sysbus.h" | ||
60 | + | ||
61 | +#define TYPE_MPS2_FPGAIO "mps2-fpgaio" | ||
62 | +#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO) | ||
63 | + | ||
64 | +typedef struct { | ||
65 | + /*< private >*/ | ||
66 | + SysBusDevice parent_obj; | ||
67 | + | ||
68 | + /*< public >*/ | ||
69 | + MemoryRegion iomem; | ||
70 | + | ||
71 | + uint32_t led0; | ||
72 | + uint32_t prescale; | ||
73 | + uint32_t misc; | ||
74 | + | ||
75 | + uint32_t prescale_clk; | ||
76 | +} MPS2FPGAIO; | ||
77 | + | ||
78 | +#endif | ||
79 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | ||
80 | new file mode 100644 | ||
81 | index XXXXXXX..XXXXXXX | ||
82 | --- /dev/null | ||
83 | +++ b/hw/misc/mps2-fpgaio.c | ||
84 | @@ -XXX,XX +XXX,XX @@ | ||
85 | +/* | ||
86 | + * ARM MPS2 AN505 FPGAIO emulation | ||
87 | + * | ||
88 | + * Copyright (c) 2018 Linaro Limited | ||
89 | + * Written by Peter Maydell | ||
90 | + * | ||
91 | + * This program is free software; you can redistribute it and/or modify | ||
92 | + * it under the terms of the GNU General Public License version 2 or | ||
93 | + * (at your option) any later version. | ||
94 | + */ | ||
95 | + | ||
96 | +/* This is a model of the "FPGA system control and I/O" block found | ||
97 | + * in the AN505 FPGA image for the MPS2 devboard. | ||
98 | + * It is documented in AN505: | ||
99 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
100 | + */ | ||
101 | + | ||
102 | +#include "qemu/osdep.h" | ||
103 | +#include "qemu/log.h" | ||
104 | +#include "qapi/error.h" | ||
105 | +#include "trace.h" | ||
106 | +#include "hw/sysbus.h" | ||
107 | +#include "hw/registerfields.h" | ||
108 | +#include "hw/misc/mps2-fpgaio.h" | ||
109 | + | ||
110 | +REG32(LED0, 0) | ||
111 | +REG32(BUTTON, 8) | ||
112 | +REG32(CLK1HZ, 0x10) | ||
113 | +REG32(CLK100HZ, 0x14) | ||
114 | +REG32(COUNTER, 0x18) | ||
115 | +REG32(PRESCALE, 0x1c) | ||
116 | +REG32(PSCNTR, 0x20) | ||
117 | +REG32(MISC, 0x4c) | ||
118 | + | ||
119 | +static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) | ||
120 | +{ | ||
121 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | ||
122 | + uint64_t r; | ||
123 | + | ||
124 | + switch (offset) { | ||
125 | + case A_LED0: | ||
126 | + r = s->led0; | ||
127 | + break; | ||
128 | + case A_BUTTON: | ||
129 | + /* User-pressable board buttons. We don't model that, so just return | ||
130 | + * zeroes. | ||
131 | + */ | ||
132 | + r = 0; | ||
133 | + break; | ||
134 | + case A_PRESCALE: | ||
135 | + r = s->prescale; | ||
136 | + break; | ||
137 | + case A_MISC: | ||
138 | + r = s->misc; | ||
139 | + break; | ||
140 | + case A_CLK1HZ: | ||
141 | + case A_CLK100HZ: | ||
142 | + case A_COUNTER: | ||
143 | + case A_PSCNTR: | ||
144 | + /* These are all upcounters of various frequencies. */ | ||
145 | + qemu_log_mask(LOG_UNIMP, "MPS2 FPGAIO: counters unimplemented\n"); | ||
146 | + r = 0; | ||
147 | + break; | ||
148 | + default: | ||
149 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
150 | + "MPS2 FPGAIO read: bad offset %x\n", (int) offset); | ||
151 | + r = 0; | ||
152 | + break; | ||
153 | + } | ||
154 | + | ||
155 | + trace_mps2_fpgaio_read(offset, r, size); | ||
156 | + return r; | ||
157 | +} | ||
158 | + | ||
159 | +static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, | ||
160 | + unsigned size) | ||
161 | +{ | ||
162 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | ||
163 | + | ||
164 | + trace_mps2_fpgaio_write(offset, value, size); | ||
165 | + | ||
166 | + switch (offset) { | ||
167 | + case A_LED0: | ||
168 | + /* LED bits [1:0] control board LEDs. We don't currently have | ||
169 | + * a mechanism for displaying this graphically, so use a trace event. | ||
170 | + */ | ||
171 | + trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', | ||
172 | + value & 0x01 ? '*' : '.'); | ||
173 | + s->led0 = value & 0x3; | ||
174 | + break; | ||
175 | + case A_PRESCALE: | ||
176 | + s->prescale = value; | ||
177 | + break; | ||
178 | + case A_MISC: | ||
179 | + /* These are control bits for some of the other devices on the | ||
180 | + * board (SPI, CLCD, etc). We don't implement that yet, so just | ||
181 | + * make the bits read as written. | ||
182 | + */ | ||
183 | + qemu_log_mask(LOG_UNIMP, | ||
184 | + "MPS2 FPGAIO: MISC control bits unimplemented\n"); | ||
185 | + s->misc = value; | ||
186 | + break; | ||
187 | + default: | ||
188 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
189 | + "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); | ||
190 | + break; | ||
191 | + } | ||
192 | +} | ||
193 | + | ||
194 | +static const MemoryRegionOps mps2_fpgaio_ops = { | ||
195 | + .read = mps2_fpgaio_read, | ||
196 | + .write = mps2_fpgaio_write, | ||
197 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
198 | +}; | ||
199 | + | ||
200 | +static void mps2_fpgaio_reset(DeviceState *dev) | ||
201 | +{ | ||
202 | + MPS2FPGAIO *s = MPS2_FPGAIO(dev); | ||
203 | + | ||
204 | + trace_mps2_fpgaio_reset(); | ||
205 | + s->led0 = 0; | ||
206 | + s->prescale = 0; | ||
207 | + s->misc = 0; | ||
208 | +} | ||
209 | + | ||
210 | +static void mps2_fpgaio_init(Object *obj) | ||
211 | +{ | ||
212 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
213 | + MPS2FPGAIO *s = MPS2_FPGAIO(obj); | ||
214 | + | ||
215 | + memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, | ||
216 | + "mps2-fpgaio", 0x1000); | ||
217 | + sysbus_init_mmio(sbd, &s->iomem); | ||
218 | +} | ||
219 | + | ||
220 | +static const VMStateDescription mps2_fpgaio_vmstate = { | ||
221 | + .name = "mps2-fpgaio", | ||
222 | + .version_id = 1, | ||
223 | + .minimum_version_id = 1, | ||
224 | + .fields = (VMStateField[]) { | ||
225 | + VMSTATE_UINT32(led0, MPS2FPGAIO), | ||
226 | + VMSTATE_UINT32(prescale, MPS2FPGAIO), | ||
227 | + VMSTATE_UINT32(misc, MPS2FPGAIO), | ||
228 | + VMSTATE_END_OF_LIST() | ||
229 | + } | ||
230 | +}; | ||
231 | + | ||
232 | +static Property mps2_fpgaio_properties[] = { | ||
233 | + /* Frequency of the prescale counter */ | ||
234 | + DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), | ||
235 | + DEFINE_PROP_END_OF_LIST(), | ||
236 | +}; | ||
237 | + | ||
238 | +static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) | ||
239 | +{ | ||
240 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
241 | + | ||
242 | + dc->vmsd = &mps2_fpgaio_vmstate; | ||
243 | + dc->reset = mps2_fpgaio_reset; | ||
244 | + dc->props = mps2_fpgaio_properties; | ||
245 | +} | ||
246 | + | ||
247 | +static const TypeInfo mps2_fpgaio_info = { | ||
248 | + .name = TYPE_MPS2_FPGAIO, | ||
249 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
250 | + .instance_size = sizeof(MPS2FPGAIO), | ||
251 | + .instance_init = mps2_fpgaio_init, | ||
252 | + .class_init = mps2_fpgaio_class_init, | ||
253 | +}; | ||
254 | + | ||
255 | +static void mps2_fpgaio_register_types(void) | ||
256 | +{ | ||
257 | + type_register_static(&mps2_fpgaio_info); | ||
258 | +} | ||
259 | + | ||
260 | +type_init(mps2_fpgaio_register_types); | ||
261 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
262 | index XXXXXXX..XXXXXXX 100644 | ||
263 | --- a/default-configs/arm-softmmu.mak | ||
264 | +++ b/default-configs/arm-softmmu.mak | ||
265 | @@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y | ||
266 | CONFIG_CMSDK_APB_TIMER=y | ||
267 | CONFIG_CMSDK_APB_UART=y | ||
268 | |||
269 | +CONFIG_MPS2_FPGAIO=y | ||
270 | CONFIG_MPS2_SCC=y | ||
271 | |||
272 | CONFIG_VERSATILE_PCI=y | ||
273 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
274 | index XXXXXXX..XXXXXXX 100644 | ||
275 | --- a/hw/misc/trace-events | ||
276 | +++ b/hw/misc/trace-events | ||
277 | @@ -XXX,XX +XXX,XX @@ mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, | ||
278 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 | ||
279 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 | ||
280 | |||
281 | +# hw/misc/mps2_fpgaio.c | ||
282 | +mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
283 | +mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
284 | +mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" | ||
285 | +mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c" | ||
286 | + | ||
287 | # hw/misc/msf2-sysreg.c | ||
288 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 | ||
289 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32 | ||
290 | -- | 23 | -- |
291 | 2.16.2 | 24 | 2.20.1 |
292 | 25 | ||
293 | 26 | diff view generated by jsdifflib |
1 | The Arm IoT Kit includes a "security controller" which is largely a | 1 | Optimize the MVE VSHL and VSHR immediate forms by using TCG vector |
---|---|---|---|
2 | collection of registers for controlling the PPCs and other bits of | 2 | ops when possible. |
3 | glue in the system. This commit provides the initial skeleton of the | ||
4 | device, implementing just the ID registers, and a couple of read-only | ||
5 | read-as-zero registers. | ||
6 | 3 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20180220180325.29818-16-peter.maydell@linaro.org | 6 | Message-id: 20210913095440.13462-10-peter.maydell@linaro.org |
10 | --- | 7 | --- |
11 | hw/misc/Makefile.objs | 1 + | 8 | target/arm/translate-mve.c | 83 +++++++++++++++++++++++++++++--------- |
12 | include/hw/misc/iotkit-secctl.h | 39 ++++ | 9 | 1 file changed, 63 insertions(+), 20 deletions(-) |
13 | hw/misc/iotkit-secctl.c | 448 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | default-configs/arm-softmmu.mak | 1 + | ||
15 | hw/misc/trace-events | 7 + | ||
16 | 5 files changed, 496 insertions(+) | ||
17 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
18 | create mode 100644 hw/misc/iotkit-secctl.c | ||
19 | 10 | ||
20 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 11 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
21 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/misc/Makefile.objs | 13 | --- a/target/arm/translate-mve.c |
23 | +++ b/hw/misc/Makefile.objs | 14 | +++ b/target/arm/translate-mve.c |
24 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) |
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 16 | return do_1imm(s, a, fn); |
26 | 17 | } | |
27 | obj-$(CONFIG_TZ_PPC) += tz-ppc.o | 18 | |
28 | +obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o | 19 | -static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
29 | 20 | - bool negateshift) | |
30 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 21 | +static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
31 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | 22 | + bool negateshift, GVecGen2iFn vecfn) |
32 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 23 | { |
33 | new file mode 100644 | 24 | TCGv_ptr qd, qm; |
34 | index XXXXXXX..XXXXXXX | 25 | int shift = a->shift; |
35 | --- /dev/null | 26 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
36 | +++ b/include/hw/misc/iotkit-secctl.h | 27 | shift = -shift; |
37 | @@ -XXX,XX +XXX,XX @@ | 28 | } |
38 | +/* | 29 | |
39 | + * ARM IoT Kit security controller | 30 | - qd = mve_qreg_ptr(a->qd); |
40 | + * | 31 | - qm = mve_qreg_ptr(a->qm); |
41 | + * Copyright (c) 2018 Linaro Limited | 32 | - fn(cpu_env, qd, qm, tcg_constant_i32(shift)); |
42 | + * Written by Peter Maydell | 33 | - tcg_temp_free_ptr(qd); |
43 | + * | 34 | - tcg_temp_free_ptr(qm); |
44 | + * This program is free software; you can redistribute it and/or modify | 35 | + if (vecfn && mve_no_predication(s)) { |
45 | + * it under the terms of the GNU General Public License version 2 or | 36 | + vecfn(a->size, mve_qreg_offset(a->qd), mve_qreg_offset(a->qm), |
46 | + * (at your option) any later version. | 37 | + shift, 16, 16); |
47 | + */ | 38 | + } else { |
48 | + | 39 | + qd = mve_qreg_ptr(a->qd); |
49 | +/* This is a model of the security controller which is part of the | 40 | + qm = mve_qreg_ptr(a->qm); |
50 | + * Arm IoT Kit and documented in | 41 | + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); |
51 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 42 | + tcg_temp_free_ptr(qd); |
52 | + * | 43 | + tcg_temp_free_ptr(qm); |
53 | + * QEMU interface: | 44 | + } |
54 | + * + sysbus MMIO region 0 is the "secure privilege control block" registers | 45 | mve_update_eci(s); |
55 | + * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 46 | return true; |
56 | + */ | 47 | } |
57 | + | 48 | |
58 | +#ifndef IOTKIT_SECCTL_H | 49 | -#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ |
59 | +#define IOTKIT_SECCTL_H | 50 | - static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
60 | + | 51 | - { \ |
61 | +#include "hw/sysbus.h" | 52 | - static MVEGenTwoOpShiftFn * const fns[] = { \ |
62 | + | 53 | - gen_helper_mve_##FN##b, \ |
63 | +#define TYPE_IOTKIT_SECCTL "iotkit-secctl" | 54 | - gen_helper_mve_##FN##h, \ |
64 | +#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | 55 | - gen_helper_mve_##FN##w, \ |
65 | + | 56 | - NULL, \ |
66 | +typedef struct IoTKitSecCtl { | 57 | - }; \ |
67 | + /*< private >*/ | 58 | - return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ |
68 | + SysBusDevice parent_obj; | 59 | +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
69 | + | 60 | + bool negateshift) |
70 | + /*< public >*/ | ||
71 | + | ||
72 | + MemoryRegion s_regs; | ||
73 | + MemoryRegion ns_regs; | ||
74 | +} IoTKitSecCtl; | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
78 | new file mode 100644 | ||
79 | index XXXXXXX..XXXXXXX | ||
80 | --- /dev/null | ||
81 | +++ b/hw/misc/iotkit-secctl.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | ||
83 | +/* | ||
84 | + * Arm IoT Kit security controller | ||
85 | + * | ||
86 | + * Copyright (c) 2018 Linaro Limited | ||
87 | + * Written by Peter Maydell | ||
88 | + * | ||
89 | + * This program is free software; you can redistribute it and/or modify | ||
90 | + * it under the terms of the GNU General Public License version 2 or | ||
91 | + * (at your option) any later version. | ||
92 | + */ | ||
93 | + | ||
94 | +#include "qemu/osdep.h" | ||
95 | +#include "qemu/log.h" | ||
96 | +#include "qapi/error.h" | ||
97 | +#include "trace.h" | ||
98 | +#include "hw/sysbus.h" | ||
99 | +#include "hw/registerfields.h" | ||
100 | +#include "hw/misc/iotkit-secctl.h" | ||
101 | + | ||
102 | +/* Registers in the secure privilege control block */ | ||
103 | +REG32(SECRESPCFG, 0x10) | ||
104 | +REG32(NSCCFG, 0x14) | ||
105 | +REG32(SECMPCINTSTATUS, 0x1c) | ||
106 | +REG32(SECPPCINTSTAT, 0x20) | ||
107 | +REG32(SECPPCINTCLR, 0x24) | ||
108 | +REG32(SECPPCINTEN, 0x28) | ||
109 | +REG32(SECMSCINTSTAT, 0x30) | ||
110 | +REG32(SECMSCINTCLR, 0x34) | ||
111 | +REG32(SECMSCINTEN, 0x38) | ||
112 | +REG32(BRGINTSTAT, 0x40) | ||
113 | +REG32(BRGINTCLR, 0x44) | ||
114 | +REG32(BRGINTEN, 0x48) | ||
115 | +REG32(AHBNSPPC0, 0x50) | ||
116 | +REG32(AHBNSPPCEXP0, 0x60) | ||
117 | +REG32(AHBNSPPCEXP1, 0x64) | ||
118 | +REG32(AHBNSPPCEXP2, 0x68) | ||
119 | +REG32(AHBNSPPCEXP3, 0x6c) | ||
120 | +REG32(APBNSPPC0, 0x70) | ||
121 | +REG32(APBNSPPC1, 0x74) | ||
122 | +REG32(APBNSPPCEXP0, 0x80) | ||
123 | +REG32(APBNSPPCEXP1, 0x84) | ||
124 | +REG32(APBNSPPCEXP2, 0x88) | ||
125 | +REG32(APBNSPPCEXP3, 0x8c) | ||
126 | +REG32(AHBSPPPC0, 0x90) | ||
127 | +REG32(AHBSPPPCEXP0, 0xa0) | ||
128 | +REG32(AHBSPPPCEXP1, 0xa4) | ||
129 | +REG32(AHBSPPPCEXP2, 0xa8) | ||
130 | +REG32(AHBSPPPCEXP3, 0xac) | ||
131 | +REG32(APBSPPPC0, 0xb0) | ||
132 | +REG32(APBSPPPC1, 0xb4) | ||
133 | +REG32(APBSPPPCEXP0, 0xc0) | ||
134 | +REG32(APBSPPPCEXP1, 0xc4) | ||
135 | +REG32(APBSPPPCEXP2, 0xc8) | ||
136 | +REG32(APBSPPPCEXP3, 0xcc) | ||
137 | +REG32(NSMSCEXP, 0xd0) | ||
138 | +REG32(PID4, 0xfd0) | ||
139 | +REG32(PID5, 0xfd4) | ||
140 | +REG32(PID6, 0xfd8) | ||
141 | +REG32(PID7, 0xfdc) | ||
142 | +REG32(PID0, 0xfe0) | ||
143 | +REG32(PID1, 0xfe4) | ||
144 | +REG32(PID2, 0xfe8) | ||
145 | +REG32(PID3, 0xfec) | ||
146 | +REG32(CID0, 0xff0) | ||
147 | +REG32(CID1, 0xff4) | ||
148 | +REG32(CID2, 0xff8) | ||
149 | +REG32(CID3, 0xffc) | ||
150 | + | ||
151 | +/* Registers in the non-secure privilege control block */ | ||
152 | +REG32(AHBNSPPPC0, 0x90) | ||
153 | +REG32(AHBNSPPPCEXP0, 0xa0) | ||
154 | +REG32(AHBNSPPPCEXP1, 0xa4) | ||
155 | +REG32(AHBNSPPPCEXP2, 0xa8) | ||
156 | +REG32(AHBNSPPPCEXP3, 0xac) | ||
157 | +REG32(APBNSPPPC0, 0xb0) | ||
158 | +REG32(APBNSPPPC1, 0xb4) | ||
159 | +REG32(APBNSPPPCEXP0, 0xc0) | ||
160 | +REG32(APBNSPPPCEXP1, 0xc4) | ||
161 | +REG32(APBNSPPPCEXP2, 0xc8) | ||
162 | +REG32(APBNSPPPCEXP3, 0xcc) | ||
163 | +/* PID and CID registers are also present in the NS block */ | ||
164 | + | ||
165 | +static const uint8_t iotkit_secctl_s_idregs[] = { | ||
166 | + 0x04, 0x00, 0x00, 0x00, | ||
167 | + 0x52, 0xb8, 0x0b, 0x00, | ||
168 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
169 | +}; | ||
170 | + | ||
171 | +static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
172 | + 0x04, 0x00, 0x00, 0x00, | ||
173 | + 0x53, 0xb8, 0x0b, 0x00, | ||
174 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
175 | +}; | ||
176 | + | ||
177 | +static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
178 | + uint64_t *pdata, | ||
179 | + unsigned size, MemTxAttrs attrs) | ||
180 | +{ | 61 | +{ |
181 | + uint64_t r; | 62 | + return do_2shift_vec(s, a, fn, negateshift, NULL); |
182 | + uint32_t offset = addr & ~0x3; | ||
183 | + | ||
184 | + switch (offset) { | ||
185 | + case A_AHBNSPPC0: | ||
186 | + case A_AHBSPPPC0: | ||
187 | + r = 0; | ||
188 | + break; | ||
189 | + case A_SECRESPCFG: | ||
190 | + case A_NSCCFG: | ||
191 | + case A_SECMPCINTSTATUS: | ||
192 | + case A_SECPPCINTSTAT: | ||
193 | + case A_SECPPCINTEN: | ||
194 | + case A_SECMSCINTSTAT: | ||
195 | + case A_SECMSCINTEN: | ||
196 | + case A_BRGINTSTAT: | ||
197 | + case A_BRGINTEN: | ||
198 | + case A_AHBNSPPCEXP0: | ||
199 | + case A_AHBNSPPCEXP1: | ||
200 | + case A_AHBNSPPCEXP2: | ||
201 | + case A_AHBNSPPCEXP3: | ||
202 | + case A_APBNSPPC0: | ||
203 | + case A_APBNSPPC1: | ||
204 | + case A_APBNSPPCEXP0: | ||
205 | + case A_APBNSPPCEXP1: | ||
206 | + case A_APBNSPPCEXP2: | ||
207 | + case A_APBNSPPCEXP3: | ||
208 | + case A_AHBSPPPCEXP0: | ||
209 | + case A_AHBSPPPCEXP1: | ||
210 | + case A_AHBSPPPCEXP2: | ||
211 | + case A_AHBSPPPCEXP3: | ||
212 | + case A_APBSPPPC0: | ||
213 | + case A_APBSPPPC1: | ||
214 | + case A_APBSPPPCEXP0: | ||
215 | + case A_APBSPPPCEXP1: | ||
216 | + case A_APBSPPPCEXP2: | ||
217 | + case A_APBSPPPCEXP3: | ||
218 | + case A_NSMSCEXP: | ||
219 | + qemu_log_mask(LOG_UNIMP, | ||
220 | + "IoTKit SecCtl S block read: " | ||
221 | + "unimplemented offset 0x%x\n", offset); | ||
222 | + r = 0; | ||
223 | + break; | ||
224 | + case A_PID4: | ||
225 | + case A_PID5: | ||
226 | + case A_PID6: | ||
227 | + case A_PID7: | ||
228 | + case A_PID0: | ||
229 | + case A_PID1: | ||
230 | + case A_PID2: | ||
231 | + case A_PID3: | ||
232 | + case A_CID0: | ||
233 | + case A_CID1: | ||
234 | + case A_CID2: | ||
235 | + case A_CID3: | ||
236 | + r = iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; | ||
237 | + break; | ||
238 | + case A_SECPPCINTCLR: | ||
239 | + case A_SECMSCINTCLR: | ||
240 | + case A_BRGINTCLR: | ||
241 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
242 | + "IotKit SecCtl S block read: write-only offset 0x%x\n", | ||
243 | + offset); | ||
244 | + r = 0; | ||
245 | + break; | ||
246 | + default: | ||
247 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
248 | + "IotKit SecCtl S block read: bad offset 0x%x\n", offset); | ||
249 | + r = 0; | ||
250 | + break; | ||
251 | + } | ||
252 | + | ||
253 | + if (size != 4) { | ||
254 | + /* None of our registers are access-sensitive, so just pull the right | ||
255 | + * byte out of the word read result. | ||
256 | + */ | ||
257 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
258 | + } | ||
259 | + | ||
260 | + trace_iotkit_secctl_s_read(offset, r, size); | ||
261 | + *pdata = r; | ||
262 | + return MEMTX_OK; | ||
263 | +} | 63 | +} |
264 | + | 64 | + |
265 | +static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | 65 | +#define DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, VECFN) \ |
266 | + uint64_t value, | 66 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
267 | + unsigned size, MemTxAttrs attrs) | 67 | + { \ |
68 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
69 | + gen_helper_mve_##FN##b, \ | ||
70 | + gen_helper_mve_##FN##h, \ | ||
71 | + gen_helper_mve_##FN##w, \ | ||
72 | + NULL, \ | ||
73 | + }; \ | ||
74 | + return do_2shift_vec(s, a, fns[a->size], NEGATESHIFT, VECFN); \ | ||
75 | } | ||
76 | |||
77 | -DO_2SHIFT(VSHLI, vshli_u, false) | ||
78 | +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ | ||
79 | + DO_2SHIFT_VEC(INSN, FN, NEGATESHIFT, NULL) | ||
80 | + | ||
81 | +static void do_gvec_shri_s(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
82 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
268 | +{ | 83 | +{ |
269 | + uint32_t offset = addr; | 84 | + /* |
270 | + | 85 | + * We get here with a negated shift count, and we must handle |
271 | + trace_iotkit_secctl_s_write(offset, value, size); | 86 | + * shifts by the element size, which tcg_gen_gvec_sari() does not do. |
272 | + | 87 | + */ |
273 | + if (size != 4) { | 88 | + shift = -shift; |
274 | + /* Byte and halfword writes are ignored */ | 89 | + if (shift == (8 << vece)) { |
275 | + qemu_log_mask(LOG_GUEST_ERROR, | 90 | + shift--; |
276 | + "IotKit SecCtl S block write: bad size, ignored\n"); | ||
277 | + return MEMTX_OK; | ||
278 | + } | 91 | + } |
279 | + | 92 | + tcg_gen_gvec_sari(vece, dofs, aofs, shift, oprsz, maxsz); |
280 | + switch (offset) { | ||
281 | + case A_SECRESPCFG: | ||
282 | + case A_NSCCFG: | ||
283 | + case A_SECPPCINTCLR: | ||
284 | + case A_SECPPCINTEN: | ||
285 | + case A_SECMSCINTCLR: | ||
286 | + case A_SECMSCINTEN: | ||
287 | + case A_BRGINTCLR: | ||
288 | + case A_BRGINTEN: | ||
289 | + case A_AHBNSPPCEXP0: | ||
290 | + case A_AHBNSPPCEXP1: | ||
291 | + case A_AHBNSPPCEXP2: | ||
292 | + case A_AHBNSPPCEXP3: | ||
293 | + case A_APBNSPPC0: | ||
294 | + case A_APBNSPPC1: | ||
295 | + case A_APBNSPPCEXP0: | ||
296 | + case A_APBNSPPCEXP1: | ||
297 | + case A_APBNSPPCEXP2: | ||
298 | + case A_APBNSPPCEXP3: | ||
299 | + case A_AHBSPPPCEXP0: | ||
300 | + case A_AHBSPPPCEXP1: | ||
301 | + case A_AHBSPPPCEXP2: | ||
302 | + case A_AHBSPPPCEXP3: | ||
303 | + case A_APBSPPPC0: | ||
304 | + case A_APBSPPPC1: | ||
305 | + case A_APBSPPPCEXP0: | ||
306 | + case A_APBSPPPCEXP1: | ||
307 | + case A_APBSPPPCEXP2: | ||
308 | + case A_APBSPPPCEXP3: | ||
309 | + qemu_log_mask(LOG_UNIMP, | ||
310 | + "IoTKit SecCtl S block write: " | ||
311 | + "unimplemented offset 0x%x\n", offset); | ||
312 | + break; | ||
313 | + case A_SECMPCINTSTATUS: | ||
314 | + case A_SECPPCINTSTAT: | ||
315 | + case A_SECMSCINTSTAT: | ||
316 | + case A_BRGINTSTAT: | ||
317 | + case A_AHBNSPPC0: | ||
318 | + case A_AHBSPPPC0: | ||
319 | + case A_NSMSCEXP: | ||
320 | + case A_PID4: | ||
321 | + case A_PID5: | ||
322 | + case A_PID6: | ||
323 | + case A_PID7: | ||
324 | + case A_PID0: | ||
325 | + case A_PID1: | ||
326 | + case A_PID2: | ||
327 | + case A_PID3: | ||
328 | + case A_CID0: | ||
329 | + case A_CID1: | ||
330 | + case A_CID2: | ||
331 | + case A_CID3: | ||
332 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
333 | + "IoTKit SecCtl S block write: " | ||
334 | + "read-only offset 0x%x\n", offset); | ||
335 | + break; | ||
336 | + default: | ||
337 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
338 | + "IotKit SecCtl S block write: bad offset 0x%x\n", | ||
339 | + offset); | ||
340 | + break; | ||
341 | + } | ||
342 | + | ||
343 | + return MEMTX_OK; | ||
344 | +} | 93 | +} |
345 | + | 94 | + |
346 | +static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | 95 | +static void do_gvec_shri_u(unsigned vece, uint32_t dofs, uint32_t aofs, |
347 | + uint64_t *pdata, | 96 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) |
348 | + unsigned size, MemTxAttrs attrs) | ||
349 | +{ | 97 | +{ |
350 | + uint64_t r; | 98 | + /* |
351 | + uint32_t offset = addr & ~0x3; | 99 | + * We get here with a negated shift count, and we must handle |
352 | + | 100 | + * shifts by the element size, which tcg_gen_gvec_shri() does not do. |
353 | + switch (offset) { | 101 | + */ |
354 | + case A_AHBNSPPPC0: | 102 | + shift = -shift; |
355 | + r = 0; | 103 | + if (shift == (8 << vece)) { |
356 | + break; | 104 | + tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, 0); |
357 | + case A_AHBNSPPPCEXP0: | 105 | + } else { |
358 | + case A_AHBNSPPPCEXP1: | 106 | + tcg_gen_gvec_shri(vece, dofs, aofs, shift, oprsz, maxsz); |
359 | + case A_AHBNSPPPCEXP2: | ||
360 | + case A_AHBNSPPPCEXP3: | ||
361 | + case A_APBNSPPPC0: | ||
362 | + case A_APBNSPPPC1: | ||
363 | + case A_APBNSPPPCEXP0: | ||
364 | + case A_APBNSPPPCEXP1: | ||
365 | + case A_APBNSPPPCEXP2: | ||
366 | + case A_APBNSPPPCEXP3: | ||
367 | + qemu_log_mask(LOG_UNIMP, | ||
368 | + "IoTKit SecCtl NS block read: " | ||
369 | + "unimplemented offset 0x%x\n", offset); | ||
370 | + break; | ||
371 | + case A_PID4: | ||
372 | + case A_PID5: | ||
373 | + case A_PID6: | ||
374 | + case A_PID7: | ||
375 | + case A_PID0: | ||
376 | + case A_PID1: | ||
377 | + case A_PID2: | ||
378 | + case A_PID3: | ||
379 | + case A_CID0: | ||
380 | + case A_CID1: | ||
381 | + case A_CID2: | ||
382 | + case A_CID3: | ||
383 | + r = iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; | ||
384 | + break; | ||
385 | + default: | ||
386 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
387 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
388 | + offset); | ||
389 | + r = 0; | ||
390 | + break; | ||
391 | + } | 107 | + } |
392 | + | ||
393 | + if (size != 4) { | ||
394 | + /* None of our registers are access-sensitive, so just pull the right | ||
395 | + * byte out of the word read result. | ||
396 | + */ | ||
397 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
398 | + } | ||
399 | + | ||
400 | + trace_iotkit_secctl_ns_read(offset, r, size); | ||
401 | + *pdata = r; | ||
402 | + return MEMTX_OK; | ||
403 | +} | 108 | +} |
404 | + | 109 | + |
405 | +static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | 110 | +DO_2SHIFT_VEC(VSHLI, vshli_u, false, tcg_gen_gvec_shli) |
406 | + uint64_t value, | 111 | DO_2SHIFT(VQSHLI_S, vqshli_s, false) |
407 | + unsigned size, MemTxAttrs attrs) | 112 | DO_2SHIFT(VQSHLI_U, vqshli_u, false) |
408 | +{ | 113 | DO_2SHIFT(VQSHLUI, vqshlui_s, false) |
409 | + uint32_t offset = addr; | 114 | /* These right shifts use a left-shift helper with negated shift count */ |
410 | + | 115 | -DO_2SHIFT(VSHRI_S, vshli_s, true) |
411 | + trace_iotkit_secctl_ns_write(offset, value, size); | 116 | -DO_2SHIFT(VSHRI_U, vshli_u, true) |
412 | + | 117 | +DO_2SHIFT_VEC(VSHRI_S, vshli_s, true, do_gvec_shri_s) |
413 | + if (size != 4) { | 118 | +DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u) |
414 | + /* Byte and halfword writes are ignored */ | 119 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) |
415 | + qemu_log_mask(LOG_GUEST_ERROR, | 120 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) |
416 | + "IotKit SecCtl NS block write: bad size, ignored\n"); | 121 | |
417 | + return MEMTX_OK; | ||
418 | + } | ||
419 | + | ||
420 | + switch (offset) { | ||
421 | + case A_AHBNSPPPCEXP0: | ||
422 | + case A_AHBNSPPPCEXP1: | ||
423 | + case A_AHBNSPPPCEXP2: | ||
424 | + case A_AHBNSPPPCEXP3: | ||
425 | + case A_APBNSPPPC0: | ||
426 | + case A_APBNSPPPC1: | ||
427 | + case A_APBNSPPPCEXP0: | ||
428 | + case A_APBNSPPPCEXP1: | ||
429 | + case A_APBNSPPPCEXP2: | ||
430 | + case A_APBNSPPPCEXP3: | ||
431 | + qemu_log_mask(LOG_UNIMP, | ||
432 | + "IoTKit SecCtl NS block write: " | ||
433 | + "unimplemented offset 0x%x\n", offset); | ||
434 | + break; | ||
435 | + case A_AHBNSPPPC0: | ||
436 | + case A_PID4: | ||
437 | + case A_PID5: | ||
438 | + case A_PID6: | ||
439 | + case A_PID7: | ||
440 | + case A_PID0: | ||
441 | + case A_PID1: | ||
442 | + case A_PID2: | ||
443 | + case A_PID3: | ||
444 | + case A_CID0: | ||
445 | + case A_CID1: | ||
446 | + case A_CID2: | ||
447 | + case A_CID3: | ||
448 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
449 | + "IoTKit SecCtl NS block write: " | ||
450 | + "read-only offset 0x%x\n", offset); | ||
451 | + break; | ||
452 | + default: | ||
453 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
454 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
455 | + offset); | ||
456 | + break; | ||
457 | + } | ||
458 | + | ||
459 | + return MEMTX_OK; | ||
460 | +} | ||
461 | + | ||
462 | +static const MemoryRegionOps iotkit_secctl_s_ops = { | ||
463 | + .read_with_attrs = iotkit_secctl_s_read, | ||
464 | + .write_with_attrs = iotkit_secctl_s_write, | ||
465 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
466 | + .valid.min_access_size = 1, | ||
467 | + .valid.max_access_size = 4, | ||
468 | + .impl.min_access_size = 1, | ||
469 | + .impl.max_access_size = 4, | ||
470 | +}; | ||
471 | + | ||
472 | +static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
473 | + .read_with_attrs = iotkit_secctl_ns_read, | ||
474 | + .write_with_attrs = iotkit_secctl_ns_write, | ||
475 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
476 | + .valid.min_access_size = 1, | ||
477 | + .valid.max_access_size = 4, | ||
478 | + .impl.min_access_size = 1, | ||
479 | + .impl.max_access_size = 4, | ||
480 | +}; | ||
481 | + | ||
482 | +static void iotkit_secctl_reset(DeviceState *dev) | ||
483 | +{ | ||
484 | + | ||
485 | +} | ||
486 | + | ||
487 | +static void iotkit_secctl_init(Object *obj) | ||
488 | +{ | ||
489 | + IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
490 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
491 | + | ||
492 | + memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | + s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | + memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops, | ||
495 | + s, "iotkit-secctl-ns-regs", 0x1000); | ||
496 | + sysbus_init_mmio(sbd, &s->s_regs); | ||
497 | + sysbus_init_mmio(sbd, &s->ns_regs); | ||
498 | +} | ||
499 | + | ||
500 | +static const VMStateDescription iotkit_secctl_vmstate = { | ||
501 | + .name = "iotkit-secctl", | ||
502 | + .version_id = 1, | ||
503 | + .minimum_version_id = 1, | ||
504 | + .fields = (VMStateField[]) { | ||
505 | + VMSTATE_END_OF_LIST() | ||
506 | + } | ||
507 | +}; | ||
508 | + | ||
509 | +static void iotkit_secctl_class_init(ObjectClass *klass, void *data) | ||
510 | +{ | ||
511 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
512 | + | ||
513 | + dc->vmsd = &iotkit_secctl_vmstate; | ||
514 | + dc->reset = iotkit_secctl_reset; | ||
515 | +} | ||
516 | + | ||
517 | +static const TypeInfo iotkit_secctl_info = { | ||
518 | + .name = TYPE_IOTKIT_SECCTL, | ||
519 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
520 | + .instance_size = sizeof(IoTKitSecCtl), | ||
521 | + .instance_init = iotkit_secctl_init, | ||
522 | + .class_init = iotkit_secctl_class_init, | ||
523 | +}; | ||
524 | + | ||
525 | +static void iotkit_secctl_register_types(void) | ||
526 | +{ | ||
527 | + type_register_static(&iotkit_secctl_info); | ||
528 | +} | ||
529 | + | ||
530 | +type_init(iotkit_secctl_register_types); | ||
531 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
532 | index XXXXXXX..XXXXXXX 100644 | ||
533 | --- a/default-configs/arm-softmmu.mak | ||
534 | +++ b/default-configs/arm-softmmu.mak | ||
535 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
536 | CONFIG_MPS2_SCC=y | ||
537 | |||
538 | CONFIG_TZ_PPC=y | ||
539 | +CONFIG_IOTKIT_SECCTL=y | ||
540 | |||
541 | CONFIG_VERSATILE_PCI=y | ||
542 | CONFIG_VERSATILE_I2C=y | ||
543 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
544 | index XXXXXXX..XXXXXXX 100644 | ||
545 | --- a/hw/misc/trace-events | ||
546 | +++ b/hw/misc/trace-events | ||
547 | @@ -XXX,XX +XXX,XX @@ tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
548 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
549 | tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
550 | tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
551 | + | ||
552 | +# hw/misc/iotkit-secctl.c | ||
553 | +iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
554 | +iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
555 | +iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
556 | +iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
557 | +iotkit_secctl_reset(void) "IoTKit SecCtl: reset" | ||
558 | -- | 122 | -- |
559 | 2.16.2 | 123 | 2.20.1 |
560 | 124 | ||
561 | 125 | diff view generated by jsdifflib |
1 | Add a model of the TrustZone peripheral protection controller (PPC), | 1 | Optimize the MVE VSHLL insns by using TCG vector ops when possible. |
---|---|---|---|
2 | which is used to gate transactions to non-TZ-aware peripherals so | 2 | This includes the VMOVL insn, which we handle in mve.decode as "VSHLL |
3 | that secure software can configure them to not be accessible to | 3 | with zero shift count". |
4 | non-secure software. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-15-peter.maydell@linaro.org | 7 | Message-id: 20210913095440.13462-11-peter.maydell@linaro.org |
9 | --- | 8 | --- |
10 | hw/misc/Makefile.objs | 2 + | 9 | target/arm/translate-mve.c | 67 +++++++++++++++++++++++++++++++++----- |
11 | include/hw/misc/tz-ppc.h | 101 ++++++++++++++ | 10 | 1 file changed, 59 insertions(+), 8 deletions(-) |
12 | hw/misc/tz-ppc.c | 302 ++++++++++++++++++++++++++++++++++++++++ | ||
13 | default-configs/arm-softmmu.mak | 2 + | ||
14 | hw/misc/trace-events | 11 ++ | ||
15 | 5 files changed, 418 insertions(+) | ||
16 | create mode 100644 include/hw/misc/tz-ppc.h | ||
17 | create mode 100644 hw/misc/tz-ppc.c | ||
18 | 11 | ||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 12 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
20 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/Makefile.objs | 14 | --- a/target/arm/translate-mve.c |
22 | +++ b/hw/misc/Makefile.objs | 15 | +++ b/target/arm/translate-mve.c |
23 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 16 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) |
24 | obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 17 | DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) |
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 18 | DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) |
26 | 19 | ||
27 | +obj-$(CONFIG_TZ_PPC) += tz-ppc.o | 20 | -#define DO_VSHLL(INSN, FN) \ |
28 | + | 21 | - static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 22 | - { \ |
30 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | 23 | - static MVEGenTwoOpShiftFn * const fns[] = { \ |
31 | obj-$(CONFIG_AUX) += auxbus.o | 24 | - gen_helper_mve_##FN##b, \ |
32 | diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h | 25 | - gen_helper_mve_##FN##h, \ |
33 | new file mode 100644 | 26 | - }; \ |
34 | index XXXXXXX..XXXXXXX | 27 | - return do_2shift(s, a, fns[a->size], false); \ |
35 | --- /dev/null | 28 | +#define DO_VSHLL(INSN, FN) \ |
36 | +++ b/include/hw/misc/tz-ppc.h | 29 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
37 | @@ -XXX,XX +XXX,XX @@ | 30 | + { \ |
31 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
32 | + gen_helper_mve_##FN##b, \ | ||
33 | + gen_helper_mve_##FN##h, \ | ||
34 | + }; \ | ||
35 | + return do_2shift_vec(s, a, fns[a->size], false, do_gvec_##FN); \ | ||
36 | } | ||
37 | |||
38 | +/* | 38 | +/* |
39 | + * ARM TrustZone peripheral protection controller emulation | 39 | + * For the VSHLL vector helpers, the vece is the size of the input |
40 | + * | 40 | + * (ie MO_8 or MO_16); the helpers want to work in the output size. |
41 | + * Copyright (c) 2018 Linaro Limited | 41 | + * The shift count can be 0..<input size>, inclusive. (0 is VMOVL.) |
42 | + * Written by Peter Maydell | ||
43 | + * | ||
44 | + * This program is free software; you can redistribute it and/or modify | ||
45 | + * it under the terms of the GNU General Public License version 2 or | ||
46 | + * (at your option) any later version. | ||
47 | + */ | 42 | + */ |
48 | + | 43 | +static void do_gvec_vshllbs(unsigned vece, uint32_t dofs, uint32_t aofs, |
49 | +/* This is a model of the TrustZone peripheral protection controller (PPC). | 44 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) |
50 | + * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM | ||
51 | + * (DDI 0571G): | ||
52 | + * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g | ||
53 | + * | ||
54 | + * The PPC sits in front of peripherals and allows secure software to | ||
55 | + * configure it to either pass through or reject transactions. | ||
56 | + * Rejected transactions may be configured to either be aborted, or to | ||
57 | + * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. | ||
58 | + * | ||
59 | + * The PPC has no register interface -- it is configured purely by a | ||
60 | + * collection of input signals from other hardware in the system. Typically | ||
61 | + * they are either hardwired or exposed in an ad-hoc register interface by | ||
62 | + * the SoC that uses the PPC. | ||
63 | + * | ||
64 | + * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC, | ||
65 | + * since the only difference between them is that the AHB version has a | ||
66 | + * "default" port which has no security checks applied. In QEMU the default | ||
67 | + * port can be emulated simply by wiring its downstream devices directly | ||
68 | + * into the parent address space, since the PPC does not need to intercept | ||
69 | + * transactions there. | ||
70 | + * | ||
71 | + * In the hardware, selection of which downstream port to use is done by | ||
72 | + * the user's decode logic asserting one of the hsel[] signals. In QEMU, | ||
73 | + * we provide 16 MMIO regions, one per port, and the user maps these into | ||
74 | + * the desired addresses to implement the address decode. | ||
75 | + * | ||
76 | + * QEMU interface: | ||
77 | + * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end | ||
78 | + * of each of the 16 ports of the PPC | ||
79 | + * + Property "port[0..15]": MemoryRegion defining the downstream device(s) | ||
80 | + * for each of the 16 ports of the PPC | ||
81 | + * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be | ||
82 | + * accessible to NonSecure transactions | ||
83 | + * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be | ||
84 | + * accessible to non-privileged transactions | ||
85 | + * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should | ||
86 | + * result in a transaction error, or 0 for the transaction to RAZ/WI | ||
87 | + * + Named GPIO input "irq_enable": set to 1 to enable interrupts | ||
88 | + * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt | ||
89 | + * + Named GPIO output "irq": set for a transaction-failed interrupt | ||
90 | + * + Property "NONSEC_MASK": if a bit is set in this mask then accesses to | ||
91 | + * the associated port do not have the TZ security check performed. (This | ||
92 | + * corresponds to the hardware allowing this to be set as a Verilog | ||
93 | + * parameter.) | ||
94 | + */ | ||
95 | + | ||
96 | +#ifndef TZ_PPC_H | ||
97 | +#define TZ_PPC_H | ||
98 | + | ||
99 | +#include "hw/sysbus.h" | ||
100 | + | ||
101 | +#define TYPE_TZ_PPC "tz-ppc" | ||
102 | +#define TZ_PPC(obj) OBJECT_CHECK(TZPPC, (obj), TYPE_TZ_PPC) | ||
103 | + | ||
104 | +#define TZ_NUM_PORTS 16 | ||
105 | + | ||
106 | +typedef struct TZPPC TZPPC; | ||
107 | + | ||
108 | +typedef struct TZPPCPort { | ||
109 | + TZPPC *ppc; | ||
110 | + MemoryRegion upstream; | ||
111 | + AddressSpace downstream_as; | ||
112 | + MemoryRegion *downstream; | ||
113 | +} TZPPCPort; | ||
114 | + | ||
115 | +struct TZPPC { | ||
116 | + /*< private >*/ | ||
117 | + SysBusDevice parent_obj; | ||
118 | + | ||
119 | + /*< public >*/ | ||
120 | + | ||
121 | + /* State: these just track the values of our input signals */ | ||
122 | + bool cfg_nonsec[TZ_NUM_PORTS]; | ||
123 | + bool cfg_ap[TZ_NUM_PORTS]; | ||
124 | + bool cfg_sec_resp; | ||
125 | + bool irq_enable; | ||
126 | + bool irq_clear; | ||
127 | + /* State: are we asserting irq ? */ | ||
128 | + bool irq_status; | ||
129 | + | ||
130 | + qemu_irq irq; | ||
131 | + | ||
132 | + /* Properties */ | ||
133 | + uint32_t nonsec_mask; | ||
134 | + | ||
135 | + TZPPCPort port[TZ_NUM_PORTS]; | ||
136 | +}; | ||
137 | + | ||
138 | +#endif | ||
139 | diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c | ||
140 | new file mode 100644 | ||
141 | index XXXXXXX..XXXXXXX | ||
142 | --- /dev/null | ||
143 | +++ b/hw/misc/tz-ppc.c | ||
144 | @@ -XXX,XX +XXX,XX @@ | ||
145 | +/* | ||
146 | + * ARM TrustZone peripheral protection controller emulation | ||
147 | + * | ||
148 | + * Copyright (c) 2018 Linaro Limited | ||
149 | + * Written by Peter Maydell | ||
150 | + * | ||
151 | + * This program is free software; you can redistribute it and/or modify | ||
152 | + * it under the terms of the GNU General Public License version 2 or | ||
153 | + * (at your option) any later version. | ||
154 | + */ | ||
155 | + | ||
156 | +#include "qemu/osdep.h" | ||
157 | +#include "qemu/log.h" | ||
158 | +#include "qapi/error.h" | ||
159 | +#include "trace.h" | ||
160 | +#include "hw/sysbus.h" | ||
161 | +#include "hw/registerfields.h" | ||
162 | +#include "hw/misc/tz-ppc.h" | ||
163 | + | ||
164 | +static void tz_ppc_update_irq(TZPPC *s) | ||
165 | +{ | 45 | +{ |
166 | + bool level = s->irq_status && s->irq_enable; | 46 | + unsigned ovece = vece + 1; |
167 | + | 47 | + unsigned ibits = vece == MO_8 ? 8 : 16; |
168 | + trace_tz_ppc_update_irq(level); | 48 | + tcg_gen_gvec_shli(ovece, dofs, aofs, ibits, oprsz, maxsz); |
169 | + qemu_set_irq(s->irq, level); | 49 | + tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz); |
170 | +} | 50 | +} |
171 | + | 51 | + |
172 | +static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) | 52 | +static void do_gvec_vshllbu(unsigned vece, uint32_t dofs, uint32_t aofs, |
53 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
173 | +{ | 54 | +{ |
174 | + TZPPC *s = TZ_PPC(opaque); | 55 | + unsigned ovece = vece + 1; |
175 | + | 56 | + tcg_gen_gvec_andi(ovece, dofs, aofs, |
176 | + assert(n < TZ_NUM_PORTS); | 57 | + ovece == MO_16 ? 0xff : 0xffff, oprsz, maxsz); |
177 | + trace_tz_ppc_cfg_nonsec(n, level); | 58 | + tcg_gen_gvec_shli(ovece, dofs, dofs, shift, oprsz, maxsz); |
178 | + s->cfg_nonsec[n] = level; | ||
179 | +} | 59 | +} |
180 | + | 60 | + |
181 | +static void tz_ppc_cfg_ap(void *opaque, int n, int level) | 61 | +static void do_gvec_vshllts(unsigned vece, uint32_t dofs, uint32_t aofs, |
62 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
182 | +{ | 63 | +{ |
183 | + TZPPC *s = TZ_PPC(opaque); | 64 | + unsigned ovece = vece + 1; |
184 | + | 65 | + unsigned ibits = vece == MO_8 ? 8 : 16; |
185 | + assert(n < TZ_NUM_PORTS); | 66 | + if (shift == 0) { |
186 | + trace_tz_ppc_cfg_ap(n, level); | 67 | + tcg_gen_gvec_sari(ovece, dofs, aofs, ibits, oprsz, maxsz); |
187 | + s->cfg_ap[n] = level; | 68 | + } else { |
188 | +} | 69 | + tcg_gen_gvec_andi(ovece, dofs, aofs, |
189 | + | 70 | + ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz); |
190 | +static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) | 71 | + tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz); |
191 | +{ | ||
192 | + TZPPC *s = TZ_PPC(opaque); | ||
193 | + | ||
194 | + trace_tz_ppc_cfg_sec_resp(level); | ||
195 | + s->cfg_sec_resp = level; | ||
196 | +} | ||
197 | + | ||
198 | +static void tz_ppc_irq_enable(void *opaque, int n, int level) | ||
199 | +{ | ||
200 | + TZPPC *s = TZ_PPC(opaque); | ||
201 | + | ||
202 | + trace_tz_ppc_irq_enable(level); | ||
203 | + s->irq_enable = level; | ||
204 | + tz_ppc_update_irq(s); | ||
205 | +} | ||
206 | + | ||
207 | +static void tz_ppc_irq_clear(void *opaque, int n, int level) | ||
208 | +{ | ||
209 | + TZPPC *s = TZ_PPC(opaque); | ||
210 | + | ||
211 | + trace_tz_ppc_irq_clear(level); | ||
212 | + | ||
213 | + s->irq_clear = level; | ||
214 | + if (level) { | ||
215 | + s->irq_status = false; | ||
216 | + tz_ppc_update_irq(s); | ||
217 | + } | 72 | + } |
218 | +} | 73 | +} |
219 | + | 74 | + |
220 | +static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) | 75 | +static void do_gvec_vshlltu(unsigned vece, uint32_t dofs, uint32_t aofs, |
76 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
221 | +{ | 77 | +{ |
222 | + /* Check whether to allow an access to port n; return true if | 78 | + unsigned ovece = vece + 1; |
223 | + * the check passes, and false if the transaction must be blocked. | 79 | + unsigned ibits = vece == MO_8 ? 8 : 16; |
224 | + * If the latter, the caller must check cfg_sec_resp to determine | 80 | + if (shift == 0) { |
225 | + * whether to abort or RAZ/WI the transaction. | 81 | + tcg_gen_gvec_shri(ovece, dofs, aofs, ibits, oprsz, maxsz); |
226 | + * The checks are: | 82 | + } else { |
227 | + * + nonsec_mask suppresses any check of the secure attribute | 83 | + tcg_gen_gvec_andi(ovece, dofs, aofs, |
228 | + * + otherwise, block if cfg_nonsec is 1 and transaction is secure, | 84 | + ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz); |
229 | + * or if cfg_nonsec is 0 and transaction is non-secure | 85 | + tcg_gen_gvec_shri(ovece, dofs, dofs, ibits - shift, oprsz, maxsz); |
230 | + * + block if transaction is usermode and cfg_ap is 0 | ||
231 | + */ | ||
232 | + if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || | ||
233 | + (attrs.user && !s->cfg_ap[n])) { | ||
234 | + /* Block the transaction. */ | ||
235 | + if (!s->irq_clear) { | ||
236 | + /* Note that holding irq_clear high suppresses interrupts */ | ||
237 | + s->irq_status = true; | ||
238 | + tz_ppc_update_irq(s); | ||
239 | + } | ||
240 | + return false; | ||
241 | + } | ||
242 | + return true; | ||
243 | +} | ||
244 | + | ||
245 | +static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, | ||
246 | + unsigned size, MemTxAttrs attrs) | ||
247 | +{ | ||
248 | + TZPPCPort *p = opaque; | ||
249 | + TZPPC *s = p->ppc; | ||
250 | + int n = p - s->port; | ||
251 | + AddressSpace *as = &p->downstream_as; | ||
252 | + uint64_t data; | ||
253 | + MemTxResult res; | ||
254 | + | ||
255 | + if (!tz_ppc_check(s, n, attrs)) { | ||
256 | + trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); | ||
257 | + if (s->cfg_sec_resp) { | ||
258 | + return MEMTX_ERROR; | ||
259 | + } else { | ||
260 | + *pdata = 0; | ||
261 | + return MEMTX_OK; | ||
262 | + } | ||
263 | + } | ||
264 | + | ||
265 | + switch (size) { | ||
266 | + case 1: | ||
267 | + data = address_space_ldub(as, addr, attrs, &res); | ||
268 | + break; | ||
269 | + case 2: | ||
270 | + data = address_space_lduw_le(as, addr, attrs, &res); | ||
271 | + break; | ||
272 | + case 4: | ||
273 | + data = address_space_ldl_le(as, addr, attrs, &res); | ||
274 | + break; | ||
275 | + case 8: | ||
276 | + data = address_space_ldq_le(as, addr, attrs, &res); | ||
277 | + break; | ||
278 | + default: | ||
279 | + g_assert_not_reached(); | ||
280 | + } | ||
281 | + *pdata = data; | ||
282 | + return res; | ||
283 | +} | ||
284 | + | ||
285 | +static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, | ||
286 | + unsigned size, MemTxAttrs attrs) | ||
287 | +{ | ||
288 | + TZPPCPort *p = opaque; | ||
289 | + TZPPC *s = p->ppc; | ||
290 | + AddressSpace *as = &p->downstream_as; | ||
291 | + int n = p - s->port; | ||
292 | + MemTxResult res; | ||
293 | + | ||
294 | + if (!tz_ppc_check(s, n, attrs)) { | ||
295 | + trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); | ||
296 | + if (s->cfg_sec_resp) { | ||
297 | + return MEMTX_ERROR; | ||
298 | + } else { | ||
299 | + return MEMTX_OK; | ||
300 | + } | ||
301 | + } | ||
302 | + | ||
303 | + switch (size) { | ||
304 | + case 1: | ||
305 | + address_space_stb(as, addr, val, attrs, &res); | ||
306 | + break; | ||
307 | + case 2: | ||
308 | + address_space_stw_le(as, addr, val, attrs, &res); | ||
309 | + break; | ||
310 | + case 4: | ||
311 | + address_space_stl_le(as, addr, val, attrs, &res); | ||
312 | + break; | ||
313 | + case 8: | ||
314 | + address_space_stq_le(as, addr, val, attrs, &res); | ||
315 | + break; | ||
316 | + default: | ||
317 | + g_assert_not_reached(); | ||
318 | + } | ||
319 | + return res; | ||
320 | +} | ||
321 | + | ||
322 | +static const MemoryRegionOps tz_ppc_ops = { | ||
323 | + .read_with_attrs = tz_ppc_read, | ||
324 | + .write_with_attrs = tz_ppc_write, | ||
325 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
326 | +}; | ||
327 | + | ||
328 | +static void tz_ppc_reset(DeviceState *dev) | ||
329 | +{ | ||
330 | + TZPPC *s = TZ_PPC(dev); | ||
331 | + | ||
332 | + trace_tz_ppc_reset(); | ||
333 | + s->cfg_sec_resp = false; | ||
334 | + memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); | ||
335 | + memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); | ||
336 | +} | ||
337 | + | ||
338 | +static void tz_ppc_init(Object *obj) | ||
339 | +{ | ||
340 | + DeviceState *dev = DEVICE(obj); | ||
341 | + TZPPC *s = TZ_PPC(obj); | ||
342 | + | ||
343 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); | ||
344 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); | ||
345 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); | ||
346 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); | ||
347 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); | ||
348 | + qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); | ||
349 | +} | ||
350 | + | ||
351 | +static void tz_ppc_realize(DeviceState *dev, Error **errp) | ||
352 | +{ | ||
353 | + Object *obj = OBJECT(dev); | ||
354 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
355 | + TZPPC *s = TZ_PPC(dev); | ||
356 | + int i; | ||
357 | + | ||
358 | + /* We can't create the upstream end of the port until realize, | ||
359 | + * as we don't know the size of the MR used as the downstream until then. | ||
360 | + */ | ||
361 | + for (i = 0; i < TZ_NUM_PORTS; i++) { | ||
362 | + TZPPCPort *port = &s->port[i]; | ||
363 | + char *name; | ||
364 | + uint64_t size; | ||
365 | + | ||
366 | + if (!port->downstream) { | ||
367 | + continue; | ||
368 | + } | ||
369 | + | ||
370 | + name = g_strdup_printf("tz-ppc-port[%d]", i); | ||
371 | + | ||
372 | + port->ppc = s; | ||
373 | + address_space_init(&port->downstream_as, port->downstream, name); | ||
374 | + | ||
375 | + size = memory_region_size(port->downstream); | ||
376 | + memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, | ||
377 | + port, name, size); | ||
378 | + sysbus_init_mmio(sbd, &port->upstream); | ||
379 | + g_free(name); | ||
380 | + } | 86 | + } |
381 | +} | 87 | +} |
382 | + | 88 | + |
383 | +static const VMStateDescription tz_ppc_vmstate = { | 89 | DO_VSHLL(VSHLL_BS, vshllbs) |
384 | + .name = "tz-ppc", | 90 | DO_VSHLL(VSHLL_BU, vshllbu) |
385 | + .version_id = 1, | 91 | DO_VSHLL(VSHLL_TS, vshllts) |
386 | + .minimum_version_id = 1, | ||
387 | + .fields = (VMStateField[]) { | ||
388 | + VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), | ||
389 | + VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), | ||
390 | + VMSTATE_BOOL(cfg_sec_resp, TZPPC), | ||
391 | + VMSTATE_BOOL(irq_enable, TZPPC), | ||
392 | + VMSTATE_BOOL(irq_clear, TZPPC), | ||
393 | + VMSTATE_BOOL(irq_status, TZPPC), | ||
394 | + VMSTATE_END_OF_LIST() | ||
395 | + } | ||
396 | +}; | ||
397 | + | ||
398 | +#define DEFINE_PORT(N) \ | ||
399 | + DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ | ||
400 | + TYPE_MEMORY_REGION, MemoryRegion *) | ||
401 | + | ||
402 | +static Property tz_ppc_properties[] = { | ||
403 | + DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), | ||
404 | + DEFINE_PORT(0), | ||
405 | + DEFINE_PORT(1), | ||
406 | + DEFINE_PORT(2), | ||
407 | + DEFINE_PORT(3), | ||
408 | + DEFINE_PORT(4), | ||
409 | + DEFINE_PORT(5), | ||
410 | + DEFINE_PORT(6), | ||
411 | + DEFINE_PORT(7), | ||
412 | + DEFINE_PORT(8), | ||
413 | + DEFINE_PORT(9), | ||
414 | + DEFINE_PORT(10), | ||
415 | + DEFINE_PORT(11), | ||
416 | + DEFINE_PORT(12), | ||
417 | + DEFINE_PORT(13), | ||
418 | + DEFINE_PORT(14), | ||
419 | + DEFINE_PORT(15), | ||
420 | + DEFINE_PROP_END_OF_LIST(), | ||
421 | +}; | ||
422 | + | ||
423 | +static void tz_ppc_class_init(ObjectClass *klass, void *data) | ||
424 | +{ | ||
425 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
426 | + | ||
427 | + dc->realize = tz_ppc_realize; | ||
428 | + dc->vmsd = &tz_ppc_vmstate; | ||
429 | + dc->reset = tz_ppc_reset; | ||
430 | + dc->props = tz_ppc_properties; | ||
431 | +} | ||
432 | + | ||
433 | +static const TypeInfo tz_ppc_info = { | ||
434 | + .name = TYPE_TZ_PPC, | ||
435 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
436 | + .instance_size = sizeof(TZPPC), | ||
437 | + .instance_init = tz_ppc_init, | ||
438 | + .class_init = tz_ppc_class_init, | ||
439 | +}; | ||
440 | + | ||
441 | +static void tz_ppc_register_types(void) | ||
442 | +{ | ||
443 | + type_register_static(&tz_ppc_info); | ||
444 | +} | ||
445 | + | ||
446 | +type_init(tz_ppc_register_types); | ||
447 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
448 | index XXXXXXX..XXXXXXX 100644 | ||
449 | --- a/default-configs/arm-softmmu.mak | ||
450 | +++ b/default-configs/arm-softmmu.mak | ||
451 | @@ -XXX,XX +XXX,XX @@ CONFIG_CMSDK_APB_UART=y | ||
452 | CONFIG_MPS2_FPGAIO=y | ||
453 | CONFIG_MPS2_SCC=y | ||
454 | |||
455 | +CONFIG_TZ_PPC=y | ||
456 | + | ||
457 | CONFIG_VERSATILE_PCI=y | ||
458 | CONFIG_VERSATILE_I2C=y | ||
459 | |||
460 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
461 | index XXXXXXX..XXXXXXX 100644 | ||
462 | --- a/hw/misc/trace-events | ||
463 | +++ b/hw/misc/trace-events | ||
464 | @@ -XXX,XX +XXX,XX @@ mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d co | ||
465 | mos6522_set_sr_int(void) "set sr_int" | ||
466 | mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 | ||
467 | mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" | ||
468 | + | ||
469 | +# hw/misc/tz-ppc.c | ||
470 | +tz_ppc_reset(void) "TZ PPC: reset" | ||
471 | +tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" | ||
472 | +tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" | ||
473 | +tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" | ||
474 | +tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" | ||
475 | +tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
476 | +tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
477 | +tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
478 | +tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
479 | -- | 92 | -- |
480 | 2.16.2 | 93 | 2.20.1 |
481 | 94 | ||
482 | 95 | diff view generated by jsdifflib |
1 | In some board or SoC models it is necessary to split a qemu_irq line | 1 | Optimize the MVE shift-and-insert insns by using TCG |
---|---|---|---|
2 | so that one input can feed multiple outputs. We currently have | 2 | vector ops when possible. |
3 | qemu_irq_split() for this, but that has several deficiencies: | ||
4 | * it can only handle splitting a line into two | ||
5 | * it unavoidably leaks memory, so it can't be used | ||
6 | in a device that can be deleted | ||
7 | |||
8 | Implement a qdev device that encapsulates splitting of IRQs, with a | ||
9 | configurable number of outputs. (This is in some ways the inverse of | ||
10 | the TYPE_OR_IRQ device.) | ||
11 | 3 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20180220180325.29818-13-peter.maydell@linaro.org | 6 | Message-id: 20210913095440.13462-12-peter.maydell@linaro.org |
15 | --- | 7 | --- |
16 | hw/core/Makefile.objs | 1 + | 8 | target/arm/translate-mve.c | 4 ++-- |
17 | include/hw/core/split-irq.h | 57 +++++++++++++++++++++++++++++ | 9 | 1 file changed, 2 insertions(+), 2 deletions(-) |
18 | include/hw/irq.h | 4 +- | ||
19 | hw/core/split-irq.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ | ||
20 | 4 files changed, 150 insertions(+), 1 deletion(-) | ||
21 | create mode 100644 include/hw/core/split-irq.h | ||
22 | create mode 100644 hw/core/split-irq.c | ||
23 | 10 | ||
24 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | 11 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
25 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/core/Makefile.objs | 13 | --- a/target/arm/translate-mve.c |
27 | +++ b/hw/core/Makefile.objs | 14 | +++ b/target/arm/translate-mve.c |
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_FITLOADER) += loader-fit.o | 15 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_VEC(VSHRI_U, vshli_u, true, do_gvec_shri_u) |
29 | common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o | 16 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) |
30 | common-obj-$(CONFIG_SOFTMMU) += register.o | 17 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) |
31 | common-obj-$(CONFIG_SOFTMMU) += or-irq.o | 18 | |
32 | +common-obj-$(CONFIG_SOFTMMU) += split-irq.o | 19 | -DO_2SHIFT(VSRI, vsri, false) |
33 | common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o | 20 | -DO_2SHIFT(VSLI, vsli, false) |
34 | 21 | +DO_2SHIFT_VEC(VSRI, vsri, false, gen_gvec_sri) | |
35 | obj-$(CONFIG_SOFTMMU) += generic-loader.o | 22 | +DO_2SHIFT_VEC(VSLI, vsli, false, gen_gvec_sli) |
36 | diff --git a/include/hw/core/split-irq.h b/include/hw/core/split-irq.h | 23 | |
37 | new file mode 100644 | 24 | #define DO_2SHIFT_FP(INSN, FN) \ |
38 | index XXXXXXX..XXXXXXX | 25 | static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
39 | --- /dev/null | ||
40 | +++ b/include/hw/core/split-irq.h | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | +/* | ||
43 | + * IRQ splitter device. | ||
44 | + * | ||
45 | + * Copyright (c) 2018 Linaro Limited. | ||
46 | + * Written by Peter Maydell | ||
47 | + * | ||
48 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
49 | + * of this software and associated documentation files (the "Software"), to deal | ||
50 | + * in the Software without restriction, including without limitation the rights | ||
51 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
52 | + * copies of the Software, and to permit persons to whom the Software is | ||
53 | + * furnished to do so, subject to the following conditions: | ||
54 | + * | ||
55 | + * The above copyright notice and this permission notice shall be included in | ||
56 | + * all copies or substantial portions of the Software. | ||
57 | + * | ||
58 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
59 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
60 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
61 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
62 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
63 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
64 | + * THE SOFTWARE. | ||
65 | + */ | ||
66 | + | ||
67 | +/* This is a simple device which has one GPIO input line and multiple | ||
68 | + * GPIO output lines. Any change on the input line is forwarded to all | ||
69 | + * of the outputs. | ||
70 | + * | ||
71 | + * QEMU interface: | ||
72 | + * + one unnamed GPIO input: the input line | ||
73 | + * + N unnamed GPIO outputs: the output lines | ||
74 | + * + QOM property "num-lines": sets the number of output lines | ||
75 | + */ | ||
76 | +#ifndef HW_SPLIT_IRQ_H | ||
77 | +#define HW_SPLIT_IRQ_H | ||
78 | + | ||
79 | +#include "hw/irq.h" | ||
80 | +#include "hw/sysbus.h" | ||
81 | +#include "qom/object.h" | ||
82 | + | ||
83 | +#define TYPE_SPLIT_IRQ "split-irq" | ||
84 | + | ||
85 | +#define MAX_SPLIT_LINES 16 | ||
86 | + | ||
87 | +typedef struct SplitIRQ SplitIRQ; | ||
88 | + | ||
89 | +#define SPLIT_IRQ(obj) OBJECT_CHECK(SplitIRQ, (obj), TYPE_SPLIT_IRQ) | ||
90 | + | ||
91 | +struct SplitIRQ { | ||
92 | + DeviceState parent_obj; | ||
93 | + | ||
94 | + qemu_irq out_irq[MAX_SPLIT_LINES]; | ||
95 | + uint16_t num_lines; | ||
96 | +}; | ||
97 | + | ||
98 | +#endif | ||
99 | diff --git a/include/hw/irq.h b/include/hw/irq.h | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/include/hw/irq.h | ||
102 | +++ b/include/hw/irq.h | ||
103 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | ||
104 | /* Returns a new IRQ with opposite polarity. */ | ||
105 | qemu_irq qemu_irq_invert(qemu_irq irq); | ||
106 | |||
107 | -/* Returns a new IRQ which feeds into both the passed IRQs */ | ||
108 | +/* Returns a new IRQ which feeds into both the passed IRQs. | ||
109 | + * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
110 | + */ | ||
111 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | ||
112 | |||
113 | /* Returns a new IRQ set which connects 1:1 to another IRQ set, which | ||
114 | diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c | ||
115 | new file mode 100644 | ||
116 | index XXXXXXX..XXXXXXX | ||
117 | --- /dev/null | ||
118 | +++ b/hw/core/split-irq.c | ||
119 | @@ -XXX,XX +XXX,XX @@ | ||
120 | +/* | ||
121 | + * IRQ splitter device. | ||
122 | + * | ||
123 | + * Copyright (c) 2018 Linaro Limited. | ||
124 | + * Written by Peter Maydell | ||
125 | + * | ||
126 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
127 | + * of this software and associated documentation files (the "Software"), to deal | ||
128 | + * in the Software without restriction, including without limitation the rights | ||
129 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
130 | + * copies of the Software, and to permit persons to whom the Software is | ||
131 | + * furnished to do so, subject to the following conditions: | ||
132 | + * | ||
133 | + * The above copyright notice and this permission notice shall be included in | ||
134 | + * all copies or substantial portions of the Software. | ||
135 | + * | ||
136 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
137 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
138 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
139 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
140 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
141 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
142 | + * THE SOFTWARE. | ||
143 | + */ | ||
144 | + | ||
145 | +#include "qemu/osdep.h" | ||
146 | +#include "hw/core/split-irq.h" | ||
147 | +#include "qapi/error.h" | ||
148 | + | ||
149 | +static void split_irq_handler(void *opaque, int n, int level) | ||
150 | +{ | ||
151 | + SplitIRQ *s = SPLIT_IRQ(opaque); | ||
152 | + int i; | ||
153 | + | ||
154 | + for (i = 0; i < s->num_lines; i++) { | ||
155 | + qemu_set_irq(s->out_irq[i], level); | ||
156 | + } | ||
157 | +} | ||
158 | + | ||
159 | +static void split_irq_init(Object *obj) | ||
160 | +{ | ||
161 | + qdev_init_gpio_in(DEVICE(obj), split_irq_handler, 1); | ||
162 | +} | ||
163 | + | ||
164 | +static void split_irq_realize(DeviceState *dev, Error **errp) | ||
165 | +{ | ||
166 | + SplitIRQ *s = SPLIT_IRQ(dev); | ||
167 | + | ||
168 | + if (s->num_lines < 1 || s->num_lines >= MAX_SPLIT_LINES) { | ||
169 | + error_setg(errp, | ||
170 | + "IRQ splitter number of lines %d is not between 1 and %d", | ||
171 | + s->num_lines, MAX_SPLIT_LINES); | ||
172 | + return; | ||
173 | + } | ||
174 | + | ||
175 | + qdev_init_gpio_out(dev, s->out_irq, s->num_lines); | ||
176 | +} | ||
177 | + | ||
178 | +static Property split_irq_properties[] = { | ||
179 | + DEFINE_PROP_UINT16("num-lines", SplitIRQ, num_lines, 1), | ||
180 | + DEFINE_PROP_END_OF_LIST(), | ||
181 | +}; | ||
182 | + | ||
183 | +static void split_irq_class_init(ObjectClass *klass, void *data) | ||
184 | +{ | ||
185 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
186 | + | ||
187 | + /* No state to reset or migrate */ | ||
188 | + dc->props = split_irq_properties; | ||
189 | + dc->realize = split_irq_realize; | ||
190 | + | ||
191 | + /* Reason: Needs to be wired up to work */ | ||
192 | + dc->user_creatable = false; | ||
193 | +} | ||
194 | + | ||
195 | +static const TypeInfo split_irq_type_info = { | ||
196 | + .name = TYPE_SPLIT_IRQ, | ||
197 | + .parent = TYPE_DEVICE, | ||
198 | + .instance_size = sizeof(SplitIRQ), | ||
199 | + .instance_init = split_irq_init, | ||
200 | + .class_init = split_irq_class_init, | ||
201 | +}; | ||
202 | + | ||
203 | +static void split_irq_register_types(void) | ||
204 | +{ | ||
205 | + type_register_static(&split_irq_type_info); | ||
206 | +} | ||
207 | + | ||
208 | +type_init(split_irq_register_types) | ||
209 | -- | 26 | -- |
210 | 2.16.2 | 27 | 2.20.1 |
211 | 28 | ||
212 | 29 | diff view generated by jsdifflib |
1 | The IoTKit Security Controller includes various registers | 1 | Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to |
---|---|---|---|
2 | that expose to software the controls for the Peripheral | 2 | use TCG vector ops when possible. |
3 | Protection Controllers in the system. Implement these. | ||
4 | 3 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-17-peter.maydell@linaro.org | 6 | Message-id: 20210913095440.13462-13-peter.maydell@linaro.org |
8 | --- | 7 | --- |
9 | include/hw/misc/iotkit-secctl.h | 64 +++++++++- | 8 | target/arm/translate-mve.c | 26 +++++++++++++++++++++----- |
10 | hw/misc/iotkit-secctl.c | 270 +++++++++++++++++++++++++++++++++++++--- | 9 | 1 file changed, 21 insertions(+), 5 deletions(-) |
11 | 2 files changed, 315 insertions(+), 19 deletions(-) | ||
12 | 10 | ||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 11 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
14 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/misc/iotkit-secctl.h | 13 | --- a/target/arm/translate-mve.c |
16 | +++ b/include/hw/misc/iotkit-secctl.h | 14 | +++ b/target/arm/translate-mve.c |
17 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) |
18 | * QEMU interface: | 16 | return true; |
19 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | 17 | } |
20 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 18 | |
21 | + * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | 19 | -static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) |
22 | + * should RAZ/WI or bus error | 20 | +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn, |
23 | + * Controlling the 2 APB PPCs in the IoTKit: | 21 | + GVecGen2iFn *vecfn) |
24 | + * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | 22 | { |
25 | + * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | 23 | TCGv_ptr qd; |
26 | + * + named GPIO outputs apb_ppc{0,1}_irq_enable | 24 | uint64_t imm; |
27 | + * + named GPIO outputs apb_ppc{0,1}_irq_clear | 25 | @@ -XXX,XX +XXX,XX @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) |
28 | + * + named GPIO inputs apb_ppc{0,1}_irq_status | 26 | |
29 | + * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit | 27 | imm = asimd_imm_const(a->imm, a->cmode, a->op); |
30 | + * might provide: | 28 | |
31 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | 29 | - qd = mve_qreg_ptr(a->qd); |
32 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | 30 | - fn(cpu_env, qd, tcg_constant_i64(imm)); |
33 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | 31 | - tcg_temp_free_ptr(qd); |
34 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | 32 | + if (vecfn && mve_no_predication(s)) { |
35 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | 33 | + vecfn(MO_64, mve_qreg_offset(a->qd), mve_qreg_offset(a->qd), |
36 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | 34 | + imm, 16, 16); |
37 | + * might provide: | 35 | + } else { |
38 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | 36 | + qd = mve_qreg_ptr(a->qd); |
39 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | 37 | + fn(cpu_env, qd, tcg_constant_i64(imm)); |
40 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | 38 | + tcg_temp_free_ptr(qd); |
41 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | 39 | + } |
42 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | 40 | mve_update_eci(s); |
43 | */ | 41 | return true; |
44 | 42 | } | |
45 | #ifndef IOTKIT_SECCTL_H | 43 | |
46 | @@ -XXX,XX +XXX,XX @@ | 44 | +static void gen_gvec_vmovi(unsigned vece, uint32_t dofs, uint32_t aofs, |
47 | #define TYPE_IOTKIT_SECCTL "iotkit-secctl" | 45 | + int64_t c, uint32_t oprsz, uint32_t maxsz) |
48 | #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
49 | |||
50 | -typedef struct IoTKitSecCtl { | ||
51 | +#define IOTS_APB_PPC0_NUM_PORTS 3 | ||
52 | +#define IOTS_APB_PPC1_NUM_PORTS 1 | ||
53 | +#define IOTS_PPC_NUM_PORTS 16 | ||
54 | +#define IOTS_NUM_APB_PPC 2 | ||
55 | +#define IOTS_NUM_APB_EXP_PPC 4 | ||
56 | +#define IOTS_NUM_AHB_EXP_PPC 4 | ||
57 | + | ||
58 | +typedef struct IoTKitSecCtl IoTKitSecCtl; | ||
59 | + | ||
60 | +/* State and IRQ lines relating to a PPC. For the | ||
61 | + * PPCs in the IoTKit not all the IRQ lines are used. | ||
62 | + */ | ||
63 | +typedef struct IoTKitSecCtlPPC { | ||
64 | + qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; | ||
65 | + qemu_irq ap[IOTS_PPC_NUM_PORTS]; | ||
66 | + qemu_irq irq_enable; | ||
67 | + qemu_irq irq_clear; | ||
68 | + | ||
69 | + uint32_t ns; | ||
70 | + uint32_t sp; | ||
71 | + uint32_t nsp; | ||
72 | + | ||
73 | + /* Number of ports actually present */ | ||
74 | + int numports; | ||
75 | + /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ | ||
76 | + int irq_bit_offset; | ||
77 | + IoTKitSecCtl *parent; | ||
78 | +} IoTKitSecCtlPPC; | ||
79 | + | ||
80 | +struct IoTKitSecCtl { | ||
81 | /*< private >*/ | ||
82 | SysBusDevice parent_obj; | ||
83 | |||
84 | /*< public >*/ | ||
85 | + qemu_irq sec_resp_cfg; | ||
86 | |||
87 | MemoryRegion s_regs; | ||
88 | MemoryRegion ns_regs; | ||
89 | -} IoTKitSecCtl; | ||
90 | + | ||
91 | + uint32_t secppcintstat; | ||
92 | + uint32_t secppcinten; | ||
93 | + uint32_t secrespcfg; | ||
94 | + | ||
95 | + IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
96 | + IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
97 | + IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; | ||
98 | +}; | ||
99 | |||
100 | #endif | ||
101 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/hw/misc/iotkit-secctl.c | ||
104 | +++ b/hw/misc/iotkit-secctl.c | ||
105 | @@ -XXX,XX +XXX,XX @@ static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
106 | 0x0d, 0xf0, 0x05, 0xb1, | ||
107 | }; | ||
108 | |||
109 | +/* The register sets for the various PPCs (AHB internal, APB internal, | ||
110 | + * AHB expansion, APB expansion) are all set up so that they are | ||
111 | + * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs | ||
112 | + * 0, 1, 2, 3 of that type, so we can convert a register address offset | ||
113 | + * into an an index into a PPC array easily. | ||
114 | + */ | ||
115 | +static inline int offset_to_ppc_idx(uint32_t offset) | ||
116 | +{ | 46 | +{ |
117 | + return extract32(offset, 2, 2); | 47 | + tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, c); |
118 | +} | 48 | +} |
119 | + | 49 | + |
120 | +typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc); | 50 | static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) |
121 | + | ||
122 | +static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn) | ||
123 | +{ | ||
124 | + int i; | ||
125 | + | ||
126 | + for (i = 0; i < IOTS_NUM_APB_PPC; i++) { | ||
127 | + fn(&s->apb[i]); | ||
128 | + } | ||
129 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
130 | + fn(&s->apbexp[i]); | ||
131 | + } | ||
132 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
133 | + fn(&s->ahbexp[i]); | ||
134 | + } | ||
135 | +} | ||
136 | + | ||
137 | static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
138 | uint64_t *pdata, | ||
139 | unsigned size, MemTxAttrs attrs) | ||
140 | { | 51 | { |
141 | uint64_t r; | 52 | /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ |
142 | uint32_t offset = addr & ~0x3; | 53 | MVEGenOneOpImmFn *fn; |
143 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | 54 | + GVecGen2iFn *vecfn; |
144 | 55 | ||
145 | switch (offset) { | 56 | if ((a->cmode & 1) && a->cmode < 12) { |
146 | case A_AHBNSPPC0: | 57 | if (a->op) { |
147 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | 58 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) |
148 | r = 0; | 59 | * so the VBIC becomes a logical AND operation. |
149 | break; | 60 | */ |
150 | case A_SECRESPCFG: | 61 | fn = gen_helper_mve_vandi; |
151 | - case A_NSCCFG: | 62 | + vecfn = tcg_gen_gvec_andi; |
152 | - case A_SECMPCINTSTATUS: | 63 | } else { |
153 | + r = s->secrespcfg; | 64 | fn = gen_helper_mve_vorri; |
154 | + break; | 65 | + vecfn = tcg_gen_gvec_ori; |
155 | case A_SECPPCINTSTAT: | 66 | } |
156 | + r = s->secppcintstat; | 67 | } else { |
157 | + break; | 68 | /* There is one unallocated cmode/op combination in this space */ |
158 | case A_SECPPCINTEN: | 69 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) |
159 | - case A_SECMSCINTSTAT: | 70 | } |
160 | - case A_SECMSCINTEN: | 71 | /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ |
161 | - case A_BRGINTSTAT: | 72 | fn = gen_helper_mve_vmovi; |
162 | - case A_BRGINTEN: | 73 | + vecfn = gen_gvec_vmovi; |
163 | + r = s->secppcinten; | 74 | } |
164 | + break; | 75 | - return do_1imm(s, a, fn); |
165 | case A_AHBNSPPCEXP0: | 76 | + return do_1imm(s, a, fn, vecfn); |
166 | case A_AHBNSPPCEXP1: | ||
167 | case A_AHBNSPPCEXP2: | ||
168 | case A_AHBNSPPCEXP3: | ||
169 | + r = s->ahbexp[offset_to_ppc_idx(offset)].ns; | ||
170 | + break; | ||
171 | case A_APBNSPPC0: | ||
172 | case A_APBNSPPC1: | ||
173 | + r = s->apb[offset_to_ppc_idx(offset)].ns; | ||
174 | + break; | ||
175 | case A_APBNSPPCEXP0: | ||
176 | case A_APBNSPPCEXP1: | ||
177 | case A_APBNSPPCEXP2: | ||
178 | case A_APBNSPPCEXP3: | ||
179 | + r = s->apbexp[offset_to_ppc_idx(offset)].ns; | ||
180 | + break; | ||
181 | case A_AHBSPPPCEXP0: | ||
182 | case A_AHBSPPPCEXP1: | ||
183 | case A_AHBSPPPCEXP2: | ||
184 | case A_AHBSPPPCEXP3: | ||
185 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
186 | + break; | ||
187 | case A_APBSPPPC0: | ||
188 | case A_APBSPPPC1: | ||
189 | + r = s->apb[offset_to_ppc_idx(offset)].sp; | ||
190 | + break; | ||
191 | case A_APBSPPPCEXP0: | ||
192 | case A_APBSPPPCEXP1: | ||
193 | case A_APBSPPPCEXP2: | ||
194 | case A_APBSPPPCEXP3: | ||
195 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
196 | + break; | ||
197 | + case A_NSCCFG: | ||
198 | + case A_SECMPCINTSTATUS: | ||
199 | + case A_SECMSCINTSTAT: | ||
200 | + case A_SECMSCINTEN: | ||
201 | + case A_BRGINTSTAT: | ||
202 | + case A_BRGINTEN: | ||
203 | case A_NSMSCEXP: | ||
204 | qemu_log_mask(LOG_UNIMP, | ||
205 | "IoTKit SecCtl S block read: " | ||
206 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
207 | return MEMTX_OK; | ||
208 | } | 77 | } |
209 | 78 | ||
210 | +static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc) | 79 | static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
211 | +{ | ||
212 | + int i; | ||
213 | + | ||
214 | + for (i = 0; i < ppc->numports; i++) { | ||
215 | + bool v; | ||
216 | + | ||
217 | + if (extract32(ppc->ns, i, 1)) { | ||
218 | + v = extract32(ppc->nsp, i, 1); | ||
219 | + } else { | ||
220 | + v = extract32(ppc->sp, i, 1); | ||
221 | + } | ||
222 | + qemu_set_irq(ppc->ap[i], v); | ||
223 | + } | ||
224 | +} | ||
225 | + | ||
226 | +static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
227 | +{ | ||
228 | + int i; | ||
229 | + | ||
230 | + ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
231 | + for (i = 0; i < ppc->numports; i++) { | ||
232 | + qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); | ||
233 | + } | ||
234 | + iotkit_secctl_update_ppc_ap(ppc); | ||
235 | +} | ||
236 | + | ||
237 | +static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
238 | +{ | ||
239 | + ppc->sp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
240 | + iotkit_secctl_update_ppc_ap(ppc); | ||
241 | +} | ||
242 | + | ||
243 | +static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
244 | +{ | ||
245 | + ppc->nsp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
246 | + iotkit_secctl_update_ppc_ap(ppc); | ||
247 | +} | ||
248 | + | ||
249 | +static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc) | ||
250 | +{ | ||
251 | + uint32_t value = ppc->parent->secppcintstat; | ||
252 | + | ||
253 | + qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1)); | ||
254 | +} | ||
255 | + | ||
256 | +static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc) | ||
257 | +{ | ||
258 | + uint32_t value = ppc->parent->secppcinten; | ||
259 | + | ||
260 | + qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)); | ||
261 | +} | ||
262 | + | ||
263 | static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
264 | uint64_t value, | ||
265 | unsigned size, MemTxAttrs attrs) | ||
266 | { | ||
267 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
268 | uint32_t offset = addr; | ||
269 | + IoTKitSecCtlPPC *ppc; | ||
270 | |||
271 | trace_iotkit_secctl_s_write(offset, value, size); | ||
272 | |||
273 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
274 | |||
275 | switch (offset) { | ||
276 | case A_SECRESPCFG: | ||
277 | - case A_NSCCFG: | ||
278 | + value &= 1; | ||
279 | + s->secrespcfg = value; | ||
280 | + qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); | ||
281 | + break; | ||
282 | case A_SECPPCINTCLR: | ||
283 | + value &= 0x00f000f3; | ||
284 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear); | ||
285 | + break; | ||
286 | case A_SECPPCINTEN: | ||
287 | - case A_SECMSCINTCLR: | ||
288 | - case A_SECMSCINTEN: | ||
289 | - case A_BRGINTCLR: | ||
290 | - case A_BRGINTEN: | ||
291 | + s->secppcinten = value & 0x00f000f3; | ||
292 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
293 | + break; | ||
294 | case A_AHBNSPPCEXP0: | ||
295 | case A_AHBNSPPCEXP1: | ||
296 | case A_AHBNSPPCEXP2: | ||
297 | case A_AHBNSPPCEXP3: | ||
298 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
299 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
300 | + break; | ||
301 | case A_APBNSPPC0: | ||
302 | case A_APBNSPPC1: | ||
303 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
304 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
305 | + break; | ||
306 | case A_APBNSPPCEXP0: | ||
307 | case A_APBNSPPCEXP1: | ||
308 | case A_APBNSPPCEXP2: | ||
309 | case A_APBNSPPCEXP3: | ||
310 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
311 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
312 | + break; | ||
313 | case A_AHBSPPPCEXP0: | ||
314 | case A_AHBSPPPCEXP1: | ||
315 | case A_AHBSPPPCEXP2: | ||
316 | case A_AHBSPPPCEXP3: | ||
317 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
318 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
319 | + break; | ||
320 | case A_APBSPPPC0: | ||
321 | case A_APBSPPPC1: | ||
322 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
323 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
324 | + break; | ||
325 | case A_APBSPPPCEXP0: | ||
326 | case A_APBSPPPCEXP1: | ||
327 | case A_APBSPPPCEXP2: | ||
328 | case A_APBSPPPCEXP3: | ||
329 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
330 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
331 | + break; | ||
332 | + case A_NSCCFG: | ||
333 | + case A_SECMSCINTCLR: | ||
334 | + case A_SECMSCINTEN: | ||
335 | + case A_BRGINTCLR: | ||
336 | + case A_BRGINTEN: | ||
337 | qemu_log_mask(LOG_UNIMP, | ||
338 | "IoTKit SecCtl S block write: " | ||
339 | "unimplemented offset 0x%x\n", offset); | ||
340 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
341 | uint64_t *pdata, | ||
342 | unsigned size, MemTxAttrs attrs) | ||
343 | { | ||
344 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
345 | uint64_t r; | ||
346 | uint32_t offset = addr & ~0x3; | ||
347 | |||
348 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
349 | case A_AHBNSPPPCEXP1: | ||
350 | case A_AHBNSPPPCEXP2: | ||
351 | case A_AHBNSPPPCEXP3: | ||
352 | + r = s->ahbexp[offset_to_ppc_idx(offset)].nsp; | ||
353 | + break; | ||
354 | case A_APBNSPPPC0: | ||
355 | case A_APBNSPPPC1: | ||
356 | + r = s->apb[offset_to_ppc_idx(offset)].nsp; | ||
357 | + break; | ||
358 | case A_APBNSPPPCEXP0: | ||
359 | case A_APBNSPPPCEXP1: | ||
360 | case A_APBNSPPPCEXP2: | ||
361 | case A_APBNSPPPCEXP3: | ||
362 | - qemu_log_mask(LOG_UNIMP, | ||
363 | - "IoTKit SecCtl NS block read: " | ||
364 | - "unimplemented offset 0x%x\n", offset); | ||
365 | + r = s->apbexp[offset_to_ppc_idx(offset)].nsp; | ||
366 | break; | ||
367 | case A_PID4: | ||
368 | case A_PID5: | ||
369 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
370 | uint64_t value, | ||
371 | unsigned size, MemTxAttrs attrs) | ||
372 | { | ||
373 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
374 | uint32_t offset = addr; | ||
375 | + IoTKitSecCtlPPC *ppc; | ||
376 | |||
377 | trace_iotkit_secctl_ns_write(offset, value, size); | ||
378 | |||
379 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
380 | case A_AHBNSPPPCEXP1: | ||
381 | case A_AHBNSPPPCEXP2: | ||
382 | case A_AHBNSPPPCEXP3: | ||
383 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
384 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
385 | + break; | ||
386 | case A_APBNSPPPC0: | ||
387 | case A_APBNSPPPC1: | ||
388 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
389 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
390 | + break; | ||
391 | case A_APBNSPPPCEXP0: | ||
392 | case A_APBNSPPPCEXP1: | ||
393 | case A_APBNSPPPCEXP2: | ||
394 | case A_APBNSPPPCEXP3: | ||
395 | - qemu_log_mask(LOG_UNIMP, | ||
396 | - "IoTKit SecCtl NS block write: " | ||
397 | - "unimplemented offset 0x%x\n", offset); | ||
398 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
399 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
400 | break; | ||
401 | case A_AHBNSPPPC0: | ||
402 | case A_PID4: | ||
403 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
404 | .impl.max_access_size = 4, | ||
405 | }; | ||
406 | |||
407 | +static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc) | ||
408 | +{ | ||
409 | + ppc->ns = 0; | ||
410 | + ppc->sp = 0; | ||
411 | + ppc->nsp = 0; | ||
412 | +} | ||
413 | + | ||
414 | static void iotkit_secctl_reset(DeviceState *dev) | ||
415 | { | ||
416 | + IoTKitSecCtl *s = IOTKIT_SECCTL(dev); | ||
417 | |||
418 | + s->secppcintstat = 0; | ||
419 | + s->secppcinten = 0; | ||
420 | + s->secrespcfg = 0; | ||
421 | + | ||
422 | + foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
423 | +} | ||
424 | + | ||
425 | +static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level) | ||
426 | +{ | ||
427 | + IoTKitSecCtlPPC *ppc = opaque; | ||
428 | + IoTKitSecCtl *s = IOTKIT_SECCTL(ppc->parent); | ||
429 | + int irqbit = ppc->irq_bit_offset + n; | ||
430 | + | ||
431 | + s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level); | ||
432 | +} | ||
433 | + | ||
434 | +static void iotkit_secctl_init_ppc(IoTKitSecCtl *s, | ||
435 | + IoTKitSecCtlPPC *ppc, | ||
436 | + const char *name, | ||
437 | + int numports, | ||
438 | + int irq_bit_offset) | ||
439 | +{ | ||
440 | + char *gpioname; | ||
441 | + DeviceState *dev = DEVICE(s); | ||
442 | + | ||
443 | + ppc->numports = numports; | ||
444 | + ppc->irq_bit_offset = irq_bit_offset; | ||
445 | + ppc->parent = s; | ||
446 | + | ||
447 | + gpioname = g_strdup_printf("%s_nonsec", name); | ||
448 | + qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports); | ||
449 | + g_free(gpioname); | ||
450 | + gpioname = g_strdup_printf("%s_ap", name); | ||
451 | + qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports); | ||
452 | + g_free(gpioname); | ||
453 | + gpioname = g_strdup_printf("%s_irq_enable", name); | ||
454 | + qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_irq_clear", name); | ||
457 | + qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1); | ||
458 | + g_free(gpioname); | ||
459 | + gpioname = g_strdup_printf("%s_irq_status", name); | ||
460 | + qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus, | ||
461 | + ppc, gpioname, 1); | ||
462 | + g_free(gpioname); | ||
463 | } | ||
464 | |||
465 | static void iotkit_secctl_init(Object *obj) | ||
466 | { | ||
467 | IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
468 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
469 | + DeviceState *dev = DEVICE(obj); | ||
470 | + int i; | ||
471 | + | ||
472 | + iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0", | ||
473 | + IOTS_APB_PPC0_NUM_PORTS, 0); | ||
474 | + iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1", | ||
475 | + IOTS_APB_PPC1_NUM_PORTS, 1); | ||
476 | + | ||
477 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
478 | + IoTKitSecCtlPPC *ppc = &s->apbexp[i]; | ||
479 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
480 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i); | ||
481 | + g_free(ppcname); | ||
482 | + } | ||
483 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
484 | + IoTKitSecCtlPPC *ppc = &s->ahbexp[i]; | ||
485 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
486 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i); | ||
487 | + g_free(ppcname); | ||
488 | + } | ||
489 | + | ||
490 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
491 | |||
492 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
495 | sysbus_init_mmio(sbd, &s->ns_regs); | ||
496 | } | ||
497 | |||
498 | +static const VMStateDescription iotkit_secctl_ppc_vmstate = { | ||
499 | + .name = "iotkit-secctl-ppc", | ||
500 | + .version_id = 1, | ||
501 | + .minimum_version_id = 1, | ||
502 | + .fields = (VMStateField[]) { | ||
503 | + VMSTATE_UINT32(ns, IoTKitSecCtlPPC), | ||
504 | + VMSTATE_UINT32(sp, IoTKitSecCtlPPC), | ||
505 | + VMSTATE_UINT32(nsp, IoTKitSecCtlPPC), | ||
506 | + VMSTATE_END_OF_LIST() | ||
507 | + } | ||
508 | +}; | ||
509 | + | ||
510 | static const VMStateDescription iotkit_secctl_vmstate = { | ||
511 | .name = "iotkit-secctl", | ||
512 | .version_id = 1, | ||
513 | .minimum_version_id = 1, | ||
514 | .fields = (VMStateField[]) { | ||
515 | + VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
516 | + VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
517 | + VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
518 | + VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
519 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
520 | + VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
521 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
522 | + VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1, | ||
523 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
524 | VMSTATE_END_OF_LIST() | ||
525 | } | ||
526 | }; | ||
527 | -- | 80 | -- |
528 | 2.16.2 | 81 | 2.20.1 |
529 | 82 | ||
530 | 83 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Include the U bit in the switches rather than testing separately. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-3-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------ | ||
11 | 1 file changed, 61 insertions(+), 68 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-a64.c | ||
16 | +++ b/target/arm/translate-a64.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
18 | int index; | ||
19 | TCGv_ptr fpst; | ||
20 | |||
21 | - switch (opcode) { | ||
22 | - case 0x0: /* MLA */ | ||
23 | - case 0x4: /* MLS */ | ||
24 | - if (!u || is_scalar) { | ||
25 | + switch (16 * u + opcode) { | ||
26 | + case 0x08: /* MUL */ | ||
27 | + case 0x10: /* MLA */ | ||
28 | + case 0x14: /* MLS */ | ||
29 | + if (is_scalar) { | ||
30 | unallocated_encoding(s); | ||
31 | return; | ||
32 | } | ||
33 | break; | ||
34 | - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | ||
35 | - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | ||
36 | - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | ||
37 | + case 0x02: /* SMLAL, SMLAL2 */ | ||
38 | + case 0x12: /* UMLAL, UMLAL2 */ | ||
39 | + case 0x06: /* SMLSL, SMLSL2 */ | ||
40 | + case 0x16: /* UMLSL, UMLSL2 */ | ||
41 | + case 0x0a: /* SMULL, SMULL2 */ | ||
42 | + case 0x1a: /* UMULL, UMULL2 */ | ||
43 | if (is_scalar) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | is_long = true; | ||
48 | break; | ||
49 | - case 0x3: /* SQDMLAL, SQDMLAL2 */ | ||
50 | - case 0x7: /* SQDMLSL, SQDMLSL2 */ | ||
51 | - case 0xb: /* SQDMULL, SQDMULL2 */ | ||
52 | + case 0x03: /* SQDMLAL, SQDMLAL2 */ | ||
53 | + case 0x07: /* SQDMLSL, SQDMLSL2 */ | ||
54 | + case 0x0b: /* SQDMULL, SQDMULL2 */ | ||
55 | is_long = true; | ||
56 | - /* fall through */ | ||
57 | - case 0xc: /* SQDMULH */ | ||
58 | - case 0xd: /* SQRDMULH */ | ||
59 | - if (u) { | ||
60 | - unallocated_encoding(s); | ||
61 | - return; | ||
62 | - } | ||
63 | break; | ||
64 | - case 0x8: /* MUL */ | ||
65 | - if (u || is_scalar) { | ||
66 | - unallocated_encoding(s); | ||
67 | - return; | ||
68 | - } | ||
69 | + case 0x0c: /* SQDMULH */ | ||
70 | + case 0x0d: /* SQRDMULH */ | ||
71 | break; | ||
72 | - case 0x1: /* FMLA */ | ||
73 | - case 0x5: /* FMLS */ | ||
74 | - if (u) { | ||
75 | - unallocated_encoding(s); | ||
76 | - return; | ||
77 | - } | ||
78 | - /* fall through */ | ||
79 | - case 0x9: /* FMUL, FMULX */ | ||
80 | + case 0x01: /* FMLA */ | ||
81 | + case 0x05: /* FMLS */ | ||
82 | + case 0x09: /* FMUL */ | ||
83 | + case 0x19: /* FMULX */ | ||
84 | if (size == 1) { | ||
85 | unallocated_encoding(s); | ||
86 | return; | ||
87 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
88 | |||
89 | read_vec_element(s, tcg_op, rn, pass, MO_64); | ||
90 | |||
91 | - switch (opcode) { | ||
92 | - case 0x5: /* FMLS */ | ||
93 | + switch (16 * u + opcode) { | ||
94 | + case 0x05: /* FMLS */ | ||
95 | /* As usual for ARM, separate negation for fused multiply-add */ | ||
96 | gen_helper_vfp_negd(tcg_op, tcg_op); | ||
97 | /* fall through */ | ||
98 | - case 0x1: /* FMLA */ | ||
99 | + case 0x01: /* FMLA */ | ||
100 | read_vec_element(s, tcg_res, rd, pass, MO_64); | ||
101 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | ||
102 | break; | ||
103 | - case 0x9: /* FMUL, FMULX */ | ||
104 | - if (u) { | ||
105 | - gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
106 | - } else { | ||
107 | - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
108 | - } | ||
109 | + case 0x09: /* FMUL */ | ||
110 | + gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
111 | + break; | ||
112 | + case 0x19: /* FMULX */ | ||
113 | + gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
114 | break; | ||
115 | default: | ||
116 | g_assert_not_reached(); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
118 | |||
119 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); | ||
120 | |||
121 | - switch (opcode) { | ||
122 | - case 0x0: /* MLA */ | ||
123 | - case 0x4: /* MLS */ | ||
124 | - case 0x8: /* MUL */ | ||
125 | + switch (16 * u + opcode) { | ||
126 | + case 0x08: /* MUL */ | ||
127 | + case 0x10: /* MLA */ | ||
128 | + case 0x14: /* MLS */ | ||
129 | { | ||
130 | static NeonGenTwoOpFn * const fns[2][2] = { | ||
131 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | ||
132 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
133 | genfn(tcg_res, tcg_op, tcg_res); | ||
134 | break; | ||
135 | } | ||
136 | - case 0x5: /* FMLS */ | ||
137 | - case 0x1: /* FMLA */ | ||
138 | + case 0x05: /* FMLS */ | ||
139 | + case 0x01: /* FMLA */ | ||
140 | read_vec_element_i32(s, tcg_res, rd, pass, | ||
141 | is_scalar ? size : MO_32); | ||
142 | switch (size) { | ||
143 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
144 | g_assert_not_reached(); | ||
145 | } | ||
146 | break; | ||
147 | - case 0x9: /* FMUL, FMULX */ | ||
148 | + case 0x09: /* FMUL */ | ||
149 | switch (size) { | ||
150 | case 1: | ||
151 | - if (u) { | ||
152 | - if (is_scalar) { | ||
153 | - gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
154 | - tcg_idx, fpst); | ||
155 | - } else { | ||
156 | - gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
157 | - tcg_idx, fpst); | ||
158 | - } | ||
159 | + if (is_scalar) { | ||
160 | + gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
161 | + tcg_idx, fpst); | ||
162 | } else { | ||
163 | - if (is_scalar) { | ||
164 | - gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
165 | - tcg_idx, fpst); | ||
166 | - } else { | ||
167 | - gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
168 | - tcg_idx, fpst); | ||
169 | - } | ||
170 | + gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
171 | + tcg_idx, fpst); | ||
172 | } | ||
173 | break; | ||
174 | case 2: | ||
175 | - if (u) { | ||
176 | - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
177 | - } else { | ||
178 | - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
179 | - } | ||
180 | + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
181 | break; | ||
182 | default: | ||
183 | g_assert_not_reached(); | ||
184 | } | ||
185 | break; | ||
186 | - case 0xc: /* SQDMULH */ | ||
187 | + case 0x19: /* FMULX */ | ||
188 | + switch (size) { | ||
189 | + case 1: | ||
190 | + if (is_scalar) { | ||
191 | + gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
192 | + tcg_idx, fpst); | ||
193 | + } else { | ||
194 | + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
195 | + tcg_idx, fpst); | ||
196 | + } | ||
197 | + break; | ||
198 | + case 2: | ||
199 | + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
200 | + break; | ||
201 | + default: | ||
202 | + g_assert_not_reached(); | ||
203 | + } | ||
204 | + break; | ||
205 | + case 0x0c: /* SQDMULH */ | ||
206 | if (size == 1) { | ||
207 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | ||
208 | tcg_op, tcg_idx); | ||
209 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
210 | tcg_op, tcg_idx); | ||
211 | } | ||
212 | break; | ||
213 | - case 0xd: /* SQRDMULH */ | ||
214 | + case 0x0d: /* SQRDMULH */ | ||
215 | if (size == 1) { | ||
216 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | ||
217 | tcg_op, tcg_idx); | ||
218 | -- | ||
219 | 2.16.2 | ||
220 | |||
221 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The integer size check was already outside of the opcode switch; | ||
4 | move the floating-point size check outside as well. Unify the | ||
5 | size vs index adjustment between fp and integer paths. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20180228193125.20577-4-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate-a64.c | 65 +++++++++++++++++++++++----------------------- | ||
13 | 1 file changed, 32 insertions(+), 33 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-a64.c | ||
18 | +++ b/target/arm/translate-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
20 | case 0x05: /* FMLS */ | ||
21 | case 0x09: /* FMUL */ | ||
22 | case 0x19: /* FMULX */ | ||
23 | - if (size == 1) { | ||
24 | - unallocated_encoding(s); | ||
25 | - return; | ||
26 | - } | ||
27 | is_fp = true; | ||
28 | break; | ||
29 | default: | ||
30 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
31 | if (is_fp) { | ||
32 | /* convert insn encoded size to TCGMemOp size */ | ||
33 | switch (size) { | ||
34 | - case 2: /* single precision */ | ||
35 | - size = MO_32; | ||
36 | - index = h << 1 | l; | ||
37 | - rm |= (m << 4); | ||
38 | - break; | ||
39 | - case 3: /* double precision */ | ||
40 | - size = MO_64; | ||
41 | - if (l || !is_q) { | ||
42 | + case 0: /* half-precision */ | ||
43 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | - index = h; | ||
48 | - rm |= (m << 4); | ||
49 | - break; | ||
50 | - case 0: /* half precision */ | ||
51 | size = MO_16; | ||
52 | - index = h << 2 | l << 1 | m; | ||
53 | - is_fp16 = true; | ||
54 | - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
55 | - break; | ||
56 | - } | ||
57 | - /* fallthru */ | ||
58 | - default: /* unallocated */ | ||
59 | - unallocated_encoding(s); | ||
60 | - return; | ||
61 | - } | ||
62 | - } else { | ||
63 | - switch (size) { | ||
64 | - case 1: | ||
65 | - index = h << 2 | l << 1 | m; | ||
66 | break; | ||
67 | - case 2: | ||
68 | - index = h << 1 | l; | ||
69 | - rm |= (m << 4); | ||
70 | + case MO_32: /* single precision */ | ||
71 | + case MO_64: /* double precision */ | ||
72 | break; | ||
73 | default: | ||
74 | unallocated_encoding(s); | ||
75 | return; | ||
76 | } | ||
77 | + } else { | ||
78 | + switch (size) { | ||
79 | + case MO_8: | ||
80 | + case MO_64: | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + } | ||
85 | + | ||
86 | + /* Given TCGMemOp size, adjust register and indexing. */ | ||
87 | + switch (size) { | ||
88 | + case MO_16: | ||
89 | + index = h << 2 | l << 1 | m; | ||
90 | + break; | ||
91 | + case MO_32: | ||
92 | + index = h << 1 | l; | ||
93 | + rm |= m << 4; | ||
94 | + break; | ||
95 | + case MO_64: | ||
96 | + if (l || !is_q) { | ||
97 | + unallocated_encoding(s); | ||
98 | + return; | ||
99 | + } | ||
100 | + index = h; | ||
101 | + rm |= m << 4; | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | } | ||
106 | |||
107 | if (!fp_access_check(s)) { | ||
108 | -- | ||
109 | 2.16.2 | ||
110 | |||
111 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-7-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 29 insertions(+) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
16 | case 0x19: /* FMULX */ | ||
17 | is_fp = true; | ||
18 | break; | ||
19 | + case 0x1d: /* SQRDMLAH */ | ||
20 | + case 0x1f: /* SQRDMLSH */ | ||
21 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
22 | + unallocated_encoding(s); | ||
23 | + return; | ||
24 | + } | ||
25 | + break; | ||
26 | default: | ||
27 | unallocated_encoding(s); | ||
28 | return; | ||
29 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
30 | tcg_op, tcg_idx); | ||
31 | } | ||
32 | break; | ||
33 | + case 0x1d: /* SQRDMLAH */ | ||
34 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
35 | + is_scalar ? size : MO_32); | ||
36 | + if (size == 1) { | ||
37 | + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | ||
38 | + tcg_op, tcg_idx, tcg_res); | ||
39 | + } else { | ||
40 | + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | ||
41 | + tcg_op, tcg_idx, tcg_res); | ||
42 | + } | ||
43 | + break; | ||
44 | + case 0x1f: /* SQRDMLSH */ | ||
45 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
46 | + is_scalar ? size : MO_32); | ||
47 | + if (size == 1) { | ||
48 | + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | ||
49 | + tcg_op, tcg_idx, tcg_res); | ||
50 | + } else { | ||
51 | + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | ||
52 | + tcg_op, tcg_idx, tcg_res); | ||
53 | + } | ||
54 | + break; | ||
55 | default: | ||
56 | g_assert_not_reached(); | ||
57 | } | ||
58 | -- | ||
59 | 2.16.2 | ||
60 | |||
61 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-9-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- | ||
9 | 1 file changed, 42 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static const char *regnames[] = | ||
16 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | ||
17 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | ||
18 | |||
19 | +/* Function prototypes for gen_ functions calling Neon helpers. */ | ||
20 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
21 | + TCGv_i32, TCGv_i32); | ||
22 | + | ||
23 | /* initialize TCG globals. */ | ||
24 | void arm_translate_init(void) | ||
25 | { | ||
26 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
27 | } | ||
28 | neon_store_reg64(cpu_V0, rd + pass); | ||
29 | } | ||
30 | - | ||
31 | - | ||
32 | break; | ||
33 | - default: /* 14 and 15 are RESERVED */ | ||
34 | - return 1; | ||
35 | + case 14: /* VQRDMLAH scalar */ | ||
36 | + case 15: /* VQRDMLSH scalar */ | ||
37 | + { | ||
38 | + NeonGenThreeOpEnvFn *fn; | ||
39 | + | ||
40 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
41 | + return 1; | ||
42 | + } | ||
43 | + if (u && ((rd | rn) & 1)) { | ||
44 | + return 1; | ||
45 | + } | ||
46 | + if (op == 14) { | ||
47 | + if (size == 1) { | ||
48 | + fn = gen_helper_neon_qrdmlah_s16; | ||
49 | + } else { | ||
50 | + fn = gen_helper_neon_qrdmlah_s32; | ||
51 | + } | ||
52 | + } else { | ||
53 | + if (size == 1) { | ||
54 | + fn = gen_helper_neon_qrdmlsh_s16; | ||
55 | + } else { | ||
56 | + fn = gen_helper_neon_qrdmlsh_s32; | ||
57 | + } | ||
58 | + } | ||
59 | + | ||
60 | + tmp2 = neon_get_scalar(size, rm); | ||
61 | + for (pass = 0; pass < (u ? 4 : 2); pass++) { | ||
62 | + tmp = neon_load_reg(rn, pass); | ||
63 | + tmp3 = neon_load_reg(rd, pass); | ||
64 | + fn(tmp, cpu_env, tmp, tmp2, tmp3); | ||
65 | + tcg_temp_free_i32(tmp3); | ||
66 | + neon_store_reg(rd, pass, tmp); | ||
67 | + } | ||
68 | + tcg_temp_free_i32(tmp2); | ||
69 | + } | ||
70 | + break; | ||
71 | + default: | ||
72 | + g_assert_not_reached(); | ||
73 | } | ||
74 | } | ||
75 | } else { /* size == 3 */ | ||
76 | -- | ||
77 | 2.16.2 | ||
78 | |||
79 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Not enabled anywhere yet. | ||
4 | |||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180228193125.20577-11-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.h | 1 + | ||
11 | linux-user/elfload.c | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
19 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | ||
20 | ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | ||
21 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | ||
22 | + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ | ||
23 | }; | ||
24 | |||
25 | static inline int arm_feature(CPUARMState *env, int feature) | ||
26 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/linux-user/elfload.c | ||
29 | +++ b/linux-user/elfload.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
31 | GET_FEATURE(ARM_FEATURE_V8_FP16, | ||
32 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | ||
33 | GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | ||
34 | + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); | ||
35 | #undef GET_FEATURE | ||
36 | |||
37 | return hwcaps; | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |