1 | Second pull request of the week; mostly RTH's support for some | 1 | The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df: |
---|---|---|---|
2 | new-in-v8.1/v8.3 instructions, and my v8M board model. | ||
3 | 2 | ||
4 | thanks | 3 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100) |
5 | -- PMM | ||
6 | |||
7 | The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f: | ||
8 | |||
9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000) | ||
10 | 4 | ||
11 | are available in the Git repository at: | 5 | are available in the Git repository at: |
12 | 6 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702 |
14 | 8 | ||
15 | for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078: | 9 | for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8: |
16 | 10 | ||
17 | target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000) | 11 | target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100) |
18 | 12 | ||
19 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
20 | target-arm queue: | 14 | target-arm queue: |
21 | * implement FCMA and RDM v8.1 and v8.3 instructions | 15 | * more MVE instructions |
22 | * enable Cortex-M33 v8M core, and provide new mps2-an505 board model | 16 | * hw/gpio/gpio_pwr: use shutdown function for reboot |
23 | that uses it | 17 | * target/arm: Check NaN mode before silencing NaN |
24 | * decodetree: Propagate return value from translate subroutines | 18 | * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine |
25 | * xlnx-zynqmp: Implement the RTC device | 19 | * hw/arm: Add basic power management to raspi. |
20 | * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc | ||
26 | 21 | ||
27 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
28 | Alistair Francis (3): | 23 | Joe Komlodi (1): |
29 | xlnx-zynqmp-rtc: Initial commit | 24 | target/arm: Check NaN mode before silencing NaN |
30 | xlnx-zynqmp-rtc: Add basic time support | ||
31 | xlnx-zynqmp: Connect the RTC device | ||
32 | 25 | ||
33 | Peter Maydell (19): | 26 | Maxim Uvarov (1): |
34 | loader: Add new load_ramdisk_as() | 27 | hw/gpio/gpio_pwr: use shutdown function for reboot |
35 | hw/arm/boot: Honour CPU's address space for image loads | ||
36 | hw/arm/armv7m: Honour CPU's address space for image loads | ||
37 | target/arm: Define an IDAU interface | ||
38 | armv7m: Forward idau property to CPU object | ||
39 | target/arm: Define init-svtor property for the reset secure VTOR value | ||
40 | armv7m: Forward init-svtor property to CPU object | ||
41 | target/arm: Add Cortex-M33 | ||
42 | hw/misc/unimp: Move struct to header file | ||
43 | include/hw/or-irq.h: Add missing include guard | ||
44 | qdev: Add new qdev_init_gpio_in_named_with_opaque() | ||
45 | hw/core/split-irq: Device that splits IRQ lines | ||
46 | hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505 | ||
47 | hw/misc/tz-ppc: Model TrustZone peripheral protection controller | ||
48 | hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton | ||
49 | hw/misc/iotkit-secctl: Add handling for PPCs | ||
50 | hw/misc/iotkit-secctl: Add remaining simple registers | ||
51 | hw/arm/iotkit: Model Arm IOT Kit | ||
52 | mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image | ||
53 | 28 | ||
54 | Richard Henderson (17): | 29 | Nolan Leake (1): |
55 | decodetree: Propagate return value from translate subroutines | 30 | hw/arm: Add basic power management to raspi. |
56 | target/arm: Add ARM_FEATURE_V8_RDM | ||
57 | target/arm: Refactor disas_simd_indexed decode | ||
58 | target/arm: Refactor disas_simd_indexed size checks | ||
59 | target/arm: Decode aa64 armv8.1 scalar three same extra | ||
60 | target/arm: Decode aa64 armv8.1 three same extra | ||
61 | target/arm: Decode aa64 armv8.1 scalar/vector x indexed element | ||
62 | target/arm: Decode aa32 armv8.1 three same | ||
63 | target/arm: Decode aa32 armv8.1 two reg and a scalar | ||
64 | target/arm: Enable ARM_FEATURE_V8_RDM | ||
65 | target/arm: Add ARM_FEATURE_V8_FCMA | ||
66 | target/arm: Decode aa64 armv8.3 fcadd | ||
67 | target/arm: Decode aa64 armv8.3 fcmla | ||
68 | target/arm: Decode aa32 armv8.3 3-same | ||
69 | target/arm: Decode aa32 armv8.3 2-reg-index | ||
70 | target/arm: Decode t32 simd 3reg and 2reg_scalar extension | ||
71 | target/arm: Enable ARM_FEATURE_V8_FCMA | ||
72 | 31 | ||
73 | hw/arm/Makefile.objs | 2 + | 32 | Patrick Venture (2): |
74 | hw/core/Makefile.objs | 1 + | 33 | docs/system/arm: Add quanta-q7l1-bmc reference |
75 | hw/misc/Makefile.objs | 4 + | 34 | docs/system/arm: Add quanta-gbs-bmc reference |
76 | hw/timer/Makefile.objs | 1 + | ||
77 | target/arm/Makefile.objs | 2 +- | ||
78 | include/hw/arm/armv7m.h | 5 + | ||
79 | include/hw/arm/iotkit.h | 109 ++++++ | ||
80 | include/hw/arm/xlnx-zynqmp.h | 2 + | ||
81 | include/hw/core/split-irq.h | 57 +++ | ||
82 | include/hw/irq.h | 4 +- | ||
83 | include/hw/loader.h | 12 +- | ||
84 | include/hw/misc/iotkit-secctl.h | 103 ++++++ | ||
85 | include/hw/misc/mps2-fpgaio.h | 43 +++ | ||
86 | include/hw/misc/tz-ppc.h | 101 ++++++ | ||
87 | include/hw/misc/unimp.h | 10 + | ||
88 | include/hw/or-irq.h | 5 + | ||
89 | include/hw/qdev-core.h | 30 +- | ||
90 | include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++ | ||
91 | target/arm/cpu.h | 8 + | ||
92 | target/arm/helper.h | 31 ++ | ||
93 | target/arm/idau.h | 61 ++++ | ||
94 | hw/arm/armv7m.c | 35 +- | ||
95 | hw/arm/boot.c | 119 ++++--- | ||
96 | hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++ | ||
97 | hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++ | ||
98 | hw/arm/xlnx-zynqmp.c | 14 + | ||
99 | hw/core/loader.c | 8 +- | ||
100 | hw/core/qdev.c | 8 +- | ||
101 | hw/core/split-irq.c | 89 +++++ | ||
102 | hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++ | ||
103 | hw/misc/mps2-fpgaio.c | 176 ++++++++++ | ||
104 | hw/misc/tz-ppc.c | 302 ++++++++++++++++ | ||
105 | hw/misc/unimp.c | 10 - | ||
106 | hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++ | ||
107 | linux-user/elfload.c | 2 + | ||
108 | target/arm/cpu.c | 66 +++- | ||
109 | target/arm/cpu64.c | 2 + | ||
110 | target/arm/helper.c | 28 +- | ||
111 | target/arm/translate-a64.c | 514 +++++++++++++++++++++------ | ||
112 | target/arm/translate.c | 275 +++++++++++++-- | ||
113 | target/arm/vec_helper.c | 429 ++++++++++++++++++++++ | ||
114 | default-configs/arm-softmmu.mak | 5 + | ||
115 | hw/misc/trace-events | 24 ++ | ||
116 | hw/timer/trace-events | 3 + | ||
117 | scripts/decodetree.py | 5 +- | ||
118 | 45 files changed, 4668 insertions(+), 200 deletions(-) | ||
119 | create mode 100644 include/hw/arm/iotkit.h | ||
120 | create mode 100644 include/hw/core/split-irq.h | ||
121 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
122 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
123 | create mode 100644 include/hw/misc/tz-ppc.h | ||
124 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
125 | create mode 100644 target/arm/idau.h | ||
126 | create mode 100644 hw/arm/iotkit.c | ||
127 | create mode 100644 hw/arm/mps2-tz.c | ||
128 | create mode 100644 hw/core/split-irq.c | ||
129 | create mode 100644 hw/misc/iotkit-secctl.c | ||
130 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
131 | create mode 100644 hw/misc/tz-ppc.c | ||
132 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
133 | create mode 100644 target/arm/vec_helper.c | ||
134 | 35 | ||
36 | Peter Maydell (18): | ||
37 | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation | ||
38 | target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH | ||
39 | target/arm: Make asimd_imm_const() public | ||
40 | target/arm: Use asimd_imm_const for A64 decode | ||
41 | target/arm: Use dup_const() instead of bitfield_replicate() | ||
42 | target/arm: Implement MVE logical immediate insns | ||
43 | target/arm: Implement MVE vector shift left by immediate insns | ||
44 | target/arm: Implement MVE vector shift right by immediate insns | ||
45 | target/arm: Implement MVE VSHLL | ||
46 | target/arm: Implement MVE VSRI, VSLI | ||
47 | target/arm: Implement MVE VSHRN, VRSHRN | ||
48 | target/arm: Implement MVE saturating narrowing shifts | ||
49 | target/arm: Implement MVE VSHLC | ||
50 | target/arm: Implement MVE VADDLV | ||
51 | target/arm: Implement MVE long shifts by immediate | ||
52 | target/arm: Implement MVE long shifts by register | ||
53 | target/arm: Implement MVE shifts by immediate | ||
54 | target/arm: Implement MVE shifts by register | ||
55 | |||
56 | Philippe Mathieu-Daudé (1): | ||
57 | tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine | ||
58 | |||
59 | docs/system/arm/aspeed.rst | 1 + | ||
60 | docs/system/arm/nuvoton.rst | 5 +- | ||
61 | include/hw/arm/bcm2835_peripherals.h | 3 +- | ||
62 | include/hw/misc/bcm2835_powermgt.h | 29 ++ | ||
63 | target/arm/helper-mve.h | 108 +++++++ | ||
64 | target/arm/translate.h | 41 +++ | ||
65 | target/arm/mve.decode | 177 ++++++++++- | ||
66 | target/arm/t32.decode | 71 ++++- | ||
67 | hw/arm/bcm2835_peripherals.c | 13 +- | ||
68 | hw/gpio/gpio_pwr.c | 2 +- | ||
69 | hw/misc/bcm2835_powermgt.c | 160 ++++++++++ | ||
70 | target/arm/helper-a64.c | 12 +- | ||
71 | target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++-- | ||
72 | target/arm/translate-a64.c | 86 +----- | ||
73 | target/arm/translate-mve.c | 261 +++++++++++++++- | ||
74 | target/arm/translate-neon.c | 81 ----- | ||
75 | target/arm/translate.c | 327 +++++++++++++++++++- | ||
76 | target/arm/vfp_helper.c | 24 +- | ||
77 | hw/misc/meson.build | 1 + | ||
78 | tests/acceptance/boot_linux_console.py | 43 +++ | ||
79 | 20 files changed, 1760 insertions(+), 209 deletions(-) | ||
80 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
81 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
82 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Initial commit of the ZynqMP RTC device. | ||
4 | |||
5 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/timer/Makefile.objs | 1 + | ||
10 | include/hw/timer/xlnx-zynqmp-rtc.h | 84 +++++++++++++++ | ||
11 | hw/timer/xlnx-zynqmp-rtc.c | 214 +++++++++++++++++++++++++++++++++++++ | ||
12 | 3 files changed, 299 insertions(+) | ||
13 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
14 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
15 | |||
16 | diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/timer/Makefile.objs | ||
19 | +++ b/hw/timer/Makefile.objs | ||
20 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx_epit.o | ||
21 | common-obj-$(CONFIG_IMX) += imx_gpt.o | ||
22 | common-obj-$(CONFIG_LM32) += lm32_timer.o | ||
23 | common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o | ||
24 | +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o | ||
25 | |||
26 | obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o | ||
27 | obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o | ||
28 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Xilinx Inc. | ||
38 | + * | ||
39 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
40 | + * | ||
41 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
42 | + * of this software and associated documentation files (the "Software"), to deal | ||
43 | + * in the Software without restriction, including without limitation the rights | ||
44 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
45 | + * copies of the Software, and to permit persons to whom the Software is | ||
46 | + * furnished to do so, subject to the following conditions: | ||
47 | + * | ||
48 | + * The above copyright notice and this permission notice shall be included in | ||
49 | + * all copies or substantial portions of the Software. | ||
50 | + * | ||
51 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
52 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
53 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
54 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
55 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
56 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
57 | + * THE SOFTWARE. | ||
58 | + */ | ||
59 | + | ||
60 | +#include "hw/register.h" | ||
61 | + | ||
62 | +#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc" | ||
63 | + | ||
64 | +#define XLNX_ZYNQMP_RTC(obj) \ | ||
65 | + OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC) | ||
66 | + | ||
67 | +REG32(SET_TIME_WRITE, 0x0) | ||
68 | +REG32(SET_TIME_READ, 0x4) | ||
69 | +REG32(CALIB_WRITE, 0x8) | ||
70 | + FIELD(CALIB_WRITE, FRACTION_EN, 20, 1) | ||
71 | + FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4) | ||
72 | + FIELD(CALIB_WRITE, MAX_TICK, 0, 16) | ||
73 | +REG32(CALIB_READ, 0xc) | ||
74 | + FIELD(CALIB_READ, FRACTION_EN, 20, 1) | ||
75 | + FIELD(CALIB_READ, FRACTION_DATA, 16, 4) | ||
76 | + FIELD(CALIB_READ, MAX_TICK, 0, 16) | ||
77 | +REG32(CURRENT_TIME, 0x10) | ||
78 | +REG32(CURRENT_TICK, 0x14) | ||
79 | + FIELD(CURRENT_TICK, VALUE, 0, 16) | ||
80 | +REG32(ALARM, 0x18) | ||
81 | +REG32(RTC_INT_STATUS, 0x20) | ||
82 | + FIELD(RTC_INT_STATUS, ALARM, 1, 1) | ||
83 | + FIELD(RTC_INT_STATUS, SECONDS, 0, 1) | ||
84 | +REG32(RTC_INT_MASK, 0x24) | ||
85 | + FIELD(RTC_INT_MASK, ALARM, 1, 1) | ||
86 | + FIELD(RTC_INT_MASK, SECONDS, 0, 1) | ||
87 | +REG32(RTC_INT_EN, 0x28) | ||
88 | + FIELD(RTC_INT_EN, ALARM, 1, 1) | ||
89 | + FIELD(RTC_INT_EN, SECONDS, 0, 1) | ||
90 | +REG32(RTC_INT_DIS, 0x2c) | ||
91 | + FIELD(RTC_INT_DIS, ALARM, 1, 1) | ||
92 | + FIELD(RTC_INT_DIS, SECONDS, 0, 1) | ||
93 | +REG32(ADDR_ERROR, 0x30) | ||
94 | + FIELD(ADDR_ERROR, STATUS, 0, 1) | ||
95 | +REG32(ADDR_ERROR_INT_MASK, 0x34) | ||
96 | + FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1) | ||
97 | +REG32(ADDR_ERROR_INT_EN, 0x38) | ||
98 | + FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1) | ||
99 | +REG32(ADDR_ERROR_INT_DIS, 0x3c) | ||
100 | + FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1) | ||
101 | +REG32(CONTROL, 0x40) | ||
102 | + FIELD(CONTROL, BATTERY_DISABLE, 31, 1) | ||
103 | + FIELD(CONTROL, OSC_CNTRL, 24, 4) | ||
104 | + FIELD(CONTROL, SLVERR_ENABLE, 0, 1) | ||
105 | +REG32(SAFETY_CHK, 0x50) | ||
106 | + | ||
107 | +#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1) | ||
108 | + | ||
109 | +typedef struct XlnxZynqMPRTC { | ||
110 | + SysBusDevice parent_obj; | ||
111 | + MemoryRegion iomem; | ||
112 | + qemu_irq irq_rtc_int; | ||
113 | + qemu_irq irq_addr_error_int; | ||
114 | + | ||
115 | + uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
116 | + RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
117 | +} XlnxZynqMPRTC; | ||
118 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
119 | new file mode 100644 | ||
120 | index XXXXXXX..XXXXXXX | ||
121 | --- /dev/null | ||
122 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | ||
123 | @@ -XXX,XX +XXX,XX @@ | ||
124 | +/* | ||
125 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
126 | + * | ||
127 | + * Copyright (c) 2017 Xilinx Inc. | ||
128 | + * | ||
129 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
130 | + * | ||
131 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
132 | + * of this software and associated documentation files (the "Software"), to deal | ||
133 | + * in the Software without restriction, including without limitation the rights | ||
134 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
135 | + * copies of the Software, and to permit persons to whom the Software is | ||
136 | + * furnished to do so, subject to the following conditions: | ||
137 | + * | ||
138 | + * The above copyright notice and this permission notice shall be included in | ||
139 | + * all copies or substantial portions of the Software. | ||
140 | + * | ||
141 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
142 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
143 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
144 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
145 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
146 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
147 | + * THE SOFTWARE. | ||
148 | + */ | ||
149 | + | ||
150 | +#include "qemu/osdep.h" | ||
151 | +#include "hw/sysbus.h" | ||
152 | +#include "hw/register.h" | ||
153 | +#include "qemu/bitops.h" | ||
154 | +#include "qemu/log.h" | ||
155 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
156 | + | ||
157 | +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
158 | +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0 | ||
159 | +#endif | ||
160 | + | ||
161 | +static void rtc_int_update_irq(XlnxZynqMPRTC *s) | ||
162 | +{ | ||
163 | + bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; | ||
164 | + qemu_set_irq(s->irq_rtc_int, pending); | ||
165 | +} | ||
166 | + | ||
167 | +static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
168 | +{ | ||
169 | + bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; | ||
170 | + qemu_set_irq(s->irq_addr_error_int, pending); | ||
171 | +} | ||
172 | + | ||
173 | +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
174 | +{ | ||
175 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
176 | + rtc_int_update_irq(s); | ||
177 | +} | ||
178 | + | ||
179 | +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
180 | +{ | ||
181 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
182 | + | ||
183 | + s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64; | ||
184 | + rtc_int_update_irq(s); | ||
185 | + return 0; | ||
186 | +} | ||
187 | + | ||
188 | +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
189 | +{ | ||
190 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
191 | + | ||
192 | + s->regs[R_RTC_INT_MASK] |= (uint32_t) val64; | ||
193 | + rtc_int_update_irq(s); | ||
194 | + return 0; | ||
195 | +} | ||
196 | + | ||
197 | +static void addr_error_postw(RegisterInfo *reg, uint64_t val64) | ||
198 | +{ | ||
199 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
200 | + addr_error_int_update_irq(s); | ||
201 | +} | ||
202 | + | ||
203 | +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
204 | +{ | ||
205 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
206 | + | ||
207 | + s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64; | ||
208 | + addr_error_int_update_irq(s); | ||
209 | + return 0; | ||
210 | +} | ||
211 | + | ||
212 | +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
213 | +{ | ||
214 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
215 | + | ||
216 | + s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64; | ||
217 | + addr_error_int_update_irq(s); | ||
218 | + return 0; | ||
219 | +} | ||
220 | + | ||
221 | +static const RegisterAccessInfo rtc_regs_info[] = { | ||
222 | + { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
223 | + },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
224 | + .ro = 0xffffffff, | ||
225 | + },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
226 | + },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
227 | + .ro = 0x1fffff, | ||
228 | + },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
229 | + .ro = 0xffffffff, | ||
230 | + },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
231 | + .ro = 0xffff, | ||
232 | + },{ .name = "ALARM", .addr = A_ALARM, | ||
233 | + },{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS, | ||
234 | + .w1c = 0x3, | ||
235 | + .post_write = rtc_int_status_postw, | ||
236 | + },{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK, | ||
237 | + .reset = 0x3, | ||
238 | + .ro = 0x3, | ||
239 | + },{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN, | ||
240 | + .pre_write = rtc_int_en_prew, | ||
241 | + },{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS, | ||
242 | + .pre_write = rtc_int_dis_prew, | ||
243 | + },{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR, | ||
244 | + .w1c = 0x1, | ||
245 | + .post_write = addr_error_postw, | ||
246 | + },{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK, | ||
247 | + .reset = 0x1, | ||
248 | + .ro = 0x1, | ||
249 | + },{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN, | ||
250 | + .pre_write = addr_error_int_en_prew, | ||
251 | + },{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS, | ||
252 | + .pre_write = addr_error_int_dis_prew, | ||
253 | + },{ .name = "CONTROL", .addr = A_CONTROL, | ||
254 | + .reset = 0x1000000, | ||
255 | + .rsvd = 0x70fffffe, | ||
256 | + },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK, | ||
257 | + } | ||
258 | +}; | ||
259 | + | ||
260 | +static void rtc_reset(DeviceState *dev) | ||
261 | +{ | ||
262 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev); | ||
263 | + unsigned int i; | ||
264 | + | ||
265 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
266 | + register_reset(&s->regs_info[i]); | ||
267 | + } | ||
268 | + | ||
269 | + rtc_int_update_irq(s); | ||
270 | + addr_error_int_update_irq(s); | ||
271 | +} | ||
272 | + | ||
273 | +static const MemoryRegionOps rtc_ops = { | ||
274 | + .read = register_read_memory, | ||
275 | + .write = register_write_memory, | ||
276 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
277 | + .valid = { | ||
278 | + .min_access_size = 4, | ||
279 | + .max_access_size = 4, | ||
280 | + }, | ||
281 | +}; | ||
282 | + | ||
283 | +static void rtc_init(Object *obj) | ||
284 | +{ | ||
285 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
286 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
287 | + RegisterInfoArray *reg_array; | ||
288 | + | ||
289 | + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
290 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
291 | + reg_array = | ||
292 | + register_init_block32(DEVICE(obj), rtc_regs_info, | ||
293 | + ARRAY_SIZE(rtc_regs_info), | ||
294 | + s->regs_info, s->regs, | ||
295 | + &rtc_ops, | ||
296 | + XLNX_ZYNQMP_RTC_ERR_DEBUG, | ||
297 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
298 | + memory_region_add_subregion(&s->iomem, | ||
299 | + 0x0, | ||
300 | + ®_array->mem); | ||
301 | + sysbus_init_mmio(sbd, &s->iomem); | ||
302 | + sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
303 | + sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
304 | +} | ||
305 | + | ||
306 | +static const VMStateDescription vmstate_rtc = { | ||
307 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
308 | + .version_id = 1, | ||
309 | + .minimum_version_id = 1, | ||
310 | + .fields = (VMStateField[]) { | ||
311 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
312 | + VMSTATE_END_OF_LIST(), | ||
313 | + } | ||
314 | +}; | ||
315 | + | ||
316 | +static void rtc_class_init(ObjectClass *klass, void *data) | ||
317 | +{ | ||
318 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
319 | + | ||
320 | + dc->reset = rtc_reset; | ||
321 | + dc->vmsd = &vmstate_rtc; | ||
322 | +} | ||
323 | + | ||
324 | +static const TypeInfo rtc_info = { | ||
325 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
326 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
327 | + .instance_size = sizeof(XlnxZynqMPRTC), | ||
328 | + .class_init = rtc_class_init, | ||
329 | + .instance_init = rtc_init, | ||
330 | +}; | ||
331 | + | ||
332 | +static void rtc_register_types(void) | ||
333 | +{ | ||
334 | + type_register_static(&rtc_info); | ||
335 | +} | ||
336 | + | ||
337 | +type_init(rtc_register_types) | ||
338 | -- | ||
339 | 2.16.2 | ||
340 | |||
341 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Allow the translate subroutines to return false for invalid insns. | 3 | Adds a line-item reference to the supported quanta-q71l-bmc aspeed |
4 | entry. | ||
4 | 5 | ||
5 | At present we can of course invoke an invalid insn exception from within | 6 | Signed-off-by: Patrick Venture <venture@google.com> |
6 | the translate subroutine, but in the short term this consolidates code. | 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
7 | In the long term it would allow the decodetree language to support | 8 | Message-id: 20210615192848.1065297-2-venture@google.com |
8 | overlapping patterns for ISA extensions. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20180227232618.2908-1-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 10 | --- |
15 | scripts/decodetree.py | 5 ++--- | 11 | docs/system/arm/aspeed.rst | 1 + |
16 | 1 file changed, 2 insertions(+), 3 deletions(-) | 12 | 1 file changed, 1 insertion(+) |
17 | 13 | ||
18 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
19 | index XXXXXXX..XXXXXXX 100755 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/scripts/decodetree.py | 16 | --- a/docs/system/arm/aspeed.rst |
21 | +++ b/scripts/decodetree.py | 17 | +++ b/docs/system/arm/aspeed.rst |
22 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | 18 | @@ -XXX,XX +XXX,XX @@ etc. |
23 | global translate_prefix | 19 | AST2400 SoC based machines : |
24 | output('typedef ', self.base.base.struct_name(), | 20 | |
25 | ' arg_', self.name, ';\n') | 21 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC |
26 | - output(translate_scope, 'void ', translate_prefix, '_', self.name, | 22 | +- ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
27 | + output(translate_scope, 'bool ', translate_prefix, '_', self.name, | 23 | |
28 | '(DisasContext *ctx, arg_', self.name, | 24 | AST2500 SoC based machines : |
29 | ' *a, ', insntype, ' insn);\n') | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | ||
32 | output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n') | ||
33 | for n, f in self.fields.items(): | ||
34 | output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') | ||
35 | - output(ind, translate_prefix, '_', self.name, | ||
36 | + output(ind, 'return ', translate_prefix, '_', self.name, | ||
37 | '(ctx, &u.f_', arg, ', insn);\n') | ||
38 | - output(ind, 'return true;\n') | ||
39 | # end Pattern | ||
40 | |||
41 | 25 | ||
42 | -- | 26 | -- |
43 | 2.16.2 | 27 | 2.20.1 |
44 | 28 | ||
45 | 29 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | 3 | Add line item reference to quanta-gbs-bmc machine. |
4 | 4 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Patrick Venture <venture@google.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
7 | Message-id: 20180228193125.20577-17-richard.henderson@linaro.org | 7 | Message-id: 20210615192848.1065297-3-venture@google.com |
8 | [PMM: fixed underline Sphinx warning] | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/cpu.c | 1 + | 11 | docs/system/arm/nuvoton.rst | 5 +++-- |
11 | target/arm/cpu64.c | 1 + | 12 | 1 file changed, 3 insertions(+), 2 deletions(-) |
12 | 2 files changed, 2 insertions(+) | ||
13 | 13 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 16 | --- a/docs/system/arm/nuvoton.rst |
17 | +++ b/target/arm/cpu.c | 17 | +++ b/docs/system/arm/nuvoton.rst |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 19 | -Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) |
20 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 20 | -===================================================== |
21 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 21 | +Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) |
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 22 | +================================================================ |
23 | cpu->midr = 0xffffffff; | 23 | |
24 | } | 24 | The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are |
25 | #endif | 25 | designed to be used as Baseboard Management Controllers (BMCs) in various |
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 26 | @@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip : |
27 | index XXXXXXX..XXXXXXX 100644 | 27 | The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and |
28 | --- a/target/arm/cpu64.c | 28 | Hyperscale applications. The following machines are based on this chip : |
29 | +++ b/target/arm/cpu64.c | 29 | |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 30 | +- ``quanta-gbs-bmc`` Quanta GBS server BMC |
31 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 31 | - ``quanta-gsj`` Quanta GSJ server BMC |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 32 | |
33 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 33 | There are also two more SoCs, NPCM710 and NPCM705, which are single-core |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | ||
35 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
36 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
37 | } | ||
38 | -- | 34 | -- |
39 | 2.16.2 | 35 | 2.20.1 |
40 | 36 | ||
41 | 37 | diff view generated by jsdifflib |
1 | The MPS2 AN505 FPGA image includes a "FPGA control block" | 1 | From: Nolan Leake <nolan@sigbus.net> |
---|---|---|---|
2 | which is a small set of registers handling LEDs, buttons | 2 | |
3 | and some counters. | 3 | This is just enough to make reboot and poweroff work. Works for |
4 | 4 | linux, u-boot, and the arm trusted firmware. Not tested, but should | |
5 | work for plan9, and bare-metal/hobby OSes, since they seem to generally | ||
6 | do what linux does for reset. | ||
7 | |||
8 | The watchdog timer functionality is not yet implemented. | ||
9 | |||
10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64 | ||
11 | Signed-off-by: Nolan Leake <nolan@sigbus.net> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20210625210209.1870217-1-nolan@sigbus.net | ||
15 | [PMM: tweaked commit title; fixed region size to 0x200; | ||
16 | moved header file to include/] | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-14-peter.maydell@linaro.org | ||
8 | --- | 18 | --- |
9 | hw/misc/Makefile.objs | 1 + | 19 | include/hw/arm/bcm2835_peripherals.h | 3 +- |
10 | include/hw/misc/mps2-fpgaio.h | 43 ++++++++++ | 20 | include/hw/misc/bcm2835_powermgt.h | 29 +++++ |
11 | hw/misc/mps2-fpgaio.c | 176 ++++++++++++++++++++++++++++++++++++++++ | 21 | hw/arm/bcm2835_peripherals.c | 13 ++- |
12 | default-configs/arm-softmmu.mak | 1 + | 22 | hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++ |
13 | hw/misc/trace-events | 6 ++ | 23 | hw/misc/meson.build | 1 + |
14 | 5 files changed, 227 insertions(+) | 24 | 5 files changed, 204 insertions(+), 2 deletions(-) |
15 | create mode 100644 include/hw/misc/mps2-fpgaio.h | 25 | create mode 100644 include/hw/misc/bcm2835_powermgt.h |
16 | create mode 100644 hw/misc/mps2-fpgaio.c | 26 | create mode 100644 hw/misc/bcm2835_powermgt.c |
17 | 27 | ||
18 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 28 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h |
19 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/misc/Makefile.objs | 30 | --- a/include/hw/arm/bcm2835_peripherals.h |
21 | +++ b/hw/misc/Makefile.objs | 31 | +++ b/include/hw/arm/bcm2835_peripherals.h |
22 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | 32 | @@ -XXX,XX +XXX,XX @@ |
23 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | 33 | #include "hw/misc/bcm2835_mphi.h" |
24 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | 34 | #include "hw/misc/bcm2835_thermal.h" |
25 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 35 | #include "hw/misc/bcm2835_cprman.h" |
26 | +obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 36 | +#include "hw/misc/bcm2835_powermgt.h" |
27 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 37 | #include "hw/sd/sdhci.h" |
28 | 38 | #include "hw/sd/bcm2835_sdhost.h" | |
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 39 | #include "hw/gpio/bcm2835_gpio.h" |
30 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h | 40 | @@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState { |
41 | BCM2835MphiState mphi; | ||
42 | UnimplementedDeviceState txp; | ||
43 | UnimplementedDeviceState armtmr; | ||
44 | - UnimplementedDeviceState powermgt; | ||
45 | + BCM2835PowerMgtState powermgt; | ||
46 | BCM2835CprmanState cprman; | ||
47 | PL011State uart0; | ||
48 | BCM2835AuxState aux; | ||
49 | diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h | ||
31 | new file mode 100644 | 50 | new file mode 100644 |
32 | index XXXXXXX..XXXXXXX | 51 | index XXXXXXX..XXXXXXX |
33 | --- /dev/null | 52 | --- /dev/null |
34 | +++ b/include/hw/misc/mps2-fpgaio.h | 53 | +++ b/include/hw/misc/bcm2835_powermgt.h |
35 | @@ -XXX,XX +XXX,XX @@ | 54 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 55 | +/* |
37 | + * ARM MPS2 FPGAIO emulation | 56 | + * BCM2835 Power Management emulation |
38 | + * | 57 | + * |
39 | + * Copyright (c) 2018 Linaro Limited | 58 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> |
40 | + * Written by Peter Maydell | 59 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> |
41 | + * | 60 | + * |
42 | + * This program is free software; you can redistribute it and/or modify | 61 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
43 | + * it under the terms of the GNU General Public License version 2 or | 62 | + * See the COPYING file in the top-level directory. |
44 | + * (at your option) any later version. | ||
45 | + */ | 63 | + */ |
46 | + | 64 | + |
47 | +/* This is a model of the FPGAIO register block in the AN505 | 65 | +#ifndef BCM2835_POWERMGT_H |
48 | + * FPGA image for the MPS2 dev board; it is documented in the | 66 | +#define BCM2835_POWERMGT_H |
49 | + * application note: | ||
50 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
51 | + * | ||
52 | + * QEMU interface: | ||
53 | + * + sysbus MMIO region 0: the register bank | ||
54 | + */ | ||
55 | + | ||
56 | +#ifndef MPS2_FPGAIO_H | ||
57 | +#define MPS2_FPGAIO_H | ||
58 | + | 67 | + |
59 | +#include "hw/sysbus.h" | 68 | +#include "hw/sysbus.h" |
60 | + | 69 | +#include "qom/object.h" |
61 | +#define TYPE_MPS2_FPGAIO "mps2-fpgaio" | 70 | + |
62 | +#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO) | 71 | +#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt" |
63 | + | 72 | +OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT) |
64 | +typedef struct { | 73 | + |
65 | + /*< private >*/ | 74 | +struct BCM2835PowerMgtState { |
66 | + SysBusDevice parent_obj; | 75 | + SysBusDevice busdev; |
67 | + | ||
68 | + /*< public >*/ | ||
69 | + MemoryRegion iomem; | 76 | + MemoryRegion iomem; |
70 | + | 77 | + |
71 | + uint32_t led0; | 78 | + uint32_t rstc; |
72 | + uint32_t prescale; | 79 | + uint32_t rsts; |
73 | + uint32_t misc; | 80 | + uint32_t wdog; |
74 | + | 81 | +}; |
75 | + uint32_t prescale_clk; | ||
76 | +} MPS2FPGAIO; | ||
77 | + | 82 | + |
78 | +#endif | 83 | +#endif |
79 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | 84 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c |
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/arm/bcm2835_peripherals.c | ||
87 | +++ b/hw/arm/bcm2835_peripherals.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) | ||
89 | |||
90 | object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", | ||
91 | OBJECT(&s->gpu_bus_mr)); | ||
92 | + | ||
93 | + /* Power Management */ | ||
94 | + object_initialize_child(obj, "powermgt", &s->powermgt, | ||
95 | + TYPE_BCM2835_POWERMGT); | ||
96 | } | ||
97 | |||
98 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
99 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
100 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | ||
101 | INTERRUPT_USB)); | ||
102 | |||
103 | + /* Power Management */ | ||
104 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { | ||
105 | + return; | ||
106 | + } | ||
107 | + | ||
108 | + memory_region_add_subregion(&s->peri_mr, PM_OFFSET, | ||
109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); | ||
110 | + | ||
111 | create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); | ||
112 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
113 | - create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); | ||
114 | create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
115 | create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
116 | create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
117 | diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c | ||
80 | new file mode 100644 | 118 | new file mode 100644 |
81 | index XXXXXXX..XXXXXXX | 119 | index XXXXXXX..XXXXXXX |
82 | --- /dev/null | 120 | --- /dev/null |
83 | +++ b/hw/misc/mps2-fpgaio.c | 121 | +++ b/hw/misc/bcm2835_powermgt.c |
84 | @@ -XXX,XX +XXX,XX @@ | 122 | @@ -XXX,XX +XXX,XX @@ |
85 | +/* | 123 | +/* |
86 | + * ARM MPS2 AN505 FPGAIO emulation | 124 | + * BCM2835 Power Management emulation |
87 | + * | 125 | + * |
88 | + * Copyright (c) 2018 Linaro Limited | 126 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> |
89 | + * Written by Peter Maydell | 127 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> |
90 | + * | 128 | + * |
91 | + * This program is free software; you can redistribute it and/or modify | 129 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
92 | + * it under the terms of the GNU General Public License version 2 or | 130 | + * See the COPYING file in the top-level directory. |
93 | + * (at your option) any later version. | ||
94 | + */ | ||
95 | + | ||
96 | +/* This is a model of the "FPGA system control and I/O" block found | ||
97 | + * in the AN505 FPGA image for the MPS2 devboard. | ||
98 | + * It is documented in AN505: | ||
99 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
100 | + */ | 131 | + */ |
101 | + | 132 | + |
102 | +#include "qemu/osdep.h" | 133 | +#include "qemu/osdep.h" |
103 | +#include "qemu/log.h" | 134 | +#include "qemu/log.h" |
104 | +#include "qapi/error.h" | 135 | +#include "qemu/module.h" |
105 | +#include "trace.h" | 136 | +#include "hw/misc/bcm2835_powermgt.h" |
106 | +#include "hw/sysbus.h" | 137 | +#include "migration/vmstate.h" |
107 | +#include "hw/registerfields.h" | 138 | +#include "sysemu/runstate.h" |
108 | +#include "hw/misc/mps2-fpgaio.h" | 139 | + |
109 | + | 140 | +#define PASSWORD 0x5a000000 |
110 | +REG32(LED0, 0) | 141 | +#define PASSWORD_MASK 0xff000000 |
111 | +REG32(BUTTON, 8) | 142 | + |
112 | +REG32(CLK1HZ, 0x10) | 143 | +#define R_RSTC 0x1c |
113 | +REG32(CLK100HZ, 0x14) | 144 | +#define V_RSTC_RESET 0x20 |
114 | +REG32(COUNTER, 0x18) | 145 | +#define R_RSTS 0x20 |
115 | +REG32(PRESCALE, 0x1c) | 146 | +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */ |
116 | +REG32(PSCNTR, 0x20) | 147 | +#define R_WDOG 0x24 |
117 | +REG32(MISC, 0x4c) | 148 | + |
118 | + | 149 | +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset, |
119 | +static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) | 150 | + unsigned size) |
120 | +{ | 151 | +{ |
121 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | 152 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; |
122 | + uint64_t r; | 153 | + uint32_t res = 0; |
123 | + | 154 | + |
124 | + switch (offset) { | 155 | + switch (offset) { |
125 | + case A_LED0: | 156 | + case R_RSTC: |
126 | + r = s->led0; | 157 | + res = s->rstc; |
127 | + break; | 158 | + break; |
128 | + case A_BUTTON: | 159 | + case R_RSTS: |
129 | + /* User-pressable board buttons. We don't model that, so just return | 160 | + res = s->rsts; |
130 | + * zeroes. | 161 | + break; |
131 | + */ | 162 | + case R_WDOG: |
132 | + r = 0; | 163 | + res = s->wdog; |
133 | + break; | 164 | + break; |
134 | + case A_PRESCALE: | 165 | + |
135 | + r = s->prescale; | ||
136 | + break; | ||
137 | + case A_MISC: | ||
138 | + r = s->misc; | ||
139 | + break; | ||
140 | + case A_CLK1HZ: | ||
141 | + case A_CLK100HZ: | ||
142 | + case A_COUNTER: | ||
143 | + case A_PSCNTR: | ||
144 | + /* These are all upcounters of various frequencies. */ | ||
145 | + qemu_log_mask(LOG_UNIMP, "MPS2 FPGAIO: counters unimplemented\n"); | ||
146 | + r = 0; | ||
147 | + break; | ||
148 | + default: | 166 | + default: |
167 | + qemu_log_mask(LOG_UNIMP, | ||
168 | + "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx | ||
169 | + "\n", offset); | ||
170 | + res = 0; | ||
171 | + break; | ||
172 | + } | ||
173 | + | ||
174 | + return res; | ||
175 | +} | ||
176 | + | ||
177 | +static void bcm2835_powermgt_write(void *opaque, hwaddr offset, | ||
178 | + uint64_t value, unsigned size) | ||
179 | +{ | ||
180 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | ||
181 | + | ||
182 | + if ((value & PASSWORD_MASK) != PASSWORD) { | ||
149 | + qemu_log_mask(LOG_GUEST_ERROR, | 183 | + qemu_log_mask(LOG_GUEST_ERROR, |
150 | + "MPS2 FPGAIO read: bad offset %x\n", (int) offset); | 184 | + "bcm2835_powermgt_write: Bad password 0x%"PRIx64 |
151 | + r = 0; | 185 | + " at offset 0x%08"HWADDR_PRIx"\n", |
152 | + break; | 186 | + value, offset); |
153 | + } | 187 | + return; |
154 | + | 188 | + } |
155 | + trace_mps2_fpgaio_read(offset, r, size); | 189 | + |
156 | + return r; | 190 | + value = value & ~PASSWORD_MASK; |
157 | +} | ||
158 | + | ||
159 | +static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, | ||
160 | + unsigned size) | ||
161 | +{ | ||
162 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | ||
163 | + | ||
164 | + trace_mps2_fpgaio_write(offset, value, size); | ||
165 | + | 191 | + |
166 | + switch (offset) { | 192 | + switch (offset) { |
167 | + case A_LED0: | 193 | + case R_RSTC: |
168 | + /* LED bits [1:0] control board LEDs. We don't currently have | 194 | + s->rstc = value; |
169 | + * a mechanism for displaying this graphically, so use a trace event. | 195 | + if (value & V_RSTC_RESET) { |
170 | + */ | 196 | + if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) { |
171 | + trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', | 197 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
172 | + value & 0x01 ? '*' : '.'); | 198 | + } else { |
173 | + s->led0 = value & 0x3; | 199 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
174 | + break; | 200 | + } |
175 | + case A_PRESCALE: | 201 | + } |
176 | + s->prescale = value; | 202 | + break; |
177 | + break; | 203 | + case R_RSTS: |
178 | + case A_MISC: | 204 | + qemu_log_mask(LOG_UNIMP, |
179 | + /* These are control bits for some of the other devices on the | 205 | + "bcm2835_powermgt_write: RSTS\n"); |
180 | + * board (SPI, CLCD, etc). We don't implement that yet, so just | 206 | + s->rsts = value; |
181 | + * make the bits read as written. | 207 | + break; |
182 | + */ | 208 | + case R_WDOG: |
183 | + qemu_log_mask(LOG_UNIMP, | 209 | + qemu_log_mask(LOG_UNIMP, |
184 | + "MPS2 FPGAIO: MISC control bits unimplemented\n"); | 210 | + "bcm2835_powermgt_write: WDOG\n"); |
185 | + s->misc = value; | 211 | + s->wdog = value; |
186 | + break; | 212 | + break; |
213 | + | ||
187 | + default: | 214 | + default: |
188 | + qemu_log_mask(LOG_GUEST_ERROR, | 215 | + qemu_log_mask(LOG_UNIMP, |
189 | + "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); | 216 | + "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx |
190 | + break; | 217 | + "\n", offset); |
191 | + } | 218 | + break; |
192 | +} | 219 | + } |
193 | + | 220 | +} |
194 | +static const MemoryRegionOps mps2_fpgaio_ops = { | 221 | + |
195 | + .read = mps2_fpgaio_read, | 222 | +static const MemoryRegionOps bcm2835_powermgt_ops = { |
196 | + .write = mps2_fpgaio_write, | 223 | + .read = bcm2835_powermgt_read, |
197 | + .endianness = DEVICE_LITTLE_ENDIAN, | 224 | + .write = bcm2835_powermgt_write, |
198 | +}; | 225 | + .endianness = DEVICE_NATIVE_ENDIAN, |
199 | + | 226 | + .impl.min_access_size = 4, |
200 | +static void mps2_fpgaio_reset(DeviceState *dev) | 227 | + .impl.max_access_size = 4, |
201 | +{ | 228 | +}; |
202 | + MPS2FPGAIO *s = MPS2_FPGAIO(dev); | 229 | + |
203 | + | 230 | +static const VMStateDescription vmstate_bcm2835_powermgt = { |
204 | + trace_mps2_fpgaio_reset(); | 231 | + .name = TYPE_BCM2835_POWERMGT, |
205 | + s->led0 = 0; | ||
206 | + s->prescale = 0; | ||
207 | + s->misc = 0; | ||
208 | +} | ||
209 | + | ||
210 | +static void mps2_fpgaio_init(Object *obj) | ||
211 | +{ | ||
212 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
213 | + MPS2FPGAIO *s = MPS2_FPGAIO(obj); | ||
214 | + | ||
215 | + memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, | ||
216 | + "mps2-fpgaio", 0x1000); | ||
217 | + sysbus_init_mmio(sbd, &s->iomem); | ||
218 | +} | ||
219 | + | ||
220 | +static const VMStateDescription mps2_fpgaio_vmstate = { | ||
221 | + .name = "mps2-fpgaio", | ||
222 | + .version_id = 1, | 232 | + .version_id = 1, |
223 | + .minimum_version_id = 1, | 233 | + .minimum_version_id = 1, |
224 | + .fields = (VMStateField[]) { | 234 | + .fields = (VMStateField[]) { |
225 | + VMSTATE_UINT32(led0, MPS2FPGAIO), | 235 | + VMSTATE_UINT32(rstc, BCM2835PowerMgtState), |
226 | + VMSTATE_UINT32(prescale, MPS2FPGAIO), | 236 | + VMSTATE_UINT32(rsts, BCM2835PowerMgtState), |
227 | + VMSTATE_UINT32(misc, MPS2FPGAIO), | 237 | + VMSTATE_UINT32(wdog, BCM2835PowerMgtState), |
228 | + VMSTATE_END_OF_LIST() | 238 | + VMSTATE_END_OF_LIST() |
229 | + } | 239 | + } |
230 | +}; | 240 | +}; |
231 | + | 241 | + |
232 | +static Property mps2_fpgaio_properties[] = { | 242 | +static void bcm2835_powermgt_init(Object *obj) |
233 | + /* Frequency of the prescale counter */ | 243 | +{ |
234 | + DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), | 244 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj); |
235 | + DEFINE_PROP_END_OF_LIST(), | 245 | + |
236 | +}; | 246 | + memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s, |
237 | + | 247 | + TYPE_BCM2835_POWERMGT, 0x200); |
238 | +static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) | 248 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); |
249 | +} | ||
250 | + | ||
251 | +static void bcm2835_powermgt_reset(DeviceState *dev) | ||
252 | +{ | ||
253 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev); | ||
254 | + | ||
255 | + /* https://elinux.org/BCM2835_registers#PM */ | ||
256 | + s->rstc = 0x00000102; | ||
257 | + s->rsts = 0x00001000; | ||
258 | + s->wdog = 0x00000000; | ||
259 | +} | ||
260 | + | ||
261 | +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) | ||
239 | +{ | 262 | +{ |
240 | + DeviceClass *dc = DEVICE_CLASS(klass); | 263 | + DeviceClass *dc = DEVICE_CLASS(klass); |
241 | + | 264 | + |
242 | + dc->vmsd = &mps2_fpgaio_vmstate; | 265 | + dc->reset = bcm2835_powermgt_reset; |
243 | + dc->reset = mps2_fpgaio_reset; | 266 | + dc->vmsd = &vmstate_bcm2835_powermgt; |
244 | + dc->props = mps2_fpgaio_properties; | 267 | +} |
245 | +} | 268 | + |
246 | + | 269 | +static TypeInfo bcm2835_powermgt_info = { |
247 | +static const TypeInfo mps2_fpgaio_info = { | 270 | + .name = TYPE_BCM2835_POWERMGT, |
248 | + .name = TYPE_MPS2_FPGAIO, | 271 | + .parent = TYPE_SYS_BUS_DEVICE, |
249 | + .parent = TYPE_SYS_BUS_DEVICE, | 272 | + .instance_size = sizeof(BCM2835PowerMgtState), |
250 | + .instance_size = sizeof(MPS2FPGAIO), | 273 | + .class_init = bcm2835_powermgt_class_init, |
251 | + .instance_init = mps2_fpgaio_init, | 274 | + .instance_init = bcm2835_powermgt_init, |
252 | + .class_init = mps2_fpgaio_class_init, | 275 | +}; |
253 | +}; | 276 | + |
254 | + | 277 | +static void bcm2835_powermgt_register_types(void) |
255 | +static void mps2_fpgaio_register_types(void) | 278 | +{ |
256 | +{ | 279 | + type_register_static(&bcm2835_powermgt_info); |
257 | + type_register_static(&mps2_fpgaio_info); | 280 | +} |
258 | +} | 281 | + |
259 | + | 282 | +type_init(bcm2835_powermgt_register_types) |
260 | +type_init(mps2_fpgaio_register_types); | 283 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build |
261 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
262 | index XXXXXXX..XXXXXXX 100644 | 284 | index XXXXXXX..XXXXXXX 100644 |
263 | --- a/default-configs/arm-softmmu.mak | 285 | --- a/hw/misc/meson.build |
264 | +++ b/default-configs/arm-softmmu.mak | 286 | +++ b/hw/misc/meson.build |
265 | @@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y | 287 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( |
266 | CONFIG_CMSDK_APB_TIMER=y | 288 | 'bcm2835_rng.c', |
267 | CONFIG_CMSDK_APB_UART=y | 289 | 'bcm2835_thermal.c', |
268 | 290 | 'bcm2835_cprman.c', | |
269 | +CONFIG_MPS2_FPGAIO=y | 291 | + 'bcm2835_powermgt.c', |
270 | CONFIG_MPS2_SCC=y | 292 | )) |
271 | 293 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | |
272 | CONFIG_VERSATILE_PCI=y | 294 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) |
273 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
274 | index XXXXXXX..XXXXXXX 100644 | ||
275 | --- a/hw/misc/trace-events | ||
276 | +++ b/hw/misc/trace-events | ||
277 | @@ -XXX,XX +XXX,XX @@ mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, | ||
278 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 | ||
279 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 | ||
280 | |||
281 | +# hw/misc/mps2_fpgaio.c | ||
282 | +mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
283 | +mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
284 | +mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" | ||
285 | +mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c" | ||
286 | + | ||
287 | # hw/misc/msf2-sysreg.c | ||
288 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 | ||
289 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32 | ||
290 | -- | 295 | -- |
291 | 2.16.2 | 296 | 2.20.1 |
292 | 297 | ||
293 | 298 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Happily, the bits are in the same places compared to a32. | 3 | Add a test booting and quickly shutdown a raspi2 machine, |
4 | to test the power management model: | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd: |
6 | Message-id: 20180228193125.20577-16-richard.henderson@linaro.org | 7 | console: [ 0.000000] Booting Linux on physical CPU 0xf00 |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019 |
9 | console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d | ||
10 | console: [ 0.000000] CPU: div instructions available: patching division code | ||
11 | console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
12 | console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B | ||
13 | ... | ||
14 | console: Boot successful. | ||
15 | console: cat /proc/cpuinfo | ||
16 | console: / # cat /proc/cpuinfo | ||
17 | ... | ||
18 | console: processor : 3 | ||
19 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
20 | console: BogoMIPS : 125.00 | ||
21 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
22 | console: CPU implementer : 0x41 | ||
23 | console: CPU architecture: 7 | ||
24 | console: CPU variant : 0x0 | ||
25 | console: CPU part : 0xc07 | ||
26 | console: CPU revision : 5 | ||
27 | console: Hardware : BCM2835 | ||
28 | console: Revision : 0000 | ||
29 | console: Serial : 0000000000000000 | ||
30 | console: cat /proc/iomem | ||
31 | console: / # cat /proc/iomem | ||
32 | console: 00000000-3bffffff : System RAM | ||
33 | console: 00008000-00afffff : Kernel code | ||
34 | console: 00c00000-00d468ef : Kernel data | ||
35 | console: 3f006000-3f006fff : dwc_otg | ||
36 | console: 3f007000-3f007eff : /soc/dma@7e007000 | ||
37 | console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880 | ||
38 | console: 3f100000-3f100027 : /soc/watchdog@7e100000 | ||
39 | console: 3f101000-3f102fff : /soc/cprman@7e101000 | ||
40 | console: 3f200000-3f2000b3 : /soc/gpio@7e200000 | ||
41 | PASS (24.59 s) | ||
42 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
43 | JOB TIME : 25.02 s | ||
44 | |||
45 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
46 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
47 | Message-id: 20210531113837.1689775-1-f4bug@amsat.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 48 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 49 | --- |
10 | target/arm/translate.c | 14 +++++++++++++- | 50 | tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++ |
11 | 1 file changed, 13 insertions(+), 1 deletion(-) | 51 | 1 file changed, 43 insertions(+) |
12 | 52 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 53 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py |
14 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 55 | --- a/tests/acceptance/boot_linux_console.py |
16 | +++ b/target/arm/translate.c | 56 | +++ b/tests/acceptance/boot_linux_console.py |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 57 | @@ -XXX,XX +XXX,XX @@ |
18 | default_exception_el(s)); | 58 | from avocado import skip |
19 | break; | 59 | from avocado import skipUnless |
20 | } | 60 | from avocado_qemu import Test |
21 | - if (((insn >> 24) & 3) == 3) { | 61 | +from avocado_qemu import exec_command |
22 | + if ((insn & 0xfe000a00) == 0xfc000800 | 62 | from avocado_qemu import exec_command_and_wait_for_pattern |
23 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 63 | from avocado_qemu import interrupt_interactive_console_until_pattern |
24 | + /* The Thumb2 and ARM encodings are identical. */ | 64 | from avocado_qemu import wait_for_console_pattern |
25 | + if (disas_neon_insn_3same_ext(s, insn)) { | 65 | @@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self): |
26 | + goto illegal_op; | 66 | """ |
27 | + } | 67 | self.do_test_arm_raspi2(0) |
28 | + } else if ((insn & 0xff000a00) == 0xfe000800 | 68 | |
29 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 69 | + def test_arm_raspi2_initrd(self): |
30 | + /* The Thumb2 and ARM encodings are identical. */ | 70 | + """ |
31 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | 71 | + :avocado: tags=arch:arm |
32 | + goto illegal_op; | 72 | + :avocado: tags=machine:raspi2 |
33 | + } | 73 | + """ |
34 | + } else if (((insn >> 24) & 3) == 3) { | 74 | + deb_url = ('http://archive.raspberrypi.org/debian/' |
35 | /* Translate into the equivalent ARM encoding. */ | 75 | + 'pool/main/r/raspberrypi-firmware/' |
36 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | 76 | + 'raspberrypi-kernel_1.20190215-1_armhf.deb') |
37 | if (disas_neon_data_insn(s, insn)) { | 77 | + deb_hash = 'cd284220b32128c5084037553db3c482426f3972' |
78 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
79 | + kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img') | ||
80 | + dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb') | ||
81 | + | ||
82 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
83 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
84 | + 'arm/rootfs-armv7a.cpio.gz') | ||
85 | + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' | ||
86 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) | ||
87 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') | ||
88 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) | ||
89 | + | ||
90 | + self.vm.set_console() | ||
91 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | ||
92 | + 'earlycon=pl011,0x3f201000 console=ttyAMA0 ' | ||
93 | + 'panic=-1 noreboot ' + | ||
94 | + 'dwc_otg.fiq_fsm_enable=0') | ||
95 | + self.vm.add_args('-kernel', kernel_path, | ||
96 | + '-dtb', dtb_path, | ||
97 | + '-initrd', initrd_path, | ||
98 | + '-append', kernel_command_line, | ||
99 | + '-no-reboot') | ||
100 | + self.vm.launch() | ||
101 | + self.wait_for_console_pattern('Boot successful.') | ||
102 | + | ||
103 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | ||
104 | + 'BCM2835') | ||
105 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | ||
106 | + '/soc/cprman@7e101000') | ||
107 | + exec_command(self, 'halt') | ||
108 | + # Wait for VM to shut down gracefully | ||
109 | + self.vm.wait() | ||
110 | + | ||
111 | def test_arm_exynos4210_initrd(self): | ||
112 | """ | ||
113 | :avocado: tags=arch:arm | ||
38 | -- | 114 | -- |
39 | 2.16.2 | 115 | 2.20.1 |
40 | 116 | ||
41 | 117 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@xilinx.com> | 1 | From: Joe Komlodi <joe.komlodi@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Allow the guest to determine the time set from the QEMU command line. | 3 | If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute |
4 | FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will | ||
5 | assert due to fpst->default_nan_mode being set. | ||
4 | 6 | ||
5 | This includes adding a trace event to debug the new time. | 7 | To avoid this, we check to see what NaN mode we're running in before we call |
8 | floatxx_silence_nan(). | ||
6 | 9 | ||
7 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | 10 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 15 | --- |
12 | include/hw/timer/xlnx-zynqmp-rtc.h | 2 ++ | 16 | target/arm/helper-a64.c | 12 +++++++++--- |
13 | hw/timer/xlnx-zynqmp-rtc.c | 58 ++++++++++++++++++++++++++++++++++++++ | 17 | target/arm/vfp_helper.c | 24 ++++++++++++++++++------ |
14 | hw/timer/trace-events | 3 ++ | 18 | 2 files changed, 27 insertions(+), 9 deletions(-) |
15 | 3 files changed, 63 insertions(+) | ||
16 | 19 | ||
17 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | 20 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/timer/xlnx-zynqmp-rtc.h | 22 | --- a/target/arm/helper-a64.c |
20 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | 23 | +++ b/target/arm/helper-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPRTC { | 24 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) |
22 | qemu_irq irq_rtc_int; | 25 | float16 nan = a; |
23 | qemu_irq irq_addr_error_int; | 26 | if (float16_is_signaling_nan(a, fpst)) { |
24 | 27 | float_raise(float_flag_invalid, fpst); | |
25 | + uint32_t tick_offset; | 28 | - nan = float16_silence_nan(a, fpst); |
26 | + | 29 | + if (!fpst->default_nan_mode) { |
27 | uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | 30 | + nan = float16_silence_nan(a, fpst); |
28 | RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | 31 | + } |
29 | } XlnxZynqMPRTC; | 32 | } |
30 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | 33 | if (fpst->default_nan_mode) { |
34 | nan = float16_default_nan(fpst); | ||
35 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) | ||
36 | float32 nan = a; | ||
37 | if (float32_is_signaling_nan(a, fpst)) { | ||
38 | float_raise(float_flag_invalid, fpst); | ||
39 | - nan = float32_silence_nan(a, fpst); | ||
40 | + if (!fpst->default_nan_mode) { | ||
41 | + nan = float32_silence_nan(a, fpst); | ||
42 | + } | ||
43 | } | ||
44 | if (fpst->default_nan_mode) { | ||
45 | nan = float32_default_nan(fpst); | ||
46 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | ||
47 | float64 nan = a; | ||
48 | if (float64_is_signaling_nan(a, fpst)) { | ||
49 | float_raise(float_flag_invalid, fpst); | ||
50 | - nan = float64_silence_nan(a, fpst); | ||
51 | + if (!fpst->default_nan_mode) { | ||
52 | + nan = float64_silence_nan(a, fpst); | ||
53 | + } | ||
54 | } | ||
55 | if (fpst->default_nan_mode) { | ||
56 | nan = float64_default_nan(fpst); | ||
57 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | 58 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/timer/xlnx-zynqmp-rtc.c | 59 | --- a/target/arm/vfp_helper.c |
33 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | 60 | +++ b/target/arm/vfp_helper.c |
34 | @@ -XXX,XX +XXX,XX @@ | 61 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) |
35 | #include "hw/register.h" | 62 | float16 nan = f16; |
36 | #include "qemu/bitops.h" | 63 | if (float16_is_signaling_nan(f16, fpst)) { |
37 | #include "qemu/log.h" | 64 | float_raise(float_flag_invalid, fpst); |
38 | +#include "hw/ptimer.h" | 65 | - nan = float16_silence_nan(f16, fpst); |
39 | +#include "qemu/cutils.h" | 66 | + if (!fpst->default_nan_mode) { |
40 | +#include "sysemu/sysemu.h" | 67 | + nan = float16_silence_nan(f16, fpst); |
41 | +#include "trace.h" | 68 | + } |
42 | #include "hw/timer/xlnx-zynqmp-rtc.h" | 69 | } |
43 | 70 | if (fpst->default_nan_mode) { | |
44 | #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | 71 | nan = float16_default_nan(fpst); |
45 | @@ -XXX,XX +XXX,XX @@ static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | 72 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) |
46 | qemu_set_irq(s->irq_addr_error_int, pending); | 73 | float32 nan = f32; |
47 | } | 74 | if (float32_is_signaling_nan(f32, fpst)) { |
48 | 75 | float_raise(float_flag_invalid, fpst); | |
49 | +static uint32_t rtc_get_count(XlnxZynqMPRTC *s) | 76 | - nan = float32_silence_nan(f32, fpst); |
50 | +{ | 77 | + if (!fpst->default_nan_mode) { |
51 | + int64_t now = qemu_clock_get_ns(rtc_clock); | 78 | + nan = float32_silence_nan(f32, fpst); |
52 | + return s->tick_offset + now / NANOSECONDS_PER_SECOND; | 79 | + } |
53 | +} | 80 | } |
54 | + | 81 | if (fpst->default_nan_mode) { |
55 | +static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64) | 82 | nan = float32_default_nan(fpst); |
56 | +{ | 83 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) |
57 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 84 | float64 nan = f64; |
58 | + | 85 | if (float64_is_signaling_nan(f64, fpst)) { |
59 | + return rtc_get_count(s); | 86 | float_raise(float_flag_invalid, fpst); |
60 | +} | 87 | - nan = float64_silence_nan(f64, fpst); |
61 | + | 88 | + if (!fpst->default_nan_mode) { |
62 | static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | 89 | + nan = float64_silence_nan(f64, fpst); |
63 | { | 90 | + } |
64 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 91 | } |
65 | @@ -XXX,XX +XXX,XX @@ static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | 92 | if (fpst->default_nan_mode) { |
66 | 93 | nan = float64_default_nan(fpst); | |
67 | static const RegisterAccessInfo rtc_regs_info[] = { | 94 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) |
68 | { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | 95 | float16 nan = f16; |
69 | + .unimp = MAKE_64BIT_MASK(0, 32), | 96 | if (float16_is_signaling_nan(f16, s)) { |
70 | },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | 97 | float_raise(float_flag_invalid, s); |
71 | .ro = 0xffffffff, | 98 | - nan = float16_silence_nan(f16, s); |
72 | + .post_read = current_time_postr, | 99 | + if (!s->default_nan_mode) { |
73 | },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | 100 | + nan = float16_silence_nan(f16, fpstp); |
74 | + .unimp = MAKE_64BIT_MASK(0, 32), | 101 | + } |
75 | },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | 102 | } |
76 | .ro = 0x1fffff, | 103 | if (s->default_nan_mode) { |
77 | },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | 104 | nan = float16_default_nan(s); |
78 | .ro = 0xffffffff, | 105 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
79 | + .post_read = current_time_postr, | 106 | float32 nan = f32; |
80 | },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | 107 | if (float32_is_signaling_nan(f32, s)) { |
81 | .ro = 0xffff, | 108 | float_raise(float_flag_invalid, s); |
82 | },{ .name = "ALARM", .addr = A_ALARM, | 109 | - nan = float32_silence_nan(f32, s); |
83 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | 110 | + if (!s->default_nan_mode) { |
84 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | 111 | + nan = float32_silence_nan(f32, fpstp); |
85 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 112 | + } |
86 | RegisterInfoArray *reg_array; | 113 | } |
87 | + struct tm current_tm; | 114 | if (s->default_nan_mode) { |
88 | 115 | nan = float32_default_nan(s); | |
89 | memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | 116 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
90 | XLNX_ZYNQMP_RTC_R_MAX * 4); | 117 | float64 nan = f64; |
91 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | 118 | if (float64_is_signaling_nan(f64, s)) { |
92 | sysbus_init_mmio(sbd, &s->iomem); | 119 | float_raise(float_flag_invalid, s); |
93 | sysbus_init_irq(sbd, &s->irq_rtc_int); | 120 | - nan = float64_silence_nan(f64, s); |
94 | sysbus_init_irq(sbd, &s->irq_addr_error_int); | 121 | + if (!s->default_nan_mode) { |
95 | + | 122 | + nan = float64_silence_nan(f64, fpstp); |
96 | + qemu_get_timedate(¤t_tm, 0); | 123 | + } |
97 | + s->tick_offset = mktimegm(¤t_tm) - | 124 | } |
98 | + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | 125 | if (s->default_nan_mode) { |
99 | + | 126 | nan = float64_default_nan(s); |
100 | + trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon, | ||
101 | + current_tm.tm_mday, current_tm.tm_hour, | ||
102 | + current_tm.tm_min, current_tm.tm_sec); | ||
103 | +} | ||
104 | + | ||
105 | +static int rtc_pre_save(void *opaque) | ||
106 | +{ | ||
107 | + XlnxZynqMPRTC *s = opaque; | ||
108 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
109 | + | ||
110 | + /* Add the time at migration */ | ||
111 | + s->tick_offset = s->tick_offset + now; | ||
112 | + | ||
113 | + return 0; | ||
114 | +} | ||
115 | + | ||
116 | +static int rtc_post_load(void *opaque, int version_id) | ||
117 | +{ | ||
118 | + XlnxZynqMPRTC *s = opaque; | ||
119 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
120 | + | ||
121 | + /* Subtract the time after migration. This combined with the pre_save | ||
122 | + * action results in us having subtracted the time that the guest was | ||
123 | + * stopped to the offset. | ||
124 | + */ | ||
125 | + s->tick_offset = s->tick_offset - now; | ||
126 | + | ||
127 | + return 0; | ||
128 | } | ||
129 | |||
130 | static const VMStateDescription vmstate_rtc = { | ||
131 | .name = TYPE_XLNX_ZYNQMP_RTC, | ||
132 | .version_id = 1, | ||
133 | .minimum_version_id = 1, | ||
134 | + .pre_save = rtc_pre_save, | ||
135 | + .post_load = rtc_post_load, | ||
136 | .fields = (VMStateField[]) { | ||
137 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
138 | + VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC), | ||
139 | VMSTATE_END_OF_LIST(), | ||
140 | } | ||
141 | }; | ||
142 | diff --git a/hw/timer/trace-events b/hw/timer/trace-events | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/hw/timer/trace-events | ||
145 | +++ b/hw/timer/trace-events | ||
146 | @@ -XXX,XX +XXX,XX @@ systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr | ||
147 | cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
148 | cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
149 | cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" | ||
150 | + | ||
151 | +# hw/timer/xlnx-zynqmp-rtc.c | ||
152 | +xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" | ||
153 | -- | 127 | -- |
154 | 2.16.2 | 128 | 2.20.1 |
155 | 129 | ||
156 | 130 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | ||
9 | hw/arm/xlnx-zynqmp.c | 14 ++++++++++++++ | ||
10 | 2 files changed, 16 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
15 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | #include "hw/dma/xlnx_dpdma.h" | ||
18 | #include "hw/display/xlnx_dp.h" | ||
19 | #include "hw/intc/xlnx-zynqmp-ipi.h" | ||
20 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
21 | |||
22 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | ||
23 | #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState { | ||
25 | XlnxDPState dp; | ||
26 | XlnxDPDMAState dpdma; | ||
27 | XlnxZynqMPIPI ipi; | ||
28 | + XlnxZynqMPRTC rtc; | ||
29 | |||
30 | char *boot_cpu; | ||
31 | ARMCPU *boot_cpu_ptr; | ||
32 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/xlnx-zynqmp.c | ||
35 | +++ b/hw/arm/xlnx-zynqmp.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #define IPI_ADDR 0xFF300000 | ||
38 | #define IPI_IRQ 64 | ||
39 | |||
40 | +#define RTC_ADDR 0xffa60000 | ||
41 | +#define RTC_IRQ 26 | ||
42 | + | ||
43 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | ||
44 | |||
45 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | ||
46 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | ||
47 | |||
48 | object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); | ||
49 | qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); | ||
50 | + | ||
51 | + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); | ||
52 | + qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); | ||
53 | } | ||
54 | |||
55 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
56 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
57 | } | ||
58 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | ||
59 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | ||
60 | + | ||
61 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | ||
62 | + if (err) { | ||
63 | + error_propagate(errp, err); | ||
64 | + return; | ||
65 | + } | ||
66 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | ||
67 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | ||
68 | } | ||
69 | |||
70 | static Property xlnx_zynqmp_props[] = { | ||
71 | -- | ||
72 | 2.16.2 | ||
73 | |||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add a function load_ramdisk_as() which behaves like the existing | ||
2 | load_ramdisk() but allows the caller to specify the AddressSpace | ||
3 | to use. This matches the pattern we have already for various | ||
4 | other loader functions. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/hw/loader.h | 12 +++++++++++- | ||
12 | hw/core/loader.c | 8 +++++++- | ||
13 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/loader.h b/include/hw/loader.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/loader.h | ||
18 | +++ b/include/hw/loader.h | ||
19 | @@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep, | ||
20 | void *translate_opaque); | ||
21 | |||
22 | /** | ||
23 | - * load_ramdisk: | ||
24 | + * load_ramdisk_as: | ||
25 | * @filename: Path to the ramdisk image | ||
26 | * @addr: Memory address to load the ramdisk to | ||
27 | * @max_sz: Maximum allowed ramdisk size (for non-u-boot ramdisks) | ||
28 | + * @as: The AddressSpace to load the ELF to. The value of address_space_memory | ||
29 | + * is used if nothing is supplied here. | ||
30 | * | ||
31 | * Load a ramdisk image with U-Boot header to the specified memory | ||
32 | * address. | ||
33 | * | ||
34 | * Returns the size of the loaded image on success, -1 otherwise. | ||
35 | */ | ||
36 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
37 | + AddressSpace *as); | ||
38 | + | ||
39 | +/** | ||
40 | + * load_ramdisk: | ||
41 | + * Same as load_ramdisk_as(), but doesn't allow the caller to specify | ||
42 | + * an AddressSpace. | ||
43 | + */ | ||
44 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz); | ||
45 | |||
46 | ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen); | ||
47 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/core/loader.c | ||
50 | +++ b/hw/core/loader.c | ||
51 | @@ -XXX,XX +XXX,XX @@ int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr, | ||
52 | |||
53 | /* Load a ramdisk. */ | ||
54 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz) | ||
55 | +{ | ||
56 | + return load_ramdisk_as(filename, addr, max_sz, NULL); | ||
57 | +} | ||
58 | + | ||
59 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
60 | + AddressSpace *as) | ||
61 | { | ||
62 | return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK, | ||
63 | - NULL, NULL, NULL); | ||
64 | + NULL, NULL, as); | ||
65 | } | ||
66 | |||
67 | /* Load a gzip-compressed kernel to a dynamically allocated buffer. */ | ||
68 | -- | ||
69 | 2.16.2 | ||
70 | |||
71 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Instead of loading kernels, device trees, and the like to | ||
2 | the system address space, use the CPU's address space. This | ||
3 | is important if we're trying to load the file to memory or | ||
4 | via an alias memory region that is provided by an SoC | ||
5 | object and thus not mapped into the system address space. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-3-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/arm/boot.c | 119 +++++++++++++++++++++++++++++++++++++--------------------- | ||
13 | 1 file changed, 76 insertions(+), 43 deletions(-) | ||
14 | |||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/boot.c | ||
18 | +++ b/hw/arm/boot.c | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #define ARM64_TEXT_OFFSET_OFFSET 8 | ||
21 | #define ARM64_MAGIC_OFFSET 56 | ||
22 | |||
23 | +static AddressSpace *arm_boot_address_space(ARMCPU *cpu, | ||
24 | + const struct arm_boot_info *info) | ||
25 | +{ | ||
26 | + /* Return the address space to use for bootloader reads and writes. | ||
27 | + * We prefer the secure address space if the CPU has it and we're | ||
28 | + * going to boot the guest into it. | ||
29 | + */ | ||
30 | + int asidx; | ||
31 | + CPUState *cs = CPU(cpu); | ||
32 | + | ||
33 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { | ||
34 | + asidx = ARMASIdx_S; | ||
35 | + } else { | ||
36 | + asidx = ARMASIdx_NS; | ||
37 | + } | ||
38 | + | ||
39 | + return cpu_get_address_space(cs, asidx); | ||
40 | +} | ||
41 | + | ||
42 | typedef enum { | ||
43 | FIXUP_NONE = 0, /* do nothing */ | ||
44 | FIXUP_TERMINATOR, /* end of insns */ | ||
45 | @@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup smpboot[] = { | ||
46 | }; | ||
47 | |||
48 | static void write_bootloader(const char *name, hwaddr addr, | ||
49 | - const ARMInsnFixup *insns, uint32_t *fixupcontext) | ||
50 | + const ARMInsnFixup *insns, uint32_t *fixupcontext, | ||
51 | + AddressSpace *as) | ||
52 | { | ||
53 | /* Fix up the specified bootloader fragment and write it into | ||
54 | * guest memory using rom_add_blob_fixed(). fixupcontext is | ||
55 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr, | ||
56 | code[i] = tswap32(insn); | ||
57 | } | ||
58 | |||
59 | - rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); | ||
60 | + rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); | ||
61 | |||
62 | g_free(code); | ||
63 | } | ||
64 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
65 | const struct arm_boot_info *info) | ||
66 | { | ||
67 | uint32_t fixupcontext[FIXUP_MAX]; | ||
68 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
69 | |||
70 | fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; | ||
71 | fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; | ||
72 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
73 | } | ||
74 | |||
75 | write_bootloader("smpboot", info->smp_loader_start, | ||
76 | - smpboot, fixupcontext); | ||
77 | + smpboot, fixupcontext, as); | ||
78 | } | ||
79 | |||
80 | void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
81 | const struct arm_boot_info *info, | ||
82 | hwaddr mvbar_addr) | ||
83 | { | ||
84 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
85 | int n; | ||
86 | uint32_t mvbar_blob[] = { | ||
87 | /* mvbar_addr: secure monitor vectors | ||
88 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
89 | for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { | ||
90 | mvbar_blob[n] = tswap32(mvbar_blob[n]); | ||
91 | } | ||
92 | - rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
93 | - mvbar_addr); | ||
94 | + rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
95 | + mvbar_addr, as); | ||
96 | |||
97 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | ||
98 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | ||
99 | } | ||
100 | - rom_add_blob_fixed("board-setup", board_setup_blob, | ||
101 | - sizeof(board_setup_blob), info->board_setup_addr); | ||
102 | + rom_add_blob_fixed_as("board-setup", board_setup_blob, | ||
103 | + sizeof(board_setup_blob), info->board_setup_addr, as); | ||
104 | } | ||
105 | |||
106 | static void default_reset_secondary(ARMCPU *cpu, | ||
107 | const struct arm_boot_info *info) | ||
108 | { | ||
109 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
110 | CPUState *cs = CPU(cpu); | ||
111 | |||
112 | - address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, | ||
113 | + address_space_stl_notdirty(as, info->smp_bootreg_addr, | ||
114 | 0, MEMTXATTRS_UNSPECIFIED, NULL); | ||
115 | cpu_set_pc(cs, info->smp_loader_start); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static inline bool have_dtb(const struct arm_boot_info *info) | ||
118 | } | ||
119 | |||
120 | #define WRITE_WORD(p, value) do { \ | ||
121 | - address_space_stl_notdirty(&address_space_memory, p, value, \ | ||
122 | + address_space_stl_notdirty(as, p, value, \ | ||
123 | MEMTXATTRS_UNSPECIFIED, NULL); \ | ||
124 | p += 4; \ | ||
125 | } while (0) | ||
126 | |||
127 | -static void set_kernel_args(const struct arm_boot_info *info) | ||
128 | +static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) | ||
129 | { | ||
130 | int initrd_size = info->initrd_size; | ||
131 | hwaddr base = info->loader_start; | ||
132 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
133 | int cmdline_size; | ||
134 | |||
135 | cmdline_size = strlen(info->kernel_cmdline); | ||
136 | - cpu_physical_memory_write(p + 8, info->kernel_cmdline, | ||
137 | - cmdline_size + 1); | ||
138 | + address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, | ||
139 | + (const uint8_t *)info->kernel_cmdline, | ||
140 | + cmdline_size + 1); | ||
141 | cmdline_size = (cmdline_size >> 2) + 1; | ||
142 | WRITE_WORD(p, cmdline_size + 2); | ||
143 | WRITE_WORD(p, 0x54410009); | ||
144 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
145 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; | ||
146 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | ||
147 | WRITE_WORD(p, 0x414f4d50); | ||
148 | - cpu_physical_memory_write(p, atag_board_buf, atag_board_len); | ||
149 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
150 | + atag_board_buf, atag_board_len); | ||
151 | p += atag_board_len; | ||
152 | } | ||
153 | /* ATAG_END */ | ||
154 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
155 | WRITE_WORD(p, 0); | ||
156 | } | ||
157 | |||
158 | -static void set_kernel_args_old(const struct arm_boot_info *info) | ||
159 | +static void set_kernel_args_old(const struct arm_boot_info *info, | ||
160 | + AddressSpace *as) | ||
161 | { | ||
162 | hwaddr p; | ||
163 | const char *s; | ||
164 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info) | ||
165 | } | ||
166 | s = info->kernel_cmdline; | ||
167 | if (s) { | ||
168 | - cpu_physical_memory_write(p, s, strlen(s) + 1); | ||
169 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
170 | + (const uint8_t *)s, strlen(s) + 1); | ||
171 | } else { | ||
172 | WRITE_WORD(p, 0); | ||
173 | } | ||
174 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
175 | * @addr: the address to load the image at | ||
176 | * @binfo: struct describing the boot environment | ||
177 | * @addr_limit: upper limit of the available memory area at @addr | ||
178 | + * @as: address space to load image to | ||
179 | * | ||
180 | * Load a device tree supplied by the machine or by the user with the | ||
181 | * '-dtb' command line option, and put it at offset @addr in target | ||
182 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
183 | * Note: Must not be called unless have_dtb(binfo) is true. | ||
184 | */ | ||
185 | static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
186 | - hwaddr addr_limit) | ||
187 | + hwaddr addr_limit, AddressSpace *as) | ||
188 | { | ||
189 | void *fdt = NULL; | ||
190 | int size, rc; | ||
191 | @@ -XXX,XX +XXX,XX @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
192 | /* Put the DTB into the memory map as a ROM image: this will ensure | ||
193 | * the DTB is copied again upon reset, even if addr points into RAM. | ||
194 | */ | ||
195 | - rom_add_blob_fixed("dtb", fdt, size, addr); | ||
196 | + rom_add_blob_fixed_as("dtb", fdt, size, addr, as); | ||
197 | |||
198 | g_free(fdt); | ||
199 | |||
200 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
201 | } | ||
202 | |||
203 | if (cs == first_cpu) { | ||
204 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
205 | + | ||
206 | cpu_set_pc(cs, info->loader_start); | ||
207 | |||
208 | if (!have_dtb(info)) { | ||
209 | if (old_param) { | ||
210 | - set_kernel_args_old(info); | ||
211 | + set_kernel_args_old(info, as); | ||
212 | } else { | ||
213 | - set_kernel_args(info); | ||
214 | + set_kernel_args(info, as); | ||
215 | } | ||
216 | } | ||
217 | } else { | ||
218 | @@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque) | ||
219 | |||
220 | static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
221 | uint64_t *lowaddr, uint64_t *highaddr, | ||
222 | - int elf_machine) | ||
223 | + int elf_machine, AddressSpace *as) | ||
224 | { | ||
225 | bool elf_is64; | ||
226 | union { | ||
227 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
228 | } | ||
229 | } | ||
230 | |||
231 | - ret = load_elf(info->kernel_filename, NULL, NULL, | ||
232 | - pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
233 | - 1, data_swab); | ||
234 | + ret = load_elf_as(info->kernel_filename, NULL, NULL, | ||
235 | + pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
236 | + 1, data_swab, as); | ||
237 | if (ret <= 0) { | ||
238 | /* The header loaded but the image didn't */ | ||
239 | exit(1); | ||
240 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
241 | } | ||
242 | |||
243 | static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
244 | - hwaddr *entry) | ||
245 | + hwaddr *entry, AddressSpace *as) | ||
246 | { | ||
247 | hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; | ||
248 | uint8_t *buffer; | ||
249 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
250 | } | ||
251 | |||
252 | *entry = mem_base + kernel_load_offset; | ||
253 | - rom_add_blob_fixed(filename, buffer, size, *entry); | ||
254 | + rom_add_blob_fixed_as(filename, buffer, size, *entry, as); | ||
255 | |||
256 | g_free(buffer); | ||
257 | |||
258 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
259 | ARMCPU *cpu = n->cpu; | ||
260 | struct arm_boot_info *info = | ||
261 | container_of(n, struct arm_boot_info, load_kernel_notifier); | ||
262 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
263 | |||
264 | /* The board code is not supposed to set secure_board_setup unless | ||
265 | * running its code in secure mode is actually possible, and KVM | ||
266 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
267 | * the kernel is supposed to be loaded by the bootloader), copy the | ||
268 | * DTB to the base of RAM for the bootloader to pick up. | ||
269 | */ | ||
270 | - if (load_dtb(info->loader_start, info, 0) < 0) { | ||
271 | + if (load_dtb(info->loader_start, info, 0, as) < 0) { | ||
272 | exit(1); | ||
273 | } | ||
274 | } | ||
275 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
276 | |||
277 | /* Assume that raw images are linux kernels, and ELF images are not. */ | ||
278 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | ||
279 | - &elf_high_addr, elf_machine); | ||
280 | + &elf_high_addr, elf_machine, as); | ||
281 | if (kernel_size > 0 && have_dtb(info)) { | ||
282 | /* If there is still some room left at the base of RAM, try and put | ||
283 | * the DTB there like we do for images loaded with -bios or -pflash. | ||
284 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
285 | if (elf_low_addr < info->loader_start) { | ||
286 | elf_low_addr = 0; | ||
287 | } | ||
288 | - if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { | ||
289 | + if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) { | ||
290 | exit(1); | ||
291 | } | ||
292 | } | ||
293 | } | ||
294 | entry = elf_entry; | ||
295 | if (kernel_size < 0) { | ||
296 | - kernel_size = load_uimage(info->kernel_filename, &entry, NULL, | ||
297 | - &is_linux, NULL, NULL); | ||
298 | + kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, | ||
299 | + &is_linux, NULL, NULL, as); | ||
300 | } | ||
301 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { | ||
302 | kernel_size = load_aarch64_image(info->kernel_filename, | ||
303 | - info->loader_start, &entry); | ||
304 | + info->loader_start, &entry, as); | ||
305 | is_linux = 1; | ||
306 | } else if (kernel_size < 0) { | ||
307 | /* 32-bit ARM */ | ||
308 | entry = info->loader_start + KERNEL_LOAD_ADDR; | ||
309 | - kernel_size = load_image_targphys(info->kernel_filename, entry, | ||
310 | - info->ram_size - KERNEL_LOAD_ADDR); | ||
311 | + kernel_size = load_image_targphys_as(info->kernel_filename, entry, | ||
312 | + info->ram_size - KERNEL_LOAD_ADDR, | ||
313 | + as); | ||
314 | is_linux = 1; | ||
315 | } | ||
316 | if (kernel_size < 0) { | ||
317 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
318 | uint32_t fixupcontext[FIXUP_MAX]; | ||
319 | |||
320 | if (info->initrd_filename) { | ||
321 | - initrd_size = load_ramdisk(info->initrd_filename, | ||
322 | - info->initrd_start, | ||
323 | - info->ram_size - | ||
324 | - info->initrd_start); | ||
325 | + initrd_size = load_ramdisk_as(info->initrd_filename, | ||
326 | + info->initrd_start, | ||
327 | + info->ram_size - info->initrd_start, | ||
328 | + as); | ||
329 | if (initrd_size < 0) { | ||
330 | - initrd_size = load_image_targphys(info->initrd_filename, | ||
331 | - info->initrd_start, | ||
332 | - info->ram_size - | ||
333 | - info->initrd_start); | ||
334 | + initrd_size = load_image_targphys_as(info->initrd_filename, | ||
335 | + info->initrd_start, | ||
336 | + info->ram_size - | ||
337 | + info->initrd_start, | ||
338 | + as); | ||
339 | } | ||
340 | if (initrd_size < 0) { | ||
341 | error_report("could not load initrd '%s'", | ||
342 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
343 | |||
344 | /* Place the DTB after the initrd in memory with alignment. */ | ||
345 | dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); | ||
346 | - if (load_dtb(dtb_start, info, 0) < 0) { | ||
347 | + if (load_dtb(dtb_start, info, 0, as) < 0) { | ||
348 | exit(1); | ||
349 | } | ||
350 | fixupcontext[FIXUP_ARGPTR] = dtb_start; | ||
351 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
352 | fixupcontext[FIXUP_ENTRYPOINT] = entry; | ||
353 | |||
354 | write_bootloader("bootloader", info->loader_start, | ||
355 | - primary_loader, fixupcontext); | ||
356 | + primary_loader, fixupcontext, as); | ||
357 | |||
358 | if (info->nb_cpus > 1) { | ||
359 | info->write_secondary_boot(cpu, info); | ||
360 | -- | ||
361 | 2.16.2 | ||
362 | |||
363 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Instead of loading guest images to the system address space, use the | ||
2 | CPU's address space. This is important if we're trying to load the | ||
3 | file to memory or via an alias memory region that is provided by an | ||
4 | SoC object and thus not mapped into the system address space. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/arm/armv7m.c | 17 ++++++++++++++--- | ||
12 | 1 file changed, 14 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/armv7m.c | ||
17 | +++ b/hw/arm/armv7m.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
19 | uint64_t entry; | ||
20 | uint64_t lowaddr; | ||
21 | int big_endian; | ||
22 | + AddressSpace *as; | ||
23 | + int asidx; | ||
24 | + CPUState *cs = CPU(cpu); | ||
25 | |||
26 | #ifdef TARGET_WORDS_BIGENDIAN | ||
27 | big_endian = 1; | ||
28 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
29 | exit(1); | ||
30 | } | ||
31 | |||
32 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | ||
33 | + asidx = ARMASIdx_S; | ||
34 | + } else { | ||
35 | + asidx = ARMASIdx_NS; | ||
36 | + } | ||
37 | + as = cpu_get_address_space(cs, asidx); | ||
38 | + | ||
39 | if (kernel_filename) { | ||
40 | - image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
41 | - NULL, big_endian, EM_ARM, 1, 0); | ||
42 | + image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
43 | + NULL, big_endian, EM_ARM, 1, 0, as); | ||
44 | if (image_size < 0) { | ||
45 | - image_size = load_image_targphys(kernel_filename, 0, mem_size); | ||
46 | + image_size = load_image_targphys_as(kernel_filename, 0, | ||
47 | + mem_size, as); | ||
48 | lowaddr = 0; | ||
49 | } | ||
50 | if (image_size < 0) { | ||
51 | -- | ||
52 | 2.16.2 | ||
53 | |||
54 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Maxim Uvarov <maxim.uvarov@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | qemu has 2 type of functions: shutdown and reboot. Shutdown |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | function has to be used for machine shutdown. Otherwise we cause |
5 | Message-id: 20180228193125.20577-12-richard.henderson@linaro.org | 5 | a reset with a bogus "cause" value, when we intended a shutdown. |
6 | |||
7 | Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org | ||
10 | [PMM: tweaked commit message] | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/helper.h | 7 ++++ | 13 | hw/gpio/gpio_pwr.c | 2 +- |
9 | target/arm/translate-a64.c | 48 ++++++++++++++++++++++- | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ | ||
11 | 3 files changed, 151 insertions(+), 1 deletion(-) | ||
12 | 15 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 16 | diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 18 | --- a/hw/gpio/gpio_pwr.c |
16 | +++ b/target/arm/helper.h | 19 | +++ b/hw/gpio/gpio_pwr.c |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 20 | @@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level) |
18 | DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 21 | static void gpio_pwr_shutdown(void *opaque, int n, int level) |
19 | void, ptr, ptr, ptr, ptr, i32) | 22 | { |
20 | 23 | if (level) { | |
21 | +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, | 24 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
22 | + void, ptr, ptr, ptr, ptr, i32) | 25 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
23 | +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | 26 | } |
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | + | ||
28 | #ifdef TARGET_AARCH64 | ||
29 | #include "helper-a64.h" | ||
30 | #endif | ||
31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate-a64.c | ||
34 | +++ b/target/arm/translate-a64.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
36 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
37 | } | 27 | } |
38 | 28 | ||
39 | +/* Expand a 3-operand + fpstatus pointer + simd data value operation using | ||
40 | + * an out-of-line helper. | ||
41 | + */ | ||
42 | +static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | ||
43 | + int rm, bool is_fp16, int data, | ||
44 | + gen_helper_gvec_3_ptr *fn) | ||
45 | +{ | ||
46 | + TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | ||
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), fpst, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | ||
51 | + tcg_temp_free_ptr(fpst); | ||
52 | +} | ||
53 | + | ||
54 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | ||
55 | * than the 32 bit equivalent. | ||
56 | */ | ||
57 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
58 | int size = extract32(insn, 22, 2); | ||
59 | bool u = extract32(insn, 29, 1); | ||
60 | bool is_q = extract32(insn, 30, 1); | ||
61 | - int feature; | ||
62 | + int feature, rot; | ||
63 | |||
64 | switch (u * 16 + opcode) { | ||
65 | case 0x10: /* SQRDMLAH (vector) */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | } | ||
68 | feature = ARM_FEATURE_V8_RDM; | ||
69 | break; | ||
70 | + case 0xc: /* FCADD, #90 */ | ||
71 | + case 0xe: /* FCADD, #270 */ | ||
72 | + if (size == 0 | ||
73 | + || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) | ||
74 | + || (size == 3 && !is_q)) { | ||
75 | + unallocated_encoding(s); | ||
76 | + return; | ||
77 | + } | ||
78 | + feature = ARM_FEATURE_V8_FCMA; | ||
79 | + break; | ||
80 | default: | ||
81 | unallocated_encoding(s); | ||
82 | return; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
84 | } | ||
85 | return; | ||
86 | |||
87 | + case 0xc: /* FCADD, #90 */ | ||
88 | + case 0xe: /* FCADD, #270 */ | ||
89 | + rot = extract32(opcode, 1, 1); | ||
90 | + switch (size) { | ||
91 | + case 1: | ||
92 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
93 | + gen_helper_gvec_fcaddh); | ||
94 | + break; | ||
95 | + case 2: | ||
96 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
97 | + gen_helper_gvec_fcadds); | ||
98 | + break; | ||
99 | + case 3: | ||
100 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
101 | + gen_helper_gvec_fcaddd); | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | + } | ||
106 | + return; | ||
107 | + | ||
108 | default: | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/vec_helper.c | ||
114 | +++ b/target/arm/vec_helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | #include "exec/exec-all.h" | ||
117 | #include "exec/helper-proto.h" | ||
118 | #include "tcg/tcg-gvec-desc.h" | ||
119 | +#include "fpu/softfloat.h" | ||
120 | |||
121 | |||
122 | +/* Note that vector data is stored in host-endian 64-bit chunks, | ||
123 | + so addressing units smaller than that needs a host-endian fixup. */ | ||
124 | +#ifdef HOST_WORDS_BIGENDIAN | ||
125 | +#define H1(x) ((x) ^ 7) | ||
126 | +#define H2(x) ((x) ^ 3) | ||
127 | +#define H4(x) ((x) ^ 1) | ||
128 | +#else | ||
129 | +#define H1(x) (x) | ||
130 | +#define H2(x) (x) | ||
131 | +#define H4(x) (x) | ||
132 | +#endif | ||
133 | + | ||
134 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
135 | |||
136 | static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
137 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
138 | } | ||
139 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
140 | } | ||
141 | + | ||
142 | +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, | ||
143 | + void *vfpst, uint32_t desc) | ||
144 | +{ | ||
145 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
146 | + float16 *d = vd; | ||
147 | + float16 *n = vn; | ||
148 | + float16 *m = vm; | ||
149 | + float_status *fpst = vfpst; | ||
150 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
151 | + uint32_t neg_imag = neg_real ^ 1; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
155 | + neg_real <<= 15; | ||
156 | + neg_imag <<= 15; | ||
157 | + | ||
158 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
159 | + float16 e0 = n[H2(i)]; | ||
160 | + float16 e1 = m[H2(i + 1)] ^ neg_imag; | ||
161 | + float16 e2 = n[H2(i + 1)]; | ||
162 | + float16 e3 = m[H2(i)] ^ neg_real; | ||
163 | + | ||
164 | + d[H2(i)] = float16_add(e0, e1, fpst); | ||
165 | + d[H2(i + 1)] = float16_add(e2, e3, fpst); | ||
166 | + } | ||
167 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
168 | +} | ||
169 | + | ||
170 | +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, | ||
171 | + void *vfpst, uint32_t desc) | ||
172 | +{ | ||
173 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
174 | + float32 *d = vd; | ||
175 | + float32 *n = vn; | ||
176 | + float32 *m = vm; | ||
177 | + float_status *fpst = vfpst; | ||
178 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
179 | + uint32_t neg_imag = neg_real ^ 1; | ||
180 | + uintptr_t i; | ||
181 | + | ||
182 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
183 | + neg_real <<= 31; | ||
184 | + neg_imag <<= 31; | ||
185 | + | ||
186 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
187 | + float32 e0 = n[H4(i)]; | ||
188 | + float32 e1 = m[H4(i + 1)] ^ neg_imag; | ||
189 | + float32 e2 = n[H4(i + 1)]; | ||
190 | + float32 e3 = m[H4(i)] ^ neg_real; | ||
191 | + | ||
192 | + d[H4(i)] = float32_add(e0, e1, fpst); | ||
193 | + d[H4(i + 1)] = float32_add(e2, e3, fpst); | ||
194 | + } | ||
195 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
196 | +} | ||
197 | + | ||
198 | +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
199 | + void *vfpst, uint32_t desc) | ||
200 | +{ | ||
201 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
202 | + float64 *d = vd; | ||
203 | + float64 *n = vn; | ||
204 | + float64 *m = vm; | ||
205 | + float_status *fpst = vfpst; | ||
206 | + uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); | ||
207 | + uint64_t neg_imag = neg_real ^ 1; | ||
208 | + uintptr_t i; | ||
209 | + | ||
210 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
211 | + neg_real <<= 63; | ||
212 | + neg_imag <<= 63; | ||
213 | + | ||
214 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
215 | + float64 e0 = n[i]; | ||
216 | + float64 e1 = m[i + 1] ^ neg_imag; | ||
217 | + float64 e2 = n[i + 1]; | ||
218 | + float64 e3 = m[i] ^ neg_real; | ||
219 | + | ||
220 | + d[i] = float64_add(e0, e1, fpst); | ||
221 | + d[i + 1] = float64_add(e2, e3, fpst); | ||
222 | + } | ||
223 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
224 | +} | ||
225 | -- | 29 | -- |
226 | 2.16.2 | 30 | 2.20.1 |
227 | 31 | ||
228 | 32 | diff view generated by jsdifflib |
1 | The Cortex-M33 allows the system to specify the reset value of the | 1 | In do_ldst(), the calculation of the offset needs to be based on the |
---|---|---|---|
2 | secure Vector Table Offset Register (VTOR) by asserting config | 2 | size of the memory access, not the size of the elements in the |
3 | signals. In particular, guest images for the MPS2 AN505 board rely | 3 | vector. This meant we were getting it wrong for the widening and |
4 | on the MPS2's initial VTOR being correct for that board. | 4 | narrowing variants of the various VLDR and VSTR insns. |
5 | Implement a QEMU property so board and SoC code can set the reset | ||
6 | value to the correct value. | ||
7 | 5 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-7-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-2-peter.maydell@linaro.org |
11 | --- | 9 | --- |
12 | target/arm/cpu.h | 3 +++ | 10 | target/arm/translate-mve.c | 17 +++++++++-------- |
13 | target/arm/cpu.c | 18 ++++++++++++++---- | 11 | 1 file changed, 9 insertions(+), 8 deletions(-) |
14 | 2 files changed, 17 insertions(+), 4 deletions(-) | ||
15 | 12 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/translate-mve.c |
19 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/translate-mve.c |
20 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 17 | @@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s) |
21 | */ | 18 | } |
22 | uint32_t psci_conduit; | 19 | } |
23 | 20 | ||
24 | + /* For v8M, initial value of the Secure VTOR */ | 21 | -static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
25 | + uint32_t init_svtor; | 22 | +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, |
26 | + | 23 | + unsigned msize) |
27 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or | ||
28 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | ||
29 | */ | ||
30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/cpu.c | ||
33 | +++ b/target/arm/cpu.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
35 | uint32_t initial_msp; /* Loaded from 0x0 */ | ||
36 | uint32_t initial_pc; /* Loaded from 0x4 */ | ||
37 | uint8_t *rom; | ||
38 | + uint32_t vecbase; | ||
39 | |||
40 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
41 | env->v7m.secure = true; | ||
42 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
43 | /* Unlike A/R profile, M profile defines the reset LR value */ | ||
44 | env->regs[14] = 0xffffffff; | ||
45 | |||
46 | - /* Load the initial SP and PC from the vector table at address 0 */ | ||
47 | - rom = rom_ptr(0); | ||
48 | + env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; | ||
49 | + | ||
50 | + /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | ||
51 | + vecbase = env->v7m.vecbase[env->v7m.secure]; | ||
52 | + rom = rom_ptr(vecbase); | ||
53 | if (rom) { | ||
54 | /* Address zero is covered by ROM which hasn't yet been | ||
55 | * copied into physical memory. | ||
56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
57 | * it got copied into memory. In the latter case, rom_ptr | ||
58 | * will return a NULL pointer and we should use ldl_phys instead. | ||
59 | */ | ||
60 | - initial_msp = ldl_phys(s->as, 0); | ||
61 | - initial_pc = ldl_phys(s->as, 4); | ||
62 | + initial_msp = ldl_phys(s->as, vecbase); | ||
63 | + initial_pc = ldl_phys(s->as, vecbase + 4); | ||
64 | } | ||
65 | |||
66 | env->regs[13] = initial_msp & 0xFFFFFFFC; | ||
67 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property = | ||
68 | pmsav7_dregion, | ||
69 | qdev_prop_uint32, uint32_t); | ||
70 | |||
71 | +/* M profile: initial value of the Secure VTOR */ | ||
72 | +static Property arm_cpu_initsvtor_property = | ||
73 | + DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | ||
74 | + | ||
75 | static void arm_cpu_post_init(Object *obj) | ||
76 | { | 24 | { |
77 | ARMCPU *cpu = ARM_CPU(obj); | 25 | TCGv_i32 addr; |
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | 26 | uint32_t offset; |
79 | qdev_prop_allow_set_link_before_realize, | 27 | @@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
80 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | 28 | return true; |
81 | &error_abort); | ||
82 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, | ||
83 | + &error_abort); | ||
84 | } | 29 | } |
85 | 30 | ||
86 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | 31 | - offset = a->imm << a->size; |
32 | + offset = a->imm << msize; | ||
33 | if (!a->a) { | ||
34 | offset = -offset; | ||
35 | } | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) | ||
37 | { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, | ||
38 | { NULL, NULL } | ||
39 | }; | ||
40 | - return do_ldst(s, a, ldstfns[a->size][a->l]); | ||
41 | + return do_ldst(s, a, ldstfns[a->size][a->l], a->size); | ||
42 | } | ||
43 | |||
44 | -#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ | ||
45 | +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ | ||
46 | static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ | ||
47 | { \ | ||
48 | static MVEGenLdStFn * const ldstfns[2][2] = { \ | ||
49 | { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ | ||
50 | { NULL, gen_helper_mve_##ULD }, \ | ||
51 | }; \ | ||
52 | - return do_ldst(s, a, ldstfns[a->u][a->l]); \ | ||
53 | + return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ | ||
54 | } | ||
55 | |||
56 | -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) | ||
57 | -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) | ||
58 | -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) | ||
59 | +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) | ||
60 | +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) | ||
61 | +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) | ||
62 | |||
63 | static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
64 | { | ||
87 | -- | 65 | -- |
88 | 2.16.2 | 66 | 2.20.1 |
89 | 67 | ||
90 | 68 | diff view generated by jsdifflib |
1 | In v8M, the Implementation Defined Attribution Unit (IDAU) is | 1 | The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH |
---|---|---|---|
2 | a small piece of hardware typically implemented in the SoC | 2 | insns had some bugs: |
3 | which provides board or SoC specific security attribution | 3 | * the 32x32 multiply of elements was being done as 32x32->32, |
4 | information for each address that the CPU performs MPU/SAU | 4 | not 32x32->64 |
5 | checks on. For QEMU, we model this with a QOM interface which | 5 | * we were incorrectly maintaining the accumulator in its full |
6 | is implemented by the board or SoC object and connected to | 6 | 72-bit form across all 4 beats of the insn; in the pseudocode |
7 | the CPU using a link property. | 7 | it is squashed back into the 64 bits of the RdaHi:RdaLo |
8 | registers after each beat | ||
8 | 9 | ||
9 | This commit defines the new interface class, adds the link | 10 | In particular, fixing the second of these allows us to recast |
10 | property to the CPU object, and makes the SAU checking | 11 | the implementation to avoid 128-bit arithmetic entirely. |
11 | code call the IDAU interface if one is present. | ||
12 | 12 | ||
13 | Since the element size here is always 4, we can also drop the | ||
14 | parameterization of ESIZE to make the code a little more readable. | ||
15 | |||
16 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20180220180325.29818-5-peter.maydell@linaro.org | 19 | Message-id: 20210628135835.6690-3-peter.maydell@linaro.org |
16 | --- | 20 | --- |
17 | target/arm/cpu.h | 3 +++ | 21 | target/arm/mve_helper.c | 38 +++++++++++++++++++++----------------- |
18 | target/arm/idau.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++ | 22 | 1 file changed, 21 insertions(+), 17 deletions(-) |
19 | target/arm/cpu.c | 15 +++++++++++++ | ||
20 | target/arm/helper.c | 28 +++++++++++++++++++++--- | ||
21 | 4 files changed, 104 insertions(+), 3 deletions(-) | ||
22 | create mode 100644 target/arm/idau.h | ||
23 | 23 | ||
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
25 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpu.h | 26 | --- a/target/arm/mve_helper.c |
27 | +++ b/target/arm/cpu.h | 27 | +++ b/target/arm/mve_helper.c |
28 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
29 | /* MemoryRegion to use for secure physical accesses */ | ||
30 | MemoryRegion *secure_memory; | ||
31 | |||
32 | + /* For v8M, pointer to the IDAU interface provided by board/SoC */ | ||
33 | + Object *idau; | ||
34 | + | ||
35 | /* 'compatible' string for this CPU for Linux device trees */ | ||
36 | const char *dtb_compatible; | ||
37 | |||
38 | diff --git a/target/arm/idau.h b/target/arm/idau.h | ||
39 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | ||
41 | --- /dev/null | ||
42 | +++ b/target/arm/idau.h | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +/* | ||
45 | + * QEMU ARM CPU -- interface for the Arm v8M IDAU | ||
46 | + * | ||
47 | + * Copyright (c) 2018 Linaro Ltd | ||
48 | + * | ||
49 | + * This program is free software; you can redistribute it and/or | ||
50 | + * modify it under the terms of the GNU General Public License | ||
51 | + * as published by the Free Software Foundation; either version 2 | ||
52 | + * of the License, or (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program; if not, see | ||
61 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
62 | + * | ||
63 | + * In the v8M architecture, the IDAU is a small piece of hardware | ||
64 | + * typically implemented in the SoC which provides board or SoC | ||
65 | + * specific security attribution information for each address that | ||
66 | + * the CPU performs MPU/SAU checks on. For QEMU, we model this with a | ||
67 | + * QOM interface which is implemented by the board or SoC object and | ||
68 | + * connected to the CPU using a link property. | ||
69 | + */ | ||
70 | + | ||
71 | +#ifndef TARGET_ARM_IDAU_H | ||
72 | +#define TARGET_ARM_IDAU_H | ||
73 | + | ||
74 | +#include "qom/object.h" | ||
75 | + | ||
76 | +#define TYPE_IDAU_INTERFACE "idau-interface" | ||
77 | +#define IDAU_INTERFACE(obj) \ | ||
78 | + INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE) | ||
79 | +#define IDAU_INTERFACE_CLASS(class) \ | ||
80 | + OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE) | ||
81 | +#define IDAU_INTERFACE_GET_CLASS(obj) \ | ||
82 | + OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE) | ||
83 | + | ||
84 | +typedef struct IDAUInterface { | ||
85 | + Object parent; | ||
86 | +} IDAUInterface; | ||
87 | + | ||
88 | +#define IREGION_NOTVALID -1 | ||
89 | + | ||
90 | +typedef struct IDAUInterfaceClass { | ||
91 | + InterfaceClass parent; | ||
92 | + | ||
93 | + /* Check the specified address and return the IDAU security information | ||
94 | + * for it by filling in iregion, exempt, ns and nsc: | ||
95 | + * iregion: IDAU region number, or IREGION_NOTVALID if not valid | ||
96 | + * exempt: true if address is exempt from security attribution | ||
97 | + * ns: true if the address is NonSecure | ||
98 | + * nsc: true if the address is NonSecure-callable | ||
99 | + */ | ||
100 | + void (*check)(IDAUInterface *ii, uint32_t address, int *iregion, | ||
101 | + bool *exempt, bool *ns, bool *nsc); | ||
102 | +} IDAUInterfaceClass; | ||
103 | + | ||
104 | +#endif | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/cpu.c | ||
108 | +++ b/target/arm/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ |
110 | */ | 29 | */ |
111 | 30 | ||
112 | #include "qemu/osdep.h" | 31 | #include "qemu/osdep.h" |
113 | +#include "target/arm/idau.h" | 32 | -#include "qemu/int128.h" |
114 | #include "qemu/error-report.h" | ||
115 | #include "qapi/error.h" | ||
116 | #include "cpu.h" | ||
117 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | ||
118 | } | ||
119 | } | ||
120 | |||
121 | + if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { | ||
122 | + object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | ||
123 | + qdev_prop_allow_set_link_before_realize, | ||
124 | + OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
125 | + &error_abort); | ||
126 | + } | ||
127 | + | ||
128 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
129 | &error_abort); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { | ||
132 | .class_init = arm_cpu_class_init, | ||
133 | }; | ||
134 | |||
135 | +static const TypeInfo idau_interface_type_info = { | ||
136 | + .name = TYPE_IDAU_INTERFACE, | ||
137 | + .parent = TYPE_INTERFACE, | ||
138 | + .class_size = sizeof(IDAUInterfaceClass), | ||
139 | +}; | ||
140 | + | ||
141 | static void arm_cpu_register_types(void) | ||
142 | { | ||
143 | const ARMCPUInfo *info = arm_cpus; | ||
144 | |||
145 | type_register_static(&arm_cpu_type_info); | ||
146 | + type_register_static(&idau_interface_type_info); | ||
147 | |||
148 | while (info->name) { | ||
149 | cpu_register(info); | ||
150 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/helper.c | ||
153 | +++ b/target/arm/helper.c | ||
154 | @@ -XXX,XX +XXX,XX @@ | ||
155 | #include "qemu/osdep.h" | ||
156 | +#include "target/arm/idau.h" | ||
157 | #include "trace.h" | ||
158 | #include "cpu.h" | 33 | #include "cpu.h" |
159 | #include "internals.h" | 34 | #include "internals.h" |
160 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 35 | #include "vec_internal.h" |
161 | */ | 36 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) |
162 | ARMCPU *cpu = arm_env_get_cpu(env); | 37 | DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) |
163 | int r; | 38 | |
164 | + bool idau_exempt = false, idau_ns = true, idau_nsc = true; | 39 | /* |
165 | + int idau_region = IREGION_NOTVALID; | 40 | - * Rounding multiply add long dual accumulate high: we must keep |
166 | 41 | - * a 72-bit internal accumulator value and return the top 64 bits. | |
167 | - /* TODO: implement IDAU */ | 42 | + * Rounding multiply add long dual accumulate high. In the pseudocode |
168 | + if (cpu->idau) { | 43 | + * this is implemented with a 72-bit internal accumulator value of which |
169 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | 44 | + * the top 64 bits are returned. We optimize this to avoid having to |
170 | + IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | 45 | + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator |
171 | + | 46 | + * is squashed back into 64-bits after each beat. |
172 | + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | 47 | */ |
173 | + &idau_nsc); | 48 | -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \ |
174 | + } | 49 | +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ |
175 | 50 | uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ | |
176 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | 51 | void *vm, uint64_t a) \ |
177 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | 52 | { \ |
178 | return; | 53 | uint16_t mask = mve_element_mask(env); \ |
54 | unsigned e; \ | ||
55 | TYPE *n = vn, *m = vm; \ | ||
56 | - Int128 acc = int128_lshift(TO128(a), 8); \ | ||
57 | - for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
58 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
59 | if (mask & 1) { \ | ||
60 | + LTYPE mul; \ | ||
61 | if (e & 1) { \ | ||
62 | - acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \ | ||
63 | - m[H##ESIZE(e)])); \ | ||
64 | + mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ | ||
65 | + if (SUB) { \ | ||
66 | + mul = -mul; \ | ||
67 | + } \ | ||
68 | } else { \ | ||
69 | - acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
70 | - m[H##ESIZE(e)])); \ | ||
71 | + mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ | ||
72 | } \ | ||
73 | - acc = int128_add(acc, int128_make64(1 << 7)); \ | ||
74 | + mul = (mul >> 8) + ((mul >> 7) & 1); \ | ||
75 | + a += mul; \ | ||
76 | } \ | ||
77 | } \ | ||
78 | mve_advance_vpt(env); \ | ||
79 | - return int128_getlo(int128_rshift(acc, 8)); \ | ||
80 | + return a; \ | ||
179 | } | 81 | } |
180 | 82 | ||
181 | - if (v8m_is_sau_exempt(env, address, access_type)) { | 83 | -DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64) |
182 | + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { | 84 | -DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64) |
183 | sattrs->ns = !regime_is_secure(env, mmu_idx); | 85 | +DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) |
184 | return; | 86 | +DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) |
185 | } | 87 | |
186 | 88 | -DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64) | |
187 | + if (idau_region != IREGION_NOTVALID) { | 89 | +DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) |
188 | + sattrs->irvalid = true; | 90 | |
189 | + sattrs->iregion = idau_region; | 91 | -DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) |
190 | + } | 92 | -DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) |
191 | + | 93 | +DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) |
192 | switch (env->sau.ctrl & 3) { | 94 | +DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) |
193 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | 95 | |
194 | break; | 96 | /* Vector add across vector */ |
195 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 97 | #define DO_VADDV(OP, ESIZE, TYPE) \ |
196 | } | ||
197 | } | ||
198 | |||
199 | - /* TODO when we support the IDAU then it may override the result here */ | ||
200 | + /* The IDAU will override the SAU lookup results if it specifies | ||
201 | + * higher security than the SAU does. | ||
202 | + */ | ||
203 | + if (!idau_ns) { | ||
204 | + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | ||
205 | + sattrs->ns = false; | ||
206 | + sattrs->nsc = idau_nsc; | ||
207 | + } | ||
208 | + } | ||
209 | break; | ||
210 | } | ||
211 | } | ||
212 | -- | 98 | -- |
213 | 2.16.2 | 99 | 2.20.1 |
214 | 100 | ||
215 | 101 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The function asimd_imm_const() in translate-neon.c is an |
---|---|---|---|
2 | implementation of the pseudocode AdvSIMDExpandImm(), which we will | ||
3 | also want for MVE. Move the implementation to translate.c, with a | ||
4 | prototype in translate.h. | ||
2 | 5 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20180228193125.20577-15-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-4-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/translate.h | 16 ++++++++++ |
9 | 1 file changed, 61 insertions(+) | 11 | target/arm/translate-neon.c | 63 ------------------------------------- |
12 | target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 73 insertions(+), 63 deletions(-) | ||
10 | 14 | ||
15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate.h | ||
18 | +++ b/target/arm/translate.h | ||
19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) | ||
20 | return opc | s->be_data; | ||
21 | } | ||
22 | |||
23 | +/** | ||
24 | + * asimd_imm_const: Expand an encoded SIMD constant value | ||
25 | + * | ||
26 | + * Expand a SIMD constant value. This is essentially the pseudocode | ||
27 | + * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for | ||
28 | + * VMVN and VBIC (when cmode < 14 && op == 1). | ||
29 | + * | ||
30 | + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | ||
31 | + * callers must catch this. | ||
32 | + * | ||
33 | + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
34 | + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
35 | + * we produce an immediate constant value of 0 in these cases. | ||
36 | + */ | ||
37 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); | ||
38 | + | ||
39 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
40 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/translate-neon.c | ||
43 | +++ b/target/arm/translate-neon.c | ||
44 | @@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh) | ||
45 | DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs) | ||
46 | DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu) | ||
47 | |||
48 | -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
49 | -{ | ||
50 | - /* | ||
51 | - * Expand the encoded constant. | ||
52 | - * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
53 | - * We choose to not special-case this and will behave as if a | ||
54 | - * valid constant encoding of 0 had been given. | ||
55 | - * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. | ||
56 | - */ | ||
57 | - switch (cmode) { | ||
58 | - case 0: case 1: | ||
59 | - /* no-op */ | ||
60 | - break; | ||
61 | - case 2: case 3: | ||
62 | - imm <<= 8; | ||
63 | - break; | ||
64 | - case 4: case 5: | ||
65 | - imm <<= 16; | ||
66 | - break; | ||
67 | - case 6: case 7: | ||
68 | - imm <<= 24; | ||
69 | - break; | ||
70 | - case 8: case 9: | ||
71 | - imm |= imm << 16; | ||
72 | - break; | ||
73 | - case 10: case 11: | ||
74 | - imm = (imm << 8) | (imm << 24); | ||
75 | - break; | ||
76 | - case 12: | ||
77 | - imm = (imm << 8) | 0xff; | ||
78 | - break; | ||
79 | - case 13: | ||
80 | - imm = (imm << 16) | 0xffff; | ||
81 | - break; | ||
82 | - case 14: | ||
83 | - if (op) { | ||
84 | - /* | ||
85 | - * This is the only case where the top and bottom 32 bits | ||
86 | - * of the encoded constant differ. | ||
87 | - */ | ||
88 | - uint64_t imm64 = 0; | ||
89 | - int n; | ||
90 | - | ||
91 | - for (n = 0; n < 8; n++) { | ||
92 | - if (imm & (1 << n)) { | ||
93 | - imm64 |= (0xffULL << (n * 8)); | ||
94 | - } | ||
95 | - } | ||
96 | - return imm64; | ||
97 | - } | ||
98 | - imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
99 | - break; | ||
100 | - case 15: | ||
101 | - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
102 | - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
103 | - break; | ||
104 | - } | ||
105 | - if (op) { | ||
106 | - imm = ~imm; | ||
107 | - } | ||
108 | - return dup_const(MO_32, imm); | ||
109 | -} | ||
110 | - | ||
111 | static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
112 | GVecGen2iFn *fn) | ||
113 | { | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 114 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
12 | index XXXXXXX..XXXXXXX 100644 | 115 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 116 | --- a/target/arm/translate.c |
14 | +++ b/target/arm/translate.c | 117 | +++ b/target/arm/translate.c |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 118 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) |
16 | return 0; | 119 | a64_translate_init(); |
17 | } | 120 | } |
18 | 121 | ||
19 | +/* Advanced SIMD two registers and a scalar extension. | 122 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
20 | + * 31 24 23 22 20 16 12 11 10 9 8 3 0 | 123 | +{ |
21 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | 124 | + /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */ |
22 | + * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | 125 | + switch (cmode) { |
23 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | 126 | + case 0: case 1: |
24 | + * | 127 | + /* no-op */ |
25 | + */ | 128 | + break; |
129 | + case 2: case 3: | ||
130 | + imm <<= 8; | ||
131 | + break; | ||
132 | + case 4: case 5: | ||
133 | + imm <<= 16; | ||
134 | + break; | ||
135 | + case 6: case 7: | ||
136 | + imm <<= 24; | ||
137 | + break; | ||
138 | + case 8: case 9: | ||
139 | + imm |= imm << 16; | ||
140 | + break; | ||
141 | + case 10: case 11: | ||
142 | + imm = (imm << 8) | (imm << 24); | ||
143 | + break; | ||
144 | + case 12: | ||
145 | + imm = (imm << 8) | 0xff; | ||
146 | + break; | ||
147 | + case 13: | ||
148 | + imm = (imm << 16) | 0xffff; | ||
149 | + break; | ||
150 | + case 14: | ||
151 | + if (op) { | ||
152 | + /* | ||
153 | + * This is the only case where the top and bottom 32 bits | ||
154 | + * of the encoded constant differ. | ||
155 | + */ | ||
156 | + uint64_t imm64 = 0; | ||
157 | + int n; | ||
26 | + | 158 | + |
27 | +static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | 159 | + for (n = 0; n < 8; n++) { |
28 | +{ | 160 | + if (imm & (1 << n)) { |
29 | + int rd, rn, rm, rot, size, opr_sz; | 161 | + imm64 |= (0xffULL << (n * 8)); |
30 | + TCGv_ptr fpst; | 162 | + } |
31 | + bool q; | 163 | + } |
32 | + | 164 | + return imm64; |
33 | + q = extract32(insn, 6, 1); | 165 | + } |
34 | + VFP_DREG_D(rd, insn); | 166 | + imm |= (imm << 8) | (imm << 16) | (imm << 24); |
35 | + VFP_DREG_N(rn, insn); | 167 | + break; |
36 | + VFP_DREG_M(rm, insn); | 168 | + case 15: |
37 | + if ((rd | rn) & q) { | 169 | + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
38 | + return 1; | 170 | + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
171 | + break; | ||
39 | + } | 172 | + } |
40 | + | 173 | + if (op) { |
41 | + if ((insn & 0xff000f10) == 0xfe000800) { | 174 | + imm = ~imm; |
42 | + /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ | ||
43 | + rot = extract32(insn, 20, 2); | ||
44 | + size = extract32(insn, 23, 1); | ||
45 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
46 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
47 | + return 1; | ||
48 | + } | ||
49 | + } else { | ||
50 | + return 1; | ||
51 | + } | 175 | + } |
52 | + | 176 | + return dup_const(MO_32, imm); |
53 | + if (s->fp_excp_el) { | ||
54 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
55 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
56 | + return 0; | ||
57 | + } | ||
58 | + if (!s->vfp_enabled) { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + opr_sz = (1 + q) * 8; | ||
63 | + fpst = get_fpstatus_ptr(1); | ||
64 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
65 | + vfp_reg_offset(1, rn), | ||
66 | + vfp_reg_offset(1, rm), fpst, | ||
67 | + opr_sz, opr_sz, rot, | ||
68 | + size ? gen_helper_gvec_fcmlas_idx | ||
69 | + : gen_helper_gvec_fcmlah_idx); | ||
70 | + tcg_temp_free_ptr(fpst); | ||
71 | + return 0; | ||
72 | +} | 177 | +} |
73 | + | 178 | + |
74 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 179 | /* Generate a label used for skipping this instruction */ |
180 | void arm_gen_condlabel(DisasContext *s) | ||
75 | { | 181 | { |
76 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
77 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
78 | goto illegal_op; | ||
79 | } | ||
80 | return; | ||
81 | + } else if ((insn & 0x0f000a00) == 0x0e000800 | ||
82 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
83 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
84 | + goto illegal_op; | ||
85 | + } | ||
86 | + return; | ||
87 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
88 | /* Coprocessor double register transfer. */ | ||
89 | ARCH(5TE); | ||
90 | -- | 182 | -- |
91 | 2.16.2 | 183 | 2.20.1 |
92 | 184 | ||
93 | 185 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The A64 AdvSIMD modified-immediate grouping uses almost the same |
---|---|---|---|
2 | constant encoding that A32 Neon does; reuse asimd_imm_const() (to | ||
3 | which we add the AArch64-specific case for cmode 15 op 1) instead of | ||
4 | reimplementing it all. | ||
2 | 5 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20180228193125.20577-13-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | [PMM: renamed e1/e2/e3/e4 to use the same naming as the version | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | of the pseudocode in the Arm ARM] | 8 | Message-id: 20210628135835.6690-5-peter.maydell@linaro.org |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | 9 | --- |
10 | target/arm/helper.h | 11 ++++ | 10 | target/arm/translate.h | 3 +- |
11 | target/arm/translate-a64.c | 94 +++++++++++++++++++++++++--- | 11 | target/arm/translate-a64.c | 86 ++++---------------------------------- |
12 | target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/translate.c | 17 +++++++- |
13 | 3 files changed, 246 insertions(+), 8 deletions(-) | 13 | 3 files changed, 24 insertions(+), 82 deletions(-) |
14 | 14 | ||
15 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.h | 17 | --- a/target/arm/translate.h |
18 | +++ b/target/arm/helper.h | 18 | +++ b/target/arm/translate.h |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) |
20 | DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | 20 | * VMVN and VBIC (when cmode < 14 && op == 1). |
21 | void, ptr, ptr, ptr, ptr, i32) | 21 | * |
22 | 22 | * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | |
23 | +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, | 23 | - * callers must catch this. |
24 | + void, ptr, ptr, ptr, ptr, i32) | 24 | + * callers must catch this; we return the 64-bit constant value defined |
25 | +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, | 25 | + * for AArch64. |
26 | + void, ptr, ptr, ptr, ptr, i32) | 26 | * |
27 | +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, | 27 | * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but |
28 | + void, ptr, ptr, ptr, ptr, i32) | 28 | * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; |
29 | +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, | ||
30 | + void, ptr, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, | ||
32 | + void, ptr, ptr, ptr, ptr, i32) | ||
33 | + | ||
34 | #ifdef TARGET_AARCH64 | ||
35 | #include "helper-a64.h" | ||
36 | #endif | ||
37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
38 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/translate-a64.c | 31 | --- a/target/arm/translate-a64.c |
40 | +++ b/target/arm/translate-a64.c | 32 | +++ b/target/arm/translate-a64.c |
41 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | 33 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
42 | } | 34 | { |
43 | feature = ARM_FEATURE_V8_RDM; | ||
44 | break; | ||
45 | + case 0x8: /* FCMLA, #0 */ | ||
46 | + case 0x9: /* FCMLA, #90 */ | ||
47 | + case 0xa: /* FCMLA, #180 */ | ||
48 | + case 0xb: /* FCMLA, #270 */ | ||
49 | case 0xc: /* FCADD, #90 */ | ||
50 | case 0xe: /* FCADD, #270 */ | ||
51 | if (size == 0 | ||
52 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
53 | } | ||
54 | return; | ||
55 | |||
56 | + case 0x8: /* FCMLA, #0 */ | ||
57 | + case 0x9: /* FCMLA, #90 */ | ||
58 | + case 0xa: /* FCMLA, #180 */ | ||
59 | + case 0xb: /* FCMLA, #270 */ | ||
60 | + rot = extract32(opcode, 0, 2); | ||
61 | + switch (size) { | ||
62 | + case 1: | ||
63 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | ||
64 | + gen_helper_gvec_fcmlah); | ||
65 | + break; | ||
66 | + case 2: | ||
67 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
68 | + gen_helper_gvec_fcmlas); | ||
69 | + break; | ||
70 | + case 3: | ||
71 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
72 | + gen_helper_gvec_fcmlad); | ||
73 | + break; | ||
74 | + default: | ||
75 | + g_assert_not_reached(); | ||
76 | + } | ||
77 | + return; | ||
78 | + | ||
79 | case 0xc: /* FCADD, #90 */ | ||
80 | case 0xe: /* FCADD, #270 */ | ||
81 | rot = extract32(opcode, 1, 1); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
83 | int rn = extract32(insn, 5, 5); | ||
84 | int rd = extract32(insn, 0, 5); | 35 | int rd = extract32(insn, 0, 5); |
85 | bool is_long = false; | 36 | int cmode = extract32(insn, 12, 4); |
86 | - bool is_fp = false; | 37 | - int cmode_3_1 = extract32(cmode, 1, 3); |
87 | + int is_fp = 0; | 38 | - int cmode_0 = extract32(cmode, 0, 1); |
88 | bool is_fp16 = false; | 39 | int o2 = extract32(insn, 11, 1); |
89 | int index; | 40 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); |
90 | TCGv_ptr fpst; | 41 | bool is_neg = extract32(insn, 29, 1); |
91 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 42 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
92 | case 0x05: /* FMLS */ | ||
93 | case 0x09: /* FMUL */ | ||
94 | case 0x19: /* FMULX */ | ||
95 | - is_fp = true; | ||
96 | + is_fp = 1; | ||
97 | break; | ||
98 | case 0x1d: /* SQRDMLAH */ | ||
99 | case 0x1f: /* SQRDMLSH */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
101 | return; | ||
102 | } | ||
103 | break; | ||
104 | + case 0x11: /* FCMLA #0 */ | ||
105 | + case 0x13: /* FCMLA #90 */ | ||
106 | + case 0x15: /* FCMLA #180 */ | ||
107 | + case 0x17: /* FCMLA #270 */ | ||
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { | ||
109 | + unallocated_encoding(s); | ||
110 | + return; | ||
111 | + } | ||
112 | + is_fp = 2; | ||
113 | + break; | ||
114 | default: | ||
115 | unallocated_encoding(s); | ||
116 | return; | 43 | return; |
117 | } | 44 | } |
118 | 45 | ||
119 | - if (is_fp) { | 46 | - /* See AdvSIMDExpandImm() in ARM ARM */ |
120 | + switch (is_fp) { | 47 | - switch (cmode_3_1) { |
121 | + case 1: /* normal fp */ | 48 | - case 0: /* Replicate(Zeros(24):imm8, 2) */ |
122 | /* convert insn encoded size to TCGMemOp size */ | 49 | - case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ |
123 | switch (size) { | 50 | - case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ |
124 | case 0: /* half-precision */ | 51 | - case 3: /* Replicate(imm8:Zeros(24), 2) */ |
125 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | 52 | - { |
126 | - unallocated_encoding(s); | 53 | - int shift = cmode_3_1 * 8; |
127 | - return; | 54 | - imm = bitfield_replicate(abcdefgh << shift, 32); |
55 | - break; | ||
56 | - } | ||
57 | - case 4: /* Replicate(Zeros(8):imm8, 4) */ | ||
58 | - case 5: /* Replicate(imm8:Zeros(8), 4) */ | ||
59 | - { | ||
60 | - int shift = (cmode_3_1 & 0x1) * 8; | ||
61 | - imm = bitfield_replicate(abcdefgh << shift, 16); | ||
62 | - break; | ||
63 | - } | ||
64 | - case 6: | ||
65 | - if (cmode_0) { | ||
66 | - /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | ||
67 | - imm = (abcdefgh << 16) | 0xffff; | ||
68 | - } else { | ||
69 | - /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | ||
70 | - imm = (abcdefgh << 8) | 0xff; | ||
71 | - } | ||
72 | - imm = bitfield_replicate(imm, 32); | ||
73 | - break; | ||
74 | - case 7: | ||
75 | - if (!cmode_0 && !is_neg) { | ||
76 | - imm = bitfield_replicate(abcdefgh, 8); | ||
77 | - } else if (!cmode_0 && is_neg) { | ||
78 | - int i; | ||
79 | - imm = 0; | ||
80 | - for (i = 0; i < 8; i++) { | ||
81 | - if ((abcdefgh) & (1 << i)) { | ||
82 | - imm |= 0xffULL << (i * 8); | ||
83 | - } | ||
128 | - } | 84 | - } |
129 | size = MO_16; | 85 | - } else if (cmode_0) { |
130 | + is_fp16 = true; | 86 | - if (is_neg) { |
131 | break; | 87 | - imm = (abcdefgh & 0x3f) << 48; |
132 | case MO_32: /* single precision */ | 88 | - if (abcdefgh & 0x80) { |
133 | case MO_64: /* double precision */ | 89 | - imm |= 0x8000000000000000ULL; |
134 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 90 | - } |
135 | unallocated_encoding(s); | 91 | - if (abcdefgh & 0x40) { |
136 | return; | 92 | - imm |= 0x3fc0000000000000ULL; |
137 | } | 93 | - } else { |
138 | - } else { | 94 | - imm |= 0x4000000000000000ULL; |
139 | + break; | 95 | - } |
140 | + | 96 | - } else { |
141 | + case 2: /* complex fp */ | 97 | - if (o2) { |
142 | + /* Each indexable element is a complex pair. */ | 98 | - /* FMOV (vector, immediate) - half-precision */ |
143 | + size <<= 1; | 99 | - imm = vfp_expand_imm(MO_16, abcdefgh); |
144 | + switch (size) { | 100 | - /* now duplicate across the lanes */ |
145 | + case MO_32: | 101 | - imm = bitfield_replicate(imm, 16); |
146 | + if (h && !is_q) { | 102 | - } else { |
147 | + unallocated_encoding(s); | 103 | - imm = (abcdefgh & 0x3f) << 19; |
148 | + return; | 104 | - if (abcdefgh & 0x80) { |
105 | - imm |= 0x80000000; | ||
106 | - } | ||
107 | - if (abcdefgh & 0x40) { | ||
108 | - imm |= 0x3e000000; | ||
109 | - } else { | ||
110 | - imm |= 0x40000000; | ||
111 | - } | ||
112 | - imm |= (imm << 32); | ||
113 | - } | ||
114 | - } | ||
115 | - } | ||
116 | - break; | ||
117 | - default: | ||
118 | - g_assert_not_reached(); | ||
119 | - } | ||
120 | - | ||
121 | - if (cmode_3_1 != 7 && is_neg) { | ||
122 | - imm = ~imm; | ||
123 | + if (cmode == 15 && o2 && !is_neg) { | ||
124 | + /* FMOV (vector, immediate) - half-precision */ | ||
125 | + imm = vfp_expand_imm(MO_16, abcdefgh); | ||
126 | + /* now duplicate across the lanes */ | ||
127 | + imm = bitfield_replicate(imm, 16); | ||
128 | + } else { | ||
129 | + imm = asimd_imm_const(abcdefgh, cmode, is_neg); | ||
130 | } | ||
131 | |||
132 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { | ||
133 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
134 | index XXXXXXX..XXXXXXX 100644 | ||
135 | --- a/target/arm/translate.c | ||
136 | +++ b/target/arm/translate.c | ||
137 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
138 | case 14: | ||
139 | if (op) { | ||
140 | /* | ||
141 | - * This is the only case where the top and bottom 32 bits | ||
142 | - * of the encoded constant differ. | ||
143 | + * This and cmode == 15 op == 1 are the only cases where | ||
144 | + * the top and bottom 32 bits of the encoded constant differ. | ||
145 | */ | ||
146 | uint64_t imm64 = 0; | ||
147 | int n; | ||
148 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
149 | imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
150 | break; | ||
151 | case 15: | ||
152 | + if (op) { | ||
153 | + /* Reserved encoding for AArch32; valid for AArch64 */ | ||
154 | + uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; | ||
155 | + if (imm & 0x80) { | ||
156 | + imm64 |= 0x8000000000000000ULL; | ||
149 | + } | 157 | + } |
150 | + is_fp16 = true; | 158 | + if (imm & 0x40) { |
151 | + break; | 159 | + imm64 |= 0x3fc0000000000000ULL; |
152 | + case MO_64: | 160 | + } else { |
153 | + break; | 161 | + imm64 |= 0x4000000000000000ULL; |
154 | + default: | 162 | + } |
155 | + unallocated_encoding(s); | 163 | + return imm64; |
156 | + return; | ||
157 | + } | 164 | + } |
158 | + break; | 165 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
159 | + | 166 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
160 | + default: /* integer */ | 167 | break; |
161 | switch (size) { | ||
162 | case MO_8: | ||
163 | case MO_64: | ||
164 | unallocated_encoding(s); | ||
165 | return; | ||
166 | } | ||
167 | + break; | ||
168 | + } | ||
169 | + if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
170 | + unallocated_encoding(s); | ||
171 | + return; | ||
172 | } | ||
173 | |||
174 | /* Given TCGMemOp size, adjust register and indexing. */ | ||
175 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
176 | fpst = NULL; | ||
177 | } | ||
178 | |||
179 | + switch (16 * u + opcode) { | ||
180 | + case 0x11: /* FCMLA #0 */ | ||
181 | + case 0x13: /* FCMLA #90 */ | ||
182 | + case 0x15: /* FCMLA #180 */ | ||
183 | + case 0x17: /* FCMLA #270 */ | ||
184 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
185 | + vec_full_reg_offset(s, rn), | ||
186 | + vec_reg_offset(s, rm, index, size), fpst, | ||
187 | + is_q ? 16 : 8, vec_full_reg_size(s), | ||
188 | + extract32(insn, 13, 2), /* rot */ | ||
189 | + size == MO_64 | ||
190 | + ? gen_helper_gvec_fcmlas_idx | ||
191 | + : gen_helper_gvec_fcmlah_idx); | ||
192 | + tcg_temp_free_ptr(fpst); | ||
193 | + return; | ||
194 | + } | ||
195 | + | ||
196 | if (size == 3) { | ||
197 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | ||
198 | int pass; | ||
199 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/target/arm/vec_helper.c | ||
202 | +++ b/target/arm/vec_helper.c | ||
203 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
204 | } | ||
205 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
206 | } | ||
207 | + | ||
208 | +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, | ||
209 | + void *vfpst, uint32_t desc) | ||
210 | +{ | ||
211 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
212 | + float16 *d = vd; | ||
213 | + float16 *n = vn; | ||
214 | + float16 *m = vm; | ||
215 | + float_status *fpst = vfpst; | ||
216 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
217 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
218 | + uint32_t neg_real = flip ^ neg_imag; | ||
219 | + uintptr_t i; | ||
220 | + | ||
221 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
222 | + neg_real <<= 15; | ||
223 | + neg_imag <<= 15; | ||
224 | + | ||
225 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
226 | + float16 e2 = n[H2(i + flip)]; | ||
227 | + float16 e1 = m[H2(i + flip)] ^ neg_real; | ||
228 | + float16 e4 = e2; | ||
229 | + float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; | ||
230 | + | ||
231 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
232 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
233 | + } | ||
234 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
235 | +} | ||
236 | + | ||
237 | +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, | ||
238 | + void *vfpst, uint32_t desc) | ||
239 | +{ | ||
240 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
241 | + float16 *d = vd; | ||
242 | + float16 *n = vn; | ||
243 | + float16 *m = vm; | ||
244 | + float_status *fpst = vfpst; | ||
245 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
246 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
247 | + uint32_t neg_real = flip ^ neg_imag; | ||
248 | + uintptr_t i; | ||
249 | + float16 e1 = m[H2(flip)]; | ||
250 | + float16 e3 = m[H2(1 - flip)]; | ||
251 | + | ||
252 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
253 | + neg_real <<= 15; | ||
254 | + neg_imag <<= 15; | ||
255 | + e1 ^= neg_real; | ||
256 | + e3 ^= neg_imag; | ||
257 | + | ||
258 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
259 | + float16 e2 = n[H2(i + flip)]; | ||
260 | + float16 e4 = e2; | ||
261 | + | ||
262 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
263 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
264 | + } | ||
265 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
266 | +} | ||
267 | + | ||
268 | +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, | ||
269 | + void *vfpst, uint32_t desc) | ||
270 | +{ | ||
271 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
272 | + float32 *d = vd; | ||
273 | + float32 *n = vn; | ||
274 | + float32 *m = vm; | ||
275 | + float_status *fpst = vfpst; | ||
276 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
277 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
278 | + uint32_t neg_real = flip ^ neg_imag; | ||
279 | + uintptr_t i; | ||
280 | + | ||
281 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
282 | + neg_real <<= 31; | ||
283 | + neg_imag <<= 31; | ||
284 | + | ||
285 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
286 | + float32 e2 = n[H4(i + flip)]; | ||
287 | + float32 e1 = m[H4(i + flip)] ^ neg_real; | ||
288 | + float32 e4 = e2; | ||
289 | + float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; | ||
290 | + | ||
291 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
292 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
293 | + } | ||
294 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
295 | +} | ||
296 | + | ||
297 | +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, | ||
298 | + void *vfpst, uint32_t desc) | ||
299 | +{ | ||
300 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
301 | + float32 *d = vd; | ||
302 | + float32 *n = vn; | ||
303 | + float32 *m = vm; | ||
304 | + float_status *fpst = vfpst; | ||
305 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
306 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
307 | + uint32_t neg_real = flip ^ neg_imag; | ||
308 | + uintptr_t i; | ||
309 | + float32 e1 = m[H4(flip)]; | ||
310 | + float32 e3 = m[H4(1 - flip)]; | ||
311 | + | ||
312 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
313 | + neg_real <<= 31; | ||
314 | + neg_imag <<= 31; | ||
315 | + e1 ^= neg_real; | ||
316 | + e3 ^= neg_imag; | ||
317 | + | ||
318 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
319 | + float32 e2 = n[H4(i + flip)]; | ||
320 | + float32 e4 = e2; | ||
321 | + | ||
322 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
323 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
324 | + } | ||
325 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
326 | +} | ||
327 | + | ||
328 | +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, | ||
329 | + void *vfpst, uint32_t desc) | ||
330 | +{ | ||
331 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
332 | + float64 *d = vd; | ||
333 | + float64 *n = vn; | ||
334 | + float64 *m = vm; | ||
335 | + float_status *fpst = vfpst; | ||
336 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
337 | + uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
338 | + uint64_t neg_real = flip ^ neg_imag; | ||
339 | + uintptr_t i; | ||
340 | + | ||
341 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
342 | + neg_real <<= 63; | ||
343 | + neg_imag <<= 63; | ||
344 | + | ||
345 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
346 | + float64 e2 = n[i + flip]; | ||
347 | + float64 e1 = m[i + flip] ^ neg_real; | ||
348 | + float64 e4 = e2; | ||
349 | + float64 e3 = m[i + 1 - flip] ^ neg_imag; | ||
350 | + | ||
351 | + d[i] = float64_muladd(e2, e1, d[i], 0, fpst); | ||
352 | + d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); | ||
353 | + } | ||
354 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
355 | +} | ||
356 | -- | 168 | -- |
357 | 2.16.2 | 169 | 2.20.1 |
358 | 170 | ||
359 | 171 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Use dup_const() instead of bitfield_replicate() in |
---|---|---|---|
2 | disas_simd_mod_imm(). | ||
2 | 3 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 4 | (We can't replace the other use of bitfield_replicate() in this file, |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | in logic_imm_decode_wmask(), because that location needs to handle 2 |
5 | Message-id: 20180228193125.20577-7-richard.henderson@linaro.org | 6 | and 4 bit elements, which dup_const() cannot.) |
7 | |||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20210628135835.6690-6-peter.maydell@linaro.org | ||
7 | --- | 11 | --- |
8 | target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ | 12 | target/arm/translate-a64.c | 2 +- |
9 | 1 file changed, 29 insertions(+) | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 14 | ||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-a64.c | 17 | --- a/target/arm/translate-a64.c |
14 | +++ b/target/arm/translate-a64.c | 18 | +++ b/target/arm/translate-a64.c |
15 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
16 | case 0x19: /* FMULX */ | 20 | /* FMOV (vector, immediate) - half-precision */ |
17 | is_fp = true; | 21 | imm = vfp_expand_imm(MO_16, abcdefgh); |
18 | break; | 22 | /* now duplicate across the lanes */ |
19 | + case 0x1d: /* SQRDMLAH */ | 23 | - imm = bitfield_replicate(imm, 16); |
20 | + case 0x1f: /* SQRDMLSH */ | 24 | + imm = dup_const(MO_16, imm); |
21 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | 25 | } else { |
22 | + unallocated_encoding(s); | 26 | imm = asimd_imm_const(abcdefgh, cmode, is_neg); |
23 | + return; | 27 | } |
24 | + } | ||
25 | + break; | ||
26 | default: | ||
27 | unallocated_encoding(s); | ||
28 | return; | ||
29 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
30 | tcg_op, tcg_idx); | ||
31 | } | ||
32 | break; | ||
33 | + case 0x1d: /* SQRDMLAH */ | ||
34 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
35 | + is_scalar ? size : MO_32); | ||
36 | + if (size == 1) { | ||
37 | + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | ||
38 | + tcg_op, tcg_idx, tcg_res); | ||
39 | + } else { | ||
40 | + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | ||
41 | + tcg_op, tcg_idx, tcg_res); | ||
42 | + } | ||
43 | + break; | ||
44 | + case 0x1f: /* SQRDMLSH */ | ||
45 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
46 | + is_scalar ? size : MO_32); | ||
47 | + if (size == 1) { | ||
48 | + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | ||
49 | + tcg_op, tcg_idx, tcg_res); | ||
50 | + } else { | ||
51 | + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | ||
52 | + tcg_op, tcg_idx, tcg_res); | ||
53 | + } | ||
54 | + break; | ||
55 | default: | ||
56 | g_assert_not_reached(); | ||
57 | } | ||
58 | -- | 28 | -- |
59 | 2.16.2 | 29 | 2.20.1 |
60 | 30 | ||
61 | 31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE logical-immediate insns (VMOV, VMVN, |
---|---|---|---|
2 | VORR and VBIC). These have essentially the same encoding | ||
3 | as their Neon equivalents, and we implement the decode | ||
4 | in the same way. | ||
2 | 5 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-5-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-7-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | target/arm/Makefile.objs | 2 +- | 10 | target/arm/helper-mve.h | 4 +++ |
9 | target/arm/helper.h | 4 ++ | 11 | target/arm/mve.decode | 17 +++++++++++++ |
10 | target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++ | 12 | target/arm/mve_helper.c | 24 ++++++++++++++++++ |
11 | target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ | 13 | target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++ |
12 | 4 files changed, 198 insertions(+), 1 deletion(-) | 14 | 4 files changed, 95 insertions(+) |
13 | create mode 100644 target/arm/vec_helper.c | ||
14 | 15 | ||
15 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/Makefile.objs | 18 | --- a/target/arm/helper-mve.h |
18 | +++ b/target/arm/Makefile.objs | 19 | +++ b/target/arm/helper-mve.h |
19 | @@ -XXX,XX +XXX,XX @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
20 | obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o | 21 | DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
21 | obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o | 22 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
22 | obj-y += translate.o op_helper.o helper.o cpu.o | 23 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
23 | -obj-y += neon_helper.o iwmmxt_helper.o | 24 | + |
24 | +obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o | 25 | +DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
25 | obj-y += gdbstub.o | 26 | +DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
26 | obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o | 27 | +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) |
27 | obj-y += crypto_helper.o | 28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
28 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/helper.h | 30 | --- a/target/arm/mve.decode |
31 | +++ b/target/arm/helper.h | 31 | +++ b/target/arm/mve.decode |
32 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) | 32 | @@ -XXX,XX +XXX,XX @@ |
33 | 33 | # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit | |
34 | DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) | 34 | %size_28 28:1 !function=plus_1 |
35 | DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) | 35 | |
36 | +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) | 36 | +# 1imm format immediate |
37 | +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) | 37 | +%imm_28_16_0 28:1 16:3 0:4 |
38 | DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) | 38 | + |
39 | DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) | 39 | &vldr_vstr rn qd imm p a w size l u |
40 | +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) | 40 | &1op qd qm size |
41 | +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) | 41 | &2op qd qm qn size |
42 | 42 | &2scalar qd qn rm size | |
43 | DEF_HELPER_1(neon_narrow_u8, i32, i64) | 43 | +&1imm qd imm cmode op |
44 | DEF_HELPER_1(neon_narrow_u16, i32, i64) | 44 | |
45 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 45 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 |
46 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
47 | @@ -XXX,XX +XXX,XX @@ | ||
48 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | ||
49 | @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ | ||
50 | size=%size_28 | ||
51 | +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0 | ||
52 | |||
53 | # The _rev suffix indicates that Vn and Vm are reversed. This is | ||
54 | # the case for shifts. In the Arm ARM these insns are documented | ||
55 | @@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd | ||
56 | # Predicate operations | ||
57 | %mask_22_13 22:1 13:3 | ||
58 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
59 | + | ||
60 | +# Logical immediate operations (1 reg and modified-immediate) | ||
61 | + | ||
62 | +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but | ||
63 | +# not in a way we can conveniently represent in decodetree without | ||
64 | +# a lot of repetition: | ||
65 | +# VORR: op=0, (cmode & 1) && cmode < 12 | ||
66 | +# VBIC: op=1, (cmode & 1) && cmode < 12 | ||
67 | +# VMOV: everything else | ||
68 | +# So we have a single decode line and check the cmode/op in the | ||
69 | +# trans function. | ||
70 | +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
71 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | 72 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/target/arm/translate-a64.c | 73 | --- a/target/arm/mve_helper.c |
48 | +++ b/target/arm/translate-a64.c | 74 | +++ b/target/arm/mve_helper.c |
49 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | 75 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG) |
50 | tcg_temp_free_ptr(fpst); | 76 | DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) |
51 | } | 77 | DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) |
52 | 78 | ||
53 | +/* AdvSIMD scalar three same extra | 79 | +/* |
54 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | 80 | + * 1 operand immediates: Vda is destination and possibly also one source. |
55 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | 81 | + * All these insns work at 64-bit widths. |
56 | + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
57 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
58 | + */ | 82 | + */ |
59 | +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | 83 | +#define DO_1OP_IMM(OP, FN) \ |
60 | + uint32_t insn) | 84 | + void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ |
61 | +{ | 85 | + { \ |
62 | + int rd = extract32(insn, 0, 5); | 86 | + uint64_t *da = vda; \ |
63 | + int rn = extract32(insn, 5, 5); | 87 | + uint16_t mask = mve_element_mask(env); \ |
64 | + int opcode = extract32(insn, 11, 4); | 88 | + unsigned e; \ |
65 | + int rm = extract32(insn, 16, 5); | 89 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ |
66 | + int size = extract32(insn, 22, 2); | 90 | + mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ |
67 | + bool u = extract32(insn, 29, 1); | 91 | + } \ |
68 | + TCGv_i32 ele1, ele2, ele3; | 92 | + mve_advance_vpt(env); \ |
69 | + TCGv_i64 res; | ||
70 | + int feature; | ||
71 | + | ||
72 | + switch (u * 16 + opcode) { | ||
73 | + case 0x10: /* SQRDMLAH (vector) */ | ||
74 | + case 0x11: /* SQRDMLSH (vector) */ | ||
75 | + if (size != 1 && size != 2) { | ||
76 | + unallocated_encoding(s); | ||
77 | + return; | ||
78 | + } | ||
79 | + feature = ARM_FEATURE_V8_RDM; | ||
80 | + break; | ||
81 | + default: | ||
82 | + unallocated_encoding(s); | ||
83 | + return; | ||
84 | + } | ||
85 | + if (!arm_dc_feature(s, feature)) { | ||
86 | + unallocated_encoding(s); | ||
87 | + return; | ||
88 | + } | ||
89 | + if (!fp_access_check(s)) { | ||
90 | + return; | ||
91 | + } | 93 | + } |
92 | + | 94 | + |
93 | + /* Do a single operation on the lowest element in the vector. | 95 | +#define DO_MOVI(N, I) (I) |
94 | + * We use the standard Neon helpers and rely on 0 OP 0 == 0 | 96 | +#define DO_ANDI(N, I) ((N) & (I)) |
95 | + * with no side effects for all these operations. | 97 | +#define DO_ORRI(N, I) ((N) | (I)) |
96 | + * OPTME: special-purpose helpers would avoid doing some | ||
97 | + * unnecessary work in the helper for the 16 bit cases. | ||
98 | + */ | ||
99 | + ele1 = tcg_temp_new_i32(); | ||
100 | + ele2 = tcg_temp_new_i32(); | ||
101 | + ele3 = tcg_temp_new_i32(); | ||
102 | + | 98 | + |
103 | + read_vec_element_i32(s, ele1, rn, 0, size); | 99 | +DO_1OP_IMM(vmovi, DO_MOVI) |
104 | + read_vec_element_i32(s, ele2, rm, 0, size); | 100 | +DO_1OP_IMM(vandi, DO_ANDI) |
105 | + read_vec_element_i32(s, ele3, rd, 0, size); | 101 | +DO_1OP_IMM(vorri, DO_ORRI) |
106 | + | 102 | + |
107 | + switch (opcode) { | 103 | #define DO_2OP(OP, ESIZE, TYPE, FN) \ |
108 | + case 0x0: /* SQRDMLAH */ | 104 | void HELPER(glue(mve_, OP))(CPUARMState *env, \ |
109 | + if (size == 1) { | 105 | void *vd, void *vn, void *vm) \ |
110 | + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | 106 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
111 | + } else { | 107 | index XXXXXXX..XXXXXXX 100644 |
112 | + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | 108 | --- a/target/arm/translate-mve.c |
113 | + } | 109 | +++ b/target/arm/translate-mve.c |
114 | + break; | 110 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); |
115 | + case 0x1: /* SQRDMLSH */ | 111 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); |
116 | + if (size == 1) { | 112 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); |
117 | + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | 113 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); |
118 | + } else { | 114 | +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); |
119 | + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | 115 | |
120 | + } | 116 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ |
121 | + break; | 117 | static inline long mve_qreg_offset(unsigned reg) |
122 | + default: | 118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) |
123 | + g_assert_not_reached(); | 119 | mve_update_eci(s); |
120 | return true; | ||
121 | } | ||
122 | + | ||
123 | +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
124 | +{ | ||
125 | + TCGv_ptr qd; | ||
126 | + uint64_t imm; | ||
127 | + | ||
128 | + if (!dc_isar_feature(aa32_mve, s) || | ||
129 | + !mve_check_qreg_bank(s, a->qd) || | ||
130 | + !fn) { | ||
131 | + return false; | ||
124 | + } | 132 | + } |
125 | + tcg_temp_free_i32(ele1); | 133 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
126 | + tcg_temp_free_i32(ele2); | 134 | + return true; |
135 | + } | ||
127 | + | 136 | + |
128 | + res = tcg_temp_new_i64(); | 137 | + imm = asimd_imm_const(a->imm, a->cmode, a->op); |
129 | + tcg_gen_extu_i32_i64(res, ele3); | ||
130 | + tcg_temp_free_i32(ele3); | ||
131 | + | 138 | + |
132 | + write_fp_dreg(s, rd, res); | 139 | + qd = mve_qreg_ptr(a->qd); |
133 | + tcg_temp_free_i64(res); | 140 | + fn(cpu_env, qd, tcg_constant_i64(imm)); |
141 | + tcg_temp_free_ptr(qd); | ||
142 | + mve_update_eci(s); | ||
143 | + return true; | ||
134 | +} | 144 | +} |
135 | + | 145 | + |
136 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, | 146 | +static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) |
137 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, | 147 | +{ |
138 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | 148 | + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ |
139 | @@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = { | 149 | + MVEGenOneOpImmFn *fn; |
140 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | ||
141 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | ||
142 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | ||
143 | + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, | ||
144 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | ||
145 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | ||
146 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | ||
147 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
148 | new file mode 100644 | ||
149 | index XXXXXXX..XXXXXXX | ||
150 | --- /dev/null | ||
151 | +++ b/target/arm/vec_helper.c | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | +/* | ||
154 | + * ARM AdvSIMD / SVE Vector Operations | ||
155 | + * | ||
156 | + * Copyright (c) 2018 Linaro | ||
157 | + * | ||
158 | + * This library is free software; you can redistribute it and/or | ||
159 | + * modify it under the terms of the GNU Lesser General Public | ||
160 | + * License as published by the Free Software Foundation; either | ||
161 | + * version 2 of the License, or (at your option) any later version. | ||
162 | + * | ||
163 | + * This library is distributed in the hope that it will be useful, | ||
164 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
165 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
166 | + * Lesser General Public License for more details. | ||
167 | + * | ||
168 | + * You should have received a copy of the GNU Lesser General Public | ||
169 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
170 | + */ | ||
171 | + | 150 | + |
172 | +#include "qemu/osdep.h" | 151 | + if ((a->cmode & 1) && a->cmode < 12) { |
173 | +#include "cpu.h" | 152 | + if (a->op) { |
174 | +#include "exec/exec-all.h" | 153 | + /* |
175 | +#include "exec/helper-proto.h" | 154 | + * For op=1, the immediate will be inverted by asimd_imm_const(), |
176 | +#include "tcg/tcg-gvec-desc.h" | 155 | + * so the VBIC becomes a logical AND operation. |
177 | + | 156 | + */ |
178 | + | 157 | + fn = gen_helper_mve_vandi; |
179 | +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | 158 | + } else { |
180 | + | 159 | + fn = gen_helper_mve_vorri; |
181 | +/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | 160 | + } |
182 | +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | 161 | + } else { |
183 | + int16_t src2, int16_t src3) | 162 | + /* There is one unallocated cmode/op combination in this space */ |
184 | +{ | 163 | + if (a->cmode == 15 && a->op == 1) { |
185 | + /* Simplify: | 164 | + return false; |
186 | + * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 | 165 | + } |
187 | + * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 | 166 | + /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ |
188 | + */ | 167 | + fn = gen_helper_mve_vmovi; |
189 | + int32_t ret = (int32_t)src1 * src2; | ||
190 | + ret = ((int32_t)src3 << 15) + ret + (1 << 14); | ||
191 | + ret >>= 15; | ||
192 | + if (ret != (int16_t)ret) { | ||
193 | + SET_QC(); | ||
194 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
195 | + } | 168 | + } |
196 | + return ret; | 169 | + return do_1imm(s, a, fn); |
197 | +} | ||
198 | + | ||
199 | +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
200 | + uint32_t src2, uint32_t src3) | ||
201 | +{ | ||
202 | + uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3); | ||
203 | + uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
204 | + return deposit32(e1, 16, 16, e2); | ||
205 | +} | ||
206 | + | ||
207 | +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | ||
208 | +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | ||
209 | + int16_t src2, int16_t src3) | ||
210 | +{ | ||
211 | + /* Similarly, using subtraction: | ||
212 | + * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
213 | + * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 | ||
214 | + */ | ||
215 | + int32_t ret = (int32_t)src1 * src2; | ||
216 | + ret = ((int32_t)src3 << 15) - ret + (1 << 14); | ||
217 | + ret >>= 15; | ||
218 | + if (ret != (int16_t)ret) { | ||
219 | + SET_QC(); | ||
220 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
221 | + } | ||
222 | + return ret; | ||
223 | +} | ||
224 | + | ||
225 | +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
226 | + uint32_t src2, uint32_t src3) | ||
227 | +{ | ||
228 | + uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3); | ||
229 | + uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
230 | + return deposit32(e1, 16, 16, e2); | ||
231 | +} | ||
232 | + | ||
233 | +/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
234 | +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
235 | + int32_t src2, int32_t src3) | ||
236 | +{ | ||
237 | + /* Simplify similarly to int_qrdmlah_s16 above. */ | ||
238 | + int64_t ret = (int64_t)src1 * src2; | ||
239 | + ret = ((int64_t)src3 << 31) + ret + (1 << 30); | ||
240 | + ret >>= 31; | ||
241 | + if (ret != (int32_t)ret) { | ||
242 | + SET_QC(); | ||
243 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
244 | + } | ||
245 | + return ret; | ||
246 | +} | ||
247 | + | ||
248 | +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
249 | +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
250 | + int32_t src2, int32_t src3) | ||
251 | +{ | ||
252 | + /* Simplify similarly to int_qrdmlsh_s16 above. */ | ||
253 | + int64_t ret = (int64_t)src1 * src2; | ||
254 | + ret = ((int64_t)src3 << 31) - ret + (1 << 30); | ||
255 | + ret >>= 31; | ||
256 | + if (ret != (int32_t)ret) { | ||
257 | + SET_QC(); | ||
258 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
259 | + } | ||
260 | + return ret; | ||
261 | +} | 170 | +} |
262 | -- | 171 | -- |
263 | 2.16.2 | 172 | 2.20.1 |
264 | 173 | ||
265 | 174 | diff view generated by jsdifflib |
1 | Add a Cortex-M33 definition. The M33 is an M profile CPU | 1 | Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL |
---|---|---|---|
2 | which implements the ARM v8M architecture, including the | 2 | and VQSHLU. |
3 | M profile Security Extension. | 3 | |
4 | The size-and-immediate encoding here is the same as Neon, and we | ||
5 | handle it the same way neon-dp.decode does. | ||
4 | 6 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-9-peter.maydell@linaro.org | 9 | Message-id: 20210628135835.6690-8-peter.maydell@linaro.org |
8 | --- | 10 | --- |
9 | target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++ | 11 | target/arm/helper-mve.h | 16 +++++++++++ |
10 | 1 file changed, 31 insertions(+) | 12 | target/arm/mve.decode | 23 +++++++++++++++ |
11 | 13 | target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ | |
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++ |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | 4 files changed, 147 insertions(+) |
14 | --- a/target/arm/cpu.c | 16 | |
15 | +++ b/target/arm/cpu.c | 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | cpu->id_isar5 = 0x00000000; | 19 | --- a/target/arm/helper-mve.h |
20 | +++ b/target/arm/helper-mve.h | ||
21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
25 | + | ||
26 | +DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | + | ||
30 | +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | + | ||
34 | +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/mve.decode | ||
44 | +++ b/target/arm/mve.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | &2op qd qm qn size | ||
47 | &2scalar qd qn rm size | ||
48 | &1imm qd imm cmode op | ||
49 | +&2shift qd qm shift size | ||
50 | |||
51 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
52 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
55 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
56 | |||
57 | +@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | ||
58 | +@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
59 | +@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
60 | + | ||
61 | # Vector loads and stores | ||
62 | |||
63 | # Widening loads and narrowing stores: | ||
64 | @@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
65 | # So we have a single decode line and check the cmode/op in the | ||
66 | # trans function. | ||
67 | Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
68 | + | ||
69 | +# Shifts by immediate | ||
70 | + | ||
71 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
72 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
73 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
74 | + | ||
75 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
76 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
77 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
78 | + | ||
79 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
80 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
81 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
82 | + | ||
83 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
84 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
85 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
86 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/target/arm/mve_helper.c | ||
89 | +++ b/target/arm/mve_helper.c | ||
90 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
91 | WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) | ||
92 | #define DO_UQRSHL_OP(N, M, satp) \ | ||
93 | WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) | ||
94 | +#define DO_SUQSHL_OP(N, M, satp) \ | ||
95 | + WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) | ||
96 | |||
97 | DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) | ||
98 | DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
99 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t) | ||
100 | DO_VADDV(vaddvub, 1, uint8_t) | ||
101 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
102 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
103 | + | ||
104 | +/* Shifts by immediate */ | ||
105 | +#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
106 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
107 | + void *vm, uint32_t shift) \ | ||
108 | + { \ | ||
109 | + TYPE *d = vd, *m = vm; \ | ||
110 | + uint16_t mask = mve_element_mask(env); \ | ||
111 | + unsigned e; \ | ||
112 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
113 | + mergemask(&d[H##ESIZE(e)], \ | ||
114 | + FN(m[H##ESIZE(e)], shift), mask); \ | ||
115 | + } \ | ||
116 | + mve_advance_vpt(env); \ | ||
117 | + } | ||
118 | + | ||
119 | +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ | ||
120 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
121 | + void *vm, uint32_t shift) \ | ||
122 | + { \ | ||
123 | + TYPE *d = vd, *m = vm; \ | ||
124 | + uint16_t mask = mve_element_mask(env); \ | ||
125 | + unsigned e; \ | ||
126 | + bool qc = false; \ | ||
127 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
128 | + bool sat = false; \ | ||
129 | + mergemask(&d[H##ESIZE(e)], \ | ||
130 | + FN(m[H##ESIZE(e)], shift, &sat), mask); \ | ||
131 | + qc |= sat & mask & 1; \ | ||
132 | + } \ | ||
133 | + if (qc) { \ | ||
134 | + env->vfp.qc[0] = qc; \ | ||
135 | + } \ | ||
136 | + mve_advance_vpt(env); \ | ||
137 | + } | ||
138 | + | ||
139 | +/* provide unsigned 2-op shift helpers for all sizes */ | ||
140 | +#define DO_2SHIFT_U(OP, FN) \ | ||
141 | + DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
142 | + DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
143 | + DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
144 | + | ||
145 | +#define DO_2SHIFT_SAT_U(OP, FN) \ | ||
146 | + DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
147 | + DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ | ||
148 | + DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) | ||
149 | +#define DO_2SHIFT_SAT_S(OP, FN) \ | ||
150 | + DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ | ||
151 | + DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ | ||
152 | + DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
153 | + | ||
154 | +DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
155 | +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
156 | +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
157 | +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
158 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
159 | index XXXXXXX..XXXXXXX 100644 | ||
160 | --- a/target/arm/translate-mve.c | ||
161 | +++ b/target/arm/translate-mve.c | ||
162 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
163 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
164 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
165 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
166 | +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
167 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
168 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
169 | typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
170 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
171 | } | ||
172 | return do_1imm(s, a, fn); | ||
18 | } | 173 | } |
19 | 174 | + | |
20 | +static void cortex_m33_initfn(Object *obj) | 175 | +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
176 | + bool negateshift) | ||
21 | +{ | 177 | +{ |
22 | + ARMCPU *cpu = ARM_CPU(obj); | 178 | + TCGv_ptr qd, qm; |
23 | + | 179 | + int shift = a->shift; |
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 180 | + |
25 | + set_feature(&cpu->env, ARM_FEATURE_M); | 181 | + if (!dc_isar_feature(aa32_mve, s) || |
26 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | 182 | + !mve_check_qreg_bank(s, a->qd | a->qm) || |
27 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 183 | + !fn) { |
28 | + cpu->midr = 0x410fd213; /* r0p3 */ | 184 | + return false; |
29 | + cpu->pmsav7_dregion = 16; | 185 | + } |
30 | + cpu->sau_sregion = 8; | 186 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
31 | + cpu->id_pfr0 = 0x00000030; | 187 | + return true; |
32 | + cpu->id_pfr1 = 0x00000210; | 188 | + } |
33 | + cpu->id_dfr0 = 0x00200000; | 189 | + |
34 | + cpu->id_afr0 = 0x00000000; | 190 | + /* |
35 | + cpu->id_mmfr0 = 0x00101F40; | 191 | + * When we handle a right shift insn using a left-shift helper |
36 | + cpu->id_mmfr1 = 0x00000000; | 192 | + * which permits a negative shift count to indicate a right-shift, |
37 | + cpu->id_mmfr2 = 0x01000000; | 193 | + * we must negate the shift count. |
38 | + cpu->id_mmfr3 = 0x00000000; | 194 | + */ |
39 | + cpu->id_isar0 = 0x01101110; | 195 | + if (negateshift) { |
40 | + cpu->id_isar1 = 0x02212000; | 196 | + shift = -shift; |
41 | + cpu->id_isar2 = 0x20232232; | 197 | + } |
42 | + cpu->id_isar3 = 0x01111131; | 198 | + |
43 | + cpu->id_isar4 = 0x01310132; | 199 | + qd = mve_qreg_ptr(a->qd); |
44 | + cpu->id_isar5 = 0x00000000; | 200 | + qm = mve_qreg_ptr(a->qm); |
45 | + cpu->clidr = 0x00000000; | 201 | + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); |
46 | + cpu->ctr = 0x8000c000; | 202 | + tcg_temp_free_ptr(qd); |
203 | + tcg_temp_free_ptr(qm); | ||
204 | + mve_update_eci(s); | ||
205 | + return true; | ||
47 | +} | 206 | +} |
48 | + | 207 | + |
49 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | 208 | +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ |
50 | { | 209 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
51 | CPUClass *cc = CPU_CLASS(oc); | 210 | + { \ |
52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | 211 | + static MVEGenTwoOpShiftFn * const fns[] = { \ |
53 | .class_init = arm_v7m_class_init }, | 212 | + gen_helper_mve_##FN##b, \ |
54 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, | 213 | + gen_helper_mve_##FN##h, \ |
55 | .class_init = arm_v7m_class_init }, | 214 | + gen_helper_mve_##FN##w, \ |
56 | + { .name = "cortex-m33", .initfn = cortex_m33_initfn, | 215 | + NULL, \ |
57 | + .class_init = arm_v7m_class_init }, | 216 | + }; \ |
58 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | 217 | + return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ |
59 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, | 218 | + } |
60 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | 219 | + |
220 | +DO_2SHIFT(VSHLI, vshli_u, false) | ||
221 | +DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
222 | +DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
223 | +DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
61 | -- | 224 | -- |
62 | 2.16.2 | 225 | 2.20.1 |
63 | 226 | ||
64 | 227 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE vector shift right by immediate insns VSHRI and |
---|---|---|---|
2 | VRSHRI. As with Neon, we implement these by using helper functions | ||
3 | which perform left shifts but allow negative shift counts to indicate | ||
4 | right shifts. | ||
2 | 5 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-6-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-9-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | target/arm/helper.h | 9 +++++ | 10 | target/arm/helper-mve.h | 12 ++++++++++++ |
9 | target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ | 11 | target/arm/translate.h | 20 ++++++++++++++++++++ |
10 | target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/mve.decode | 28 ++++++++++++++++++++++++++++ |
11 | 3 files changed, 166 insertions(+) | 13 | target/arm/mve_helper.c | 7 +++++++ |
14 | target/arm/translate-mve.c | 5 +++++ | ||
15 | target/arm/translate-neon.c | 18 ------------------ | ||
16 | 6 files changed, 72 insertions(+), 18 deletions(-) | ||
12 | 17 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 20 | --- a/target/arm/helper-mve.h |
16 | +++ b/target/arm/helper.h | 21 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(dc_zva, void, env, i64) | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
18 | DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
19 | DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) |
20 | 25 | ||
21 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, | 26 | +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | + void, ptr, ptr, ptr, ptr, i32) | 27 | +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, | 28 | +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | ||
28 | + void, ptr, ptr, ptr, ptr, i32) | ||
29 | + | 29 | + |
30 | #ifdef TARGET_AARCH64 | 30 | DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | #include "helper-a64.h" | 31 | DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | #endif | 32 | DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 33 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
35 | DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | + | ||
42 | +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
45 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/translate-a64.c | 47 | --- a/target/arm/translate.h |
36 | +++ b/target/arm/translate-a64.c | 48 | +++ b/target/arm/translate.h |
37 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, | 49 | @@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x) |
38 | vec_full_reg_size(s), gvec_op); | 50 | return x * 2 + 1; |
39 | } | 51 | } |
40 | 52 | ||
41 | +/* Expand a 3-operand + env pointer operation using | 53 | +static inline int rsub_64(DisasContext *s, int x) |
42 | + * an out-of-line helper. | ||
43 | + */ | ||
44 | +static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
45 | + int rn, int rm, gen_helper_gvec_3_ptr *fn) | ||
46 | +{ | 54 | +{ |
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | 55 | + return 64 - x; |
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), cpu_env, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
51 | +} | 56 | +} |
52 | + | 57 | + |
53 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | 58 | +static inline int rsub_32(DisasContext *s, int x) |
54 | * than the 32 bit equivalent. | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | ||
57 | clear_vec_high(s, is_q, rd); | ||
58 | } | ||
59 | |||
60 | +/* AdvSIMD three same extra | ||
61 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
62 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
63 | + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
64 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
65 | + */ | ||
66 | +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | +{ | 59 | +{ |
68 | + int rd = extract32(insn, 0, 5); | 60 | + return 32 - x; |
69 | + int rn = extract32(insn, 5, 5); | ||
70 | + int opcode = extract32(insn, 11, 4); | ||
71 | + int rm = extract32(insn, 16, 5); | ||
72 | + int size = extract32(insn, 22, 2); | ||
73 | + bool u = extract32(insn, 29, 1); | ||
74 | + bool is_q = extract32(insn, 30, 1); | ||
75 | + int feature; | ||
76 | + | ||
77 | + switch (u * 16 + opcode) { | ||
78 | + case 0x10: /* SQRDMLAH (vector) */ | ||
79 | + case 0x11: /* SQRDMLSH (vector) */ | ||
80 | + if (size != 1 && size != 2) { | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + feature = ARM_FEATURE_V8_RDM; | ||
85 | + break; | ||
86 | + default: | ||
87 | + unallocated_encoding(s); | ||
88 | + return; | ||
89 | + } | ||
90 | + if (!arm_dc_feature(s, feature)) { | ||
91 | + unallocated_encoding(s); | ||
92 | + return; | ||
93 | + } | ||
94 | + if (!fp_access_check(s)) { | ||
95 | + return; | ||
96 | + } | ||
97 | + | ||
98 | + switch (opcode) { | ||
99 | + case 0x0: /* SQRDMLAH (vector) */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); | ||
103 | + break; | ||
104 | + case 2: | ||
105 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); | ||
106 | + break; | ||
107 | + default: | ||
108 | + g_assert_not_reached(); | ||
109 | + } | ||
110 | + return; | ||
111 | + | ||
112 | + case 0x1: /* SQRDMLSH (vector) */ | ||
113 | + switch (size) { | ||
114 | + case 1: | ||
115 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); | ||
116 | + break; | ||
117 | + case 2: | ||
118 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); | ||
119 | + break; | ||
120 | + default: | ||
121 | + g_assert_not_reached(); | ||
122 | + } | ||
123 | + return; | ||
124 | + | ||
125 | + default: | ||
126 | + g_assert_not_reached(); | ||
127 | + } | ||
128 | +} | 61 | +} |
129 | + | 62 | + |
130 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, | 63 | +static inline int rsub_16(DisasContext *s, int x) |
131 | int size, int rn, int rd) | ||
132 | { | ||
133 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | ||
134 | static const AArch64DecodeTable data_proc_simd[] = { | ||
135 | /* pattern , mask , fn */ | ||
136 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | ||
137 | + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, | ||
138 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | ||
139 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | ||
140 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | ||
141 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/vec_helper.c | ||
144 | +++ b/target/arm/vec_helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ | ||
146 | |||
147 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
148 | |||
149 | +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
150 | +{ | 64 | +{ |
151 | + uint64_t *d = vd + opr_sz; | 65 | + return 16 - x; |
152 | + uintptr_t i; | ||
153 | + | ||
154 | + for (i = opr_sz; i < max_sz; i += 8) { | ||
155 | + *d++ = 0; | ||
156 | + } | ||
157 | +} | 66 | +} |
158 | + | 67 | + |
159 | /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | 68 | +static inline int rsub_8(DisasContext *s, int x) |
160 | static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
161 | int16_t src2, int16_t src3) | ||
162 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
163 | return deposit32(e1, 16, 16, e2); | ||
164 | } | ||
165 | |||
166 | +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, | ||
167 | + void *ve, uint32_t desc) | ||
168 | +{ | 69 | +{ |
169 | + uintptr_t opr_sz = simd_oprsz(desc); | 70 | + return 8 - x; |
170 | + int16_t *d = vd; | ||
171 | + int16_t *n = vn; | ||
172 | + int16_t *m = vm; | ||
173 | + CPUARMState *env = ve; | ||
174 | + uintptr_t i; | ||
175 | + | ||
176 | + for (i = 0; i < opr_sz / 2; ++i) { | ||
177 | + d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); | ||
178 | + } | ||
179 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
180 | +} | 71 | +} |
181 | + | 72 | + |
182 | /* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | 73 | static inline int arm_dc_feature(DisasContext *dc, int feature) |
183 | static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | 74 | { |
184 | int16_t src2, int16_t src3) | 75 | return (dc->features & (1ULL << feature)) != 0; |
185 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | 76 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
186 | return deposit32(e1, 16, 16, e2); | 77 | index XXXXXXX..XXXXXXX 100644 |
78 | --- a/target/arm/mve.decode | ||
79 | +++ b/target/arm/mve.decode | ||
80 | @@ -XXX,XX +XXX,XX @@ | ||
81 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
82 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
83 | |||
84 | +# Right shifts are encoded as N - shift, where N is the element size in bits. | ||
85 | +%rshift_i5 16:5 !function=rsub_32 | ||
86 | +%rshift_i4 16:4 !function=rsub_16 | ||
87 | +%rshift_i3 16:3 !function=rsub_8 | ||
88 | + | ||
89 | +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
90 | + size=0 shift=%rshift_i3 | ||
91 | +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
92 | + size=1 shift=%rshift_i4 | ||
93 | +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
94 | + size=2 shift=%rshift_i5 | ||
95 | + | ||
96 | # Vector loads and stores | ||
97 | |||
98 | # Widening loads and narrowing stores: | ||
99 | @@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
100 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
101 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
102 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
103 | + | ||
104 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
105 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
106 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
107 | + | ||
108 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
109 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
110 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
111 | + | ||
112 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
113 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
114 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
115 | + | ||
116 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
117 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
118 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
119 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/target/arm/mve_helper.c | ||
122 | +++ b/target/arm/mve_helper.c | ||
123 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
124 | DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
125 | DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
126 | DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
127 | +#define DO_2SHIFT_S(OP, FN) \ | ||
128 | + DO_2SHIFT(OP##b, 1, int8_t, FN) \ | ||
129 | + DO_2SHIFT(OP##h, 2, int16_t, FN) \ | ||
130 | + DO_2SHIFT(OP##w, 4, int32_t, FN) | ||
131 | |||
132 | #define DO_2SHIFT_SAT_U(OP, FN) \ | ||
133 | DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
134 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
135 | DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
136 | |||
137 | DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
138 | +DO_2SHIFT_S(vshli_s, DO_VSHLS) | ||
139 | DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
140 | DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
141 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
142 | +DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
143 | +DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
144 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/target/arm/translate-mve.c | ||
147 | +++ b/target/arm/translate-mve.c | ||
148 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false) | ||
149 | DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
150 | DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
151 | DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
152 | +/* These right shifts use a left-shift helper with negated shift count */ | ||
153 | +DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
154 | +DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
155 | +DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
156 | +DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
157 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
158 | index XXXXXXX..XXXXXXX 100644 | ||
159 | --- a/target/arm/translate-neon.c | ||
160 | +++ b/target/arm/translate-neon.c | ||
161 | @@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x) | ||
162 | return x + 1; | ||
187 | } | 163 | } |
188 | 164 | ||
189 | +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, | 165 | -static inline int rsub_64(DisasContext *s, int x) |
190 | + void *ve, uint32_t desc) | 166 | -{ |
191 | +{ | 167 | - return 64 - x; |
192 | + uintptr_t opr_sz = simd_oprsz(desc); | 168 | -} |
193 | + int16_t *d = vd; | 169 | - |
194 | + int16_t *n = vn; | 170 | -static inline int rsub_32(DisasContext *s, int x) |
195 | + int16_t *m = vm; | 171 | -{ |
196 | + CPUARMState *env = ve; | 172 | - return 32 - x; |
197 | + uintptr_t i; | 173 | -} |
198 | + | 174 | -static inline int rsub_16(DisasContext *s, int x) |
199 | + for (i = 0; i < opr_sz / 2; ++i) { | 175 | -{ |
200 | + d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]); | 176 | - return 16 - x; |
201 | + } | 177 | -} |
202 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 178 | -static inline int rsub_8(DisasContext *s, int x) |
203 | +} | 179 | -{ |
204 | + | 180 | - return 8 - x; |
205 | /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | 181 | -} |
206 | uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | 182 | - |
207 | int32_t src2, int32_t src3) | 183 | static inline int neon_3same_fp_size(DisasContext *s, int x) |
208 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | 184 | { |
209 | return ret; | 185 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ |
210 | } | ||
211 | |||
212 | +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, | ||
213 | + void *ve, uint32_t desc) | ||
214 | +{ | ||
215 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
216 | + int32_t *d = vd; | ||
217 | + int32_t *n = vn; | ||
218 | + int32_t *m = vm; | ||
219 | + CPUARMState *env = ve; | ||
220 | + uintptr_t i; | ||
221 | + | ||
222 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
223 | + d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); | ||
224 | + } | ||
225 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
226 | +} | ||
227 | + | ||
228 | /* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
229 | uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
230 | int32_t src2, int32_t src3) | ||
231 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
232 | } | ||
233 | return ret; | ||
234 | } | ||
235 | + | ||
236 | +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
237 | + void *ve, uint32_t desc) | ||
238 | +{ | ||
239 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
240 | + int32_t *d = vd; | ||
241 | + int32_t *n = vn; | ||
242 | + int32_t *m = vm; | ||
243 | + CPUARMState *env = ve; | ||
244 | + uintptr_t i; | ||
245 | + | ||
246 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
247 | + d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); | ||
248 | + } | ||
249 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
250 | +} | ||
251 | -- | 186 | -- |
252 | 2.16.2 | 187 | 2.20.1 |
253 | 188 | ||
254 | 189 | diff view generated by jsdifflib |
1 | Model the Arm IoT Kit documented in | 1 | Implement the MVE VHLL (vector shift left long) insn. This has two |
---|---|---|---|
2 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 2 | encodings: the T1 encoding is the usual shift-by-immediate format, |
3 | 3 | and the T2 encoding is a special case where the shift count is always | |
4 | The Arm IoT Kit is a subsystem which includes a CPU and some devices, | 4 | equal to the element size. |
5 | and is intended be extended by adding extra devices to form a | ||
6 | complete system. It is used in the MPS2 board's AN505 image for the | ||
7 | Cortex-M33. | ||
8 | 5 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20180220180325.29818-19-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-10-peter.maydell@linaro.org |
12 | --- | 9 | --- |
13 | hw/arm/Makefile.objs | 1 + | 10 | target/arm/helper-mve.h | 9 +++++++ |
14 | include/hw/arm/iotkit.h | 109 ++++++++ | 11 | target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++--- |
15 | hw/arm/iotkit.c | 598 ++++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/mve_helper.c | 32 +++++++++++++++++++++++ |
16 | default-configs/arm-softmmu.mak | 1 + | 13 | target/arm/translate-mve.c | 15 +++++++++++ |
17 | 4 files changed, 709 insertions(+) | 14 | 4 files changed, 105 insertions(+), 4 deletions(-) |
18 | create mode 100644 include/hw/arm/iotkit.h | ||
19 | create mode 100644 hw/arm/iotkit.c | ||
20 | 15 | ||
21 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/Makefile.objs | 18 | --- a/target/arm/helper-mve.h |
24 | +++ b/hw/arm/Makefile.objs | 19 | +++ b/target/arm/helper-mve.h |
25 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 21 | DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | obj-$(CONFIG_MPS2) += mps2.o | 22 | DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 23 | DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | +obj-$(CONFIG_IOTKIT) += iotkit.o | 24 | + |
30 | diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h | 25 | +DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | new file mode 100644 | 26 | +DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | index XXXXXXX..XXXXXXX | 27 | +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | --- /dev/null | 28 | +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | +++ b/include/hw/arm/iotkit.h | 29 | +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/mve.decode | ||
36 | +++ b/target/arm/mve.decode | ||
35 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 38 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
37 | + * ARM IoT Kit | 39 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 |
38 | + * | 40 | |
39 | + * Copyright (c) 2018 Linaro Limited | 41 | +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 |
40 | + * Written by Peter Maydell | 42 | +@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
41 | + * | 43 | +# VSHLL encoding T2 where shift == esize |
42 | + * This program is free software; you can redistribute it and/or modify | 44 | +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \ |
43 | + * it under the terms of the GNU General Public License version 2 or | 45 | + qd=%qd qm=%qm size=0 shift=8 |
44 | + * (at your option) any later version. | 46 | +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \ |
45 | + */ | 47 | + qd=%qd qm=%qm size=1 shift=16 |
46 | + | 48 | + |
47 | +/* This is a model of the Arm IoT Kit which is documented in | 49 | # Right shifts are encoded as N - shift, where N is the element size in bits. |
48 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 50 | %rshift_i5 16:5 !function=rsub_32 |
49 | + * It contains: | 51 | %rshift_i4 16:4 !function=rsub_16 |
50 | + * a Cortex-M33 | 52 | @@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op |
51 | + * the IDAU | 53 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op |
52 | + * some timers and watchdogs | 54 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op |
53 | + * two peripheral protection controllers | 55 | |
54 | + * a memory protection controller | 56 | -VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
55 | + * a security controller | 57 | -VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
56 | + * a bus fabric which arranges that some parts of the address | 58 | +# The VSHLL T2 encoding is not a @2op pattern, but is here because it |
57 | + * space are secure and non-secure aliases of each other | 59 | +# overlaps what would be size=0b11 VMULH/VRMULH |
58 | + * | ||
59 | + * QEMU interface: | ||
60 | + * + QOM property "memory" is a MemoryRegion containing the devices provided | ||
61 | + * by the board model. | ||
62 | + * + QOM property "MAINCLK" is the frequency of the main system clock | ||
63 | + * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts | ||
64 | + * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which | ||
65 | + * are wired to the NVIC lines 32 .. n+32 | ||
66 | + * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit | ||
67 | + * might provide: | ||
68 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
69 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
70 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
71 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
72 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
73 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
74 | + * might provide: | ||
75 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
76 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
77 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
78 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
79 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
80 | + */ | ||
81 | + | ||
82 | +#ifndef IOTKIT_H | ||
83 | +#define IOTKIT_H | ||
84 | + | ||
85 | +#include "hw/sysbus.h" | ||
86 | +#include "hw/arm/armv7m.h" | ||
87 | +#include "hw/misc/iotkit-secctl.h" | ||
88 | +#include "hw/misc/tz-ppc.h" | ||
89 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
90 | +#include "hw/misc/unimp.h" | ||
91 | +#include "hw/or-irq.h" | ||
92 | +#include "hw/core/split-irq.h" | ||
93 | + | ||
94 | +#define TYPE_IOTKIT "iotkit" | ||
95 | +#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) | ||
96 | + | ||
97 | +/* We have an IRQ splitter and an OR gate input for each external PPC | ||
98 | + * and the 2 internal PPCs | ||
99 | + */ | ||
100 | +#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) | ||
101 | +#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) | ||
102 | + | ||
103 | +typedef struct IoTKit { | ||
104 | + /*< private >*/ | ||
105 | + SysBusDevice parent_obj; | ||
106 | + | ||
107 | + /*< public >*/ | ||
108 | + ARMv7MState armv7m; | ||
109 | + IoTKitSecCtl secctl; | ||
110 | + TZPPC apb_ppc0; | ||
111 | + TZPPC apb_ppc1; | ||
112 | + CMSDKAPBTIMER timer0; | ||
113 | + CMSDKAPBTIMER timer1; | ||
114 | + qemu_or_irq ppc_irq_orgate; | ||
115 | + SplitIRQ sec_resp_splitter; | ||
116 | + SplitIRQ ppc_irq_splitter[NUM_PPCS]; | ||
117 | + | ||
118 | + UnimplementedDeviceState dualtimer; | ||
119 | + UnimplementedDeviceState s32ktimer; | ||
120 | + | ||
121 | + MemoryRegion container; | ||
122 | + MemoryRegion alias1; | ||
123 | + MemoryRegion alias2; | ||
124 | + MemoryRegion alias3; | ||
125 | + MemoryRegion sram0; | ||
126 | + | ||
127 | + qemu_irq *exp_irqs; | ||
128 | + qemu_irq ppc0_irq; | ||
129 | + qemu_irq ppc1_irq; | ||
130 | + qemu_irq sec_resp_cfg; | ||
131 | + qemu_irq sec_resp_cfg_in; | ||
132 | + qemu_irq nsc_cfg_in; | ||
133 | + | ||
134 | + qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; | ||
135 | + | ||
136 | + uint32_t nsccfg; | ||
137 | + | ||
138 | + /* Properties */ | ||
139 | + MemoryRegion *board_memory; | ||
140 | + uint32_t exp_numirq; | ||
141 | + uint32_t mainclk_frq; | ||
142 | +} IoTKit; | ||
143 | + | ||
144 | +#endif | ||
145 | diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c | ||
146 | new file mode 100644 | ||
147 | index XXXXXXX..XXXXXXX | ||
148 | --- /dev/null | ||
149 | +++ b/hw/arm/iotkit.c | ||
150 | @@ -XXX,XX +XXX,XX @@ | ||
151 | +/* | ||
152 | + * Arm IoT Kit | ||
153 | + * | ||
154 | + * Copyright (c) 2018 Linaro Limited | ||
155 | + * Written by Peter Maydell | ||
156 | + * | ||
157 | + * This program is free software; you can redistribute it and/or modify | ||
158 | + * it under the terms of the GNU General Public License version 2 or | ||
159 | + * (at your option) any later version. | ||
160 | + */ | ||
161 | + | ||
162 | +#include "qemu/osdep.h" | ||
163 | +#include "qemu/log.h" | ||
164 | +#include "qapi/error.h" | ||
165 | +#include "trace.h" | ||
166 | +#include "hw/sysbus.h" | ||
167 | +#include "hw/registerfields.h" | ||
168 | +#include "hw/arm/iotkit.h" | ||
169 | +#include "hw/misc/unimp.h" | ||
170 | +#include "hw/arm/arm.h" | ||
171 | + | ||
172 | +/* Create an alias region of @size bytes starting at @base | ||
173 | + * which mirrors the memory starting at @orig. | ||
174 | + */ | ||
175 | +static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, | ||
176 | + hwaddr base, hwaddr size, hwaddr orig) | ||
177 | +{ | 60 | +{ |
178 | + memory_region_init_alias(mr, NULL, name, &s->container, orig, size); | 61 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b |
179 | + /* The alias is even lower priority than unimplemented_device regions */ | 62 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h |
180 | + memory_region_add_subregion_overlap(&s->container, base, mr, -1500); | 63 | |
64 | -VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
65 | -VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
66 | + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
181 | +} | 67 | +} |
182 | + | 68 | + |
183 | +static void init_sysbus_child(Object *parent, const char *childname, | ||
184 | + void *child, size_t childsize, | ||
185 | + const char *childtype) | ||
186 | +{ | 69 | +{ |
187 | + object_initialize(child, childsize, childtype); | 70 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b |
188 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | 71 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h |
189 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | 72 | + |
73 | + VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
190 | +} | 74 | +} |
191 | + | 75 | + |
192 | +static void irq_status_forwarder(void *opaque, int n, int level) | ||
193 | +{ | 76 | +{ |
194 | + qemu_irq destirq = opaque; | 77 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b |
78 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
195 | + | 79 | + |
196 | + qemu_set_irq(destirq, level); | 80 | + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
197 | +} | 81 | +} |
198 | + | 82 | + |
199 | +static void nsccfg_handler(void *opaque, int n, int level) | ||
200 | +{ | 83 | +{ |
201 | + IoTKit *s = IOTKIT(opaque); | 84 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b |
85 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
202 | + | 86 | + |
203 | + s->nsccfg = level; | 87 | + VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
204 | +} | 88 | +} |
89 | |||
90 | VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
91 | VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
92 | @@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
93 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
94 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
95 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
205 | + | 96 | + |
206 | +static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) | 97 | +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file |
207 | +{ | 98 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b |
208 | + /* Each of the 4 AHB and 4 APB PPCs that might be present in a | 99 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h |
209 | + * system using the IoTKit has a collection of control lines which | ||
210 | + * are provided by the security controller and which we want to | ||
211 | + * expose as control lines on the IoTKit device itself, so the | ||
212 | + * code using the IoTKit can wire them up to the PPCs. | ||
213 | + */ | ||
214 | + SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; | ||
215 | + DeviceState *iotkitdev = DEVICE(s); | ||
216 | + DeviceState *dev_secctl = DEVICE(&s->secctl); | ||
217 | + DeviceState *dev_splitter = DEVICE(splitter); | ||
218 | + char *name; | ||
219 | + | 100 | + |
220 | + name = g_strdup_printf("%s_nonsec", ppcname); | 101 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b |
221 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | 102 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h |
222 | + g_free(name); | ||
223 | + name = g_strdup_printf("%s_ap", ppcname); | ||
224 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
225 | + g_free(name); | ||
226 | + name = g_strdup_printf("%s_irq_enable", ppcname); | ||
227 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
228 | + g_free(name); | ||
229 | + name = g_strdup_printf("%s_irq_clear", ppcname); | ||
230 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
231 | + g_free(name); | ||
232 | + | 103 | + |
233 | + /* irq_status is a little more tricky, because we need to | 104 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b |
234 | + * split it so we can send it both to the security controller | 105 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
235 | + * and to our OR gate for the NVIC interrupt line. | ||
236 | + * Connect up the splitter's outputs, and create a GPIO input | ||
237 | + * which will pass the line state to the input splitter. | ||
238 | + */ | ||
239 | + name = g_strdup_printf("%s_irq_status", ppcname); | ||
240 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
241 | + qdev_get_gpio_in_named(dev_secctl, | ||
242 | + name, 0)); | ||
243 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
244 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); | ||
245 | + s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); | ||
246 | + qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, | ||
247 | + s->irq_status_in[ppcnum], name, 1); | ||
248 | + g_free(name); | ||
249 | +} | ||
250 | + | 106 | + |
251 | +static void iotkit_forward_sec_resp_cfg(IoTKit *s) | 107 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b |
252 | +{ | 108 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
253 | + /* Forward the 3rd output from the splitter device as a | 109 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
254 | + * named GPIO output of the iotkit object. | 110 | index XXXXXXX..XXXXXXX 100644 |
255 | + */ | 111 | --- a/target/arm/mve_helper.c |
256 | + DeviceState *dev = DEVICE(s); | 112 | +++ b/target/arm/mve_helper.c |
257 | + DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); | 113 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) |
114 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
115 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
116 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
258 | + | 117 | + |
259 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | 118 | +/* |
260 | + s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, | 119 | + * Long shifts taking half-sized inputs from top or bottom of the input |
261 | + s->sec_resp_cfg, 1); | 120 | + * vector and producing a double-width result. ESIZE, TYPE are for |
262 | + qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); | 121 | + * the input, and LESIZE, LTYPE for the output. |
263 | +} | 122 | + * Unlike the normal shift helpers, we do not handle negative shift counts, |
264 | + | 123 | + * because the long shift is strictly left-only. |
265 | +static void iotkit_init(Object *obj) | 124 | + */ |
266 | +{ | 125 | +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ |
267 | + IoTKit *s = IOTKIT(obj); | 126 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
268 | + int i; | 127 | + void *vm, uint32_t shift) \ |
269 | + | 128 | + { \ |
270 | + memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); | 129 | + LTYPE *d = vd; \ |
271 | + | 130 | + TYPE *m = vm; \ |
272 | + init_sysbus_child(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), | 131 | + uint16_t mask = mve_element_mask(env); \ |
273 | + TYPE_ARMV7M); | 132 | + unsigned le; \ |
274 | + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", | 133 | + assert(shift <= 16); \ |
275 | + ARM_CPU_TYPE_NAME("cortex-m33")); | 134 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ |
276 | + | 135 | + LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ |
277 | + init_sysbus_child(obj, "secctl", &s->secctl, sizeof(s->secctl), | 136 | + mergemask(&d[H##LESIZE(le)], r, mask); \ |
278 | + TYPE_IOTKIT_SECCTL); | 137 | + } \ |
279 | + init_sysbus_child(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), | 138 | + mve_advance_vpt(env); \ |
280 | + TYPE_TZ_PPC); | ||
281 | + init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), | ||
282 | + TYPE_TZ_PPC); | ||
283 | + init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0), | ||
284 | + TYPE_CMSDK_APB_TIMER); | ||
285 | + init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1), | ||
286 | + TYPE_CMSDK_APB_TIMER); | ||
287 | + init_sysbus_child(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), | ||
288 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
289 | + object_initialize(&s->ppc_irq_orgate, sizeof(s->ppc_irq_orgate), | ||
290 | + TYPE_OR_IRQ); | ||
291 | + object_property_add_child(obj, "ppc-irq-orgate", | ||
292 | + OBJECT(&s->ppc_irq_orgate), &error_abort); | ||
293 | + object_initialize(&s->sec_resp_splitter, sizeof(s->sec_resp_splitter), | ||
294 | + TYPE_SPLIT_IRQ); | ||
295 | + object_property_add_child(obj, "sec-resp-splitter", | ||
296 | + OBJECT(&s->sec_resp_splitter), &error_abort); | ||
297 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
298 | + char *name = g_strdup_printf("ppc-irq-splitter-%d", i); | ||
299 | + SplitIRQ *splitter = &s->ppc_irq_splitter[i]; | ||
300 | + | ||
301 | + object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ); | ||
302 | + object_property_add_child(obj, name, OBJECT(splitter), &error_abort); | ||
303 | + } | ||
304 | + init_sysbus_child(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), | ||
305 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
306 | +} | ||
307 | + | ||
308 | +static void iotkit_exp_irq(void *opaque, int n, int level) | ||
309 | +{ | ||
310 | + IoTKit *s = IOTKIT(opaque); | ||
311 | + | ||
312 | + qemu_set_irq(s->exp_irqs[n], level); | ||
313 | +} | ||
314 | + | ||
315 | +static void iotkit_realize(DeviceState *dev, Error **errp) | ||
316 | +{ | ||
317 | + IoTKit *s = IOTKIT(dev); | ||
318 | + int i; | ||
319 | + MemoryRegion *mr; | ||
320 | + Error *err = NULL; | ||
321 | + SysBusDevice *sbd_apb_ppc0; | ||
322 | + SysBusDevice *sbd_secctl; | ||
323 | + DeviceState *dev_apb_ppc0; | ||
324 | + DeviceState *dev_apb_ppc1; | ||
325 | + DeviceState *dev_secctl; | ||
326 | + DeviceState *dev_splitter; | ||
327 | + | ||
328 | + if (!s->board_memory) { | ||
329 | + error_setg(errp, "memory property was not set"); | ||
330 | + return; | ||
331 | + } | 139 | + } |
332 | + | 140 | + |
333 | + if (!s->mainclk_frq) { | 141 | +#define DO_VSHLL_ALL(OP, TOP) \ |
334 | + error_setg(errp, "MAINCLK property was not set"); | 142 | + DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ |
335 | + return; | 143 | + DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ |
144 | + DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ | ||
145 | + DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ | ||
146 | + | ||
147 | +DO_VSHLL_ALL(vshllb, false) | ||
148 | +DO_VSHLL_ALL(vshllt, true) | ||
149 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/target/arm/translate-mve.c | ||
152 | +++ b/target/arm/translate-mve.c | ||
153 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
154 | DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
155 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
156 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
157 | + | ||
158 | +#define DO_VSHLL(INSN, FN) \ | ||
159 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
160 | + { \ | ||
161 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
162 | + gen_helper_mve_##FN##b, \ | ||
163 | + gen_helper_mve_##FN##h, \ | ||
164 | + }; \ | ||
165 | + return do_2shift(s, a, fns[a->size], false); \ | ||
336 | + } | 166 | + } |
337 | + | 167 | + |
338 | + /* Handling of which devices should be available only to secure | 168 | +DO_VSHLL(VSHLL_BS, vshllbs) |
339 | + * code is usually done differently for M profile than for A profile. | 169 | +DO_VSHLL(VSHLL_BU, vshllbu) |
340 | + * Instead of putting some devices only into the secure address space, | 170 | +DO_VSHLL(VSHLL_TS, vshllts) |
341 | + * devices exist in both address spaces but with hard-wired security | 171 | +DO_VSHLL(VSHLL_TU, vshlltu) |
342 | + * permissions that will cause the CPU to fault for non-secure accesses. | ||
343 | + * | ||
344 | + * The IoTKit has an IDAU (Implementation Defined Access Unit), | ||
345 | + * which specifies hard-wired security permissions for different | ||
346 | + * areas of the physical address space. For the IoTKit IDAU, the | ||
347 | + * top 4 bits of the physical address are the IDAU region ID, and | ||
348 | + * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS | ||
349 | + * region, otherwise it is an S region. | ||
350 | + * | ||
351 | + * The various devices and RAMs are generally all mapped twice, | ||
352 | + * once into a region that the IDAU defines as secure and once | ||
353 | + * into a non-secure region. They sit behind either a Memory | ||
354 | + * Protection Controller (for RAM) or a Peripheral Protection | ||
355 | + * Controller (for devices), which allow a more fine grained | ||
356 | + * configuration of whether non-secure accesses are permitted. | ||
357 | + * | ||
358 | + * (The other place that guest software can configure security | ||
359 | + * permissions is in the architected SAU (Security Attribution | ||
360 | + * Unit), which is entirely inside the CPU. The IDAU can upgrade | ||
361 | + * the security attributes for a region to more restrictive than | ||
362 | + * the SAU specifies, but cannot downgrade them.) | ||
363 | + * | ||
364 | + * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff | ||
365 | + * 0x20000000..0x2007ffff 32KB FPGA block RAM | ||
366 | + * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff | ||
367 | + * 0x40000000..0x4000ffff base peripheral region 1 | ||
368 | + * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) | ||
369 | + * 0x40020000..0x4002ffff system control element peripherals | ||
370 | + * 0x40080000..0x400fffff base peripheral region 2 | ||
371 | + * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff | ||
372 | + */ | ||
373 | + | ||
374 | + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | ||
375 | + | ||
376 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32); | ||
377 | + /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 | ||
378 | + * register in the IoT Kit System Control Register block, and the | ||
379 | + * initial value of that is in turn specifiable by the FPGA that | ||
380 | + * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, | ||
381 | + * and simply set the CPU's init-svtor to the IoT Kit default value. | ||
382 | + */ | ||
383 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); | ||
384 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), | ||
385 | + "memory", &err); | ||
386 | + if (err) { | ||
387 | + error_propagate(errp, err); | ||
388 | + return; | ||
389 | + } | ||
390 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); | ||
391 | + if (err) { | ||
392 | + error_propagate(errp, err); | ||
393 | + return; | ||
394 | + } | ||
395 | + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | ||
396 | + if (err) { | ||
397 | + error_propagate(errp, err); | ||
398 | + return; | ||
399 | + } | ||
400 | + | ||
401 | + /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ | ||
402 | + s->exp_irqs = g_new(qemu_irq, s->exp_numirq); | ||
403 | + for (i = 0; i < s->exp_numirq; i++) { | ||
404 | + s->exp_irqs[i] = qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); | ||
405 | + } | ||
406 | + qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); | ||
407 | + | ||
408 | + /* Set up the big aliases first */ | ||
409 | + make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); | ||
410 | + make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); | ||
411 | + /* The 0x50000000..0x5fffffff region is not a pure alias: it has | ||
412 | + * a few extra devices that only appear there (generally the | ||
413 | + * control interfaces for the protection controllers). | ||
414 | + * We implement this by mapping those devices over the top of this | ||
415 | + * alias MR at a higher priority. | ||
416 | + */ | ||
417 | + make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); | ||
418 | + | ||
419 | + /* This RAM should be behind a Memory Protection Controller, but we | ||
420 | + * don't implement that yet. | ||
421 | + */ | ||
422 | + memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err); | ||
423 | + if (err) { | ||
424 | + error_propagate(errp, err); | ||
425 | + return; | ||
426 | + } | ||
427 | + memory_region_add_subregion(&s->container, 0x20000000, &s->sram0); | ||
428 | + | ||
429 | + /* Security controller */ | ||
430 | + object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); | ||
431 | + if (err) { | ||
432 | + error_propagate(errp, err); | ||
433 | + return; | ||
434 | + } | ||
435 | + sbd_secctl = SYS_BUS_DEVICE(&s->secctl); | ||
436 | + dev_secctl = DEVICE(&s->secctl); | ||
437 | + sysbus_mmio_map(sbd_secctl, 0, 0x50080000); | ||
438 | + sysbus_mmio_map(sbd_secctl, 1, 0x40080000); | ||
439 | + | ||
440 | + s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); | ||
441 | + qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); | ||
442 | + | ||
443 | + /* The sec_resp_cfg output from the security controller must be split into | ||
444 | + * multiple lines, one for each of the PPCs within the IoTKit and one | ||
445 | + * that will be an output from the IoTKit to the system. | ||
446 | + */ | ||
447 | + object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, | ||
448 | + "num-lines", &err); | ||
449 | + if (err) { | ||
450 | + error_propagate(errp, err); | ||
451 | + return; | ||
452 | + } | ||
453 | + object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, | ||
454 | + "realized", &err); | ||
455 | + if (err) { | ||
456 | + error_propagate(errp, err); | ||
457 | + return; | ||
458 | + } | ||
459 | + dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
460 | + qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, | ||
461 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
462 | + | ||
463 | + /* Devices behind APB PPC0: | ||
464 | + * 0x40000000: timer0 | ||
465 | + * 0x40001000: timer1 | ||
466 | + * 0x40002000: dual timer | ||
467 | + * We must configure and realize each downstream device and connect | ||
468 | + * it to the appropriate PPC port; then we can realize the PPC and | ||
469 | + * map its upstream ends to the right place in the container. | ||
470 | + */ | ||
471 | + qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); | ||
472 | + object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); | ||
473 | + if (err) { | ||
474 | + error_propagate(errp, err); | ||
475 | + return; | ||
476 | + } | ||
477 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, | ||
478 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
479 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); | ||
480 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); | ||
481 | + if (err) { | ||
482 | + error_propagate(errp, err); | ||
483 | + return; | ||
484 | + } | ||
485 | + | ||
486 | + qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); | ||
487 | + object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); | ||
488 | + if (err) { | ||
489 | + error_propagate(errp, err); | ||
490 | + return; | ||
491 | + } | ||
492 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, | ||
493 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
494 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); | ||
495 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); | ||
496 | + if (err) { | ||
497 | + error_propagate(errp, err); | ||
498 | + return; | ||
499 | + } | ||
500 | + | ||
501 | + qdev_prop_set_string(DEVICE(&s->dualtimer), "name", "Dual timer"); | ||
502 | + qdev_prop_set_uint64(DEVICE(&s->dualtimer), "size", 0x1000); | ||
503 | + object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); | ||
504 | + if (err) { | ||
505 | + error_propagate(errp, err); | ||
506 | + return; | ||
507 | + } | ||
508 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); | ||
509 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); | ||
510 | + if (err) { | ||
511 | + error_propagate(errp, err); | ||
512 | + return; | ||
513 | + } | ||
514 | + | ||
515 | + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); | ||
516 | + if (err) { | ||
517 | + error_propagate(errp, err); | ||
518 | + return; | ||
519 | + } | ||
520 | + | ||
521 | + sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); | ||
522 | + dev_apb_ppc0 = DEVICE(&s->apb_ppc0); | ||
523 | + | ||
524 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); | ||
525 | + memory_region_add_subregion(&s->container, 0x40000000, mr); | ||
526 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); | ||
527 | + memory_region_add_subregion(&s->container, 0x40001000, mr); | ||
528 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); | ||
529 | + memory_region_add_subregion(&s->container, 0x40002000, mr); | ||
530 | + for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { | ||
531 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, | ||
532 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
533 | + "cfg_nonsec", i)); | ||
534 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, | ||
535 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
536 | + "cfg_ap", i)); | ||
537 | + } | ||
538 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, | ||
539 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
540 | + "irq_enable", 0)); | ||
541 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, | ||
542 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
543 | + "irq_clear", 0)); | ||
544 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
545 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
546 | + "cfg_sec_resp", 0)); | ||
547 | + | ||
548 | + /* All the PPC irq lines (from the 2 internal PPCs and the 8 external | ||
549 | + * ones) are sent individually to the security controller, and also | ||
550 | + * ORed together to give a single combined PPC interrupt to the NVIC. | ||
551 | + */ | ||
552 | + object_property_set_int(OBJECT(&s->ppc_irq_orgate), | ||
553 | + NUM_PPCS, "num-lines", &err); | ||
554 | + if (err) { | ||
555 | + error_propagate(errp, err); | ||
556 | + return; | ||
557 | + } | ||
558 | + object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, | ||
559 | + "realized", &err); | ||
560 | + if (err) { | ||
561 | + error_propagate(errp, err); | ||
562 | + return; | ||
563 | + } | ||
564 | + qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, | ||
565 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); | ||
566 | + | ||
567 | + /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ | ||
568 | + | ||
569 | + /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */ | ||
570 | + /* Devices behind APB PPC1: | ||
571 | + * 0x4002f000: S32K timer | ||
572 | + */ | ||
573 | + qdev_prop_set_string(DEVICE(&s->s32ktimer), "name", "S32KTIMER"); | ||
574 | + qdev_prop_set_uint64(DEVICE(&s->s32ktimer), "size", 0x1000); | ||
575 | + object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); | ||
576 | + if (err) { | ||
577 | + error_propagate(errp, err); | ||
578 | + return; | ||
579 | + } | ||
580 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); | ||
581 | + object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); | ||
582 | + if (err) { | ||
583 | + error_propagate(errp, err); | ||
584 | + return; | ||
585 | + } | ||
586 | + | ||
587 | + object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); | ||
588 | + if (err) { | ||
589 | + error_propagate(errp, err); | ||
590 | + return; | ||
591 | + } | ||
592 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); | ||
593 | + memory_region_add_subregion(&s->container, 0x4002f000, mr); | ||
594 | + | ||
595 | + dev_apb_ppc1 = DEVICE(&s->apb_ppc1); | ||
596 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, | ||
597 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
598 | + "cfg_nonsec", 0)); | ||
599 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, | ||
600 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
601 | + "cfg_ap", 0)); | ||
602 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, | ||
603 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
604 | + "irq_enable", 0)); | ||
605 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, | ||
606 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
607 | + "irq_clear", 0)); | ||
608 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
609 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
610 | + "cfg_sec_resp", 0)); | ||
611 | + | ||
612 | + /* Using create_unimplemented_device() maps the stub into the | ||
613 | + * system address space rather than into our container, but the | ||
614 | + * overall effect to the guest is the same. | ||
615 | + */ | ||
616 | + create_unimplemented_device("SYSINFO", 0x40020000, 0x1000); | ||
617 | + | ||
618 | + create_unimplemented_device("SYSCONTROL", 0x50021000, 0x1000); | ||
619 | + create_unimplemented_device("S32KWATCHDOG", 0x5002e000, 0x1000); | ||
620 | + | ||
621 | + /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ | ||
622 | + | ||
623 | + create_unimplemented_device("NS watchdog", 0x40081000, 0x1000); | ||
624 | + create_unimplemented_device("S watchdog", 0x50081000, 0x1000); | ||
625 | + | ||
626 | + create_unimplemented_device("SRAM0 MPC", 0x50083000, 0x1000); | ||
627 | + | ||
628 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
629 | + Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); | ||
630 | + | ||
631 | + object_property_set_int(splitter, 2, "num-lines", &err); | ||
632 | + if (err) { | ||
633 | + error_propagate(errp, err); | ||
634 | + return; | ||
635 | + } | ||
636 | + object_property_set_bool(splitter, true, "realized", &err); | ||
637 | + if (err) { | ||
638 | + error_propagate(errp, err); | ||
639 | + return; | ||
640 | + } | ||
641 | + } | ||
642 | + | ||
643 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
644 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
645 | + | ||
646 | + iotkit_forward_ppc(s, ppcname, i); | ||
647 | + g_free(ppcname); | ||
648 | + } | ||
649 | + | ||
650 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
651 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
652 | + | ||
653 | + iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); | ||
654 | + g_free(ppcname); | ||
655 | + } | ||
656 | + | ||
657 | + for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { | ||
658 | + /* Wire up IRQ splitter for internal PPCs */ | ||
659 | + DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); | ||
660 | + char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", | ||
661 | + i - NUM_EXTERNAL_PPCS); | ||
662 | + TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; | ||
663 | + | ||
664 | + qdev_connect_gpio_out(devs, 0, | ||
665 | + qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); | ||
666 | + qdev_connect_gpio_out(devs, 1, | ||
667 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); | ||
668 | + qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, | ||
669 | + qdev_get_gpio_in(devs, 0)); | ||
670 | + } | ||
671 | + | ||
672 | + iotkit_forward_sec_resp_cfg(s); | ||
673 | + | ||
674 | + system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; | ||
675 | +} | ||
676 | + | ||
677 | +static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, | ||
678 | + int *iregion, bool *exempt, bool *ns, bool *nsc) | ||
679 | +{ | ||
680 | + /* For IoTKit systems the IDAU responses are simple logical functions | ||
681 | + * of the address bits. The NSC attribute is guest-adjustable via the | ||
682 | + * NSCCFG register in the security controller. | ||
683 | + */ | ||
684 | + IoTKit *s = IOTKIT(ii); | ||
685 | + int region = extract32(address, 28, 4); | ||
686 | + | ||
687 | + *ns = !(region & 1); | ||
688 | + *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); | ||
689 | + /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | ||
690 | + *exempt = (address & 0xeff00000) == 0xe0000000; | ||
691 | + *iregion = region; | ||
692 | +} | ||
693 | + | ||
694 | +static const VMStateDescription iotkit_vmstate = { | ||
695 | + .name = "iotkit", | ||
696 | + .version_id = 1, | ||
697 | + .minimum_version_id = 1, | ||
698 | + .fields = (VMStateField[]) { | ||
699 | + VMSTATE_UINT32(nsccfg, IoTKit), | ||
700 | + VMSTATE_END_OF_LIST() | ||
701 | + } | ||
702 | +}; | ||
703 | + | ||
704 | +static Property iotkit_properties[] = { | ||
705 | + DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, | ||
706 | + MemoryRegion *), | ||
707 | + DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), | ||
708 | + DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), | ||
709 | + DEFINE_PROP_END_OF_LIST() | ||
710 | +}; | ||
711 | + | ||
712 | +static void iotkit_reset(DeviceState *dev) | ||
713 | +{ | ||
714 | + IoTKit *s = IOTKIT(dev); | ||
715 | + | ||
716 | + s->nsccfg = 0; | ||
717 | +} | ||
718 | + | ||
719 | +static void iotkit_class_init(ObjectClass *klass, void *data) | ||
720 | +{ | ||
721 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
722 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); | ||
723 | + | ||
724 | + dc->realize = iotkit_realize; | ||
725 | + dc->vmsd = &iotkit_vmstate; | ||
726 | + dc->props = iotkit_properties; | ||
727 | + dc->reset = iotkit_reset; | ||
728 | + iic->check = iotkit_idau_check; | ||
729 | +} | ||
730 | + | ||
731 | +static const TypeInfo iotkit_info = { | ||
732 | + .name = TYPE_IOTKIT, | ||
733 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
734 | + .instance_size = sizeof(IoTKit), | ||
735 | + .instance_init = iotkit_init, | ||
736 | + .class_init = iotkit_class_init, | ||
737 | + .interfaces = (InterfaceInfo[]) { | ||
738 | + { TYPE_IDAU_INTERFACE }, | ||
739 | + { } | ||
740 | + } | ||
741 | +}; | ||
742 | + | ||
743 | +static void iotkit_register_types(void) | ||
744 | +{ | ||
745 | + type_register_static(&iotkit_info); | ||
746 | +} | ||
747 | + | ||
748 | +type_init(iotkit_register_types); | ||
749 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
750 | index XXXXXXX..XXXXXXX 100644 | ||
751 | --- a/default-configs/arm-softmmu.mak | ||
752 | +++ b/default-configs/arm-softmmu.mak | ||
753 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
754 | CONFIG_MPS2_SCC=y | ||
755 | |||
756 | CONFIG_TZ_PPC=y | ||
757 | +CONFIG_IOTKIT=y | ||
758 | CONFIG_IOTKIT_SECCTL=y | ||
759 | |||
760 | CONFIG_VERSATILE_PCI=y | ||
761 | -- | 172 | -- |
762 | 2.16.2 | 173 | 2.20.1 |
763 | 174 | ||
764 | 175 | diff view generated by jsdifflib |
1 | Define a new board model for the MPS2 with an AN505 FPGA image | 1 | Implement the MVE VSRI and VSLI insns, which perform a |
---|---|---|---|
2 | containing a Cortex-M33. Since the FPGA images for TrustZone | 2 | shift-and-insert operation. |
3 | cores (AN505, and the similar AN519 for Cortex-M23) have a | ||
4 | significantly different layout of devices to the non-TrustZone | ||
5 | images, we use a new source file rather than shoehorning them | ||
6 | into the existing mps2.c. | ||
7 | 3 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-20-peter.maydell@linaro.org | 6 | Message-id: 20210628135835.6690-11-peter.maydell@linaro.org |
11 | --- | 7 | --- |
12 | hw/arm/Makefile.objs | 1 + | 8 | target/arm/helper-mve.h | 8 ++++++++ |
13 | hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++ | 9 | target/arm/mve.decode | 9 ++++++++ |
14 | 2 files changed, 504 insertions(+) | 10 | target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++ |
15 | create mode 100644 hw/arm/mps2-tz.c | 11 | target/arm/translate-mve.c | 3 +++ |
12 | 4 files changed, 62 insertions(+) | ||
16 | 13 | ||
17 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/Makefile.objs | 16 | --- a/target/arm/helper-mve.h |
20 | +++ b/hw/arm/Makefile.objs | 17 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 19 | DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 20 | DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | obj-$(CONFIG_MPS2) += mps2.o | 21 | DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | +obj-$(CONFIG_MPS2) += mps2-tz.o | ||
26 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | ||
27 | obj-$(CONFIG_IOTKIT) += iotkit.o | ||
28 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/hw/arm/mps2-tz.c | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * ARM V2M MPS2 board emulation, trustzone aware FPGA images | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Linaro Limited | ||
38 | + * Written by Peter Maydell | ||
39 | + * | ||
40 | + * This program is free software; you can redistribute it and/or modify | ||
41 | + * it under the terms of the GNU General Public License version 2 or | ||
42 | + * (at your option) any later version. | ||
43 | + */ | ||
44 | + | 22 | + |
45 | +/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | 23 | +DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
46 | + * FPGA but is otherwise the same as the 2). Since the CPU itself | 24 | +DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
47 | + * and most of the devices are in the FPGA, the details of the board | 25 | +DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
48 | + * as seen by the guest depend significantly on the FPGA image. | ||
49 | + * This source file covers the following FPGA images, for TrustZone cores: | ||
50 | + * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 | ||
51 | + * | ||
52 | + * Links to the TRM for the board itself and to the various Application | ||
53 | + * Notes which document the FPGA images can be found here: | ||
54 | + * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | ||
55 | + * | ||
56 | + * Board TRM: | ||
57 | + * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | ||
58 | + * Application Note AN505: | ||
59 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
60 | + * | ||
61 | + * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | ||
62 | + * (ARM ECM0601256) for the details of some of the device layout: | ||
63 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
64 | + */ | ||
65 | + | 26 | + |
66 | +#include "qemu/osdep.h" | 27 | +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
67 | +#include "qapi/error.h" | 28 | +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
68 | +#include "qemu/error-report.h" | 29 | +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
69 | +#include "hw/arm/arm.h" | 30 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
70 | +#include "hw/arm/armv7m.h" | 31 | index XXXXXXX..XXXXXXX 100644 |
71 | +#include "hw/or-irq.h" | 32 | --- a/target/arm/mve.decode |
72 | +#include "hw/boards.h" | 33 | +++ b/target/arm/mve.decode |
73 | +#include "exec/address-spaces.h" | 34 | @@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
74 | +#include "sysemu/sysemu.h" | 35 | |
75 | +#include "hw/misc/unimp.h" | 36 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b |
76 | +#include "hw/char/cmsdk-apb-uart.h" | 37 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
77 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
78 | +#include "hw/misc/mps2-scc.h" | ||
79 | +#include "hw/misc/mps2-fpgaio.h" | ||
80 | +#include "hw/arm/iotkit.h" | ||
81 | +#include "hw/devices.h" | ||
82 | +#include "net/net.h" | ||
83 | +#include "hw/core/split-irq.h" | ||
84 | + | 38 | + |
85 | +typedef enum MPS2TZFPGAType { | 39 | +# Shift-and-insert |
86 | + FPGA_AN505, | 40 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b |
87 | +} MPS2TZFPGAType; | 41 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h |
42 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
88 | + | 43 | + |
89 | +typedef struct { | 44 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b |
90 | + MachineClass parent; | 45 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h |
91 | + MPS2TZFPGAType fpga_type; | 46 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w |
92 | + uint32_t scc_id; | 47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
93 | +} MPS2TZMachineClass; | 48 | index XXXXXXX..XXXXXXX 100644 |
94 | + | 49 | --- a/target/arm/mve_helper.c |
95 | +typedef struct { | 50 | +++ b/target/arm/mve_helper.c |
96 | + MachineState parent; | 51 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) |
97 | + | 52 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) |
98 | + IoTKit iotkit; | 53 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) |
99 | + MemoryRegion psram; | 54 | |
100 | + MemoryRegion ssram1; | 55 | +/* Shift-and-insert; we always work with 64 bits at a time */ |
101 | + MemoryRegion ssram1_m; | 56 | +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ |
102 | + MemoryRegion ssram23; | 57 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
103 | + MPS2SCC scc; | 58 | + void *vm, uint32_t shift) \ |
104 | + MPS2FPGAIO fpgaio; | 59 | + { \ |
105 | + TZPPC ppc[5]; | 60 | + uint64_t *d = vd, *m = vm; \ |
106 | + UnimplementedDeviceState ssram_mpc[3]; | 61 | + uint16_t mask; \ |
107 | + UnimplementedDeviceState spi[5]; | 62 | + uint64_t shiftmask; \ |
108 | + UnimplementedDeviceState i2c[4]; | 63 | + unsigned e; \ |
109 | + UnimplementedDeviceState i2s_audio; | 64 | + if (shift == 0 || shift == ESIZE * 8) { \ |
110 | + UnimplementedDeviceState gpio[5]; | 65 | + /* \ |
111 | + UnimplementedDeviceState dma[4]; | 66 | + * Only VSLI can shift by 0; only VSRI can shift by <dt>. \ |
112 | + UnimplementedDeviceState gfx; | 67 | + * The generic logic would give the right answer for 0 but \ |
113 | + CMSDKAPBUART uart[5]; | 68 | + * fails for <dt>. \ |
114 | + SplitIRQ sec_resp_splitter; | 69 | + */ \ |
115 | + qemu_or_irq uart_irq_orgate; | 70 | + goto done; \ |
116 | +} MPS2TZMachineState; | 71 | + } \ |
117 | + | 72 | + assert(shift < ESIZE * 8); \ |
118 | +#define TYPE_MPS2TZ_MACHINE "mps2tz" | 73 | + mask = mve_element_mask(env); \ |
119 | +#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") | 74 | + /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ |
120 | + | 75 | + shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ |
121 | +#define MPS2TZ_MACHINE(obj) \ | 76 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ |
122 | + OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) | 77 | + uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ |
123 | +#define MPS2TZ_MACHINE_GET_CLASS(obj) \ | 78 | + (d[H8(e)] & ~shiftmask); \ |
124 | + OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) | 79 | + mergemask(&d[H8(e)], r, mask); \ |
125 | +#define MPS2TZ_MACHINE_CLASS(klass) \ | 80 | + } \ |
126 | + OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) | 81 | +done: \ |
127 | + | 82 | + mve_advance_vpt(env); \ |
128 | +/* Main SYSCLK frequency in Hz */ | ||
129 | +#define SYSCLK_FRQ 20000000 | ||
130 | + | ||
131 | +/* Initialize the auxiliary RAM region @mr and map it into | ||
132 | + * the memory map at @base. | ||
133 | + */ | ||
134 | +static void make_ram(MemoryRegion *mr, const char *name, | ||
135 | + hwaddr base, hwaddr size) | ||
136 | +{ | ||
137 | + memory_region_init_ram(mr, NULL, name, size, &error_fatal); | ||
138 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
139 | +} | ||
140 | + | ||
141 | +/* Create an alias of an entire original MemoryRegion @orig | ||
142 | + * located at @base in the memory map. | ||
143 | + */ | ||
144 | +static void make_ram_alias(MemoryRegion *mr, const char *name, | ||
145 | + MemoryRegion *orig, hwaddr base) | ||
146 | +{ | ||
147 | + memory_region_init_alias(mr, NULL, name, orig, 0, | ||
148 | + memory_region_size(orig)); | ||
149 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
150 | +} | ||
151 | + | ||
152 | +static void init_sysbus_child(Object *parent, const char *childname, | ||
153 | + void *child, size_t childsize, | ||
154 | + const char *childtype) | ||
155 | +{ | ||
156 | + object_initialize(child, childsize, childtype); | ||
157 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | ||
158 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
159 | + | ||
160 | +} | ||
161 | + | ||
162 | +/* Most of the devices in the AN505 FPGA image sit behind | ||
163 | + * Peripheral Protection Controllers. These data structures | ||
164 | + * define the layout of which devices sit behind which PPCs. | ||
165 | + * The devfn for each port is a function which creates, configures | ||
166 | + * and initializes the device, returning the MemoryRegion which | ||
167 | + * needs to be plugged into the downstream end of the PPC port. | ||
168 | + */ | ||
169 | +typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, | ||
170 | + const char *name, hwaddr size); | ||
171 | + | ||
172 | +typedef struct PPCPortInfo { | ||
173 | + const char *name; | ||
174 | + MakeDevFn *devfn; | ||
175 | + void *opaque; | ||
176 | + hwaddr addr; | ||
177 | + hwaddr size; | ||
178 | +} PPCPortInfo; | ||
179 | + | ||
180 | +typedef struct PPCInfo { | ||
181 | + const char *name; | ||
182 | + PPCPortInfo ports[TZ_NUM_PORTS]; | ||
183 | +} PPCInfo; | ||
184 | + | ||
185 | +static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | ||
186 | + void *opaque, | ||
187 | + const char *name, hwaddr size) | ||
188 | +{ | ||
189 | + /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | ||
190 | + * and return a pointer to its MemoryRegion. | ||
191 | + */ | ||
192 | + UnimplementedDeviceState *uds = opaque; | ||
193 | + | ||
194 | + init_sysbus_child(OBJECT(mms), name, uds, | ||
195 | + sizeof(UnimplementedDeviceState), | ||
196 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
197 | + qdev_prop_set_string(DEVICE(uds), "name", name); | ||
198 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | ||
199 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | ||
200 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); | ||
201 | +} | ||
202 | + | ||
203 | +static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | ||
204 | + const char *name, hwaddr size) | ||
205 | +{ | ||
206 | + CMSDKAPBUART *uart = opaque; | ||
207 | + int i = uart - &mms->uart[0]; | ||
208 | + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; | ||
209 | + int rxirqno = i * 2; | ||
210 | + int txirqno = i * 2 + 1; | ||
211 | + int combirqno = i + 10; | ||
212 | + SysBusDevice *s; | ||
213 | + DeviceState *iotkitdev = DEVICE(&mms->iotkit); | ||
214 | + DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | ||
215 | + | ||
216 | + init_sysbus_child(OBJECT(mms), name, uart, | ||
217 | + sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); | ||
218 | + qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); | ||
219 | + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); | ||
220 | + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | ||
221 | + s = SYS_BUS_DEVICE(uart); | ||
222 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, | ||
223 | + "EXP_IRQ", txirqno)); | ||
224 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, | ||
225 | + "EXP_IRQ", rxirqno)); | ||
226 | + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); | ||
227 | + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | ||
228 | + sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, | ||
229 | + "EXP_IRQ", combirqno)); | ||
230 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); | ||
231 | +} | ||
232 | + | ||
233 | +static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | ||
234 | + const char *name, hwaddr size) | ||
235 | +{ | ||
236 | + MPS2SCC *scc = opaque; | ||
237 | + DeviceState *sccdev; | ||
238 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
239 | + | ||
240 | + object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); | ||
241 | + sccdev = DEVICE(scc); | ||
242 | + qdev_set_parent_bus(sccdev, sysbus_get_default()); | ||
243 | + qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | ||
244 | + qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); | ||
245 | + qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | ||
246 | + object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); | ||
247 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); | ||
248 | +} | ||
249 | + | ||
250 | +static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | ||
251 | + const char *name, hwaddr size) | ||
252 | +{ | ||
253 | + MPS2FPGAIO *fpgaio = opaque; | ||
254 | + | ||
255 | + object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); | ||
256 | + qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); | ||
257 | + object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); | ||
258 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
259 | +} | ||
260 | + | ||
261 | +static void mps2tz_common_init(MachineState *machine) | ||
262 | +{ | ||
263 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
264 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
265 | + MemoryRegion *system_memory = get_system_memory(); | ||
266 | + DeviceState *iotkitdev; | ||
267 | + DeviceState *dev_splitter; | ||
268 | + int i; | ||
269 | + | ||
270 | + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | ||
271 | + error_report("This board can only be used with CPU %s", | ||
272 | + mc->default_cpu_type); | ||
273 | + exit(1); | ||
274 | + } | 83 | + } |
275 | + | 84 | + |
276 | + init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, | 85 | +#define DO_SHL(N, SHIFT) ((N) << (SHIFT)) |
277 | + sizeof(mms->iotkit), TYPE_IOTKIT); | 86 | +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) |
278 | + iotkitdev = DEVICE(&mms->iotkit); | 87 | +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) |
279 | + object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | 88 | +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) |
280 | + "memory", &error_abort); | ||
281 | + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); | ||
282 | + qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); | ||
283 | + object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", | ||
284 | + &error_fatal); | ||
285 | + | 89 | + |
286 | + /* The sec_resp_cfg output from the IoTKit must be split into multiple | 90 | +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) |
287 | + * lines, one for each of the PPCs we create here. | 91 | +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) |
288 | + */ | 92 | +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) |
289 | + object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), | 93 | +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) |
290 | + TYPE_SPLIT_IRQ); | 94 | +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) |
291 | + object_property_add_child(OBJECT(machine), "sec-resp-splitter", | 95 | +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) |
292 | + OBJECT(&mms->sec_resp_splitter), &error_abort); | ||
293 | + object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, | ||
294 | + "num-lines", &error_fatal); | ||
295 | + object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, | ||
296 | + "realized", &error_fatal); | ||
297 | + dev_splitter = DEVICE(&mms->sec_resp_splitter); | ||
298 | + qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, | ||
299 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
300 | + | 96 | + |
301 | + /* The IoTKit sets up much of the memory layout, including | 97 | /* |
302 | + * the aliases between secure and non-secure regions in the | 98 | * Long shifts taking half-sized inputs from top or bottom of the input |
303 | + * address space. The FPGA itself contains: | 99 | * vector and producing a double-width result. ESIZE, TYPE are for |
304 | + * | 100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
305 | + * 0x00000000..0x003fffff SSRAM1 | 101 | index XXXXXXX..XXXXXXX 100644 |
306 | + * 0x00400000..0x007fffff alias of SSRAM1 | 102 | --- a/target/arm/translate-mve.c |
307 | + * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 | 103 | +++ b/target/arm/translate-mve.c |
308 | + * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices | 104 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true) |
309 | + * 0x80000000..0x80ffffff 16MB PSRAM | 105 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) |
310 | + */ | 106 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) |
107 | |||
108 | +DO_2SHIFT(VSRI, vsri, false) | ||
109 | +DO_2SHIFT(VSLI, vsli, false) | ||
311 | + | 110 | + |
312 | + /* The FPGA images have an odd combination of different RAMs, | 111 | #define DO_VSHLL(INSN, FN) \ |
313 | + * because in hardware they are different implementations and | 112 | static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
314 | + * connected to different buses, giving varying performance/size | 113 | { \ |
315 | + * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | ||
316 | + * call the 16MB our "system memory", as it's the largest lump. | ||
317 | + */ | ||
318 | + memory_region_allocate_system_memory(&mms->psram, | ||
319 | + NULL, "mps.ram", 0x01000000); | ||
320 | + memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); | ||
321 | + | ||
322 | + /* The SSRAM memories should all be behind Memory Protection Controllers, | ||
323 | + * but we don't implement that yet. | ||
324 | + */ | ||
325 | + make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000); | ||
326 | + make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000); | ||
327 | + | ||
328 | + make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000); | ||
329 | + | ||
330 | + /* The overflow IRQs for all UARTs are ORed together. | ||
331 | + * Tx, Rx and "combined" IRQs are sent to the NVIC separately. | ||
332 | + * Create the OR gate for this. | ||
333 | + */ | ||
334 | + object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), | ||
335 | + TYPE_OR_IRQ); | ||
336 | + object_property_add_child(OBJECT(mms), "uart-irq-orgate", | ||
337 | + OBJECT(&mms->uart_irq_orgate), &error_abort); | ||
338 | + object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", | ||
339 | + &error_fatal); | ||
340 | + object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, | ||
341 | + "realized", &error_fatal); | ||
342 | + qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | ||
343 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); | ||
344 | + | ||
345 | + /* Most of the devices in the FPGA are behind Peripheral Protection | ||
346 | + * Controllers. The required order for initializing things is: | ||
347 | + * + initialize the PPC | ||
348 | + * + initialize, configure and realize downstream devices | ||
349 | + * + connect downstream device MemoryRegions to the PPC | ||
350 | + * + realize the PPC | ||
351 | + * + map the PPC's MemoryRegions to the places in the address map | ||
352 | + * where the downstream devices should appear | ||
353 | + * + wire up the PPC's control lines to the IoTKit object | ||
354 | + */ | ||
355 | + | ||
356 | + const PPCInfo ppcs[] = { { | ||
357 | + .name = "apb_ppcexp0", | ||
358 | + .ports = { | ||
359 | + { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0], | ||
360 | + 0x58007000, 0x1000 }, | ||
361 | + { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1], | ||
362 | + 0x58008000, 0x1000 }, | ||
363 | + { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2], | ||
364 | + 0x58009000, 0x1000 }, | ||
365 | + }, | ||
366 | + }, { | ||
367 | + .name = "apb_ppcexp1", | ||
368 | + .ports = { | ||
369 | + { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, | ||
370 | + { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, | ||
371 | + { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, | ||
372 | + { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, | ||
373 | + { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, | ||
374 | + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, | ||
375 | + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | ||
376 | + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | ||
377 | + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | ||
378 | + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | ||
379 | + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
380 | + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
381 | + { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
382 | + { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | ||
383 | + }, | ||
384 | + }, { | ||
385 | + .name = "apb_ppcexp2", | ||
386 | + .ports = { | ||
387 | + { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, | ||
388 | + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, | ||
389 | + 0x40301000, 0x1000 }, | ||
390 | + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, | ||
391 | + }, | ||
392 | + }, { | ||
393 | + .name = "ahb_ppcexp0", | ||
394 | + .ports = { | ||
395 | + { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, | ||
396 | + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, | ||
397 | + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
398 | + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
399 | + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
400 | + { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, | ||
401 | + }, | ||
402 | + }, { | ||
403 | + .name = "ahb_ppcexp1", | ||
404 | + .ports = { | ||
405 | + { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, | ||
406 | + { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, | ||
407 | + { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, | ||
408 | + { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, | ||
409 | + }, | ||
410 | + }, | ||
411 | + }; | ||
412 | + | ||
413 | + for (i = 0; i < ARRAY_SIZE(ppcs); i++) { | ||
414 | + const PPCInfo *ppcinfo = &ppcs[i]; | ||
415 | + TZPPC *ppc = &mms->ppc[i]; | ||
416 | + DeviceState *ppcdev; | ||
417 | + int port; | ||
418 | + char *gpioname; | ||
419 | + | ||
420 | + init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, | ||
421 | + sizeof(TZPPC), TYPE_TZ_PPC); | ||
422 | + ppcdev = DEVICE(ppc); | ||
423 | + | ||
424 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
425 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
426 | + MemoryRegion *mr; | ||
427 | + char *portname; | ||
428 | + | ||
429 | + if (!pinfo->devfn) { | ||
430 | + continue; | ||
431 | + } | ||
432 | + | ||
433 | + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | ||
434 | + portname = g_strdup_printf("port[%d]", port); | ||
435 | + object_property_set_link(OBJECT(ppc), OBJECT(mr), | ||
436 | + portname, &error_fatal); | ||
437 | + g_free(portname); | ||
438 | + } | ||
439 | + | ||
440 | + object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); | ||
441 | + | ||
442 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
443 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
444 | + | ||
445 | + if (!pinfo->devfn) { | ||
446 | + continue; | ||
447 | + } | ||
448 | + sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); | ||
449 | + | ||
450 | + gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); | ||
451 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
452 | + qdev_get_gpio_in_named(ppcdev, | ||
453 | + "cfg_nonsec", | ||
454 | + port)); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_ap", ppcinfo->name); | ||
457 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
458 | + qdev_get_gpio_in_named(ppcdev, | ||
459 | + "cfg_ap", port)); | ||
460 | + g_free(gpioname); | ||
461 | + } | ||
462 | + | ||
463 | + gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); | ||
464 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | ||
465 | + qdev_get_gpio_in_named(ppcdev, | ||
466 | + "irq_enable", 0)); | ||
467 | + g_free(gpioname); | ||
468 | + gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); | ||
469 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | ||
470 | + qdev_get_gpio_in_named(ppcdev, | ||
471 | + "irq_clear", 0)); | ||
472 | + g_free(gpioname); | ||
473 | + gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); | ||
474 | + qdev_connect_gpio_out_named(ppcdev, "irq", 0, | ||
475 | + qdev_get_gpio_in_named(iotkitdev, | ||
476 | + gpioname, 0)); | ||
477 | + g_free(gpioname); | ||
478 | + | ||
479 | + qdev_connect_gpio_out(dev_splitter, i, | ||
480 | + qdev_get_gpio_in_named(ppcdev, | ||
481 | + "cfg_sec_resp", 0)); | ||
482 | + } | ||
483 | + | ||
484 | + /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
485 | + * except that it doesn't support the checksum-offload feature. | ||
486 | + * The ethernet controller is not behind a PPC. | ||
487 | + */ | ||
488 | + lan9118_init(&nd_table[0], 0x42000000, | ||
489 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | ||
490 | + | ||
491 | + create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); | ||
492 | + | ||
493 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | ||
494 | +} | ||
495 | + | ||
496 | +static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
497 | +{ | ||
498 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
499 | + | ||
500 | + mc->init = mps2tz_common_init; | ||
501 | + mc->max_cpus = 1; | ||
502 | +} | ||
503 | + | ||
504 | +static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | ||
505 | +{ | ||
506 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
507 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
508 | + | ||
509 | + mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; | ||
510 | + mmc->fpga_type = FPGA_AN505; | ||
511 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | ||
512 | + mmc->scc_id = 0x41040000 | (505 << 4); | ||
513 | +} | ||
514 | + | ||
515 | +static const TypeInfo mps2tz_info = { | ||
516 | + .name = TYPE_MPS2TZ_MACHINE, | ||
517 | + .parent = TYPE_MACHINE, | ||
518 | + .abstract = true, | ||
519 | + .instance_size = sizeof(MPS2TZMachineState), | ||
520 | + .class_size = sizeof(MPS2TZMachineClass), | ||
521 | + .class_init = mps2tz_class_init, | ||
522 | +}; | ||
523 | + | ||
524 | +static const TypeInfo mps2tz_an505_info = { | ||
525 | + .name = TYPE_MPS2TZ_AN505_MACHINE, | ||
526 | + .parent = TYPE_MPS2TZ_MACHINE, | ||
527 | + .class_init = mps2tz_an505_class_init, | ||
528 | +}; | ||
529 | + | ||
530 | +static void mps2tz_machine_init(void) | ||
531 | +{ | ||
532 | + type_register_static(&mps2tz_info); | ||
533 | + type_register_static(&mps2tz_an505_info); | ||
534 | +} | ||
535 | + | ||
536 | +type_init(mps2tz_machine_init); | ||
537 | -- | 114 | -- |
538 | 2.16.2 | 115 | 2.20.1 |
539 | 116 | ||
540 | 117 | diff view generated by jsdifflib |
1 | The IoTKit Security Controller includes various registers | 1 | Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN. |
---|---|---|---|
2 | that expose to software the controls for the Peripheral | 2 | |
3 | Protection Controllers in the system. Implement these. | 3 | do_urshr() is borrowed from sve_helper.c. |
4 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-17-peter.maydell@linaro.org | 7 | Message-id: 20210628135835.6690-12-peter.maydell@linaro.org |
8 | --- | 8 | --- |
9 | include/hw/misc/iotkit-secctl.h | 64 +++++++++- | 9 | target/arm/helper-mve.h | 10 ++++++++++ |
10 | hw/misc/iotkit-secctl.c | 270 +++++++++++++++++++++++++++++++++++++--- | 10 | target/arm/mve.decode | 11 +++++++++++ |
11 | 2 files changed, 315 insertions(+), 19 deletions(-) | 11 | target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ |
12 | target/arm/translate-mve.c | 15 ++++++++++++++ | ||
13 | 4 files changed, 76 insertions(+) | ||
12 | 14 | ||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/misc/iotkit-secctl.h | 17 | --- a/target/arm/helper-mve.h |
16 | +++ b/include/hw/misc/iotkit-secctl.h | 18 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
18 | * QEMU interface: | 20 | DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
19 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | 21 | DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
20 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 22 | DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | + * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | ||
22 | + * should RAZ/WI or bus error | ||
23 | + * Controlling the 2 APB PPCs in the IoTKit: | ||
24 | + * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
25 | + * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
26 | + * + named GPIO outputs apb_ppc{0,1}_irq_enable | ||
27 | + * + named GPIO outputs apb_ppc{0,1}_irq_clear | ||
28 | + * + named GPIO inputs apb_ppc{0,1}_irq_status | ||
29 | + * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit | ||
30 | + * might provide: | ||
31 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
32 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
33 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
34 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
35 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
36 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
37 | + * might provide: | ||
38 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
39 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
40 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
41 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
42 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
43 | */ | ||
44 | |||
45 | #ifndef IOTKIT_SECCTL_H | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
48 | #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
49 | |||
50 | -typedef struct IoTKitSecCtl { | ||
51 | +#define IOTS_APB_PPC0_NUM_PORTS 3 | ||
52 | +#define IOTS_APB_PPC1_NUM_PORTS 1 | ||
53 | +#define IOTS_PPC_NUM_PORTS 16 | ||
54 | +#define IOTS_NUM_APB_PPC 2 | ||
55 | +#define IOTS_NUM_APB_EXP_PPC 4 | ||
56 | +#define IOTS_NUM_AHB_EXP_PPC 4 | ||
57 | + | 23 | + |
58 | +typedef struct IoTKitSecCtl IoTKitSecCtl; | 24 | +DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | +DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
59 | + | 28 | + |
60 | +/* State and IRQ lines relating to a PPC. For the | 29 | +DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
61 | + * PPCs in the IoTKit not all the IRQ lines are used. | 30 | +DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | +DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/mve.decode | ||
36 | +++ b/target/arm/mve.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
38 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
39 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
40 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
41 | + | ||
42 | +# Narrowing shifts (which only support b and h sizes) | ||
43 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
44 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
45 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
46 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
47 | + | ||
48 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
49 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
50 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
51 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
57 | |||
58 | DO_VSHLL_ALL(vshllb, false) | ||
59 | DO_VSHLL_ALL(vshllt, true) | ||
60 | + | ||
61 | +/* | ||
62 | + * Narrowing right shifts, taking a double sized input, shifting it | ||
63 | + * and putting the result in either the top or bottom half of the output. | ||
64 | + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. | ||
62 | + */ | 65 | + */ |
63 | +typedef struct IoTKitSecCtlPPC { | 66 | +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ |
64 | + qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; | 67 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
65 | + qemu_irq ap[IOTS_PPC_NUM_PORTS]; | 68 | + void *vm, uint32_t shift) \ |
66 | + qemu_irq irq_enable; | 69 | + { \ |
67 | + qemu_irq irq_clear; | 70 | + LTYPE *m = vm; \ |
71 | + TYPE *d = vd; \ | ||
72 | + uint16_t mask = mve_element_mask(env); \ | ||
73 | + unsigned le; \ | ||
74 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
75 | + TYPE r = FN(m[H##LESIZE(le)], shift); \ | ||
76 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | ||
77 | + } \ | ||
78 | + mve_advance_vpt(env); \ | ||
79 | + } | ||
68 | + | 80 | + |
69 | + uint32_t ns; | 81 | +#define DO_VSHRN_ALL(OP, FN) \ |
70 | + uint32_t sp; | 82 | + DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ |
71 | + uint32_t nsp; | 83 | + DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ |
84 | + DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ | ||
85 | + DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) | ||
72 | + | 86 | + |
73 | + /* Number of ports actually present */ | 87 | +static inline uint64_t do_urshr(uint64_t x, unsigned sh) |
74 | + int numports; | ||
75 | + /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ | ||
76 | + int irq_bit_offset; | ||
77 | + IoTKitSecCtl *parent; | ||
78 | +} IoTKitSecCtlPPC; | ||
79 | + | ||
80 | +struct IoTKitSecCtl { | ||
81 | /*< private >*/ | ||
82 | SysBusDevice parent_obj; | ||
83 | |||
84 | /*< public >*/ | ||
85 | + qemu_irq sec_resp_cfg; | ||
86 | |||
87 | MemoryRegion s_regs; | ||
88 | MemoryRegion ns_regs; | ||
89 | -} IoTKitSecCtl; | ||
90 | + | ||
91 | + uint32_t secppcintstat; | ||
92 | + uint32_t secppcinten; | ||
93 | + uint32_t secrespcfg; | ||
94 | + | ||
95 | + IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
96 | + IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
97 | + IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; | ||
98 | +}; | ||
99 | |||
100 | #endif | ||
101 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/hw/misc/iotkit-secctl.c | ||
104 | +++ b/hw/misc/iotkit-secctl.c | ||
105 | @@ -XXX,XX +XXX,XX @@ static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
106 | 0x0d, 0xf0, 0x05, 0xb1, | ||
107 | }; | ||
108 | |||
109 | +/* The register sets for the various PPCs (AHB internal, APB internal, | ||
110 | + * AHB expansion, APB expansion) are all set up so that they are | ||
111 | + * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs | ||
112 | + * 0, 1, 2, 3 of that type, so we can convert a register address offset | ||
113 | + * into an an index into a PPC array easily. | ||
114 | + */ | ||
115 | +static inline int offset_to_ppc_idx(uint32_t offset) | ||
116 | +{ | 88 | +{ |
117 | + return extract32(offset, 2, 2); | 89 | + if (likely(sh < 64)) { |
118 | +} | 90 | + return (x >> sh) + ((x >> (sh - 1)) & 1); |
119 | + | 91 | + } else if (sh == 64) { |
120 | +typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc); | 92 | + return x >> 63; |
121 | + | 93 | + } else { |
122 | +static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn) | 94 | + return 0; |
123 | +{ | ||
124 | + int i; | ||
125 | + | ||
126 | + for (i = 0; i < IOTS_NUM_APB_PPC; i++) { | ||
127 | + fn(&s->apb[i]); | ||
128 | + } | ||
129 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
130 | + fn(&s->apbexp[i]); | ||
131 | + } | ||
132 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
133 | + fn(&s->ahbexp[i]); | ||
134 | + } | 95 | + } |
135 | +} | 96 | +} |
136 | + | 97 | + |
137 | static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | 98 | +DO_VSHRN_ALL(vshrn, DO_SHR) |
138 | uint64_t *pdata, | 99 | +DO_VSHRN_ALL(vrshrn, do_urshr) |
139 | unsigned size, MemTxAttrs attrs) | 100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
140 | { | 101 | index XXXXXXX..XXXXXXX 100644 |
141 | uint64_t r; | 102 | --- a/target/arm/translate-mve.c |
142 | uint32_t offset = addr & ~0x3; | 103 | +++ b/target/arm/translate-mve.c |
143 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | 104 | @@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs) |
144 | 105 | DO_VSHLL(VSHLL_BU, vshllbu) | |
145 | switch (offset) { | 106 | DO_VSHLL(VSHLL_TS, vshllts) |
146 | case A_AHBNSPPC0: | 107 | DO_VSHLL(VSHLL_TU, vshlltu) |
147 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
148 | r = 0; | ||
149 | break; | ||
150 | case A_SECRESPCFG: | ||
151 | - case A_NSCCFG: | ||
152 | - case A_SECMPCINTSTATUS: | ||
153 | + r = s->secrespcfg; | ||
154 | + break; | ||
155 | case A_SECPPCINTSTAT: | ||
156 | + r = s->secppcintstat; | ||
157 | + break; | ||
158 | case A_SECPPCINTEN: | ||
159 | - case A_SECMSCINTSTAT: | ||
160 | - case A_SECMSCINTEN: | ||
161 | - case A_BRGINTSTAT: | ||
162 | - case A_BRGINTEN: | ||
163 | + r = s->secppcinten; | ||
164 | + break; | ||
165 | case A_AHBNSPPCEXP0: | ||
166 | case A_AHBNSPPCEXP1: | ||
167 | case A_AHBNSPPCEXP2: | ||
168 | case A_AHBNSPPCEXP3: | ||
169 | + r = s->ahbexp[offset_to_ppc_idx(offset)].ns; | ||
170 | + break; | ||
171 | case A_APBNSPPC0: | ||
172 | case A_APBNSPPC1: | ||
173 | + r = s->apb[offset_to_ppc_idx(offset)].ns; | ||
174 | + break; | ||
175 | case A_APBNSPPCEXP0: | ||
176 | case A_APBNSPPCEXP1: | ||
177 | case A_APBNSPPCEXP2: | ||
178 | case A_APBNSPPCEXP3: | ||
179 | + r = s->apbexp[offset_to_ppc_idx(offset)].ns; | ||
180 | + break; | ||
181 | case A_AHBSPPPCEXP0: | ||
182 | case A_AHBSPPPCEXP1: | ||
183 | case A_AHBSPPPCEXP2: | ||
184 | case A_AHBSPPPCEXP3: | ||
185 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
186 | + break; | ||
187 | case A_APBSPPPC0: | ||
188 | case A_APBSPPPC1: | ||
189 | + r = s->apb[offset_to_ppc_idx(offset)].sp; | ||
190 | + break; | ||
191 | case A_APBSPPPCEXP0: | ||
192 | case A_APBSPPPCEXP1: | ||
193 | case A_APBSPPPCEXP2: | ||
194 | case A_APBSPPPCEXP3: | ||
195 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
196 | + break; | ||
197 | + case A_NSCCFG: | ||
198 | + case A_SECMPCINTSTATUS: | ||
199 | + case A_SECMSCINTSTAT: | ||
200 | + case A_SECMSCINTEN: | ||
201 | + case A_BRGINTSTAT: | ||
202 | + case A_BRGINTEN: | ||
203 | case A_NSMSCEXP: | ||
204 | qemu_log_mask(LOG_UNIMP, | ||
205 | "IoTKit SecCtl S block read: " | ||
206 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
207 | return MEMTX_OK; | ||
208 | } | ||
209 | |||
210 | +static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc) | ||
211 | +{ | ||
212 | + int i; | ||
213 | + | 108 | + |
214 | + for (i = 0; i < ppc->numports; i++) { | 109 | +#define DO_2SHIFT_N(INSN, FN) \ |
215 | + bool v; | 110 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
216 | + | 111 | + { \ |
217 | + if (extract32(ppc->ns, i, 1)) { | 112 | + static MVEGenTwoOpShiftFn * const fns[] = { \ |
218 | + v = extract32(ppc->nsp, i, 1); | 113 | + gen_helper_mve_##FN##b, \ |
219 | + } else { | 114 | + gen_helper_mve_##FN##h, \ |
220 | + v = extract32(ppc->sp, i, 1); | 115 | + }; \ |
221 | + } | 116 | + return do_2shift(s, a, fns[a->size], false); \ |
222 | + qemu_set_irq(ppc->ap[i], v); | ||
223 | + } | ||
224 | +} | ||
225 | + | ||
226 | +static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
227 | +{ | ||
228 | + int i; | ||
229 | + | ||
230 | + ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
231 | + for (i = 0; i < ppc->numports; i++) { | ||
232 | + qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); | ||
233 | + } | ||
234 | + iotkit_secctl_update_ppc_ap(ppc); | ||
235 | +} | ||
236 | + | ||
237 | +static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
238 | +{ | ||
239 | + ppc->sp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
240 | + iotkit_secctl_update_ppc_ap(ppc); | ||
241 | +} | ||
242 | + | ||
243 | +static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
244 | +{ | ||
245 | + ppc->nsp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
246 | + iotkit_secctl_update_ppc_ap(ppc); | ||
247 | +} | ||
248 | + | ||
249 | +static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc) | ||
250 | +{ | ||
251 | + uint32_t value = ppc->parent->secppcintstat; | ||
252 | + | ||
253 | + qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1)); | ||
254 | +} | ||
255 | + | ||
256 | +static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc) | ||
257 | +{ | ||
258 | + uint32_t value = ppc->parent->secppcinten; | ||
259 | + | ||
260 | + qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)); | ||
261 | +} | ||
262 | + | ||
263 | static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
264 | uint64_t value, | ||
265 | unsigned size, MemTxAttrs attrs) | ||
266 | { | ||
267 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
268 | uint32_t offset = addr; | ||
269 | + IoTKitSecCtlPPC *ppc; | ||
270 | |||
271 | trace_iotkit_secctl_s_write(offset, value, size); | ||
272 | |||
273 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
274 | |||
275 | switch (offset) { | ||
276 | case A_SECRESPCFG: | ||
277 | - case A_NSCCFG: | ||
278 | + value &= 1; | ||
279 | + s->secrespcfg = value; | ||
280 | + qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); | ||
281 | + break; | ||
282 | case A_SECPPCINTCLR: | ||
283 | + value &= 0x00f000f3; | ||
284 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear); | ||
285 | + break; | ||
286 | case A_SECPPCINTEN: | ||
287 | - case A_SECMSCINTCLR: | ||
288 | - case A_SECMSCINTEN: | ||
289 | - case A_BRGINTCLR: | ||
290 | - case A_BRGINTEN: | ||
291 | + s->secppcinten = value & 0x00f000f3; | ||
292 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
293 | + break; | ||
294 | case A_AHBNSPPCEXP0: | ||
295 | case A_AHBNSPPCEXP1: | ||
296 | case A_AHBNSPPCEXP2: | ||
297 | case A_AHBNSPPCEXP3: | ||
298 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
299 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
300 | + break; | ||
301 | case A_APBNSPPC0: | ||
302 | case A_APBNSPPC1: | ||
303 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
304 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
305 | + break; | ||
306 | case A_APBNSPPCEXP0: | ||
307 | case A_APBNSPPCEXP1: | ||
308 | case A_APBNSPPCEXP2: | ||
309 | case A_APBNSPPCEXP3: | ||
310 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
311 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
312 | + break; | ||
313 | case A_AHBSPPPCEXP0: | ||
314 | case A_AHBSPPPCEXP1: | ||
315 | case A_AHBSPPPCEXP2: | ||
316 | case A_AHBSPPPCEXP3: | ||
317 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
318 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
319 | + break; | ||
320 | case A_APBSPPPC0: | ||
321 | case A_APBSPPPC1: | ||
322 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
323 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
324 | + break; | ||
325 | case A_APBSPPPCEXP0: | ||
326 | case A_APBSPPPCEXP1: | ||
327 | case A_APBSPPPCEXP2: | ||
328 | case A_APBSPPPCEXP3: | ||
329 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
330 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
331 | + break; | ||
332 | + case A_NSCCFG: | ||
333 | + case A_SECMSCINTCLR: | ||
334 | + case A_SECMSCINTEN: | ||
335 | + case A_BRGINTCLR: | ||
336 | + case A_BRGINTEN: | ||
337 | qemu_log_mask(LOG_UNIMP, | ||
338 | "IoTKit SecCtl S block write: " | ||
339 | "unimplemented offset 0x%x\n", offset); | ||
340 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
341 | uint64_t *pdata, | ||
342 | unsigned size, MemTxAttrs attrs) | ||
343 | { | ||
344 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
345 | uint64_t r; | ||
346 | uint32_t offset = addr & ~0x3; | ||
347 | |||
348 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
349 | case A_AHBNSPPPCEXP1: | ||
350 | case A_AHBNSPPPCEXP2: | ||
351 | case A_AHBNSPPPCEXP3: | ||
352 | + r = s->ahbexp[offset_to_ppc_idx(offset)].nsp; | ||
353 | + break; | ||
354 | case A_APBNSPPPC0: | ||
355 | case A_APBNSPPPC1: | ||
356 | + r = s->apb[offset_to_ppc_idx(offset)].nsp; | ||
357 | + break; | ||
358 | case A_APBNSPPPCEXP0: | ||
359 | case A_APBNSPPPCEXP1: | ||
360 | case A_APBNSPPPCEXP2: | ||
361 | case A_APBNSPPPCEXP3: | ||
362 | - qemu_log_mask(LOG_UNIMP, | ||
363 | - "IoTKit SecCtl NS block read: " | ||
364 | - "unimplemented offset 0x%x\n", offset); | ||
365 | + r = s->apbexp[offset_to_ppc_idx(offset)].nsp; | ||
366 | break; | ||
367 | case A_PID4: | ||
368 | case A_PID5: | ||
369 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
370 | uint64_t value, | ||
371 | unsigned size, MemTxAttrs attrs) | ||
372 | { | ||
373 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
374 | uint32_t offset = addr; | ||
375 | + IoTKitSecCtlPPC *ppc; | ||
376 | |||
377 | trace_iotkit_secctl_ns_write(offset, value, size); | ||
378 | |||
379 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
380 | case A_AHBNSPPPCEXP1: | ||
381 | case A_AHBNSPPPCEXP2: | ||
382 | case A_AHBNSPPPCEXP3: | ||
383 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
384 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
385 | + break; | ||
386 | case A_APBNSPPPC0: | ||
387 | case A_APBNSPPPC1: | ||
388 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
389 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
390 | + break; | ||
391 | case A_APBNSPPPCEXP0: | ||
392 | case A_APBNSPPPCEXP1: | ||
393 | case A_APBNSPPPCEXP2: | ||
394 | case A_APBNSPPPCEXP3: | ||
395 | - qemu_log_mask(LOG_UNIMP, | ||
396 | - "IoTKit SecCtl NS block write: " | ||
397 | - "unimplemented offset 0x%x\n", offset); | ||
398 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
399 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
400 | break; | ||
401 | case A_AHBNSPPPC0: | ||
402 | case A_PID4: | ||
403 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
404 | .impl.max_access_size = 4, | ||
405 | }; | ||
406 | |||
407 | +static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc) | ||
408 | +{ | ||
409 | + ppc->ns = 0; | ||
410 | + ppc->sp = 0; | ||
411 | + ppc->nsp = 0; | ||
412 | +} | ||
413 | + | ||
414 | static void iotkit_secctl_reset(DeviceState *dev) | ||
415 | { | ||
416 | + IoTKitSecCtl *s = IOTKIT_SECCTL(dev); | ||
417 | |||
418 | + s->secppcintstat = 0; | ||
419 | + s->secppcinten = 0; | ||
420 | + s->secrespcfg = 0; | ||
421 | + | ||
422 | + foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
423 | +} | ||
424 | + | ||
425 | +static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level) | ||
426 | +{ | ||
427 | + IoTKitSecCtlPPC *ppc = opaque; | ||
428 | + IoTKitSecCtl *s = IOTKIT_SECCTL(ppc->parent); | ||
429 | + int irqbit = ppc->irq_bit_offset + n; | ||
430 | + | ||
431 | + s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level); | ||
432 | +} | ||
433 | + | ||
434 | +static void iotkit_secctl_init_ppc(IoTKitSecCtl *s, | ||
435 | + IoTKitSecCtlPPC *ppc, | ||
436 | + const char *name, | ||
437 | + int numports, | ||
438 | + int irq_bit_offset) | ||
439 | +{ | ||
440 | + char *gpioname; | ||
441 | + DeviceState *dev = DEVICE(s); | ||
442 | + | ||
443 | + ppc->numports = numports; | ||
444 | + ppc->irq_bit_offset = irq_bit_offset; | ||
445 | + ppc->parent = s; | ||
446 | + | ||
447 | + gpioname = g_strdup_printf("%s_nonsec", name); | ||
448 | + qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports); | ||
449 | + g_free(gpioname); | ||
450 | + gpioname = g_strdup_printf("%s_ap", name); | ||
451 | + qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports); | ||
452 | + g_free(gpioname); | ||
453 | + gpioname = g_strdup_printf("%s_irq_enable", name); | ||
454 | + qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_irq_clear", name); | ||
457 | + qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1); | ||
458 | + g_free(gpioname); | ||
459 | + gpioname = g_strdup_printf("%s_irq_status", name); | ||
460 | + qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus, | ||
461 | + ppc, gpioname, 1); | ||
462 | + g_free(gpioname); | ||
463 | } | ||
464 | |||
465 | static void iotkit_secctl_init(Object *obj) | ||
466 | { | ||
467 | IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
468 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
469 | + DeviceState *dev = DEVICE(obj); | ||
470 | + int i; | ||
471 | + | ||
472 | + iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0", | ||
473 | + IOTS_APB_PPC0_NUM_PORTS, 0); | ||
474 | + iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1", | ||
475 | + IOTS_APB_PPC1_NUM_PORTS, 1); | ||
476 | + | ||
477 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
478 | + IoTKitSecCtlPPC *ppc = &s->apbexp[i]; | ||
479 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
480 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i); | ||
481 | + g_free(ppcname); | ||
482 | + } | ||
483 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
484 | + IoTKitSecCtlPPC *ppc = &s->ahbexp[i]; | ||
485 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
486 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i); | ||
487 | + g_free(ppcname); | ||
488 | + } | 117 | + } |
489 | + | 118 | + |
490 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | 119 | +DO_2SHIFT_N(VSHRNB, vshrnb) |
491 | 120 | +DO_2SHIFT_N(VSHRNT, vshrnt) | |
492 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | 121 | +DO_2SHIFT_N(VRSHRNB, vrshrnb) |
493 | s, "iotkit-secctl-s-regs", 0x1000); | 122 | +DO_2SHIFT_N(VRSHRNT, vrshrnt) |
494 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
495 | sysbus_init_mmio(sbd, &s->ns_regs); | ||
496 | } | ||
497 | |||
498 | +static const VMStateDescription iotkit_secctl_ppc_vmstate = { | ||
499 | + .name = "iotkit-secctl-ppc", | ||
500 | + .version_id = 1, | ||
501 | + .minimum_version_id = 1, | ||
502 | + .fields = (VMStateField[]) { | ||
503 | + VMSTATE_UINT32(ns, IoTKitSecCtlPPC), | ||
504 | + VMSTATE_UINT32(sp, IoTKitSecCtlPPC), | ||
505 | + VMSTATE_UINT32(nsp, IoTKitSecCtlPPC), | ||
506 | + VMSTATE_END_OF_LIST() | ||
507 | + } | ||
508 | +}; | ||
509 | + | ||
510 | static const VMStateDescription iotkit_secctl_vmstate = { | ||
511 | .name = "iotkit-secctl", | ||
512 | .version_id = 1, | ||
513 | .minimum_version_id = 1, | ||
514 | .fields = (VMStateField[]) { | ||
515 | + VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
516 | + VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
517 | + VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
518 | + VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
519 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
520 | + VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
521 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
522 | + VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1, | ||
523 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
524 | VMSTATE_END_OF_LIST() | ||
525 | } | ||
526 | }; | ||
527 | -- | 123 | -- |
528 | 2.16.2 | 124 | 2.20.1 |
529 | 125 | ||
530 | 126 | diff view generated by jsdifflib |
1 | In some board or SoC models it is necessary to split a qemu_irq line | 1 | Implement the MVE saturating shift-right-and-narrow insns |
---|---|---|---|
2 | so that one input can feed multiple outputs. We currently have | 2 | VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN. |
3 | qemu_irq_split() for this, but that has several deficiencies: | 3 | |
4 | * it can only handle splitting a line into two | 4 | do_srshr() is borrowed from sve_helper.c. |
5 | * it unavoidably leaks memory, so it can't be used | ||
6 | in a device that can be deleted | ||
7 | |||
8 | Implement a qdev device that encapsulates splitting of IRQs, with a | ||
9 | configurable number of outputs. (This is in some ways the inverse of | ||
10 | the TYPE_OR_IRQ device.) | ||
11 | 5 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20180220180325.29818-13-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-13-peter.maydell@linaro.org |
15 | --- | 9 | --- |
16 | hw/core/Makefile.objs | 1 + | 10 | target/arm/helper-mve.h | 30 +++++++++++ |
17 | include/hw/core/split-irq.h | 57 +++++++++++++++++++++++++++++ | 11 | target/arm/mve.decode | 28 ++++++++++ |
18 | include/hw/irq.h | 4 +- | 12 | target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++ |
19 | hw/core/split-irq.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ | 13 | target/arm/translate-mve.c | 12 +++++ |
20 | 4 files changed, 150 insertions(+), 1 deletion(-) | 14 | 4 files changed, 174 insertions(+) |
21 | create mode 100644 include/hw/core/split-irq.h | 15 | |
22 | create mode 100644 hw/core/split-irq.c | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
23 | 17 | index XXXXXXX..XXXXXXX 100644 | |
24 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | 18 | --- a/target/arm/helper-mve.h |
25 | index XXXXXXX..XXXXXXX 100644 | 19 | +++ b/target/arm/helper-mve.h |
26 | --- a/hw/core/Makefile.objs | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | +++ b/hw/core/Makefile.objs | 21 | DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_FITLOADER) += loader-fit.o | 22 | DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o | 23 | DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | common-obj-$(CONFIG_SOFTMMU) += register.o | 24 | + |
31 | common-obj-$(CONFIG_SOFTMMU) += or-irq.o | 25 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | +common-obj-$(CONFIG_SOFTMMU) += split-irq.o | 26 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o | 27 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | 28 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
35 | obj-$(CONFIG_SOFTMMU) += generic-loader.o | 29 | + |
36 | diff --git a/include/hw/core/split-irq.h b/include/hw/core/split-irq.h | 30 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
37 | new file mode 100644 | 31 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
38 | index XXXXXXX..XXXXXXX | 32 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
39 | --- /dev/null | 33 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
40 | +++ b/include/hw/core/split-irq.h | 34 | + |
41 | @@ -XXX,XX +XXX,XX @@ | 35 | +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
42 | +/* | 36 | +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
43 | + * IRQ splitter device. | 37 | +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
44 | + * | 38 | +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
45 | + * Copyright (c) 2018 Linaro Limited. | 39 | + |
46 | + * Written by Peter Maydell | 40 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
47 | + * | 41 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
48 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 42 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
49 | + * of this software and associated documentation files (the "Software"), to deal | 43 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
50 | + * in the Software without restriction, including without limitation the rights | 44 | + |
51 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 45 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
52 | + * copies of the Software, and to permit persons to whom the Software is | 46 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
53 | + * furnished to do so, subject to the following conditions: | 47 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
54 | + * | 48 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
55 | + * The above copyright notice and this permission notice shall be included in | 49 | + |
56 | + * all copies or substantial portions of the Software. | 50 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
57 | + * | 51 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
58 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 52 | +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
59 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 53 | +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
60 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 54 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
61 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 55 | index XXXXXXX..XXXXXXX 100644 |
62 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | 56 | --- a/target/arm/mve.decode |
63 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 57 | +++ b/target/arm/mve.decode |
64 | + * THE SOFTWARE. | 58 | @@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b |
65 | + */ | 59 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h |
66 | + | 60 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b |
67 | +/* This is a simple device which has one GPIO input line and multiple | 61 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h |
68 | + * GPIO output lines. Any change on the input line is forwarded to all | 62 | + |
69 | + * of the outputs. | 63 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b |
70 | + * | 64 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h |
71 | + * QEMU interface: | 65 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b |
72 | + * + one unnamed GPIO input: the input line | 66 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h |
73 | + * + N unnamed GPIO outputs: the output lines | 67 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b |
74 | + * + QOM property "num-lines": sets the number of output lines | 68 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h |
75 | + */ | 69 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b |
76 | +#ifndef HW_SPLIT_IRQ_H | 70 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h |
77 | +#define HW_SPLIT_IRQ_H | 71 | + |
78 | + | 72 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
79 | +#include "hw/irq.h" | 73 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
80 | +#include "hw/sysbus.h" | 74 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
81 | +#include "qom/object.h" | 75 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h |
82 | + | 76 | + |
83 | +#define TYPE_SPLIT_IRQ "split-irq" | 77 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b |
84 | + | 78 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h |
85 | +#define MAX_SPLIT_LINES 16 | 79 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b |
86 | + | 80 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h |
87 | +typedef struct SplitIRQ SplitIRQ; | 81 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b |
88 | + | 82 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h |
89 | +#define SPLIT_IRQ(obj) OBJECT_CHECK(SplitIRQ, (obj), TYPE_SPLIT_IRQ) | 83 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b |
90 | + | 84 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h |
91 | +struct SplitIRQ { | 85 | + |
92 | + DeviceState parent_obj; | 86 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
93 | + | 87 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
94 | + qemu_irq out_irq[MAX_SPLIT_LINES]; | 88 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
95 | + uint16_t num_lines; | 89 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h |
96 | +}; | 90 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
97 | + | 91 | index XXXXXXX..XXXXXXX 100644 |
98 | +#endif | 92 | --- a/target/arm/mve_helper.c |
99 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 93 | +++ b/target/arm/mve_helper.c |
100 | index XXXXXXX..XXXXXXX 100644 | 94 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh) |
101 | --- a/include/hw/irq.h | 95 | } |
102 | +++ b/include/hw/irq.h | 96 | } |
103 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | 97 | |
104 | /* Returns a new IRQ with opposite polarity. */ | 98 | +static inline int64_t do_srshr(int64_t x, unsigned sh) |
105 | qemu_irq qemu_irq_invert(qemu_irq irq); | ||
106 | |||
107 | -/* Returns a new IRQ which feeds into both the passed IRQs */ | ||
108 | +/* Returns a new IRQ which feeds into both the passed IRQs. | ||
109 | + * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
110 | + */ | ||
111 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | ||
112 | |||
113 | /* Returns a new IRQ set which connects 1:1 to another IRQ set, which | ||
114 | diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c | ||
115 | new file mode 100644 | ||
116 | index XXXXXXX..XXXXXXX | ||
117 | --- /dev/null | ||
118 | +++ b/hw/core/split-irq.c | ||
119 | @@ -XXX,XX +XXX,XX @@ | ||
120 | +/* | ||
121 | + * IRQ splitter device. | ||
122 | + * | ||
123 | + * Copyright (c) 2018 Linaro Limited. | ||
124 | + * Written by Peter Maydell | ||
125 | + * | ||
126 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
127 | + * of this software and associated documentation files (the "Software"), to deal | ||
128 | + * in the Software without restriction, including without limitation the rights | ||
129 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
130 | + * copies of the Software, and to permit persons to whom the Software is | ||
131 | + * furnished to do so, subject to the following conditions: | ||
132 | + * | ||
133 | + * The above copyright notice and this permission notice shall be included in | ||
134 | + * all copies or substantial portions of the Software. | ||
135 | + * | ||
136 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
137 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
138 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
139 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
140 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
141 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
142 | + * THE SOFTWARE. | ||
143 | + */ | ||
144 | + | ||
145 | +#include "qemu/osdep.h" | ||
146 | +#include "hw/core/split-irq.h" | ||
147 | +#include "qapi/error.h" | ||
148 | + | ||
149 | +static void split_irq_handler(void *opaque, int n, int level) | ||
150 | +{ | 99 | +{ |
151 | + SplitIRQ *s = SPLIT_IRQ(opaque); | 100 | + if (likely(sh < 64)) { |
152 | + int i; | 101 | + return (x >> sh) + ((x >> (sh - 1)) & 1); |
153 | + | 102 | + } else { |
154 | + for (i = 0; i < s->num_lines; i++) { | 103 | + /* Rounding the sign bit always produces 0. */ |
155 | + qemu_set_irq(s->out_irq[i], level); | 104 | + return 0; |
156 | + } | 105 | + } |
157 | +} | 106 | +} |
158 | + | 107 | + |
159 | +static void split_irq_init(Object *obj) | 108 | DO_VSHRN_ALL(vshrn, DO_SHR) |
109 | DO_VSHRN_ALL(vrshrn, do_urshr) | ||
110 | + | ||
111 | +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, | ||
112 | + bool *satp) | ||
160 | +{ | 113 | +{ |
161 | + qdev_init_gpio_in(DEVICE(obj), split_irq_handler, 1); | 114 | + if (val > max) { |
115 | + *satp = true; | ||
116 | + return max; | ||
117 | + } else if (val < min) { | ||
118 | + *satp = true; | ||
119 | + return min; | ||
120 | + } else { | ||
121 | + return val; | ||
122 | + } | ||
162 | +} | 123 | +} |
163 | + | 124 | + |
164 | +static void split_irq_realize(DeviceState *dev, Error **errp) | 125 | +/* Saturating narrowing right shifts */ |
165 | +{ | 126 | +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ |
166 | + SplitIRQ *s = SPLIT_IRQ(dev); | 127 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
167 | + | 128 | + void *vm, uint32_t shift) \ |
168 | + if (s->num_lines < 1 || s->num_lines >= MAX_SPLIT_LINES) { | 129 | + { \ |
169 | + error_setg(errp, | 130 | + LTYPE *m = vm; \ |
170 | + "IRQ splitter number of lines %d is not between 1 and %d", | 131 | + TYPE *d = vd; \ |
171 | + s->num_lines, MAX_SPLIT_LINES); | 132 | + uint16_t mask = mve_element_mask(env); \ |
172 | + return; | 133 | + bool qc = false; \ |
134 | + unsigned le; \ | ||
135 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
136 | + bool sat = false; \ | ||
137 | + TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ | ||
138 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | ||
139 | + qc |= sat && (mask & 1 << (TOP * ESIZE)); \ | ||
140 | + } \ | ||
141 | + if (qc) { \ | ||
142 | + env->vfp.qc[0] = qc; \ | ||
143 | + } \ | ||
144 | + mve_advance_vpt(env); \ | ||
173 | + } | 145 | + } |
174 | + | 146 | + |
175 | + qdev_init_gpio_out(dev, s->out_irq, s->num_lines); | 147 | +#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ |
176 | +} | 148 | + DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ |
177 | + | 149 | + DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) |
178 | +static Property split_irq_properties[] = { | 150 | + |
179 | + DEFINE_PROP_UINT16("num-lines", SplitIRQ, num_lines, 1), | 151 | +#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ |
180 | + DEFINE_PROP_END_OF_LIST(), | 152 | + DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ |
181 | +}; | 153 | + DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) |
182 | + | 154 | + |
183 | +static void split_irq_class_init(ObjectClass *klass, void *data) | 155 | +#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ |
184 | +{ | 156 | + DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ |
185 | + DeviceClass *dc = DEVICE_CLASS(klass); | 157 | + DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) |
186 | + | 158 | + |
187 | + /* No state to reset or migrate */ | 159 | +#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ |
188 | + dc->props = split_irq_properties; | 160 | + DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ |
189 | + dc->realize = split_irq_realize; | 161 | + DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) |
190 | + | 162 | + |
191 | + /* Reason: Needs to be wired up to work */ | 163 | +#define DO_SHRN_SB(N, M, SATP) \ |
192 | + dc->user_creatable = false; | 164 | + do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) |
193 | +} | 165 | +#define DO_SHRN_UB(N, M, SATP) \ |
194 | + | 166 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) |
195 | +static const TypeInfo split_irq_type_info = { | 167 | +#define DO_SHRUN_B(N, M, SATP) \ |
196 | + .name = TYPE_SPLIT_IRQ, | 168 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) |
197 | + .parent = TYPE_DEVICE, | 169 | + |
198 | + .instance_size = sizeof(SplitIRQ), | 170 | +#define DO_SHRN_SH(N, M, SATP) \ |
199 | + .instance_init = split_irq_init, | 171 | + do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) |
200 | + .class_init = split_irq_class_init, | 172 | +#define DO_SHRN_UH(N, M, SATP) \ |
201 | +}; | 173 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) |
202 | + | 174 | +#define DO_SHRUN_H(N, M, SATP) \ |
203 | +static void split_irq_register_types(void) | 175 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) |
204 | +{ | 176 | + |
205 | + type_register_static(&split_irq_type_info); | 177 | +#define DO_RSHRN_SB(N, M, SATP) \ |
206 | +} | 178 | + do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) |
207 | + | 179 | +#define DO_RSHRN_UB(N, M, SATP) \ |
208 | +type_init(split_irq_register_types) | 180 | + do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) |
181 | +#define DO_RSHRUN_B(N, M, SATP) \ | ||
182 | + do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) | ||
183 | + | ||
184 | +#define DO_RSHRN_SH(N, M, SATP) \ | ||
185 | + do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) | ||
186 | +#define DO_RSHRN_UH(N, M, SATP) \ | ||
187 | + do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) | ||
188 | +#define DO_RSHRUN_H(N, M, SATP) \ | ||
189 | + do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) | ||
190 | + | ||
191 | +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) | ||
192 | +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) | ||
193 | +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) | ||
194 | +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) | ||
195 | +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) | ||
196 | +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) | ||
197 | + | ||
198 | +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) | ||
199 | +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) | ||
200 | +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
201 | +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
202 | +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
203 | +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
204 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
205 | index XXXXXXX..XXXXXXX 100644 | ||
206 | --- a/target/arm/translate-mve.c | ||
207 | +++ b/target/arm/translate-mve.c | ||
208 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb) | ||
209 | DO_2SHIFT_N(VSHRNT, vshrnt) | ||
210 | DO_2SHIFT_N(VRSHRNB, vrshrnb) | ||
211 | DO_2SHIFT_N(VRSHRNT, vrshrnt) | ||
212 | +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) | ||
213 | +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) | ||
214 | +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) | ||
215 | +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) | ||
216 | +DO_2SHIFT_N(VQSHRUNB, vqshrunb) | ||
217 | +DO_2SHIFT_N(VQSHRUNT, vqshrunt) | ||
218 | +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) | ||
219 | +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) | ||
220 | +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
221 | +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
222 | +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
223 | +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
209 | -- | 224 | -- |
210 | 2.16.2 | 225 | 2.20.1 |
211 | 226 | ||
212 | 227 | diff view generated by jsdifflib |
1 | Create an "idau" property on the armv7m container object which | 1 | Implement the MVE VSHLC insn, which performs a shift left of the |
---|---|---|---|
2 | we can forward to the CPU object. Annoyingly, we can't use | 2 | entire vector with carry in bits provided from a general purpose |
3 | object_property_add_alias() because the CPU object we want to | 3 | register and carry out bits written back to that register. |
4 | forward to doesn't exist until the armv7m container is realized. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-6-peter.maydell@linaro.org | 7 | Message-id: 20210628135835.6690-14-peter.maydell@linaro.org |
9 | --- | 8 | --- |
10 | include/hw/arm/armv7m.h | 3 +++ | 9 | target/arm/helper-mve.h | 2 ++ |
11 | hw/arm/armv7m.c | 9 +++++++++ | 10 | target/arm/mve.decode | 2 ++ |
12 | 2 files changed, 12 insertions(+) | 11 | target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ |
12 | target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 72 insertions(+) | ||
13 | 14 | ||
14 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/armv7m.h | 17 | --- a/target/arm/helper-mve.h |
17 | +++ b/include/hw/arm/armv7m.h | 18 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
19 | 20 | DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
20 | #include "hw/sysbus.h" | 21 | DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | #include "hw/intc/armv7m_nvic.h" | 22 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | +#include "target/arm/idau.h" | 23 | + |
23 | 24 | +DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | |
24 | #define TYPE_BITBAND "ARM,bitband-memory" | 25 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
25 | #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | ||
26 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
27 | * + Property "memory": MemoryRegion defining the physical address space | ||
28 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
29 | * devices will be automatically layered on top of this view.) | ||
30 | + * + Property "idau": IDAU interface (forwarded to CPU object) | ||
31 | */ | ||
32 | typedef struct ARMv7MState { | ||
33 | /*< private >*/ | ||
34 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
35 | char *cpu_type; | ||
36 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
37 | MemoryRegion *board_memory; | ||
38 | + Object *idau; | ||
39 | } ARMv7MState; | ||
40 | |||
41 | #endif | ||
42 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/hw/arm/armv7m.c | 27 | --- a/target/arm/mve.decode |
45 | +++ b/hw/arm/armv7m.c | 28 | +++ b/target/arm/mve.decode |
46 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
47 | #include "sysemu/qtest.h" | 30 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
48 | #include "qemu/error-report.h" | 31 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
49 | #include "exec/address-spaces.h" | 32 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h |
50 | +#include "target/arm/idau.h" | 33 | + |
51 | 34 | +VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd | |
52 | /* Bitbanded IO. Each word corresponds to a single bit. */ | 35 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
53 | 36 | index XXXXXXX..XXXXXXX 100644 | |
54 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 37 | --- a/target/arm/mve_helper.c |
55 | 38 | +++ b/target/arm/mve_helper.c | |
56 | object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", | 39 | @@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) |
57 | &error_abort); | 40 | DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) |
58 | + if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { | 41 | DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) |
59 | + object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); | 42 | DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) |
60 | + if (err != NULL) { | 43 | + |
61 | + error_propagate(errp, err); | 44 | +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, |
62 | + return; | 45 | + uint32_t shift) |
46 | +{ | ||
47 | + uint32_t *d = vd; | ||
48 | + uint16_t mask = mve_element_mask(env); | ||
49 | + unsigned e; | ||
50 | + uint32_t r; | ||
51 | + | ||
52 | + /* | ||
53 | + * For each 32-bit element, we shift it left, bringing in the | ||
54 | + * low 'shift' bits of rdm at the bottom. Bits shifted out at | ||
55 | + * the top become the new rdm, if the predicate mask permits. | ||
56 | + * The final rdm value is returned to update the register. | ||
57 | + * shift == 0 here means "shift by 32 bits". | ||
58 | + */ | ||
59 | + if (shift == 0) { | ||
60 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
61 | + r = rdm; | ||
62 | + if (mask & 1) { | ||
63 | + rdm = d[H4(e)]; | ||
64 | + } | ||
65 | + mergemask(&d[H4(e)], r, mask); | ||
66 | + } | ||
67 | + } else { | ||
68 | + uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); | ||
69 | + | ||
70 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
71 | + r = (d[H4(e)] << shift) | (rdm & shiftmask); | ||
72 | + if (mask & 1) { | ||
73 | + rdm = d[H4(e)] >> (32 - shift); | ||
74 | + } | ||
75 | + mergemask(&d[H4(e)], r, mask); | ||
63 | + } | 76 | + } |
64 | + } | 77 | + } |
65 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | 78 | + mve_advance_vpt(env); |
66 | if (err != NULL) { | 79 | + return rdm; |
67 | error_propagate(errp, err); | 80 | +} |
68 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | 81 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
69 | DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), | 82 | index XXXXXXX..XXXXXXX 100644 |
70 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | 83 | --- a/target/arm/translate-mve.c |
71 | MemoryRegion *), | 84 | +++ b/target/arm/translate-mve.c |
72 | + DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | 85 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) |
73 | DEFINE_PROP_END_OF_LIST(), | 86 | DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) |
74 | }; | 87 | DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) |
75 | 88 | DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | |
89 | + | ||
90 | +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) | ||
91 | +{ | ||
92 | + /* | ||
93 | + * Whole Vector Left Shift with Carry. The carry is taken | ||
94 | + * from a general purpose register and written back there. | ||
95 | + * An imm of 0 means "shift by 32". | ||
96 | + */ | ||
97 | + TCGv_ptr qd; | ||
98 | + TCGv_i32 rdm; | ||
99 | + | ||
100 | + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { | ||
101 | + return false; | ||
102 | + } | ||
103 | + if (a->rdm == 13 || a->rdm == 15) { | ||
104 | + /* CONSTRAINED UNPREDICTABLE: we UNDEF */ | ||
105 | + return false; | ||
106 | + } | ||
107 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
108 | + return true; | ||
109 | + } | ||
110 | + | ||
111 | + qd = mve_qreg_ptr(a->qd); | ||
112 | + rdm = load_reg(s, a->rdm); | ||
113 | + gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); | ||
114 | + store_reg(s, a->rdm, rdm); | ||
115 | + tcg_temp_free_ptr(qd); | ||
116 | + mve_update_eci(s); | ||
117 | + return true; | ||
118 | +} | ||
76 | -- | 119 | -- |
77 | 2.16.2 | 120 | 2.20.1 |
78 | 121 | ||
79 | 122 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Create an "init-svtor" property on the armv7m container | ||
2 | object which we can forward to the CPU object. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20180220180325.29818-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | include/hw/arm/armv7m.h | 2 ++ | ||
9 | hw/arm/armv7m.c | 9 +++++++++ | ||
10 | 2 files changed, 11 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/armv7m.h | ||
15 | +++ b/include/hw/arm/armv7m.h | ||
16 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
17 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
18 | * devices will be automatically layered on top of this view.) | ||
19 | * + Property "idau": IDAU interface (forwarded to CPU object) | ||
20 | + * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) | ||
21 | */ | ||
22 | typedef struct ARMv7MState { | ||
23 | /*< private >*/ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
25 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
26 | MemoryRegion *board_memory; | ||
27 | Object *idau; | ||
28 | + uint32_t init_svtor; | ||
29 | } ARMv7MState; | ||
30 | |||
31 | #endif | ||
32 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/armv7m.c | ||
35 | +++ b/hw/arm/armv7m.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
37 | return; | ||
38 | } | ||
39 | } | ||
40 | + if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { | ||
41 | + object_property_set_uint(OBJECT(s->cpu), s->init_svtor, | ||
42 | + "init-svtor", &err); | ||
43 | + if (err != NULL) { | ||
44 | + error_propagate(errp, err); | ||
45 | + return; | ||
46 | + } | ||
47 | + } | ||
48 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
49 | if (err != NULL) { | ||
50 | error_propagate(errp, err); | ||
51 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
52 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
53 | MemoryRegion *), | ||
54 | DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
55 | + DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), | ||
56 | DEFINE_PROP_END_OF_LIST(), | ||
57 | }; | ||
58 | |||
59 | -- | ||
60 | 2.16.2 | ||
61 | |||
62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the definition of the struct for the unimplemented-device | ||
2 | from unimp.c to unimp.h, so that users can embed the struct | ||
3 | in their own device structs if they prefer. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-10-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/misc/unimp.h | 10 ++++++++++ | ||
11 | hw/misc/unimp.c | 10 ---------- | ||
12 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/misc/unimp.h | ||
17 | +++ b/include/hw/misc/unimp.h | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" | ||
21 | |||
22 | +#define UNIMPLEMENTED_DEVICE(obj) \ | ||
23 | + OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
24 | + | ||
25 | +typedef struct { | ||
26 | + SysBusDevice parent_obj; | ||
27 | + MemoryRegion iomem; | ||
28 | + char *name; | ||
29 | + uint64_t size; | ||
30 | +} UnimplementedDeviceState; | ||
31 | + | ||
32 | /** | ||
33 | * create_unimplemented_device: create and map a dummy device | ||
34 | * @name: name of the device for debug logging | ||
35 | diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/misc/unimp.c | ||
38 | +++ b/hw/misc/unimp.c | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | #include "qemu/log.h" | ||
41 | #include "qapi/error.h" | ||
42 | |||
43 | -#define UNIMPLEMENTED_DEVICE(obj) \ | ||
44 | - OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
45 | - | ||
46 | -typedef struct { | ||
47 | - SysBusDevice parent_obj; | ||
48 | - MemoryRegion iomem; | ||
49 | - char *name; | ||
50 | - uint64_t size; | ||
51 | -} UnimplementedDeviceState; | ||
52 | - | ||
53 | static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size) | ||
54 | { | ||
55 | UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
56 | -- | ||
57 | 2.16.2 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The or-irq.h header file is missing the customary guard against | ||
2 | multiple inclusion, which means compilation fails if it gets | ||
3 | included twice. Fix the omission. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-11-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/or-irq.h | 5 +++++ | ||
11 | 1 file changed, 5 insertions(+) | ||
12 | |||
13 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/or-irq.h | ||
16 | +++ b/include/hw/or-irq.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * THE SOFTWARE. | ||
19 | */ | ||
20 | |||
21 | +#ifndef HW_OR_IRQ_H | ||
22 | +#define HW_OR_IRQ_H | ||
23 | + | ||
24 | #include "hw/irq.h" | ||
25 | #include "hw/sysbus.h" | ||
26 | #include "qom/object.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct OrIRQState { | ||
28 | bool levels[MAX_OR_LINES]; | ||
29 | uint16_t num_lines; | ||
30 | }; | ||
31 | + | ||
32 | +#endif | ||
33 | -- | ||
34 | 2.16.2 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The function qdev_init_gpio_in_named() passes the DeviceState pointer | ||
2 | as the opaque data pointor for the irq handler function. Usually | ||
3 | this is what you want, but in some cases it would be helpful to use | ||
4 | some other data pointer. | ||
5 | 1 | ||
6 | Add a new function qdev_init_gpio_in_named_with_opaque() which allows | ||
7 | the caller to specify the data pointer they want. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180220180325.29818-12-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/hw/qdev-core.h | 30 ++++++++++++++++++++++++++++-- | ||
15 | hw/core/qdev.c | 8 +++++--- | ||
16 | 2 files changed, 33 insertions(+), 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/qdev-core.h | ||
21 | +++ b/include/hw/qdev-core.h | ||
22 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
23 | /* GPIO inputs also double as IRQ sinks. */ | ||
24 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
25 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
26 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
27 | - const char *name, int n); | ||
28 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
29 | const char *name, int n); | ||
30 | +/** | ||
31 | + * qdev_init_gpio_in_named_with_opaque: create an array of input GPIO lines | ||
32 | + * for the specified device | ||
33 | + * | ||
34 | + * @dev: Device to create input GPIOs for | ||
35 | + * @handler: Function to call when GPIO line value is set | ||
36 | + * @opaque: Opaque data pointer to pass to @handler | ||
37 | + * @name: Name of the GPIO input (must be unique for this device) | ||
38 | + * @n: Number of GPIO lines in this input set | ||
39 | + */ | ||
40 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
41 | + qemu_irq_handler handler, | ||
42 | + void *opaque, | ||
43 | + const char *name, int n); | ||
44 | + | ||
45 | +/** | ||
46 | + * qdev_init_gpio_in_named: create an array of input GPIO lines | ||
47 | + * for the specified device | ||
48 | + * | ||
49 | + * Like qdev_init_gpio_in_named_with_opaque(), but the opaque pointer | ||
50 | + * passed to the handler is @dev (which is the most commonly desired behaviour). | ||
51 | + */ | ||
52 | +static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
53 | + qemu_irq_handler handler, | ||
54 | + const char *name, int n) | ||
55 | +{ | ||
56 | + qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
57 | +} | ||
58 | |||
59 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
60 | const char *name); | ||
61 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/core/qdev.c | ||
64 | +++ b/hw/core/qdev.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, | ||
66 | return ngl; | ||
67 | } | ||
68 | |||
69 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
70 | - const char *name, int n) | ||
71 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
72 | + qemu_irq_handler handler, | ||
73 | + void *opaque, | ||
74 | + const char *name, int n) | ||
75 | { | ||
76 | int i; | ||
77 | NamedGPIOList *gpio_list = qdev_get_named_gpio_list(dev, name); | ||
78 | |||
79 | assert(gpio_list->num_out == 0 || !name); | ||
80 | gpio_list->in = qemu_extend_irqs(gpio_list->in, gpio_list->num_in, handler, | ||
81 | - dev, n); | ||
82 | + opaque, n); | ||
83 | |||
84 | if (!name) { | ||
85 | name = "unnamed-gpio-in"; | ||
86 | -- | ||
87 | 2.16.2 | ||
88 | |||
89 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE VADDLV insn; this is similar to VADDV, except |
---|---|---|---|
2 | that it accumulates 32-bit elements into a 64-bit accumulator | ||
3 | stored in a pair of general-purpose registers. | ||
2 | 4 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20180228193125.20577-14-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210628135835.6690-15-peter.maydell@linaro.org | ||
7 | --- | 8 | --- |
8 | target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 9 | target/arm/helper-mve.h | 3 ++ |
9 | 1 file changed, 68 insertions(+) | 10 | target/arm/mve.decode | 6 +++- |
11 | target/arm/mve_helper.c | 19 ++++++++++++ | ||
12 | target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 90 insertions(+), 1 deletion(-) | ||
10 | 14 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 17 | --- a/target/arm/helper-mve.h |
14 | +++ b/target/arm/translate.c | 18 | +++ b/target/arm/helper-mve.h |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
16 | return 0; | 20 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
21 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
22 | |||
23 | +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) | ||
24 | +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) | ||
25 | + | ||
26 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
27 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
28 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/mve.decode | ||
32 | +++ b/target/arm/mve.decode | ||
33 | @@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
34 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
35 | |||
36 | # Vector add across vector | ||
37 | -VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
38 | +{ | ||
39 | + VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
40 | + VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \ | ||
41 | + rdahi=%rdahi rdalo=%rdalo | ||
42 | +} | ||
43 | |||
44 | # Predicate operations | ||
45 | %mask_22_13 22:1 13:3 | ||
46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/mve_helper.c | ||
49 | +++ b/target/arm/mve_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t) | ||
51 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
52 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
53 | |||
54 | +#define DO_VADDLV(OP, TYPE, LTYPE) \ | ||
55 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ | ||
56 | + uint64_t ra) \ | ||
57 | + { \ | ||
58 | + uint16_t mask = mve_element_mask(env); \ | ||
59 | + unsigned e; \ | ||
60 | + TYPE *m = vm; \ | ||
61 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
62 | + if (mask & 1) { \ | ||
63 | + ra += (LTYPE)m[H4(e)]; \ | ||
64 | + } \ | ||
65 | + } \ | ||
66 | + mve_advance_vpt(env); \ | ||
67 | + return ra; \ | ||
68 | + } \ | ||
69 | + | ||
70 | +DO_VADDLV(vaddlv_s, int32_t, int64_t) | ||
71 | +DO_VADDLV(vaddlv_u, uint32_t, uint64_t) | ||
72 | + | ||
73 | /* Shifts by immediate */ | ||
74 | #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
75 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
76 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/translate-mve.c | ||
79 | +++ b/target/arm/translate-mve.c | ||
80 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
81 | return true; | ||
17 | } | 82 | } |
18 | 83 | ||
19 | +/* Advanced SIMD three registers of the same length extension. | 84 | +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) |
20 | + * 31 25 23 22 20 16 12 11 10 9 8 3 0 | ||
21 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
22 | + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
23 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
24 | + */ | ||
25 | +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
26 | +{ | 85 | +{ |
27 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | 86 | + /* |
28 | + int rd, rn, rm, rot, size, opr_sz; | 87 | + * Vector Add Long Across Vector: accumulate the 32-bit |
29 | + TCGv_ptr fpst; | 88 | + * elements of the vector into a 64-bit result stored in |
30 | + bool q; | 89 | + * a pair of general-purpose registers. |
90 | + * No need to check Qm's bank: it is only 3 bits in decode. | ||
91 | + */ | ||
92 | + TCGv_ptr qm; | ||
93 | + TCGv_i64 rda; | ||
94 | + TCGv_i32 rdalo, rdahi; | ||
31 | + | 95 | + |
32 | + q = extract32(insn, 6, 1); | 96 | + if (!dc_isar_feature(aa32_mve, s)) { |
33 | + VFP_DREG_D(rd, insn); | 97 | + return false; |
34 | + VFP_DREG_N(rn, insn); | 98 | + } |
35 | + VFP_DREG_M(rm, insn); | 99 | + /* |
36 | + if ((rd | rn | rm) & q) { | 100 | + * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related |
37 | + return 1; | 101 | + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. |
102 | + */ | ||
103 | + if (a->rdahi == 13 || a->rdahi == 15) { | ||
104 | + return false; | ||
105 | + } | ||
106 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
107 | + return true; | ||
38 | + } | 108 | + } |
39 | + | 109 | + |
40 | + if ((insn & 0xfe200f10) == 0xfc200800) { | 110 | + /* |
41 | + /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ | 111 | + * This insn is subject to beat-wise execution. Partial execution |
42 | + size = extract32(insn, 20, 1); | 112 | + * of an A=0 (no-accumulate) insn which does not execute the first |
43 | + rot = extract32(insn, 23, 2); | 113 | + * beat must start with the current value of RdaHi:RdaLo, not zero. |
44 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | 114 | + */ |
45 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | 115 | + if (a->a || mve_skip_first_beat(s)) { |
46 | + return 1; | 116 | + /* Accumulate input from RdaHi:RdaLo */ |
47 | + } | 117 | + rda = tcg_temp_new_i64(); |
48 | + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | 118 | + rdalo = load_reg(s, a->rdalo); |
49 | + } else if ((insn & 0xfea00f10) == 0xfc800800) { | 119 | + rdahi = load_reg(s, a->rdahi); |
50 | + /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | 120 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
51 | + size = extract32(insn, 20, 1); | 121 | + tcg_temp_free_i32(rdalo); |
52 | + rot = extract32(insn, 24, 1); | 122 | + tcg_temp_free_i32(rdahi); |
53 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
54 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
55 | + return 1; | ||
56 | + } | ||
57 | + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
58 | + } else { | 123 | + } else { |
59 | + return 1; | 124 | + /* Accumulate starting at zero */ |
125 | + rda = tcg_const_i64(0); | ||
60 | + } | 126 | + } |
61 | + | 127 | + |
62 | + if (s->fp_excp_el) { | 128 | + qm = mve_qreg_ptr(a->qm); |
63 | + gen_exception_insn(s, 4, EXCP_UDEF, | 129 | + if (a->u) { |
64 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | 130 | + gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); |
65 | + return 0; | 131 | + } else { |
132 | + gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); | ||
66 | + } | 133 | + } |
67 | + if (!s->vfp_enabled) { | 134 | + tcg_temp_free_ptr(qm); |
68 | + return 1; | ||
69 | + } | ||
70 | + | 135 | + |
71 | + opr_sz = (1 + q) * 8; | 136 | + rdalo = tcg_temp_new_i32(); |
72 | + fpst = get_fpstatus_ptr(1); | 137 | + rdahi = tcg_temp_new_i32(); |
73 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | 138 | + tcg_gen_extrl_i64_i32(rdalo, rda); |
74 | + vfp_reg_offset(1, rn), | 139 | + tcg_gen_extrh_i64_i32(rdahi, rda); |
75 | + vfp_reg_offset(1, rm), fpst, | 140 | + store_reg(s, a->rdalo, rdalo); |
76 | + opr_sz, opr_sz, rot, fn_gvec_ptr); | 141 | + store_reg(s, a->rdahi, rdahi); |
77 | + tcg_temp_free_ptr(fpst); | 142 | + tcg_temp_free_i64(rda); |
78 | + return 0; | 143 | + mve_update_eci(s); |
144 | + return true; | ||
79 | +} | 145 | +} |
80 | + | 146 | + |
81 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 147 | static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) |
82 | { | 148 | { |
83 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | 149 | TCGv_ptr qd; |
84 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
85 | } | ||
86 | } | ||
87 | } | ||
88 | + } else if ((insn & 0x0e000a00) == 0x0c000800 | ||
89 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
90 | + if (disas_neon_insn_3same_ext(s, insn)) { | ||
91 | + goto illegal_op; | ||
92 | + } | ||
93 | + return; | ||
94 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
95 | /* Coprocessor double register transfer. */ | ||
96 | ARCH(5TE); | ||
97 | -- | 150 | -- |
98 | 2.16.2 | 151 | 2.20.1 |
99 | 152 | ||
100 | 153 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The MVE extension to v8.1M includes some new shift instructions which |
---|---|---|---|
2 | 2 | sit entirely within the non-coprocessor part of the encoding space | |
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | and which operate only on general-purpose registers. They take up |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | the space which was previously UNPREDICTABLE MOVS and ORRS encodings |
5 | Message-id: 20180228193125.20577-9-richard.henderson@linaro.org | 5 | with Rm == 13 or 15. |
6 | |||
7 | Implement the long shifts by immediate, which perform shifts on a | ||
8 | pair of general-purpose registers treated as a 64-bit quantity, with | ||
9 | an immediate shift count between 1 and 32. | ||
10 | |||
11 | Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for | ||
12 | the Rm==13,15 case, we need to explicitly emit code to UNDEF for the | ||
13 | cases where v8.1M now requires that. (Trying to change MOVS and ORRS | ||
14 | is too difficult, because the functions that generate the code are | ||
15 | shared between a dozen different kinds of arithmetic or logical | ||
16 | instruction for all A32, T16 and T32 encodings, and for some insns | ||
17 | and some encodings Rm==13,15 are valid.) | ||
18 | |||
19 | We make the helper functions we need for UQSHLL and SQSHLL take | ||
20 | a 32-bit value which the helper casts to int8_t because we'll need | ||
21 | these helpers also for the shift-by-register insns, where the shift | ||
22 | count might be < 0 or > 32. | ||
23 | |||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20210628135835.6690-16-peter.maydell@linaro.org | ||
7 | --- | 27 | --- |
8 | target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- | 28 | target/arm/helper-mve.h | 3 ++ |
9 | 1 file changed, 42 insertions(+), 4 deletions(-) | 29 | target/arm/translate.h | 1 + |
10 | 30 | target/arm/t32.decode | 28 +++++++++++++ | |
31 | target/arm/mve_helper.c | 10 +++++ | ||
32 | target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++ | ||
33 | 5 files changed, 132 insertions(+) | ||
34 | |||
35 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/helper-mve.h | ||
38 | +++ b/target/arm/helper-mve.h | ||
39 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | |||
42 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | ||
43 | + | ||
44 | +DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
45 | +DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
46 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/translate.h | ||
49 | +++ b/target/arm/translate.h | ||
50 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
51 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
52 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
53 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
54 | +typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
55 | |||
56 | /** | ||
57 | * arm_tbflags_from_tb: | ||
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/t32.decode | ||
61 | +++ b/target/arm/t32.decode | ||
62 | @@ -XXX,XX +XXX,XX @@ | ||
63 | &mcr !extern cp opc1 crn crm opc2 rt | ||
64 | &mcrr !extern cp opc1 crm rt rt2 | ||
65 | |||
66 | +&mve_shl_ri rdalo rdahi shim | ||
67 | + | ||
68 | +# rdahi: bits [3:1] from insn, bit 0 is 1 | ||
69 | +# rdalo: bits [3:1] from insn, bit 0 is 0 | ||
70 | +%rdahi_9 9:3 !function=times_2_plus_1 | ||
71 | +%rdalo_17 17:3 !function=times_2 | ||
72 | + | ||
73 | # Data-processing (register) | ||
74 | |||
75 | %imm5_12_6 12:3 6:2 | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ | ||
78 | &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 | ||
79 | |||
80 | +@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
81 | + &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
82 | + | ||
83 | { | ||
84 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
85 | AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi | ||
86 | } | ||
87 | BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
88 | { | ||
89 | + # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS | ||
90 | + # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE | ||
91 | + # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that | ||
92 | + # they explicitly call unallocated_encoding() for cases that must UNDEF | ||
93 | + # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting | ||
94 | + # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
95 | + # handling them as r13 and r15 accesses with the same semantics as A32). | ||
96 | + [ | ||
97 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
98 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
99 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
100 | + | ||
101 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
102 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
103 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
104 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
105 | + ] | ||
106 | + | ||
107 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
108 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
109 | } | ||
110 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/target/arm/mve_helper.c | ||
113 | +++ b/target/arm/mve_helper.c | ||
114 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
115 | mve_advance_vpt(env); | ||
116 | return rdm; | ||
117 | } | ||
118 | + | ||
119 | +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
120 | +{ | ||
121 | + return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
122 | +} | ||
123 | + | ||
124 | +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
125 | +{ | ||
126 | + return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
127 | +} | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 128 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
12 | index XXXXXXX..XXXXXXX 100644 | 129 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 130 | --- a/target/arm/translate.c |
14 | +++ b/target/arm/translate.c | 131 | +++ b/target/arm/translate.c |
15 | @@ -XXX,XX +XXX,XX @@ static const char *regnames[] = | 132 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a) |
16 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | 133 | return true; |
17 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | 134 | } |
18 | 135 | ||
19 | +/* Function prototypes for gen_ functions calling Neon helpers. */ | 136 | +/* |
20 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | 137 | + * v8.1M MVE wide-shifts |
21 | + TCGv_i32, TCGv_i32); | 138 | + */ |
22 | + | 139 | +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a, |
23 | /* initialize TCG globals. */ | 140 | + WideShiftImmFn *fn) |
24 | void arm_translate_init(void) | 141 | +{ |
25 | { | 142 | + TCGv_i64 rda; |
26 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 143 | + TCGv_i32 rdalo, rdahi; |
27 | } | 144 | + |
28 | neon_store_reg64(cpu_V0, rd + pass); | 145 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
29 | } | 146 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
30 | - | 147 | + return false; |
31 | - | 148 | + } |
32 | break; | 149 | + if (a->rdahi == 15) { |
33 | - default: /* 14 and 15 are RESERVED */ | 150 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ |
34 | - return 1; | 151 | + return false; |
35 | + case 14: /* VQRDMLAH scalar */ | 152 | + } |
36 | + case 15: /* VQRDMLSH scalar */ | 153 | + if (!dc_isar_feature(aa32_mve, s) || |
37 | + { | 154 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
38 | + NeonGenThreeOpEnvFn *fn; | 155 | + a->rdahi == 13) { |
39 | + | 156 | + /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */ |
40 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | 157 | + unallocated_encoding(s); |
41 | + return 1; | 158 | + return true; |
42 | + } | 159 | + } |
43 | + if (u && ((rd | rn) & 1)) { | 160 | + |
44 | + return 1; | 161 | + if (a->shim == 0) { |
45 | + } | 162 | + a->shim = 32; |
46 | + if (op == 14) { | 163 | + } |
47 | + if (size == 1) { | 164 | + |
48 | + fn = gen_helper_neon_qrdmlah_s16; | 165 | + rda = tcg_temp_new_i64(); |
49 | + } else { | 166 | + rdalo = load_reg(s, a->rdalo); |
50 | + fn = gen_helper_neon_qrdmlah_s32; | 167 | + rdahi = load_reg(s, a->rdahi); |
51 | + } | 168 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
52 | + } else { | 169 | + |
53 | + if (size == 1) { | 170 | + fn(rda, rda, a->shim); |
54 | + fn = gen_helper_neon_qrdmlsh_s16; | 171 | + |
55 | + } else { | 172 | + tcg_gen_extrl_i64_i32(rdalo, rda); |
56 | + fn = gen_helper_neon_qrdmlsh_s32; | 173 | + tcg_gen_extrh_i64_i32(rdahi, rda); |
57 | + } | 174 | + store_reg(s, a->rdalo, rdalo); |
58 | + } | 175 | + store_reg(s, a->rdahi, rdahi); |
59 | + | 176 | + tcg_temp_free_i64(rda); |
60 | + tmp2 = neon_get_scalar(size, rm); | 177 | + |
61 | + for (pass = 0; pass < (u ? 4 : 2); pass++) { | 178 | + return true; |
62 | + tmp = neon_load_reg(rn, pass); | 179 | +} |
63 | + tmp3 = neon_load_reg(rd, pass); | 180 | + |
64 | + fn(tmp, cpu_env, tmp, tmp2, tmp3); | 181 | +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
65 | + tcg_temp_free_i32(tmp3); | 182 | +{ |
66 | + neon_store_reg(rd, pass, tmp); | 183 | + return do_mve_shl_ri(s, a, tcg_gen_sari_i64); |
67 | + } | 184 | +} |
68 | + tcg_temp_free_i32(tmp2); | 185 | + |
69 | + } | 186 | +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a) |
70 | + break; | 187 | +{ |
71 | + default: | 188 | + return do_mve_shl_ri(s, a, tcg_gen_shli_i64); |
72 | + g_assert_not_reached(); | 189 | +} |
73 | } | 190 | + |
74 | } | 191 | +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
75 | } else { /* size == 3 */ | 192 | +{ |
193 | + return do_mve_shl_ri(s, a, tcg_gen_shri_i64); | ||
194 | +} | ||
195 | + | ||
196 | +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
197 | +{ | ||
198 | + gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
199 | +} | ||
200 | + | ||
201 | +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
202 | +{ | ||
203 | + return do_mve_shl_ri(s, a, gen_mve_sqshll); | ||
204 | +} | ||
205 | + | ||
206 | +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
207 | +{ | ||
208 | + gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
209 | +} | ||
210 | + | ||
211 | +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
212 | +{ | ||
213 | + return do_mve_shl_ri(s, a, gen_mve_uqshll); | ||
214 | +} | ||
215 | + | ||
216 | +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
217 | +{ | ||
218 | + return do_mve_shl_ri(s, a, gen_srshr64_i64); | ||
219 | +} | ||
220 | + | ||
221 | +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
222 | +{ | ||
223 | + return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
224 | +} | ||
225 | + | ||
226 | /* | ||
227 | * Multiply and multiply accumulate | ||
228 | */ | ||
76 | -- | 229 | -- |
77 | 2.16.2 | 230 | 2.20.1 |
78 | 231 | ||
79 | 232 | diff view generated by jsdifflib |
1 | Add a model of the TrustZone peripheral protection controller (PPC), | 1 | Implement the MVE long shifts by register, which perform shifts on a |
---|---|---|---|
2 | which is used to gate transactions to non-TZ-aware peripherals so | 2 | pair of general-purpose registers treated as a 64-bit quantity, with |
3 | that secure software can configure them to not be accessible to | 3 | the shift count in another general-purpose register, which might be |
4 | non-secure software. | 4 | either positive or negative. |
5 | |||
6 | Like the long-shifts-by-immediate, these encodings sit in the space | ||
7 | that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15. | ||
8 | Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and | ||
9 | also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases), | ||
10 | we have to move the CSEL pattern into the same decodetree group. | ||
5 | 11 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-15-peter.maydell@linaro.org | 14 | Message-id: 20210628135835.6690-17-peter.maydell@linaro.org |
9 | --- | 15 | --- |
10 | hw/misc/Makefile.objs | 2 + | 16 | target/arm/helper-mve.h | 6 +++ |
11 | include/hw/misc/tz-ppc.h | 101 ++++++++++++++ | 17 | target/arm/translate.h | 1 + |
12 | hw/misc/tz-ppc.c | 302 ++++++++++++++++++++++++++++++++++++++++ | 18 | target/arm/t32.decode | 16 +++++-- |
13 | default-configs/arm-softmmu.mak | 2 + | 19 | target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++ |
14 | hw/misc/trace-events | 11 ++ | 20 | target/arm/translate.c | 69 ++++++++++++++++++++++++++++++ |
15 | 5 files changed, 418 insertions(+) | 21 | 5 files changed, 182 insertions(+), 3 deletions(-) |
16 | create mode 100644 include/hw/misc/tz-ppc.h | 22 | |
17 | create mode 100644 hw/misc/tz-ppc.c | 23 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
18 | 24 | index XXXXXXX..XXXXXXX 100644 | |
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 25 | --- a/target/arm/helper-mve.h |
20 | index XXXXXXX..XXXXXXX 100644 | 26 | +++ b/target/arm/helper-mve.h |
21 | --- a/hw/misc/Makefile.objs | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | +++ b/hw/misc/Makefile.objs | 28 | |
23 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 29 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) |
24 | obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 30 | |
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 31 | +DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) |
26 | 32 | +DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32) | |
27 | +obj-$(CONFIG_TZ_PPC) += tz-ppc.o | 33 | DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
28 | + | 34 | DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 35 | +DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) |
30 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | 36 | +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
31 | obj-$(CONFIG_AUX) += auxbus.o | 37 | +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
32 | diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h | 38 | +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
33 | new file mode 100644 | 39 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
34 | index XXXXXXX..XXXXXXX | 40 | index XXXXXXX..XXXXXXX 100644 |
35 | --- /dev/null | 41 | --- a/target/arm/translate.h |
36 | +++ b/include/hw/misc/tz-ppc.h | 42 | +++ b/target/arm/translate.h |
43 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
44 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
45 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
46 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
47 | +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
48 | |||
49 | /** | ||
50 | * arm_tbflags_from_tb: | ||
51 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/t32.decode | ||
54 | +++ b/target/arm/t32.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ | 55 | @@ -XXX,XX +XXX,XX @@ |
38 | +/* | 56 | &mcrr !extern cp opc1 crm rt rt2 |
39 | + * ARM TrustZone peripheral protection controller emulation | 57 | |
40 | + * | 58 | &mve_shl_ri rdalo rdahi shim |
41 | + * Copyright (c) 2018 Linaro Limited | 59 | +&mve_shl_rr rdalo rdahi rm |
42 | + * Written by Peter Maydell | 60 | |
43 | + * | 61 | # rdahi: bits [3:1] from insn, bit 0 is 1 |
44 | + * This program is free software; you can redistribute it and/or modify | 62 | # rdalo: bits [3:1] from insn, bit 0 is 0 |
45 | + * it under the terms of the GNU General Public License version 2 or | ||
46 | + * (at your option) any later version. | ||
47 | + */ | ||
48 | + | ||
49 | +/* This is a model of the TrustZone peripheral protection controller (PPC). | ||
50 | + * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM | ||
51 | + * (DDI 0571G): | ||
52 | + * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g | ||
53 | + * | ||
54 | + * The PPC sits in front of peripherals and allows secure software to | ||
55 | + * configure it to either pass through or reject transactions. | ||
56 | + * Rejected transactions may be configured to either be aborted, or to | ||
57 | + * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. | ||
58 | + * | ||
59 | + * The PPC has no register interface -- it is configured purely by a | ||
60 | + * collection of input signals from other hardware in the system. Typically | ||
61 | + * they are either hardwired or exposed in an ad-hoc register interface by | ||
62 | + * the SoC that uses the PPC. | ||
63 | + * | ||
64 | + * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC, | ||
65 | + * since the only difference between them is that the AHB version has a | ||
66 | + * "default" port which has no security checks applied. In QEMU the default | ||
67 | + * port can be emulated simply by wiring its downstream devices directly | ||
68 | + * into the parent address space, since the PPC does not need to intercept | ||
69 | + * transactions there. | ||
70 | + * | ||
71 | + * In the hardware, selection of which downstream port to use is done by | ||
72 | + * the user's decode logic asserting one of the hsel[] signals. In QEMU, | ||
73 | + * we provide 16 MMIO regions, one per port, and the user maps these into | ||
74 | + * the desired addresses to implement the address decode. | ||
75 | + * | ||
76 | + * QEMU interface: | ||
77 | + * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end | ||
78 | + * of each of the 16 ports of the PPC | ||
79 | + * + Property "port[0..15]": MemoryRegion defining the downstream device(s) | ||
80 | + * for each of the 16 ports of the PPC | ||
81 | + * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be | ||
82 | + * accessible to NonSecure transactions | ||
83 | + * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be | ||
84 | + * accessible to non-privileged transactions | ||
85 | + * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should | ||
86 | + * result in a transaction error, or 0 for the transaction to RAZ/WI | ||
87 | + * + Named GPIO input "irq_enable": set to 1 to enable interrupts | ||
88 | + * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt | ||
89 | + * + Named GPIO output "irq": set for a transaction-failed interrupt | ||
90 | + * + Property "NONSEC_MASK": if a bit is set in this mask then accesses to | ||
91 | + * the associated port do not have the TZ security check performed. (This | ||
92 | + * corresponds to the hardware allowing this to be set as a Verilog | ||
93 | + * parameter.) | ||
94 | + */ | ||
95 | + | ||
96 | +#ifndef TZ_PPC_H | ||
97 | +#define TZ_PPC_H | ||
98 | + | ||
99 | +#include "hw/sysbus.h" | ||
100 | + | ||
101 | +#define TYPE_TZ_PPC "tz-ppc" | ||
102 | +#define TZ_PPC(obj) OBJECT_CHECK(TZPPC, (obj), TYPE_TZ_PPC) | ||
103 | + | ||
104 | +#define TZ_NUM_PORTS 16 | ||
105 | + | ||
106 | +typedef struct TZPPC TZPPC; | ||
107 | + | ||
108 | +typedef struct TZPPCPort { | ||
109 | + TZPPC *ppc; | ||
110 | + MemoryRegion upstream; | ||
111 | + AddressSpace downstream_as; | ||
112 | + MemoryRegion *downstream; | ||
113 | +} TZPPCPort; | ||
114 | + | ||
115 | +struct TZPPC { | ||
116 | + /*< private >*/ | ||
117 | + SysBusDevice parent_obj; | ||
118 | + | ||
119 | + /*< public >*/ | ||
120 | + | ||
121 | + /* State: these just track the values of our input signals */ | ||
122 | + bool cfg_nonsec[TZ_NUM_PORTS]; | ||
123 | + bool cfg_ap[TZ_NUM_PORTS]; | ||
124 | + bool cfg_sec_resp; | ||
125 | + bool irq_enable; | ||
126 | + bool irq_clear; | ||
127 | + /* State: are we asserting irq ? */ | ||
128 | + bool irq_status; | ||
129 | + | ||
130 | + qemu_irq irq; | ||
131 | + | ||
132 | + /* Properties */ | ||
133 | + uint32_t nonsec_mask; | ||
134 | + | ||
135 | + TZPPCPort port[TZ_NUM_PORTS]; | ||
136 | +}; | ||
137 | + | ||
138 | +#endif | ||
139 | diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c | ||
140 | new file mode 100644 | ||
141 | index XXXXXXX..XXXXXXX | ||
142 | --- /dev/null | ||
143 | +++ b/hw/misc/tz-ppc.c | ||
144 | @@ -XXX,XX +XXX,XX @@ | 63 | @@ -XXX,XX +XXX,XX @@ |
145 | +/* | 64 | |
146 | + * ARM TrustZone peripheral protection controller emulation | 65 | @mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ |
147 | + * | 66 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 |
148 | + * Copyright (c) 2018 Linaro Limited | 67 | +@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ |
149 | + * Written by Peter Maydell | 68 | + &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 |
150 | + * | 69 | |
151 | + * This program is free software; you can redistribute it and/or modify | 70 | { |
152 | + * it under the terms of the GNU General Public License version 2 or | 71 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi |
153 | + * (at your option) any later version. | 72 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi |
154 | + */ | 73 | URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri |
155 | + | 74 | SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri |
156 | +#include "qemu/osdep.h" | 75 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri |
157 | +#include "qemu/log.h" | 76 | + |
158 | +#include "qapi/error.h" | 77 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr |
159 | +#include "trace.h" | 78 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr |
160 | +#include "hw/sysbus.h" | 79 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr |
161 | +#include "hw/registerfields.h" | 80 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr |
162 | +#include "hw/misc/tz-ppc.h" | 81 | + UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr |
163 | + | 82 | + SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr |
164 | +static void tz_ppc_update_irq(TZPPC *s) | 83 | ] |
165 | +{ | 84 | |
166 | + bool level = s->irq_status && s->irq_enable; | 85 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi |
167 | + | 86 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi |
168 | + trace_tz_ppc_update_irq(level); | 87 | + |
169 | + qemu_set_irq(s->irq, level); | 88 | + # v8.1M CSEL and friends |
170 | +} | 89 | + CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 |
171 | + | 90 | } |
172 | +static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) | 91 | { |
173 | +{ | 92 | MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi |
174 | + TZPPC *s = TZ_PPC(opaque); | 93 | @@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi |
175 | + | 94 | } |
176 | + assert(n < TZ_NUM_PORTS); | 95 | RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi |
177 | + trace_tz_ppc_cfg_nonsec(n, level); | 96 | |
178 | + s->cfg_nonsec[n] = level; | 97 | -# v8.1M CSEL and friends |
179 | +} | 98 | -CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 |
180 | + | 99 | - |
181 | +static void tz_ppc_cfg_ap(void *opaque, int n, int level) | 100 | # Data-processing (register-shifted register) |
182 | +{ | 101 | |
183 | + TZPPC *s = TZ_PPC(opaque); | 102 | MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ |
184 | + | 103 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
185 | + assert(n < TZ_NUM_PORTS); | 104 | index XXXXXXX..XXXXXXX 100644 |
186 | + trace_tz_ppc_cfg_ap(n, level); | 105 | --- a/target/arm/mve_helper.c |
187 | + s->cfg_ap[n] = level; | 106 | +++ b/target/arm/mve_helper.c |
188 | +} | 107 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, |
189 | + | 108 | return rdm; |
190 | +static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) | 109 | } |
191 | +{ | 110 | |
192 | + TZPPC *s = TZ_PPC(opaque); | 111 | +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) |
193 | + | 112 | +{ |
194 | + trace_tz_ppc_cfg_sec_resp(level); | 113 | + return do_sqrshl_d(n, -(int8_t)shift, false, NULL); |
195 | + s->cfg_sec_resp = level; | 114 | +} |
196 | +} | 115 | + |
197 | + | 116 | +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) |
198 | +static void tz_ppc_irq_enable(void *opaque, int n, int level) | 117 | +{ |
199 | +{ | 118 | + return do_uqrshl_d(n, (int8_t)shift, false, NULL); |
200 | + TZPPC *s = TZ_PPC(opaque); | 119 | +} |
201 | + | 120 | + |
202 | + trace_tz_ppc_irq_enable(level); | 121 | uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) |
203 | + s->irq_enable = level; | 122 | { |
204 | + tz_ppc_update_irq(s); | 123 | return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); |
205 | +} | 124 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) |
206 | + | 125 | { |
207 | +static void tz_ppc_irq_clear(void *opaque, int n, int level) | 126 | return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); |
208 | +{ | 127 | } |
209 | + TZPPC *s = TZ_PPC(opaque); | 128 | + |
210 | + | 129 | +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) |
211 | + trace_tz_ppc_irq_clear(level); | 130 | +{ |
212 | + | 131 | + return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); |
213 | + s->irq_clear = level; | 132 | +} |
214 | + if (level) { | 133 | + |
215 | + s->irq_status = false; | 134 | +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) |
216 | + tz_ppc_update_irq(s); | 135 | +{ |
217 | + } | 136 | + return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); |
218 | +} | 137 | +} |
219 | + | 138 | + |
220 | +static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) | 139 | +/* Operate on 64-bit values, but saturate at 48 bits */ |
221 | +{ | 140 | +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, |
222 | + /* Check whether to allow an access to port n; return true if | 141 | + bool round, uint32_t *sat) |
223 | + * the check passes, and false if the transaction must be blocked. | 142 | +{ |
224 | + * If the latter, the caller must check cfg_sec_resp to determine | 143 | + if (shift <= -48) { |
225 | + * whether to abort or RAZ/WI the transaction. | 144 | + /* Rounding the sign bit always produces 0. */ |
226 | + * The checks are: | 145 | + if (round) { |
227 | + * + nonsec_mask suppresses any check of the secure attribute | 146 | + return 0; |
228 | + * + otherwise, block if cfg_nonsec is 1 and transaction is secure, | 147 | + } |
229 | + * or if cfg_nonsec is 0 and transaction is non-secure | 148 | + return src >> 63; |
230 | + * + block if transaction is usermode and cfg_ap is 0 | 149 | + } else if (shift < 0) { |
231 | + */ | 150 | + if (round) { |
232 | + if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || | 151 | + src >>= -shift - 1; |
233 | + (attrs.user && !s->cfg_ap[n])) { | 152 | + return (src >> 1) + (src & 1); |
234 | + /* Block the transaction. */ | 153 | + } |
235 | + if (!s->irq_clear) { | 154 | + return src >> -shift; |
236 | + /* Note that holding irq_clear high suppresses interrupts */ | 155 | + } else if (shift < 48) { |
237 | + s->irq_status = true; | 156 | + int64_t val = src << shift; |
238 | + tz_ppc_update_irq(s); | 157 | + int64_t extval = sextract64(val, 0, 48); |
239 | + } | 158 | + if (!sat || val == extval) { |
159 | + return extval; | ||
160 | + } | ||
161 | + } else if (!sat || src == 0) { | ||
162 | + return 0; | ||
163 | + } | ||
164 | + | ||
165 | + *sat = 1; | ||
166 | + return (1ULL << 47) - (src >= 0); | ||
167 | +} | ||
168 | + | ||
169 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
170 | +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, | ||
171 | + bool round, uint32_t *sat) | ||
172 | +{ | ||
173 | + uint64_t val, extval; | ||
174 | + | ||
175 | + if (shift <= -(48 + round)) { | ||
176 | + return 0; | ||
177 | + } else if (shift < 0) { | ||
178 | + if (round) { | ||
179 | + val = src >> (-shift - 1); | ||
180 | + val = (val >> 1) + (val & 1); | ||
181 | + } else { | ||
182 | + val = src >> -shift; | ||
183 | + } | ||
184 | + extval = extract64(val, 0, 48); | ||
185 | + if (!sat || val == extval) { | ||
186 | + return extval; | ||
187 | + } | ||
188 | + } else if (shift < 48) { | ||
189 | + uint64_t val = src << shift; | ||
190 | + uint64_t extval = extract64(val, 0, 48); | ||
191 | + if (!sat || val == extval) { | ||
192 | + return extval; | ||
193 | + } | ||
194 | + } else if (!sat || src == 0) { | ||
195 | + return 0; | ||
196 | + } | ||
197 | + | ||
198 | + *sat = 1; | ||
199 | + return MAKE_64BIT_MASK(0, 48); | ||
200 | +} | ||
201 | + | ||
202 | +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
203 | +{ | ||
204 | + return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); | ||
205 | +} | ||
206 | + | ||
207 | +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
208 | +{ | ||
209 | + return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
210 | +} | ||
211 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/target/arm/translate.c | ||
214 | +++ b/target/arm/translate.c | ||
215 | @@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
216 | return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
217 | } | ||
218 | |||
219 | +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn) | ||
220 | +{ | ||
221 | + TCGv_i64 rda; | ||
222 | + TCGv_i32 rdalo, rdahi; | ||
223 | + | ||
224 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
225 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
240 | + return false; | 226 | + return false; |
241 | + } | 227 | + } |
228 | + if (a->rdahi == 15) { | ||
229 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | ||
230 | + return false; | ||
231 | + } | ||
232 | + if (!dc_isar_feature(aa32_mve, s) || | ||
233 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
234 | + a->rdahi == 13 || a->rm == 13 || a->rm == 15 || | ||
235 | + a->rm == a->rdahi || a->rm == a->rdalo) { | ||
236 | + /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
237 | + unallocated_encoding(s); | ||
238 | + return true; | ||
239 | + } | ||
240 | + | ||
241 | + rda = tcg_temp_new_i64(); | ||
242 | + rdalo = load_reg(s, a->rdalo); | ||
243 | + rdahi = load_reg(s, a->rdahi); | ||
244 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
245 | + | ||
246 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ | ||
247 | + fn(rda, cpu_env, rda, cpu_R[a->rm]); | ||
248 | + | ||
249 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
250 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
251 | + store_reg(s, a->rdalo, rdalo); | ||
252 | + store_reg(s, a->rdahi, rdahi); | ||
253 | + tcg_temp_free_i64(rda); | ||
254 | + | ||
242 | + return true; | 255 | + return true; |
243 | +} | 256 | +} |
244 | + | 257 | + |
245 | +static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, | 258 | +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a) |
246 | + unsigned size, MemTxAttrs attrs) | 259 | +{ |
247 | +{ | 260 | + return do_mve_shl_rr(s, a, gen_helper_mve_ushll); |
248 | + TZPPCPort *p = opaque; | 261 | +} |
249 | + TZPPC *s = p->ppc; | 262 | + |
250 | + int n = p - s->port; | 263 | +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a) |
251 | + AddressSpace *as = &p->downstream_as; | 264 | +{ |
252 | + uint64_t data; | 265 | + return do_mve_shl_rr(s, a, gen_helper_mve_sshrl); |
253 | + MemTxResult res; | 266 | +} |
254 | + | 267 | + |
255 | + if (!tz_ppc_check(s, n, attrs)) { | 268 | +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a) |
256 | + trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); | 269 | +{ |
257 | + if (s->cfg_sec_resp) { | 270 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll); |
258 | + return MEMTX_ERROR; | 271 | +} |
259 | + } else { | 272 | + |
260 | + *pdata = 0; | 273 | +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a) |
261 | + return MEMTX_OK; | 274 | +{ |
262 | + } | 275 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl); |
263 | + } | 276 | +} |
264 | + | 277 | + |
265 | + switch (size) { | 278 | +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
266 | + case 1: | 279 | +{ |
267 | + data = address_space_ldub(as, addr, attrs, &res); | 280 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48); |
268 | + break; | 281 | +} |
269 | + case 2: | 282 | + |
270 | + data = address_space_lduw_le(as, addr, attrs, &res); | 283 | +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
271 | + break; | 284 | +{ |
272 | + case 4: | 285 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); |
273 | + data = address_space_ldl_le(as, addr, attrs, &res); | 286 | +} |
274 | + break; | 287 | + |
275 | + case 8: | 288 | /* |
276 | + data = address_space_ldq_le(as, addr, attrs, &res); | 289 | * Multiply and multiply accumulate |
277 | + break; | 290 | */ |
278 | + default: | ||
279 | + g_assert_not_reached(); | ||
280 | + } | ||
281 | + *pdata = data; | ||
282 | + return res; | ||
283 | +} | ||
284 | + | ||
285 | +static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, | ||
286 | + unsigned size, MemTxAttrs attrs) | ||
287 | +{ | ||
288 | + TZPPCPort *p = opaque; | ||
289 | + TZPPC *s = p->ppc; | ||
290 | + AddressSpace *as = &p->downstream_as; | ||
291 | + int n = p - s->port; | ||
292 | + MemTxResult res; | ||
293 | + | ||
294 | + if (!tz_ppc_check(s, n, attrs)) { | ||
295 | + trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); | ||
296 | + if (s->cfg_sec_resp) { | ||
297 | + return MEMTX_ERROR; | ||
298 | + } else { | ||
299 | + return MEMTX_OK; | ||
300 | + } | ||
301 | + } | ||
302 | + | ||
303 | + switch (size) { | ||
304 | + case 1: | ||
305 | + address_space_stb(as, addr, val, attrs, &res); | ||
306 | + break; | ||
307 | + case 2: | ||
308 | + address_space_stw_le(as, addr, val, attrs, &res); | ||
309 | + break; | ||
310 | + case 4: | ||
311 | + address_space_stl_le(as, addr, val, attrs, &res); | ||
312 | + break; | ||
313 | + case 8: | ||
314 | + address_space_stq_le(as, addr, val, attrs, &res); | ||
315 | + break; | ||
316 | + default: | ||
317 | + g_assert_not_reached(); | ||
318 | + } | ||
319 | + return res; | ||
320 | +} | ||
321 | + | ||
322 | +static const MemoryRegionOps tz_ppc_ops = { | ||
323 | + .read_with_attrs = tz_ppc_read, | ||
324 | + .write_with_attrs = tz_ppc_write, | ||
325 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
326 | +}; | ||
327 | + | ||
328 | +static void tz_ppc_reset(DeviceState *dev) | ||
329 | +{ | ||
330 | + TZPPC *s = TZ_PPC(dev); | ||
331 | + | ||
332 | + trace_tz_ppc_reset(); | ||
333 | + s->cfg_sec_resp = false; | ||
334 | + memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); | ||
335 | + memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); | ||
336 | +} | ||
337 | + | ||
338 | +static void tz_ppc_init(Object *obj) | ||
339 | +{ | ||
340 | + DeviceState *dev = DEVICE(obj); | ||
341 | + TZPPC *s = TZ_PPC(obj); | ||
342 | + | ||
343 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); | ||
344 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); | ||
345 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); | ||
346 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); | ||
347 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); | ||
348 | + qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); | ||
349 | +} | ||
350 | + | ||
351 | +static void tz_ppc_realize(DeviceState *dev, Error **errp) | ||
352 | +{ | ||
353 | + Object *obj = OBJECT(dev); | ||
354 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
355 | + TZPPC *s = TZ_PPC(dev); | ||
356 | + int i; | ||
357 | + | ||
358 | + /* We can't create the upstream end of the port until realize, | ||
359 | + * as we don't know the size of the MR used as the downstream until then. | ||
360 | + */ | ||
361 | + for (i = 0; i < TZ_NUM_PORTS; i++) { | ||
362 | + TZPPCPort *port = &s->port[i]; | ||
363 | + char *name; | ||
364 | + uint64_t size; | ||
365 | + | ||
366 | + if (!port->downstream) { | ||
367 | + continue; | ||
368 | + } | ||
369 | + | ||
370 | + name = g_strdup_printf("tz-ppc-port[%d]", i); | ||
371 | + | ||
372 | + port->ppc = s; | ||
373 | + address_space_init(&port->downstream_as, port->downstream, name); | ||
374 | + | ||
375 | + size = memory_region_size(port->downstream); | ||
376 | + memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, | ||
377 | + port, name, size); | ||
378 | + sysbus_init_mmio(sbd, &port->upstream); | ||
379 | + g_free(name); | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +static const VMStateDescription tz_ppc_vmstate = { | ||
384 | + .name = "tz-ppc", | ||
385 | + .version_id = 1, | ||
386 | + .minimum_version_id = 1, | ||
387 | + .fields = (VMStateField[]) { | ||
388 | + VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), | ||
389 | + VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), | ||
390 | + VMSTATE_BOOL(cfg_sec_resp, TZPPC), | ||
391 | + VMSTATE_BOOL(irq_enable, TZPPC), | ||
392 | + VMSTATE_BOOL(irq_clear, TZPPC), | ||
393 | + VMSTATE_BOOL(irq_status, TZPPC), | ||
394 | + VMSTATE_END_OF_LIST() | ||
395 | + } | ||
396 | +}; | ||
397 | + | ||
398 | +#define DEFINE_PORT(N) \ | ||
399 | + DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ | ||
400 | + TYPE_MEMORY_REGION, MemoryRegion *) | ||
401 | + | ||
402 | +static Property tz_ppc_properties[] = { | ||
403 | + DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), | ||
404 | + DEFINE_PORT(0), | ||
405 | + DEFINE_PORT(1), | ||
406 | + DEFINE_PORT(2), | ||
407 | + DEFINE_PORT(3), | ||
408 | + DEFINE_PORT(4), | ||
409 | + DEFINE_PORT(5), | ||
410 | + DEFINE_PORT(6), | ||
411 | + DEFINE_PORT(7), | ||
412 | + DEFINE_PORT(8), | ||
413 | + DEFINE_PORT(9), | ||
414 | + DEFINE_PORT(10), | ||
415 | + DEFINE_PORT(11), | ||
416 | + DEFINE_PORT(12), | ||
417 | + DEFINE_PORT(13), | ||
418 | + DEFINE_PORT(14), | ||
419 | + DEFINE_PORT(15), | ||
420 | + DEFINE_PROP_END_OF_LIST(), | ||
421 | +}; | ||
422 | + | ||
423 | +static void tz_ppc_class_init(ObjectClass *klass, void *data) | ||
424 | +{ | ||
425 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
426 | + | ||
427 | + dc->realize = tz_ppc_realize; | ||
428 | + dc->vmsd = &tz_ppc_vmstate; | ||
429 | + dc->reset = tz_ppc_reset; | ||
430 | + dc->props = tz_ppc_properties; | ||
431 | +} | ||
432 | + | ||
433 | +static const TypeInfo tz_ppc_info = { | ||
434 | + .name = TYPE_TZ_PPC, | ||
435 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
436 | + .instance_size = sizeof(TZPPC), | ||
437 | + .instance_init = tz_ppc_init, | ||
438 | + .class_init = tz_ppc_class_init, | ||
439 | +}; | ||
440 | + | ||
441 | +static void tz_ppc_register_types(void) | ||
442 | +{ | ||
443 | + type_register_static(&tz_ppc_info); | ||
444 | +} | ||
445 | + | ||
446 | +type_init(tz_ppc_register_types); | ||
447 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
448 | index XXXXXXX..XXXXXXX 100644 | ||
449 | --- a/default-configs/arm-softmmu.mak | ||
450 | +++ b/default-configs/arm-softmmu.mak | ||
451 | @@ -XXX,XX +XXX,XX @@ CONFIG_CMSDK_APB_UART=y | ||
452 | CONFIG_MPS2_FPGAIO=y | ||
453 | CONFIG_MPS2_SCC=y | ||
454 | |||
455 | +CONFIG_TZ_PPC=y | ||
456 | + | ||
457 | CONFIG_VERSATILE_PCI=y | ||
458 | CONFIG_VERSATILE_I2C=y | ||
459 | |||
460 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
461 | index XXXXXXX..XXXXXXX 100644 | ||
462 | --- a/hw/misc/trace-events | ||
463 | +++ b/hw/misc/trace-events | ||
464 | @@ -XXX,XX +XXX,XX @@ mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d co | ||
465 | mos6522_set_sr_int(void) "set sr_int" | ||
466 | mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 | ||
467 | mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" | ||
468 | + | ||
469 | +# hw/misc/tz-ppc.c | ||
470 | +tz_ppc_reset(void) "TZ PPC: reset" | ||
471 | +tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" | ||
472 | +tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" | ||
473 | +tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" | ||
474 | +tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" | ||
475 | +tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
476 | +tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
477 | +tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
478 | +tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
479 | -- | 291 | -- |
480 | 2.16.2 | 292 | 2.20.1 |
481 | 293 | ||
482 | 294 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE shifts by immediate, which perform shifts |
---|---|---|---|
2 | 2 | on a single general-purpose register. | |
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | These patterns overlap with the long-shift-by-immediates, |
5 | Message-id: 20180228193125.20577-8-richard.henderson@linaro.org | 5 | so we have to rearrange the grouping a little here. |
6 | |||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210628135835.6690-18-peter.maydell@linaro.org | ||
7 | --- | 10 | --- |
8 | target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++----------- | 11 | target/arm/helper-mve.h | 3 ++ |
9 | 1 file changed, 67 insertions(+), 19 deletions(-) | 12 | target/arm/translate.h | 1 + |
10 | 13 | target/arm/t32.decode | 31 ++++++++++++++----- | |
14 | target/arm/mve_helper.c | 10 ++++++ | ||
15 | target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++-- | ||
16 | 5 files changed, 104 insertions(+), 9 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper-mve.h | ||
21 | +++ b/target/arm/helper-mve.h | ||
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
23 | DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
24 | DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
25 | DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
26 | + | ||
27 | +DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
28 | +DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
29 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate.h | ||
32 | +++ b/target/arm/translate.h | ||
33 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
34 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
35 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
36 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
37 | +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
38 | |||
39 | /** | ||
40 | * arm_tbflags_from_tb: | ||
41 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/t32.decode | ||
44 | +++ b/target/arm/t32.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | |||
47 | &mve_shl_ri rdalo rdahi shim | ||
48 | &mve_shl_rr rdalo rdahi rm | ||
49 | +&mve_sh_ri rda shim | ||
50 | |||
51 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
52 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
55 | @mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
56 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
57 | +@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | ||
58 | + &mve_sh_ri shim=%imm5_12_6 | ||
59 | |||
60 | { | ||
61 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
62 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
63 | # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
64 | # handling them as r13 and r15 accesses with the same semantics as A32). | ||
65 | [ | ||
66 | - LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
67 | - LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
68 | - ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
69 | + { | ||
70 | + UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri | ||
71 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
72 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
73 | + } | ||
74 | |||
75 | - UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
76 | - URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
77 | - SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
78 | - SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
79 | + { | ||
80 | + URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri | ||
81 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
82 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
83 | + } | ||
84 | + | ||
85 | + { | ||
86 | + SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri | ||
87 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
88 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
89 | + } | ||
90 | + | ||
91 | + { | ||
92 | + SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri | ||
93 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
94 | + } | ||
95 | |||
96 | LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
97 | ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
98 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/arm/mve_helper.c | ||
101 | +++ b/target/arm/mve_helper.c | ||
102 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
103 | { | ||
104 | return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
105 | } | ||
106 | + | ||
107 | +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
108 | +{ | ||
109 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
110 | +} | ||
111 | + | ||
112 | +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
113 | +{ | ||
114 | + return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
115 | +} | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 116 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
12 | index XXXXXXX..XXXXXXX 100644 | 117 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 118 | --- a/target/arm/translate.c |
14 | +++ b/target/arm/translate.c | 119 | +++ b/target/arm/translate.c |
15 | @@ -XXX,XX +XXX,XX @@ | 120 | @@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) |
16 | #include "disas/disas.h" | 121 | |
17 | #include "exec/exec-all.h" | 122 | static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) |
18 | #include "tcg-op.h" | 123 | { |
19 | +#include "tcg-op-gvec.h" | 124 | - TCGv_i32 t = tcg_temp_new_i32(); |
20 | #include "qemu/log.h" | 125 | + TCGv_i32 t; |
21 | #include "qemu/bitops.h" | 126 | |
22 | #include "arm_ldst.h" | 127 | + /* Handle shift by the input size for the benefit of trans_SRSHR_ri */ |
23 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_narrow_op(int op, int u, int size, | 128 | + if (sh == 32) { |
24 | #define NEON_3R_VPMAX 20 | 129 | + tcg_gen_movi_i32(d, 0); |
25 | #define NEON_3R_VPMIN 21 | 130 | + return; |
26 | #define NEON_3R_VQDMULH_VQRDMULH 22 | 131 | + } |
27 | -#define NEON_3R_VPADD 23 | 132 | + t = tcg_temp_new_i32(); |
28 | +#define NEON_3R_VPADD_VQRDMLAH 23 | 133 | tcg_gen_extract_i32(t, a, sh - 1, 1); |
29 | #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ | 134 | tcg_gen_sari_i32(d, a, sh); |
30 | -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ | 135 | tcg_gen_add_i32(d, d, t); |
31 | +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ | 136 | @@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) |
32 | #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ | 137 | |
33 | #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ | 138 | static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) |
34 | #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ | 139 | { |
35 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_3r_sizes[] = { | 140 | - TCGv_i32 t = tcg_temp_new_i32(); |
36 | [NEON_3R_VPMAX] = 0x7, | 141 | + TCGv_i32 t; |
37 | [NEON_3R_VPMIN] = 0x7, | 142 | |
38 | [NEON_3R_VQDMULH_VQRDMULH] = 0x6, | 143 | + /* Handle shift by the input size for the benefit of trans_URSHR_ri */ |
39 | - [NEON_3R_VPADD] = 0x7, | 144 | + if (sh == 32) { |
40 | + [NEON_3R_VPADD_VQRDMLAH] = 0x7, | 145 | + tcg_gen_extract_i32(d, a, sh - 1, 1); |
41 | [NEON_3R_SHA] = 0xf, /* size field encodes op type */ | 146 | + return; |
42 | - [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */ | 147 | + } |
43 | + [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ | 148 | + t = tcg_temp_new_i32(); |
44 | [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ | 149 | tcg_gen_extract_i32(t, a, sh - 1, 1); |
45 | [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ | 150 | tcg_gen_shri_i32(d, a, sh); |
46 | [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ | 151 | tcg_gen_add_i32(d, d, t); |
47 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_2rm_sizes[] = { | 152 | @@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
48 | [NEON_2RM_VCVT_UF] = 0x4, | 153 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); |
49 | }; | 154 | } |
50 | 155 | ||
51 | + | 156 | +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn) |
52 | +/* Expand v8.1 simd helper. */ | 157 | +{ |
53 | +static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, | 158 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
54 | + int q, int rd, int rn, int rm) | 159 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
55 | +{ | 160 | + return false; |
56 | + if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | 161 | + } |
57 | + int opr_sz = (1 + q) * 8; | 162 | + if (!dc_isar_feature(aa32_mve, s) || |
58 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | 163 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
59 | + vfp_reg_offset(1, rn), | 164 | + a->rda == 13 || a->rda == 15) { |
60 | + vfp_reg_offset(1, rm), cpu_env, | 165 | + /* These rda cases are UNPREDICTABLE; we choose to UNDEF */ |
61 | + opr_sz, opr_sz, 0, fn); | 166 | + unallocated_encoding(s); |
62 | + return 0; | 167 | + return true; |
63 | + } | 168 | + } |
64 | + return 1; | 169 | + |
65 | +} | 170 | + if (a->shim == 0) { |
66 | + | 171 | + a->shim = 32; |
67 | /* Translate a NEON data processing instruction. Return nonzero if the | 172 | + } |
68 | instruction is invalid. | 173 | + fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); |
69 | We process data in a mixture of 32-bit and 64-bit chunks. | 174 | + |
70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 175 | + return true; |
71 | if (q && ((rd | rn | rm) & 1)) { | 176 | +} |
72 | return 1; | 177 | + |
73 | } | 178 | +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a) |
74 | - /* | 179 | +{ |
75 | - * The SHA-1/SHA-256 3-register instructions require special treatment | 180 | + return do_mve_sh_ri(s, a, gen_urshr32_i32); |
76 | - * here, as their size field is overloaded as an op type selector, and | 181 | +} |
77 | - * they all consume their input in a single pass. | 182 | + |
78 | - */ | 183 | +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a) |
79 | - if (op == NEON_3R_SHA) { | 184 | +{ |
80 | + switch (op) { | 185 | + return do_mve_sh_ri(s, a, gen_srshr32_i32); |
81 | + case NEON_3R_SHA: | 186 | +} |
82 | + /* The SHA-1/SHA-256 3-register instructions require special | 187 | + |
83 | + * treatment here, as their size field is overloaded as an | 188 | +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) |
84 | + * op type selector, and they all consume their input in a | 189 | +{ |
85 | + * single pass. | 190 | + gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); |
86 | + */ | 191 | +} |
87 | if (!q) { | 192 | + |
88 | return 1; | 193 | +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
89 | } | 194 | +{ |
90 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 195 | + return do_mve_sh_ri(s, a, gen_mve_sqshl); |
91 | tcg_temp_free_ptr(ptr2); | 196 | +} |
92 | tcg_temp_free_ptr(ptr3); | 197 | + |
93 | return 0; | 198 | +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) |
94 | + | 199 | +{ |
95 | + case NEON_3R_VPADD_VQRDMLAH: | 200 | + gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); |
96 | + if (!u) { | 201 | +} |
97 | + break; /* VPADD */ | 202 | + |
98 | + } | 203 | +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
99 | + /* VQRDMLAH */ | 204 | +{ |
100 | + switch (size) { | 205 | + return do_mve_sh_ri(s, a, gen_mve_uqshl); |
101 | + case 1: | 206 | +} |
102 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16, | 207 | + |
103 | + q, rd, rn, rm); | 208 | /* |
104 | + case 2: | 209 | * Multiply and multiply accumulate |
105 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32, | 210 | */ |
106 | + q, rd, rn, rm); | ||
107 | + } | ||
108 | + return 1; | ||
109 | + | ||
110 | + case NEON_3R_VFM_VQRDMLSH: | ||
111 | + if (!u) { | ||
112 | + /* VFM, VFMS */ | ||
113 | + if (size == 1) { | ||
114 | + return 1; | ||
115 | + } | ||
116 | + break; | ||
117 | + } | ||
118 | + /* VQRDMLSH */ | ||
119 | + switch (size) { | ||
120 | + case 1: | ||
121 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16, | ||
122 | + q, rd, rn, rm); | ||
123 | + case 2: | ||
124 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32, | ||
125 | + q, rd, rn, rm); | ||
126 | + } | ||
127 | + return 1; | ||
128 | } | ||
129 | if (size == 3 && op != NEON_3R_LOGIC) { | ||
130 | /* 64-bit element instructions. */ | ||
131 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
132 | rm = rtmp; | ||
133 | } | ||
134 | break; | ||
135 | - case NEON_3R_VPADD: | ||
136 | - if (u) { | ||
137 | - return 1; | ||
138 | - } | ||
139 | - /* Fall through */ | ||
140 | + case NEON_3R_VPADD_VQRDMLAH: | ||
141 | case NEON_3R_VPMAX: | ||
142 | case NEON_3R_VPMIN: | ||
143 | pairwise = 1; | ||
144 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
145 | return 1; | ||
146 | } | ||
147 | break; | ||
148 | - case NEON_3R_VFM: | ||
149 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { | ||
150 | + case NEON_3R_VFM_VQRDMLSH: | ||
151 | + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { | ||
152 | return 1; | ||
153 | } | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
156 | } | ||
157 | } | ||
158 | break; | ||
159 | - case NEON_3R_VPADD: | ||
160 | + case NEON_3R_VPADD_VQRDMLAH: | ||
161 | switch (size) { | ||
162 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; | ||
163 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | ||
164 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
165 | } | ||
166 | } | ||
167 | break; | ||
168 | - case NEON_3R_VFM: | ||
169 | + case NEON_3R_VFM_VQRDMLSH: | ||
170 | { | ||
171 | /* VFMA, VFMS: fused multiply-add */ | ||
172 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
173 | -- | 211 | -- |
174 | 2.16.2 | 212 | 2.20.1 |
175 | 213 | ||
176 | 214 | diff view generated by jsdifflib |
1 | The Arm IoT Kit includes a "security controller" which is largely a | 1 | Implement the MVE shifts by register, which perform |
---|---|---|---|
2 | collection of registers for controlling the PPCs and other bits of | 2 | shifts on a single general-purpose register. |
3 | glue in the system. This commit provides the initial skeleton of the | ||
4 | device, implementing just the ID registers, and a couple of read-only | ||
5 | read-as-zero registers. | ||
6 | 3 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20180220180325.29818-16-peter.maydell@linaro.org | 6 | Message-id: 20210628135835.6690-19-peter.maydell@linaro.org |
10 | --- | 7 | --- |
11 | hw/misc/Makefile.objs | 1 + | 8 | target/arm/helper-mve.h | 2 ++ |
12 | include/hw/misc/iotkit-secctl.h | 39 ++++ | 9 | target/arm/translate.h | 1 + |
13 | hw/misc/iotkit-secctl.c | 448 ++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/t32.decode | 18 ++++++++++++++---- |
14 | default-configs/arm-softmmu.mak | 1 + | 11 | target/arm/mve_helper.c | 10 ++++++++++ |
15 | hw/misc/trace-events | 7 + | 12 | target/arm/translate.c | 30 ++++++++++++++++++++++++++++++ |
16 | 5 files changed, 496 insertions(+) | 13 | 5 files changed, 57 insertions(+), 4 deletions(-) |
17 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
18 | create mode 100644 hw/misc/iotkit-secctl.c | ||
19 | 14 | ||
20 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
21 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/misc/Makefile.objs | 17 | --- a/target/arm/helper-mve.h |
23 | +++ b/hw/misc/Makefile.objs | 18 | +++ b/target/arm/helper-mve.h |
24 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 20 | |
26 | 21 | DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | |
27 | obj-$(CONFIG_TZ_PPC) += tz-ppc.o | 22 | DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) |
28 | +obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o | 23 | +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32) |
29 | 24 | +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32) | |
30 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 25 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
31 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | 26 | index XXXXXXX..XXXXXXX 100644 |
32 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 27 | --- a/target/arm/translate.h |
33 | new file mode 100644 | 28 | +++ b/target/arm/translate.h |
34 | index XXXXXXX..XXXXXXX | 29 | @@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); |
35 | --- /dev/null | 30 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); |
36 | +++ b/include/hw/misc/iotkit-secctl.h | 31 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); |
32 | typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
33 | +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | ||
34 | |||
35 | /** | ||
36 | * arm_tbflags_from_tb: | ||
37 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/t32.decode | ||
40 | +++ b/target/arm/t32.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ | 41 | @@ -XXX,XX +XXX,XX @@ |
38 | +/* | 42 | &mve_shl_ri rdalo rdahi shim |
39 | + * ARM IoT Kit security controller | 43 | &mve_shl_rr rdalo rdahi rm |
40 | + * | 44 | &mve_sh_ri rda shim |
41 | + * Copyright (c) 2018 Linaro Limited | 45 | +&mve_sh_rr rda rm |
42 | + * Written by Peter Maydell | 46 | |
43 | + * | 47 | # rdahi: bits [3:1] from insn, bit 0 is 1 |
44 | + * This program is free software; you can redistribute it and/or modify | 48 | # rdalo: bits [3:1] from insn, bit 0 is 0 |
45 | + * it under the terms of the GNU General Public License version 2 or | ||
46 | + * (at your option) any later version. | ||
47 | + */ | ||
48 | + | ||
49 | +/* This is a model of the security controller which is part of the | ||
50 | + * Arm IoT Kit and documented in | ||
51 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
52 | + * | ||
53 | + * QEMU interface: | ||
54 | + * + sysbus MMIO region 0 is the "secure privilege control block" registers | ||
55 | + * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
56 | + */ | ||
57 | + | ||
58 | +#ifndef IOTKIT_SECCTL_H | ||
59 | +#define IOTKIT_SECCTL_H | ||
60 | + | ||
61 | +#include "hw/sysbus.h" | ||
62 | + | ||
63 | +#define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
64 | +#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
65 | + | ||
66 | +typedef struct IoTKitSecCtl { | ||
67 | + /*< private >*/ | ||
68 | + SysBusDevice parent_obj; | ||
69 | + | ||
70 | + /*< public >*/ | ||
71 | + | ||
72 | + MemoryRegion s_regs; | ||
73 | + MemoryRegion ns_regs; | ||
74 | +} IoTKitSecCtl; | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
78 | new file mode 100644 | ||
79 | index XXXXXXX..XXXXXXX | ||
80 | --- /dev/null | ||
81 | +++ b/hw/misc/iotkit-secctl.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | 49 | @@ -XXX,XX +XXX,XX @@ |
83 | +/* | 50 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 |
84 | + * Arm IoT Kit security controller | 51 | @mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ |
85 | + * | 52 | &mve_sh_ri shim=%imm5_12_6 |
86 | + * Copyright (c) 2018 Linaro Limited | 53 | +@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr |
87 | + * Written by Peter Maydell | 54 | |
88 | + * | 55 | { |
89 | + * This program is free software; you can redistribute it and/or modify | 56 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi |
90 | + * it under the terms of the GNU General Public License version 2 or | 57 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi |
91 | + * (at your option) any later version. | 58 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri |
92 | + */ | 59 | } |
93 | + | 60 | |
94 | +#include "qemu/osdep.h" | 61 | - LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr |
95 | +#include "qemu/log.h" | 62 | - ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr |
96 | +#include "qapi/error.h" | 63 | - UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr |
97 | +#include "trace.h" | 64 | - SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr |
98 | +#include "hw/sysbus.h" | 65 | + { |
99 | +#include "hw/registerfields.h" | 66 | + UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr |
100 | +#include "hw/misc/iotkit-secctl.h" | 67 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr |
101 | + | 68 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr |
102 | +/* Registers in the secure privilege control block */ | ||
103 | +REG32(SECRESPCFG, 0x10) | ||
104 | +REG32(NSCCFG, 0x14) | ||
105 | +REG32(SECMPCINTSTATUS, 0x1c) | ||
106 | +REG32(SECPPCINTSTAT, 0x20) | ||
107 | +REG32(SECPPCINTCLR, 0x24) | ||
108 | +REG32(SECPPCINTEN, 0x28) | ||
109 | +REG32(SECMSCINTSTAT, 0x30) | ||
110 | +REG32(SECMSCINTCLR, 0x34) | ||
111 | +REG32(SECMSCINTEN, 0x38) | ||
112 | +REG32(BRGINTSTAT, 0x40) | ||
113 | +REG32(BRGINTCLR, 0x44) | ||
114 | +REG32(BRGINTEN, 0x48) | ||
115 | +REG32(AHBNSPPC0, 0x50) | ||
116 | +REG32(AHBNSPPCEXP0, 0x60) | ||
117 | +REG32(AHBNSPPCEXP1, 0x64) | ||
118 | +REG32(AHBNSPPCEXP2, 0x68) | ||
119 | +REG32(AHBNSPPCEXP3, 0x6c) | ||
120 | +REG32(APBNSPPC0, 0x70) | ||
121 | +REG32(APBNSPPC1, 0x74) | ||
122 | +REG32(APBNSPPCEXP0, 0x80) | ||
123 | +REG32(APBNSPPCEXP1, 0x84) | ||
124 | +REG32(APBNSPPCEXP2, 0x88) | ||
125 | +REG32(APBNSPPCEXP3, 0x8c) | ||
126 | +REG32(AHBSPPPC0, 0x90) | ||
127 | +REG32(AHBSPPPCEXP0, 0xa0) | ||
128 | +REG32(AHBSPPPCEXP1, 0xa4) | ||
129 | +REG32(AHBSPPPCEXP2, 0xa8) | ||
130 | +REG32(AHBSPPPCEXP3, 0xac) | ||
131 | +REG32(APBSPPPC0, 0xb0) | ||
132 | +REG32(APBSPPPC1, 0xb4) | ||
133 | +REG32(APBSPPPCEXP0, 0xc0) | ||
134 | +REG32(APBSPPPCEXP1, 0xc4) | ||
135 | +REG32(APBSPPPCEXP2, 0xc8) | ||
136 | +REG32(APBSPPPCEXP3, 0xcc) | ||
137 | +REG32(NSMSCEXP, 0xd0) | ||
138 | +REG32(PID4, 0xfd0) | ||
139 | +REG32(PID5, 0xfd4) | ||
140 | +REG32(PID6, 0xfd8) | ||
141 | +REG32(PID7, 0xfdc) | ||
142 | +REG32(PID0, 0xfe0) | ||
143 | +REG32(PID1, 0xfe4) | ||
144 | +REG32(PID2, 0xfe8) | ||
145 | +REG32(PID3, 0xfec) | ||
146 | +REG32(CID0, 0xff0) | ||
147 | +REG32(CID1, 0xff4) | ||
148 | +REG32(CID2, 0xff8) | ||
149 | +REG32(CID3, 0xffc) | ||
150 | + | ||
151 | +/* Registers in the non-secure privilege control block */ | ||
152 | +REG32(AHBNSPPPC0, 0x90) | ||
153 | +REG32(AHBNSPPPCEXP0, 0xa0) | ||
154 | +REG32(AHBNSPPPCEXP1, 0xa4) | ||
155 | +REG32(AHBNSPPPCEXP2, 0xa8) | ||
156 | +REG32(AHBNSPPPCEXP3, 0xac) | ||
157 | +REG32(APBNSPPPC0, 0xb0) | ||
158 | +REG32(APBNSPPPC1, 0xb4) | ||
159 | +REG32(APBNSPPPCEXP0, 0xc0) | ||
160 | +REG32(APBNSPPPCEXP1, 0xc4) | ||
161 | +REG32(APBNSPPPCEXP2, 0xc8) | ||
162 | +REG32(APBNSPPPCEXP3, 0xcc) | ||
163 | +/* PID and CID registers are also present in the NS block */ | ||
164 | + | ||
165 | +static const uint8_t iotkit_secctl_s_idregs[] = { | ||
166 | + 0x04, 0x00, 0x00, 0x00, | ||
167 | + 0x52, 0xb8, 0x0b, 0x00, | ||
168 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
169 | +}; | ||
170 | + | ||
171 | +static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
172 | + 0x04, 0x00, 0x00, 0x00, | ||
173 | + 0x53, 0xb8, 0x0b, 0x00, | ||
174 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
175 | +}; | ||
176 | + | ||
177 | +static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
178 | + uint64_t *pdata, | ||
179 | + unsigned size, MemTxAttrs attrs) | ||
180 | +{ | ||
181 | + uint64_t r; | ||
182 | + uint32_t offset = addr & ~0x3; | ||
183 | + | ||
184 | + switch (offset) { | ||
185 | + case A_AHBNSPPC0: | ||
186 | + case A_AHBSPPPC0: | ||
187 | + r = 0; | ||
188 | + break; | ||
189 | + case A_SECRESPCFG: | ||
190 | + case A_NSCCFG: | ||
191 | + case A_SECMPCINTSTATUS: | ||
192 | + case A_SECPPCINTSTAT: | ||
193 | + case A_SECPPCINTEN: | ||
194 | + case A_SECMSCINTSTAT: | ||
195 | + case A_SECMSCINTEN: | ||
196 | + case A_BRGINTSTAT: | ||
197 | + case A_BRGINTEN: | ||
198 | + case A_AHBNSPPCEXP0: | ||
199 | + case A_AHBNSPPCEXP1: | ||
200 | + case A_AHBNSPPCEXP2: | ||
201 | + case A_AHBNSPPCEXP3: | ||
202 | + case A_APBNSPPC0: | ||
203 | + case A_APBNSPPC1: | ||
204 | + case A_APBNSPPCEXP0: | ||
205 | + case A_APBNSPPCEXP1: | ||
206 | + case A_APBNSPPCEXP2: | ||
207 | + case A_APBNSPPCEXP3: | ||
208 | + case A_AHBSPPPCEXP0: | ||
209 | + case A_AHBSPPPCEXP1: | ||
210 | + case A_AHBSPPPCEXP2: | ||
211 | + case A_AHBSPPPCEXP3: | ||
212 | + case A_APBSPPPC0: | ||
213 | + case A_APBSPPPC1: | ||
214 | + case A_APBSPPPCEXP0: | ||
215 | + case A_APBSPPPCEXP1: | ||
216 | + case A_APBSPPPCEXP2: | ||
217 | + case A_APBSPPPCEXP3: | ||
218 | + case A_NSMSCEXP: | ||
219 | + qemu_log_mask(LOG_UNIMP, | ||
220 | + "IoTKit SecCtl S block read: " | ||
221 | + "unimplemented offset 0x%x\n", offset); | ||
222 | + r = 0; | ||
223 | + break; | ||
224 | + case A_PID4: | ||
225 | + case A_PID5: | ||
226 | + case A_PID6: | ||
227 | + case A_PID7: | ||
228 | + case A_PID0: | ||
229 | + case A_PID1: | ||
230 | + case A_PID2: | ||
231 | + case A_PID3: | ||
232 | + case A_CID0: | ||
233 | + case A_CID1: | ||
234 | + case A_CID2: | ||
235 | + case A_CID3: | ||
236 | + r = iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; | ||
237 | + break; | ||
238 | + case A_SECPPCINTCLR: | ||
239 | + case A_SECMSCINTCLR: | ||
240 | + case A_BRGINTCLR: | ||
241 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
242 | + "IotKit SecCtl S block read: write-only offset 0x%x\n", | ||
243 | + offset); | ||
244 | + r = 0; | ||
245 | + break; | ||
246 | + default: | ||
247 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
248 | + "IotKit SecCtl S block read: bad offset 0x%x\n", offset); | ||
249 | + r = 0; | ||
250 | + break; | ||
251 | + } | 69 | + } |
252 | + | 70 | + |
253 | + if (size != 4) { | 71 | + { |
254 | + /* None of our registers are access-sensitive, so just pull the right | 72 | + SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr |
255 | + * byte out of the word read result. | 73 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr |
256 | + */ | 74 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr |
257 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
258 | + } | 75 | + } |
259 | + | 76 | + |
260 | + trace_iotkit_secctl_s_read(offset, r, size); | 77 | UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr |
261 | + *pdata = r; | 78 | SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr |
262 | + return MEMTX_OK; | 79 | ] |
80 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/mve_helper.c | ||
83 | +++ b/target/arm/mve_helper.c | ||
84 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
85 | { | ||
86 | return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
87 | } | ||
88 | + | ||
89 | +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
90 | +{ | ||
91 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); | ||
263 | +} | 92 | +} |
264 | + | 93 | + |
265 | +static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | 94 | +uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) |
266 | + uint64_t value, | ||
267 | + unsigned size, MemTxAttrs attrs) | ||
268 | +{ | 95 | +{ |
269 | + uint32_t offset = addr; | 96 | + return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); |
270 | + | 97 | +} |
271 | + trace_iotkit_secctl_s_write(offset, value, size); | 98 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
272 | + | 99 | index XXXXXXX..XXXXXXX 100644 |
273 | + if (size != 4) { | 100 | --- a/target/arm/translate.c |
274 | + /* Byte and halfword writes are ignored */ | 101 | +++ b/target/arm/translate.c |
275 | + qemu_log_mask(LOG_GUEST_ERROR, | 102 | @@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
276 | + "IotKit SecCtl S block write: bad size, ignored\n"); | 103 | return do_mve_sh_ri(s, a, gen_mve_uqshl); |
277 | + return MEMTX_OK; | 104 | } |
105 | |||
106 | +static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn) | ||
107 | +{ | ||
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
109 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
110 | + return false; | ||
111 | + } | ||
112 | + if (!dc_isar_feature(aa32_mve, s) || | ||
113 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
114 | + a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 || | ||
115 | + a->rm == a->rda) { | ||
116 | + /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
117 | + unallocated_encoding(s); | ||
118 | + return true; | ||
278 | + } | 119 | + } |
279 | + | 120 | + |
280 | + switch (offset) { | 121 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ |
281 | + case A_SECRESPCFG: | 122 | + fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); |
282 | + case A_NSCCFG: | 123 | + return true; |
283 | + case A_SECPPCINTCLR: | ||
284 | + case A_SECPPCINTEN: | ||
285 | + case A_SECMSCINTCLR: | ||
286 | + case A_SECMSCINTEN: | ||
287 | + case A_BRGINTCLR: | ||
288 | + case A_BRGINTEN: | ||
289 | + case A_AHBNSPPCEXP0: | ||
290 | + case A_AHBNSPPCEXP1: | ||
291 | + case A_AHBNSPPCEXP2: | ||
292 | + case A_AHBNSPPCEXP3: | ||
293 | + case A_APBNSPPC0: | ||
294 | + case A_APBNSPPC1: | ||
295 | + case A_APBNSPPCEXP0: | ||
296 | + case A_APBNSPPCEXP1: | ||
297 | + case A_APBNSPPCEXP2: | ||
298 | + case A_APBNSPPCEXP3: | ||
299 | + case A_AHBSPPPCEXP0: | ||
300 | + case A_AHBSPPPCEXP1: | ||
301 | + case A_AHBSPPPCEXP2: | ||
302 | + case A_AHBSPPPCEXP3: | ||
303 | + case A_APBSPPPC0: | ||
304 | + case A_APBSPPPC1: | ||
305 | + case A_APBSPPPCEXP0: | ||
306 | + case A_APBSPPPCEXP1: | ||
307 | + case A_APBSPPPCEXP2: | ||
308 | + case A_APBSPPPCEXP3: | ||
309 | + qemu_log_mask(LOG_UNIMP, | ||
310 | + "IoTKit SecCtl S block write: " | ||
311 | + "unimplemented offset 0x%x\n", offset); | ||
312 | + break; | ||
313 | + case A_SECMPCINTSTATUS: | ||
314 | + case A_SECPPCINTSTAT: | ||
315 | + case A_SECMSCINTSTAT: | ||
316 | + case A_BRGINTSTAT: | ||
317 | + case A_AHBNSPPC0: | ||
318 | + case A_AHBSPPPC0: | ||
319 | + case A_NSMSCEXP: | ||
320 | + case A_PID4: | ||
321 | + case A_PID5: | ||
322 | + case A_PID6: | ||
323 | + case A_PID7: | ||
324 | + case A_PID0: | ||
325 | + case A_PID1: | ||
326 | + case A_PID2: | ||
327 | + case A_PID3: | ||
328 | + case A_CID0: | ||
329 | + case A_CID1: | ||
330 | + case A_CID2: | ||
331 | + case A_CID3: | ||
332 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
333 | + "IoTKit SecCtl S block write: " | ||
334 | + "read-only offset 0x%x\n", offset); | ||
335 | + break; | ||
336 | + default: | ||
337 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
338 | + "IotKit SecCtl S block write: bad offset 0x%x\n", | ||
339 | + offset); | ||
340 | + break; | ||
341 | + } | ||
342 | + | ||
343 | + return MEMTX_OK; | ||
344 | +} | 124 | +} |
345 | + | 125 | + |
346 | +static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | 126 | +static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a) |
347 | + uint64_t *pdata, | ||
348 | + unsigned size, MemTxAttrs attrs) | ||
349 | +{ | 127 | +{ |
350 | + uint64_t r; | 128 | + return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr); |
351 | + uint32_t offset = addr & ~0x3; | ||
352 | + | ||
353 | + switch (offset) { | ||
354 | + case A_AHBNSPPPC0: | ||
355 | + r = 0; | ||
356 | + break; | ||
357 | + case A_AHBNSPPPCEXP0: | ||
358 | + case A_AHBNSPPPCEXP1: | ||
359 | + case A_AHBNSPPPCEXP2: | ||
360 | + case A_AHBNSPPPCEXP3: | ||
361 | + case A_APBNSPPPC0: | ||
362 | + case A_APBNSPPPC1: | ||
363 | + case A_APBNSPPPCEXP0: | ||
364 | + case A_APBNSPPPCEXP1: | ||
365 | + case A_APBNSPPPCEXP2: | ||
366 | + case A_APBNSPPPCEXP3: | ||
367 | + qemu_log_mask(LOG_UNIMP, | ||
368 | + "IoTKit SecCtl NS block read: " | ||
369 | + "unimplemented offset 0x%x\n", offset); | ||
370 | + break; | ||
371 | + case A_PID4: | ||
372 | + case A_PID5: | ||
373 | + case A_PID6: | ||
374 | + case A_PID7: | ||
375 | + case A_PID0: | ||
376 | + case A_PID1: | ||
377 | + case A_PID2: | ||
378 | + case A_PID3: | ||
379 | + case A_CID0: | ||
380 | + case A_CID1: | ||
381 | + case A_CID2: | ||
382 | + case A_CID3: | ||
383 | + r = iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; | ||
384 | + break; | ||
385 | + default: | ||
386 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
387 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
388 | + offset); | ||
389 | + r = 0; | ||
390 | + break; | ||
391 | + } | ||
392 | + | ||
393 | + if (size != 4) { | ||
394 | + /* None of our registers are access-sensitive, so just pull the right | ||
395 | + * byte out of the word read result. | ||
396 | + */ | ||
397 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
398 | + } | ||
399 | + | ||
400 | + trace_iotkit_secctl_ns_read(offset, r, size); | ||
401 | + *pdata = r; | ||
402 | + return MEMTX_OK; | ||
403 | +} | 129 | +} |
404 | + | 130 | + |
405 | +static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | 131 | +static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a) |
406 | + uint64_t value, | ||
407 | + unsigned size, MemTxAttrs attrs) | ||
408 | +{ | 132 | +{ |
409 | + uint32_t offset = addr; | 133 | + return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl); |
410 | + | ||
411 | + trace_iotkit_secctl_ns_write(offset, value, size); | ||
412 | + | ||
413 | + if (size != 4) { | ||
414 | + /* Byte and halfword writes are ignored */ | ||
415 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
416 | + "IotKit SecCtl NS block write: bad size, ignored\n"); | ||
417 | + return MEMTX_OK; | ||
418 | + } | ||
419 | + | ||
420 | + switch (offset) { | ||
421 | + case A_AHBNSPPPCEXP0: | ||
422 | + case A_AHBNSPPPCEXP1: | ||
423 | + case A_AHBNSPPPCEXP2: | ||
424 | + case A_AHBNSPPPCEXP3: | ||
425 | + case A_APBNSPPPC0: | ||
426 | + case A_APBNSPPPC1: | ||
427 | + case A_APBNSPPPCEXP0: | ||
428 | + case A_APBNSPPPCEXP1: | ||
429 | + case A_APBNSPPPCEXP2: | ||
430 | + case A_APBNSPPPCEXP3: | ||
431 | + qemu_log_mask(LOG_UNIMP, | ||
432 | + "IoTKit SecCtl NS block write: " | ||
433 | + "unimplemented offset 0x%x\n", offset); | ||
434 | + break; | ||
435 | + case A_AHBNSPPPC0: | ||
436 | + case A_PID4: | ||
437 | + case A_PID5: | ||
438 | + case A_PID6: | ||
439 | + case A_PID7: | ||
440 | + case A_PID0: | ||
441 | + case A_PID1: | ||
442 | + case A_PID2: | ||
443 | + case A_PID3: | ||
444 | + case A_CID0: | ||
445 | + case A_CID1: | ||
446 | + case A_CID2: | ||
447 | + case A_CID3: | ||
448 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
449 | + "IoTKit SecCtl NS block write: " | ||
450 | + "read-only offset 0x%x\n", offset); | ||
451 | + break; | ||
452 | + default: | ||
453 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
454 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
455 | + offset); | ||
456 | + break; | ||
457 | + } | ||
458 | + | ||
459 | + return MEMTX_OK; | ||
460 | +} | 134 | +} |
461 | + | 135 | + |
462 | +static const MemoryRegionOps iotkit_secctl_s_ops = { | 136 | /* |
463 | + .read_with_attrs = iotkit_secctl_s_read, | 137 | * Multiply and multiply accumulate |
464 | + .write_with_attrs = iotkit_secctl_s_write, | 138 | */ |
465 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
466 | + .valid.min_access_size = 1, | ||
467 | + .valid.max_access_size = 4, | ||
468 | + .impl.min_access_size = 1, | ||
469 | + .impl.max_access_size = 4, | ||
470 | +}; | ||
471 | + | ||
472 | +static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
473 | + .read_with_attrs = iotkit_secctl_ns_read, | ||
474 | + .write_with_attrs = iotkit_secctl_ns_write, | ||
475 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
476 | + .valid.min_access_size = 1, | ||
477 | + .valid.max_access_size = 4, | ||
478 | + .impl.min_access_size = 1, | ||
479 | + .impl.max_access_size = 4, | ||
480 | +}; | ||
481 | + | ||
482 | +static void iotkit_secctl_reset(DeviceState *dev) | ||
483 | +{ | ||
484 | + | ||
485 | +} | ||
486 | + | ||
487 | +static void iotkit_secctl_init(Object *obj) | ||
488 | +{ | ||
489 | + IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
490 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
491 | + | ||
492 | + memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | + s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | + memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops, | ||
495 | + s, "iotkit-secctl-ns-regs", 0x1000); | ||
496 | + sysbus_init_mmio(sbd, &s->s_regs); | ||
497 | + sysbus_init_mmio(sbd, &s->ns_regs); | ||
498 | +} | ||
499 | + | ||
500 | +static const VMStateDescription iotkit_secctl_vmstate = { | ||
501 | + .name = "iotkit-secctl", | ||
502 | + .version_id = 1, | ||
503 | + .minimum_version_id = 1, | ||
504 | + .fields = (VMStateField[]) { | ||
505 | + VMSTATE_END_OF_LIST() | ||
506 | + } | ||
507 | +}; | ||
508 | + | ||
509 | +static void iotkit_secctl_class_init(ObjectClass *klass, void *data) | ||
510 | +{ | ||
511 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
512 | + | ||
513 | + dc->vmsd = &iotkit_secctl_vmstate; | ||
514 | + dc->reset = iotkit_secctl_reset; | ||
515 | +} | ||
516 | + | ||
517 | +static const TypeInfo iotkit_secctl_info = { | ||
518 | + .name = TYPE_IOTKIT_SECCTL, | ||
519 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
520 | + .instance_size = sizeof(IoTKitSecCtl), | ||
521 | + .instance_init = iotkit_secctl_init, | ||
522 | + .class_init = iotkit_secctl_class_init, | ||
523 | +}; | ||
524 | + | ||
525 | +static void iotkit_secctl_register_types(void) | ||
526 | +{ | ||
527 | + type_register_static(&iotkit_secctl_info); | ||
528 | +} | ||
529 | + | ||
530 | +type_init(iotkit_secctl_register_types); | ||
531 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
532 | index XXXXXXX..XXXXXXX 100644 | ||
533 | --- a/default-configs/arm-softmmu.mak | ||
534 | +++ b/default-configs/arm-softmmu.mak | ||
535 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
536 | CONFIG_MPS2_SCC=y | ||
537 | |||
538 | CONFIG_TZ_PPC=y | ||
539 | +CONFIG_IOTKIT_SECCTL=y | ||
540 | |||
541 | CONFIG_VERSATILE_PCI=y | ||
542 | CONFIG_VERSATILE_I2C=y | ||
543 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
544 | index XXXXXXX..XXXXXXX 100644 | ||
545 | --- a/hw/misc/trace-events | ||
546 | +++ b/hw/misc/trace-events | ||
547 | @@ -XXX,XX +XXX,XX @@ tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
548 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
549 | tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
550 | tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
551 | + | ||
552 | +# hw/misc/iotkit-secctl.c | ||
553 | +iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
554 | +iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
555 | +iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
556 | +iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
557 | +iotkit_secctl_reset(void) "IoTKit SecCtl: reset" | ||
558 | -- | 139 | -- |
559 | 2.16.2 | 140 | 2.20.1 |
560 | 141 | ||
561 | 142 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add remaining easy registers to iotkit-secctl: | ||
2 | * NSCCFG just routes its two bits out to external GPIO lines | ||
3 | * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's | ||
4 | bus fabric can never report errors | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180220180325.29818-18-peter.maydell@linaro.org | ||
8 | --- | ||
9 | include/hw/misc/iotkit-secctl.h | 4 ++++ | ||
10 | hw/misc/iotkit-secctl.c | 32 ++++++++++++++++++++++++++------ | ||
11 | 2 files changed, 30 insertions(+), 6 deletions(-) | ||
12 | |||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/misc/iotkit-secctl.h | ||
16 | +++ b/include/hw/misc/iotkit-secctl.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
19 | * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | ||
20 | * should RAZ/WI or bus error | ||
21 | + * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value | ||
22 | * Controlling the 2 APB PPCs in the IoTKit: | ||
23 | * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
24 | * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
25 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
26 | |||
27 | /*< public >*/ | ||
28 | qemu_irq sec_resp_cfg; | ||
29 | + qemu_irq nsc_cfg_irq; | ||
30 | |||
31 | MemoryRegion s_regs; | ||
32 | MemoryRegion ns_regs; | ||
33 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
34 | uint32_t secppcintstat; | ||
35 | uint32_t secppcinten; | ||
36 | uint32_t secrespcfg; | ||
37 | + uint32_t nsccfg; | ||
38 | + uint32_t brginten; | ||
39 | |||
40 | IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
41 | IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
42 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/misc/iotkit-secctl.c | ||
45 | +++ b/hw/misc/iotkit-secctl.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
47 | case A_SECRESPCFG: | ||
48 | r = s->secrespcfg; | ||
49 | break; | ||
50 | + case A_NSCCFG: | ||
51 | + r = s->nsccfg; | ||
52 | + break; | ||
53 | case A_SECPPCINTSTAT: | ||
54 | r = s->secppcintstat; | ||
55 | break; | ||
56 | case A_SECPPCINTEN: | ||
57 | r = s->secppcinten; | ||
58 | break; | ||
59 | + case A_BRGINTSTAT: | ||
60 | + /* QEMU's bus fabric can never report errors as it doesn't buffer | ||
61 | + * writes, so we never report bridge interrupts. | ||
62 | + */ | ||
63 | + r = 0; | ||
64 | + break; | ||
65 | + case A_BRGINTEN: | ||
66 | + r = s->brginten; | ||
67 | + break; | ||
68 | case A_AHBNSPPCEXP0: | ||
69 | case A_AHBNSPPCEXP1: | ||
70 | case A_AHBNSPPCEXP2: | ||
71 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
72 | case A_APBSPPPCEXP3: | ||
73 | r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
74 | break; | ||
75 | - case A_NSCCFG: | ||
76 | case A_SECMPCINTSTATUS: | ||
77 | case A_SECMSCINTSTAT: | ||
78 | case A_SECMSCINTEN: | ||
79 | - case A_BRGINTSTAT: | ||
80 | - case A_BRGINTEN: | ||
81 | case A_NSMSCEXP: | ||
82 | qemu_log_mask(LOG_UNIMP, | ||
83 | "IoTKit SecCtl S block read: " | ||
84 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
85 | } | ||
86 | |||
87 | switch (offset) { | ||
88 | + case A_NSCCFG: | ||
89 | + s->nsccfg = value & 3; | ||
90 | + qemu_set_irq(s->nsc_cfg_irq, s->nsccfg); | ||
91 | + break; | ||
92 | case A_SECRESPCFG: | ||
93 | value &= 1; | ||
94 | s->secrespcfg = value; | ||
95 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
96 | s->secppcinten = value & 0x00f000f3; | ||
97 | foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
98 | break; | ||
99 | + case A_BRGINTCLR: | ||
100 | + break; | ||
101 | + case A_BRGINTEN: | ||
102 | + s->brginten = value & 0xffff0000; | ||
103 | + break; | ||
104 | case A_AHBNSPPCEXP0: | ||
105 | case A_AHBNSPPCEXP1: | ||
106 | case A_AHBNSPPCEXP2: | ||
107 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
108 | ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
109 | iotkit_secctl_ppc_sp_write(ppc, value); | ||
110 | break; | ||
111 | - case A_NSCCFG: | ||
112 | case A_SECMSCINTCLR: | ||
113 | case A_SECMSCINTEN: | ||
114 | - case A_BRGINTCLR: | ||
115 | - case A_BRGINTEN: | ||
116 | qemu_log_mask(LOG_UNIMP, | ||
117 | "IoTKit SecCtl S block write: " | ||
118 | "unimplemented offset 0x%x\n", offset); | ||
119 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_reset(DeviceState *dev) | ||
120 | s->secppcintstat = 0; | ||
121 | s->secppcinten = 0; | ||
122 | s->secrespcfg = 0; | ||
123 | + s->nsccfg = 0; | ||
124 | + s->brginten = 0; | ||
125 | |||
126 | foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
127 | } | ||
128 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
129 | } | ||
130 | |||
131 | qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
132 | + qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); | ||
133 | |||
134 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
135 | s, "iotkit-secctl-s-regs", 0x1000); | ||
136 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_vmstate = { | ||
137 | VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
138 | VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
139 | VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
140 | + VMSTATE_UINT32(nsccfg, IoTKitSecCtl), | ||
141 | + VMSTATE_UINT32(brginten, IoTKitSecCtl), | ||
142 | VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
143 | iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
144 | VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
145 | -- | ||
146 | 2.16.2 | ||
147 | |||
148 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Not enabled anywhere yet. | ||
4 | |||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180228193125.20577-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 1 + | ||
12 | linux-user/elfload.c | 1 + | ||
13 | 2 files changed, 2 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
20 | ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ | ||
21 | ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ | ||
22 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | ||
23 | + ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | ||
24 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | ||
25 | }; | ||
26 | |||
27 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/linux-user/elfload.c | ||
30 | +++ b/linux-user/elfload.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
32 | GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); | ||
33 | GET_FEATURE(ARM_FEATURE_V8_FP16, | ||
34 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | ||
35 | + GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | ||
36 | #undef GET_FEATURE | ||
37 | |||
38 | return hwcaps; | ||
39 | -- | ||
40 | 2.16.2 | ||
41 | |||
42 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Include the U bit in the switches rather than testing separately. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-3-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------ | ||
11 | 1 file changed, 61 insertions(+), 68 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-a64.c | ||
16 | +++ b/target/arm/translate-a64.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
18 | int index; | ||
19 | TCGv_ptr fpst; | ||
20 | |||
21 | - switch (opcode) { | ||
22 | - case 0x0: /* MLA */ | ||
23 | - case 0x4: /* MLS */ | ||
24 | - if (!u || is_scalar) { | ||
25 | + switch (16 * u + opcode) { | ||
26 | + case 0x08: /* MUL */ | ||
27 | + case 0x10: /* MLA */ | ||
28 | + case 0x14: /* MLS */ | ||
29 | + if (is_scalar) { | ||
30 | unallocated_encoding(s); | ||
31 | return; | ||
32 | } | ||
33 | break; | ||
34 | - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | ||
35 | - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | ||
36 | - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | ||
37 | + case 0x02: /* SMLAL, SMLAL2 */ | ||
38 | + case 0x12: /* UMLAL, UMLAL2 */ | ||
39 | + case 0x06: /* SMLSL, SMLSL2 */ | ||
40 | + case 0x16: /* UMLSL, UMLSL2 */ | ||
41 | + case 0x0a: /* SMULL, SMULL2 */ | ||
42 | + case 0x1a: /* UMULL, UMULL2 */ | ||
43 | if (is_scalar) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | is_long = true; | ||
48 | break; | ||
49 | - case 0x3: /* SQDMLAL, SQDMLAL2 */ | ||
50 | - case 0x7: /* SQDMLSL, SQDMLSL2 */ | ||
51 | - case 0xb: /* SQDMULL, SQDMULL2 */ | ||
52 | + case 0x03: /* SQDMLAL, SQDMLAL2 */ | ||
53 | + case 0x07: /* SQDMLSL, SQDMLSL2 */ | ||
54 | + case 0x0b: /* SQDMULL, SQDMULL2 */ | ||
55 | is_long = true; | ||
56 | - /* fall through */ | ||
57 | - case 0xc: /* SQDMULH */ | ||
58 | - case 0xd: /* SQRDMULH */ | ||
59 | - if (u) { | ||
60 | - unallocated_encoding(s); | ||
61 | - return; | ||
62 | - } | ||
63 | break; | ||
64 | - case 0x8: /* MUL */ | ||
65 | - if (u || is_scalar) { | ||
66 | - unallocated_encoding(s); | ||
67 | - return; | ||
68 | - } | ||
69 | + case 0x0c: /* SQDMULH */ | ||
70 | + case 0x0d: /* SQRDMULH */ | ||
71 | break; | ||
72 | - case 0x1: /* FMLA */ | ||
73 | - case 0x5: /* FMLS */ | ||
74 | - if (u) { | ||
75 | - unallocated_encoding(s); | ||
76 | - return; | ||
77 | - } | ||
78 | - /* fall through */ | ||
79 | - case 0x9: /* FMUL, FMULX */ | ||
80 | + case 0x01: /* FMLA */ | ||
81 | + case 0x05: /* FMLS */ | ||
82 | + case 0x09: /* FMUL */ | ||
83 | + case 0x19: /* FMULX */ | ||
84 | if (size == 1) { | ||
85 | unallocated_encoding(s); | ||
86 | return; | ||
87 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
88 | |||
89 | read_vec_element(s, tcg_op, rn, pass, MO_64); | ||
90 | |||
91 | - switch (opcode) { | ||
92 | - case 0x5: /* FMLS */ | ||
93 | + switch (16 * u + opcode) { | ||
94 | + case 0x05: /* FMLS */ | ||
95 | /* As usual for ARM, separate negation for fused multiply-add */ | ||
96 | gen_helper_vfp_negd(tcg_op, tcg_op); | ||
97 | /* fall through */ | ||
98 | - case 0x1: /* FMLA */ | ||
99 | + case 0x01: /* FMLA */ | ||
100 | read_vec_element(s, tcg_res, rd, pass, MO_64); | ||
101 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | ||
102 | break; | ||
103 | - case 0x9: /* FMUL, FMULX */ | ||
104 | - if (u) { | ||
105 | - gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
106 | - } else { | ||
107 | - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
108 | - } | ||
109 | + case 0x09: /* FMUL */ | ||
110 | + gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
111 | + break; | ||
112 | + case 0x19: /* FMULX */ | ||
113 | + gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
114 | break; | ||
115 | default: | ||
116 | g_assert_not_reached(); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
118 | |||
119 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); | ||
120 | |||
121 | - switch (opcode) { | ||
122 | - case 0x0: /* MLA */ | ||
123 | - case 0x4: /* MLS */ | ||
124 | - case 0x8: /* MUL */ | ||
125 | + switch (16 * u + opcode) { | ||
126 | + case 0x08: /* MUL */ | ||
127 | + case 0x10: /* MLA */ | ||
128 | + case 0x14: /* MLS */ | ||
129 | { | ||
130 | static NeonGenTwoOpFn * const fns[2][2] = { | ||
131 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | ||
132 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
133 | genfn(tcg_res, tcg_op, tcg_res); | ||
134 | break; | ||
135 | } | ||
136 | - case 0x5: /* FMLS */ | ||
137 | - case 0x1: /* FMLA */ | ||
138 | + case 0x05: /* FMLS */ | ||
139 | + case 0x01: /* FMLA */ | ||
140 | read_vec_element_i32(s, tcg_res, rd, pass, | ||
141 | is_scalar ? size : MO_32); | ||
142 | switch (size) { | ||
143 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
144 | g_assert_not_reached(); | ||
145 | } | ||
146 | break; | ||
147 | - case 0x9: /* FMUL, FMULX */ | ||
148 | + case 0x09: /* FMUL */ | ||
149 | switch (size) { | ||
150 | case 1: | ||
151 | - if (u) { | ||
152 | - if (is_scalar) { | ||
153 | - gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
154 | - tcg_idx, fpst); | ||
155 | - } else { | ||
156 | - gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
157 | - tcg_idx, fpst); | ||
158 | - } | ||
159 | + if (is_scalar) { | ||
160 | + gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
161 | + tcg_idx, fpst); | ||
162 | } else { | ||
163 | - if (is_scalar) { | ||
164 | - gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
165 | - tcg_idx, fpst); | ||
166 | - } else { | ||
167 | - gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
168 | - tcg_idx, fpst); | ||
169 | - } | ||
170 | + gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
171 | + tcg_idx, fpst); | ||
172 | } | ||
173 | break; | ||
174 | case 2: | ||
175 | - if (u) { | ||
176 | - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
177 | - } else { | ||
178 | - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
179 | - } | ||
180 | + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
181 | break; | ||
182 | default: | ||
183 | g_assert_not_reached(); | ||
184 | } | ||
185 | break; | ||
186 | - case 0xc: /* SQDMULH */ | ||
187 | + case 0x19: /* FMULX */ | ||
188 | + switch (size) { | ||
189 | + case 1: | ||
190 | + if (is_scalar) { | ||
191 | + gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
192 | + tcg_idx, fpst); | ||
193 | + } else { | ||
194 | + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
195 | + tcg_idx, fpst); | ||
196 | + } | ||
197 | + break; | ||
198 | + case 2: | ||
199 | + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
200 | + break; | ||
201 | + default: | ||
202 | + g_assert_not_reached(); | ||
203 | + } | ||
204 | + break; | ||
205 | + case 0x0c: /* SQDMULH */ | ||
206 | if (size == 1) { | ||
207 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | ||
208 | tcg_op, tcg_idx); | ||
209 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
210 | tcg_op, tcg_idx); | ||
211 | } | ||
212 | break; | ||
213 | - case 0xd: /* SQRDMULH */ | ||
214 | + case 0x0d: /* SQRDMULH */ | ||
215 | if (size == 1) { | ||
216 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | ||
217 | tcg_op, tcg_idx); | ||
218 | -- | ||
219 | 2.16.2 | ||
220 | |||
221 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The integer size check was already outside of the opcode switch; | ||
4 | move the floating-point size check outside as well. Unify the | ||
5 | size vs index adjustment between fp and integer paths. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20180228193125.20577-4-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate-a64.c | 65 +++++++++++++++++++++++----------------------- | ||
13 | 1 file changed, 32 insertions(+), 33 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-a64.c | ||
18 | +++ b/target/arm/translate-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
20 | case 0x05: /* FMLS */ | ||
21 | case 0x09: /* FMUL */ | ||
22 | case 0x19: /* FMULX */ | ||
23 | - if (size == 1) { | ||
24 | - unallocated_encoding(s); | ||
25 | - return; | ||
26 | - } | ||
27 | is_fp = true; | ||
28 | break; | ||
29 | default: | ||
30 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
31 | if (is_fp) { | ||
32 | /* convert insn encoded size to TCGMemOp size */ | ||
33 | switch (size) { | ||
34 | - case 2: /* single precision */ | ||
35 | - size = MO_32; | ||
36 | - index = h << 1 | l; | ||
37 | - rm |= (m << 4); | ||
38 | - break; | ||
39 | - case 3: /* double precision */ | ||
40 | - size = MO_64; | ||
41 | - if (l || !is_q) { | ||
42 | + case 0: /* half-precision */ | ||
43 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | - index = h; | ||
48 | - rm |= (m << 4); | ||
49 | - break; | ||
50 | - case 0: /* half precision */ | ||
51 | size = MO_16; | ||
52 | - index = h << 2 | l << 1 | m; | ||
53 | - is_fp16 = true; | ||
54 | - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
55 | - break; | ||
56 | - } | ||
57 | - /* fallthru */ | ||
58 | - default: /* unallocated */ | ||
59 | - unallocated_encoding(s); | ||
60 | - return; | ||
61 | - } | ||
62 | - } else { | ||
63 | - switch (size) { | ||
64 | - case 1: | ||
65 | - index = h << 2 | l << 1 | m; | ||
66 | break; | ||
67 | - case 2: | ||
68 | - index = h << 1 | l; | ||
69 | - rm |= (m << 4); | ||
70 | + case MO_32: /* single precision */ | ||
71 | + case MO_64: /* double precision */ | ||
72 | break; | ||
73 | default: | ||
74 | unallocated_encoding(s); | ||
75 | return; | ||
76 | } | ||
77 | + } else { | ||
78 | + switch (size) { | ||
79 | + case MO_8: | ||
80 | + case MO_64: | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + } | ||
85 | + | ||
86 | + /* Given TCGMemOp size, adjust register and indexing. */ | ||
87 | + switch (size) { | ||
88 | + case MO_16: | ||
89 | + index = h << 2 | l << 1 | m; | ||
90 | + break; | ||
91 | + case MO_32: | ||
92 | + index = h << 1 | l; | ||
93 | + rm |= m << 4; | ||
94 | + break; | ||
95 | + case MO_64: | ||
96 | + if (l || !is_q) { | ||
97 | + unallocated_encoding(s); | ||
98 | + return; | ||
99 | + } | ||
100 | + index = h; | ||
101 | + rm |= m << 4; | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | } | ||
106 | |||
107 | if (!fp_access_check(s)) { | ||
108 | -- | ||
109 | 2.16.2 | ||
110 | |||
111 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180228193125.20577-10-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.c | 1 + | ||
11 | target/arm/cpu64.c | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | ||
19 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | ||
20 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
21 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
23 | cpu->midr = 0xffffffff; | ||
24 | } | ||
25 | #endif | ||
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/cpu64.c | ||
29 | +++ b/target/arm/cpu64.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | ||
31 | set_feature(&cpu->env, ARM_FEATURE_V8_SM4); | ||
32 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
33 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
35 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | ||
36 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
37 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Not enabled anywhere yet. | ||
4 | |||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180228193125.20577-11-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.h | 1 + | ||
11 | linux-user/elfload.c | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
19 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | ||
20 | ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | ||
21 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | ||
22 | + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ | ||
23 | }; | ||
24 | |||
25 | static inline int arm_feature(CPUARMState *env, int feature) | ||
26 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/linux-user/elfload.c | ||
29 | +++ b/linux-user/elfload.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
31 | GET_FEATURE(ARM_FEATURE_V8_FP16, | ||
32 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | ||
33 | GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | ||
34 | + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); | ||
35 | #undef GET_FEATURE | ||
36 | |||
37 | return hwcaps; | ||
38 | -- | ||
39 | 2.16.2 | ||
40 | |||
41 | diff view generated by jsdifflib |