Second pull request of the week; mostly RTH's support for some

new-in-v8.1/v8.3 instructions, and my v8M board model.

thanks

-- PMM

The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302

for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078:

target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000)

* implement FCMA and RDM v8.1 and v8.3 instructions

* enable Cortex-M33 v8M core, and provide new mps2-an505 board model

that uses it

* decodetree: Propagate return value from translate subroutines

* xlnx-zynqmp: Implement the RTC device

Alistair Francis (3):

xlnx-zynqmp-rtc: Initial commit

xlnx-zynqmp-rtc: Add basic time support

xlnx-zynqmp: Connect the RTC device

Peter Maydell (19):

loader: Add new load_ramdisk_as()

hw/arm/boot: Honour CPU's address space for image loads

hw/arm/armv7m: Honour CPU's address space for image loads

target/arm: Define an IDAU interface

armv7m: Forward idau property to CPU object

target/arm: Define init-svtor property for the reset secure VTOR value

armv7m: Forward init-svtor property to CPU object

target/arm: Add Cortex-M33

hw/misc/unimp: Move struct to header file

include/hw/or-irq.h: Add missing include guard

qdev: Add new qdev_init_gpio_in_named_with_opaque()

hw/core/split-irq: Device that splits IRQ lines

hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505

hw/misc/tz-ppc: Model TrustZone peripheral protection controller

hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton

hw/misc/iotkit-secctl: Add handling for PPCs

hw/misc/iotkit-secctl: Add remaining simple registers

hw/arm/iotkit: Model Arm IOT Kit

mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image

Richard Henderson (17):

decodetree: Propagate return value from translate subroutines

target/arm: Add ARM_FEATURE_V8_RDM

target/arm: Refactor disas_simd_indexed decode

target/arm: Refactor disas_simd_indexed size checks

target/arm: Decode aa64 armv8.1 scalar three same extra

target/arm: Decode aa64 armv8.1 three same extra

target/arm: Decode aa64 armv8.1 scalar/vector x indexed element

target/arm: Decode aa32 armv8.1 three same

target/arm: Decode aa32 armv8.1 two reg and a scalar

target/arm: Enable ARM_FEATURE_V8_RDM

target/arm: Add ARM_FEATURE_V8_FCMA

target/arm: Decode aa64 armv8.3 fcadd

target/arm: Decode aa64 armv8.3 fcmla

target/arm: Decode aa32 armv8.3 3-same

target/arm: Decode aa32 armv8.3 2-reg-index

target/arm: Decode t32 simd 3reg and 2reg_scalar extension

target/arm: Enable ARM_FEATURE_V8_FCMA

hw/arm/Makefile.objs | 2 +

hw/core/Makefile.objs | 1 +

hw/misc/Makefile.objs | 4 +

hw/timer/Makefile.objs | 1 +

target/arm/Makefile.objs | 2 +-

include/hw/arm/armv7m.h | 5 +

include/hw/arm/iotkit.h | 109 ++++++

include/hw/arm/xlnx-zynqmp.h | 2 +

include/hw/core/split-irq.h | 57 +++

include/hw/irq.h | 4 +-

include/hw/loader.h | 12 +-

include/hw/misc/iotkit-secctl.h | 103 ++++++

include/hw/misc/mps2-fpgaio.h | 43 +++

include/hw/misc/tz-ppc.h | 101 ++++++

include/hw/misc/unimp.h | 10 +

include/hw/or-irq.h | 5 +

include/hw/qdev-core.h | 30 +-

include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++

target/arm/cpu.h | 8 +

target/arm/helper.h | 31 ++

target/arm/idau.h | 61 ++++

hw/arm/armv7m.c | 35 +-

hw/arm/boot.c | 119 ++++---

hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++

hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++

hw/arm/xlnx-zynqmp.c | 14 +

hw/core/loader.c | 8 +-

hw/core/qdev.c | 8 +-

hw/core/split-irq.c | 89 +++++

hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++

hw/misc/mps2-fpgaio.c | 176 ++++++++++

hw/misc/tz-ppc.c | 302 ++++++++++++++++

hw/misc/unimp.c | 10 -

hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++

linux-user/elfload.c | 2 +

target/arm/cpu.c | 66 +++-

target/arm/cpu64.c | 2 +

target/arm/helper.c | 28 +-

target/arm/translate-a64.c | 514 +++++++++++++++++++++------

target/arm/translate.c | 275 +++++++++++++--

target/arm/vec_helper.c | 429 ++++++++++++++++++++++

default-configs/arm-softmmu.mak | 5 +

hw/misc/trace-events | 24 ++

hw/timer/trace-events | 3 +

scripts/decodetree.py | 5 +-

45 files changed, 4668 insertions(+), 200 deletions(-)

create mode 100644 include/hw/arm/iotkit.h

create mode 100644 include/hw/core/split-irq.h

create mode 100644 include/hw/misc/iotkit-secctl.h

create mode 100644 include/hw/misc/mps2-fpgaio.h

create mode 100644 include/hw/misc/tz-ppc.h

create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h

create mode 100644 target/arm/idau.h

create mode 100644 hw/arm/iotkit.c

create mode 100644 hw/arm/mps2-tz.c

create mode 100644 hw/core/split-irq.c

create mode 100644 hw/misc/iotkit-secctl.c

create mode 100644 hw/misc/mps2-fpgaio.c

create mode 100644 hw/misc/tz-ppc.c

create mode 100644 hw/timer/xlnx-zynqmp-rtc.c

create mode 100644 target/arm/vec_helper.c

From: Alistair Francis <alistair.francis@xilinx.com>

Allow the guest to determine the time set from the QEMU command line.

This includes adding a trace event to debug the new time.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

include/hw/timer/xlnx-zynqmp-rtc.h | 2 ++

hw/timer/xlnx-zynqmp-rtc.c | 58 ++++++++++++++++++++++++++++++++++++++

hw/timer/trace-events | 3 ++

3 files changed, 63 insertions(+)

diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h

--- a/include/hw/timer/xlnx-zynqmp-rtc.h

+++ b/include/hw/timer/xlnx-zynqmp-rtc.h

@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPRTC {

qemu_irq irq_rtc_int;

qemu_irq irq_addr_error_int;

+ uint32_t tick_offset;

+

uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX];

RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX];

} XlnxZynqMPRTC;

diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/xlnx-zynqmp-rtc.c

+++ b/hw/timer/xlnx-zynqmp-rtc.c

@@ -XXX,XX +XXX,XX @@

#include "hw/register.h"

#include "qemu/bitops.h"

#include "qemu/log.h"

+#include "hw/ptimer.h"

+#include "qemu/cutils.h"

+#include "sysemu/sysemu.h"

+#include "trace.h"

#include "hw/timer/xlnx-zynqmp-rtc.h"

#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG

@@ -XXX,XX +XXX,XX @@ static void addr_error_int_update_irq(XlnxZynqMPRTC *s)

qemu_set_irq(s->irq_addr_error_int, pending);

}

+static uint32_t rtc_get_count(XlnxZynqMPRTC *s)

+{

+ int64_t now = qemu_clock_get_ns(rtc_clock);

+ return s->tick_offset + now / NANOSECONDS_PER_SECOND;

+}

+

+static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64)

+{

+ XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);

+

+ return rtc_get_count(s);

+}

+

static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)

{

XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);

@@ -XXX,XX +XXX,XX @@ static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)

static const RegisterAccessInfo rtc_regs_info[] = {

{ .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE,

+ .unimp = MAKE_64BIT_MASK(0, 32),

},{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ,

.ro = 0xffffffff,

+ .post_read = current_time_postr,

},{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE,

+ .unimp = MAKE_64BIT_MASK(0, 32),

},{ .name = "CALIB_READ", .addr = A_CALIB_READ,

.ro = 0x1fffff,

},{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME,

.ro = 0xffffffff,

+ .post_read = current_time_postr,

},{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK,

.ro = 0xffff,

},{ .name = "ALARM", .addr = A_ALARM,

@@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj)

XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);

SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

RegisterInfoArray *reg_array;

+ struct tm current_tm;

memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,

XLNX_ZYNQMP_RTC_R_MAX * 4);

@@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj)

sysbus_init_mmio(sbd, &s->iomem);

sysbus_init_irq(sbd, &s->irq_rtc_int);

sysbus_init_irq(sbd, &s->irq_addr_error_int);

+

+ qemu_get_timedate(&current_tm, 0);

+ s->tick_offset = mktimegm(&current_tm) -

+ qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;

+

+ trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon,

+ current_tm.tm_mday, current_tm.tm_hour,

+ current_tm.tm_min, current_tm.tm_sec);

+}

+

+static int rtc_pre_save(void *opaque)

+{

+ XlnxZynqMPRTC *s = opaque;

+ int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;

+

+ /* Add the time at migration */

+ s->tick_offset = s->tick_offset + now;

+

+ return 0;

+}

+

+static int rtc_post_load(void *opaque, int version_id)

+{

+ XlnxZynqMPRTC *s = opaque;

+ int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;

+

+ /* Subtract the time after migration. This combined with the pre_save

+ * action results in us having subtracted the time that the guest was

+ * stopped to the offset.

+ */

+ s->tick_offset = s->tick_offset - now;

+

+ return 0;

}

static const VMStateDescription vmstate_rtc = {

.name = TYPE_XLNX_ZYNQMP_RTC,

.version_id = 1,

.minimum_version_id = 1,

+ .pre_save = rtc_pre_save,

+ .post_load = rtc_post_load,

.fields = (VMStateField[]) {

VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),

+ VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC),

VMSTATE_END_OF_LIST(),

}

};

diff --git a/hw/timer/trace-events b/hw/timer/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/trace-events

+++ b/hw/timer/trace-events

@@ -XXX,XX +XXX,XX @@ systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr

cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset"

+

+# hw/timer/xlnx-zynqmp-rtc.c

+xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d"

2.16.2

Not enabled anywhere yet.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180228193125.20577-11-richard.henderson@linaro.org

target/arm/cpu.h | 1 +

linux-user/elfload.c | 1 +

2 files changed, 2 insertions(+)

@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)

GET_FEATURE(ARM_FEATURE_V8_FP16,

ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);

GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM);

+ GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA);

#undef GET_FEATURE

2.16.2

Instead of loading guest images to the system address space, use the

CPU's address space. This is important if we're trying to load the

file to memory or via an alias memory region that is provided by an

SoC object and thus not mapped into the system address space.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180220180325.29818-4-peter.maydell@linaro.org

hw/arm/armv7m.c | 17 ++++++++++++++---

1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c

--- a/hw/arm/armv7m.c

+++ b/hw/arm/armv7m.c

@@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)

uint64_t entry;

uint64_t lowaddr;

int big_endian;

+ AddressSpace *as;

+ int asidx;

+ CPUState *cs = CPU(cpu);

#ifdef TARGET_WORDS_BIGENDIAN

big_endian = 1;

@@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)

exit(1);

}

+ if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {

+ asidx = ARMASIdx_S;

+ } else {

+ asidx = ARMASIdx_NS;

+ }

+ as = cpu_get_address_space(cs, asidx);

+

if (kernel_filename) {

- image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,

- NULL, big_endian, EM_ARM, 1, 0);

+ image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr,

+ NULL, big_endian, EM_ARM, 1, 0, as);

if (image_size < 0) {

- image_size = load_image_targphys(kernel_filename, 0, mem_size);

+ image_size = load_image_targphys_as(kernel_filename, 0,

+ mem_size, as);

lowaddr = 0;

}

if (image_size < 0) {

2.16.2

Define a new board model for the MPS2 with an AN505 FPGA image

containing a Cortex-M33. Since the FPGA images for TrustZone

cores (AN505, and the similar AN519 for Cortex-M23) have a

significantly different layout of devices to the non-TrustZone

images, we use a new source file rather than shoehorning them

into the existing mps2.c.

Message-id: 20180220180325.29818-20-peter.maydell@linaro.org

hw/arm/Makefile.objs | 1 +

hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 504 insertions(+)

create mode 100644 hw/arm/mps2-tz.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

obj-$(CONFIG_MPS2) += mps2.o

+obj-$(CONFIG_MPS2) += mps2-tz.o

obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

obj-$(CONFIG_IOTKIT) += iotkit.o

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@

+ * ARM V2M MPS2 board emulation, trustzone aware FPGA images

+ *

+ * Copyright (c) 2017 Linaro Limited

+ * Written by Peter Maydell

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger

+ * FPGA but is otherwise the same as the 2). Since the CPU itself

+ * and most of the devices are in the FPGA, the details of the board

+ * as seen by the guest depend significantly on the FPGA image.

+ * This source file covers the following FPGA images, for TrustZone cores:

+ * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505

+ *

+ * Links to the TRM for the board itself and to the various Application

+ * Notes which document the FPGA images can be found here:

+ * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2

+ *

+ * Board TRM:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf

+ * Application Note AN505:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html

+ *

+ * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide

+ * (ARM ECM0601256) for the details of some of the device layout:

+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu/error-report.h"

+#include "hw/arm/arm.h"

+#include "hw/arm/armv7m.h"

+#include "hw/or-irq.h"

+#include "hw/boards.h"

+#include "exec/address-spaces.h"

+#include "sysemu/sysemu.h"

+#include "hw/misc/unimp.h"

+#include "hw/char/cmsdk-apb-uart.h"

+#include "hw/timer/cmsdk-apb-timer.h"

+#include "hw/misc/mps2-scc.h"

+#include "hw/misc/mps2-fpgaio.h"

+#include "hw/arm/iotkit.h"

+#include "hw/devices.h"

+#include "net/net.h"

+#include "hw/core/split-irq.h"

+

+typedef enum MPS2TZFPGAType {

+ FPGA_AN505,

+} MPS2TZFPGAType;

+

+typedef struct {

+ MachineClass parent;

+ MPS2TZFPGAType fpga_type;

+ uint32_t scc_id;

+} MPS2TZMachineClass;

+

+typedef struct {

+ MachineState parent;

+

+ IoTKit iotkit;

+ MemoryRegion psram;

+ MemoryRegion ssram1;

+ MemoryRegion ssram1_m;

+ MemoryRegion ssram23;

+ MPS2SCC scc;

+ MPS2FPGAIO fpgaio;

+ TZPPC ppc[5];

+ UnimplementedDeviceState ssram_mpc[3];

+ UnimplementedDeviceState spi[5];

+ UnimplementedDeviceState i2c[4];

+ UnimplementedDeviceState i2s_audio;

+ UnimplementedDeviceState gpio[5];

+ UnimplementedDeviceState dma[4];

+ UnimplementedDeviceState gfx;

+ CMSDKAPBUART uart[5];

+ SplitIRQ sec_resp_splitter;

+ qemu_or_irq uart_irq_orgate;

+} MPS2TZMachineState;

+

+#define TYPE_MPS2TZ_MACHINE "mps2tz"

+#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")

+

+#define MPS2TZ_MACHINE(obj) \

+ OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE)

+#define MPS2TZ_MACHINE_GET_CLASS(obj) \

+ OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE)

+#define MPS2TZ_MACHINE_CLASS(klass) \

+ OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE)

+

+/* Main SYSCLK frequency in Hz */

+#define SYSCLK_FRQ 20000000

+

+/* Initialize the auxiliary RAM region @mr and map it into

+ * the memory map at @base.

+ */

+static void make_ram(MemoryRegion *mr, const char *name,

+ hwaddr base, hwaddr size)

+ memory_region_init_ram(mr, NULL, name, size, &error_fatal);

+ memory_region_add_subregion(get_system_memory(), base, mr);

+/* Create an alias of an entire original MemoryRegion @orig

+ * located at @base in the memory map.

+ */

+static void make_ram_alias(MemoryRegion *mr, const char *name,

+ MemoryRegion *orig, hwaddr base)

+ memory_region_init_alias(mr, NULL, name, orig, 0,

+ memory_region_size(orig));

+ memory_region_add_subregion(get_system_memory(), base, mr);

+static void init_sysbus_child(Object *parent, const char *childname,

+ void *child, size_t childsize,

+ const char *childtype)

+ object_initialize(child, childsize, childtype);

+ object_property_add_child(parent, childname, OBJECT(child), &error_abort);

+ qdev_set_parent_bus(DEVICE(child), sysbus_get_default());

+

+/* Most of the devices in the AN505 FPGA image sit behind

+ * Peripheral Protection Controllers. These data structures

+ * define the layout of which devices sit behind which PPCs.

+ * The devfn for each port is a function which creates, configures

+ * and initializes the device, returning the MemoryRegion which

+ * needs to be plugged into the downstream end of the PPC port.

+ */

+typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size);

+

+typedef struct PPCPortInfo {

+ const char *name;

+ MakeDevFn *devfn;

+ void *opaque;

+ hwaddr addr;

+ hwaddr size;

+} PPCPortInfo;

+

+typedef struct PPCInfo {

+ const char *name;

+ PPCPortInfo ports[TZ_NUM_PORTS];

+} PPCInfo;

+

+static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,

+ void *opaque,

+ const char *name, hwaddr size)

+ /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,

+ * and return a pointer to its MemoryRegion.

+ */

+ UnimplementedDeviceState *uds = opaque;

+

+ init_sysbus_child(OBJECT(mms), name, uds,

+ sizeof(UnimplementedDeviceState),

+ TYPE_UNIMPLEMENTED_DEVICE);

+ qdev_prop_set_string(DEVICE(uds), "name", name);

+ qdev_prop_set_uint64(DEVICE(uds), "size", size);

+ object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);

+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);

+static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size)

+{

+ CMSDKAPBUART *uart = opaque;

+ int i = uart - &mms->uart[0];

+ Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;

+ int rxirqno = i * 2;

+ int txirqno = i * 2 + 1;

+ int combirqno = i + 10;

+ SysBusDevice *s;

+ DeviceState *iotkitdev = DEVICE(&mms->iotkit);

+ DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);

+

+ init_sysbus_child(OBJECT(mms), name, uart,

+ sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);

+ qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr);

+ qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);

+ object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);

+ s = SYS_BUS_DEVICE(uart);

+ sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,

+ "EXP_IRQ", txirqno));

+ sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,

+ "EXP_IRQ", rxirqno));

+ sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));

+ sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));

+ sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev,

+ "EXP_IRQ", combirqno));

+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);

+}

+

+static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size)

+{

+ MPS2SCC *scc = opaque;

+ DeviceState *sccdev;

+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);

+

+ object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC);

+ sccdev = DEVICE(scc);

+ qdev_set_parent_bus(sccdev, sysbus_get_default());

+ qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);

+ qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);

+ qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);

+ object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal);

+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);

+}

+

+static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size)

+{

+ MPS2FPGAIO *fpgaio = opaque;

+

+ object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);

+ qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default());

+ object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);

+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);

+}

+

+static void mps2tz_common_init(MachineState *machine)

+{

+ MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);

+ MachineClass *mc = MACHINE_GET_CLASS(machine);

+ MemoryRegion *system_memory = get_system_memory();

+ DeviceState *iotkitdev;

+ DeviceState *dev_splitter;

+ int i;

+

+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {

+ error_report("This board can only be used with CPU %s",

+ mc->default_cpu_type);

+ exit(1);

+ }

+

+ init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit,

+ sizeof(mms->iotkit), TYPE_IOTKIT);

+ iotkitdev = DEVICE(&mms->iotkit);

+ object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),

+ "memory", &error_abort);

+ qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92);

+ qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);

+ object_property_set_bool(OBJECT(&mms->iotkit), true, "realized",

+ &error_fatal);

+

+ /* The sec_resp_cfg output from the IoTKit must be split into multiple

+ * lines, one for each of the PPCs we create here.

+ */

+ object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),

+ TYPE_SPLIT_IRQ);

+ object_property_add_child(OBJECT(machine), "sec-resp-splitter",

+ OBJECT(&mms->sec_resp_splitter), &error_abort);

+ object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5,

+ "num-lines", &error_fatal);

+ object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,

+ "realized", &error_fatal);

+ dev_splitter = DEVICE(&mms->sec_resp_splitter);

+ qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,

+ qdev_get_gpio_in(dev_splitter, 0));

+

+ /* The IoTKit sets up much of the memory layout, including

+ * the aliases between secure and non-secure regions in the

+ * address space. The FPGA itself contains:

+ *

+ * 0x00000000..0x003fffff SSRAM1

+ * 0x00400000..0x007fffff alias of SSRAM1

+ * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3

+ * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices

+ * 0x80000000..0x80ffffff 16MB PSRAM

+ */

+

+ /* The FPGA images have an odd combination of different RAMs,

+ * because in hardware they are different implementations and

+ * connected to different buses, giving varying performance/size

+ * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily

+ * call the 16MB our "system memory", as it's the largest lump.

+ */

+ memory_region_allocate_system_memory(&mms->psram,

+ NULL, "mps.ram", 0x01000000);

+ memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);

+

+ /* The SSRAM memories should all be behind Memory Protection Controllers,

+ * but we don't implement that yet.

+ */

+ make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000);

+ make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000);

+

+ make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000);

+

+ /* The overflow IRQs for all UARTs are ORed together.

+ * Tx, Rx and "combined" IRQs are sent to the NVIC separately.

+ * Create the OR gate for this.

+ */

+ object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),

+ TYPE_OR_IRQ);

+ object_property_add_child(OBJECT(mms), "uart-irq-orgate",

+ OBJECT(&mms->uart_irq_orgate), &error_abort);

+ object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",

+ &error_fatal);

+ object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,

+ "realized", &error_fatal);

+ qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,

+ qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15));

+

+ /* Most of the devices in the FPGA are behind Peripheral Protection

+ * Controllers. The required order for initializing things is:

+ * + initialize the PPC

+ * + initialize, configure and realize downstream devices

+ * + connect downstream device MemoryRegions to the PPC

+ * + realize the PPC

+ * + map the PPC's MemoryRegions to the places in the address map

+ * where the downstream devices should appear

+ * + wire up the PPC's control lines to the IoTKit object

+ */

+

+ const PPCInfo ppcs[] = { {

+ .name = "apb_ppcexp0",

+ .ports = {

+ { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0],

+ 0x58007000, 0x1000 },

+ { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1],

+ 0x58008000, 0x1000 },

+ { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2],

+ 0x58009000, 0x1000 },

+ },

+ }, {

+ .name = "apb_ppcexp1",

+ .ports = {

+ { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 },

+ { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 },

+ { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 },

+ { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 },

+ { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 },

+ { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },

+ { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },

+ { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },

+ { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },

+ { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },

+ { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },

+ { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },

+ { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },

+ { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },

+ },

+ }, {

+ .name = "apb_ppcexp2",

+ .ports = {

+ { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },

+ { "i2s-audio", make_unimp_dev, &mms->i2s_audio,

+ 0x40301000, 0x1000 },

+ { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },

+ },

+ }, {

+ .name = "ahb_ppcexp0",

+ .ports = {

+ { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },

+ { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },

+ { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },

+ { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },

+ { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },

+ { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 },

+ },

+ }, {