Second pull request of the week; mostly RTH's support for some

new-in-v8.1/v8.3 instructions, and my v8M board model.

The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302

for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078:

target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000)

* implement FCMA and RDM v8.1 and v8.3 instructions

* enable Cortex-M33 v8M core, and provide new mps2-an505 board model

that uses it

* decodetree: Propagate return value from translate subroutines

* xlnx-zynqmp: Implement the RTC device

Alistair Francis (3):

xlnx-zynqmp-rtc: Initial commit

xlnx-zynqmp-rtc: Add basic time support

xlnx-zynqmp: Connect the RTC device

Peter Maydell (19):

loader: Add new load_ramdisk_as()

hw/arm/boot: Honour CPU's address space for image loads

hw/arm/armv7m: Honour CPU's address space for image loads

target/arm: Define an IDAU interface

armv7m: Forward idau property to CPU object

target/arm: Define init-svtor property for the reset secure VTOR value

armv7m: Forward init-svtor property to CPU object

target/arm: Add Cortex-M33

hw/misc/unimp: Move struct to header file

include/hw/or-irq.h: Add missing include guard

qdev: Add new qdev_init_gpio_in_named_with_opaque()

hw/core/split-irq: Device that splits IRQ lines

hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505

hw/misc/tz-ppc: Model TrustZone peripheral protection controller

hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton

hw/misc/iotkit-secctl: Add handling for PPCs

hw/misc/iotkit-secctl: Add remaining simple registers

hw/arm/iotkit: Model Arm IOT Kit

mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image

Richard Henderson (17):

decodetree: Propagate return value from translate subroutines

target/arm: Add ARM_FEATURE_V8_RDM

target/arm: Refactor disas_simd_indexed decode

target/arm: Refactor disas_simd_indexed size checks

target/arm: Decode aa64 armv8.1 scalar three same extra

target/arm: Decode aa64 armv8.1 three same extra

target/arm: Decode aa64 armv8.1 scalar/vector x indexed element

target/arm: Decode aa32 armv8.1 three same

target/arm: Decode aa32 armv8.1 two reg and a scalar

target/arm: Enable ARM_FEATURE_V8_RDM

target/arm: Add ARM_FEATURE_V8_FCMA

target/arm: Decode aa64 armv8.3 fcadd

target/arm: Decode aa64 armv8.3 fcmla

target/arm: Decode aa32 armv8.3 3-same

target/arm: Decode aa32 armv8.3 2-reg-index

target/arm: Decode t32 simd 3reg and 2reg_scalar extension

target/arm: Enable ARM_FEATURE_V8_FCMA

hw/arm/Makefile.objs | 2 +

hw/core/Makefile.objs | 1 +

hw/misc/Makefile.objs | 4 +

hw/timer/Makefile.objs | 1 +

target/arm/Makefile.objs | 2 +-

include/hw/arm/armv7m.h | 5 +

include/hw/arm/iotkit.h | 109 ++++++

include/hw/arm/xlnx-zynqmp.h | 2 +

include/hw/core/split-irq.h | 57 +++

include/hw/irq.h | 4 +-

include/hw/loader.h | 12 +-

include/hw/misc/iotkit-secctl.h | 103 ++++++

include/hw/misc/mps2-fpgaio.h | 43 +++

include/hw/misc/tz-ppc.h | 101 ++++++

include/hw/misc/unimp.h | 10 +

include/hw/or-irq.h | 5 +

include/hw/qdev-core.h | 30 +-

include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++

target/arm/cpu.h | 8 +

target/arm/helper.h | 31 ++

target/arm/idau.h | 61 ++++

hw/arm/armv7m.c | 35 +-

hw/arm/boot.c | 119 ++++---

hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++

hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++

hw/arm/xlnx-zynqmp.c | 14 +

hw/core/loader.c | 8 +-

hw/core/qdev.c | 8 +-

hw/core/split-irq.c | 89 +++++

hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++

hw/misc/mps2-fpgaio.c | 176 ++++++++++

hw/misc/tz-ppc.c | 302 ++++++++++++++++

hw/misc/unimp.c | 10 -

hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++

linux-user/elfload.c | 2 +

target/arm/cpu.c | 66 +++-

target/arm/cpu64.c | 2 +

target/arm/helper.c | 28 +-

target/arm/translate-a64.c | 514 +++++++++++++++++++++------

target/arm/translate.c | 275 +++++++++++++--

target/arm/vec_helper.c | 429 ++++++++++++++++++++++

default-configs/arm-softmmu.mak | 5 +

hw/misc/trace-events | 24 ++

hw/timer/trace-events | 3 +

scripts/decodetree.py | 5 +-

45 files changed, 4668 insertions(+), 200 deletions(-)

create mode 100644 include/hw/arm/iotkit.h

create mode 100644 include/hw/core/split-irq.h

create mode 100644 include/hw/misc/iotkit-secctl.h

create mode 100644 include/hw/misc/mps2-fpgaio.h

create mode 100644 include/hw/misc/tz-ppc.h

create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h

create mode 100644 target/arm/idau.h

create mode 100644 hw/arm/iotkit.c

create mode 100644 hw/arm/mps2-tz.c

create mode 100644 hw/core/split-irq.c

create mode 100644 hw/misc/iotkit-secctl.c

create mode 100644 hw/misc/mps2-fpgaio.c

create mode 100644 hw/misc/tz-ppc.c

create mode 100644 hw/timer/xlnx-zynqmp-rtc.c

create mode 100644 target/arm/vec_helper.c

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180228193125.20577-5-richard.henderson@linaro.org

target/arm/Makefile.objs | 2 +-

target/arm/helper.h | 4 ++

target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++

target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++

4 files changed, 198 insertions(+), 1 deletion(-)

create mode 100644 target/arm/vec_helper.c

diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs

--- a/target/arm/Makefile.objs

+++ b/target/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o

obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o

obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o

obj-y += translate.o op_helper.o helper.o cpu.o

-obj-y += neon_helper.o iwmmxt_helper.o

+obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o

obj-y += gdbstub.o

obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o

obj-y += crypto_helper.o

diff --git a/target/arm/helper.h b/target/arm/helper.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)

DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)

DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)

+DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32)

+DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32)

DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32)

DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32)

+DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32)

+DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32)

DEF_HELPER_1(neon_narrow_u8, i32, i64)

DEF_HELPER_1(neon_narrow_u16, i32, i64)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,

tcg_temp_free_ptr(fpst);

}

+/* AdvSIMD scalar three same extra

+ * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0

+ * +-----+---+-----------+------+---+------+---+--------+---+----+----+

+ * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |

+ * +-----+---+-----------+------+---+------+---+--------+---+----+----+

+ */

+static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,

+ uint32_t insn)

+{

+ int rd = extract32(insn, 0, 5);

+ int rn = extract32(insn, 5, 5);

+ int opcode = extract32(insn, 11, 4);

+ int rm = extract32(insn, 16, 5);

+ int size = extract32(insn, 22, 2);

+ bool u = extract32(insn, 29, 1);

+ TCGv_i32 ele1, ele2, ele3;

+ TCGv_i64 res;

+ int feature;

+

+ switch (u * 16 + opcode) {

+ case 0x10: /* SQRDMLAH (vector) */

+ case 0x11: /* SQRDMLSH (vector) */

+ if (size != 1 && size != 2) {

+ unallocated_encoding(s);

+ return;

+ }

+ feature = ARM_FEATURE_V8_RDM;

+ break;

+ default:

+ unallocated_encoding(s);

+ return;

+ }

+ if (!arm_dc_feature(s, feature)) {

+ unallocated_encoding(s);

+ return;

+ }

+ if (!fp_access_check(s)) {

+ return;

+ }

+

+ /* Do a single operation on the lowest element in the vector.

+ * We use the standard Neon helpers and rely on 0 OP 0 == 0

+ * with no side effects for all these operations.

+ * OPTME: special-purpose helpers would avoid doing some

+ * unnecessary work in the helper for the 16 bit cases.

+ */

+ ele1 = tcg_temp_new_i32();

+ ele2 = tcg_temp_new_i32();

+ ele3 = tcg_temp_new_i32();

+

+ read_vec_element_i32(s, ele1, rn, 0, size);

+ read_vec_element_i32(s, ele2, rm, 0, size);

+ read_vec_element_i32(s, ele3, rd, 0, size);

+

+ switch (opcode) {

+ case 0x0: /* SQRDMLAH */

+ if (size == 1) {

+ gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3);

+ } else {

+ gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3);

+ }

+ break;

+ case 0x1: /* SQRDMLSH */

+ if (size == 1) {

+ gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3);

+ } else {

+ gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3);

+ }

+ break;

+ default:

+ g_assert_not_reached();

+ }

+ tcg_temp_free_i32(ele1);

+ tcg_temp_free_i32(ele2);

+

+ res = tcg_temp_new_i64();

+ tcg_gen_extu_i32_i64(res, ele3);

+ tcg_temp_free_i32(ele3);

+

+ write_fp_dreg(s, rd, res);

+ tcg_temp_free_i64(res);

+}

+

static void handle_2misc_64(DisasContext *s, int opcode, bool u,

TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,

TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)

@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {

{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },

{ 0x2e000000, 0xbf208400, disas_simd_ext },

{ 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },

+ { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra },

{ 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },

{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },

{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },

diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c

+++ b/target/arm/vec_helper.c

+/*

+ * ARM AdvSIMD / SVE Vector Operations

+ *

+ * Copyright (c) 2018 Linaro

+ *

+ * This library is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU Lesser General Public

+ * License as published by the Free Software Foundation; either

+ * version 2 of the License, or (at your option) any later version.

+ *

+ * This library is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

+ * Lesser General Public License for more details.

+ *

+ * You should have received a copy of the GNU Lesser General Public

+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.

+ */

+#include "qemu/osdep.h"

+#include "cpu.h"

+#include "exec/exec-all.h"

+#include "exec/helper-proto.h"

+#include "tcg/tcg-gvec-desc.h"

+#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q

+/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */

+static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,

+ int16_t src2, int16_t src3)

+{

+ /* Simplify:

+ * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16

+ * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15

+ */

+ int32_t ret = (int32_t)src1 * src2;

+ ret = ((int32_t)src3 << 15) + ret + (1 << 14);

+ ret >>= 15;

+ if (ret != (int16_t)ret) {

+ SET_QC();

+ ret = (ret < 0 ? -0x8000 : 0x7fff);

+ }

+ return ret;

+}

+

+uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,

+ uint32_t src2, uint32_t src3)

+{

+ uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);

+ uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);

+ return deposit32(e1, 16, 16, e2);

+}

+

+/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */

+static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,

+ int16_t src2, int16_t src3)

+{

+ /* Similarly, using subtraction:

+ * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16

+ * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15

+ */

+ int32_t ret = (int32_t)src1 * src2;

+ ret = ((int32_t)src3 << 15) - ret + (1 << 14);

+ ret >>= 15;

+ if (ret != (int16_t)ret) {

+ SET_QC();

+ ret = (ret < 0 ? -0x8000 : 0x7fff);

+ }

+ return ret;

+}

+

+uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,

+ uint32_t src2, uint32_t src3)

+{

+ uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);

+ uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);

+ return deposit32(e1, 16, 16, e2);

+}

+

+/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */

+uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,

+ int32_t src2, int32_t src3)

+{

+ /* Simplify similarly to int_qrdmlah_s16 above. */

+ int64_t ret = (int64_t)src1 * src2;

+ ret = ((int64_t)src3 << 31) + ret + (1 << 30);

+ ret >>= 31;

+ if (ret != (int32_t)ret) {

+ SET_QC();

+ ret = (ret < 0 ? INT32_MIN : INT32_MAX);

+ }

+ return ret;

+}

+

+/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */

+uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,

+ int32_t src2, int32_t src3)

+{

+ /* Simplify similarly to int_qrdmlsh_s16 above. */

+ int64_t ret = (int64_t)src1 * src2;

+ ret = ((int64_t)src3 << 31) - ret + (1 << 30);

+ ret >>= 31;

+ if (ret != (int32_t)ret) {

+ SET_QC();

+ ret = (ret < 0 ? INT32_MIN : INT32_MAX);

+ }

+ return ret;

+}

2.16.2

Create an "init-svtor" property on the armv7m container

object which we can forward to the CPU object.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180220180325.29818-8-peter.maydell@linaro.org

include/hw/arm/armv7m.h | 2 ++

hw/arm/armv7m.c | 9 +++++++++

2 files changed, 11 insertions(+)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h

--- a/include/hw/arm/armv7m.h

+++ b/include/hw/arm/armv7m.h

@@ -XXX,XX +XXX,XX @@ typedef struct {

* that CPU accesses see. (The NVIC, bitbanding and other CPU-internal

* devices will be automatically layered on top of this view.)

* + Property "idau": IDAU interface (forwarded to CPU object)

+ * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)

*/

typedef struct ARMv7MState {

/*< private >*/

@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {

/* MemoryRegion the board provides to us (with its devices, RAM, etc) */

MemoryRegion *board_memory;

Object *idau;

+ uint32_t init_svtor;

} ARMv7MState;

#endif

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/armv7m.c

+++ b/hw/arm/armv7m.c

@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)

return;

}

}

+ if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {

+ object_property_set_uint(OBJECT(s->cpu), s->init_svtor,

+ "init-svtor", &err);

+ if (err != NULL) {

+ error_propagate(errp, err);

+ return;

+ }

+ }

object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);

if (err != NULL) {

error_propagate(errp, err);

@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {

DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,

MemoryRegion *),

DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),

+ DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),

DEFINE_PROP_END_OF_LIST(),

};

2.16.2

Define a new board model for the MPS2 with an AN505 FPGA image

containing a Cortex-M33. Since the FPGA images for TrustZone

cores (AN505, and the similar AN519 for Cortex-M23) have a

significantly different layout of devices to the non-TrustZone

images, we use a new source file rather than shoehorning them

into the existing mps2.c.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180220180325.29818-20-peter.maydell@linaro.org

hw/arm/Makefile.objs | 1 +

hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 504 insertions(+)

create mode 100644 hw/arm/mps2-tz.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

obj-$(CONFIG_MPS2) += mps2.o

+obj-$(CONFIG_MPS2) += mps2-tz.o

obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

obj-$(CONFIG_IOTKIT) += iotkit.o

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * ARM V2M MPS2 board emulation, trustzone aware FPGA images

+ *

+ * Copyright (c) 2017 Linaro Limited

+ * Written by Peter Maydell

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+ */

+/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger

+ * FPGA but is otherwise the same as the 2). Since the CPU itself

+ * and most of the devices are in the FPGA, the details of the board

+ * as seen by the guest depend significantly on the FPGA image.

+ * This source file covers the following FPGA images, for TrustZone cores:

+ * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505

+ *

+ * Links to the TRM for the board itself and to the various Application

+ * Notes which document the FPGA images can be found here:

+ * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2

+ *

+ * Board TRM:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf

+ * Application Note AN505:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html

+ *

+ * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide

+ * (ARM ECM0601256) for the details of some of the device layout:

+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu/error-report.h"

+#include "hw/arm/arm.h"

+#include "hw/arm/armv7m.h"

+#include "hw/or-irq.h"

+#include "hw/boards.h"

+#include "exec/address-spaces.h"

+#include "sysemu/sysemu.h"

+#include "hw/misc/unimp.h"

+#include "hw/char/cmsdk-apb-uart.h"

+#include "hw/timer/cmsdk-apb-timer.h"

+#include "hw/misc/mps2-scc.h"

+#include "hw/misc/mps2-fpgaio.h"

+#include "hw/arm/iotkit.h"

+#include "hw/devices.h"

+#include "net/net.h"

+#include "hw/core/split-irq.h"

+

+typedef enum MPS2TZFPGAType {

+ FPGA_AN505,

+} MPS2TZFPGAType;

+

+typedef struct {

+ MachineClass parent;

+ MPS2TZFPGAType fpga_type;

+ uint32_t scc_id;

+} MPS2TZMachineClass;

+

+typedef struct {

+ MachineState parent;

+

+ IoTKit iotkit;

+ MemoryRegion psram;

+ MemoryRegion ssram1;

+ MemoryRegion ssram1_m;

+ MemoryRegion ssram23;

+ MPS2SCC scc;

+ MPS2FPGAIO fpgaio;

+ TZPPC ppc[5];

+ UnimplementedDeviceState ssram_mpc[3];

+ UnimplementedDeviceState spi[5];

+ UnimplementedDeviceState i2c[4];

+ UnimplementedDeviceState i2s_audio;

+ UnimplementedDeviceState gpio[5];

+ UnimplementedDeviceState dma[4];

+ UnimplementedDeviceState gfx;

+ CMSDKAPBUART uart[5];

+ SplitIRQ sec_resp_splitter;

+ qemu_or_irq uart_irq_orgate;

+} MPS2TZMachineState;

+

+#define TYPE_MPS2TZ_MACHINE "mps2tz"

+#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")

+

+#define MPS2TZ_MACHINE(obj) \

+ OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE)

+#define MPS2TZ_MACHINE_GET_CLASS(obj) \

+ OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE)

+#define MPS2TZ_MACHINE_CLASS(klass) \

+ OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE)

+

+/* Main SYSCLK frequency in Hz */

+#define SYSCLK_FRQ 20000000

+

+/* Initialize the auxiliary RAM region @mr and map it into

+ * the memory map at @base.

+ */

+static void make_ram(MemoryRegion *mr, const char *name,

+ hwaddr base, hwaddr size)

+{

+ memory_region_init_ram(mr, NULL, name, size, &error_fatal);

+ memory_region_add_subregion(get_system_memory(), base, mr);

+}

+

+/* Create an alias of an entire original MemoryRegion @orig

+ * located at @base in the memory map.

+ */

+static void make_ram_alias(MemoryRegion *mr, const char *name,

+ MemoryRegion *orig, hwaddr base)

+{

+ memory_region_init_alias(mr, NULL, name, orig, 0,

+ memory_region_size(orig));

+ memory_region_add_subregion(get_system_memory(), base, mr);

+}

+

+static void init_sysbus_child(Object *parent, const char *childname,

+ void *child, size_t childsize,

+ const char *childtype)

+{

+ object_initialize(child, childsize, childtype);

+ object_property_add_child(parent, childname, OBJECT(child), &error_abort);

+ qdev_set_parent_bus(DEVICE(child), sysbus_get_default());

+

+}

+

+/* Most of the devices in the AN505 FPGA image sit behind

+ * Peripheral Protection Controllers. These data structures

+ * define the layout of which devices sit behind which PPCs.

+ * The devfn for each port is a function which creates, configures

+ * and initializes the device, returning the MemoryRegion which

+ * needs to be plugged into the downstream end of the PPC port.

+ */

+typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size);

+

+typedef struct PPCPortInfo {

+ const char *name;

+ MakeDevFn *devfn;

+ void *opaque;

+ hwaddr addr;

+ hwaddr size;

+} PPCPortInfo;

+

+typedef struct PPCInfo {

+ const char *name;

+ PPCPortInfo ports[TZ_NUM_PORTS];

+} PPCInfo;

+

+static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,

+ void *opaque,

+ const char *name, hwaddr size)

+{

+ /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,

+ * and return a pointer to its MemoryRegion.

+ */

+ UnimplementedDeviceState *uds = opaque;

+

+ init_sysbus_child(OBJECT(mms), name, uds,

+ sizeof(UnimplementedDeviceState),

+ TYPE_UNIMPLEMENTED_DEVICE);

+ qdev_prop_set_string(DEVICE(uds), "name", name);

+ qdev_prop_set_uint64(DEVICE(uds), "size", size);

+ object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);

+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);

+}

+

+static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size)

+{

+ CMSDKAPBUART *uart = opaque;

+ int i = uart - &mms->uart[0];

+ Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;

+ int rxirqno = i * 2;

+ int txirqno = i * 2 + 1;

+ int combirqno = i + 10;

+ SysBusDevice *s;

+ DeviceState *iotkitdev = DEVICE(&mms->iotkit);

+ DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);

+

+ init_sysbus_child(OBJECT(mms), name, uart,

+ sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);

+ qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr);

+ qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);

+ object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);

+ s = SYS_BUS_DEVICE(uart);

+ sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,

+ "EXP_IRQ", txirqno));

+ sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,

+ "EXP_IRQ", rxirqno));

+ sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));

+ sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));

+ sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev,

+ "EXP_IRQ", combirqno));

+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);

+}

+

+static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,

+ const char *name, hwaddr size)

+{

+ MPS2SCC *scc = opaque;

+ DeviceState *sccdev;

+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);

+

+ object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC);

+ sccdev = DEVICE(scc);

+ qdev_set_parent_bus(sccdev, sysbus_get_default());