1 | Second pull request of the week; mostly RTH's support for some | 1 | First arm pullreq of the 5.1 cycle; mostly bugfixes and some |
---|---|---|---|
2 | new-in-v8.1/v8.3 instructions, and my v8M board model. | 2 | cleanup patches. The new clock modelling framework is the big |
3 | thing here. | ||
3 | 4 | ||
4 | thanks | ||
5 | -- PMM | 5 | -- PMM |
6 | 6 | ||
7 | The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f: | 7 | The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062: |
8 | 8 | ||
9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000) | 9 | Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100) |
10 | 10 | ||
11 | are available in the Git repository at: | 11 | are available in the Git repository at: |
12 | 12 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430 |
14 | 14 | ||
15 | for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078: | 15 | for you to fetch changes up to 1267437e593e85498f9105b3bdab796630d2e83f: |
16 | 16 | ||
17 | target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000) | 17 | hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 11:52:29 +0100) |
18 | 18 | ||
19 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
20 | target-arm queue: | 20 | target-arm queue: |
21 | * implement FCMA and RDM v8.1 and v8.3 instructions | 21 | * xlnx-zdma: Fix endianness handling of descriptor loading |
22 | * enable Cortex-M33 v8M core, and provide new mps2-an505 board model | 22 | * nrf51: Fix last GPIO CNF address |
23 | that uses it | 23 | * gicv3: Use gicr_typer in arm_gicv3_icc_reset |
24 | * decodetree: Propagate return value from translate subroutines | 24 | * msf2: Add EMAC block to SmartFusion2 SoC |
25 | * xlnx-zynqmp: Implement the RTC device | 25 | * New clock modelling framework |
26 | * hw/arm: versal: Setup the ADMA with 128bit bus-width | ||
27 | * Cadence: gem: fix wraparound in 64bit descriptors | ||
28 | * cadence_gem: clear RX control descriptor | ||
29 | * target/arm: Vectorize integer comparison vs zero | ||
30 | * hw/arm/virt: dt: add kaslr-seed property | ||
31 | * hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes | ||
26 | 32 | ||
27 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
28 | Alistair Francis (3): | 34 | Cameron Esfahani (1): |
29 | xlnx-zynqmp-rtc: Initial commit | 35 | nrf51: Fix last GPIO CNF address |
30 | xlnx-zynqmp-rtc: Add basic time support | ||
31 | xlnx-zynqmp: Connect the RTC device | ||
32 | 36 | ||
33 | Peter Maydell (19): | 37 | Damien Hedde (7): |
34 | loader: Add new load_ramdisk_as() | 38 | hw/core/clock-vmstate: define a vmstate entry for clock state |
35 | hw/arm/boot: Honour CPU's address space for image loads | 39 | qdev: add clock input&output support to devices. |
36 | hw/arm/armv7m: Honour CPU's address space for image loads | 40 | qdev-clock: introduce an init array to ease the device construction |
37 | target/arm: Define an IDAU interface | 41 | hw/misc/zynq_slcr: add clock generation for uarts |
38 | armv7m: Forward idau property to CPU object | 42 | hw/char/cadence_uart: add clock support |
39 | target/arm: Define init-svtor property for the reset secure VTOR value | 43 | hw/arm/xilinx_zynq: connect uart clocks to slcr |
40 | armv7m: Forward init-svtor property to CPU object | 44 | qdev-monitor: print the device's clock with info qtree |
41 | target/arm: Add Cortex-M33 | ||
42 | hw/misc/unimp: Move struct to header file | ||
43 | include/hw/or-irq.h: Add missing include guard | ||
44 | qdev: Add new qdev_init_gpio_in_named_with_opaque() | ||
45 | hw/core/split-irq: Device that splits IRQ lines | ||
46 | hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505 | ||
47 | hw/misc/tz-ppc: Model TrustZone peripheral protection controller | ||
48 | hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton | ||
49 | hw/misc/iotkit-secctl: Add handling for PPCs | ||
50 | hw/misc/iotkit-secctl: Add remaining simple registers | ||
51 | hw/arm/iotkit: Model Arm IOT Kit | ||
52 | mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image | ||
53 | 45 | ||
54 | Richard Henderson (17): | 46 | Edgar E. Iglesias (7): |
55 | decodetree: Propagate return value from translate subroutines | 47 | dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness |
56 | target/arm: Add ARM_FEATURE_V8_RDM | 48 | dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness |
57 | target/arm: Refactor disas_simd_indexed decode | 49 | hw/arm: versal: Setup the ADMA with 128bit bus-width |
58 | target/arm: Refactor disas_simd_indexed size checks | 50 | device_tree: Allow name wildcards in qemu_fdt_node_path() |
59 | target/arm: Decode aa64 armv8.1 scalar three same extra | 51 | device_tree: Constify compat in qemu_fdt_node_path() |
60 | target/arm: Decode aa64 armv8.1 three same extra | 52 | hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102 |
61 | target/arm: Decode aa64 armv8.1 scalar/vector x indexed element | 53 | hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes |
62 | target/arm: Decode aa32 armv8.1 three same | ||
63 | target/arm: Decode aa32 armv8.1 two reg and a scalar | ||
64 | target/arm: Enable ARM_FEATURE_V8_RDM | ||
65 | target/arm: Add ARM_FEATURE_V8_FCMA | ||
66 | target/arm: Decode aa64 armv8.3 fcadd | ||
67 | target/arm: Decode aa64 armv8.3 fcmla | ||
68 | target/arm: Decode aa32 armv8.3 3-same | ||
69 | target/arm: Decode aa32 armv8.3 2-reg-index | ||
70 | target/arm: Decode t32 simd 3reg and 2reg_scalar extension | ||
71 | target/arm: Enable ARM_FEATURE_V8_FCMA | ||
72 | 54 | ||
73 | hw/arm/Makefile.objs | 2 + | 55 | Jerome Forissier (2): |
74 | hw/core/Makefile.objs | 1 + | 56 | hw/arm/virt: dt: move creation of /secure-chosen to create_fdt() |
75 | hw/misc/Makefile.objs | 4 + | 57 | hw/arm/virt: dt: add kaslr-seed property |
76 | hw/timer/Makefile.objs | 1 + | ||
77 | target/arm/Makefile.objs | 2 +- | ||
78 | include/hw/arm/armv7m.h | 5 + | ||
79 | include/hw/arm/iotkit.h | 109 ++++++ | ||
80 | include/hw/arm/xlnx-zynqmp.h | 2 + | ||
81 | include/hw/core/split-irq.h | 57 +++ | ||
82 | include/hw/irq.h | 4 +- | ||
83 | include/hw/loader.h | 12 +- | ||
84 | include/hw/misc/iotkit-secctl.h | 103 ++++++ | ||
85 | include/hw/misc/mps2-fpgaio.h | 43 +++ | ||
86 | include/hw/misc/tz-ppc.h | 101 ++++++ | ||
87 | include/hw/misc/unimp.h | 10 + | ||
88 | include/hw/or-irq.h | 5 + | ||
89 | include/hw/qdev-core.h | 30 +- | ||
90 | include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++ | ||
91 | target/arm/cpu.h | 8 + | ||
92 | target/arm/helper.h | 31 ++ | ||
93 | target/arm/idau.h | 61 ++++ | ||
94 | hw/arm/armv7m.c | 35 +- | ||
95 | hw/arm/boot.c | 119 ++++--- | ||
96 | hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++ | ||
97 | hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++ | ||
98 | hw/arm/xlnx-zynqmp.c | 14 + | ||
99 | hw/core/loader.c | 8 +- | ||
100 | hw/core/qdev.c | 8 +- | ||
101 | hw/core/split-irq.c | 89 +++++ | ||
102 | hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++ | ||
103 | hw/misc/mps2-fpgaio.c | 176 ++++++++++ | ||
104 | hw/misc/tz-ppc.c | 302 ++++++++++++++++ | ||
105 | hw/misc/unimp.c | 10 - | ||
106 | hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++ | ||
107 | linux-user/elfload.c | 2 + | ||
108 | target/arm/cpu.c | 66 +++- | ||
109 | target/arm/cpu64.c | 2 + | ||
110 | target/arm/helper.c | 28 +- | ||
111 | target/arm/translate-a64.c | 514 +++++++++++++++++++++------ | ||
112 | target/arm/translate.c | 275 +++++++++++++-- | ||
113 | target/arm/vec_helper.c | 429 ++++++++++++++++++++++ | ||
114 | default-configs/arm-softmmu.mak | 5 + | ||
115 | hw/misc/trace-events | 24 ++ | ||
116 | hw/timer/trace-events | 3 + | ||
117 | scripts/decodetree.py | 5 +- | ||
118 | 45 files changed, 4668 insertions(+), 200 deletions(-) | ||
119 | create mode 100644 include/hw/arm/iotkit.h | ||
120 | create mode 100644 include/hw/core/split-irq.h | ||
121 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
122 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
123 | create mode 100644 include/hw/misc/tz-ppc.h | ||
124 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
125 | create mode 100644 target/arm/idau.h | ||
126 | create mode 100644 hw/arm/iotkit.c | ||
127 | create mode 100644 hw/arm/mps2-tz.c | ||
128 | create mode 100644 hw/core/split-irq.c | ||
129 | create mode 100644 hw/misc/iotkit-secctl.c | ||
130 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
131 | create mode 100644 hw/misc/tz-ppc.c | ||
132 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
133 | create mode 100644 target/arm/vec_helper.c | ||
134 | 58 | ||
59 | Keqian Zhu (2): | ||
60 | bugfix: Use gicr_typer in arm_gicv3_icc_reset | ||
61 | Typo: Correct the name of CPU hotplug memory region | ||
62 | |||
63 | Peter Maydell (2): | ||
64 | hw/core/clock: introduce clock object | ||
65 | docs/clocks: add device's clock documentation | ||
66 | |||
67 | Philippe Mathieu-Daudé (3): | ||
68 | target/arm: Restrict the Address Translate write operation to TCG accel | ||
69 | target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] | ||
70 | target/arm/cpu: Update coding style to make checkpatch.pl happy | ||
71 | |||
72 | Ramon Fried (2): | ||
73 | Cadence: gem: fix wraparound in 64bit descriptors | ||
74 | net: cadence_gem: clear RX control descriptor | ||
75 | |||
76 | Richard Henderson (1): | ||
77 | target/arm: Vectorize integer comparison vs zero | ||
78 | |||
79 | Subbaraya Sundeep (3): | ||
80 | hw/net: Add Smartfusion2 emac block | ||
81 | msf2: Add EMAC block to SmartFusion2 SoC | ||
82 | tests/boot_linux_console: Add ethernet test to SmartFusion2 | ||
83 | |||
84 | Thomas Huth (1): | ||
85 | target/arm: Make cpu_register() available for other files | ||
86 | |||
87 | hw/core/Makefile.objs | 2 + | ||
88 | hw/net/Makefile.objs | 1 + | ||
89 | tests/Makefile.include | 1 + | ||
90 | include/hw/arm/msf2-soc.h | 2 + | ||
91 | include/hw/char/cadence_uart.h | 1 + | ||
92 | include/hw/clock.h | 225 +++++++++++++ | ||
93 | include/hw/gpio/nrf51_gpio.h | 2 +- | ||
94 | include/hw/net/msf2-emac.h | 53 +++ | ||
95 | include/hw/qdev-clock.h | 159 +++++++++ | ||
96 | include/hw/qdev-core.h | 12 + | ||
97 | include/sysemu/device_tree.h | 5 +- | ||
98 | target/arm/cpu-qom.h | 9 +- | ||
99 | target/arm/helper.h | 27 +- | ||
100 | target/arm/translate.h | 5 + | ||
101 | device_tree.c | 4 +- | ||
102 | hw/acpi/cpu.c | 2 +- | ||
103 | hw/arm/msf2-soc.c | 26 +- | ||
104 | hw/arm/virt.c | 20 +- | ||
105 | hw/arm/xilinx_zynq.c | 57 +++- | ||
106 | hw/arm/xlnx-versal.c | 2 + | ||
107 | hw/arm/xlnx-zcu102.c | 39 ++- | ||
108 | hw/char/cadence_uart.c | 73 +++- | ||
109 | hw/core/clock-vmstate.c | 25 ++ | ||
110 | hw/core/clock.c | 130 ++++++++ | ||
111 | hw/core/qdev-clock.c | 185 +++++++++++ | ||
112 | hw/core/qdev.c | 12 + | ||
113 | hw/dma/xlnx-zdma.c | 25 +- | ||
114 | hw/intc/arm_gicv3_kvm.c | 4 +- | ||
115 | hw/misc/zynq_slcr.c | 172 +++++++++- | ||
116 | hw/net/cadence_gem.c | 16 +- | ||
117 | hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++ | ||
118 | qdev-monitor.c | 9 + | ||
119 | target/arm/cpu.c | 25 +- | ||
120 | target/arm/cpu64.c | 16 +- | ||
121 | target/arm/helper.c | 17 + | ||
122 | target/arm/neon_helper.c | 24 -- | ||
123 | target/arm/translate-a64.c | 64 +--- | ||
124 | target/arm/translate.c | 256 ++++++++++++-- | ||
125 | target/arm/vec_helper.c | 25 ++ | ||
126 | MAINTAINERS | 2 + | ||
127 | docs/devel/clocks.rst | 391 ++++++++++++++++++++++ | ||
128 | docs/devel/index.rst | 1 + | ||
129 | hw/char/trace-events | 3 + | ||
130 | hw/core/trace-events | 7 + | ||
131 | tests/acceptance/boot_linux_console.py | 15 +- | ||
132 | 45 files changed, 2538 insertions(+), 202 deletions(-) | ||
133 | create mode 100644 include/hw/clock.h | ||
134 | create mode 100644 include/hw/net/msf2-emac.h | ||
135 | create mode 100644 include/hw/qdev-clock.h | ||
136 | create mode 100644 hw/core/clock-vmstate.c | ||
137 | create mode 100644 hw/core/clock.c | ||
138 | create mode 100644 hw/core/qdev-clock.c | ||
139 | create mode 100644 hw/net/msf2-emac.c | ||
140 | create mode 100644 docs/devel/clocks.rst | ||
141 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | The integer size check was already outside of the opcode switch; | 3 | Fix descriptor loading from memory wrt host endianness. |
4 | move the floating-point size check outside as well. Unify the | ||
5 | size vs index adjustment between fp and integer paths. | ||
6 | 4 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
9 | Message-id: 20180228193125.20577-4-richard.henderson@linaro.org | 7 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20200404122718.25111-2-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | target/arm/translate-a64.c | 65 +++++++++++++++++++++++----------------------- | 12 | hw/dma/xlnx-zdma.c | 11 +++++++---- |
13 | 1 file changed, 32 insertions(+), 33 deletions(-) | 13 | 1 file changed, 7 insertions(+), 4 deletions(-) |
14 | 14 | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 15 | diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 17 | --- a/hw/dma/xlnx-zdma.c |
18 | +++ b/target/arm/translate-a64.c | 18 | +++ b/hw/dma/xlnx-zdma.c |
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr) |
20 | case 0x05: /* FMLS */ | 20 | s->regs[basereg + 1] = addr >> 32; |
21 | case 0x09: /* FMUL */ | 21 | } |
22 | case 0x19: /* FMULX */ | 22 | |
23 | - if (size == 1) { | 23 | -static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf) |
24 | - unallocated_encoding(s); | 24 | +static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, |
25 | - return; | 25 | + XlnxZDMADescr *descr) |
26 | - } | 26 | { |
27 | is_fp = true; | 27 | /* ZDMA descriptors must be aligned to their own size. */ |
28 | break; | 28 | if (addr % sizeof(XlnxZDMADescr)) { |
29 | default: | 29 | qemu_log_mask(LOG_GUEST_ERROR, |
30 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 30 | "zdma: unaligned descriptor at %" PRIx64, |
31 | if (is_fp) { | 31 | addr); |
32 | /* convert insn encoded size to TCGMemOp size */ | 32 | - memset(buf, 0x0, sizeof(XlnxZDMADescr)); |
33 | switch (size) { | 33 | + memset(descr, 0x0, sizeof(XlnxZDMADescr)); |
34 | - case 2: /* single precision */ | 34 | s->error = true; |
35 | - size = MO_32; | 35 | return false; |
36 | - index = h << 1 | l; | ||
37 | - rm |= (m << 4); | ||
38 | - break; | ||
39 | - case 3: /* double precision */ | ||
40 | - size = MO_64; | ||
41 | - if (l || !is_q) { | ||
42 | + case 0: /* half-precision */ | ||
43 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | - index = h; | ||
48 | - rm |= (m << 4); | ||
49 | - break; | ||
50 | - case 0: /* half precision */ | ||
51 | size = MO_16; | ||
52 | - index = h << 2 | l << 1 | m; | ||
53 | - is_fp16 = true; | ||
54 | - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
55 | - break; | ||
56 | - } | ||
57 | - /* fallthru */ | ||
58 | - default: /* unallocated */ | ||
59 | - unallocated_encoding(s); | ||
60 | - return; | ||
61 | - } | ||
62 | - } else { | ||
63 | - switch (size) { | ||
64 | - case 1: | ||
65 | - index = h << 2 | l << 1 | m; | ||
66 | break; | ||
67 | - case 2: | ||
68 | - index = h << 1 | l; | ||
69 | - rm |= (m << 4); | ||
70 | + case MO_32: /* single precision */ | ||
71 | + case MO_64: /* double precision */ | ||
72 | break; | ||
73 | default: | ||
74 | unallocated_encoding(s); | ||
75 | return; | ||
76 | } | ||
77 | + } else { | ||
78 | + switch (size) { | ||
79 | + case MO_8: | ||
80 | + case MO_64: | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + } | ||
85 | + | ||
86 | + /* Given TCGMemOp size, adjust register and indexing. */ | ||
87 | + switch (size) { | ||
88 | + case MO_16: | ||
89 | + index = h << 2 | l << 1 | m; | ||
90 | + break; | ||
91 | + case MO_32: | ||
92 | + index = h << 1 | l; | ||
93 | + rm |= m << 4; | ||
94 | + break; | ||
95 | + case MO_64: | ||
96 | + if (l || !is_q) { | ||
97 | + unallocated_encoding(s); | ||
98 | + return; | ||
99 | + } | ||
100 | + index = h; | ||
101 | + rm |= m << 4; | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | } | 36 | } |
106 | 37 | ||
107 | if (!fp_access_check(s)) { | 38 | - address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr)); |
39 | + descr->addr = address_space_ldq_le(s->dma_as, addr, s->attr, NULL); | ||
40 | + descr->size = address_space_ldl_le(s->dma_as, addr + 8, s->attr, NULL); | ||
41 | + descr->attr = address_space_ldl_le(s->dma_as, addr + 12, s->attr, NULL); | ||
42 | return true; | ||
43 | } | ||
44 | |||
45 | @@ -XXX,XX +XXX,XX @@ static void zdma_update_descr_addr(XlnxZDMA *s, bool type, | ||
46 | } else { | ||
47 | addr = zdma_get_regaddr64(s, basereg); | ||
48 | addr += sizeof(s->dsc_dst); | ||
49 | - address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8); | ||
50 | + next = address_space_ldq_le(s->dma_as, addr, s->attr, NULL); | ||
51 | } | ||
52 | |||
53 | zdma_put_regaddr64(s, basereg, next); | ||
108 | -- | 54 | -- |
109 | 2.16.2 | 55 | 2.20.1 |
110 | 56 | ||
111 | 57 | diff view generated by jsdifflib |
1 | Instead of loading kernels, device trees, and the like to | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | the system address space, use the CPU's address space. This | ||
3 | is important if we're trying to load the file to memory or | ||
4 | via an alias memory region that is provided by an SoC | ||
5 | object and thus not mapped into the system address space. | ||
6 | 2 | ||
3 | Fix descriptor loading from registers wrt host endianness. | ||
4 | |||
5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
7 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
8 | Message-id: 20200404122718.25111-3-edgar.iglesias@gmail.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-3-peter.maydell@linaro.org | ||
11 | --- | 10 | --- |
12 | hw/arm/boot.c | 119 +++++++++++++++++++++++++++++++++++++--------------------- | 11 | hw/dma/xlnx-zdma.c | 14 ++++++++++---- |
13 | 1 file changed, 76 insertions(+), 43 deletions(-) | 12 | 1 file changed, 10 insertions(+), 4 deletions(-) |
14 | 13 | ||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 14 | diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/boot.c | 16 | --- a/hw/dma/xlnx-zdma.c |
18 | +++ b/hw/arm/boot.c | 17 | +++ b/hw/dma/xlnx-zdma.c |
19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr) |
20 | #define ARM64_TEXT_OFFSET_OFFSET 8 | 19 | s->regs[basereg + 1] = addr >> 32; |
21 | #define ARM64_MAGIC_OFFSET 56 | 20 | } |
22 | 21 | ||
23 | +static AddressSpace *arm_boot_address_space(ARMCPU *cpu, | 22 | +static void zdma_load_descriptor_reg(XlnxZDMA *s, unsigned int reg, |
24 | + const struct arm_boot_info *info) | 23 | + XlnxZDMADescr *descr) |
25 | +{ | 24 | +{ |
26 | + /* Return the address space to use for bootloader reads and writes. | 25 | + descr->addr = zdma_get_regaddr64(s, reg); |
27 | + * We prefer the secure address space if the CPU has it and we're | 26 | + descr->size = s->regs[reg + 2]; |
28 | + * going to boot the guest into it. | 27 | + descr->attr = s->regs[reg + 3]; |
29 | + */ | ||
30 | + int asidx; | ||
31 | + CPUState *cs = CPU(cpu); | ||
32 | + | ||
33 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { | ||
34 | + asidx = ARMASIdx_S; | ||
35 | + } else { | ||
36 | + asidx = ARMASIdx_NS; | ||
37 | + } | ||
38 | + | ||
39 | + return cpu_get_address_space(cs, asidx); | ||
40 | +} | 28 | +} |
41 | + | 29 | + |
42 | typedef enum { | 30 | static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, |
43 | FIXUP_NONE = 0, /* do nothing */ | 31 | XlnxZDMADescr *descr) |
44 | FIXUP_TERMINATOR, /* end of insns */ | ||
45 | @@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup smpboot[] = { | ||
46 | }; | ||
47 | |||
48 | static void write_bootloader(const char *name, hwaddr addr, | ||
49 | - const ARMInsnFixup *insns, uint32_t *fixupcontext) | ||
50 | + const ARMInsnFixup *insns, uint32_t *fixupcontext, | ||
51 | + AddressSpace *as) | ||
52 | { | 32 | { |
53 | /* Fix up the specified bootloader fragment and write it into | 33 | @@ -XXX,XX +XXX,XX @@ static void zdma_load_src_descriptor(XlnxZDMA *s) |
54 | * guest memory using rom_add_blob_fixed(). fixupcontext is | 34 | unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); |
55 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr, | 35 | |
56 | code[i] = tswap32(insn); | 36 | if (ptype == PT_REG) { |
37 | - memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0], | ||
38 | - sizeof(s->dsc_src)); | ||
39 | + zdma_load_descriptor_reg(s, R_ZDMA_CH_SRC_DSCR_WORD0, &s->dsc_src); | ||
40 | return; | ||
57 | } | 41 | } |
58 | 42 | ||
59 | - rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); | 43 | @@ -XXX,XX +XXX,XX @@ static void zdma_load_dst_descriptor(XlnxZDMA *s) |
60 | + rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); | 44 | bool dst_type; |
61 | 45 | ||
62 | g_free(code); | 46 | if (ptype == PT_REG) { |
63 | } | 47 | - memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0], |
64 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | 48 | - sizeof(s->dsc_dst)); |
65 | const struct arm_boot_info *info) | 49 | + zdma_load_descriptor_reg(s, R_ZDMA_CH_DST_DSCR_WORD0, &s->dsc_dst); |
66 | { | 50 | return; |
67 | uint32_t fixupcontext[FIXUP_MAX]; | ||
68 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
69 | |||
70 | fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; | ||
71 | fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; | ||
72 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
73 | } | 51 | } |
74 | 52 | ||
75 | write_bootloader("smpboot", info->smp_loader_start, | ||
76 | - smpboot, fixupcontext); | ||
77 | + smpboot, fixupcontext, as); | ||
78 | } | ||
79 | |||
80 | void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
81 | const struct arm_boot_info *info, | ||
82 | hwaddr mvbar_addr) | ||
83 | { | ||
84 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
85 | int n; | ||
86 | uint32_t mvbar_blob[] = { | ||
87 | /* mvbar_addr: secure monitor vectors | ||
88 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
89 | for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { | ||
90 | mvbar_blob[n] = tswap32(mvbar_blob[n]); | ||
91 | } | ||
92 | - rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
93 | - mvbar_addr); | ||
94 | + rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
95 | + mvbar_addr, as); | ||
96 | |||
97 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | ||
98 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | ||
99 | } | ||
100 | - rom_add_blob_fixed("board-setup", board_setup_blob, | ||
101 | - sizeof(board_setup_blob), info->board_setup_addr); | ||
102 | + rom_add_blob_fixed_as("board-setup", board_setup_blob, | ||
103 | + sizeof(board_setup_blob), info->board_setup_addr, as); | ||
104 | } | ||
105 | |||
106 | static void default_reset_secondary(ARMCPU *cpu, | ||
107 | const struct arm_boot_info *info) | ||
108 | { | ||
109 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
110 | CPUState *cs = CPU(cpu); | ||
111 | |||
112 | - address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, | ||
113 | + address_space_stl_notdirty(as, info->smp_bootreg_addr, | ||
114 | 0, MEMTXATTRS_UNSPECIFIED, NULL); | ||
115 | cpu_set_pc(cs, info->smp_loader_start); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static inline bool have_dtb(const struct arm_boot_info *info) | ||
118 | } | ||
119 | |||
120 | #define WRITE_WORD(p, value) do { \ | ||
121 | - address_space_stl_notdirty(&address_space_memory, p, value, \ | ||
122 | + address_space_stl_notdirty(as, p, value, \ | ||
123 | MEMTXATTRS_UNSPECIFIED, NULL); \ | ||
124 | p += 4; \ | ||
125 | } while (0) | ||
126 | |||
127 | -static void set_kernel_args(const struct arm_boot_info *info) | ||
128 | +static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) | ||
129 | { | ||
130 | int initrd_size = info->initrd_size; | ||
131 | hwaddr base = info->loader_start; | ||
132 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
133 | int cmdline_size; | ||
134 | |||
135 | cmdline_size = strlen(info->kernel_cmdline); | ||
136 | - cpu_physical_memory_write(p + 8, info->kernel_cmdline, | ||
137 | - cmdline_size + 1); | ||
138 | + address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, | ||
139 | + (const uint8_t *)info->kernel_cmdline, | ||
140 | + cmdline_size + 1); | ||
141 | cmdline_size = (cmdline_size >> 2) + 1; | ||
142 | WRITE_WORD(p, cmdline_size + 2); | ||
143 | WRITE_WORD(p, 0x54410009); | ||
144 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
145 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; | ||
146 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | ||
147 | WRITE_WORD(p, 0x414f4d50); | ||
148 | - cpu_physical_memory_write(p, atag_board_buf, atag_board_len); | ||
149 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
150 | + atag_board_buf, atag_board_len); | ||
151 | p += atag_board_len; | ||
152 | } | ||
153 | /* ATAG_END */ | ||
154 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
155 | WRITE_WORD(p, 0); | ||
156 | } | ||
157 | |||
158 | -static void set_kernel_args_old(const struct arm_boot_info *info) | ||
159 | +static void set_kernel_args_old(const struct arm_boot_info *info, | ||
160 | + AddressSpace *as) | ||
161 | { | ||
162 | hwaddr p; | ||
163 | const char *s; | ||
164 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info) | ||
165 | } | ||
166 | s = info->kernel_cmdline; | ||
167 | if (s) { | ||
168 | - cpu_physical_memory_write(p, s, strlen(s) + 1); | ||
169 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
170 | + (const uint8_t *)s, strlen(s) + 1); | ||
171 | } else { | ||
172 | WRITE_WORD(p, 0); | ||
173 | } | ||
174 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
175 | * @addr: the address to load the image at | ||
176 | * @binfo: struct describing the boot environment | ||
177 | * @addr_limit: upper limit of the available memory area at @addr | ||
178 | + * @as: address space to load image to | ||
179 | * | ||
180 | * Load a device tree supplied by the machine or by the user with the | ||
181 | * '-dtb' command line option, and put it at offset @addr in target | ||
182 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
183 | * Note: Must not be called unless have_dtb(binfo) is true. | ||
184 | */ | ||
185 | static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
186 | - hwaddr addr_limit) | ||
187 | + hwaddr addr_limit, AddressSpace *as) | ||
188 | { | ||
189 | void *fdt = NULL; | ||
190 | int size, rc; | ||
191 | @@ -XXX,XX +XXX,XX @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
192 | /* Put the DTB into the memory map as a ROM image: this will ensure | ||
193 | * the DTB is copied again upon reset, even if addr points into RAM. | ||
194 | */ | ||
195 | - rom_add_blob_fixed("dtb", fdt, size, addr); | ||
196 | + rom_add_blob_fixed_as("dtb", fdt, size, addr, as); | ||
197 | |||
198 | g_free(fdt); | ||
199 | |||
200 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
201 | } | ||
202 | |||
203 | if (cs == first_cpu) { | ||
204 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
205 | + | ||
206 | cpu_set_pc(cs, info->loader_start); | ||
207 | |||
208 | if (!have_dtb(info)) { | ||
209 | if (old_param) { | ||
210 | - set_kernel_args_old(info); | ||
211 | + set_kernel_args_old(info, as); | ||
212 | } else { | ||
213 | - set_kernel_args(info); | ||
214 | + set_kernel_args(info, as); | ||
215 | } | ||
216 | } | ||
217 | } else { | ||
218 | @@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque) | ||
219 | |||
220 | static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
221 | uint64_t *lowaddr, uint64_t *highaddr, | ||
222 | - int elf_machine) | ||
223 | + int elf_machine, AddressSpace *as) | ||
224 | { | ||
225 | bool elf_is64; | ||
226 | union { | ||
227 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
228 | } | ||
229 | } | ||
230 | |||
231 | - ret = load_elf(info->kernel_filename, NULL, NULL, | ||
232 | - pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
233 | - 1, data_swab); | ||
234 | + ret = load_elf_as(info->kernel_filename, NULL, NULL, | ||
235 | + pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
236 | + 1, data_swab, as); | ||
237 | if (ret <= 0) { | ||
238 | /* The header loaded but the image didn't */ | ||
239 | exit(1); | ||
240 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
241 | } | ||
242 | |||
243 | static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
244 | - hwaddr *entry) | ||
245 | + hwaddr *entry, AddressSpace *as) | ||
246 | { | ||
247 | hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; | ||
248 | uint8_t *buffer; | ||
249 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
250 | } | ||
251 | |||
252 | *entry = mem_base + kernel_load_offset; | ||
253 | - rom_add_blob_fixed(filename, buffer, size, *entry); | ||
254 | + rom_add_blob_fixed_as(filename, buffer, size, *entry, as); | ||
255 | |||
256 | g_free(buffer); | ||
257 | |||
258 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
259 | ARMCPU *cpu = n->cpu; | ||
260 | struct arm_boot_info *info = | ||
261 | container_of(n, struct arm_boot_info, load_kernel_notifier); | ||
262 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
263 | |||
264 | /* The board code is not supposed to set secure_board_setup unless | ||
265 | * running its code in secure mode is actually possible, and KVM | ||
266 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
267 | * the kernel is supposed to be loaded by the bootloader), copy the | ||
268 | * DTB to the base of RAM for the bootloader to pick up. | ||
269 | */ | ||
270 | - if (load_dtb(info->loader_start, info, 0) < 0) { | ||
271 | + if (load_dtb(info->loader_start, info, 0, as) < 0) { | ||
272 | exit(1); | ||
273 | } | ||
274 | } | ||
275 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
276 | |||
277 | /* Assume that raw images are linux kernels, and ELF images are not. */ | ||
278 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | ||
279 | - &elf_high_addr, elf_machine); | ||
280 | + &elf_high_addr, elf_machine, as); | ||
281 | if (kernel_size > 0 && have_dtb(info)) { | ||
282 | /* If there is still some room left at the base of RAM, try and put | ||
283 | * the DTB there like we do for images loaded with -bios or -pflash. | ||
284 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
285 | if (elf_low_addr < info->loader_start) { | ||
286 | elf_low_addr = 0; | ||
287 | } | ||
288 | - if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { | ||
289 | + if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) { | ||
290 | exit(1); | ||
291 | } | ||
292 | } | ||
293 | } | ||
294 | entry = elf_entry; | ||
295 | if (kernel_size < 0) { | ||
296 | - kernel_size = load_uimage(info->kernel_filename, &entry, NULL, | ||
297 | - &is_linux, NULL, NULL); | ||
298 | + kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, | ||
299 | + &is_linux, NULL, NULL, as); | ||
300 | } | ||
301 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { | ||
302 | kernel_size = load_aarch64_image(info->kernel_filename, | ||
303 | - info->loader_start, &entry); | ||
304 | + info->loader_start, &entry, as); | ||
305 | is_linux = 1; | ||
306 | } else if (kernel_size < 0) { | ||
307 | /* 32-bit ARM */ | ||
308 | entry = info->loader_start + KERNEL_LOAD_ADDR; | ||
309 | - kernel_size = load_image_targphys(info->kernel_filename, entry, | ||
310 | - info->ram_size - KERNEL_LOAD_ADDR); | ||
311 | + kernel_size = load_image_targphys_as(info->kernel_filename, entry, | ||
312 | + info->ram_size - KERNEL_LOAD_ADDR, | ||
313 | + as); | ||
314 | is_linux = 1; | ||
315 | } | ||
316 | if (kernel_size < 0) { | ||
317 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
318 | uint32_t fixupcontext[FIXUP_MAX]; | ||
319 | |||
320 | if (info->initrd_filename) { | ||
321 | - initrd_size = load_ramdisk(info->initrd_filename, | ||
322 | - info->initrd_start, | ||
323 | - info->ram_size - | ||
324 | - info->initrd_start); | ||
325 | + initrd_size = load_ramdisk_as(info->initrd_filename, | ||
326 | + info->initrd_start, | ||
327 | + info->ram_size - info->initrd_start, | ||
328 | + as); | ||
329 | if (initrd_size < 0) { | ||
330 | - initrd_size = load_image_targphys(info->initrd_filename, | ||
331 | - info->initrd_start, | ||
332 | - info->ram_size - | ||
333 | - info->initrd_start); | ||
334 | + initrd_size = load_image_targphys_as(info->initrd_filename, | ||
335 | + info->initrd_start, | ||
336 | + info->ram_size - | ||
337 | + info->initrd_start, | ||
338 | + as); | ||
339 | } | ||
340 | if (initrd_size < 0) { | ||
341 | error_report("could not load initrd '%s'", | ||
342 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
343 | |||
344 | /* Place the DTB after the initrd in memory with alignment. */ | ||
345 | dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); | ||
346 | - if (load_dtb(dtb_start, info, 0) < 0) { | ||
347 | + if (load_dtb(dtb_start, info, 0, as) < 0) { | ||
348 | exit(1); | ||
349 | } | ||
350 | fixupcontext[FIXUP_ARGPTR] = dtb_start; | ||
351 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
352 | fixupcontext[FIXUP_ENTRYPOINT] = entry; | ||
353 | |||
354 | write_bootloader("bootloader", info->loader_start, | ||
355 | - primary_loader, fixupcontext); | ||
356 | + primary_loader, fixupcontext, as); | ||
357 | |||
358 | if (info->nb_cpus > 1) { | ||
359 | info->write_secondary_boot(cpu, info); | ||
360 | -- | 53 | -- |
361 | 2.16.2 | 54 | 2.20.1 |
362 | 55 | ||
363 | 56 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Cameron Esfahani <dirty@apple.com> |
---|---|---|---|
2 | 2 | ||
3 | Not enabled anywhere yet. | 3 | NRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the last |
4 | valid CNF register: it's referring to the last byte of the last valid | ||
5 | CNF register. | ||
4 | 6 | ||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | This hasn't been a problem up to now, as current implementation in |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | memory.c turns an unaligned 4-byte read from 0x77f to a single byte read |
7 | Message-id: 20180228193125.20577-11-richard.henderson@linaro.org | 9 | and the qtest only looks at the least-significant byte of the register. |
10 | |||
11 | But when running with patches which fix unaligned accesses in memory.c, | ||
12 | the qtest breaks. | ||
13 | |||
14 | Considering NRF51 doesn't support unaligned accesses, the simplest fix | ||
15 | is to actually set NRF51_GPIO_REG_CNF_END to the start of the last valid | ||
16 | CNF register: 0x77c. | ||
17 | |||
18 | Now, qtests work with or without the unaligned access patches. | ||
19 | |||
20 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
21 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
22 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
23 | Signed-off-by: Cameron Esfahani <dirty@apple.com> | ||
24 | Message-id: 51b427f06838622da783d38ba56e3630d6d85c60.1586925392.git.dirty@apple.com | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 27 | --- |
10 | target/arm/cpu.h | 1 + | 28 | include/hw/gpio/nrf51_gpio.h | 2 +- |
11 | linux-user/elfload.c | 1 + | 29 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 2 files changed, 2 insertions(+) | ||
13 | 30 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 31 | diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h |
15 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 33 | --- a/include/hw/gpio/nrf51_gpio.h |
17 | +++ b/target/arm/cpu.h | 34 | +++ b/include/hw/gpio/nrf51_gpio.h |
18 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 35 | @@ -XXX,XX +XXX,XX @@ |
19 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | 36 | #define NRF51_GPIO_REG_DIRSET 0x518 |
20 | ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | 37 | #define NRF51_GPIO_REG_DIRCLR 0x51C |
21 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | 38 | #define NRF51_GPIO_REG_CNF_START 0x700 |
22 | + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ | 39 | -#define NRF51_GPIO_REG_CNF_END 0x77F |
23 | }; | 40 | +#define NRF51_GPIO_REG_CNF_END 0x77C |
24 | 41 | ||
25 | static inline int arm_feature(CPUARMState *env, int feature) | 42 | #define NRF51_GPIO_PULLDOWN 1 |
26 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 43 | #define NRF51_GPIO_PULLUP 3 |
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/linux-user/elfload.c | ||
29 | +++ b/linux-user/elfload.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
31 | GET_FEATURE(ARM_FEATURE_V8_FP16, | ||
32 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | ||
33 | GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | ||
34 | + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); | ||
35 | #undef GET_FEATURE | ||
36 | |||
37 | return hwcaps; | ||
38 | -- | 44 | -- |
39 | 2.16.2 | 45 | 2.20.1 |
40 | 46 | ||
41 | 47 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Keqian Zhu <zhukeqian1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer, | ||
4 | of which high 32bit is constructed by mp_affinity. For most case, | ||
5 | the high 32bit of mp_affinity is zero, so it will always access the | ||
6 | ICC_CTLR_EL1 of CPU0. | ||
7 | |||
8 | Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> | ||
9 | Message-id: 20200413091552.62748-2-zhukeqian1@huawei.com | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-8-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++----------- | 13 | hw/intc/arm_gicv3_kvm.c | 4 +--- |
9 | 1 file changed, 67 insertions(+), 19 deletions(-) | 14 | 1 file changed, 1 insertion(+), 3 deletions(-) |
10 | 15 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 16 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c |
12 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 18 | --- a/hw/intc/arm_gicv3_kvm.c |
14 | +++ b/target/arm/translate.c | 19 | +++ b/hw/intc/arm_gicv3_kvm.c |
15 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s) |
16 | #include "disas/disas.h" | 21 | |
17 | #include "exec/exec-all.h" | 22 | static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
18 | #include "tcg-op.h" | 23 | { |
19 | +#include "tcg-op-gvec.h" | 24 | - ARMCPU *cpu; |
20 | #include "qemu/log.h" | 25 | GICv3State *s; |
21 | #include "qemu/bitops.h" | 26 | GICv3CPUState *c; |
22 | #include "arm_ldst.h" | 27 | |
23 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_narrow_op(int op, int u, int size, | 28 | c = (GICv3CPUState *)env->gicv3state; |
24 | #define NEON_3R_VPMAX 20 | 29 | s = c->gic; |
25 | #define NEON_3R_VPMIN 21 | 30 | - cpu = ARM_CPU(c->cpu); |
26 | #define NEON_3R_VQDMULH_VQRDMULH 22 | 31 | |
27 | -#define NEON_3R_VPADD 23 | 32 | c->icc_pmr_el1 = 0; |
28 | +#define NEON_3R_VPADD_VQRDMLAH 23 | 33 | c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; |
29 | #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ | 34 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
30 | -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ | 35 | |
31 | +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ | 36 | /* Initialize to actual HW supported configuration */ |
32 | #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ | 37 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, |
33 | #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ | 38 | - KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), |
34 | #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ | 39 | + KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), |
35 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_3r_sizes[] = { | 40 | &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); |
36 | [NEON_3R_VPMAX] = 0x7, | 41 | |
37 | [NEON_3R_VPMIN] = 0x7, | 42 | c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; |
38 | [NEON_3R_VQDMULH_VQRDMULH] = 0x6, | ||
39 | - [NEON_3R_VPADD] = 0x7, | ||
40 | + [NEON_3R_VPADD_VQRDMLAH] = 0x7, | ||
41 | [NEON_3R_SHA] = 0xf, /* size field encodes op type */ | ||
42 | - [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */ | ||
43 | + [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ | ||
44 | [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ | ||
45 | [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ | ||
46 | [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ | ||
47 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_2rm_sizes[] = { | ||
48 | [NEON_2RM_VCVT_UF] = 0x4, | ||
49 | }; | ||
50 | |||
51 | + | ||
52 | +/* Expand v8.1 simd helper. */ | ||
53 | +static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, | ||
54 | + int q, int rd, int rn, int rm) | ||
55 | +{ | ||
56 | + if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
57 | + int opr_sz = (1 + q) * 8; | ||
58 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
59 | + vfp_reg_offset(1, rn), | ||
60 | + vfp_reg_offset(1, rm), cpu_env, | ||
61 | + opr_sz, opr_sz, 0, fn); | ||
62 | + return 0; | ||
63 | + } | ||
64 | + return 1; | ||
65 | +} | ||
66 | + | ||
67 | /* Translate a NEON data processing instruction. Return nonzero if the | ||
68 | instruction is invalid. | ||
69 | We process data in a mixture of 32-bit and 64-bit chunks. | ||
70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
71 | if (q && ((rd | rn | rm) & 1)) { | ||
72 | return 1; | ||
73 | } | ||
74 | - /* | ||
75 | - * The SHA-1/SHA-256 3-register instructions require special treatment | ||
76 | - * here, as their size field is overloaded as an op type selector, and | ||
77 | - * they all consume their input in a single pass. | ||
78 | - */ | ||
79 | - if (op == NEON_3R_SHA) { | ||
80 | + switch (op) { | ||
81 | + case NEON_3R_SHA: | ||
82 | + /* The SHA-1/SHA-256 3-register instructions require special | ||
83 | + * treatment here, as their size field is overloaded as an | ||
84 | + * op type selector, and they all consume their input in a | ||
85 | + * single pass. | ||
86 | + */ | ||
87 | if (!q) { | ||
88 | return 1; | ||
89 | } | ||
90 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
91 | tcg_temp_free_ptr(ptr2); | ||
92 | tcg_temp_free_ptr(ptr3); | ||
93 | return 0; | ||
94 | + | ||
95 | + case NEON_3R_VPADD_VQRDMLAH: | ||
96 | + if (!u) { | ||
97 | + break; /* VPADD */ | ||
98 | + } | ||
99 | + /* VQRDMLAH */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16, | ||
103 | + q, rd, rn, rm); | ||
104 | + case 2: | ||
105 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32, | ||
106 | + q, rd, rn, rm); | ||
107 | + } | ||
108 | + return 1; | ||
109 | + | ||
110 | + case NEON_3R_VFM_VQRDMLSH: | ||
111 | + if (!u) { | ||
112 | + /* VFM, VFMS */ | ||
113 | + if (size == 1) { | ||
114 | + return 1; | ||
115 | + } | ||
116 | + break; | ||
117 | + } | ||
118 | + /* VQRDMLSH */ | ||
119 | + switch (size) { | ||
120 | + case 1: | ||
121 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16, | ||
122 | + q, rd, rn, rm); | ||
123 | + case 2: | ||
124 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32, | ||
125 | + q, rd, rn, rm); | ||
126 | + } | ||
127 | + return 1; | ||
128 | } | ||
129 | if (size == 3 && op != NEON_3R_LOGIC) { | ||
130 | /* 64-bit element instructions. */ | ||
131 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
132 | rm = rtmp; | ||
133 | } | ||
134 | break; | ||
135 | - case NEON_3R_VPADD: | ||
136 | - if (u) { | ||
137 | - return 1; | ||
138 | - } | ||
139 | - /* Fall through */ | ||
140 | + case NEON_3R_VPADD_VQRDMLAH: | ||
141 | case NEON_3R_VPMAX: | ||
142 | case NEON_3R_VPMIN: | ||
143 | pairwise = 1; | ||
144 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
145 | return 1; | ||
146 | } | ||
147 | break; | ||
148 | - case NEON_3R_VFM: | ||
149 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { | ||
150 | + case NEON_3R_VFM_VQRDMLSH: | ||
151 | + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { | ||
152 | return 1; | ||
153 | } | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
156 | } | ||
157 | } | ||
158 | break; | ||
159 | - case NEON_3R_VPADD: | ||
160 | + case NEON_3R_VPADD_VQRDMLAH: | ||
161 | switch (size) { | ||
162 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; | ||
163 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | ||
164 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
165 | } | ||
166 | } | ||
167 | break; | ||
168 | - case NEON_3R_VFM: | ||
169 | + case NEON_3R_VFM_VQRDMLSH: | ||
170 | { | ||
171 | /* VFMA, VFMS: fused multiply-add */ | ||
172 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
173 | -- | 43 | -- |
174 | 2.16.2 | 44 | 2.20.1 |
175 | 45 | ||
176 | 46 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Keqian Zhu <zhukeqian1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Allow the translate subroutines to return false for invalid insns. | 3 | Replace "acpi-mem-hotplug" with "acpi-cpu-hotplug" |
4 | 4 | ||
5 | At present we can of course invoke an invalid insn exception from within | 5 | Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> |
6 | the translate subroutine, but in the short term this consolidates code. | 6 | Message-id: 20200413091552.62748-4-zhukeqian1@huawei.com |
7 | In the long term it would allow the decodetree language to support | ||
8 | overlapping patterns for ISA extensions. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20180227232618.2908-1-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 9 | --- |
15 | scripts/decodetree.py | 5 ++--- | 10 | hw/acpi/cpu.c | 2 +- |
16 | 1 file changed, 2 insertions(+), 3 deletions(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
17 | 12 | ||
18 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py | 13 | diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c |
19 | index XXXXXXX..XXXXXXX 100755 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/scripts/decodetree.py | 15 | --- a/hw/acpi/cpu.c |
21 | +++ b/scripts/decodetree.py | 16 | +++ b/hw/acpi/cpu.c |
22 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | 17 | @@ -XXX,XX +XXX,XX @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, |
23 | global translate_prefix | 18 | state->devs[i].arch_id = id_list->cpus[i].arch_id; |
24 | output('typedef ', self.base.base.struct_name(), | 19 | } |
25 | ' arg_', self.name, ';\n') | 20 | memory_region_init_io(&state->ctrl_reg, owner, &cpu_hotplug_ops, state, |
26 | - output(translate_scope, 'void ', translate_prefix, '_', self.name, | 21 | - "acpi-mem-hotplug", ACPI_CPU_HOTPLUG_REG_LEN); |
27 | + output(translate_scope, 'bool ', translate_prefix, '_', self.name, | 22 | + "acpi-cpu-hotplug", ACPI_CPU_HOTPLUG_REG_LEN); |
28 | '(DisasContext *ctx, arg_', self.name, | 23 | memory_region_add_subregion(as, base_addr, &state->ctrl_reg); |
29 | ' *a, ', insntype, ' insn);\n') | 24 | } |
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | ||
32 | output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n') | ||
33 | for n, f in self.fields.items(): | ||
34 | output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') | ||
35 | - output(ind, translate_prefix, '_', self.name, | ||
36 | + output(ind, 'return ', translate_prefix, '_', self.name, | ||
37 | '(ctx, &u.f_', arg, ', insn);\n') | ||
38 | - output(ind, 'return true;\n') | ||
39 | # end Pattern | ||
40 | |||
41 | 25 | ||
42 | -- | 26 | -- |
43 | 2.16.2 | 27 | 2.20.1 |
44 | 28 | ||
45 | 29 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@xilinx.com> | 1 | From: Subbaraya Sundeep <sundeep.lkml@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Initial commit of the ZynqMP RTC device. | 3 | Modelled Ethernet MAC of Smartfusion2 SoC. |
4 | Micrel KSZ8051 PHY is present on Emcraft's | ||
5 | SOM kit hence same PHY is emulated. | ||
4 | 6 | ||
5 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | 7 | Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
9 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 1587048891-30493-2-git-send-email-sundeep.lkml@gmail.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 12 | --- |
9 | hw/timer/Makefile.objs | 1 + | 13 | hw/net/Makefile.objs | 1 + |
10 | include/hw/timer/xlnx-zynqmp-rtc.h | 84 +++++++++++++++ | 14 | include/hw/net/msf2-emac.h | 53 ++++ |
11 | hw/timer/xlnx-zynqmp-rtc.c | 214 +++++++++++++++++++++++++++++++++++++ | 15 | hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++++++ |
12 | 3 files changed, 299 insertions(+) | 16 | MAINTAINERS | 2 + |
13 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | 17 | 4 files changed, 645 insertions(+) |
14 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | 18 | create mode 100644 include/hw/net/msf2-emac.h |
19 | create mode 100644 hw/net/msf2-emac.c | ||
15 | 20 | ||
16 | diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs | 21 | diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs |
17 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/timer/Makefile.objs | 23 | --- a/hw/net/Makefile.objs |
19 | +++ b/hw/timer/Makefile.objs | 24 | +++ b/hw/net/Makefile.objs |
20 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx_epit.o | 25 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \ |
21 | common-obj-$(CONFIG_IMX) += imx_gpt.o | 26 | obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o |
22 | common-obj-$(CONFIG_LM32) += lm32_timer.o | 27 | |
23 | common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o | 28 | common-obj-$(CONFIG_CAN_BUS) += can/ |
24 | +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o | 29 | +common-obj-$(CONFIG_MSF2) += msf2-emac.o |
25 | 30 | diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h | |
26 | obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o | ||
27 | obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o | ||
28 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
29 | new file mode 100644 | 31 | new file mode 100644 |
30 | index XXXXXXX..XXXXXXX | 32 | index XXXXXXX..XXXXXXX |
31 | --- /dev/null | 33 | --- /dev/null |
32 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | 34 | +++ b/include/hw/net/msf2-emac.h |
33 | @@ -XXX,XX +XXX,XX @@ | 35 | @@ -XXX,XX +XXX,XX @@ |
34 | +/* | 36 | +/* |
35 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | 37 | + * QEMU model of the Smartfusion2 Ethernet MAC. |
36 | + * | 38 | + * |
37 | + * Copyright (c) 2017 Xilinx Inc. | 39 | + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. |
38 | + * | ||
39 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
40 | + * | 40 | + * |
41 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 41 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
42 | + * of this software and associated documentation files (the "Software"), to deal | 42 | + * of this software and associated documentation files (the "Software"), to deal |
43 | + * in the Software without restriction, including without limitation the rights | 43 | + * in the Software without restriction, including without limitation the rights |
44 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 44 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
... | ... | ||
55 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | 55 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
56 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 56 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
57 | + * THE SOFTWARE. | 57 | + * THE SOFTWARE. |
58 | + */ | 58 | + */ |
59 | + | 59 | + |
60 | +#include "hw/register.h" | 60 | +#include "hw/sysbus.h" |
61 | + | 61 | +#include "exec/memory.h" |
62 | +#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc" | 62 | +#include "net/net.h" |
63 | + | 63 | +#include "net/eth.h" |
64 | +#define XLNX_ZYNQMP_RTC(obj) \ | 64 | + |
65 | + OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC) | 65 | +#define TYPE_MSS_EMAC "msf2-emac" |
66 | + | 66 | +#define MSS_EMAC(obj) \ |
67 | +REG32(SET_TIME_WRITE, 0x0) | 67 | + OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC) |
68 | +REG32(SET_TIME_READ, 0x4) | 68 | + |
69 | +REG32(CALIB_WRITE, 0x8) | 69 | +#define R_MAX (0x1a0 / 4) |
70 | + FIELD(CALIB_WRITE, FRACTION_EN, 20, 1) | 70 | +#define PHY_MAX_REGS 32 |
71 | + FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4) | 71 | + |
72 | + FIELD(CALIB_WRITE, MAX_TICK, 0, 16) | 72 | +typedef struct MSF2EmacState { |
73 | +REG32(CALIB_READ, 0xc) | 73 | + SysBusDevice parent; |
74 | + FIELD(CALIB_READ, FRACTION_EN, 20, 1) | 74 | + |
75 | + FIELD(CALIB_READ, FRACTION_DATA, 16, 4) | 75 | + MemoryRegion mmio; |
76 | + FIELD(CALIB_READ, MAX_TICK, 0, 16) | 76 | + MemoryRegion *dma_mr; |
77 | +REG32(CURRENT_TIME, 0x10) | 77 | + AddressSpace dma_as; |
78 | +REG32(CURRENT_TICK, 0x14) | 78 | + |
79 | + FIELD(CURRENT_TICK, VALUE, 0, 16) | 79 | + qemu_irq irq; |
80 | +REG32(ALARM, 0x18) | 80 | + NICState *nic; |
81 | +REG32(RTC_INT_STATUS, 0x20) | 81 | + NICConf conf; |
82 | + FIELD(RTC_INT_STATUS, ALARM, 1, 1) | 82 | + |
83 | + FIELD(RTC_INT_STATUS, SECONDS, 0, 1) | 83 | + uint8_t mac_addr[ETH_ALEN]; |
84 | +REG32(RTC_INT_MASK, 0x24) | 84 | + uint32_t rx_desc; |
85 | + FIELD(RTC_INT_MASK, ALARM, 1, 1) | 85 | + uint16_t phy_regs[PHY_MAX_REGS]; |
86 | + FIELD(RTC_INT_MASK, SECONDS, 0, 1) | 86 | + |
87 | +REG32(RTC_INT_EN, 0x28) | 87 | + uint32_t regs[R_MAX]; |
88 | + FIELD(RTC_INT_EN, ALARM, 1, 1) | 88 | +} MSF2EmacState; |
89 | + FIELD(RTC_INT_EN, SECONDS, 0, 1) | 89 | diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c |
90 | +REG32(RTC_INT_DIS, 0x2c) | ||
91 | + FIELD(RTC_INT_DIS, ALARM, 1, 1) | ||
92 | + FIELD(RTC_INT_DIS, SECONDS, 0, 1) | ||
93 | +REG32(ADDR_ERROR, 0x30) | ||
94 | + FIELD(ADDR_ERROR, STATUS, 0, 1) | ||
95 | +REG32(ADDR_ERROR_INT_MASK, 0x34) | ||
96 | + FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1) | ||
97 | +REG32(ADDR_ERROR_INT_EN, 0x38) | ||
98 | + FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1) | ||
99 | +REG32(ADDR_ERROR_INT_DIS, 0x3c) | ||
100 | + FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1) | ||
101 | +REG32(CONTROL, 0x40) | ||
102 | + FIELD(CONTROL, BATTERY_DISABLE, 31, 1) | ||
103 | + FIELD(CONTROL, OSC_CNTRL, 24, 4) | ||
104 | + FIELD(CONTROL, SLVERR_ENABLE, 0, 1) | ||
105 | +REG32(SAFETY_CHK, 0x50) | ||
106 | + | ||
107 | +#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1) | ||
108 | + | ||
109 | +typedef struct XlnxZynqMPRTC { | ||
110 | + SysBusDevice parent_obj; | ||
111 | + MemoryRegion iomem; | ||
112 | + qemu_irq irq_rtc_int; | ||
113 | + qemu_irq irq_addr_error_int; | ||
114 | + | ||
115 | + uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
116 | + RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
117 | +} XlnxZynqMPRTC; | ||
118 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
119 | new file mode 100644 | 90 | new file mode 100644 |
120 | index XXXXXXX..XXXXXXX | 91 | index XXXXXXX..XXXXXXX |
121 | --- /dev/null | 92 | --- /dev/null |
122 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | 93 | +++ b/hw/net/msf2-emac.c |
123 | @@ -XXX,XX +XXX,XX @@ | 94 | @@ -XXX,XX +XXX,XX @@ |
124 | +/* | 95 | +/* |
125 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | 96 | + * QEMU model of the Smartfusion2 Ethernet MAC. |
126 | + * | 97 | + * |
127 | + * Copyright (c) 2017 Xilinx Inc. | 98 | + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. |
128 | + * | ||
129 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
130 | + * | 99 | + * |
131 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 100 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
132 | + * of this software and associated documentation files (the "Software"), to deal | 101 | + * of this software and associated documentation files (the "Software"), to deal |
133 | + * in the Software without restriction, including without limitation the rights | 102 | + * in the Software without restriction, including without limitation the rights |
134 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 103 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
... | ... | ||
143 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 112 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
144 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 113 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
145 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | 114 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
146 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 115 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
147 | + * THE SOFTWARE. | 116 | + * THE SOFTWARE. |
117 | + * | ||
118 | + * Refer to section Ethernet MAC in the document: | ||
119 | + * UG0331: SmartFusion2 Microcontroller Subsystem User Guide | ||
120 | + * Datasheet URL: | ||
121 | + * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/ | ||
122 | + * 56758-soc?lang=en&limit=20&limitstart=220 | ||
148 | + */ | 123 | + */ |
149 | + | 124 | + |
150 | +#include "qemu/osdep.h" | 125 | +#include "qemu/osdep.h" |
151 | +#include "hw/sysbus.h" | 126 | +#include "qemu-common.h" |
152 | +#include "hw/register.h" | ||
153 | +#include "qemu/bitops.h" | ||
154 | +#include "qemu/log.h" | 127 | +#include "qemu/log.h" |
155 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | 128 | +#include "qapi/error.h" |
156 | + | 129 | +#include "exec/address-spaces.h" |
157 | +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | 130 | +#include "hw/registerfields.h" |
158 | +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0 | 131 | +#include "hw/net/msf2-emac.h" |
159 | +#endif | 132 | +#include "hw/net/mii.h" |
160 | + | 133 | +#include "hw/irq.h" |
161 | +static void rtc_int_update_irq(XlnxZynqMPRTC *s) | 134 | +#include "hw/qdev-properties.h" |
162 | +{ | 135 | +#include "migration/vmstate.h" |
163 | + bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; | 136 | + |
164 | + qemu_set_irq(s->irq_rtc_int, pending); | 137 | +REG32(CFG1, 0x0) |
165 | +} | 138 | + FIELD(CFG1, RESET, 31, 1) |
166 | + | 139 | + FIELD(CFG1, RX_EN, 2, 1) |
167 | +static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | 140 | + FIELD(CFG1, TX_EN, 0, 1) |
168 | +{ | 141 | + FIELD(CFG1, LB_EN, 8, 1) |
169 | + bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; | 142 | +REG32(CFG2, 0x4) |
170 | + qemu_set_irq(s->irq_addr_error_int, pending); | 143 | +REG32(IFG, 0x8) |
171 | +} | 144 | +REG32(HALF_DUPLEX, 0xc) |
172 | + | 145 | +REG32(MAX_FRAME_LENGTH, 0x10) |
173 | +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | 146 | +REG32(MII_CMD, 0x24) |
174 | +{ | 147 | + FIELD(MII_CMD, READ, 0, 1) |
175 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 148 | +REG32(MII_ADDR, 0x28) |
176 | + rtc_int_update_irq(s); | 149 | + FIELD(MII_ADDR, REGADDR, 0, 5) |
177 | +} | 150 | + FIELD(MII_ADDR, PHYADDR, 8, 5) |
178 | + | 151 | +REG32(MII_CTL, 0x2c) |
179 | +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64) | 152 | +REG32(MII_STS, 0x30) |
180 | +{ | 153 | +REG32(STA1, 0x40) |
181 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 154 | +REG32(STA2, 0x44) |
182 | + | 155 | +REG32(FIFO_CFG0, 0x48) |
183 | + s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64; | 156 | +REG32(FIFO_CFG4, 0x58) |
184 | + rtc_int_update_irq(s); | 157 | + FIELD(FIFO_CFG4, BCAST, 9, 1) |
185 | + return 0; | 158 | + FIELD(FIFO_CFG4, MCAST, 8, 1) |
186 | +} | 159 | +REG32(FIFO_CFG5, 0x5C) |
187 | + | 160 | + FIELD(FIFO_CFG5, BCAST, 9, 1) |
188 | +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64) | 161 | + FIELD(FIFO_CFG5, MCAST, 8, 1) |
189 | +{ | 162 | +REG32(DMA_TX_CTL, 0x180) |
190 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 163 | + FIELD(DMA_TX_CTL, EN, 0, 1) |
191 | + | 164 | +REG32(DMA_TX_DESC, 0x184) |
192 | + s->regs[R_RTC_INT_MASK] |= (uint32_t) val64; | 165 | +REG32(DMA_TX_STATUS, 0x188) |
193 | + rtc_int_update_irq(s); | 166 | + FIELD(DMA_TX_STATUS, PKTCNT, 16, 8) |
194 | + return 0; | 167 | + FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1) |
195 | +} | 168 | + FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1) |
196 | + | 169 | +REG32(DMA_RX_CTL, 0x18c) |
197 | +static void addr_error_postw(RegisterInfo *reg, uint64_t val64) | 170 | + FIELD(DMA_RX_CTL, EN, 0, 1) |
198 | +{ | 171 | +REG32(DMA_RX_DESC, 0x190) |
199 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 172 | +REG32(DMA_RX_STATUS, 0x194) |
200 | + addr_error_int_update_irq(s); | 173 | + FIELD(DMA_RX_STATUS, PKTCNT, 16, 8) |
201 | +} | 174 | + FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1) |
202 | + | 175 | + FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1) |
203 | +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64) | 176 | +REG32(DMA_IRQ_MASK, 0x198) |
204 | +{ | 177 | +REG32(DMA_IRQ, 0x19c) |
205 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 178 | + |
206 | + | 179 | +#define EMPTY_MASK (1 << 31) |
207 | + s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64; | 180 | +#define PKT_SIZE 0x7FF |
208 | + addr_error_int_update_irq(s); | 181 | +#define PHYADDR 0x1 |
209 | + return 0; | 182 | +#define MAX_PKT_SIZE 2048 |
210 | +} | 183 | + |
211 | + | 184 | +typedef struct { |
212 | +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | 185 | + uint32_t pktaddr; |
213 | +{ | 186 | + uint32_t pktsize; |
214 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 187 | + uint32_t next; |
215 | + | 188 | +} EmacDesc; |
216 | + s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64; | 189 | + |
217 | + addr_error_int_update_irq(s); | 190 | +static uint32_t emac_get_isr(MSF2EmacState *s) |
218 | + return 0; | 191 | +{ |
219 | +} | 192 | + uint32_t ier = s->regs[R_DMA_IRQ_MASK]; |
220 | + | 193 | + uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF; |
221 | +static const RegisterAccessInfo rtc_regs_info[] = { | 194 | + uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF; |
222 | + { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | 195 | + uint32_t isr = (rx << 4) | tx; |
223 | + },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | 196 | + |
224 | + .ro = 0xffffffff, | 197 | + s->regs[R_DMA_IRQ] = ier & isr; |
225 | + },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | 198 | + return s->regs[R_DMA_IRQ]; |
226 | + },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | 199 | +} |
227 | + .ro = 0x1fffff, | 200 | + |
228 | + },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | 201 | +static void emac_update_irq(MSF2EmacState *s) |
229 | + .ro = 0xffffffff, | 202 | +{ |
230 | + },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | 203 | + bool intr = emac_get_isr(s); |
231 | + .ro = 0xffff, | 204 | + |
232 | + },{ .name = "ALARM", .addr = A_ALARM, | 205 | + qemu_set_irq(s->irq, intr); |
233 | + },{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS, | 206 | +} |
234 | + .w1c = 0x3, | 207 | + |
235 | + .post_write = rtc_int_status_postw, | 208 | +static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) |
236 | + },{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK, | 209 | +{ |
237 | + .reset = 0x3, | 210 | + address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); |
238 | + .ro = 0x3, | 211 | + /* Convert from LE into host endianness. */ |
239 | + },{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN, | 212 | + d->pktaddr = le32_to_cpu(d->pktaddr); |
240 | + .pre_write = rtc_int_en_prew, | 213 | + d->pktsize = le32_to_cpu(d->pktsize); |
241 | + },{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS, | 214 | + d->next = le32_to_cpu(d->next); |
242 | + .pre_write = rtc_int_dis_prew, | 215 | +} |
243 | + },{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR, | 216 | + |
244 | + .w1c = 0x1, | 217 | +static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) |
245 | + .post_write = addr_error_postw, | 218 | +{ |
246 | + },{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK, | 219 | + /* Convert from host endianness into LE. */ |
247 | + .reset = 0x1, | 220 | + d->pktaddr = cpu_to_le32(d->pktaddr); |
248 | + .ro = 0x1, | 221 | + d->pktsize = cpu_to_le32(d->pktsize); |
249 | + },{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN, | 222 | + d->next = cpu_to_le32(d->next); |
250 | + .pre_write = addr_error_int_en_prew, | 223 | + |
251 | + },{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS, | 224 | + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); |
252 | + .pre_write = addr_error_int_dis_prew, | 225 | +} |
253 | + },{ .name = "CONTROL", .addr = A_CONTROL, | 226 | + |
254 | + .reset = 0x1000000, | 227 | +static void msf2_dma_tx(MSF2EmacState *s) |
255 | + .rsvd = 0x70fffffe, | 228 | +{ |
256 | + },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK, | 229 | + NetClientState *nc = qemu_get_queue(s->nic); |
230 | + hwaddr desc = s->regs[R_DMA_TX_DESC]; | ||
231 | + uint8_t buf[MAX_PKT_SIZE]; | ||
232 | + EmacDesc d; | ||
233 | + int size; | ||
234 | + uint8_t pktcnt; | ||
235 | + uint32_t status; | ||
236 | + | ||
237 | + if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { | ||
238 | + return; | ||
239 | + } | ||
240 | + | ||
241 | + while (1) { | ||
242 | + emac_load_desc(s, &d, desc); | ||
243 | + if (d.pktsize & EMPTY_MASK) { | ||
244 | + break; | ||
245 | + } | ||
246 | + size = d.pktsize & PKT_SIZE; | ||
247 | + address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, | ||
248 | + buf, size); | ||
249 | + /* | ||
250 | + * This is very basic way to send packets. Ideally there should be | ||
251 | + * a FIFO and packets should be sent out from FIFO only when | ||
252 | + * R_CFG1 bit 0 is set. | ||
253 | + */ | ||
254 | + if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { | ||
255 | + nc->info->receive(nc, buf, size); | ||
256 | + } else { | ||
257 | + qemu_send_packet(nc, buf, size); | ||
258 | + } | ||
259 | + d.pktsize |= EMPTY_MASK; | ||
260 | + emac_store_desc(s, &d, desc); | ||
261 | + /* update sent packets count */ | ||
262 | + status = s->regs[R_DMA_TX_STATUS]; | ||
263 | + pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT); | ||
264 | + pktcnt++; | ||
265 | + s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS, | ||
266 | + PKTCNT, pktcnt); | ||
267 | + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK; | ||
268 | + desc = d.next; | ||
269 | + } | ||
270 | + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK; | ||
271 | + s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK; | ||
272 | +} | ||
273 | + | ||
274 | +static void msf2_phy_update_link(MSF2EmacState *s) | ||
275 | +{ | ||
276 | + /* Autonegotiation status mirrors link status. */ | ||
277 | + if (qemu_get_queue(s->nic)->link_down) { | ||
278 | + s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | | ||
279 | + MII_BMSR_LINK_ST); | ||
280 | + } else { | ||
281 | + s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | | ||
282 | + MII_BMSR_LINK_ST); | ||
283 | + } | ||
284 | +} | ||
285 | + | ||
286 | +static void msf2_phy_reset(MSF2EmacState *s) | ||
287 | +{ | ||
288 | + memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); | ||
289 | + s->phy_regs[MII_BMCR] = 0x1140; | ||
290 | + s->phy_regs[MII_BMSR] = 0x7968; | ||
291 | + s->phy_regs[MII_PHYID1] = 0x0022; | ||
292 | + s->phy_regs[MII_PHYID2] = 0x1550; | ||
293 | + s->phy_regs[MII_ANAR] = 0x01E1; | ||
294 | + s->phy_regs[MII_ANLPAR] = 0xCDE1; | ||
295 | + | ||
296 | + msf2_phy_update_link(s); | ||
297 | +} | ||
298 | + | ||
299 | +static void write_to_phy(MSF2EmacState *s) | ||
300 | +{ | ||
301 | + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; | ||
302 | + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & | ||
303 | + R_MII_ADDR_REGADDR_MASK; | ||
304 | + uint16_t data = s->regs[R_MII_CTL] & 0xFFFF; | ||
305 | + | ||
306 | + if (phy_addr != PHYADDR) { | ||
307 | + return; | ||
308 | + } | ||
309 | + | ||
310 | + switch (reg_addr) { | ||
311 | + case MII_BMCR: | ||
312 | + if (data & MII_BMCR_RESET) { | ||
313 | + /* Phy reset */ | ||
314 | + msf2_phy_reset(s); | ||
315 | + data &= ~MII_BMCR_RESET; | ||
316 | + } | ||
317 | + if (data & MII_BMCR_AUTOEN) { | ||
318 | + /* Complete autonegotiation immediately */ | ||
319 | + data &= ~MII_BMCR_AUTOEN; | ||
320 | + s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; | ||
321 | + } | ||
322 | + break; | ||
323 | + } | ||
324 | + | ||
325 | + s->phy_regs[reg_addr] = data; | ||
326 | +} | ||
327 | + | ||
328 | +static uint16_t read_from_phy(MSF2EmacState *s) | ||
329 | +{ | ||
330 | + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; | ||
331 | + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & | ||
332 | + R_MII_ADDR_REGADDR_MASK; | ||
333 | + | ||
334 | + if (phy_addr == PHYADDR) { | ||
335 | + return s->phy_regs[reg_addr]; | ||
336 | + } else { | ||
337 | + return 0xFFFF; | ||
338 | + } | ||
339 | +} | ||
340 | + | ||
341 | +static void msf2_emac_do_reset(MSF2EmacState *s) | ||
342 | +{ | ||
343 | + memset(&s->regs[0], 0, sizeof(s->regs)); | ||
344 | + s->regs[R_CFG1] = 0x80000000; | ||
345 | + s->regs[R_CFG2] = 0x00007000; | ||
346 | + s->regs[R_IFG] = 0x40605060; | ||
347 | + s->regs[R_HALF_DUPLEX] = 0x00A1F037; | ||
348 | + s->regs[R_MAX_FRAME_LENGTH] = 0x00000600; | ||
349 | + s->regs[R_FIFO_CFG5] = 0X3FFFF; | ||
350 | + | ||
351 | + msf2_phy_reset(s); | ||
352 | +} | ||
353 | + | ||
354 | +static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size) | ||
355 | +{ | ||
356 | + MSF2EmacState *s = opaque; | ||
357 | + uint32_t r = 0; | ||
358 | + | ||
359 | + addr >>= 2; | ||
360 | + | ||
361 | + switch (addr) { | ||
362 | + case R_DMA_IRQ: | ||
363 | + r = emac_get_isr(s); | ||
364 | + break; | ||
365 | + default: | ||
366 | + if (addr >= ARRAY_SIZE(s->regs)) { | ||
367 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
368 | + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, | ||
369 | + addr * 4); | ||
370 | + return r; | ||
371 | + } | ||
372 | + r = s->regs[addr]; | ||
373 | + break; | ||
374 | + } | ||
375 | + return r; | ||
376 | +} | ||
377 | + | ||
378 | +static void emac_write(void *opaque, hwaddr addr, uint64_t val64, | ||
379 | + unsigned int size) | ||
380 | +{ | ||
381 | + MSF2EmacState *s = opaque; | ||
382 | + uint32_t value = val64; | ||
383 | + uint32_t enreqbits; | ||
384 | + uint8_t pktcnt; | ||
385 | + | ||
386 | + addr >>= 2; | ||
387 | + switch (addr) { | ||
388 | + case R_DMA_TX_CTL: | ||
389 | + s->regs[addr] = value; | ||
390 | + if (value & R_DMA_TX_CTL_EN_MASK) { | ||
391 | + msf2_dma_tx(s); | ||
392 | + } | ||
393 | + break; | ||
394 | + case R_DMA_RX_CTL: | ||
395 | + s->regs[addr] = value; | ||
396 | + if (value & R_DMA_RX_CTL_EN_MASK) { | ||
397 | + s->rx_desc = s->regs[R_DMA_RX_DESC]; | ||
398 | + qemu_flush_queued_packets(qemu_get_queue(s->nic)); | ||
399 | + } | ||
400 | + break; | ||
401 | + case R_CFG1: | ||
402 | + s->regs[addr] = value; | ||
403 | + if (value & R_CFG1_RESET_MASK) { | ||
404 | + msf2_emac_do_reset(s); | ||
405 | + } | ||
406 | + break; | ||
407 | + case R_FIFO_CFG0: | ||
408 | + /* | ||
409 | + * For our implementation, turning on modules is instantaneous, | ||
410 | + * so the states requested via the *ENREQ bits appear in the | ||
411 | + * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC | ||
412 | + * module are not emulated here since it deals with start of frames, | ||
413 | + * inter-packet gap and control frames. | ||
414 | + */ | ||
415 | + enreqbits = extract32(value, 8, 5); | ||
416 | + s->regs[addr] = deposit32(value, 16, 5, enreqbits); | ||
417 | + break; | ||
418 | + case R_DMA_TX_DESC: | ||
419 | + if (value & 0x3) { | ||
420 | + qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be" | ||
421 | + " 32 bit aligned\n"); | ||
422 | + } | ||
423 | + /* Ignore [1:0] bits */ | ||
424 | + s->regs[addr] = value & ~3; | ||
425 | + break; | ||
426 | + case R_DMA_RX_DESC: | ||
427 | + if (value & 0x3) { | ||
428 | + qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be" | ||
429 | + " 32 bit aligned\n"); | ||
430 | + } | ||
431 | + /* Ignore [1:0] bits */ | ||
432 | + s->regs[addr] = value & ~3; | ||
433 | + break; | ||
434 | + case R_DMA_TX_STATUS: | ||
435 | + if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) { | ||
436 | + s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK; | ||
437 | + } | ||
438 | + if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) { | ||
439 | + pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); | ||
440 | + pktcnt--; | ||
441 | + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS, | ||
442 | + PKTCNT, pktcnt); | ||
443 | + if (pktcnt == 0) { | ||
444 | + s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK; | ||
445 | + } | ||
446 | + } | ||
447 | + break; | ||
448 | + case R_DMA_RX_STATUS: | ||
449 | + if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) { | ||
450 | + s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK; | ||
451 | + } | ||
452 | + if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) { | ||
453 | + pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); | ||
454 | + pktcnt--; | ||
455 | + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS, | ||
456 | + PKTCNT, pktcnt); | ||
457 | + if (pktcnt == 0) { | ||
458 | + s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK; | ||
459 | + } | ||
460 | + } | ||
461 | + break; | ||
462 | + case R_DMA_IRQ: | ||
463 | + break; | ||
464 | + case R_MII_CMD: | ||
465 | + if (value & R_MII_CMD_READ_MASK) { | ||
466 | + s->regs[R_MII_STS] = read_from_phy(s); | ||
467 | + } | ||
468 | + break; | ||
469 | + case R_MII_CTL: | ||
470 | + s->regs[addr] = value; | ||
471 | + write_to_phy(s); | ||
472 | + break; | ||
473 | + case R_STA1: | ||
474 | + s->regs[addr] = value; | ||
475 | + /* | ||
476 | + * R_STA1 [31:24] : octet 1 of mac address | ||
477 | + * R_STA1 [23:16] : octet 2 of mac address | ||
478 | + * R_STA1 [15:8] : octet 3 of mac address | ||
479 | + * R_STA1 [7:0] : octet 4 of mac address | ||
480 | + */ | ||
481 | + stl_be_p(s->mac_addr, value); | ||
482 | + break; | ||
483 | + case R_STA2: | ||
484 | + s->regs[addr] = value; | ||
485 | + /* | ||
486 | + * R_STA2 [31:24] : octet 5 of mac address | ||
487 | + * R_STA2 [23:16] : octet 6 of mac address | ||
488 | + */ | ||
489 | + stw_be_p(s->mac_addr + 4, value >> 16); | ||
490 | + break; | ||
491 | + default: | ||
492 | + if (addr >= ARRAY_SIZE(s->regs)) { | ||
493 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
494 | + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, | ||
495 | + addr * 4); | ||
496 | + return; | ||
497 | + } | ||
498 | + s->regs[addr] = value; | ||
499 | + break; | ||
500 | + } | ||
501 | + emac_update_irq(s); | ||
502 | +} | ||
503 | + | ||
504 | +static const MemoryRegionOps emac_ops = { | ||
505 | + .read = emac_read, | ||
506 | + .write = emac_write, | ||
507 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
508 | + .impl = { | ||
509 | + .min_access_size = 4, | ||
510 | + .max_access_size = 4 | ||
257 | + } | 511 | + } |
258 | +}; | 512 | +}; |
259 | + | 513 | + |
260 | +static void rtc_reset(DeviceState *dev) | 514 | +static bool emac_can_rx(NetClientState *nc) |
261 | +{ | 515 | +{ |
262 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev); | 516 | + MSF2EmacState *s = qemu_get_nic_opaque(nc); |
263 | + unsigned int i; | 517 | + |
264 | + | 518 | + return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && |
265 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | 519 | + (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); |
266 | + register_reset(&s->regs_info[i]); | 520 | +} |
267 | + } | 521 | + |
268 | + | 522 | +static bool addr_filter_ok(MSF2EmacState *s, const uint8_t *buf) |
269 | + rtc_int_update_irq(s); | 523 | +{ |
270 | + addr_error_int_update_irq(s); | 524 | + /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */ |
271 | +} | 525 | + const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, |
272 | + | 526 | + 0xFF, 0xFF }; |
273 | +static const MemoryRegionOps rtc_ops = { | 527 | + bool bcast_en = true; |
274 | + .read = register_read_memory, | 528 | + bool mcast_en = true; |
275 | + .write = register_write_memory, | 529 | + |
276 | + .endianness = DEVICE_LITTLE_ENDIAN, | 530 | + if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_BCAST_MASK) { |
277 | + .valid = { | 531 | + bcast_en = true; /* Broadcast dont care for drop circuitry */ |
278 | + .min_access_size = 4, | 532 | + } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_BCAST_MASK) { |
279 | + .max_access_size = 4, | 533 | + bcast_en = false; |
280 | + }, | 534 | + } |
535 | + | ||
536 | + if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_MCAST_MASK) { | ||
537 | + mcast_en = true; /* Multicast dont care for drop circuitry */ | ||
538 | + } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_MCAST_MASK) { | ||
539 | + mcast_en = false; | ||
540 | + } | ||
541 | + | ||
542 | + if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) { | ||
543 | + return bcast_en; | ||
544 | + } | ||
545 | + | ||
546 | + if (buf[0] & 1) { | ||
547 | + return mcast_en; | ||
548 | + } | ||
549 | + | ||
550 | + return !memcmp(buf, s->mac_addr, sizeof(s->mac_addr)); | ||
551 | +} | ||
552 | + | ||
553 | +static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size) | ||
554 | +{ | ||
555 | + MSF2EmacState *s = qemu_get_nic_opaque(nc); | ||
556 | + EmacDesc d; | ||
557 | + uint8_t pktcnt; | ||
558 | + uint32_t status; | ||
559 | + | ||
560 | + if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { | ||
561 | + return size; | ||
562 | + } | ||
563 | + if (!addr_filter_ok(s, buf)) { | ||
564 | + return size; | ||
565 | + } | ||
566 | + | ||
567 | + emac_load_desc(s, &d, s->rx_desc); | ||
568 | + | ||
569 | + if (d.pktsize & EMPTY_MASK) { | ||
570 | + address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, | ||
571 | + buf, size & PKT_SIZE); | ||
572 | + d.pktsize = size & PKT_SIZE; | ||
573 | + emac_store_desc(s, &d, s->rx_desc); | ||
574 | + /* update received packets count */ | ||
575 | + status = s->regs[R_DMA_RX_STATUS]; | ||
576 | + pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT); | ||
577 | + pktcnt++; | ||
578 | + s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS, | ||
579 | + PKTCNT, pktcnt); | ||
580 | + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK; | ||
581 | + s->rx_desc = d.next; | ||
582 | + } else { | ||
583 | + s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK; | ||
584 | + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK; | ||
585 | + } | ||
586 | + emac_update_irq(s); | ||
587 | + return size; | ||
588 | +} | ||
589 | + | ||
590 | +static void msf2_emac_reset(DeviceState *dev) | ||
591 | +{ | ||
592 | + MSF2EmacState *s = MSS_EMAC(dev); | ||
593 | + | ||
594 | + msf2_emac_do_reset(s); | ||
595 | +} | ||
596 | + | ||
597 | +static void emac_set_link(NetClientState *nc) | ||
598 | +{ | ||
599 | + MSF2EmacState *s = qemu_get_nic_opaque(nc); | ||
600 | + | ||
601 | + msf2_phy_update_link(s); | ||
602 | +} | ||
603 | + | ||
604 | +static NetClientInfo net_msf2_emac_info = { | ||
605 | + .type = NET_CLIENT_DRIVER_NIC, | ||
606 | + .size = sizeof(NICState), | ||
607 | + .can_receive = emac_can_rx, | ||
608 | + .receive = emac_rx, | ||
609 | + .link_status_changed = emac_set_link, | ||
281 | +}; | 610 | +}; |
282 | + | 611 | + |
283 | +static void rtc_init(Object *obj) | 612 | +static void msf2_emac_realize(DeviceState *dev, Error **errp) |
284 | +{ | 613 | +{ |
285 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | 614 | + MSF2EmacState *s = MSS_EMAC(dev); |
286 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 615 | + |
287 | + RegisterInfoArray *reg_array; | 616 | + if (!s->dma_mr) { |
288 | + | 617 | + error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); |
289 | + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | 618 | + return; |
290 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | 619 | + } |
291 | + reg_array = | 620 | + |
292 | + register_init_block32(DEVICE(obj), rtc_regs_info, | 621 | + address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); |
293 | + ARRAY_SIZE(rtc_regs_info), | 622 | + |
294 | + s->regs_info, s->regs, | 623 | + qemu_macaddr_default_if_unset(&s->conf.macaddr); |
295 | + &rtc_ops, | 624 | + s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf, |
296 | + XLNX_ZYNQMP_RTC_ERR_DEBUG, | 625 | + object_get_typename(OBJECT(dev)), dev->id, s); |
297 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | 626 | + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
298 | + memory_region_add_subregion(&s->iomem, | 627 | +} |
299 | + 0x0, | 628 | + |
300 | + ®_array->mem); | 629 | +static void msf2_emac_init(Object *obj) |
301 | + sysbus_init_mmio(sbd, &s->iomem); | 630 | +{ |
302 | + sysbus_init_irq(sbd, &s->irq_rtc_int); | 631 | + MSF2EmacState *s = MSS_EMAC(obj); |
303 | + sysbus_init_irq(sbd, &s->irq_addr_error_int); | 632 | + |
304 | +} | 633 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); |
305 | + | 634 | + |
306 | +static const VMStateDescription vmstate_rtc = { | 635 | + memory_region_init_io(&s->mmio, obj, &emac_ops, s, |
307 | + .name = TYPE_XLNX_ZYNQMP_RTC, | 636 | + "msf2-emac", R_MAX * 4); |
637 | + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
638 | +} | ||
639 | + | ||
640 | +static Property msf2_emac_properties[] = { | ||
641 | + DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, | ||
642 | + TYPE_MEMORY_REGION, MemoryRegion *), | ||
643 | + DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), | ||
644 | + DEFINE_PROP_END_OF_LIST(), | ||
645 | +}; | ||
646 | + | ||
647 | +static const VMStateDescription vmstate_msf2_emac = { | ||
648 | + .name = TYPE_MSS_EMAC, | ||
308 | + .version_id = 1, | 649 | + .version_id = 1, |
309 | + .minimum_version_id = 1, | 650 | + .minimum_version_id = 1, |
310 | + .fields = (VMStateField[]) { | 651 | + .fields = (VMStateField[]) { |
311 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | 652 | + VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN), |
312 | + VMSTATE_END_OF_LIST(), | 653 | + VMSTATE_UINT32(rx_desc, MSF2EmacState), |
654 | + VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS), | ||
655 | + VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX), | ||
656 | + VMSTATE_END_OF_LIST() | ||
313 | + } | 657 | + } |
314 | +}; | 658 | +}; |
315 | + | 659 | + |
316 | +static void rtc_class_init(ObjectClass *klass, void *data) | 660 | +static void msf2_emac_class_init(ObjectClass *klass, void *data) |
317 | +{ | 661 | +{ |
318 | + DeviceClass *dc = DEVICE_CLASS(klass); | 662 | + DeviceClass *dc = DEVICE_CLASS(klass); |
319 | + | 663 | + |
320 | + dc->reset = rtc_reset; | 664 | + dc->realize = msf2_emac_realize; |
321 | + dc->vmsd = &vmstate_rtc; | 665 | + dc->reset = msf2_emac_reset; |
322 | +} | 666 | + dc->vmsd = &vmstate_msf2_emac; |
323 | + | 667 | + device_class_set_props(dc, msf2_emac_properties); |
324 | +static const TypeInfo rtc_info = { | 668 | +} |
325 | + .name = TYPE_XLNX_ZYNQMP_RTC, | 669 | + |
670 | +static const TypeInfo msf2_emac_info = { | ||
671 | + .name = TYPE_MSS_EMAC, | ||
326 | + .parent = TYPE_SYS_BUS_DEVICE, | 672 | + .parent = TYPE_SYS_BUS_DEVICE, |
327 | + .instance_size = sizeof(XlnxZynqMPRTC), | 673 | + .instance_size = sizeof(MSF2EmacState), |
328 | + .class_init = rtc_class_init, | 674 | + .instance_init = msf2_emac_init, |
329 | + .instance_init = rtc_init, | 675 | + .class_init = msf2_emac_class_init, |
330 | +}; | 676 | +}; |
331 | + | 677 | + |
332 | +static void rtc_register_types(void) | 678 | +static void msf2_emac_register_types(void) |
333 | +{ | 679 | +{ |
334 | + type_register_static(&rtc_info); | 680 | + type_register_static(&msf2_emac_info); |
335 | +} | 681 | +} |
336 | + | 682 | + |
337 | +type_init(rtc_register_types) | 683 | +type_init(msf2_emac_register_types) |
684 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
685 | index XXXXXXX..XXXXXXX 100644 | ||
686 | --- a/MAINTAINERS | ||
687 | +++ b/MAINTAINERS | ||
688 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/msf2-soc.h | ||
689 | F: include/hw/misc/msf2-sysreg.h | ||
690 | F: include/hw/timer/mss-timer.h | ||
691 | F: include/hw/ssi/mss-spi.h | ||
692 | +F: hw/net/msf2-emac.c | ||
693 | +F: include/hw/net/msf2-emac.h | ||
694 | |||
695 | Emcraft M2S-FG484 | ||
696 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
338 | -- | 697 | -- |
339 | 2.16.2 | 698 | 2.20.1 |
340 | 699 | ||
341 | 700 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@xilinx.com> | 1 | From: Subbaraya Sundeep <sundeep.lkml@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | 3 | With SmartFusion2 Ethernet MAC model in |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | place this patch adds the same to SoC. |
5 | |||
6 | Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 1587048891-30493-3-git-send-email-sundeep.lkml@gmail.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | 12 | include/hw/arm/msf2-soc.h | 2 ++ |
9 | hw/arm/xlnx-zynqmp.c | 14 ++++++++++++++ | 13 | hw/arm/msf2-soc.c | 26 ++++++++++++++++++++++++-- |
10 | 2 files changed, 16 insertions(+) | 14 | 2 files changed, 26 insertions(+), 2 deletions(-) |
11 | 15 | ||
12 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 16 | diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/arm/xlnx-zynqmp.h | 18 | --- a/include/hw/arm/msf2-soc.h |
15 | +++ b/include/hw/arm/xlnx-zynqmp.h | 19 | +++ b/include/hw/arm/msf2-soc.h |
16 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
17 | #include "hw/dma/xlnx_dpdma.h" | 21 | #include "hw/timer/mss-timer.h" |
18 | #include "hw/display/xlnx_dp.h" | 22 | #include "hw/misc/msf2-sysreg.h" |
19 | #include "hw/intc/xlnx-zynqmp-ipi.h" | 23 | #include "hw/ssi/mss-spi.h" |
20 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | 24 | +#include "hw/net/msf2-emac.h" |
21 | 25 | ||
22 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | 26 | #define TYPE_MSF2_SOC "msf2-soc" |
23 | #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ | 27 | #define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState { | 28 | @@ -XXX,XX +XXX,XX @@ typedef struct MSF2State { |
25 | XlnxDPState dp; | 29 | MSF2SysregState sysreg; |
26 | XlnxDPDMAState dpdma; | 30 | MSSTimerState timer; |
27 | XlnxZynqMPIPI ipi; | 31 | MSSSpiState spi[MSF2_NUM_SPIS]; |
28 | + XlnxZynqMPRTC rtc; | 32 | + MSF2EmacState emac; |
29 | 33 | } MSF2State; | |
30 | char *boot_cpu; | 34 | |
31 | ARMCPU *boot_cpu_ptr; | 35 | #endif |
32 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | 36 | diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c |
33 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/hw/arm/xlnx-zynqmp.c | 38 | --- a/hw/arm/msf2-soc.c |
35 | +++ b/hw/arm/xlnx-zynqmp.c | 39 | +++ b/hw/arm/msf2-soc.c |
36 | @@ -XXX,XX +XXX,XX @@ | 40 | @@ -XXX,XX +XXX,XX @@ |
37 | #define IPI_ADDR 0xFF300000 | 41 | /* |
38 | #define IPI_IRQ 64 | 42 | * SmartFusion2 SoC emulation. |
39 | 43 | * | |
40 | +#define RTC_ADDR 0xffa60000 | 44 | - * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com> |
41 | +#define RTC_IRQ 26 | 45 | + * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com> |
46 | * | ||
47 | * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
48 | * of this software and associated documentation files (the "Software"), to deal | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | |||
51 | #define MSF2_TIMER_BASE 0x40004000 | ||
52 | #define MSF2_SYSREG_BASE 0x40038000 | ||
53 | +#define MSF2_EMAC_BASE 0x40041000 | ||
54 | |||
55 | #define ENVM_BASE_ADDRESS 0x60000000 | ||
56 | |||
57 | #define SRAM_BASE_ADDRESS 0x20000000 | ||
58 | |||
59 | +#define MSF2_EMAC_IRQ 12 | ||
42 | + | 60 | + |
43 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | 61 | #define MSF2_ENVM_MAX_SIZE (512 * KiB) |
44 | 62 | ||
45 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | 63 | /* |
46 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | 64 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_initfn(Object *obj) |
47 | 65 | sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), | |
48 | object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); | 66 | TYPE_MSS_SPI); |
49 | qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); | 67 | } |
50 | + | 68 | + |
51 | + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); | 69 | + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), |
52 | + qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); | 70 | + TYPE_MSS_EMAC); |
71 | + if (nd_table[0].used) { | ||
72 | + qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); | ||
73 | + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); | ||
74 | + } | ||
53 | } | 75 | } |
54 | 76 | ||
55 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | 77 | static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) |
56 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | 78 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) |
79 | g_free(bus_name); | ||
57 | } | 80 | } |
58 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | 81 | |
59 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | 82 | + dev = DEVICE(&s->emac); |
60 | + | 83 | + object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()), |
61 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | 84 | + "ahb-bus", &error_abort); |
62 | + if (err) { | 85 | + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); |
86 | + if (err != NULL) { | ||
63 | + error_propagate(errp, err); | 87 | + error_propagate(errp, err); |
64 | + return; | 88 | + return; |
65 | + } | 89 | + } |
66 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | 90 | + busdev = SYS_BUS_DEVICE(dev); |
67 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | 91 | + sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); |
92 | + sysbus_connect_irq(busdev, 0, | ||
93 | + qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ)); | ||
94 | + | ||
95 | /* Below devices are not modelled yet. */ | ||
96 | create_unimplemented_device("i2c_0", 0x40002000, 0x1000); | ||
97 | create_unimplemented_device("dma", 0x40003000, 0x1000); | ||
98 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) | ||
99 | create_unimplemented_device("can", 0x40015000, 0x1000); | ||
100 | create_unimplemented_device("rtc", 0x40017000, 0x1000); | ||
101 | create_unimplemented_device("apb_config", 0x40020000, 0x10000); | ||
102 | - create_unimplemented_device("emac", 0x40041000, 0x1000); | ||
103 | create_unimplemented_device("usb", 0x40043000, 0x1000); | ||
68 | } | 104 | } |
69 | 105 | ||
70 | static Property xlnx_zynqmp_props[] = { | ||
71 | -- | 106 | -- |
72 | 2.16.2 | 107 | 2.20.1 |
73 | 108 | ||
74 | 109 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Subbaraya Sundeep <sundeep.lkml@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Include the U bit in the switches rather than testing separately. | 3 | In addition to simple serial test this patch uses ping |
4 | to test the ethernet block modelled in SmartFusion2 SoC. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Message-id: 20180228193125.20577-3-richard.henderson@linaro.org | 8 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
9 | Message-id: 1587048891-30493-4-git-send-email-sundeep.lkml@gmail.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------ | 12 | tests/acceptance/boot_linux_console.py | 15 ++++++++++----- |
11 | 1 file changed, 61 insertions(+), 68 deletions(-) | 13 | 1 file changed, 10 insertions(+), 5 deletions(-) |
12 | 14 | ||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 15 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a64.c | 17 | --- a/tests/acceptance/boot_linux_console.py |
16 | +++ b/target/arm/translate-a64.c | 18 | +++ b/tests/acceptance/boot_linux_console.py |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): |
18 | int index; | 20 | """ |
19 | TCGv_ptr fpst; | 21 | uboot_url = ('https://raw.githubusercontent.com/' |
20 | 22 | 'Subbaraya-Sundeep/qemu-test-binaries/' | |
21 | - switch (opcode) { | 23 | - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/u-boot') |
22 | - case 0x0: /* MLA */ | 24 | - uboot_hash = 'abba5d9c24cdd2d49cdc2a8aa92976cf20737eff' |
23 | - case 0x4: /* MLS */ | 25 | + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/u-boot') |
24 | - if (!u || is_scalar) { | 26 | + uboot_hash = 'cbb8cbab970f594bf6523b9855be209c08374ae2' |
25 | + switch (16 * u + opcode) { | 27 | uboot_path = self.fetch_asset(uboot_url, asset_hash=uboot_hash) |
26 | + case 0x08: /* MUL */ | 28 | spi_url = ('https://raw.githubusercontent.com/' |
27 | + case 0x10: /* MLA */ | 29 | 'Subbaraya-Sundeep/qemu-test-binaries/' |
28 | + case 0x14: /* MLS */ | 30 | - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/spi.bin') |
29 | + if (is_scalar) { | 31 | - spi_hash = '85f698329d38de63aea6e884a86fbde70890a78a' |
30 | unallocated_encoding(s); | 32 | + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/spi.bin') |
31 | return; | 33 | + spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501' |
32 | } | 34 | spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash) |
33 | break; | 35 | |
34 | - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | 36 | self.vm.set_console() |
35 | - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | 37 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(Test): |
36 | - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | 38 | '-drive', 'file=' + spi_path + ',if=mtd,format=raw', |
37 | + case 0x02: /* SMLAL, SMLAL2 */ | 39 | '-no-reboot') |
38 | + case 0x12: /* UMLAL, UMLAL2 */ | 40 | self.vm.launch() |
39 | + case 0x06: /* SMLSL, SMLSL2 */ | 41 | - self.wait_for_console_pattern('init started: BusyBox') |
40 | + case 0x16: /* UMLSL, UMLSL2 */ | 42 | + self.wait_for_console_pattern('Enter \'help\' for a list') |
41 | + case 0x0a: /* SMULL, SMULL2 */ | 43 | + |
42 | + case 0x1a: /* UMULL, UMULL2 */ | 44 | + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 10.0.2.15', |
43 | if (is_scalar) { | 45 | + 'eth0: link becomes ready') |
44 | unallocated_encoding(s); | 46 | + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2', |
45 | return; | 47 | + '3 packets transmitted, 3 packets received, 0% packet loss') |
46 | } | 48 | |
47 | is_long = true; | 49 | def do_test_arm_raspi2(self, uart_id): |
48 | break; | 50 | """ |
49 | - case 0x3: /* SQDMLAL, SQDMLAL2 */ | ||
50 | - case 0x7: /* SQDMLSL, SQDMLSL2 */ | ||
51 | - case 0xb: /* SQDMULL, SQDMULL2 */ | ||
52 | + case 0x03: /* SQDMLAL, SQDMLAL2 */ | ||
53 | + case 0x07: /* SQDMLSL, SQDMLSL2 */ | ||
54 | + case 0x0b: /* SQDMULL, SQDMULL2 */ | ||
55 | is_long = true; | ||
56 | - /* fall through */ | ||
57 | - case 0xc: /* SQDMULH */ | ||
58 | - case 0xd: /* SQRDMULH */ | ||
59 | - if (u) { | ||
60 | - unallocated_encoding(s); | ||
61 | - return; | ||
62 | - } | ||
63 | break; | ||
64 | - case 0x8: /* MUL */ | ||
65 | - if (u || is_scalar) { | ||
66 | - unallocated_encoding(s); | ||
67 | - return; | ||
68 | - } | ||
69 | + case 0x0c: /* SQDMULH */ | ||
70 | + case 0x0d: /* SQRDMULH */ | ||
71 | break; | ||
72 | - case 0x1: /* FMLA */ | ||
73 | - case 0x5: /* FMLS */ | ||
74 | - if (u) { | ||
75 | - unallocated_encoding(s); | ||
76 | - return; | ||
77 | - } | ||
78 | - /* fall through */ | ||
79 | - case 0x9: /* FMUL, FMULX */ | ||
80 | + case 0x01: /* FMLA */ | ||
81 | + case 0x05: /* FMLS */ | ||
82 | + case 0x09: /* FMUL */ | ||
83 | + case 0x19: /* FMULX */ | ||
84 | if (size == 1) { | ||
85 | unallocated_encoding(s); | ||
86 | return; | ||
87 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
88 | |||
89 | read_vec_element(s, tcg_op, rn, pass, MO_64); | ||
90 | |||
91 | - switch (opcode) { | ||
92 | - case 0x5: /* FMLS */ | ||
93 | + switch (16 * u + opcode) { | ||
94 | + case 0x05: /* FMLS */ | ||
95 | /* As usual for ARM, separate negation for fused multiply-add */ | ||
96 | gen_helper_vfp_negd(tcg_op, tcg_op); | ||
97 | /* fall through */ | ||
98 | - case 0x1: /* FMLA */ | ||
99 | + case 0x01: /* FMLA */ | ||
100 | read_vec_element(s, tcg_res, rd, pass, MO_64); | ||
101 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | ||
102 | break; | ||
103 | - case 0x9: /* FMUL, FMULX */ | ||
104 | - if (u) { | ||
105 | - gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
106 | - } else { | ||
107 | - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
108 | - } | ||
109 | + case 0x09: /* FMUL */ | ||
110 | + gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
111 | + break; | ||
112 | + case 0x19: /* FMULX */ | ||
113 | + gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
114 | break; | ||
115 | default: | ||
116 | g_assert_not_reached(); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
118 | |||
119 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); | ||
120 | |||
121 | - switch (opcode) { | ||
122 | - case 0x0: /* MLA */ | ||
123 | - case 0x4: /* MLS */ | ||
124 | - case 0x8: /* MUL */ | ||
125 | + switch (16 * u + opcode) { | ||
126 | + case 0x08: /* MUL */ | ||
127 | + case 0x10: /* MLA */ | ||
128 | + case 0x14: /* MLS */ | ||
129 | { | ||
130 | static NeonGenTwoOpFn * const fns[2][2] = { | ||
131 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | ||
132 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
133 | genfn(tcg_res, tcg_op, tcg_res); | ||
134 | break; | ||
135 | } | ||
136 | - case 0x5: /* FMLS */ | ||
137 | - case 0x1: /* FMLA */ | ||
138 | + case 0x05: /* FMLS */ | ||
139 | + case 0x01: /* FMLA */ | ||
140 | read_vec_element_i32(s, tcg_res, rd, pass, | ||
141 | is_scalar ? size : MO_32); | ||
142 | switch (size) { | ||
143 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
144 | g_assert_not_reached(); | ||
145 | } | ||
146 | break; | ||
147 | - case 0x9: /* FMUL, FMULX */ | ||
148 | + case 0x09: /* FMUL */ | ||
149 | switch (size) { | ||
150 | case 1: | ||
151 | - if (u) { | ||
152 | - if (is_scalar) { | ||
153 | - gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
154 | - tcg_idx, fpst); | ||
155 | - } else { | ||
156 | - gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
157 | - tcg_idx, fpst); | ||
158 | - } | ||
159 | + if (is_scalar) { | ||
160 | + gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
161 | + tcg_idx, fpst); | ||
162 | } else { | ||
163 | - if (is_scalar) { | ||
164 | - gen_helper_advsimd_mulh(tcg_res, tcg_op, | ||
165 | - tcg_idx, fpst); | ||
166 | - } else { | ||
167 | - gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
168 | - tcg_idx, fpst); | ||
169 | - } | ||
170 | + gen_helper_advsimd_mul2h(tcg_res, tcg_op, | ||
171 | + tcg_idx, fpst); | ||
172 | } | ||
173 | break; | ||
174 | case 2: | ||
175 | - if (u) { | ||
176 | - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
177 | - } else { | ||
178 | - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
179 | - } | ||
180 | + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | ||
181 | break; | ||
182 | default: | ||
183 | g_assert_not_reached(); | ||
184 | } | ||
185 | break; | ||
186 | - case 0xc: /* SQDMULH */ | ||
187 | + case 0x19: /* FMULX */ | ||
188 | + switch (size) { | ||
189 | + case 1: | ||
190 | + if (is_scalar) { | ||
191 | + gen_helper_advsimd_mulxh(tcg_res, tcg_op, | ||
192 | + tcg_idx, fpst); | ||
193 | + } else { | ||
194 | + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | ||
195 | + tcg_idx, fpst); | ||
196 | + } | ||
197 | + break; | ||
198 | + case 2: | ||
199 | + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | ||
200 | + break; | ||
201 | + default: | ||
202 | + g_assert_not_reached(); | ||
203 | + } | ||
204 | + break; | ||
205 | + case 0x0c: /* SQDMULH */ | ||
206 | if (size == 1) { | ||
207 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | ||
208 | tcg_op, tcg_idx); | ||
209 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
210 | tcg_op, tcg_idx); | ||
211 | } | ||
212 | break; | ||
213 | - case 0xd: /* SQRDMULH */ | ||
214 | + case 0x0d: /* SQRDMULH */ | ||
215 | if (size == 1) { | ||
216 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | ||
217 | tcg_op, tcg_idx); | ||
218 | -- | 51 | -- |
219 | 2.16.2 | 52 | 2.20.1 |
220 | 53 | ||
221 | 54 | diff view generated by jsdifflib |
1 | In some board or SoC models it is necessary to split a qemu_irq line | 1 | This object may be used to represent a clock inside a clock tree. |
---|---|---|---|
2 | so that one input can feed multiple outputs. We currently have | 2 | |
3 | qemu_irq_split() for this, but that has several deficiencies: | 3 | A clock may be connected to another clock so that it receives update, |
4 | * it can only handle splitting a line into two | 4 | through a callback, whenever the source/parent clock is updated. |
5 | * it unavoidably leaks memory, so it can't be used | 5 | |
6 | in a device that can be deleted | 6 | Although only the root clock of a clock tree controls the values |
7 | 7 | (represented as periods) of all clocks in tree, each clock holds | |
8 | Implement a qdev device that encapsulates splitting of IRQs, with a | 8 | a local state containing the current value so that it can be fetched |
9 | configurable number of outputs. (This is in some ways the inverse of | 9 | independently. It will allows us to fullfill migration requirements |
10 | the TYPE_OR_IRQ device.) | 10 | by migrating each clock independently of others. |
11 | 11 | ||
12 | This is based on the original work of Frederic Konrad. | ||
13 | |||
14 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
17 | Message-id: 20200406135251.157596-2-damien.hedde@greensocs.com | ||
18 | [PMM: Use uint64_t rather than unsigned long long in trace events; | ||
19 | the dtrace backend can't handle the latter] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20180220180325.29818-13-peter.maydell@linaro.org | ||
15 | --- | 21 | --- |
16 | hw/core/Makefile.objs | 1 + | 22 | hw/core/Makefile.objs | 1 + |
17 | include/hw/core/split-irq.h | 57 +++++++++++++++++++++++++++++ | 23 | include/hw/clock.h | 216 ++++++++++++++++++++++++++++++++++++++++++ |
18 | include/hw/irq.h | 4 +- | 24 | hw/core/clock.c | 130 +++++++++++++++++++++++++ |
19 | hw/core/split-irq.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ | 25 | hw/core/trace-events | 7 ++ |
20 | 4 files changed, 150 insertions(+), 1 deletion(-) | 26 | 4 files changed, 354 insertions(+) |
21 | create mode 100644 include/hw/core/split-irq.h | 27 | create mode 100644 include/hw/clock.h |
22 | create mode 100644 hw/core/split-irq.c | 28 | create mode 100644 hw/core/clock.c |
23 | 29 | ||
24 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | 30 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs |
25 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/hw/core/Makefile.objs | 32 | --- a/hw/core/Makefile.objs |
27 | +++ b/hw/core/Makefile.objs | 33 | +++ b/hw/core/Makefile.objs |
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_FITLOADER) += loader-fit.o | 34 | @@ -XXX,XX +XXX,XX @@ common-obj-y += hotplug.o |
29 | common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o | 35 | common-obj-y += vmstate-if.o |
30 | common-obj-$(CONFIG_SOFTMMU) += register.o | 36 | # irq.o needed for qdev GPIO handling: |
31 | common-obj-$(CONFIG_SOFTMMU) += or-irq.o | 37 | common-obj-y += irq.o |
32 | +common-obj-$(CONFIG_SOFTMMU) += split-irq.o | 38 | +common-obj-y += clock.o |
33 | common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o | 39 | |
34 | 40 | common-obj-$(CONFIG_SOFTMMU) += reset.o | |
35 | obj-$(CONFIG_SOFTMMU) += generic-loader.o | 41 | common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o |
36 | diff --git a/include/hw/core/split-irq.h b/include/hw/core/split-irq.h | 42 | diff --git a/include/hw/clock.h b/include/hw/clock.h |
37 | new file mode 100644 | 43 | new file mode 100644 |
38 | index XXXXXXX..XXXXXXX | 44 | index XXXXXXX..XXXXXXX |
39 | --- /dev/null | 45 | --- /dev/null |
40 | +++ b/include/hw/core/split-irq.h | 46 | +++ b/include/hw/clock.h |
41 | @@ -XXX,XX +XXX,XX @@ | 47 | @@ -XXX,XX +XXX,XX @@ |
42 | +/* | 48 | +/* |
43 | + * IRQ splitter device. | 49 | + * Hardware Clocks |
44 | + * | 50 | + * |
45 | + * Copyright (c) 2018 Linaro Limited. | 51 | + * Copyright GreenSocs 2016-2020 |
46 | + * Written by Peter Maydell | 52 | + * |
47 | + * | 53 | + * Authors: |
48 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 54 | + * Frederic Konrad |
49 | + * of this software and associated documentation files (the "Software"), to deal | 55 | + * Damien Hedde |
50 | + * in the Software without restriction, including without limitation the rights | 56 | + * |
51 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 57 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
52 | + * copies of the Software, and to permit persons to whom the Software is | 58 | + * See the COPYING file in the top-level directory. |
53 | + * furnished to do so, subject to the following conditions: | 59 | + */ |
54 | + * | 60 | + |
55 | + * The above copyright notice and this permission notice shall be included in | 61 | +#ifndef QEMU_HW_CLOCK_H |
56 | + * all copies or substantial portions of the Software. | 62 | +#define QEMU_HW_CLOCK_H |
57 | + * | 63 | + |
58 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
59 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
60 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
61 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
62 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
63 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
64 | + * THE SOFTWARE. | ||
65 | + */ | ||
66 | + | ||
67 | +/* This is a simple device which has one GPIO input line and multiple | ||
68 | + * GPIO output lines. Any change on the input line is forwarded to all | ||
69 | + * of the outputs. | ||
70 | + * | ||
71 | + * QEMU interface: | ||
72 | + * + one unnamed GPIO input: the input line | ||
73 | + * + N unnamed GPIO outputs: the output lines | ||
74 | + * + QOM property "num-lines": sets the number of output lines | ||
75 | + */ | ||
76 | +#ifndef HW_SPLIT_IRQ_H | ||
77 | +#define HW_SPLIT_IRQ_H | ||
78 | + | ||
79 | +#include "hw/irq.h" | ||
80 | +#include "hw/sysbus.h" | ||
81 | +#include "qom/object.h" | 64 | +#include "qom/object.h" |
82 | + | 65 | +#include "qemu/queue.h" |
83 | +#define TYPE_SPLIT_IRQ "split-irq" | 66 | + |
84 | + | 67 | +#define TYPE_CLOCK "clock" |
85 | +#define MAX_SPLIT_LINES 16 | 68 | +#define CLOCK(obj) OBJECT_CHECK(Clock, (obj), TYPE_CLOCK) |
86 | + | 69 | + |
87 | +typedef struct SplitIRQ SplitIRQ; | 70 | +typedef void ClockCallback(void *opaque); |
88 | + | 71 | + |
89 | +#define SPLIT_IRQ(obj) OBJECT_CHECK(SplitIRQ, (obj), TYPE_SPLIT_IRQ) | 72 | +/* |
90 | + | 73 | + * clock store a value representing the clock's period in 2^-32ns unit. |
91 | +struct SplitIRQ { | 74 | + * It can represent: |
92 | + DeviceState parent_obj; | 75 | + * + periods from 2^-32ns up to 4seconds |
93 | + | 76 | + * + frequency from ~0.25Hz 2e10Ghz |
94 | + qemu_irq out_irq[MAX_SPLIT_LINES]; | 77 | + * Resolution of frequency representation decreases with frequency: |
95 | + uint16_t num_lines; | 78 | + * + at 100MHz, resolution is ~2mHz |
79 | + * + at 1Ghz, resolution is ~0.2Hz | ||
80 | + * + at 10Ghz, resolution is ~20Hz | ||
81 | + */ | ||
82 | +#define CLOCK_SECOND (1000000000llu << 32) | ||
83 | + | ||
84 | +/* | ||
85 | + * macro helpers to convert to hertz / nanosecond | ||
86 | + */ | ||
87 | +#define CLOCK_PERIOD_FROM_NS(ns) ((ns) * (CLOCK_SECOND / 1000000000llu)) | ||
88 | +#define CLOCK_PERIOD_TO_NS(per) ((per) / (CLOCK_SECOND / 1000000000llu)) | ||
89 | +#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_SECOND / (hz) : 0u) | ||
90 | +#define CLOCK_PERIOD_TO_HZ(per) (((per) != 0) ? CLOCK_SECOND / (per) : 0u) | ||
91 | + | ||
92 | +/** | ||
93 | + * Clock: | ||
94 | + * @parent_obj: parent class | ||
95 | + * @period: unsigned integer representing the period of the clock | ||
96 | + * @canonical_path: clock path string cache (used for trace purpose) | ||
97 | + * @callback: called when clock changes | ||
98 | + * @callback_opaque: argument for @callback | ||
99 | + * @source: source (or parent in clock tree) of the clock | ||
100 | + * @children: list of clocks connected to this one (it is their source) | ||
101 | + * @sibling: structure used to form a clock list | ||
102 | + */ | ||
103 | + | ||
104 | +typedef struct Clock Clock; | ||
105 | + | ||
106 | +struct Clock { | ||
107 | + /*< private >*/ | ||
108 | + Object parent_obj; | ||
109 | + | ||
110 | + /* all fields are private and should not be modified directly */ | ||
111 | + | ||
112 | + /* fields */ | ||
113 | + uint64_t period; | ||
114 | + char *canonical_path; | ||
115 | + ClockCallback *callback; | ||
116 | + void *callback_opaque; | ||
117 | + | ||
118 | + /* Clocks are organized in a clock tree */ | ||
119 | + Clock *source; | ||
120 | + QLIST_HEAD(, Clock) children; | ||
121 | + QLIST_ENTRY(Clock) sibling; | ||
96 | +}; | 122 | +}; |
97 | + | 123 | + |
98 | +#endif | 124 | +/** |
99 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 125 | + * clock_setup_canonical_path: |
100 | index XXXXXXX..XXXXXXX 100644 | 126 | + * @clk: clock |
101 | --- a/include/hw/irq.h | 127 | + * |
102 | +++ b/include/hw/irq.h | 128 | + * compute the canonical path of the clock (used by log messages) |
103 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | 129 | + */ |
104 | /* Returns a new IRQ with opposite polarity. */ | 130 | +void clock_setup_canonical_path(Clock *clk); |
105 | qemu_irq qemu_irq_invert(qemu_irq irq); | 131 | + |
106 | 132 | +/** | |
107 | -/* Returns a new IRQ which feeds into both the passed IRQs */ | 133 | + * clock_set_callback: |
108 | +/* Returns a new IRQ which feeds into both the passed IRQs. | 134 | + * @clk: the clock to register the callback into |
109 | + * It's probably better to use the TYPE_SPLIT_IRQ device instead. | 135 | + * @cb: the callback function |
110 | + */ | 136 | + * @opaque: the argument to the callback |
111 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | 137 | + * |
112 | 138 | + * Register a callback called on every clock update. | |
113 | /* Returns a new IRQ set which connects 1:1 to another IRQ set, which | 139 | + */ |
114 | diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c | 140 | +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque); |
141 | + | ||
142 | +/** | ||
143 | + * clock_clear_callback: | ||
144 | + * @clk: the clock to delete the callback from | ||
145 | + * | ||
146 | + * Unregister the callback registered with clock_set_callback. | ||
147 | + */ | ||
148 | +void clock_clear_callback(Clock *clk); | ||
149 | + | ||
150 | +/** | ||
151 | + * clock_set_source: | ||
152 | + * @clk: the clock. | ||
153 | + * @src: the source clock | ||
154 | + * | ||
155 | + * Setup @src as the clock source of @clk. The current @src period | ||
156 | + * value is also copied to @clk and its subtree but no callback is | ||
157 | + * called. | ||
158 | + * Further @src update will be propagated to @clk and its subtree. | ||
159 | + */ | ||
160 | +void clock_set_source(Clock *clk, Clock *src); | ||
161 | + | ||
162 | +/** | ||
163 | + * clock_set: | ||
164 | + * @clk: the clock to initialize. | ||
165 | + * @value: the clock's value, 0 means unclocked | ||
166 | + * | ||
167 | + * Set the local cached period value of @clk to @value. | ||
168 | + */ | ||
169 | +void clock_set(Clock *clk, uint64_t value); | ||
170 | + | ||
171 | +static inline void clock_set_hz(Clock *clk, unsigned hz) | ||
172 | +{ | ||
173 | + clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz)); | ||
174 | +} | ||
175 | + | ||
176 | +static inline void clock_set_ns(Clock *clk, unsigned ns) | ||
177 | +{ | ||
178 | + clock_set(clk, CLOCK_PERIOD_FROM_NS(ns)); | ||
179 | +} | ||
180 | + | ||
181 | +/** | ||
182 | + * clock_propagate: | ||
183 | + * @clk: the clock | ||
184 | + * | ||
185 | + * Propagate the clock period that has been previously configured using | ||
186 | + * @clock_set(). This will update recursively all connected clocks. | ||
187 | + * It is an error to call this function on a clock which has a source. | ||
188 | + * Note: this function must not be called during device inititialization | ||
189 | + * or migration. | ||
190 | + */ | ||
191 | +void clock_propagate(Clock *clk); | ||
192 | + | ||
193 | +/** | ||
194 | + * clock_update: | ||
195 | + * @clk: the clock to update. | ||
196 | + * @value: the new clock's value, 0 means unclocked | ||
197 | + * | ||
198 | + * Update the @clk to the new @value. All connected clocks will be informed | ||
199 | + * of this update. This is equivalent to call @clock_set() then | ||
200 | + * @clock_propagate(). | ||
201 | + */ | ||
202 | +static inline void clock_update(Clock *clk, uint64_t value) | ||
203 | +{ | ||
204 | + clock_set(clk, value); | ||
205 | + clock_propagate(clk); | ||
206 | +} | ||
207 | + | ||
208 | +static inline void clock_update_hz(Clock *clk, unsigned hz) | ||
209 | +{ | ||
210 | + clock_update(clk, CLOCK_PERIOD_FROM_HZ(hz)); | ||
211 | +} | ||
212 | + | ||
213 | +static inline void clock_update_ns(Clock *clk, unsigned ns) | ||
214 | +{ | ||
215 | + clock_update(clk, CLOCK_PERIOD_FROM_NS(ns)); | ||
216 | +} | ||
217 | + | ||
218 | +/** | ||
219 | + * clock_get: | ||
220 | + * @clk: the clk to fetch the clock | ||
221 | + * | ||
222 | + * @return: the current period. | ||
223 | + */ | ||
224 | +static inline uint64_t clock_get(const Clock *clk) | ||
225 | +{ | ||
226 | + return clk->period; | ||
227 | +} | ||
228 | + | ||
229 | +static inline unsigned clock_get_hz(Clock *clk) | ||
230 | +{ | ||
231 | + return CLOCK_PERIOD_TO_HZ(clock_get(clk)); | ||
232 | +} | ||
233 | + | ||
234 | +static inline unsigned clock_get_ns(Clock *clk) | ||
235 | +{ | ||
236 | + return CLOCK_PERIOD_TO_NS(clock_get(clk)); | ||
237 | +} | ||
238 | + | ||
239 | +/** | ||
240 | + * clock_is_enabled: | ||
241 | + * @clk: a clock | ||
242 | + * | ||
243 | + * @return: true if the clock is running. | ||
244 | + */ | ||
245 | +static inline bool clock_is_enabled(const Clock *clk) | ||
246 | +{ | ||
247 | + return clock_get(clk) != 0; | ||
248 | +} | ||
249 | + | ||
250 | +static inline void clock_init(Clock *clk, uint64_t value) | ||
251 | +{ | ||
252 | + clock_set(clk, value); | ||
253 | +} | ||
254 | +static inline void clock_init_hz(Clock *clk, uint64_t value) | ||
255 | +{ | ||
256 | + clock_set_hz(clk, value); | ||
257 | +} | ||
258 | +static inline void clock_init_ns(Clock *clk, uint64_t value) | ||
259 | +{ | ||
260 | + clock_set_ns(clk, value); | ||
261 | +} | ||
262 | + | ||
263 | +#endif /* QEMU_HW_CLOCK_H */ | ||
264 | diff --git a/hw/core/clock.c b/hw/core/clock.c | ||
115 | new file mode 100644 | 265 | new file mode 100644 |
116 | index XXXXXXX..XXXXXXX | 266 | index XXXXXXX..XXXXXXX |
117 | --- /dev/null | 267 | --- /dev/null |
118 | +++ b/hw/core/split-irq.c | 268 | +++ b/hw/core/clock.c |
119 | @@ -XXX,XX +XXX,XX @@ | 269 | @@ -XXX,XX +XXX,XX @@ |
120 | +/* | 270 | +/* |
121 | + * IRQ splitter device. | 271 | + * Hardware Clocks |
122 | + * | 272 | + * |
123 | + * Copyright (c) 2018 Linaro Limited. | 273 | + * Copyright GreenSocs 2016-2020 |
124 | + * Written by Peter Maydell | 274 | + * |
125 | + * | 275 | + * Authors: |
126 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 276 | + * Frederic Konrad |
127 | + * of this software and associated documentation files (the "Software"), to deal | 277 | + * Damien Hedde |
128 | + * in the Software without restriction, including without limitation the rights | 278 | + * |
129 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 279 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
130 | + * copies of the Software, and to permit persons to whom the Software is | 280 | + * See the COPYING file in the top-level directory. |
131 | + * furnished to do so, subject to the following conditions: | ||
132 | + * | ||
133 | + * The above copyright notice and this permission notice shall be included in | ||
134 | + * all copies or substantial portions of the Software. | ||
135 | + * | ||
136 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
137 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
138 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
139 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
140 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
141 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
142 | + * THE SOFTWARE. | ||
143 | + */ | 281 | + */ |
144 | + | 282 | + |
145 | +#include "qemu/osdep.h" | 283 | +#include "qemu/osdep.h" |
146 | +#include "hw/core/split-irq.h" | 284 | +#include "hw/clock.h" |
147 | +#include "qapi/error.h" | 285 | +#include "trace.h" |
148 | + | 286 | + |
149 | +static void split_irq_handler(void *opaque, int n, int level) | 287 | +#define CLOCK_PATH(_clk) (_clk->canonical_path) |
150 | +{ | 288 | + |
151 | + SplitIRQ *s = SPLIT_IRQ(opaque); | 289 | +void clock_setup_canonical_path(Clock *clk) |
152 | + int i; | 290 | +{ |
153 | + | 291 | + g_free(clk->canonical_path); |
154 | + for (i = 0; i < s->num_lines; i++) { | 292 | + clk->canonical_path = object_get_canonical_path(OBJECT(clk)); |
155 | + qemu_set_irq(s->out_irq[i], level); | 293 | +} |
294 | + | ||
295 | +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque) | ||
296 | +{ | ||
297 | + clk->callback = cb; | ||
298 | + clk->callback_opaque = opaque; | ||
299 | +} | ||
300 | + | ||
301 | +void clock_clear_callback(Clock *clk) | ||
302 | +{ | ||
303 | + clock_set_callback(clk, NULL, NULL); | ||
304 | +} | ||
305 | + | ||
306 | +void clock_set(Clock *clk, uint64_t period) | ||
307 | +{ | ||
308 | + trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period), | ||
309 | + CLOCK_PERIOD_TO_NS(period)); | ||
310 | + clk->period = period; | ||
311 | +} | ||
312 | + | ||
313 | +static void clock_propagate_period(Clock *clk, bool call_callbacks) | ||
314 | +{ | ||
315 | + Clock *child; | ||
316 | + | ||
317 | + QLIST_FOREACH(child, &clk->children, sibling) { | ||
318 | + if (child->period != clk->period) { | ||
319 | + child->period = clk->period; | ||
320 | + trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), | ||
321 | + CLOCK_PERIOD_TO_NS(clk->period), | ||
322 | + call_callbacks); | ||
323 | + if (call_callbacks && child->callback) { | ||
324 | + child->callback(child->callback_opaque); | ||
325 | + } | ||
326 | + clock_propagate_period(child, call_callbacks); | ||
327 | + } | ||
156 | + } | 328 | + } |
157 | +} | 329 | +} |
158 | + | 330 | + |
159 | +static void split_irq_init(Object *obj) | 331 | +void clock_propagate(Clock *clk) |
160 | +{ | 332 | +{ |
161 | + qdev_init_gpio_in(DEVICE(obj), split_irq_handler, 1); | 333 | + assert(clk->source == NULL); |
162 | +} | 334 | + trace_clock_propagate(CLOCK_PATH(clk)); |
163 | + | 335 | + clock_propagate_period(clk, true); |
164 | +static void split_irq_realize(DeviceState *dev, Error **errp) | 336 | +} |
165 | +{ | 337 | + |
166 | + SplitIRQ *s = SPLIT_IRQ(dev); | 338 | +void clock_set_source(Clock *clk, Clock *src) |
167 | + | 339 | +{ |
168 | + if (s->num_lines < 1 || s->num_lines >= MAX_SPLIT_LINES) { | 340 | + /* changing clock source is not supported */ |
169 | + error_setg(errp, | 341 | + assert(!clk->source); |
170 | + "IRQ splitter number of lines %d is not between 1 and %d", | 342 | + |
171 | + s->num_lines, MAX_SPLIT_LINES); | 343 | + trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src)); |
344 | + | ||
345 | + clk->period = src->period; | ||
346 | + QLIST_INSERT_HEAD(&src->children, clk, sibling); | ||
347 | + clk->source = src; | ||
348 | + clock_propagate_period(clk, false); | ||
349 | +} | ||
350 | + | ||
351 | +static void clock_disconnect(Clock *clk) | ||
352 | +{ | ||
353 | + if (clk->source == NULL) { | ||
172 | + return; | 354 | + return; |
173 | + } | 355 | + } |
174 | + | 356 | + |
175 | + qdev_init_gpio_out(dev, s->out_irq, s->num_lines); | 357 | + trace_clock_disconnect(CLOCK_PATH(clk)); |
176 | +} | 358 | + |
177 | + | 359 | + clk->source = NULL; |
178 | +static Property split_irq_properties[] = { | 360 | + QLIST_REMOVE(clk, sibling); |
179 | + DEFINE_PROP_UINT16("num-lines", SplitIRQ, num_lines, 1), | 361 | +} |
180 | + DEFINE_PROP_END_OF_LIST(), | 362 | + |
363 | +static void clock_initfn(Object *obj) | ||
364 | +{ | ||
365 | + Clock *clk = CLOCK(obj); | ||
366 | + | ||
367 | + QLIST_INIT(&clk->children); | ||
368 | +} | ||
369 | + | ||
370 | +static void clock_finalizefn(Object *obj) | ||
371 | +{ | ||
372 | + Clock *clk = CLOCK(obj); | ||
373 | + Clock *child, *next; | ||
374 | + | ||
375 | + /* clear our list of children */ | ||
376 | + QLIST_FOREACH_SAFE(child, &clk->children, sibling, next) { | ||
377 | + clock_disconnect(child); | ||
378 | + } | ||
379 | + | ||
380 | + /* remove us from source's children list */ | ||
381 | + clock_disconnect(clk); | ||
382 | + | ||
383 | + g_free(clk->canonical_path); | ||
384 | +} | ||
385 | + | ||
386 | +static const TypeInfo clock_info = { | ||
387 | + .name = TYPE_CLOCK, | ||
388 | + .parent = TYPE_OBJECT, | ||
389 | + .instance_size = sizeof(Clock), | ||
390 | + .instance_init = clock_initfn, | ||
391 | + .instance_finalize = clock_finalizefn, | ||
181 | +}; | 392 | +}; |
182 | + | 393 | + |
183 | +static void split_irq_class_init(ObjectClass *klass, void *data) | 394 | +static void clock_register_types(void) |
184 | +{ | 395 | +{ |
185 | + DeviceClass *dc = DEVICE_CLASS(klass); | 396 | + type_register_static(&clock_info); |
186 | + | 397 | +} |
187 | + /* No state to reset or migrate */ | 398 | + |
188 | + dc->props = split_irq_properties; | 399 | +type_init(clock_register_types) |
189 | + dc->realize = split_irq_realize; | 400 | diff --git a/hw/core/trace-events b/hw/core/trace-events |
190 | + | 401 | index XXXXXXX..XXXXXXX 100644 |
191 | + /* Reason: Needs to be wired up to work */ | 402 | --- a/hw/core/trace-events |
192 | + dc->user_creatable = false; | 403 | +++ b/hw/core/trace-events |
193 | +} | 404 | @@ -XXX,XX +XXX,XX @@ resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int |
194 | + | 405 | resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" |
195 | +static const TypeInfo split_irq_type_info = { | 406 | resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" |
196 | + .name = TYPE_SPLIT_IRQ, | 407 | resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)" |
197 | + .parent = TYPE_DEVICE, | 408 | + |
198 | + .instance_size = sizeof(SplitIRQ), | 409 | +# clock.c |
199 | + .instance_init = split_irq_init, | 410 | +clock_set_source(const char *clk, const char *src) "'%s', src='%s'" |
200 | + .class_init = split_irq_class_init, | 411 | +clock_disconnect(const char *clk) "'%s'" |
201 | +}; | 412 | +clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64 |
202 | + | 413 | +clock_propagate(const char *clk) "'%s'" |
203 | +static void split_irq_register_types(void) | 414 | +clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d" |
204 | +{ | ||
205 | + type_register_static(&split_irq_type_info); | ||
206 | +} | ||
207 | + | ||
208 | +type_init(split_irq_register_types) | ||
209 | -- | 415 | -- |
210 | 2.16.2 | 416 | 2.20.1 |
211 | 417 | ||
212 | 418 | diff view generated by jsdifflib |
1 | Add a model of the TrustZone peripheral protection controller (PPC), | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | which is used to gate transactions to non-TZ-aware peripherals so | ||
3 | that secure software can configure them to not be accessible to | ||
4 | non-secure software. | ||
5 | 2 | ||
3 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
8 | Message-id: 20200406135251.157596-3-damien.hedde@greensocs.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-15-peter.maydell@linaro.org | ||
9 | --- | 10 | --- |
10 | hw/misc/Makefile.objs | 2 + | 11 | hw/core/Makefile.objs | 1 + |
11 | include/hw/misc/tz-ppc.h | 101 ++++++++++++++ | 12 | include/hw/clock.h | 9 +++++++++ |
12 | hw/misc/tz-ppc.c | 302 ++++++++++++++++++++++++++++++++++++++++ | 13 | hw/core/clock-vmstate.c | 25 +++++++++++++++++++++++++ |
13 | default-configs/arm-softmmu.mak | 2 + | 14 | 3 files changed, 35 insertions(+) |
14 | hw/misc/trace-events | 11 ++ | 15 | create mode 100644 hw/core/clock-vmstate.c |
15 | 5 files changed, 418 insertions(+) | ||
16 | create mode 100644 include/hw/misc/tz-ppc.h | ||
17 | create mode 100644 hw/misc/tz-ppc.c | ||
18 | 16 | ||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 17 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs |
20 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/Makefile.objs | 19 | --- a/hw/core/Makefile.objs |
22 | +++ b/hw/misc/Makefile.objs | 20 | +++ b/hw/core/Makefile.objs |
23 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 21 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SOFTMMU) += null-machine.o |
24 | obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 22 | common-obj-$(CONFIG_SOFTMMU) += loader.o |
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 23 | common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o |
26 | 24 | common-obj-$(CONFIG_SOFTMMU) += numa.o | |
27 | +obj-$(CONFIG_TZ_PPC) += tz-ppc.o | 25 | +common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o |
26 | obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o | ||
27 | |||
28 | common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o | ||
29 | diff --git a/include/hw/clock.h b/include/hw/clock.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/include/hw/clock.h | ||
32 | +++ b/include/hw/clock.h | ||
33 | @@ -XXX,XX +XXX,XX @@ struct Clock { | ||
34 | QLIST_ENTRY(Clock) sibling; | ||
35 | }; | ||
36 | |||
37 | +/* | ||
38 | + * vmstate description entry to be added in device vmsd. | ||
39 | + */ | ||
40 | +extern const VMStateDescription vmstate_clock; | ||
41 | +#define VMSTATE_CLOCK(field, state) \ | ||
42 | + VMSTATE_CLOCK_V(field, state, 0) | ||
43 | +#define VMSTATE_CLOCK_V(field, state, version) \ | ||
44 | + VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock) | ||
28 | + | 45 | + |
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 46 | /** |
30 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | 47 | * clock_setup_canonical_path: |
31 | obj-$(CONFIG_AUX) += auxbus.o | 48 | * @clk: clock |
32 | diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h | 49 | diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c |
33 | new file mode 100644 | 50 | new file mode 100644 |
34 | index XXXXXXX..XXXXXXX | 51 | index XXXXXXX..XXXXXXX |
35 | --- /dev/null | 52 | --- /dev/null |
36 | +++ b/include/hw/misc/tz-ppc.h | 53 | +++ b/hw/core/clock-vmstate.c |
37 | @@ -XXX,XX +XXX,XX @@ | 54 | @@ -XXX,XX +XXX,XX @@ |
38 | +/* | 55 | +/* |
39 | + * ARM TrustZone peripheral protection controller emulation | 56 | + * Clock migration structure |
40 | + * | 57 | + * |
41 | + * Copyright (c) 2018 Linaro Limited | 58 | + * Copyright GreenSocs 2019-2020 |
42 | + * Written by Peter Maydell | ||
43 | + * | 59 | + * |
44 | + * This program is free software; you can redistribute it and/or modify | 60 | + * Authors: |
45 | + * it under the terms of the GNU General Public License version 2 or | 61 | + * Damien Hedde |
46 | + * (at your option) any later version. | ||
47 | + */ | ||
48 | + | ||
49 | +/* This is a model of the TrustZone peripheral protection controller (PPC). | ||
50 | + * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM | ||
51 | + * (DDI 0571G): | ||
52 | + * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g | ||
53 | + * | 62 | + * |
54 | + * The PPC sits in front of peripherals and allows secure software to | 63 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
55 | + * configure it to either pass through or reject transactions. | 64 | + * See the COPYING file in the top-level directory. |
56 | + * Rejected transactions may be configured to either be aborted, or to | ||
57 | + * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. | ||
58 | + * | ||
59 | + * The PPC has no register interface -- it is configured purely by a | ||
60 | + * collection of input signals from other hardware in the system. Typically | ||
61 | + * they are either hardwired or exposed in an ad-hoc register interface by | ||
62 | + * the SoC that uses the PPC. | ||
63 | + * | ||
64 | + * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC, | ||
65 | + * since the only difference between them is that the AHB version has a | ||
66 | + * "default" port which has no security checks applied. In QEMU the default | ||
67 | + * port can be emulated simply by wiring its downstream devices directly | ||
68 | + * into the parent address space, since the PPC does not need to intercept | ||
69 | + * transactions there. | ||
70 | + * | ||
71 | + * In the hardware, selection of which downstream port to use is done by | ||
72 | + * the user's decode logic asserting one of the hsel[] signals. In QEMU, | ||
73 | + * we provide 16 MMIO regions, one per port, and the user maps these into | ||
74 | + * the desired addresses to implement the address decode. | ||
75 | + * | ||
76 | + * QEMU interface: | ||
77 | + * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end | ||
78 | + * of each of the 16 ports of the PPC | ||
79 | + * + Property "port[0..15]": MemoryRegion defining the downstream device(s) | ||
80 | + * for each of the 16 ports of the PPC | ||
81 | + * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be | ||
82 | + * accessible to NonSecure transactions | ||
83 | + * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be | ||
84 | + * accessible to non-privileged transactions | ||
85 | + * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should | ||
86 | + * result in a transaction error, or 0 for the transaction to RAZ/WI | ||
87 | + * + Named GPIO input "irq_enable": set to 1 to enable interrupts | ||
88 | + * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt | ||
89 | + * + Named GPIO output "irq": set for a transaction-failed interrupt | ||
90 | + * + Property "NONSEC_MASK": if a bit is set in this mask then accesses to | ||
91 | + * the associated port do not have the TZ security check performed. (This | ||
92 | + * corresponds to the hardware allowing this to be set as a Verilog | ||
93 | + * parameter.) | ||
94 | + */ | ||
95 | + | ||
96 | +#ifndef TZ_PPC_H | ||
97 | +#define TZ_PPC_H | ||
98 | + | ||
99 | +#include "hw/sysbus.h" | ||
100 | + | ||
101 | +#define TYPE_TZ_PPC "tz-ppc" | ||
102 | +#define TZ_PPC(obj) OBJECT_CHECK(TZPPC, (obj), TYPE_TZ_PPC) | ||
103 | + | ||
104 | +#define TZ_NUM_PORTS 16 | ||
105 | + | ||
106 | +typedef struct TZPPC TZPPC; | ||
107 | + | ||
108 | +typedef struct TZPPCPort { | ||
109 | + TZPPC *ppc; | ||
110 | + MemoryRegion upstream; | ||
111 | + AddressSpace downstream_as; | ||
112 | + MemoryRegion *downstream; | ||
113 | +} TZPPCPort; | ||
114 | + | ||
115 | +struct TZPPC { | ||
116 | + /*< private >*/ | ||
117 | + SysBusDevice parent_obj; | ||
118 | + | ||
119 | + /*< public >*/ | ||
120 | + | ||
121 | + /* State: these just track the values of our input signals */ | ||
122 | + bool cfg_nonsec[TZ_NUM_PORTS]; | ||
123 | + bool cfg_ap[TZ_NUM_PORTS]; | ||
124 | + bool cfg_sec_resp; | ||
125 | + bool irq_enable; | ||
126 | + bool irq_clear; | ||
127 | + /* State: are we asserting irq ? */ | ||
128 | + bool irq_status; | ||
129 | + | ||
130 | + qemu_irq irq; | ||
131 | + | ||
132 | + /* Properties */ | ||
133 | + uint32_t nonsec_mask; | ||
134 | + | ||
135 | + TZPPCPort port[TZ_NUM_PORTS]; | ||
136 | +}; | ||
137 | + | ||
138 | +#endif | ||
139 | diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c | ||
140 | new file mode 100644 | ||
141 | index XXXXXXX..XXXXXXX | ||
142 | --- /dev/null | ||
143 | +++ b/hw/misc/tz-ppc.c | ||
144 | @@ -XXX,XX +XXX,XX @@ | ||
145 | +/* | ||
146 | + * ARM TrustZone peripheral protection controller emulation | ||
147 | + * | ||
148 | + * Copyright (c) 2018 Linaro Limited | ||
149 | + * Written by Peter Maydell | ||
150 | + * | ||
151 | + * This program is free software; you can redistribute it and/or modify | ||
152 | + * it under the terms of the GNU General Public License version 2 or | ||
153 | + * (at your option) any later version. | ||
154 | + */ | 65 | + */ |
155 | + | 66 | + |
156 | +#include "qemu/osdep.h" | 67 | +#include "qemu/osdep.h" |
157 | +#include "qemu/log.h" | 68 | +#include "migration/vmstate.h" |
158 | +#include "qapi/error.h" | 69 | +#include "hw/clock.h" |
159 | +#include "trace.h" | ||
160 | +#include "hw/sysbus.h" | ||
161 | +#include "hw/registerfields.h" | ||
162 | +#include "hw/misc/tz-ppc.h" | ||
163 | + | 70 | + |
164 | +static void tz_ppc_update_irq(TZPPC *s) | 71 | +const VMStateDescription vmstate_clock = { |
165 | +{ | 72 | + .name = "clock", |
166 | + bool level = s->irq_status && s->irq_enable; | 73 | + .version_id = 0, |
167 | + | 74 | + .minimum_version_id = 0, |
168 | + trace_tz_ppc_update_irq(level); | ||
169 | + qemu_set_irq(s->irq, level); | ||
170 | +} | ||
171 | + | ||
172 | +static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) | ||
173 | +{ | ||
174 | + TZPPC *s = TZ_PPC(opaque); | ||
175 | + | ||
176 | + assert(n < TZ_NUM_PORTS); | ||
177 | + trace_tz_ppc_cfg_nonsec(n, level); | ||
178 | + s->cfg_nonsec[n] = level; | ||
179 | +} | ||
180 | + | ||
181 | +static void tz_ppc_cfg_ap(void *opaque, int n, int level) | ||
182 | +{ | ||
183 | + TZPPC *s = TZ_PPC(opaque); | ||
184 | + | ||
185 | + assert(n < TZ_NUM_PORTS); | ||
186 | + trace_tz_ppc_cfg_ap(n, level); | ||
187 | + s->cfg_ap[n] = level; | ||
188 | +} | ||
189 | + | ||
190 | +static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) | ||
191 | +{ | ||
192 | + TZPPC *s = TZ_PPC(opaque); | ||
193 | + | ||
194 | + trace_tz_ppc_cfg_sec_resp(level); | ||
195 | + s->cfg_sec_resp = level; | ||
196 | +} | ||
197 | + | ||
198 | +static void tz_ppc_irq_enable(void *opaque, int n, int level) | ||
199 | +{ | ||
200 | + TZPPC *s = TZ_PPC(opaque); | ||
201 | + | ||
202 | + trace_tz_ppc_irq_enable(level); | ||
203 | + s->irq_enable = level; | ||
204 | + tz_ppc_update_irq(s); | ||
205 | +} | ||
206 | + | ||
207 | +static void tz_ppc_irq_clear(void *opaque, int n, int level) | ||
208 | +{ | ||
209 | + TZPPC *s = TZ_PPC(opaque); | ||
210 | + | ||
211 | + trace_tz_ppc_irq_clear(level); | ||
212 | + | ||
213 | + s->irq_clear = level; | ||
214 | + if (level) { | ||
215 | + s->irq_status = false; | ||
216 | + tz_ppc_update_irq(s); | ||
217 | + } | ||
218 | +} | ||
219 | + | ||
220 | +static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) | ||
221 | +{ | ||
222 | + /* Check whether to allow an access to port n; return true if | ||
223 | + * the check passes, and false if the transaction must be blocked. | ||
224 | + * If the latter, the caller must check cfg_sec_resp to determine | ||
225 | + * whether to abort or RAZ/WI the transaction. | ||
226 | + * The checks are: | ||
227 | + * + nonsec_mask suppresses any check of the secure attribute | ||
228 | + * + otherwise, block if cfg_nonsec is 1 and transaction is secure, | ||
229 | + * or if cfg_nonsec is 0 and transaction is non-secure | ||
230 | + * + block if transaction is usermode and cfg_ap is 0 | ||
231 | + */ | ||
232 | + if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || | ||
233 | + (attrs.user && !s->cfg_ap[n])) { | ||
234 | + /* Block the transaction. */ | ||
235 | + if (!s->irq_clear) { | ||
236 | + /* Note that holding irq_clear high suppresses interrupts */ | ||
237 | + s->irq_status = true; | ||
238 | + tz_ppc_update_irq(s); | ||
239 | + } | ||
240 | + return false; | ||
241 | + } | ||
242 | + return true; | ||
243 | +} | ||
244 | + | ||
245 | +static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, | ||
246 | + unsigned size, MemTxAttrs attrs) | ||
247 | +{ | ||
248 | + TZPPCPort *p = opaque; | ||
249 | + TZPPC *s = p->ppc; | ||
250 | + int n = p - s->port; | ||
251 | + AddressSpace *as = &p->downstream_as; | ||
252 | + uint64_t data; | ||
253 | + MemTxResult res; | ||
254 | + | ||
255 | + if (!tz_ppc_check(s, n, attrs)) { | ||
256 | + trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); | ||
257 | + if (s->cfg_sec_resp) { | ||
258 | + return MEMTX_ERROR; | ||
259 | + } else { | ||
260 | + *pdata = 0; | ||
261 | + return MEMTX_OK; | ||
262 | + } | ||
263 | + } | ||
264 | + | ||
265 | + switch (size) { | ||
266 | + case 1: | ||
267 | + data = address_space_ldub(as, addr, attrs, &res); | ||
268 | + break; | ||
269 | + case 2: | ||
270 | + data = address_space_lduw_le(as, addr, attrs, &res); | ||
271 | + break; | ||
272 | + case 4: | ||
273 | + data = address_space_ldl_le(as, addr, attrs, &res); | ||
274 | + break; | ||
275 | + case 8: | ||
276 | + data = address_space_ldq_le(as, addr, attrs, &res); | ||
277 | + break; | ||
278 | + default: | ||
279 | + g_assert_not_reached(); | ||
280 | + } | ||
281 | + *pdata = data; | ||
282 | + return res; | ||
283 | +} | ||
284 | + | ||
285 | +static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, | ||
286 | + unsigned size, MemTxAttrs attrs) | ||
287 | +{ | ||
288 | + TZPPCPort *p = opaque; | ||
289 | + TZPPC *s = p->ppc; | ||
290 | + AddressSpace *as = &p->downstream_as; | ||
291 | + int n = p - s->port; | ||
292 | + MemTxResult res; | ||
293 | + | ||
294 | + if (!tz_ppc_check(s, n, attrs)) { | ||
295 | + trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); | ||
296 | + if (s->cfg_sec_resp) { | ||
297 | + return MEMTX_ERROR; | ||
298 | + } else { | ||
299 | + return MEMTX_OK; | ||
300 | + } | ||
301 | + } | ||
302 | + | ||
303 | + switch (size) { | ||
304 | + case 1: | ||
305 | + address_space_stb(as, addr, val, attrs, &res); | ||
306 | + break; | ||
307 | + case 2: | ||
308 | + address_space_stw_le(as, addr, val, attrs, &res); | ||
309 | + break; | ||
310 | + case 4: | ||
311 | + address_space_stl_le(as, addr, val, attrs, &res); | ||
312 | + break; | ||
313 | + case 8: | ||
314 | + address_space_stq_le(as, addr, val, attrs, &res); | ||
315 | + break; | ||
316 | + default: | ||
317 | + g_assert_not_reached(); | ||
318 | + } | ||
319 | + return res; | ||
320 | +} | ||
321 | + | ||
322 | +static const MemoryRegionOps tz_ppc_ops = { | ||
323 | + .read_with_attrs = tz_ppc_read, | ||
324 | + .write_with_attrs = tz_ppc_write, | ||
325 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
326 | +}; | ||
327 | + | ||
328 | +static void tz_ppc_reset(DeviceState *dev) | ||
329 | +{ | ||
330 | + TZPPC *s = TZ_PPC(dev); | ||
331 | + | ||
332 | + trace_tz_ppc_reset(); | ||
333 | + s->cfg_sec_resp = false; | ||
334 | + memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); | ||
335 | + memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); | ||
336 | +} | ||
337 | + | ||
338 | +static void tz_ppc_init(Object *obj) | ||
339 | +{ | ||
340 | + DeviceState *dev = DEVICE(obj); | ||
341 | + TZPPC *s = TZ_PPC(obj); | ||
342 | + | ||
343 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); | ||
344 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); | ||
345 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); | ||
346 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); | ||
347 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); | ||
348 | + qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); | ||
349 | +} | ||
350 | + | ||
351 | +static void tz_ppc_realize(DeviceState *dev, Error **errp) | ||
352 | +{ | ||
353 | + Object *obj = OBJECT(dev); | ||
354 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
355 | + TZPPC *s = TZ_PPC(dev); | ||
356 | + int i; | ||
357 | + | ||
358 | + /* We can't create the upstream end of the port until realize, | ||
359 | + * as we don't know the size of the MR used as the downstream until then. | ||
360 | + */ | ||
361 | + for (i = 0; i < TZ_NUM_PORTS; i++) { | ||
362 | + TZPPCPort *port = &s->port[i]; | ||
363 | + char *name; | ||
364 | + uint64_t size; | ||
365 | + | ||
366 | + if (!port->downstream) { | ||
367 | + continue; | ||
368 | + } | ||
369 | + | ||
370 | + name = g_strdup_printf("tz-ppc-port[%d]", i); | ||
371 | + | ||
372 | + port->ppc = s; | ||
373 | + address_space_init(&port->downstream_as, port->downstream, name); | ||
374 | + | ||
375 | + size = memory_region_size(port->downstream); | ||
376 | + memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, | ||
377 | + port, name, size); | ||
378 | + sysbus_init_mmio(sbd, &port->upstream); | ||
379 | + g_free(name); | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +static const VMStateDescription tz_ppc_vmstate = { | ||
384 | + .name = "tz-ppc", | ||
385 | + .version_id = 1, | ||
386 | + .minimum_version_id = 1, | ||
387 | + .fields = (VMStateField[]) { | 75 | + .fields = (VMStateField[]) { |
388 | + VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), | 76 | + VMSTATE_UINT64(period, Clock), |
389 | + VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), | ||
390 | + VMSTATE_BOOL(cfg_sec_resp, TZPPC), | ||
391 | + VMSTATE_BOOL(irq_enable, TZPPC), | ||
392 | + VMSTATE_BOOL(irq_clear, TZPPC), | ||
393 | + VMSTATE_BOOL(irq_status, TZPPC), | ||
394 | + VMSTATE_END_OF_LIST() | 77 | + VMSTATE_END_OF_LIST() |
395 | + } | 78 | + } |
396 | +}; | 79 | +}; |
397 | + | ||
398 | +#define DEFINE_PORT(N) \ | ||
399 | + DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ | ||
400 | + TYPE_MEMORY_REGION, MemoryRegion *) | ||
401 | + | ||
402 | +static Property tz_ppc_properties[] = { | ||
403 | + DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), | ||
404 | + DEFINE_PORT(0), | ||
405 | + DEFINE_PORT(1), | ||
406 | + DEFINE_PORT(2), | ||
407 | + DEFINE_PORT(3), | ||
408 | + DEFINE_PORT(4), | ||
409 | + DEFINE_PORT(5), | ||
410 | + DEFINE_PORT(6), | ||
411 | + DEFINE_PORT(7), | ||
412 | + DEFINE_PORT(8), | ||
413 | + DEFINE_PORT(9), | ||
414 | + DEFINE_PORT(10), | ||
415 | + DEFINE_PORT(11), | ||
416 | + DEFINE_PORT(12), | ||
417 | + DEFINE_PORT(13), | ||
418 | + DEFINE_PORT(14), | ||
419 | + DEFINE_PORT(15), | ||
420 | + DEFINE_PROP_END_OF_LIST(), | ||
421 | +}; | ||
422 | + | ||
423 | +static void tz_ppc_class_init(ObjectClass *klass, void *data) | ||
424 | +{ | ||
425 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
426 | + | ||
427 | + dc->realize = tz_ppc_realize; | ||
428 | + dc->vmsd = &tz_ppc_vmstate; | ||
429 | + dc->reset = tz_ppc_reset; | ||
430 | + dc->props = tz_ppc_properties; | ||
431 | +} | ||
432 | + | ||
433 | +static const TypeInfo tz_ppc_info = { | ||
434 | + .name = TYPE_TZ_PPC, | ||
435 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
436 | + .instance_size = sizeof(TZPPC), | ||
437 | + .instance_init = tz_ppc_init, | ||
438 | + .class_init = tz_ppc_class_init, | ||
439 | +}; | ||
440 | + | ||
441 | +static void tz_ppc_register_types(void) | ||
442 | +{ | ||
443 | + type_register_static(&tz_ppc_info); | ||
444 | +} | ||
445 | + | ||
446 | +type_init(tz_ppc_register_types); | ||
447 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
448 | index XXXXXXX..XXXXXXX 100644 | ||
449 | --- a/default-configs/arm-softmmu.mak | ||
450 | +++ b/default-configs/arm-softmmu.mak | ||
451 | @@ -XXX,XX +XXX,XX @@ CONFIG_CMSDK_APB_UART=y | ||
452 | CONFIG_MPS2_FPGAIO=y | ||
453 | CONFIG_MPS2_SCC=y | ||
454 | |||
455 | +CONFIG_TZ_PPC=y | ||
456 | + | ||
457 | CONFIG_VERSATILE_PCI=y | ||
458 | CONFIG_VERSATILE_I2C=y | ||
459 | |||
460 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
461 | index XXXXXXX..XXXXXXX 100644 | ||
462 | --- a/hw/misc/trace-events | ||
463 | +++ b/hw/misc/trace-events | ||
464 | @@ -XXX,XX +XXX,XX @@ mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d co | ||
465 | mos6522_set_sr_int(void) "set sr_int" | ||
466 | mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 | ||
467 | mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" | ||
468 | + | ||
469 | +# hw/misc/tz-ppc.c | ||
470 | +tz_ppc_reset(void) "TZ PPC: reset" | ||
471 | +tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" | ||
472 | +tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" | ||
473 | +tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" | ||
474 | +tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" | ||
475 | +tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
476 | +tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
477 | +tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
478 | +tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
479 | -- | 80 | -- |
480 | 2.16.2 | 81 | 2.20.1 |
481 | 82 | ||
482 | 83 | diff view generated by jsdifflib |
1 | The MPS2 AN505 FPGA image includes a "FPGA control block" | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | which is a small set of registers handling LEDs, buttons | 2 | |
3 | and some counters. | 3 | Add functions to easily handle clocks with devices. |
4 | 4 | Clock inputs and outputs should be used to handle clock propagation | |
5 | between devices. | ||
6 | The API is very similar the GPIO API. | ||
7 | |||
8 | This is based on the original work of Frederic Konrad. | ||
9 | |||
10 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
11 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-id: 20200406135251.157596-4-damien.hedde@greensocs.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-14-peter.maydell@linaro.org | ||
8 | --- | 15 | --- |
9 | hw/misc/Makefile.objs | 1 + | 16 | hw/core/Makefile.objs | 2 +- |
10 | include/hw/misc/mps2-fpgaio.h | 43 ++++++++++ | 17 | tests/Makefile.include | 1 + |
11 | hw/misc/mps2-fpgaio.c | 176 ++++++++++++++++++++++++++++++++++++++++ | 18 | include/hw/qdev-clock.h | 104 +++++++++++++++++++++++++ |
12 | default-configs/arm-softmmu.mak | 1 + | 19 | include/hw/qdev-core.h | 12 +++ |
13 | hw/misc/trace-events | 6 ++ | 20 | hw/core/qdev-clock.c | 168 ++++++++++++++++++++++++++++++++++++++++ |
14 | 5 files changed, 227 insertions(+) | 21 | hw/core/qdev.c | 12 +++ |
15 | create mode 100644 include/hw/misc/mps2-fpgaio.h | 22 | 6 files changed, 298 insertions(+), 1 deletion(-) |
16 | create mode 100644 hw/misc/mps2-fpgaio.c | 23 | create mode 100644 include/hw/qdev-clock.h |
17 | 24 | create mode 100644 hw/core/qdev-clock.c | |
18 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 25 | |
26 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | ||
19 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/misc/Makefile.objs | 28 | --- a/hw/core/Makefile.objs |
21 | +++ b/hw/misc/Makefile.objs | 29 | +++ b/hw/core/Makefile.objs |
22 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | 30 | @@ -XXX,XX +XXX,XX @@ common-obj-y += hotplug.o |
23 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | 31 | common-obj-y += vmstate-if.o |
24 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | 32 | # irq.o needed for qdev GPIO handling: |
25 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | 33 | common-obj-y += irq.o |
26 | +obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | 34 | -common-obj-y += clock.o |
27 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | 35 | +common-obj-y += clock.o qdev-clock.o |
28 | 36 | ||
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | 37 | common-obj-$(CONFIG_SOFTMMU) += reset.o |
30 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h | 38 | common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o |
39 | diff --git a/tests/Makefile.include b/tests/Makefile.include | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/tests/Makefile.include | ||
42 | +++ b/tests/Makefile.include | ||
43 | @@ -XXX,XX +XXX,XX @@ tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ | ||
44 | hw/core/fw-path-provider.o \ | ||
45 | hw/core/reset.o \ | ||
46 | hw/core/vmstate-if.o \ | ||
47 | + hw/core/clock.o hw/core/qdev-clock.o \ | ||
48 | $(test-qapi-obj-y) | ||
49 | tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ | ||
50 | migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \ | ||
51 | diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h | ||
31 | new file mode 100644 | 52 | new file mode 100644 |
32 | index XXXXXXX..XXXXXXX | 53 | index XXXXXXX..XXXXXXX |
33 | --- /dev/null | 54 | --- /dev/null |
34 | +++ b/include/hw/misc/mps2-fpgaio.h | 55 | +++ b/include/hw/qdev-clock.h |
35 | @@ -XXX,XX +XXX,XX @@ | 56 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 57 | +/* |
37 | + * ARM MPS2 FPGAIO emulation | 58 | + * Device's clock input and output |
38 | + * | 59 | + * |
39 | + * Copyright (c) 2018 Linaro Limited | 60 | + * Copyright GreenSocs 2016-2020 |
40 | + * Written by Peter Maydell | 61 | + * |
41 | + * | 62 | + * Authors: |
42 | + * This program is free software; you can redistribute it and/or modify | 63 | + * Frederic Konrad |
43 | + * it under the terms of the GNU General Public License version 2 or | 64 | + * Damien Hedde |
44 | + * (at your option) any later version. | 65 | + * |
45 | + */ | 66 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
46 | + | 67 | + * See the COPYING file in the top-level directory. |
47 | +/* This is a model of the FPGAIO register block in the AN505 | 68 | + */ |
48 | + * FPGA image for the MPS2 dev board; it is documented in the | 69 | + |
49 | + * application note: | 70 | +#ifndef QDEV_CLOCK_H |
50 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | 71 | +#define QDEV_CLOCK_H |
51 | + * | 72 | + |
52 | + * QEMU interface: | 73 | +#include "hw/clock.h" |
53 | + * + sysbus MMIO region 0: the register bank | 74 | + |
54 | + */ | 75 | +/** |
55 | + | 76 | + * qdev_init_clock_in: |
56 | +#ifndef MPS2_FPGAIO_H | 77 | + * @dev: the device to add an input clock to |
57 | +#define MPS2_FPGAIO_H | 78 | + * @name: the name of the clock (can't be NULL). |
58 | + | 79 | + * @callback: optional callback to be called on update or NULL. |
59 | +#include "hw/sysbus.h" | 80 | + * @opaque: argument for the callback |
60 | + | 81 | + * @returns: a pointer to the newly added clock |
61 | +#define TYPE_MPS2_FPGAIO "mps2-fpgaio" | 82 | + * |
62 | +#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO) | 83 | + * Add an input clock to device @dev as a clock named @name. |
63 | + | 84 | + * This adds a child<> property. |
64 | +typedef struct { | 85 | + * The callback will be called with @opaque as opaque parameter. |
65 | + /*< private >*/ | 86 | + */ |
66 | + SysBusDevice parent_obj; | 87 | +Clock *qdev_init_clock_in(DeviceState *dev, const char *name, |
67 | + | 88 | + ClockCallback *callback, void *opaque); |
68 | + /*< public >*/ | 89 | + |
69 | + MemoryRegion iomem; | 90 | +/** |
70 | + | 91 | + * qdev_init_clock_out: |
71 | + uint32_t led0; | 92 | + * @dev: the device to add an output clock to |
72 | + uint32_t prescale; | 93 | + * @name: the name of the clock (can't be NULL). |
73 | + uint32_t misc; | 94 | + * @returns: a pointer to the newly added clock |
74 | + | 95 | + * |
75 | + uint32_t prescale_clk; | 96 | + * Add an output clock to device @dev as a clock named @name. |
76 | +} MPS2FPGAIO; | 97 | + * This adds a child<> property. |
77 | + | 98 | + */ |
78 | +#endif | 99 | +Clock *qdev_init_clock_out(DeviceState *dev, const char *name); |
79 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | 100 | + |
101 | +/** | ||
102 | + * qdev_get_clock_in: | ||
103 | + * @dev: the device which has the clock | ||
104 | + * @name: the name of the clock (can't be NULL). | ||
105 | + * @returns: a pointer to the clock | ||
106 | + * | ||
107 | + * Get the input clock @name from @dev or NULL if does not exist. | ||
108 | + */ | ||
109 | +Clock *qdev_get_clock_in(DeviceState *dev, const char *name); | ||
110 | + | ||
111 | +/** | ||
112 | + * qdev_get_clock_out: | ||
113 | + * @dev: the device which has the clock | ||
114 | + * @name: the name of the clock (can't be NULL). | ||
115 | + * @returns: a pointer to the clock | ||
116 | + * | ||
117 | + * Get the output clock @name from @dev or NULL if does not exist. | ||
118 | + */ | ||
119 | +Clock *qdev_get_clock_out(DeviceState *dev, const char *name); | ||
120 | + | ||
121 | +/** | ||
122 | + * qdev_connect_clock_in: | ||
123 | + * @dev: a device | ||
124 | + * @name: the name of an input clock in @dev | ||
125 | + * @source: the source clock (an output clock of another device for example) | ||
126 | + * | ||
127 | + * Set the source clock of input clock @name of device @dev to @source. | ||
128 | + * @source period update will be propagated to @name clock. | ||
129 | + */ | ||
130 | +static inline void qdev_connect_clock_in(DeviceState *dev, const char *name, | ||
131 | + Clock *source) | ||
132 | +{ | ||
133 | + clock_set_source(qdev_get_clock_in(dev, name), source); | ||
134 | +} | ||
135 | + | ||
136 | +/** | ||
137 | + * qdev_alias_clock: | ||
138 | + * @dev: the device which has the clock | ||
139 | + * @name: the name of the clock in @dev (can't be NULL) | ||
140 | + * @alias_dev: the device to add the clock | ||
141 | + * @alias_name: the name of the clock in @container | ||
142 | + * @returns: a pointer to the clock | ||
143 | + * | ||
144 | + * Add a clock @alias_name in @alias_dev which is an alias of the clock @name | ||
145 | + * in @dev. The direction _in_ or _out_ will the same as the original. | ||
146 | + * An alias clock must not be modified or used by @alias_dev and should | ||
147 | + * typically be only only for device composition purpose. | ||
148 | + */ | ||
149 | +Clock *qdev_alias_clock(DeviceState *dev, const char *name, | ||
150 | + DeviceState *alias_dev, const char *alias_name); | ||
151 | + | ||
152 | +/** | ||
153 | + * qdev_finalize_clocklist: | ||
154 | + * @dev: the device being finalized | ||
155 | + * | ||
156 | + * Clear the clocklist from @dev. Only used internally in qdev. | ||
157 | + */ | ||
158 | +void qdev_finalize_clocklist(DeviceState *dev); | ||
159 | + | ||
160 | +#endif /* QDEV_CLOCK_H */ | ||
161 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/include/hw/qdev-core.h | ||
164 | +++ b/include/hw/qdev-core.h | ||
165 | @@ -XXX,XX +XXX,XX @@ struct NamedGPIOList { | ||
166 | QLIST_ENTRY(NamedGPIOList) node; | ||
167 | }; | ||
168 | |||
169 | +typedef struct Clock Clock; | ||
170 | +typedef struct NamedClockList NamedClockList; | ||
171 | + | ||
172 | +struct NamedClockList { | ||
173 | + char *name; | ||
174 | + Clock *clock; | ||
175 | + bool output; | ||
176 | + bool alias; | ||
177 | + QLIST_ENTRY(NamedClockList) node; | ||
178 | +}; | ||
179 | + | ||
180 | /** | ||
181 | * DeviceState: | ||
182 | * @realized: Indicates whether the device has been fully constructed. | ||
183 | @@ -XXX,XX +XXX,XX @@ struct DeviceState { | ||
184 | bool allow_unplug_during_migration; | ||
185 | BusState *parent_bus; | ||
186 | QLIST_HEAD(, NamedGPIOList) gpios; | ||
187 | + QLIST_HEAD(, NamedClockList) clocks; | ||
188 | QLIST_HEAD(, BusState) child_bus; | ||
189 | int num_child_bus; | ||
190 | int instance_id_alias; | ||
191 | diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c | ||
80 | new file mode 100644 | 192 | new file mode 100644 |
81 | index XXXXXXX..XXXXXXX | 193 | index XXXXXXX..XXXXXXX |
82 | --- /dev/null | 194 | --- /dev/null |
83 | +++ b/hw/misc/mps2-fpgaio.c | 195 | +++ b/hw/core/qdev-clock.c |
84 | @@ -XXX,XX +XXX,XX @@ | 196 | @@ -XXX,XX +XXX,XX @@ |
85 | +/* | 197 | +/* |
86 | + * ARM MPS2 AN505 FPGAIO emulation | 198 | + * Device's clock input and output |
87 | + * | 199 | + * |
88 | + * Copyright (c) 2018 Linaro Limited | 200 | + * Copyright GreenSocs 2016-2020 |
89 | + * Written by Peter Maydell | 201 | + * |
90 | + * | 202 | + * Authors: |
91 | + * This program is free software; you can redistribute it and/or modify | 203 | + * Frederic Konrad |
92 | + * it under the terms of the GNU General Public License version 2 or | 204 | + * Damien Hedde |
93 | + * (at your option) any later version. | 205 | + * |
94 | + */ | 206 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
95 | + | 207 | + * See the COPYING file in the top-level directory. |
96 | +/* This is a model of the "FPGA system control and I/O" block found | ||
97 | + * in the AN505 FPGA image for the MPS2 devboard. | ||
98 | + * It is documented in AN505: | ||
99 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
100 | + */ | 208 | + */ |
101 | + | 209 | + |
102 | +#include "qemu/osdep.h" | 210 | +#include "qemu/osdep.h" |
103 | +#include "qemu/log.h" | 211 | +#include "hw/qdev-clock.h" |
212 | +#include "hw/qdev-core.h" | ||
104 | +#include "qapi/error.h" | 213 | +#include "qapi/error.h" |
105 | +#include "trace.h" | 214 | + |
106 | +#include "hw/sysbus.h" | 215 | +/* |
107 | +#include "hw/registerfields.h" | 216 | + * qdev_init_clocklist: |
108 | +#include "hw/misc/mps2-fpgaio.h" | 217 | + * Add a new clock in a device |
109 | + | 218 | + */ |
110 | +REG32(LED0, 0) | 219 | +static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *name, |
111 | +REG32(BUTTON, 8) | 220 | + bool output, Clock *clk) |
112 | +REG32(CLK1HZ, 0x10) | 221 | +{ |
113 | +REG32(CLK100HZ, 0x14) | 222 | + NamedClockList *ncl; |
114 | +REG32(COUNTER, 0x18) | 223 | + |
115 | +REG32(PRESCALE, 0x1c) | 224 | + /* |
116 | +REG32(PSCNTR, 0x20) | 225 | + * Clock must be added before realize() so that we can compute the |
117 | +REG32(MISC, 0x4c) | 226 | + * clock's canonical path during device_realize(). |
118 | + | 227 | + */ |
119 | +static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) | 228 | + assert(!dev->realized); |
120 | +{ | 229 | + |
121 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | 230 | + /* |
122 | + uint64_t r; | 231 | + * The ncl structure is freed by qdev_finalize_clocklist() which will |
123 | + | 232 | + * be called during @dev's device_finalize(). |
124 | + switch (offset) { | 233 | + */ |
125 | + case A_LED0: | 234 | + ncl = g_new0(NamedClockList, 1); |
126 | + r = s->led0; | 235 | + ncl->name = g_strdup(name); |
127 | + break; | 236 | + ncl->output = output; |
128 | + case A_BUTTON: | 237 | + ncl->alias = (clk != NULL); |
129 | + /* User-pressable board buttons. We don't model that, so just return | 238 | + |
130 | + * zeroes. | 239 | + /* |
131 | + */ | 240 | + * Trying to create a clock whose name clashes with some other |
132 | + r = 0; | 241 | + * clock or property is a bug in the caller and we will abort(). |
133 | + break; | 242 | + */ |
134 | + case A_PRESCALE: | 243 | + if (clk == NULL) { |
135 | + r = s->prescale; | 244 | + clk = CLOCK(object_new(TYPE_CLOCK)); |
136 | + break; | 245 | + object_property_add_child(OBJECT(dev), name, OBJECT(clk), &error_abort); |
137 | + case A_MISC: | 246 | + if (output) { |
138 | + r = s->misc; | 247 | + /* |
139 | + break; | 248 | + * Remove object_new()'s initial reference. |
140 | + case A_CLK1HZ: | 249 | + * Note that for inputs, the reference created by object_new() |
141 | + case A_CLK100HZ: | 250 | + * will be deleted in qdev_finalize_clocklist(). |
142 | + case A_COUNTER: | 251 | + */ |
143 | + case A_PSCNTR: | 252 | + object_unref(OBJECT(clk)); |
144 | + /* These are all upcounters of various frequencies. */ | 253 | + } |
145 | + qemu_log_mask(LOG_UNIMP, "MPS2 FPGAIO: counters unimplemented\n"); | 254 | + } else { |
146 | + r = 0; | 255 | + object_property_add_link(OBJECT(dev), name, |
147 | + break; | 256 | + object_get_typename(OBJECT(clk)), |
148 | + default: | 257 | + (Object **) &ncl->clock, |
149 | + qemu_log_mask(LOG_GUEST_ERROR, | 258 | + NULL, OBJ_PROP_LINK_STRONG, &error_abort); |
150 | + "MPS2 FPGAIO read: bad offset %x\n", (int) offset); | ||
151 | + r = 0; | ||
152 | + break; | ||
153 | + } | 259 | + } |
154 | + | 260 | + |
155 | + trace_mps2_fpgaio_read(offset, r, size); | 261 | + ncl->clock = clk; |
156 | + return r; | 262 | + |
157 | +} | 263 | + QLIST_INSERT_HEAD(&dev->clocks, ncl, node); |
158 | + | 264 | + return ncl; |
159 | +static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, | 265 | +} |
160 | + unsigned size) | 266 | + |
161 | +{ | 267 | +void qdev_finalize_clocklist(DeviceState *dev) |
162 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | 268 | +{ |
163 | + | 269 | + /* called by @dev's device_finalize() */ |
164 | + trace_mps2_fpgaio_write(offset, value, size); | 270 | + NamedClockList *ncl, *ncl_next; |
165 | + | 271 | + |
166 | + switch (offset) { | 272 | + QLIST_FOREACH_SAFE(ncl, &dev->clocks, node, ncl_next) { |
167 | + case A_LED0: | 273 | + QLIST_REMOVE(ncl, node); |
168 | + /* LED bits [1:0] control board LEDs. We don't currently have | 274 | + if (!ncl->output && !ncl->alias) { |
169 | + * a mechanism for displaying this graphically, so use a trace event. | 275 | + /* |
170 | + */ | 276 | + * We kept a reference on the input clock to ensure it lives up to |
171 | + trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', | 277 | + * this point so we can safely remove the callback. |
172 | + value & 0x01 ? '*' : '.'); | 278 | + * It avoids having a callback to a deleted object if ncl->clock |
173 | + s->led0 = value & 0x3; | 279 | + * is still referenced somewhere else (eg: by a clock output). |
174 | + break; | 280 | + */ |
175 | + case A_PRESCALE: | 281 | + clock_clear_callback(ncl->clock); |
176 | + s->prescale = value; | 282 | + object_unref(OBJECT(ncl->clock)); |
177 | + break; | 283 | + } |
178 | + case A_MISC: | 284 | + g_free(ncl->name); |
179 | + /* These are control bits for some of the other devices on the | 285 | + g_free(ncl); |
180 | + * board (SPI, CLCD, etc). We don't implement that yet, so just | ||
181 | + * make the bits read as written. | ||
182 | + */ | ||
183 | + qemu_log_mask(LOG_UNIMP, | ||
184 | + "MPS2 FPGAIO: MISC control bits unimplemented\n"); | ||
185 | + s->misc = value; | ||
186 | + break; | ||
187 | + default: | ||
188 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
189 | + "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); | ||
190 | + break; | ||
191 | + } | 286 | + } |
192 | +} | 287 | +} |
193 | + | 288 | + |
194 | +static const MemoryRegionOps mps2_fpgaio_ops = { | 289 | +Clock *qdev_init_clock_out(DeviceState *dev, const char *name) |
195 | + .read = mps2_fpgaio_read, | 290 | +{ |
196 | + .write = mps2_fpgaio_write, | 291 | + NamedClockList *ncl; |
197 | + .endianness = DEVICE_LITTLE_ENDIAN, | 292 | + |
198 | +}; | 293 | + assert(name); |
199 | + | 294 | + |
200 | +static void mps2_fpgaio_reset(DeviceState *dev) | 295 | + ncl = qdev_init_clocklist(dev, name, true, NULL); |
201 | +{ | 296 | + |
202 | + MPS2FPGAIO *s = MPS2_FPGAIO(dev); | 297 | + return ncl->clock; |
203 | + | 298 | +} |
204 | + trace_mps2_fpgaio_reset(); | 299 | + |
205 | + s->led0 = 0; | 300 | +Clock *qdev_init_clock_in(DeviceState *dev, const char *name, |
206 | + s->prescale = 0; | 301 | + ClockCallback *callback, void *opaque) |
207 | + s->misc = 0; | 302 | +{ |
208 | +} | 303 | + NamedClockList *ncl; |
209 | + | 304 | + |
210 | +static void mps2_fpgaio_init(Object *obj) | 305 | + assert(name); |
211 | +{ | 306 | + |
212 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 307 | + ncl = qdev_init_clocklist(dev, name, false, NULL); |
213 | + MPS2FPGAIO *s = MPS2_FPGAIO(obj); | 308 | + |
214 | + | 309 | + if (callback) { |
215 | + memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, | 310 | + clock_set_callback(ncl->clock, callback, opaque); |
216 | + "mps2-fpgaio", 0x1000); | ||
217 | + sysbus_init_mmio(sbd, &s->iomem); | ||
218 | +} | ||
219 | + | ||
220 | +static const VMStateDescription mps2_fpgaio_vmstate = { | ||
221 | + .name = "mps2-fpgaio", | ||
222 | + .version_id = 1, | ||
223 | + .minimum_version_id = 1, | ||
224 | + .fields = (VMStateField[]) { | ||
225 | + VMSTATE_UINT32(led0, MPS2FPGAIO), | ||
226 | + VMSTATE_UINT32(prescale, MPS2FPGAIO), | ||
227 | + VMSTATE_UINT32(misc, MPS2FPGAIO), | ||
228 | + VMSTATE_END_OF_LIST() | ||
229 | + } | 311 | + } |
230 | +}; | 312 | + return ncl->clock; |
231 | + | 313 | +} |
232 | +static Property mps2_fpgaio_properties[] = { | 314 | + |
233 | + /* Frequency of the prescale counter */ | 315 | +static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *name) |
234 | + DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), | 316 | +{ |
235 | + DEFINE_PROP_END_OF_LIST(), | 317 | + NamedClockList *ncl; |
236 | +}; | 318 | + |
237 | + | 319 | + QLIST_FOREACH(ncl, &dev->clocks, node) { |
238 | +static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) | 320 | + if (strcmp(name, ncl->name) == 0) { |
239 | +{ | 321 | + return ncl; |
240 | + DeviceClass *dc = DEVICE_CLASS(klass); | 322 | + } |
241 | + | 323 | + } |
242 | + dc->vmsd = &mps2_fpgaio_vmstate; | 324 | + |
243 | + dc->reset = mps2_fpgaio_reset; | 325 | + return NULL; |
244 | + dc->props = mps2_fpgaio_properties; | 326 | +} |
245 | +} | 327 | + |
246 | + | 328 | +Clock *qdev_get_clock_in(DeviceState *dev, const char *name) |
247 | +static const TypeInfo mps2_fpgaio_info = { | 329 | +{ |
248 | + .name = TYPE_MPS2_FPGAIO, | 330 | + NamedClockList *ncl; |
249 | + .parent = TYPE_SYS_BUS_DEVICE, | 331 | + |
250 | + .instance_size = sizeof(MPS2FPGAIO), | 332 | + assert(name); |
251 | + .instance_init = mps2_fpgaio_init, | 333 | + |
252 | + .class_init = mps2_fpgaio_class_init, | 334 | + ncl = qdev_get_clocklist(dev, name); |
253 | +}; | 335 | + assert(!ncl->output); |
254 | + | 336 | + |
255 | +static void mps2_fpgaio_register_types(void) | 337 | + return ncl->clock; |
256 | +{ | 338 | +} |
257 | + type_register_static(&mps2_fpgaio_info); | 339 | + |
258 | +} | 340 | +Clock *qdev_get_clock_out(DeviceState *dev, const char *name) |
259 | + | 341 | +{ |
260 | +type_init(mps2_fpgaio_register_types); | 342 | + NamedClockList *ncl; |
261 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | 343 | + |
344 | + assert(name); | ||
345 | + | ||
346 | + ncl = qdev_get_clocklist(dev, name); | ||
347 | + assert(ncl->output); | ||
348 | + | ||
349 | + return ncl->clock; | ||
350 | +} | ||
351 | + | ||
352 | +Clock *qdev_alias_clock(DeviceState *dev, const char *name, | ||
353 | + DeviceState *alias_dev, const char *alias_name) | ||
354 | +{ | ||
355 | + NamedClockList *ncl; | ||
356 | + | ||
357 | + assert(name && alias_name); | ||
358 | + | ||
359 | + ncl = qdev_get_clocklist(dev, name); | ||
360 | + | ||
361 | + qdev_init_clocklist(alias_dev, alias_name, ncl->output, ncl->clock); | ||
362 | + | ||
363 | + return ncl->clock; | ||
364 | +} | ||
365 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
262 | index XXXXXXX..XXXXXXX 100644 | 366 | index XXXXXXX..XXXXXXX 100644 |
263 | --- a/default-configs/arm-softmmu.mak | 367 | --- a/hw/core/qdev.c |
264 | +++ b/default-configs/arm-softmmu.mak | 368 | +++ b/hw/core/qdev.c |
265 | @@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y | 369 | @@ -XXX,XX +XXX,XX @@ |
266 | CONFIG_CMSDK_APB_TIMER=y | 370 | #include "hw/qdev-properties.h" |
267 | CONFIG_CMSDK_APB_UART=y | 371 | #include "hw/boards.h" |
268 | 372 | #include "hw/sysbus.h" | |
269 | +CONFIG_MPS2_FPGAIO=y | 373 | +#include "hw/qdev-clock.h" |
270 | CONFIG_MPS2_SCC=y | 374 | #include "migration/vmstate.h" |
271 | 375 | #include "trace.h" | |
272 | CONFIG_VERSATILE_PCI=y | 376 | |
273 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | 377 | @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) |
274 | index XXXXXXX..XXXXXXX 100644 | 378 | DeviceClass *dc = DEVICE_GET_CLASS(dev); |
275 | --- a/hw/misc/trace-events | 379 | HotplugHandler *hotplug_ctrl; |
276 | +++ b/hw/misc/trace-events | 380 | BusState *bus; |
277 | @@ -XXX,XX +XXX,XX @@ mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, | 381 | + NamedClockList *ncl; |
278 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 | 382 | Error *local_err = NULL; |
279 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 | 383 | bool unattached_parent = false; |
280 | 384 | static int unattached_count; | |
281 | +# hw/misc/mps2_fpgaio.c | 385 | @@ -XXX,XX +XXX,XX @@ static void device_set_realized(Object *obj, bool value, Error **errp) |
282 | +mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | 386 | */ |
283 | +mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | 387 | g_free(dev->canonical_path); |
284 | +mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" | 388 | dev->canonical_path = object_get_canonical_path(OBJECT(dev)); |
285 | +mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c" | 389 | + QLIST_FOREACH(ncl, &dev->clocks, node) { |
286 | + | 390 | + if (ncl->alias) { |
287 | # hw/misc/msf2-sysreg.c | 391 | + continue; |
288 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 | 392 | + } else { |
289 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32 | 393 | + clock_setup_canonical_path(ncl->clock); |
394 | + } | ||
395 | + } | ||
396 | |||
397 | if (qdev_get_vmsd(dev)) { | ||
398 | if (vmstate_register_with_alias_id(VMSTATE_IF(dev), | ||
399 | @@ -XXX,XX +XXX,XX @@ static void device_initfn(Object *obj) | ||
400 | dev->allow_unplug_during_migration = false; | ||
401 | |||
402 | QLIST_INIT(&dev->gpios); | ||
403 | + QLIST_INIT(&dev->clocks); | ||
404 | } | ||
405 | |||
406 | static void device_post_init(Object *obj) | ||
407 | @@ -XXX,XX +XXX,XX @@ static void device_finalize(Object *obj) | ||
408 | */ | ||
409 | } | ||
410 | |||
411 | + qdev_finalize_clocklist(dev); | ||
412 | + | ||
413 | /* Only send event if the device had been completely realized */ | ||
414 | if (dev->pending_deleted_event) { | ||
415 | g_assert(dev->canonical_path); | ||
290 | -- | 416 | -- |
291 | 2.16.2 | 417 | 2.20.1 |
292 | 418 | ||
293 | 419 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Introduce a function and macro helpers to setup several clocks |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | in a device from a static array description. |
5 | Message-id: 20180228193125.20577-6-richard.henderson@linaro.org | 5 | |
6 | An element of the array describes the clock (name and direction) as | ||
7 | well as the related callback and an optional offset to store the | ||
8 | created object pointer in the device state structure. | ||
9 | |||
10 | The array must be terminated by a special element QDEV_CLOCK_END. | ||
11 | |||
12 | This is based on the original work of Frederic Konrad. | ||
13 | |||
14 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
16 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
18 | Message-id: 20200406135251.157596-5-damien.hedde@greensocs.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 20 | --- |
8 | target/arm/helper.h | 9 +++++ | 21 | include/hw/qdev-clock.h | 55 +++++++++++++++++++++++++++++++++++++++++ |
9 | target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ | 22 | hw/core/qdev-clock.c | 17 +++++++++++++ |
10 | target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++ | 23 | 2 files changed, 72 insertions(+) |
11 | 3 files changed, 166 insertions(+) | ||
12 | 24 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 25 | diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h |
14 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 27 | --- a/include/hw/qdev-clock.h |
16 | +++ b/target/arm/helper.h | 28 | +++ b/include/hw/qdev-clock.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(dc_zva, void, env, i64) | 29 | @@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name, |
18 | DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 30 | */ |
19 | DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 31 | void qdev_finalize_clocklist(DeviceState *dev); |
20 | 32 | ||
21 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, | 33 | +/** |
22 | + void, ptr, ptr, ptr, ptr, i32) | 34 | + * ClockPortInitElem: |
23 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, | 35 | + * @name: name of the clock (can't be NULL) |
24 | + void, ptr, ptr, ptr, ptr, i32) | 36 | + * @output: indicates whether the clock is input or output |
25 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 37 | + * @callback: for inputs, optional callback to be called on clock's update |
26 | + void, ptr, ptr, ptr, ptr, i32) | 38 | + * with device as opaque |
27 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 39 | + * @offset: optional offset to store the ClockIn or ClockOut pointer in device |
28 | + void, ptr, ptr, ptr, ptr, i32) | 40 | + * state structure (0 means unused) |
41 | + */ | ||
42 | +struct ClockPortInitElem { | ||
43 | + const char *name; | ||
44 | + bool is_output; | ||
45 | + ClockCallback *callback; | ||
46 | + size_t offset; | ||
47 | +}; | ||
29 | + | 48 | + |
30 | #ifdef TARGET_AARCH64 | 49 | +#define clock_offset_value(devstate, field) \ |
31 | #include "helper-a64.h" | 50 | + (offsetof(devstate, field) + \ |
32 | #endif | 51 | + type_check(Clock *, typeof_field(devstate, field))) |
33 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 52 | + |
34 | index XXXXXXX..XXXXXXX 100644 | 53 | +#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \ |
35 | --- a/target/arm/translate-a64.c | 54 | + .name = (stringify(field)), \ |
36 | +++ b/target/arm/translate-a64.c | 55 | + .is_output = out_not_in, \ |
37 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, | 56 | + .callback = cb, \ |
38 | vec_full_reg_size(s), gvec_op); | 57 | + .offset = clock_offset_value(devstate, field), \ |
39 | } | ||
40 | |||
41 | +/* Expand a 3-operand + env pointer operation using | ||
42 | + * an out-of-line helper. | ||
43 | + */ | ||
44 | +static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
45 | + int rn, int rm, gen_helper_gvec_3_ptr *fn) | ||
46 | +{ | ||
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), cpu_env, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
51 | +} | 58 | +} |
52 | + | 59 | + |
53 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | 60 | +/** |
54 | * than the 32 bit equivalent. | 61 | + * QDEV_CLOCK_(IN|OUT): |
55 | */ | 62 | + * @devstate: structure type. @dev argument of qdev_init_clocks below must be |
56 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | 63 | + * a pointer to that same type. |
57 | clear_vec_high(s, is_q, rd); | 64 | + * @field: a field in @_devstate (must be Clock*) |
65 | + * @callback: (for input only) callback (or NULL) to be called with the device | ||
66 | + * state as argument | ||
67 | + * | ||
68 | + * The name of the clock will be derived from @field | ||
69 | + */ | ||
70 | +#define QDEV_CLOCK_IN(devstate, field, callback) \ | ||
71 | + QDEV_CLOCK(false, devstate, field, callback) | ||
72 | + | ||
73 | +#define QDEV_CLOCK_OUT(devstate, field) \ | ||
74 | + QDEV_CLOCK(true, devstate, field, NULL) | ||
75 | + | ||
76 | +#define QDEV_CLOCK_END { .name = NULL } | ||
77 | + | ||
78 | +typedef struct ClockPortInitElem ClockPortInitArray[]; | ||
79 | + | ||
80 | +/** | ||
81 | + * qdev_init_clocks: | ||
82 | + * @dev: the device to add clocks to | ||
83 | + * @clocks: a QDEV_CLOCK_END-terminated array which contains the | ||
84 | + * clocks information. | ||
85 | + */ | ||
86 | +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks); | ||
87 | + | ||
88 | #endif /* QDEV_CLOCK_H */ | ||
89 | diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c | ||
90 | index XXXXXXX..XXXXXXX 100644 | ||
91 | --- a/hw/core/qdev-clock.c | ||
92 | +++ b/hw/core/qdev-clock.c | ||
93 | @@ -XXX,XX +XXX,XX @@ Clock *qdev_init_clock_in(DeviceState *dev, const char *name, | ||
94 | return ncl->clock; | ||
58 | } | 95 | } |
59 | 96 | ||
60 | +/* AdvSIMD three same extra | 97 | +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks) |
61 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
62 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
63 | + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
64 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
65 | + */ | ||
66 | +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | +{ | 98 | +{ |
68 | + int rd = extract32(insn, 0, 5); | 99 | + const struct ClockPortInitElem *elem; |
69 | + int rn = extract32(insn, 5, 5); | ||
70 | + int opcode = extract32(insn, 11, 4); | ||
71 | + int rm = extract32(insn, 16, 5); | ||
72 | + int size = extract32(insn, 22, 2); | ||
73 | + bool u = extract32(insn, 29, 1); | ||
74 | + bool is_q = extract32(insn, 30, 1); | ||
75 | + int feature; | ||
76 | + | 100 | + |
77 | + switch (u * 16 + opcode) { | 101 | + for (elem = &clocks[0]; elem->name != NULL; elem++) { |
78 | + case 0x10: /* SQRDMLAH (vector) */ | 102 | + Clock **clkp; |
79 | + case 0x11: /* SQRDMLSH (vector) */ | 103 | + /* offset cannot be inside the DeviceState part */ |
80 | + if (size != 1 && size != 2) { | 104 | + assert(elem->offset > sizeof(DeviceState)); |
81 | + unallocated_encoding(s); | 105 | + clkp = (Clock **)(((void *) dev) + elem->offset); |
82 | + return; | 106 | + if (elem->is_output) { |
107 | + *clkp = qdev_init_clock_out(dev, elem->name); | ||
108 | + } else { | ||
109 | + *clkp = qdev_init_clock_in(dev, elem->name, elem->callback, dev); | ||
83 | + } | 110 | + } |
84 | + feature = ARM_FEATURE_V8_RDM; | ||
85 | + break; | ||
86 | + default: | ||
87 | + unallocated_encoding(s); | ||
88 | + return; | ||
89 | + } | ||
90 | + if (!arm_dc_feature(s, feature)) { | ||
91 | + unallocated_encoding(s); | ||
92 | + return; | ||
93 | + } | ||
94 | + if (!fp_access_check(s)) { | ||
95 | + return; | ||
96 | + } | ||
97 | + | ||
98 | + switch (opcode) { | ||
99 | + case 0x0: /* SQRDMLAH (vector) */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); | ||
103 | + break; | ||
104 | + case 2: | ||
105 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); | ||
106 | + break; | ||
107 | + default: | ||
108 | + g_assert_not_reached(); | ||
109 | + } | ||
110 | + return; | ||
111 | + | ||
112 | + case 0x1: /* SQRDMLSH (vector) */ | ||
113 | + switch (size) { | ||
114 | + case 1: | ||
115 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); | ||
116 | + break; | ||
117 | + case 2: | ||
118 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); | ||
119 | + break; | ||
120 | + default: | ||
121 | + g_assert_not_reached(); | ||
122 | + } | ||
123 | + return; | ||
124 | + | ||
125 | + default: | ||
126 | + g_assert_not_reached(); | ||
127 | + } | 111 | + } |
128 | +} | 112 | +} |
129 | + | 113 | + |
130 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, | 114 | static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *name) |
131 | int size, int rn, int rd) | ||
132 | { | 115 | { |
133 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | 116 | NamedClockList *ncl; |
134 | static const AArch64DecodeTable data_proc_simd[] = { | ||
135 | /* pattern , mask , fn */ | ||
136 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | ||
137 | + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, | ||
138 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | ||
139 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | ||
140 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | ||
141 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/vec_helper.c | ||
144 | +++ b/target/arm/vec_helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ | ||
146 | |||
147 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
148 | |||
149 | +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
150 | +{ | ||
151 | + uint64_t *d = vd + opr_sz; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + for (i = opr_sz; i < max_sz; i += 8) { | ||
155 | + *d++ = 0; | ||
156 | + } | ||
157 | +} | ||
158 | + | ||
159 | /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
160 | static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
161 | int16_t src2, int16_t src3) | ||
162 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
163 | return deposit32(e1, 16, 16, e2); | ||
164 | } | ||
165 | |||
166 | +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, | ||
167 | + void *ve, uint32_t desc) | ||
168 | +{ | ||
169 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
170 | + int16_t *d = vd; | ||
171 | + int16_t *n = vn; | ||
172 | + int16_t *m = vm; | ||
173 | + CPUARMState *env = ve; | ||
174 | + uintptr_t i; | ||
175 | + | ||
176 | + for (i = 0; i < opr_sz / 2; ++i) { | ||
177 | + d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); | ||
178 | + } | ||
179 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
180 | +} | ||
181 | + | ||
182 | /* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | ||
183 | static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | ||
184 | int16_t src2, int16_t src3) | ||
185 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
186 | return deposit32(e1, 16, 16, e2); | ||
187 | } | ||
188 | |||
189 | +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, | ||
190 | + void *ve, uint32_t desc) | ||
191 | +{ | ||
192 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
193 | + int16_t *d = vd; | ||
194 | + int16_t *n = vn; | ||
195 | + int16_t *m = vm; | ||
196 | + CPUARMState *env = ve; | ||
197 | + uintptr_t i; | ||
198 | + | ||
199 | + for (i = 0; i < opr_sz / 2; ++i) { | ||
200 | + d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]); | ||
201 | + } | ||
202 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
203 | +} | ||
204 | + | ||
205 | /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
206 | uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
207 | int32_t src2, int32_t src3) | ||
208 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
209 | return ret; | ||
210 | } | ||
211 | |||
212 | +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, | ||
213 | + void *ve, uint32_t desc) | ||
214 | +{ | ||
215 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
216 | + int32_t *d = vd; | ||
217 | + int32_t *n = vn; | ||
218 | + int32_t *m = vm; | ||
219 | + CPUARMState *env = ve; | ||
220 | + uintptr_t i; | ||
221 | + | ||
222 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
223 | + d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); | ||
224 | + } | ||
225 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
226 | +} | ||
227 | + | ||
228 | /* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
229 | uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
230 | int32_t src2, int32_t src3) | ||
231 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
232 | } | ||
233 | return ret; | ||
234 | } | ||
235 | + | ||
236 | +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
237 | + void *ve, uint32_t desc) | ||
238 | +{ | ||
239 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
240 | + int32_t *d = vd; | ||
241 | + int32_t *n = vn; | ||
242 | + int32_t *m = vm; | ||
243 | + CPUARMState *env = ve; | ||
244 | + uintptr_t i; | ||
245 | + | ||
246 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
247 | + d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); | ||
248 | + } | ||
249 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
250 | +} | ||
251 | -- | 117 | -- |
252 | 2.16.2 | 118 | 2.20.1 |
253 | 119 | ||
254 | 120 | diff view generated by jsdifflib |
1 | The Arm IoT Kit includes a "security controller" which is largely a | 1 | Add the documentation about the clock inputs and outputs in devices. |
---|---|---|---|
2 | collection of registers for controlling the PPCs and other bits of | ||
3 | glue in the system. This commit provides the initial skeleton of the | ||
4 | device, implementing just the ID registers, and a couple of read-only | ||
5 | read-as-zero registers. | ||
6 | 2 | ||
3 | This is based on the original work of Frederic Konrad. | ||
4 | |||
5 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
8 | Message-id: 20200406135251.157596-6-damien.hedde@greensocs.com | ||
9 | [PMM: Editing pass for minor grammar, style and Sphinx | ||
10 | formatting fixes] | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-16-peter.maydell@linaro.org | ||
10 | --- | 13 | --- |
11 | hw/misc/Makefile.objs | 1 + | 14 | docs/devel/clocks.rst | 391 ++++++++++++++++++++++++++++++++++++++++++ |
12 | include/hw/misc/iotkit-secctl.h | 39 ++++ | 15 | docs/devel/index.rst | 1 + |
13 | hw/misc/iotkit-secctl.c | 448 ++++++++++++++++++++++++++++++++++++++++ | 16 | 2 files changed, 392 insertions(+) |
14 | default-configs/arm-softmmu.mak | 1 + | 17 | create mode 100644 docs/devel/clocks.rst |
15 | hw/misc/trace-events | 7 + | ||
16 | 5 files changed, 496 insertions(+) | ||
17 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
18 | create mode 100644 hw/misc/iotkit-secctl.c | ||
19 | 18 | ||
20 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 19 | diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst |
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/misc/Makefile.objs | ||
23 | +++ b/hw/misc/Makefile.objs | ||
24 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | ||
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | ||
26 | |||
27 | obj-$(CONFIG_TZ_PPC) += tz-ppc.o | ||
28 | +obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o | ||
29 | |||
30 | obj-$(CONFIG_PVPANIC) += pvpanic.o | ||
31 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | ||
32 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
33 | new file mode 100644 | 20 | new file mode 100644 |
34 | index XXXXXXX..XXXXXXX | 21 | index XXXXXXX..XXXXXXX |
35 | --- /dev/null | 22 | --- /dev/null |
36 | +++ b/include/hw/misc/iotkit-secctl.h | 23 | +++ b/docs/devel/clocks.rst |
37 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
38 | +/* | 25 | +Modelling a clock tree in QEMU |
39 | + * ARM IoT Kit security controller | 26 | +============================== |
40 | + * | 27 | + |
41 | + * Copyright (c) 2018 Linaro Limited | 28 | +What are clocks? |
42 | + * Written by Peter Maydell | 29 | +---------------- |
43 | + * | 30 | + |
44 | + * This program is free software; you can redistribute it and/or modify | 31 | +Clocks are QOM objects developed for the purpose of modelling the |
45 | + * it under the terms of the GNU General Public License version 2 or | 32 | +distribution of clocks in QEMU. |
46 | + * (at your option) any later version. | 33 | + |
47 | + */ | 34 | +They allow us to model the clock distribution of a platform and detect |
48 | + | 35 | +configuration errors in the clock tree such as badly configured PLL, clock |
49 | +/* This is a model of the security controller which is part of the | 36 | +source selection or disabled clock. |
50 | + * Arm IoT Kit and documented in | 37 | + |
51 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 38 | +The object is *Clock* and its QOM name is ``clock`` (in C code, the macro |
52 | + * | 39 | +``TYPE_CLOCK``). |
53 | + * QEMU interface: | 40 | + |
54 | + * + sysbus MMIO region 0 is the "secure privilege control block" registers | 41 | +Clocks are typically used with devices where they are used to model inputs |
55 | + * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 42 | +and outputs. They are created in a similar way to GPIOs. Inputs and outputs |
56 | + */ | 43 | +of different devices can be connected together. |
57 | + | 44 | + |
58 | +#ifndef IOTKIT_SECCTL_H | 45 | +In these cases a Clock object is a child of a Device object, but this |
59 | +#define IOTKIT_SECCTL_H | 46 | +is not a requirement. Clocks can be independent of devices. For |
60 | + | 47 | +example it is possible to create a clock outside of any device to |
61 | +#include "hw/sysbus.h" | 48 | +model the main clock source of a machine. |
62 | + | 49 | + |
63 | +#define TYPE_IOTKIT_SECCTL "iotkit-secctl" | 50 | +Here is an example of clocks:: |
64 | +#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | 51 | + |
65 | + | 52 | + +---------+ +----------------------+ +--------------+ |
66 | +typedef struct IoTKitSecCtl { | 53 | + | Clock 1 | | Device B | | Device C | |
67 | + /*< private >*/ | 54 | + | | | +-------+ +-------+ | | +-------+ | |
68 | + SysBusDevice parent_obj; | 55 | + | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| | |
69 | + | 56 | + +---------+ | | | (in) | | (out) | | | | (in) | | |
70 | + /*< public >*/ | 57 | + | | +-------+ +-------+ | | +-------+ | |
71 | + | 58 | + | | +-------+ | +--------------+ |
72 | + MemoryRegion s_regs; | 59 | + | | |Clock 4|>> |
73 | + MemoryRegion ns_regs; | 60 | + | | | (out) | | +--------------+ |
74 | +} IoTKitSecCtl; | 61 | + | | +-------+ | | Device D | |
75 | + | 62 | + | | +-------+ | | +-------+ | |
76 | +#endif | 63 | + | | |Clock 5|>>--->>|Clock 7| | |
77 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | 64 | + | | | (out) | | | | (in) | | |
78 | new file mode 100644 | 65 | + | | +-------+ | | +-------+ | |
79 | index XXXXXXX..XXXXXXX | 66 | + | +----------------------+ | | |
80 | --- /dev/null | 67 | + | | +-------+ | |
81 | +++ b/hw/misc/iotkit-secctl.c | 68 | + +----------------------------->>|Clock 8| | |
82 | @@ -XXX,XX +XXX,XX @@ | 69 | + | | (in) | | |
83 | +/* | 70 | + | +-------+ | |
84 | + * Arm IoT Kit security controller | 71 | + +--------------+ |
85 | + * | 72 | + |
86 | + * Copyright (c) 2018 Linaro Limited | 73 | +Clocks are defined in the ``include/hw/clock.h`` header and device |
87 | + * Written by Peter Maydell | 74 | +related functions are defined in the ``include/hw/qdev-clock.h`` |
88 | + * | 75 | +header. |
89 | + * This program is free software; you can redistribute it and/or modify | 76 | + |
90 | + * it under the terms of the GNU General Public License version 2 or | 77 | +The clock state |
91 | + * (at your option) any later version. | 78 | +--------------- |
92 | + */ | 79 | + |
93 | + | 80 | +The state of a clock is its period; it is stored as an integer |
94 | +#include "qemu/osdep.h" | 81 | +representing it in units of 2 :sup:`-32` ns. The special value of 0 is used to |
95 | +#include "qemu/log.h" | 82 | +represent the clock being inactive or gated. The clocks do not model |
96 | +#include "qapi/error.h" | 83 | +the signal itself (pin toggling) or other properties such as the duty |
97 | +#include "trace.h" | 84 | +cycle. |
98 | +#include "hw/sysbus.h" | 85 | + |
99 | +#include "hw/registerfields.h" | 86 | +All clocks contain this state: outputs as well as inputs. This allows |
100 | +#include "hw/misc/iotkit-secctl.h" | 87 | +the current period of a clock to be fetched at any time. When a clock |
101 | + | 88 | +is updated, the value is immediately propagated to all connected |
102 | +/* Registers in the secure privilege control block */ | 89 | +clocks in the tree. |
103 | +REG32(SECRESPCFG, 0x10) | 90 | + |
104 | +REG32(NSCCFG, 0x14) | 91 | +To ease interaction with clocks, helpers with a unit suffix are defined for |
105 | +REG32(SECMPCINTSTATUS, 0x1c) | 92 | +every clock state setter or getter. The suffixes are: |
106 | +REG32(SECPPCINTSTAT, 0x20) | 93 | + |
107 | +REG32(SECPPCINTCLR, 0x24) | 94 | +- ``_ns`` for handling periods in nanoseconds |
108 | +REG32(SECPPCINTEN, 0x28) | 95 | +- ``_hz`` for handling frequencies in hertz |
109 | +REG32(SECMSCINTSTAT, 0x30) | 96 | + |
110 | +REG32(SECMSCINTCLR, 0x34) | 97 | +The 0 period value is converted to 0 in hertz and vice versa. 0 always means |
111 | +REG32(SECMSCINTEN, 0x38) | 98 | +that the clock is disabled. |
112 | +REG32(BRGINTSTAT, 0x40) | 99 | + |
113 | +REG32(BRGINTCLR, 0x44) | 100 | +Adding a new clock |
114 | +REG32(BRGINTEN, 0x48) | 101 | +------------------ |
115 | +REG32(AHBNSPPC0, 0x50) | 102 | + |
116 | +REG32(AHBNSPPCEXP0, 0x60) | 103 | +Adding clocks to a device must be done during the init method of the Device |
117 | +REG32(AHBNSPPCEXP1, 0x64) | 104 | +instance. |
118 | +REG32(AHBNSPPCEXP2, 0x68) | 105 | + |
119 | +REG32(AHBNSPPCEXP3, 0x6c) | 106 | +To add an input clock to a device, the function ``qdev_init_clock_in()`` |
120 | +REG32(APBNSPPC0, 0x70) | 107 | +must be used. It takes the name, a callback and an opaque parameter |
121 | +REG32(APBNSPPC1, 0x74) | 108 | +for the callback (this will be explained in a following section). |
122 | +REG32(APBNSPPCEXP0, 0x80) | 109 | +Output is simpler; only the name is required. Typically:: |
123 | +REG32(APBNSPPCEXP1, 0x84) | 110 | + |
124 | +REG32(APBNSPPCEXP2, 0x88) | 111 | + qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev); |
125 | +REG32(APBNSPPCEXP3, 0x8c) | 112 | + qdev_init_clock_out(DEVICE(dev), "clk_out"); |
126 | +REG32(AHBSPPPC0, 0x90) | 113 | + |
127 | +REG32(AHBSPPPCEXP0, 0xa0) | 114 | +Both functions return the created Clock pointer, which should be saved in the |
128 | +REG32(AHBSPPPCEXP1, 0xa4) | 115 | +device's state structure for further use. |
129 | +REG32(AHBSPPPCEXP2, 0xa8) | 116 | + |
130 | +REG32(AHBSPPPCEXP3, 0xac) | 117 | +These objects will be automatically deleted by the QOM reference mechanism. |
131 | +REG32(APBSPPPC0, 0xb0) | 118 | + |
132 | +REG32(APBSPPPC1, 0xb4) | 119 | +Note that it is possible to create a static array describing clock inputs and |
133 | +REG32(APBSPPPCEXP0, 0xc0) | 120 | +outputs. The function ``qdev_init_clocks()`` must be called with the array as |
134 | +REG32(APBSPPPCEXP1, 0xc4) | 121 | +parameter to initialize the clocks: it has the same behaviour as calling the |
135 | +REG32(APBSPPPCEXP2, 0xc8) | 122 | +``qdev_init_clock_in/out()`` for each clock in the array. To ease the array |
136 | +REG32(APBSPPPCEXP3, 0xcc) | 123 | +construction, some macros are defined in ``include/hw/qdev-clock.h``. |
137 | +REG32(NSMSCEXP, 0xd0) | 124 | +As an example, the following creates 2 clocks to a device: one input and one |
138 | +REG32(PID4, 0xfd0) | 125 | +output. |
139 | +REG32(PID5, 0xfd4) | 126 | + |
140 | +REG32(PID6, 0xfd8) | 127 | +.. code-block:: c |
141 | +REG32(PID7, 0xfdc) | 128 | + |
142 | +REG32(PID0, 0xfe0) | 129 | + /* device structure containing pointers to the clock objects */ |
143 | +REG32(PID1, 0xfe4) | 130 | + typedef struct MyDeviceState { |
144 | +REG32(PID2, 0xfe8) | 131 | + DeviceState parent_obj; |
145 | +REG32(PID3, 0xfec) | 132 | + Clock *clk_in; |
146 | +REG32(CID0, 0xff0) | 133 | + Clock *clk_out; |
147 | +REG32(CID1, 0xff4) | 134 | + } MyDeviceState; |
148 | +REG32(CID2, 0xff8) | 135 | + |
149 | +REG32(CID3, 0xffc) | 136 | + /* |
150 | + | 137 | + * callback for the input clock (see "Callback on input clock |
151 | +/* Registers in the non-secure privilege control block */ | 138 | + * change" section below for more information). |
152 | +REG32(AHBNSPPPC0, 0x90) | 139 | + */ |
153 | +REG32(AHBNSPPPCEXP0, 0xa0) | 140 | + static void clk_in_callback(void *opaque); |
154 | +REG32(AHBNSPPPCEXP1, 0xa4) | 141 | + |
155 | +REG32(AHBNSPPPCEXP2, 0xa8) | 142 | + /* |
156 | +REG32(AHBNSPPPCEXP3, 0xac) | 143 | + * static array describing clocks: |
157 | +REG32(APBNSPPPC0, 0xb0) | 144 | + * + a clock input named "clk_in", whose pointer is stored in |
158 | +REG32(APBNSPPPC1, 0xb4) | 145 | + * the clk_in field of a MyDeviceState structure with callback |
159 | +REG32(APBNSPPPCEXP0, 0xc0) | 146 | + * clk_in_callback. |
160 | +REG32(APBNSPPPCEXP1, 0xc4) | 147 | + * + a clock output named "clk_out" whose pointer is stored in |
161 | +REG32(APBNSPPPCEXP2, 0xc8) | 148 | + * the clk_out field of a MyDeviceState structure. |
162 | +REG32(APBNSPPPCEXP3, 0xcc) | 149 | + */ |
163 | +/* PID and CID registers are also present in the NS block */ | 150 | + static const ClockPortInitArray mydev_clocks = { |
164 | + | 151 | + QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback), |
165 | +static const uint8_t iotkit_secctl_s_idregs[] = { | 152 | + QDEV_CLOCK_OUT(MyDeviceState, clk_out), |
166 | + 0x04, 0x00, 0x00, 0x00, | 153 | + QDEV_CLOCK_END |
167 | + 0x52, 0xb8, 0x0b, 0x00, | 154 | + }; |
168 | + 0x0d, 0xf0, 0x05, 0xb1, | 155 | + |
169 | +}; | 156 | + /* device initialization function */ |
170 | + | 157 | + static void mydev_init(Object *obj) |
171 | +static const uint8_t iotkit_secctl_ns_idregs[] = { | 158 | + { |
172 | + 0x04, 0x00, 0x00, 0x00, | 159 | + /* cast to MyDeviceState */ |
173 | + 0x53, 0xb8, 0x0b, 0x00, | 160 | + MyDeviceState *mydev = MYDEVICE(obj); |
174 | + 0x0d, 0xf0, 0x05, 0xb1, | 161 | + /* create and fill the pointer fields in the MyDeviceState */ |
175 | +}; | 162 | + qdev_init_clocks(mydev, mydev_clocks); |
176 | + | 163 | + [...] |
177 | +static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
178 | + uint64_t *pdata, | ||
179 | + unsigned size, MemTxAttrs attrs) | ||
180 | +{ | ||
181 | + uint64_t r; | ||
182 | + uint32_t offset = addr & ~0x3; | ||
183 | + | ||
184 | + switch (offset) { | ||
185 | + case A_AHBNSPPC0: | ||
186 | + case A_AHBSPPPC0: | ||
187 | + r = 0; | ||
188 | + break; | ||
189 | + case A_SECRESPCFG: | ||
190 | + case A_NSCCFG: | ||
191 | + case A_SECMPCINTSTATUS: | ||
192 | + case A_SECPPCINTSTAT: | ||
193 | + case A_SECPPCINTEN: | ||
194 | + case A_SECMSCINTSTAT: | ||
195 | + case A_SECMSCINTEN: | ||
196 | + case A_BRGINTSTAT: | ||
197 | + case A_BRGINTEN: | ||
198 | + case A_AHBNSPPCEXP0: | ||
199 | + case A_AHBNSPPCEXP1: | ||
200 | + case A_AHBNSPPCEXP2: | ||
201 | + case A_AHBNSPPCEXP3: | ||
202 | + case A_APBNSPPC0: | ||
203 | + case A_APBNSPPC1: | ||
204 | + case A_APBNSPPCEXP0: | ||
205 | + case A_APBNSPPCEXP1: | ||
206 | + case A_APBNSPPCEXP2: | ||
207 | + case A_APBNSPPCEXP3: | ||
208 | + case A_AHBSPPPCEXP0: | ||
209 | + case A_AHBSPPPCEXP1: | ||
210 | + case A_AHBSPPPCEXP2: | ||
211 | + case A_AHBSPPPCEXP3: | ||
212 | + case A_APBSPPPC0: | ||
213 | + case A_APBSPPPC1: | ||
214 | + case A_APBSPPPCEXP0: | ||
215 | + case A_APBSPPPCEXP1: | ||
216 | + case A_APBSPPPCEXP2: | ||
217 | + case A_APBSPPPCEXP3: | ||
218 | + case A_NSMSCEXP: | ||
219 | + qemu_log_mask(LOG_UNIMP, | ||
220 | + "IoTKit SecCtl S block read: " | ||
221 | + "unimplemented offset 0x%x\n", offset); | ||
222 | + r = 0; | ||
223 | + break; | ||
224 | + case A_PID4: | ||
225 | + case A_PID5: | ||
226 | + case A_PID6: | ||
227 | + case A_PID7: | ||
228 | + case A_PID0: | ||
229 | + case A_PID1: | ||
230 | + case A_PID2: | ||
231 | + case A_PID3: | ||
232 | + case A_CID0: | ||
233 | + case A_CID1: | ||
234 | + case A_CID2: | ||
235 | + case A_CID3: | ||
236 | + r = iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; | ||
237 | + break; | ||
238 | + case A_SECPPCINTCLR: | ||
239 | + case A_SECMSCINTCLR: | ||
240 | + case A_BRGINTCLR: | ||
241 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
242 | + "IotKit SecCtl S block read: write-only offset 0x%x\n", | ||
243 | + offset); | ||
244 | + r = 0; | ||
245 | + break; | ||
246 | + default: | ||
247 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
248 | + "IotKit SecCtl S block read: bad offset 0x%x\n", offset); | ||
249 | + r = 0; | ||
250 | + break; | ||
251 | + } | 164 | + } |
252 | + | 165 | + |
253 | + if (size != 4) { | 166 | +An alternative way to create a clock is to simply call |
254 | + /* None of our registers are access-sensitive, so just pull the right | 167 | +``object_new(TYPE_CLOCK)``. In that case the clock will neither be an |
255 | + * byte out of the word read result. | 168 | +input nor an output of a device. After the whole QOM hierarchy of the |
169 | +clock has been set ``clock_setup_canonical_path()`` should be called. | ||
170 | + | ||
171 | +At creation, the period of the clock is 0: the clock is disabled. You can | ||
172 | +change it using ``clock_set_ns()`` or ``clock_set_hz()``. | ||
173 | + | ||
174 | +Note that if you are creating a clock with a fixed period which will never | ||
175 | +change (for example the main clock source of a board), then you'll have | ||
176 | +nothing else to do. This value will be propagated to other clocks when | ||
177 | +connecting the clocks together and devices will fetch the right value during | ||
178 | +the first reset. | ||
179 | + | ||
180 | +Retrieving clocks from a device | ||
181 | +------------------------------- | ||
182 | + | ||
183 | +``qdev_get_clock_in()`` and ``dev_get_clock_out()`` are available to | ||
184 | +get the clock inputs or outputs of a device. For example: | ||
185 | + | ||
186 | +.. code-block:: c | ||
187 | + | ||
188 | + Clock *clk = qdev_get_clock_in(DEVICE(mydev), "clk_in"); | ||
189 | + | ||
190 | +or: | ||
191 | + | ||
192 | +.. code-block:: c | ||
193 | + | ||
194 | + Clock *clk = qdev_get_clock_out(DEVICE(mydev), "clk_out"); | ||
195 | + | ||
196 | +Connecting two clocks together | ||
197 | +------------------------------ | ||
198 | + | ||
199 | +To connect two clocks together, use the ``clock_set_source()`` function. | ||
200 | +Given two clocks ``clk1``, and ``clk2``, ``clock_set_source(clk2, clk1);`` | ||
201 | +configures ``clk2`` to follow the ``clk1`` period changes. Every time ``clk1`` | ||
202 | +is updated, ``clk2`` will be updated too. | ||
203 | + | ||
204 | +When connecting clock between devices, prefer using the | ||
205 | +``qdev_connect_clock_in()`` function to set the source of an input | ||
206 | +device clock. For example, to connect the input clock ``clk2`` of | ||
207 | +``devB`` to the output clock ``clk1`` of ``devA``, do: | ||
208 | + | ||
209 | +.. code-block:: c | ||
210 | + | ||
211 | + qdev_connect_clock_in(devB, "clk2", qdev_get_clock_out(devA, "clk1")) | ||
212 | + | ||
213 | +We used ``qdev_get_clock_out()`` above, but any clock can drive an | ||
214 | +input clock, even another input clock. The following diagram shows | ||
215 | +some examples of connections. Note also that a clock can drive several | ||
216 | +other clocks. | ||
217 | + | ||
218 | +:: | ||
219 | + | ||
220 | + +------------+ +--------------------------------------------------+ | ||
221 | + | Device A | | Device B | | ||
222 | + | | | +---------------------+ | | ||
223 | + | | | | Device C | | | ||
224 | + | +-------+ | | +-------+ | +-------+ +-------+ | +-------+ | | ||
225 | + | |Clock 1|>>-->>|Clock 2|>>+-->>|Clock 3| |Clock 5|>>>>|Clock 6|>> | ||
226 | + | | (out) | | | | (in) | | | | (in) | | (out) | | | (out) | | | ||
227 | + | +-------+ | | +-------+ | | +-------+ +-------+ | +-------+ | | ||
228 | + +------------+ | | +---------------------+ | | ||
229 | + | | | | ||
230 | + | | +--------------+ | | ||
231 | + | | | Device D | | | ||
232 | + | | | +-------+ | | | ||
233 | + | +-->>|Clock 4| | | | ||
234 | + | | | (in) | | | | ||
235 | + | | +-------+ | | | ||
236 | + | +--------------+ | | ||
237 | + +--------------------------------------------------+ | ||
238 | + | ||
239 | +In the above example, when *Clock 1* is updated by *Device A*, three | ||
240 | +clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*. | ||
241 | + | ||
242 | +It is not possible to disconnect a clock or to change the clock connection | ||
243 | +after it is connected. | ||
244 | + | ||
245 | +Unconnected input clocks | ||
246 | +------------------------ | ||
247 | + | ||
248 | +A newly created input clock is disabled (period of 0). This means the | ||
249 | +clock will be considered as disabled until the period is updated. If | ||
250 | +the clock remains unconnected it will always keep its initial value | ||
251 | +of 0. If this is not the desired behaviour, ``clock_set()``, | ||
252 | +``clock_set_ns()`` or ``clock_set_hz()`` should be called on the Clock | ||
253 | +object during device instance init. For example: | ||
254 | + | ||
255 | +.. code-block:: c | ||
256 | + | ||
257 | + clk = qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback, | ||
258 | + dev); | ||
259 | + /* set initial value to 10ns / 100MHz */ | ||
260 | + clock_set_ns(clk, 10); | ||
261 | + | ||
262 | +Fetching clock frequency/period | ||
263 | +------------------------------- | ||
264 | + | ||
265 | +To get the current state of a clock, use the functions ``clock_get()``, | ||
266 | +``clock_get_ns()`` or ``clock_get_hz()``. | ||
267 | + | ||
268 | +It is also possible to register a callback on clock frequency changes. | ||
269 | +Here is an example: | ||
270 | + | ||
271 | +.. code-block:: c | ||
272 | + | ||
273 | + void clock_callback(void *opaque) { | ||
274 | + MyDeviceState *s = (MyDeviceState *) opaque; | ||
275 | + /* | ||
276 | + * 'opaque' is the argument passed to qdev_init_clock_in(); | ||
277 | + * usually this will be the device state pointer. | ||
256 | + */ | 278 | + */ |
257 | + r = extract32(r, (addr & 3) * 8, size * 8); | 279 | + |
280 | + /* do something with the new period */ | ||
281 | + fprintf(stdout, "device new period is %" PRIu64 "ns\n", | ||
282 | + clock_get_ns(dev->my_clk_input)); | ||
258 | + } | 283 | + } |
259 | + | 284 | + |
260 | + trace_iotkit_secctl_s_read(offset, r, size); | 285 | +Changing a clock period |
261 | + *pdata = r; | 286 | +----------------------- |
262 | + return MEMTX_OK; | 287 | + |
263 | +} | 288 | +A device can change its outputs using the ``clock_update()``, |
264 | + | 289 | +``clock_update_ns()`` or ``clock_update_hz()`` function. It will trigger |
265 | +static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | 290 | +updates on every connected input. |
266 | + uint64_t value, | 291 | + |
267 | + unsigned size, MemTxAttrs attrs) | 292 | +For example, let's say that we have an output clock *clkout* and we |
268 | +{ | 293 | +have a pointer to it in the device state because we did the following |
269 | + uint32_t offset = addr; | 294 | +in init phase: |
270 | + | 295 | + |
271 | + trace_iotkit_secctl_s_write(offset, value, size); | 296 | +.. code-block:: c |
272 | + | 297 | + |
273 | + if (size != 4) { | 298 | + dev->clkout = qdev_init_clock_out(DEVICE(dev), "clkout"); |
274 | + /* Byte and halfword writes are ignored */ | 299 | + |
275 | + qemu_log_mask(LOG_GUEST_ERROR, | 300 | +Then at any time (apart from the cases listed below), it is possible to |
276 | + "IotKit SecCtl S block write: bad size, ignored\n"); | 301 | +change the clock value by doing: |
277 | + return MEMTX_OK; | 302 | + |
303 | +.. code-block:: c | ||
304 | + | ||
305 | + clock_update_hz(dev->clkout, 1000 * 1000 * 1000); /* 1GHz */ | ||
306 | + | ||
307 | +Because updating a clock may trigger any side effects through | ||
308 | +connected clocks and their callbacks, this operation must be done | ||
309 | +while holding the qemu io lock. | ||
310 | + | ||
311 | +For the same reason, one can update clocks only when it is allowed to have | ||
312 | +side effects on other objects. In consequence, it is forbidden: | ||
313 | + | ||
314 | +* during migration, | ||
315 | +* and in the enter phase of reset. | ||
316 | + | ||
317 | +Note that calling ``clock_update[_ns|_hz]()`` is equivalent to calling | ||
318 | +``clock_set[_ns|_hz]()`` (with the same arguments) then | ||
319 | +``clock_propagate()`` on the clock. Thus, setting the clock value can | ||
320 | +be separated from triggering the side-effects. This is often required | ||
321 | +to factorize code to handle reset and migration in devices. | ||
322 | + | ||
323 | +Aliasing clocks | ||
324 | +--------------- | ||
325 | + | ||
326 | +Sometimes, one needs to forward, or inherit, a clock from another | ||
327 | +device. Typically, when doing device composition, a device might | ||
328 | +expose a sub-device's clock without interfering with it. The function | ||
329 | +``qdev_alias_clock()`` can be used to achieve this behaviour. Note | ||
330 | +that it is possible to expose the clock under a different name. | ||
331 | +``qdev_alias_clock()`` works for both input and output clocks. | ||
332 | + | ||
333 | +For example, if device B is a child of device A, | ||
334 | +``device_a_instance_init()`` may do something like this: | ||
335 | + | ||
336 | +.. code-block:: c | ||
337 | + | ||
338 | + void device_a_instance_init(Object *obj) | ||
339 | + { | ||
340 | + AState *A = DEVICE_A(obj); | ||
341 | + BState *B; | ||
342 | + /* create object B as child of A */ | ||
343 | + [...] | ||
344 | + qdev_alias_clock(B, "clk", A, "b_clk"); | ||
345 | + /* | ||
346 | + * Now A has a clock "b_clk" which is an alias to | ||
347 | + * the clock "clk" of its child B. | ||
348 | + */ | ||
278 | + } | 349 | + } |
279 | + | 350 | + |
280 | + switch (offset) { | 351 | +This function does not return any clock object. The new clock has the |
281 | + case A_SECRESPCFG: | 352 | +same direction (input or output) as the original one. This function |
282 | + case A_NSCCFG: | 353 | +only adds a link to the existing clock. In the above example, object B |
283 | + case A_SECPPCINTCLR: | 354 | +remains the only object allowed to use the clock and device A must not |
284 | + case A_SECPPCINTEN: | 355 | +try to change the clock period or set a callback to the clock. This |
285 | + case A_SECMSCINTCLR: | 356 | +diagram describes the example with an input clock:: |
286 | + case A_SECMSCINTEN: | 357 | + |
287 | + case A_BRGINTCLR: | 358 | + +--------------------------+ |
288 | + case A_BRGINTEN: | 359 | + | Device A | |
289 | + case A_AHBNSPPCEXP0: | 360 | + | +--------------+ | |
290 | + case A_AHBNSPPCEXP1: | 361 | + | | Device B | | |
291 | + case A_AHBNSPPCEXP2: | 362 | + | | +-------+ | | |
292 | + case A_AHBNSPPCEXP3: | 363 | + >>"b_clk">>>| "clk" | | | |
293 | + case A_APBNSPPC0: | 364 | + | (in) | | (in) | | | |
294 | + case A_APBNSPPC1: | 365 | + | | +-------+ | | |
295 | + case A_APBNSPPCEXP0: | 366 | + | +--------------+ | |
296 | + case A_APBNSPPCEXP1: | 367 | + +--------------------------+ |
297 | + case A_APBNSPPCEXP2: | 368 | + |
298 | + case A_APBNSPPCEXP3: | 369 | +Migration |
299 | + case A_AHBSPPPCEXP0: | 370 | +--------- |
300 | + case A_AHBSPPPCEXP1: | 371 | + |
301 | + case A_AHBSPPPCEXP2: | 372 | +Clock state is not migrated automatically. Every device must handle its |
302 | + case A_AHBSPPPCEXP3: | 373 | +clock migration. Alias clocks must not be migrated. |
303 | + case A_APBSPPPC0: | 374 | + |
304 | + case A_APBSPPPC1: | 375 | +To ensure clock states are restored correctly during migration, there |
305 | + case A_APBSPPPCEXP0: | 376 | +are two solutions. |
306 | + case A_APBSPPPCEXP1: | 377 | + |
307 | + case A_APBSPPPCEXP2: | 378 | +Clock states can be migrated by adding an entry into the device |
308 | + case A_APBSPPPCEXP3: | 379 | +vmstate description. You should use the ``VMSTATE_CLOCK`` macro for this. |
309 | + qemu_log_mask(LOG_UNIMP, | 380 | +This is typically used to migrate an input clock state. For example: |
310 | + "IoTKit SecCtl S block write: " | 381 | + |
311 | + "unimplemented offset 0x%x\n", offset); | 382 | +.. code-block:: c |
312 | + break; | 383 | + |
313 | + case A_SECMPCINTSTATUS: | 384 | + MyDeviceState { |
314 | + case A_SECPPCINTSTAT: | 385 | + DeviceState parent_obj; |
315 | + case A_SECMSCINTSTAT: | 386 | + [...] /* some fields */ |
316 | + case A_BRGINTSTAT: | 387 | + Clock *clk; |
317 | + case A_AHBNSPPC0: | 388 | + }; |
318 | + case A_AHBSPPPC0: | 389 | + |
319 | + case A_NSMSCEXP: | 390 | + VMStateDescription my_device_vmstate = { |
320 | + case A_PID4: | 391 | + .name = "my_device", |
321 | + case A_PID5: | 392 | + .fields = (VMStateField[]) { |
322 | + case A_PID6: | 393 | + [...], /* other migrated fields */ |
323 | + case A_PID7: | 394 | + VMSTATE_CLOCK(clk, MyDeviceState), |
324 | + case A_PID0: | 395 | + VMSTATE_END_OF_LIST() |
325 | + case A_PID1: | 396 | + } |
326 | + case A_PID2: | 397 | + }; |
327 | + case A_PID3: | 398 | + |
328 | + case A_CID0: | 399 | +The second solution is to restore the clock state using information already |
329 | + case A_CID1: | 400 | +at our disposal. This can be used to restore output clock states using the |
330 | + case A_CID2: | 401 | +device state. The functions ``clock_set[_ns|_hz]()`` can be used during the |
331 | + case A_CID3: | 402 | +``post_load()`` migration callback. |
332 | + qemu_log_mask(LOG_GUEST_ERROR, | 403 | + |
333 | + "IoTKit SecCtl S block write: " | 404 | +When adding clock support to an existing device, if you care about |
334 | + "read-only offset 0x%x\n", offset); | 405 | +migration compatibility you will need to be careful, as simply adding |
335 | + break; | 406 | +a ``VMSTATE_CLOCK()`` line will break compatibility. Instead, you can |
336 | + default: | 407 | +put the ``VMSTATE_CLOCK()`` line into a vmstate subsection with a |
337 | + qemu_log_mask(LOG_GUEST_ERROR, | 408 | +suitable ``needed`` function, and use ``clock_set()`` in a |
338 | + "IotKit SecCtl S block write: bad offset 0x%x\n", | 409 | +``pre_load()`` function to set the default value that will be used if |
339 | + offset); | 410 | +the source virtual machine in the migration does not send the clock |
340 | + break; | 411 | +state. |
341 | + } | 412 | + |
342 | + | 413 | +Care should be taken not to use ``clock_update[_ns|_hz]()`` or |
343 | + return MEMTX_OK; | 414 | +``clock_propagate()`` during the whole migration procedure because it |
344 | +} | 415 | +will trigger side effects to other devices in an unknown state. |
345 | + | 416 | diff --git a/docs/devel/index.rst b/docs/devel/index.rst |
346 | +static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
347 | + uint64_t *pdata, | ||
348 | + unsigned size, MemTxAttrs attrs) | ||
349 | +{ | ||
350 | + uint64_t r; | ||
351 | + uint32_t offset = addr & ~0x3; | ||
352 | + | ||
353 | + switch (offset) { | ||
354 | + case A_AHBNSPPPC0: | ||
355 | + r = 0; | ||
356 | + break; | ||
357 | + case A_AHBNSPPPCEXP0: | ||
358 | + case A_AHBNSPPPCEXP1: | ||
359 | + case A_AHBNSPPPCEXP2: | ||
360 | + case A_AHBNSPPPCEXP3: | ||
361 | + case A_APBNSPPPC0: | ||
362 | + case A_APBNSPPPC1: | ||
363 | + case A_APBNSPPPCEXP0: | ||
364 | + case A_APBNSPPPCEXP1: | ||
365 | + case A_APBNSPPPCEXP2: | ||
366 | + case A_APBNSPPPCEXP3: | ||
367 | + qemu_log_mask(LOG_UNIMP, | ||
368 | + "IoTKit SecCtl NS block read: " | ||
369 | + "unimplemented offset 0x%x\n", offset); | ||
370 | + break; | ||
371 | + case A_PID4: | ||
372 | + case A_PID5: | ||
373 | + case A_PID6: | ||
374 | + case A_PID7: | ||
375 | + case A_PID0: | ||
376 | + case A_PID1: | ||
377 | + case A_PID2: | ||
378 | + case A_PID3: | ||
379 | + case A_CID0: | ||
380 | + case A_CID1: | ||
381 | + case A_CID2: | ||
382 | + case A_CID3: | ||
383 | + r = iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; | ||
384 | + break; | ||
385 | + default: | ||
386 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
387 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
388 | + offset); | ||
389 | + r = 0; | ||
390 | + break; | ||
391 | + } | ||
392 | + | ||
393 | + if (size != 4) { | ||
394 | + /* None of our registers are access-sensitive, so just pull the right | ||
395 | + * byte out of the word read result. | ||
396 | + */ | ||
397 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
398 | + } | ||
399 | + | ||
400 | + trace_iotkit_secctl_ns_read(offset, r, size); | ||
401 | + *pdata = r; | ||
402 | + return MEMTX_OK; | ||
403 | +} | ||
404 | + | ||
405 | +static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
406 | + uint64_t value, | ||
407 | + unsigned size, MemTxAttrs attrs) | ||
408 | +{ | ||
409 | + uint32_t offset = addr; | ||
410 | + | ||
411 | + trace_iotkit_secctl_ns_write(offset, value, size); | ||
412 | + | ||
413 | + if (size != 4) { | ||
414 | + /* Byte and halfword writes are ignored */ | ||
415 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
416 | + "IotKit SecCtl NS block write: bad size, ignored\n"); | ||
417 | + return MEMTX_OK; | ||
418 | + } | ||
419 | + | ||
420 | + switch (offset) { | ||
421 | + case A_AHBNSPPPCEXP0: | ||
422 | + case A_AHBNSPPPCEXP1: | ||
423 | + case A_AHBNSPPPCEXP2: | ||
424 | + case A_AHBNSPPPCEXP3: | ||
425 | + case A_APBNSPPPC0: | ||
426 | + case A_APBNSPPPC1: | ||
427 | + case A_APBNSPPPCEXP0: | ||
428 | + case A_APBNSPPPCEXP1: | ||
429 | + case A_APBNSPPPCEXP2: | ||
430 | + case A_APBNSPPPCEXP3: | ||
431 | + qemu_log_mask(LOG_UNIMP, | ||
432 | + "IoTKit SecCtl NS block write: " | ||
433 | + "unimplemented offset 0x%x\n", offset); | ||
434 | + break; | ||
435 | + case A_AHBNSPPPC0: | ||
436 | + case A_PID4: | ||
437 | + case A_PID5: | ||
438 | + case A_PID6: | ||
439 | + case A_PID7: | ||
440 | + case A_PID0: | ||
441 | + case A_PID1: | ||
442 | + case A_PID2: | ||
443 | + case A_PID3: | ||
444 | + case A_CID0: | ||
445 | + case A_CID1: | ||
446 | + case A_CID2: | ||
447 | + case A_CID3: | ||
448 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
449 | + "IoTKit SecCtl NS block write: " | ||
450 | + "read-only offset 0x%x\n", offset); | ||
451 | + break; | ||
452 | + default: | ||
453 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
454 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
455 | + offset); | ||
456 | + break; | ||
457 | + } | ||
458 | + | ||
459 | + return MEMTX_OK; | ||
460 | +} | ||
461 | + | ||
462 | +static const MemoryRegionOps iotkit_secctl_s_ops = { | ||
463 | + .read_with_attrs = iotkit_secctl_s_read, | ||
464 | + .write_with_attrs = iotkit_secctl_s_write, | ||
465 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
466 | + .valid.min_access_size = 1, | ||
467 | + .valid.max_access_size = 4, | ||
468 | + .impl.min_access_size = 1, | ||
469 | + .impl.max_access_size = 4, | ||
470 | +}; | ||
471 | + | ||
472 | +static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
473 | + .read_with_attrs = iotkit_secctl_ns_read, | ||
474 | + .write_with_attrs = iotkit_secctl_ns_write, | ||
475 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
476 | + .valid.min_access_size = 1, | ||
477 | + .valid.max_access_size = 4, | ||
478 | + .impl.min_access_size = 1, | ||
479 | + .impl.max_access_size = 4, | ||
480 | +}; | ||
481 | + | ||
482 | +static void iotkit_secctl_reset(DeviceState *dev) | ||
483 | +{ | ||
484 | + | ||
485 | +} | ||
486 | + | ||
487 | +static void iotkit_secctl_init(Object *obj) | ||
488 | +{ | ||
489 | + IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
490 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
491 | + | ||
492 | + memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | + s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | + memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops, | ||
495 | + s, "iotkit-secctl-ns-regs", 0x1000); | ||
496 | + sysbus_init_mmio(sbd, &s->s_regs); | ||
497 | + sysbus_init_mmio(sbd, &s->ns_regs); | ||
498 | +} | ||
499 | + | ||
500 | +static const VMStateDescription iotkit_secctl_vmstate = { | ||
501 | + .name = "iotkit-secctl", | ||
502 | + .version_id = 1, | ||
503 | + .minimum_version_id = 1, | ||
504 | + .fields = (VMStateField[]) { | ||
505 | + VMSTATE_END_OF_LIST() | ||
506 | + } | ||
507 | +}; | ||
508 | + | ||
509 | +static void iotkit_secctl_class_init(ObjectClass *klass, void *data) | ||
510 | +{ | ||
511 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
512 | + | ||
513 | + dc->vmsd = &iotkit_secctl_vmstate; | ||
514 | + dc->reset = iotkit_secctl_reset; | ||
515 | +} | ||
516 | + | ||
517 | +static const TypeInfo iotkit_secctl_info = { | ||
518 | + .name = TYPE_IOTKIT_SECCTL, | ||
519 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
520 | + .instance_size = sizeof(IoTKitSecCtl), | ||
521 | + .instance_init = iotkit_secctl_init, | ||
522 | + .class_init = iotkit_secctl_class_init, | ||
523 | +}; | ||
524 | + | ||
525 | +static void iotkit_secctl_register_types(void) | ||
526 | +{ | ||
527 | + type_register_static(&iotkit_secctl_info); | ||
528 | +} | ||
529 | + | ||
530 | +type_init(iotkit_secctl_register_types); | ||
531 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
532 | index XXXXXXX..XXXXXXX 100644 | 417 | index XXXXXXX..XXXXXXX 100644 |
533 | --- a/default-configs/arm-softmmu.mak | 418 | --- a/docs/devel/index.rst |
534 | +++ b/default-configs/arm-softmmu.mak | 419 | +++ b/docs/devel/index.rst |
535 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | 420 | @@ -XXX,XX +XXX,XX @@ Contents: |
536 | CONFIG_MPS2_SCC=y | 421 | bitops |
537 | 422 | reset | |
538 | CONFIG_TZ_PPC=y | 423 | s390-dasd-ipl |
539 | +CONFIG_IOTKIT_SECCTL=y | 424 | + clocks |
540 | |||
541 | CONFIG_VERSATILE_PCI=y | ||
542 | CONFIG_VERSATILE_I2C=y | ||
543 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
544 | index XXXXXXX..XXXXXXX 100644 | ||
545 | --- a/hw/misc/trace-events | ||
546 | +++ b/hw/misc/trace-events | ||
547 | @@ -XXX,XX +XXX,XX @@ tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
548 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
549 | tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
550 | tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
551 | + | ||
552 | +# hw/misc/iotkit-secctl.c | ||
553 | +iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
554 | +iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
555 | +iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
556 | +iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
557 | +iotkit_secctl_reset(void) "IoTKit SecCtl: reset" | ||
558 | -- | 425 | -- |
559 | 2.16.2 | 426 | 2.20.1 |
560 | 427 | ||
561 | 428 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | 2 | ||
3 | Not enabled anywhere yet. | 3 | Add some clocks to zynq_slcr |
4 | 4 | + the main input clock (ps_clk) | |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | + the reference clock outputs for each uart (uart0 & 1) |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | This commit also transitional the slcr to multi-phase reset as it is |
8 | Message-id: 20180228193125.20577-2-richard.henderson@linaro.org | 8 | required to initialize the clocks correctly. |
9 | |||
10 | The clock frequencies are computed using the internal pll & uart configuration | ||
11 | registers and the input ps_clk frequency. | ||
12 | |||
13 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
14 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
15 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | Message-id: 20200406135251.157596-7-damien.hedde@greensocs.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 18 | --- |
11 | target/arm/cpu.h | 1 + | 19 | hw/misc/zynq_slcr.c | 172 ++++++++++++++++++++++++++++++++++++++++++-- |
12 | linux-user/elfload.c | 1 + | 20 | 1 file changed, 168 insertions(+), 4 deletions(-) |
13 | 2 files changed, 2 insertions(+) | 21 | |
14 | 22 | diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c | |
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 24 | --- a/hw/misc/zynq_slcr.c |
18 | +++ b/target/arm/cpu.h | 25 | +++ b/hw/misc/zynq_slcr.c |
19 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 26 | @@ -XXX,XX +XXX,XX @@ |
20 | ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ | 27 | #include "qemu/log.h" |
21 | ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ | 28 | #include "qemu/module.h" |
22 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | 29 | #include "hw/registerfields.h" |
23 | + ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | 30 | +#include "hw/qdev-clock.h" |
24 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | 31 | |
32 | #ifndef ZYNQ_SLCR_ERR_DEBUG | ||
33 | #define ZYNQ_SLCR_ERR_DEBUG 0 | ||
34 | @@ -XXX,XX +XXX,XX @@ REG32(LOCKSTA, 0x00c) | ||
35 | REG32(ARM_PLL_CTRL, 0x100) | ||
36 | REG32(DDR_PLL_CTRL, 0x104) | ||
37 | REG32(IO_PLL_CTRL, 0x108) | ||
38 | +/* fields for [ARM|DDR|IO]_PLL_CTRL registers */ | ||
39 | + FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1) | ||
40 | + FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1) | ||
41 | + FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1) | ||
42 | + FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1) | ||
43 | + FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7) | ||
44 | REG32(PLL_STATUS, 0x10c) | ||
45 | REG32(ARM_PLL_CFG, 0x110) | ||
46 | REG32(DDR_PLL_CFG, 0x114) | ||
47 | @@ -XXX,XX +XXX,XX @@ REG32(SMC_CLK_CTRL, 0x148) | ||
48 | REG32(LQSPI_CLK_CTRL, 0x14c) | ||
49 | REG32(SDIO_CLK_CTRL, 0x150) | ||
50 | REG32(UART_CLK_CTRL, 0x154) | ||
51 | + FIELD(UART_CLK_CTRL, CLKACT0, 0, 1) | ||
52 | + FIELD(UART_CLK_CTRL, CLKACT1, 1, 1) | ||
53 | + FIELD(UART_CLK_CTRL, SRCSEL, 4, 2) | ||
54 | + FIELD(UART_CLK_CTRL, DIVISOR, 8, 6) | ||
55 | REG32(SPI_CLK_CTRL, 0x158) | ||
56 | REG32(CAN_CLK_CTRL, 0x15c) | ||
57 | REG32(CAN_MIOCLK_CTRL, 0x160) | ||
58 | @@ -XXX,XX +XXX,XX @@ typedef struct ZynqSLCRState { | ||
59 | MemoryRegion iomem; | ||
60 | |||
61 | uint32_t regs[ZYNQ_SLCR_NUM_REGS]; | ||
62 | + | ||
63 | + Clock *ps_clk; | ||
64 | + Clock *uart0_ref_clk; | ||
65 | + Clock *uart1_ref_clk; | ||
66 | } ZynqSLCRState; | ||
67 | |||
68 | -static void zynq_slcr_reset(DeviceState *d) | ||
69 | +/* | ||
70 | + * return the output frequency of ARM/DDR/IO pll | ||
71 | + * using input frequency and PLL_CTRL register | ||
72 | + */ | ||
73 | +static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg) | ||
74 | { | ||
75 | - ZynqSLCRState *s = ZYNQ_SLCR(d); | ||
76 | + uint32_t mult = ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >> | ||
77 | + R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT); | ||
78 | + | ||
79 | + /* first, check if pll is bypassed */ | ||
80 | + if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) { | ||
81 | + return input; | ||
82 | + } | ||
83 | + | ||
84 | + /* is pll disabled ? */ | ||
85 | + if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK | | ||
86 | + R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) { | ||
87 | + return 0; | ||
88 | + } | ||
89 | + | ||
90 | + /* frequency multiplier -> period division */ | ||
91 | + return input / mult; | ||
92 | +} | ||
93 | + | ||
94 | +/* | ||
95 | + * return the output period of a clock given: | ||
96 | + * + the periods in an array corresponding to input mux selector | ||
97 | + * + the register xxx_CLK_CTRL value | ||
98 | + * + enable bit index in ctrl register | ||
99 | + * | ||
100 | + * This function makes the assumption that the ctrl_reg value is organized as | ||
101 | + * follows: | ||
102 | + * + bits[13:8] clock frequency divisor | ||
103 | + * + bits[5:4] clock mux selector (index in array) | ||
104 | + * + bits[index] clock enable | ||
105 | + */ | ||
106 | +static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], | ||
107 | + uint32_t ctrl_reg, | ||
108 | + unsigned index) | ||
109 | +{ | ||
110 | + uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */ | ||
111 | + uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */ | ||
112 | + | ||
113 | + /* first, check if clock is disabled */ | ||
114 | + if (((ctrl_reg >> index) & 1u) == 0) { | ||
115 | + return 0; | ||
116 | + } | ||
117 | + | ||
118 | + /* | ||
119 | + * according to the Zynq technical ref. manual UG585 v1.12.2 in | ||
120 | + * Clocks chapter, section 25.10.1 page 705: | ||
121 | + * "The 6-bit divider provides a divide range of 1 to 63" | ||
122 | + * We follow here what is implemented in linux kernel and consider | ||
123 | + * the 0 value as a bypass (no division). | ||
124 | + */ | ||
125 | + /* frequency divisor -> period multiplication */ | ||
126 | + return periods[srcsel] * (divisor ? divisor : 1u); | ||
127 | +} | ||
128 | + | ||
129 | +/* | ||
130 | + * macro helper around zynq_slcr_compute_clock to avoid repeating | ||
131 | + * the register name. | ||
132 | + */ | ||
133 | +#define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ | ||
134 | + zynq_slcr_compute_clock((plls), (state)->regs[reg], \ | ||
135 | + reg ## _ ## enable_field ## _SHIFT) | ||
136 | + | ||
137 | +/** | ||
138 | + * Compute and set the ouputs clocks periods. | ||
139 | + * But do not propagate them further. Connected clocks | ||
140 | + * will not receive any updates (See zynq_slcr_compute_clocks()) | ||
141 | + */ | ||
142 | +static void zynq_slcr_compute_clocks(ZynqSLCRState *s) | ||
143 | +{ | ||
144 | + uint64_t ps_clk = clock_get(s->ps_clk); | ||
145 | + | ||
146 | + /* consider outputs clocks are disabled while in reset */ | ||
147 | + if (device_is_in_reset(DEVICE(s))) { | ||
148 | + ps_clk = 0; | ||
149 | + } | ||
150 | + | ||
151 | + uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]); | ||
152 | + uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]); | ||
153 | + uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]); | ||
154 | + | ||
155 | + uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll}; | ||
156 | + | ||
157 | + /* compute uartX reference clocks */ | ||
158 | + clock_set(s->uart0_ref_clk, | ||
159 | + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); | ||
160 | + clock_set(s->uart1_ref_clk, | ||
161 | + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); | ||
162 | +} | ||
163 | + | ||
164 | +/** | ||
165 | + * Propagate the outputs clocks. | ||
166 | + * zynq_slcr_compute_clocks() should have been called before | ||
167 | + * to configure them. | ||
168 | + */ | ||
169 | +static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) | ||
170 | +{ | ||
171 | + clock_propagate(s->uart0_ref_clk); | ||
172 | + clock_propagate(s->uart1_ref_clk); | ||
173 | +} | ||
174 | + | ||
175 | +static void zynq_slcr_ps_clk_callback(void *opaque) | ||
176 | +{ | ||
177 | + ZynqSLCRState *s = (ZynqSLCRState *) opaque; | ||
178 | + zynq_slcr_compute_clocks(s); | ||
179 | + zynq_slcr_propagate_clocks(s); | ||
180 | +} | ||
181 | + | ||
182 | +static void zynq_slcr_reset_init(Object *obj, ResetType type) | ||
183 | +{ | ||
184 | + ZynqSLCRState *s = ZYNQ_SLCR(obj); | ||
185 | int i; | ||
186 | |||
187 | DB_PRINT("RESET\n"); | ||
188 | @@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d) | ||
189 | s->regs[R_DDRIOB + 12] = 0x00000021; | ||
190 | } | ||
191 | |||
192 | +static void zynq_slcr_reset_hold(Object *obj) | ||
193 | +{ | ||
194 | + ZynqSLCRState *s = ZYNQ_SLCR(obj); | ||
195 | + | ||
196 | + /* will disable all output clocks */ | ||
197 | + zynq_slcr_compute_clocks(s); | ||
198 | + zynq_slcr_propagate_clocks(s); | ||
199 | +} | ||
200 | + | ||
201 | +static void zynq_slcr_reset_exit(Object *obj) | ||
202 | +{ | ||
203 | + ZynqSLCRState *s = ZYNQ_SLCR(obj); | ||
204 | + | ||
205 | + /* will compute output clocks according to ps_clk and registers */ | ||
206 | + zynq_slcr_compute_clocks(s); | ||
207 | + zynq_slcr_propagate_clocks(s); | ||
208 | +} | ||
209 | |||
210 | static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) | ||
211 | { | ||
212 | @@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset, | ||
213 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
214 | } | ||
215 | break; | ||
216 | + case R_IO_PLL_CTRL: | ||
217 | + case R_ARM_PLL_CTRL: | ||
218 | + case R_DDR_PLL_CTRL: | ||
219 | + case R_UART_CLK_CTRL: | ||
220 | + zynq_slcr_compute_clocks(s); | ||
221 | + zynq_slcr_propagate_clocks(s); | ||
222 | + break; | ||
223 | } | ||
224 | } | ||
225 | |||
226 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps slcr_ops = { | ||
227 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
25 | }; | 228 | }; |
26 | 229 | ||
27 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 230 | +static const ClockPortInitArray zynq_slcr_clocks = { |
28 | index XXXXXXX..XXXXXXX 100644 | 231 | + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), |
29 | --- a/linux-user/elfload.c | 232 | + QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), |
30 | +++ b/linux-user/elfload.c | 233 | + QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | 234 | + QDEV_CLOCK_END |
32 | GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); | 235 | +}; |
33 | GET_FEATURE(ARM_FEATURE_V8_FP16, | 236 | + |
34 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | 237 | static void zynq_slcr_init(Object *obj) |
35 | + GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | 238 | { |
36 | #undef GET_FEATURE | 239 | ZynqSLCRState *s = ZYNQ_SLCR(obj); |
37 | 240 | @@ -XXX,XX +XXX,XX @@ static void zynq_slcr_init(Object *obj) | |
38 | return hwcaps; | 241 | memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", |
242 | ZYNQ_SLCR_MMIO_SIZE); | ||
243 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | ||
244 | + | ||
245 | + qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); | ||
246 | } | ||
247 | |||
248 | static const VMStateDescription vmstate_zynq_slcr = { | ||
249 | .name = "zynq_slcr", | ||
250 | - .version_id = 2, | ||
251 | + .version_id = 3, | ||
252 | .minimum_version_id = 2, | ||
253 | .fields = (VMStateField[]) { | ||
254 | VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS), | ||
255 | + VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3), | ||
256 | VMSTATE_END_OF_LIST() | ||
257 | } | ||
258 | }; | ||
259 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_zynq_slcr = { | ||
260 | static void zynq_slcr_class_init(ObjectClass *klass, void *data) | ||
261 | { | ||
262 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
263 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
264 | |||
265 | dc->vmsd = &vmstate_zynq_slcr; | ||
266 | - dc->reset = zynq_slcr_reset; | ||
267 | + rc->phases.enter = zynq_slcr_reset_init; | ||
268 | + rc->phases.hold = zynq_slcr_reset_hold; | ||
269 | + rc->phases.exit = zynq_slcr_reset_exit; | ||
270 | } | ||
271 | |||
272 | static const TypeInfo zynq_slcr_info = { | ||
39 | -- | 273 | -- |
40 | 2.16.2 | 274 | 2.20.1 |
41 | 275 | ||
42 | 276 | diff view generated by jsdifflib |
1 | Model the Arm IoT Kit documented in | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 2 | |
3 | 3 | Switch the cadence uart to multi-phase reset and add the | |
4 | The Arm IoT Kit is a subsystem which includes a CPU and some devices, | 4 | reference clock input. |
5 | and is intended be extended by adding extra devices to form a | 5 | |
6 | complete system. It is used in the MPS2 board's AN505 image for the | 6 | The input clock frequency is added to the migration structure. |
7 | Cortex-M33. | 7 | |
8 | 8 | The reference clock controls the baudrate generation. If it disabled, | |
9 | any input characters and events are ignored. | ||
10 | |||
11 | If this clock remains unconnected, the uart behaves as before | ||
12 | (it default to a 50MHz ref clock). | ||
13 | |||
14 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
15 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
16 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20180220180325.29818-19-peter.maydell@linaro.org | ||
12 | --- | 19 | --- |
13 | hw/arm/Makefile.objs | 1 + | 20 | include/hw/char/cadence_uart.h | 1 + |
14 | include/hw/arm/iotkit.h | 109 ++++++++ | 21 | hw/char/cadence_uart.c | 73 +++++++++++++++++++++++++++++----- |
15 | hw/arm/iotkit.c | 598 ++++++++++++++++++++++++++++++++++++++++ | 22 | hw/char/trace-events | 3 ++ |
16 | default-configs/arm-softmmu.mak | 1 + | 23 | 3 files changed, 67 insertions(+), 10 deletions(-) |
17 | 4 files changed, 709 insertions(+) | 24 | |
18 | create mode 100644 include/hw/arm/iotkit.h | 25 | diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h |
19 | create mode 100644 hw/arm/iotkit.c | ||
20 | |||
21 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
22 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/Makefile.objs | 27 | --- a/include/hw/char/cadence_uart.h |
24 | +++ b/hw/arm/Makefile.objs | 28 | +++ b/include/hw/char/cadence_uart.h |
25 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 29 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
26 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 30 | CharBackend chr; |
27 | obj-$(CONFIG_MPS2) += mps2.o | 31 | qemu_irq irq; |
28 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 32 | QEMUTimer *fifo_trigger_handle; |
29 | +obj-$(CONFIG_IOTKIT) += iotkit.o | 33 | + Clock *refclk; |
30 | diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h | 34 | } CadenceUARTState; |
31 | new file mode 100644 | 35 | |
32 | index XXXXXXX..XXXXXXX | 36 | static inline DeviceState *cadence_uart_create(hwaddr addr, |
33 | --- /dev/null | 37 | diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c |
34 | +++ b/include/hw/arm/iotkit.h | 38 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/hw/char/cadence_uart.c | ||
40 | +++ b/hw/char/cadence_uart.c | ||
35 | @@ -XXX,XX +XXX,XX @@ | 41 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 42 | #include "qemu/module.h" |
37 | + * ARM IoT Kit | 43 | #include "hw/char/cadence_uart.h" |
38 | + * | 44 | #include "hw/irq.h" |
39 | + * Copyright (c) 2018 Linaro Limited | 45 | +#include "hw/qdev-clock.h" |
40 | + * Written by Peter Maydell | 46 | +#include "trace.h" |
41 | + * | 47 | |
42 | + * This program is free software; you can redistribute it and/or modify | 48 | #ifdef CADENCE_UART_ERR_DEBUG |
43 | + * it under the terms of the GNU General Public License version 2 or | 49 | #define DB_PRINT(...) do { \ |
44 | + * (at your option) any later version. | ||
45 | + */ | ||
46 | + | ||
47 | +/* This is a model of the Arm IoT Kit which is documented in | ||
48 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
49 | + * It contains: | ||
50 | + * a Cortex-M33 | ||
51 | + * the IDAU | ||
52 | + * some timers and watchdogs | ||
53 | + * two peripheral protection controllers | ||
54 | + * a memory protection controller | ||
55 | + * a security controller | ||
56 | + * a bus fabric which arranges that some parts of the address | ||
57 | + * space are secure and non-secure aliases of each other | ||
58 | + * | ||
59 | + * QEMU interface: | ||
60 | + * + QOM property "memory" is a MemoryRegion containing the devices provided | ||
61 | + * by the board model. | ||
62 | + * + QOM property "MAINCLK" is the frequency of the main system clock | ||
63 | + * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts | ||
64 | + * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which | ||
65 | + * are wired to the NVIC lines 32 .. n+32 | ||
66 | + * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit | ||
67 | + * might provide: | ||
68 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
69 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
70 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
71 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
72 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
73 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
74 | + * might provide: | ||
75 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
76 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
77 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
78 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
79 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
80 | + */ | ||
81 | + | ||
82 | +#ifndef IOTKIT_H | ||
83 | +#define IOTKIT_H | ||
84 | + | ||
85 | +#include "hw/sysbus.h" | ||
86 | +#include "hw/arm/armv7m.h" | ||
87 | +#include "hw/misc/iotkit-secctl.h" | ||
88 | +#include "hw/misc/tz-ppc.h" | ||
89 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
90 | +#include "hw/misc/unimp.h" | ||
91 | +#include "hw/or-irq.h" | ||
92 | +#include "hw/core/split-irq.h" | ||
93 | + | ||
94 | +#define TYPE_IOTKIT "iotkit" | ||
95 | +#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) | ||
96 | + | ||
97 | +/* We have an IRQ splitter and an OR gate input for each external PPC | ||
98 | + * and the 2 internal PPCs | ||
99 | + */ | ||
100 | +#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) | ||
101 | +#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) | ||
102 | + | ||
103 | +typedef struct IoTKit { | ||
104 | + /*< private >*/ | ||
105 | + SysBusDevice parent_obj; | ||
106 | + | ||
107 | + /*< public >*/ | ||
108 | + ARMv7MState armv7m; | ||
109 | + IoTKitSecCtl secctl; | ||
110 | + TZPPC apb_ppc0; | ||
111 | + TZPPC apb_ppc1; | ||
112 | + CMSDKAPBTIMER timer0; | ||
113 | + CMSDKAPBTIMER timer1; | ||
114 | + qemu_or_irq ppc_irq_orgate; | ||
115 | + SplitIRQ sec_resp_splitter; | ||
116 | + SplitIRQ ppc_irq_splitter[NUM_PPCS]; | ||
117 | + | ||
118 | + UnimplementedDeviceState dualtimer; | ||
119 | + UnimplementedDeviceState s32ktimer; | ||
120 | + | ||
121 | + MemoryRegion container; | ||
122 | + MemoryRegion alias1; | ||
123 | + MemoryRegion alias2; | ||
124 | + MemoryRegion alias3; | ||
125 | + MemoryRegion sram0; | ||
126 | + | ||
127 | + qemu_irq *exp_irqs; | ||
128 | + qemu_irq ppc0_irq; | ||
129 | + qemu_irq ppc1_irq; | ||
130 | + qemu_irq sec_resp_cfg; | ||
131 | + qemu_irq sec_resp_cfg_in; | ||
132 | + qemu_irq nsc_cfg_in; | ||
133 | + | ||
134 | + qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; | ||
135 | + | ||
136 | + uint32_t nsccfg; | ||
137 | + | ||
138 | + /* Properties */ | ||
139 | + MemoryRegion *board_memory; | ||
140 | + uint32_t exp_numirq; | ||
141 | + uint32_t mainclk_frq; | ||
142 | +} IoTKit; | ||
143 | + | ||
144 | +#endif | ||
145 | diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c | ||
146 | new file mode 100644 | ||
147 | index XXXXXXX..XXXXXXX | ||
148 | --- /dev/null | ||
149 | +++ b/hw/arm/iotkit.c | ||
150 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ |
151 | +/* | 51 | #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) |
152 | + * Arm IoT Kit | 52 | #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) |
153 | + * | 53 | |
154 | + * Copyright (c) 2018 Linaro Limited | 54 | -#define UART_INPUT_CLK 50000000 |
155 | + * Written by Peter Maydell | 55 | +#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000) |
156 | + * | 56 | |
157 | + * This program is free software; you can redistribute it and/or modify | 57 | #define R_CR (0x00/4) |
158 | + * it under the terms of the GNU General Public License version 2 or | 58 | #define R_MR (0x04/4) |
159 | + * (at your option) any later version. | 59 | @@ -XXX,XX +XXX,XX @@ static void uart_send_breaks(CadenceUARTState *s) |
160 | + */ | 60 | static void uart_parameters_setup(CadenceUARTState *s) |
161 | + | 61 | { |
162 | +#include "qemu/osdep.h" | 62 | QEMUSerialSetParams ssp; |
163 | +#include "qemu/log.h" | 63 | - unsigned int baud_rate, packet_size; |
164 | +#include "qapi/error.h" | 64 | + unsigned int baud_rate, packet_size, input_clk; |
165 | +#include "trace.h" | 65 | + input_clk = clock_get_hz(s->refclk); |
166 | +#include "hw/sysbus.h" | 66 | |
167 | +#include "hw/registerfields.h" | 67 | - baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? |
168 | +#include "hw/arm/iotkit.h" | 68 | - UART_INPUT_CLK / 8 : UART_INPUT_CLK; |
169 | +#include "hw/misc/unimp.h" | 69 | + baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; |
170 | +#include "hw/arm/arm.h" | 70 | + baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); |
171 | + | 71 | + trace_cadence_uart_baudrate(baud_rate); |
172 | +/* Create an alias region of @size bytes starting at @base | 72 | + |
173 | + * which mirrors the memory starting at @orig. | 73 | + ssp.speed = baud_rate; |
174 | + */ | 74 | |
175 | +static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, | 75 | - ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); |
176 | + hwaddr base, hwaddr size, hwaddr orig) | 76 | packet_size = 1; |
177 | +{ | 77 | |
178 | + memory_region_init_alias(mr, NULL, name, &s->container, orig, size); | 78 | switch (s->r[R_MR] & UART_MR_PAR) { |
179 | + /* The alias is even lower priority than unimplemented_device regions */ | 79 | @@ -XXX,XX +XXX,XX @@ static void uart_parameters_setup(CadenceUARTState *s) |
180 | + memory_region_add_subregion_overlap(&s->container, base, mr, -1500); | 80 | } |
181 | +} | 81 | |
182 | + | 82 | packet_size += ssp.data_bits + ssp.stop_bits; |
183 | +static void init_sysbus_child(Object *parent, const char *childname, | 83 | + if (ssp.speed == 0) { |
184 | + void *child, size_t childsize, | 84 | + /* |
185 | + const char *childtype) | 85 | + * Avoid division-by-zero below. |
186 | +{ | 86 | + * TODO: find something better |
187 | + object_initialize(child, childsize, childtype); | 87 | + */ |
188 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | 88 | + ssp.speed = 1; |
189 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
190 | +} | ||
191 | + | ||
192 | +static void irq_status_forwarder(void *opaque, int n, int level) | ||
193 | +{ | ||
194 | + qemu_irq destirq = opaque; | ||
195 | + | ||
196 | + qemu_set_irq(destirq, level); | ||
197 | +} | ||
198 | + | ||
199 | +static void nsccfg_handler(void *opaque, int n, int level) | ||
200 | +{ | ||
201 | + IoTKit *s = IOTKIT(opaque); | ||
202 | + | ||
203 | + s->nsccfg = level; | ||
204 | +} | ||
205 | + | ||
206 | +static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) | ||
207 | +{ | ||
208 | + /* Each of the 4 AHB and 4 APB PPCs that might be present in a | ||
209 | + * system using the IoTKit has a collection of control lines which | ||
210 | + * are provided by the security controller and which we want to | ||
211 | + * expose as control lines on the IoTKit device itself, so the | ||
212 | + * code using the IoTKit can wire them up to the PPCs. | ||
213 | + */ | ||
214 | + SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; | ||
215 | + DeviceState *iotkitdev = DEVICE(s); | ||
216 | + DeviceState *dev_secctl = DEVICE(&s->secctl); | ||
217 | + DeviceState *dev_splitter = DEVICE(splitter); | ||
218 | + char *name; | ||
219 | + | ||
220 | + name = g_strdup_printf("%s_nonsec", ppcname); | ||
221 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
222 | + g_free(name); | ||
223 | + name = g_strdup_printf("%s_ap", ppcname); | ||
224 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
225 | + g_free(name); | ||
226 | + name = g_strdup_printf("%s_irq_enable", ppcname); | ||
227 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
228 | + g_free(name); | ||
229 | + name = g_strdup_printf("%s_irq_clear", ppcname); | ||
230 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
231 | + g_free(name); | ||
232 | + | ||
233 | + /* irq_status is a little more tricky, because we need to | ||
234 | + * split it so we can send it both to the security controller | ||
235 | + * and to our OR gate for the NVIC interrupt line. | ||
236 | + * Connect up the splitter's outputs, and create a GPIO input | ||
237 | + * which will pass the line state to the input splitter. | ||
238 | + */ | ||
239 | + name = g_strdup_printf("%s_irq_status", ppcname); | ||
240 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
241 | + qdev_get_gpio_in_named(dev_secctl, | ||
242 | + name, 0)); | ||
243 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
244 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); | ||
245 | + s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); | ||
246 | + qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, | ||
247 | + s->irq_status_in[ppcnum], name, 1); | ||
248 | + g_free(name); | ||
249 | +} | ||
250 | + | ||
251 | +static void iotkit_forward_sec_resp_cfg(IoTKit *s) | ||
252 | +{ | ||
253 | + /* Forward the 3rd output from the splitter device as a | ||
254 | + * named GPIO output of the iotkit object. | ||
255 | + */ | ||
256 | + DeviceState *dev = DEVICE(s); | ||
257 | + DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
258 | + | ||
259 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
260 | + s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, | ||
261 | + s->sec_resp_cfg, 1); | ||
262 | + qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); | ||
263 | +} | ||
264 | + | ||
265 | +static void iotkit_init(Object *obj) | ||
266 | +{ | ||
267 | + IoTKit *s = IOTKIT(obj); | ||
268 | + int i; | ||
269 | + | ||
270 | + memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); | ||
271 | + | ||
272 | + init_sysbus_child(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), | ||
273 | + TYPE_ARMV7M); | ||
274 | + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", | ||
275 | + ARM_CPU_TYPE_NAME("cortex-m33")); | ||
276 | + | ||
277 | + init_sysbus_child(obj, "secctl", &s->secctl, sizeof(s->secctl), | ||
278 | + TYPE_IOTKIT_SECCTL); | ||
279 | + init_sysbus_child(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), | ||
280 | + TYPE_TZ_PPC); | ||
281 | + init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), | ||
282 | + TYPE_TZ_PPC); | ||
283 | + init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0), | ||
284 | + TYPE_CMSDK_APB_TIMER); | ||
285 | + init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1), | ||
286 | + TYPE_CMSDK_APB_TIMER); | ||
287 | + init_sysbus_child(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), | ||
288 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
289 | + object_initialize(&s->ppc_irq_orgate, sizeof(s->ppc_irq_orgate), | ||
290 | + TYPE_OR_IRQ); | ||
291 | + object_property_add_child(obj, "ppc-irq-orgate", | ||
292 | + OBJECT(&s->ppc_irq_orgate), &error_abort); | ||
293 | + object_initialize(&s->sec_resp_splitter, sizeof(s->sec_resp_splitter), | ||
294 | + TYPE_SPLIT_IRQ); | ||
295 | + object_property_add_child(obj, "sec-resp-splitter", | ||
296 | + OBJECT(&s->sec_resp_splitter), &error_abort); | ||
297 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
298 | + char *name = g_strdup_printf("ppc-irq-splitter-%d", i); | ||
299 | + SplitIRQ *splitter = &s->ppc_irq_splitter[i]; | ||
300 | + | ||
301 | + object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ); | ||
302 | + object_property_add_child(obj, name, OBJECT(splitter), &error_abort); | ||
303 | + } | 89 | + } |
304 | + init_sysbus_child(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), | 90 | s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; |
305 | + TYPE_UNIMPLEMENTED_DEVICE); | 91 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
306 | +} | 92 | } |
307 | + | 93 | @@ -XXX,XX +XXX,XX @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) |
308 | +static void iotkit_exp_irq(void *opaque, int n, int level) | 94 | CadenceUARTState *s = opaque; |
309 | +{ | 95 | uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; |
310 | + IoTKit *s = IOTKIT(opaque); | 96 | |
311 | + | 97 | + /* ignore characters when unclocked or in reset */ |
312 | + qemu_set_irq(s->exp_irqs[n], level); | 98 | + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { |
313 | +} | ||
314 | + | ||
315 | +static void iotkit_realize(DeviceState *dev, Error **errp) | ||
316 | +{ | ||
317 | + IoTKit *s = IOTKIT(dev); | ||
318 | + int i; | ||
319 | + MemoryRegion *mr; | ||
320 | + Error *err = NULL; | ||
321 | + SysBusDevice *sbd_apb_ppc0; | ||
322 | + SysBusDevice *sbd_secctl; | ||
323 | + DeviceState *dev_apb_ppc0; | ||
324 | + DeviceState *dev_apb_ppc1; | ||
325 | + DeviceState *dev_secctl; | ||
326 | + DeviceState *dev_splitter; | ||
327 | + | ||
328 | + if (!s->board_memory) { | ||
329 | + error_setg(errp, "memory property was not set"); | ||
330 | + return; | 99 | + return; |
331 | + } | 100 | + } |
332 | + | 101 | + |
333 | + if (!s->mainclk_frq) { | 102 | if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { |
334 | + error_setg(errp, "MAINCLK property was not set"); | 103 | uart_write_rx_fifo(opaque, buf, size); |
104 | } | ||
105 | @@ -XXX,XX +XXX,XX @@ static void uart_event(void *opaque, QEMUChrEvent event) | ||
106 | CadenceUARTState *s = opaque; | ||
107 | uint8_t buf = '\0'; | ||
108 | |||
109 | + /* ignore characters when unclocked or in reset */ | ||
110 | + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { | ||
335 | + return; | 111 | + return; |
336 | + } | 112 | + } |
337 | + | 113 | + |
338 | + /* Handling of which devices should be available only to secure | 114 | if (event == CHR_EVENT_BREAK) { |
339 | + * code is usually done differently for M profile than for A profile. | 115 | uart_write_rx_fifo(opaque, &buf, 1); |
340 | + * Instead of putting some devices only into the secure address space, | 116 | } |
341 | + * devices exist in both address spaces but with hard-wired security | 117 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps uart_ops = { |
342 | + * permissions that will cause the CPU to fault for non-secure accesses. | 118 | .endianness = DEVICE_NATIVE_ENDIAN, |
343 | + * | 119 | }; |
344 | + * The IoTKit has an IDAU (Implementation Defined Access Unit), | 120 | |
345 | + * which specifies hard-wired security permissions for different | 121 | -static void cadence_uart_reset(DeviceState *dev) |
346 | + * areas of the physical address space. For the IoTKit IDAU, the | 122 | +static void cadence_uart_reset_init(Object *obj, ResetType type) |
347 | + * top 4 bits of the physical address are the IDAU region ID, and | 123 | { |
348 | + * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS | 124 | - CadenceUARTState *s = CADENCE_UART(dev); |
349 | + * region, otherwise it is an S region. | 125 | + CadenceUARTState *s = CADENCE_UART(obj); |
350 | + * | 126 | |
351 | + * The various devices and RAMs are generally all mapped twice, | 127 | s->r[R_CR] = 0x00000128; |
352 | + * once into a region that the IDAU defines as secure and once | 128 | s->r[R_IMR] = 0; |
353 | + * into a non-secure region. They sit behind either a Memory | 129 | @@ -XXX,XX +XXX,XX @@ static void cadence_uart_reset(DeviceState *dev) |
354 | + * Protection Controller (for RAM) or a Peripheral Protection | 130 | s->r[R_BRGR] = 0x0000028B; |
355 | + * Controller (for devices), which allow a more fine grained | 131 | s->r[R_BDIV] = 0x0000000F; |
356 | + * configuration of whether non-secure accesses are permitted. | 132 | s->r[R_TTRIG] = 0x00000020; |
357 | + * | ||
358 | + * (The other place that guest software can configure security | ||
359 | + * permissions is in the architected SAU (Security Attribution | ||
360 | + * Unit), which is entirely inside the CPU. The IDAU can upgrade | ||
361 | + * the security attributes for a region to more restrictive than | ||
362 | + * the SAU specifies, but cannot downgrade them.) | ||
363 | + * | ||
364 | + * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff | ||
365 | + * 0x20000000..0x2007ffff 32KB FPGA block RAM | ||
366 | + * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff | ||
367 | + * 0x40000000..0x4000ffff base peripheral region 1 | ||
368 | + * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) | ||
369 | + * 0x40020000..0x4002ffff system control element peripherals | ||
370 | + * 0x40080000..0x400fffff base peripheral region 2 | ||
371 | + * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff | ||
372 | + */ | ||
373 | + | ||
374 | + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | ||
375 | + | ||
376 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32); | ||
377 | + /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 | ||
378 | + * register in the IoT Kit System Control Register block, and the | ||
379 | + * initial value of that is in turn specifiable by the FPGA that | ||
380 | + * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, | ||
381 | + * and simply set the CPU's init-svtor to the IoT Kit default value. | ||
382 | + */ | ||
383 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); | ||
384 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), | ||
385 | + "memory", &err); | ||
386 | + if (err) { | ||
387 | + error_propagate(errp, err); | ||
388 | + return; | ||
389 | + } | ||
390 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); | ||
391 | + if (err) { | ||
392 | + error_propagate(errp, err); | ||
393 | + return; | ||
394 | + } | ||
395 | + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | ||
396 | + if (err) { | ||
397 | + error_propagate(errp, err); | ||
398 | + return; | ||
399 | + } | ||
400 | + | ||
401 | + /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ | ||
402 | + s->exp_irqs = g_new(qemu_irq, s->exp_numirq); | ||
403 | + for (i = 0; i < s->exp_numirq; i++) { | ||
404 | + s->exp_irqs[i] = qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); | ||
405 | + } | ||
406 | + qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); | ||
407 | + | ||
408 | + /* Set up the big aliases first */ | ||
409 | + make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); | ||
410 | + make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); | ||
411 | + /* The 0x50000000..0x5fffffff region is not a pure alias: it has | ||
412 | + * a few extra devices that only appear there (generally the | ||
413 | + * control interfaces for the protection controllers). | ||
414 | + * We implement this by mapping those devices over the top of this | ||
415 | + * alias MR at a higher priority. | ||
416 | + */ | ||
417 | + make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); | ||
418 | + | ||
419 | + /* This RAM should be behind a Memory Protection Controller, but we | ||
420 | + * don't implement that yet. | ||
421 | + */ | ||
422 | + memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err); | ||
423 | + if (err) { | ||
424 | + error_propagate(errp, err); | ||
425 | + return; | ||
426 | + } | ||
427 | + memory_region_add_subregion(&s->container, 0x20000000, &s->sram0); | ||
428 | + | ||
429 | + /* Security controller */ | ||
430 | + object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); | ||
431 | + if (err) { | ||
432 | + error_propagate(errp, err); | ||
433 | + return; | ||
434 | + } | ||
435 | + sbd_secctl = SYS_BUS_DEVICE(&s->secctl); | ||
436 | + dev_secctl = DEVICE(&s->secctl); | ||
437 | + sysbus_mmio_map(sbd_secctl, 0, 0x50080000); | ||
438 | + sysbus_mmio_map(sbd_secctl, 1, 0x40080000); | ||
439 | + | ||
440 | + s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); | ||
441 | + qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); | ||
442 | + | ||
443 | + /* The sec_resp_cfg output from the security controller must be split into | ||
444 | + * multiple lines, one for each of the PPCs within the IoTKit and one | ||
445 | + * that will be an output from the IoTKit to the system. | ||
446 | + */ | ||
447 | + object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, | ||
448 | + "num-lines", &err); | ||
449 | + if (err) { | ||
450 | + error_propagate(errp, err); | ||
451 | + return; | ||
452 | + } | ||
453 | + object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, | ||
454 | + "realized", &err); | ||
455 | + if (err) { | ||
456 | + error_propagate(errp, err); | ||
457 | + return; | ||
458 | + } | ||
459 | + dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
460 | + qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, | ||
461 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
462 | + | ||
463 | + /* Devices behind APB PPC0: | ||
464 | + * 0x40000000: timer0 | ||
465 | + * 0x40001000: timer1 | ||
466 | + * 0x40002000: dual timer | ||
467 | + * We must configure and realize each downstream device and connect | ||
468 | + * it to the appropriate PPC port; then we can realize the PPC and | ||
469 | + * map its upstream ends to the right place in the container. | ||
470 | + */ | ||
471 | + qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); | ||
472 | + object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); | ||
473 | + if (err) { | ||
474 | + error_propagate(errp, err); | ||
475 | + return; | ||
476 | + } | ||
477 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, | ||
478 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
479 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); | ||
480 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); | ||
481 | + if (err) { | ||
482 | + error_propagate(errp, err); | ||
483 | + return; | ||
484 | + } | ||
485 | + | ||
486 | + qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); | ||
487 | + object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); | ||
488 | + if (err) { | ||
489 | + error_propagate(errp, err); | ||
490 | + return; | ||
491 | + } | ||
492 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, | ||
493 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
494 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); | ||
495 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); | ||
496 | + if (err) { | ||
497 | + error_propagate(errp, err); | ||
498 | + return; | ||
499 | + } | ||
500 | + | ||
501 | + qdev_prop_set_string(DEVICE(&s->dualtimer), "name", "Dual timer"); | ||
502 | + qdev_prop_set_uint64(DEVICE(&s->dualtimer), "size", 0x1000); | ||
503 | + object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); | ||
504 | + if (err) { | ||
505 | + error_propagate(errp, err); | ||
506 | + return; | ||
507 | + } | ||
508 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); | ||
509 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); | ||
510 | + if (err) { | ||
511 | + error_propagate(errp, err); | ||
512 | + return; | ||
513 | + } | ||
514 | + | ||
515 | + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); | ||
516 | + if (err) { | ||
517 | + error_propagate(errp, err); | ||
518 | + return; | ||
519 | + } | ||
520 | + | ||
521 | + sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); | ||
522 | + dev_apb_ppc0 = DEVICE(&s->apb_ppc0); | ||
523 | + | ||
524 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); | ||
525 | + memory_region_add_subregion(&s->container, 0x40000000, mr); | ||
526 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); | ||
527 | + memory_region_add_subregion(&s->container, 0x40001000, mr); | ||
528 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); | ||
529 | + memory_region_add_subregion(&s->container, 0x40002000, mr); | ||
530 | + for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { | ||
531 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, | ||
532 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
533 | + "cfg_nonsec", i)); | ||
534 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, | ||
535 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
536 | + "cfg_ap", i)); | ||
537 | + } | ||
538 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, | ||
539 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
540 | + "irq_enable", 0)); | ||
541 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, | ||
542 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
543 | + "irq_clear", 0)); | ||
544 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
545 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
546 | + "cfg_sec_resp", 0)); | ||
547 | + | ||
548 | + /* All the PPC irq lines (from the 2 internal PPCs and the 8 external | ||
549 | + * ones) are sent individually to the security controller, and also | ||
550 | + * ORed together to give a single combined PPC interrupt to the NVIC. | ||
551 | + */ | ||
552 | + object_property_set_int(OBJECT(&s->ppc_irq_orgate), | ||
553 | + NUM_PPCS, "num-lines", &err); | ||
554 | + if (err) { | ||
555 | + error_propagate(errp, err); | ||
556 | + return; | ||
557 | + } | ||
558 | + object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, | ||
559 | + "realized", &err); | ||
560 | + if (err) { | ||
561 | + error_propagate(errp, err); | ||
562 | + return; | ||
563 | + } | ||
564 | + qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, | ||
565 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); | ||
566 | + | ||
567 | + /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ | ||
568 | + | ||
569 | + /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */ | ||
570 | + /* Devices behind APB PPC1: | ||
571 | + * 0x4002f000: S32K timer | ||
572 | + */ | ||
573 | + qdev_prop_set_string(DEVICE(&s->s32ktimer), "name", "S32KTIMER"); | ||
574 | + qdev_prop_set_uint64(DEVICE(&s->s32ktimer), "size", 0x1000); | ||
575 | + object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); | ||
576 | + if (err) { | ||
577 | + error_propagate(errp, err); | ||
578 | + return; | ||
579 | + } | ||
580 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); | ||
581 | + object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); | ||
582 | + if (err) { | ||
583 | + error_propagate(errp, err); | ||
584 | + return; | ||
585 | + } | ||
586 | + | ||
587 | + object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); | ||
588 | + if (err) { | ||
589 | + error_propagate(errp, err); | ||
590 | + return; | ||
591 | + } | ||
592 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); | ||
593 | + memory_region_add_subregion(&s->container, 0x4002f000, mr); | ||
594 | + | ||
595 | + dev_apb_ppc1 = DEVICE(&s->apb_ppc1); | ||
596 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, | ||
597 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
598 | + "cfg_nonsec", 0)); | ||
599 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, | ||
600 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
601 | + "cfg_ap", 0)); | ||
602 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, | ||
603 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
604 | + "irq_enable", 0)); | ||
605 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, | ||
606 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
607 | + "irq_clear", 0)); | ||
608 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
609 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
610 | + "cfg_sec_resp", 0)); | ||
611 | + | ||
612 | + /* Using create_unimplemented_device() maps the stub into the | ||
613 | + * system address space rather than into our container, but the | ||
614 | + * overall effect to the guest is the same. | ||
615 | + */ | ||
616 | + create_unimplemented_device("SYSINFO", 0x40020000, 0x1000); | ||
617 | + | ||
618 | + create_unimplemented_device("SYSCONTROL", 0x50021000, 0x1000); | ||
619 | + create_unimplemented_device("S32KWATCHDOG", 0x5002e000, 0x1000); | ||
620 | + | ||
621 | + /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ | ||
622 | + | ||
623 | + create_unimplemented_device("NS watchdog", 0x40081000, 0x1000); | ||
624 | + create_unimplemented_device("S watchdog", 0x50081000, 0x1000); | ||
625 | + | ||
626 | + create_unimplemented_device("SRAM0 MPC", 0x50083000, 0x1000); | ||
627 | + | ||
628 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
629 | + Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); | ||
630 | + | ||
631 | + object_property_set_int(splitter, 2, "num-lines", &err); | ||
632 | + if (err) { | ||
633 | + error_propagate(errp, err); | ||
634 | + return; | ||
635 | + } | ||
636 | + object_property_set_bool(splitter, true, "realized", &err); | ||
637 | + if (err) { | ||
638 | + error_propagate(errp, err); | ||
639 | + return; | ||
640 | + } | ||
641 | + } | ||
642 | + | ||
643 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
644 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
645 | + | ||
646 | + iotkit_forward_ppc(s, ppcname, i); | ||
647 | + g_free(ppcname); | ||
648 | + } | ||
649 | + | ||
650 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
651 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
652 | + | ||
653 | + iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); | ||
654 | + g_free(ppcname); | ||
655 | + } | ||
656 | + | ||
657 | + for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { | ||
658 | + /* Wire up IRQ splitter for internal PPCs */ | ||
659 | + DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); | ||
660 | + char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", | ||
661 | + i - NUM_EXTERNAL_PPCS); | ||
662 | + TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; | ||
663 | + | ||
664 | + qdev_connect_gpio_out(devs, 0, | ||
665 | + qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); | ||
666 | + qdev_connect_gpio_out(devs, 1, | ||
667 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); | ||
668 | + qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, | ||
669 | + qdev_get_gpio_in(devs, 0)); | ||
670 | + } | ||
671 | + | ||
672 | + iotkit_forward_sec_resp_cfg(s); | ||
673 | + | ||
674 | + system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; | ||
675 | +} | 133 | +} |
676 | + | 134 | + |
677 | +static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, | 135 | +static void cadence_uart_reset_hold(Object *obj) |
678 | + int *iregion, bool *exempt, bool *ns, bool *nsc) | ||
679 | +{ | 136 | +{ |
680 | + /* For IoTKit systems the IDAU responses are simple logical functions | 137 | + CadenceUARTState *s = CADENCE_UART(obj); |
681 | + * of the address bits. The NSC attribute is guest-adjustable via the | 138 | |
682 | + * NSCCFG register in the security controller. | 139 | uart_rx_reset(s); |
683 | + */ | 140 | uart_tx_reset(s); |
684 | + IoTKit *s = IOTKIT(ii); | 141 | @@ -XXX,XX +XXX,XX @@ static void cadence_uart_realize(DeviceState *dev, Error **errp) |
685 | + int region = extract32(address, 28, 4); | 142 | uart_event, NULL, s, NULL, true); |
686 | + | 143 | } |
687 | + *ns = !(region & 1); | 144 | |
688 | + *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); | 145 | +static void cadence_uart_refclk_update(void *opaque) |
689 | + /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | 146 | +{ |
690 | + *exempt = (address & 0xeff00000) == 0xe0000000; | 147 | + CadenceUARTState *s = opaque; |
691 | + *iregion = region; | 148 | + |
149 | + /* recompute uart's speed on clock change */ | ||
150 | + uart_parameters_setup(s); | ||
692 | +} | 151 | +} |
693 | + | 152 | + |
694 | +static const VMStateDescription iotkit_vmstate = { | 153 | static void cadence_uart_init(Object *obj) |
695 | + .name = "iotkit", | 154 | { |
696 | + .version_id = 1, | 155 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
697 | + .minimum_version_id = 1, | 156 | @@ -XXX,XX +XXX,XX @@ static void cadence_uart_init(Object *obj) |
698 | + .fields = (VMStateField[]) { | 157 | sysbus_init_mmio(sbd, &s->iomem); |
699 | + VMSTATE_UINT32(nsccfg, IoTKit), | 158 | sysbus_init_irq(sbd, &s->irq); |
700 | + VMSTATE_END_OF_LIST() | 159 | |
701 | + } | 160 | + s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", |
702 | +}; | 161 | + cadence_uart_refclk_update, s); |
703 | + | 162 | + /* initialize the frequency in case the clock remains unconnected */ |
704 | +static Property iotkit_properties[] = { | 163 | + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); |
705 | + DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, | 164 | + |
706 | + MemoryRegion *), | 165 | s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; |
707 | + DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), | 166 | } |
708 | + DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), | 167 | |
709 | + DEFINE_PROP_END_OF_LIST() | 168 | +static int cadence_uart_pre_load(void *opaque) |
710 | +}; | ||
711 | + | ||
712 | +static void iotkit_reset(DeviceState *dev) | ||
713 | +{ | 169 | +{ |
714 | + IoTKit *s = IOTKIT(dev); | 170 | + CadenceUARTState *s = opaque; |
715 | + | 171 | + |
716 | + s->nsccfg = 0; | 172 | + /* the frequency will be overriden if the refclk field is present */ |
173 | + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); | ||
174 | + return 0; | ||
717 | +} | 175 | +} |
718 | + | 176 | + |
719 | +static void iotkit_class_init(ObjectClass *klass, void *data) | 177 | static int cadence_uart_post_load(void *opaque, int version_id) |
720 | +{ | 178 | { |
721 | + DeviceClass *dc = DEVICE_CLASS(klass); | 179 | CadenceUARTState *s = opaque; |
722 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); | 180 | @@ -XXX,XX +XXX,XX @@ static int cadence_uart_post_load(void *opaque, int version_id) |
723 | + | 181 | |
724 | + dc->realize = iotkit_realize; | 182 | static const VMStateDescription vmstate_cadence_uart = { |
725 | + dc->vmsd = &iotkit_vmstate; | 183 | .name = "cadence_uart", |
726 | + dc->props = iotkit_properties; | 184 | - .version_id = 2, |
727 | + dc->reset = iotkit_reset; | 185 | + .version_id = 3, |
728 | + iic->check = iotkit_idau_check; | 186 | .minimum_version_id = 2, |
729 | +} | 187 | + .pre_load = cadence_uart_pre_load, |
730 | + | 188 | .post_load = cadence_uart_post_load, |
731 | +static const TypeInfo iotkit_info = { | 189 | .fields = (VMStateField[]) { |
732 | + .name = TYPE_IOTKIT, | 190 | VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), |
733 | + .parent = TYPE_SYS_BUS_DEVICE, | 191 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_uart = { |
734 | + .instance_size = sizeof(IoTKit), | 192 | VMSTATE_UINT32(tx_count, CadenceUARTState), |
735 | + .instance_init = iotkit_init, | 193 | VMSTATE_UINT32(rx_wpos, CadenceUARTState), |
736 | + .class_init = iotkit_class_init, | 194 | VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), |
737 | + .interfaces = (InterfaceInfo[]) { | 195 | + VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3), |
738 | + { TYPE_IDAU_INTERFACE }, | 196 | VMSTATE_END_OF_LIST() |
739 | + { } | 197 | - } |
740 | + } | 198 | + }, |
741 | +}; | 199 | }; |
742 | + | 200 | |
743 | +static void iotkit_register_types(void) | 201 | static Property cadence_uart_properties[] = { |
744 | +{ | 202 | @@ -XXX,XX +XXX,XX @@ static Property cadence_uart_properties[] = { |
745 | + type_register_static(&iotkit_info); | 203 | static void cadence_uart_class_init(ObjectClass *klass, void *data) |
746 | +} | 204 | { |
747 | + | 205 | DeviceClass *dc = DEVICE_CLASS(klass); |
748 | +type_init(iotkit_register_types); | 206 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
749 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | 207 | |
208 | dc->realize = cadence_uart_realize; | ||
209 | dc->vmsd = &vmstate_cadence_uart; | ||
210 | - dc->reset = cadence_uart_reset; | ||
211 | + rc->phases.enter = cadence_uart_reset_init; | ||
212 | + rc->phases.hold = cadence_uart_reset_hold; | ||
213 | device_class_set_props(dc, cadence_uart_properties); | ||
214 | } | ||
215 | |||
216 | diff --git a/hw/char/trace-events b/hw/char/trace-events | ||
750 | index XXXXXXX..XXXXXXX 100644 | 217 | index XXXXXXX..XXXXXXX 100644 |
751 | --- a/default-configs/arm-softmmu.mak | 218 | --- a/hw/char/trace-events |
752 | +++ b/default-configs/arm-softmmu.mak | 219 | +++ b/hw/char/trace-events |
753 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | 220 | @@ -XXX,XX +XXX,XX @@ exynos_uart_wo_read(uint32_t channel, const char *name, uint32_t reg) "UART%d: T |
754 | CONFIG_MPS2_SCC=y | 221 | exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d" |
755 | 222 | exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d" | |
756 | CONFIG_TZ_PPC=y | 223 | exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: Rx timeout stat=0x%x intsp=0x%x" |
757 | +CONFIG_IOTKIT=y | 224 | + |
758 | CONFIG_IOTKIT_SECCTL=y | 225 | +# hw/char/cadence_uart.c |
759 | 226 | +cadence_uart_baudrate(unsigned baudrate) "baudrate %u" | |
760 | CONFIG_VERSATILE_PCI=y | ||
761 | -- | 227 | -- |
762 | 2.16.2 | 228 | 2.20.1 |
763 | 229 | ||
764 | 230 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Add the connection between the slcr's output clocks and the uarts inputs. |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | |
5 | Message-id: 20180228193125.20577-14-richard.henderson@linaro.org | 5 | Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz |
6 | (the default frequency). This clock is used to feed the slcr's input | ||
7 | clock. | ||
8 | |||
9 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
12 | Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 14 | --- |
8 | target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 15 | hw/arm/xilinx_zynq.c | 57 +++++++++++++++++++++++++++++++++++++------- |
9 | 1 file changed, 68 insertions(+) | 16 | 1 file changed, 49 insertions(+), 8 deletions(-) |
10 | 17 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 18 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 20 | --- a/hw/arm/xilinx_zynq.c |
14 | +++ b/target/arm/translate.c | 21 | +++ b/hw/arm/xilinx_zynq.c |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 22 | @@ -XXX,XX +XXX,XX @@ |
16 | return 0; | 23 | #include "hw/char/cadence_uart.h" |
24 | #include "hw/net/cadence_gem.h" | ||
25 | #include "hw/cpu/a9mpcore.h" | ||
26 | +#include "hw/qdev-clock.h" | ||
27 | +#include "sysemu/reset.h" | ||
28 | + | ||
29 | +#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") | ||
30 | +#define ZYNQ_MACHINE(obj) \ | ||
31 | + OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE) | ||
32 | + | ||
33 | +/* board base frequency: 33.333333 MHz */ | ||
34 | +#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) | ||
35 | |||
36 | #define NUM_SPI_FLASHES 4 | ||
37 | #define NUM_QSPI_FLASHES 2 | ||
38 | @@ -XXX,XX +XXX,XX @@ static const int dma_irqs[8] = { | ||
39 | 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ | ||
40 | 0xe5801000 + (addr) | ||
41 | |||
42 | +typedef struct ZynqMachineState { | ||
43 | + MachineState parent; | ||
44 | + Clock *ps_clk; | ||
45 | +} ZynqMachineState; | ||
46 | + | ||
47 | static void zynq_write_board_setup(ARMCPU *cpu, | ||
48 | const struct arm_boot_info *info) | ||
49 | { | ||
50 | @@ -XXX,XX +XXX,XX @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, | ||
51 | |||
52 | static void zynq_init(MachineState *machine) | ||
53 | { | ||
54 | + ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); | ||
55 | ARMCPU *cpu; | ||
56 | MemoryRegion *address_space_mem = get_system_memory(); | ||
57 | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); | ||
58 | - DeviceState *dev; | ||
59 | + DeviceState *dev, *slcr; | ||
60 | SysBusDevice *busdev; | ||
61 | qemu_irq pic[64]; | ||
62 | int n; | ||
63 | @@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine) | ||
64 | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, | ||
65 | 0); | ||
66 | |||
67 | - dev = qdev_create(NULL, "xilinx,zynq_slcr"); | ||
68 | - qdev_init_nofail(dev); | ||
69 | - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); | ||
70 | + /* Create slcr, keep a pointer to connect clocks */ | ||
71 | + slcr = qdev_create(NULL, "xilinx,zynq_slcr"); | ||
72 | + qdev_init_nofail(slcr); | ||
73 | + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); | ||
74 | + | ||
75 | + /* Create the main clock source, and feed slcr with it */ | ||
76 | + zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); | ||
77 | + object_property_add_child(OBJECT(zynq_machine), "ps_clk", | ||
78 | + OBJECT(zynq_machine->ps_clk), &error_abort); | ||
79 | + object_unref(OBJECT(zynq_machine->ps_clk)); | ||
80 | + clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); | ||
81 | + qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); | ||
82 | |||
83 | dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); | ||
84 | qdev_prop_set_uint32(dev, "num-cpu", 1); | ||
85 | @@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine) | ||
86 | sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); | ||
87 | sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); | ||
88 | |||
89 | - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); | ||
90 | - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); | ||
91 | + dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); | ||
92 | + qdev_connect_clock_in(dev, "refclk", | ||
93 | + qdev_get_clock_out(slcr, "uart0_ref_clk")); | ||
94 | + dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); | ||
95 | + qdev_connect_clock_in(dev, "refclk", | ||
96 | + qdev_get_clock_out(slcr, "uart1_ref_clk")); | ||
97 | |||
98 | sysbus_create_varargs("cadence_ttc", 0xF8001000, | ||
99 | pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); | ||
100 | @@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine) | ||
101 | arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); | ||
17 | } | 102 | } |
18 | 103 | ||
19 | +/* Advanced SIMD three registers of the same length extension. | 104 | -static void zynq_machine_init(MachineClass *mc) |
20 | + * 31 25 23 22 20 16 12 11 10 9 8 3 0 | 105 | +static void zynq_machine_class_init(ObjectClass *oc, void *data) |
21 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | 106 | { |
22 | + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | 107 | + MachineClass *mc = MACHINE_CLASS(oc); |
23 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | 108 | mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; |
24 | + */ | 109 | mc->init = zynq_init; |
25 | +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 110 | mc->max_cpus = 1; |
111 | @@ -XXX,XX +XXX,XX @@ static void zynq_machine_init(MachineClass *mc) | ||
112 | mc->default_ram_id = "zynq.ext_ram"; | ||
113 | } | ||
114 | |||
115 | -DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) | ||
116 | +static const TypeInfo zynq_machine_type = { | ||
117 | + .name = TYPE_ZYNQ_MACHINE, | ||
118 | + .parent = TYPE_MACHINE, | ||
119 | + .class_init = zynq_machine_class_init, | ||
120 | + .instance_size = sizeof(ZynqMachineState), | ||
121 | +}; | ||
122 | + | ||
123 | +static void zynq_machine_register_types(void) | ||
26 | +{ | 124 | +{ |
27 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | 125 | + type_register_static(&zynq_machine_type); |
28 | + int rd, rn, rm, rot, size, opr_sz; | ||
29 | + TCGv_ptr fpst; | ||
30 | + bool q; | ||
31 | + | ||
32 | + q = extract32(insn, 6, 1); | ||
33 | + VFP_DREG_D(rd, insn); | ||
34 | + VFP_DREG_N(rn, insn); | ||
35 | + VFP_DREG_M(rm, insn); | ||
36 | + if ((rd | rn | rm) & q) { | ||
37 | + return 1; | ||
38 | + } | ||
39 | + | ||
40 | + if ((insn & 0xfe200f10) == 0xfc200800) { | ||
41 | + /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ | ||
42 | + size = extract32(insn, 20, 1); | ||
43 | + rot = extract32(insn, 23, 2); | ||
44 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
45 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
46 | + return 1; | ||
47 | + } | ||
48 | + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | ||
49 | + } else if ((insn & 0xfea00f10) == 0xfc800800) { | ||
50 | + /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | ||
51 | + size = extract32(insn, 20, 1); | ||
52 | + rot = extract32(insn, 24, 1); | ||
53 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
54 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
55 | + return 1; | ||
56 | + } | ||
57 | + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
58 | + } else { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + if (s->fp_excp_el) { | ||
63 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
64 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
65 | + return 0; | ||
66 | + } | ||
67 | + if (!s->vfp_enabled) { | ||
68 | + return 1; | ||
69 | + } | ||
70 | + | ||
71 | + opr_sz = (1 + q) * 8; | ||
72 | + fpst = get_fpstatus_ptr(1); | ||
73 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
74 | + vfp_reg_offset(1, rn), | ||
75 | + vfp_reg_offset(1, rm), fpst, | ||
76 | + opr_sz, opr_sz, rot, fn_gvec_ptr); | ||
77 | + tcg_temp_free_ptr(fpst); | ||
78 | + return 0; | ||
79 | +} | 126 | +} |
80 | + | 127 | + |
81 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 128 | +type_init(zynq_machine_register_types) |
82 | { | ||
83 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
84 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
85 | } | ||
86 | } | ||
87 | } | ||
88 | + } else if ((insn & 0x0e000a00) == 0x0c000800 | ||
89 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
90 | + if (disas_neon_insn_3same_ext(s, insn)) { | ||
91 | + goto illegal_op; | ||
92 | + } | ||
93 | + return; | ||
94 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
95 | /* Coprocessor double register transfer. */ | ||
96 | ARCH(5TE); | ||
97 | -- | 129 | -- |
98 | 2.16.2 | 130 | 2.20.1 |
99 | 131 | ||
100 | 132 | diff view generated by jsdifflib |
1 | Create an "init-svtor" property on the armv7m container | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | object which we can forward to the CPU object. | ||
3 | 2 | ||
3 | This prints the clocks attached to a DeviceState when using | ||
4 | "info qtree" monitor command. For every clock, it displays the | ||
5 | direction, the name and if the clock is forwarded. For input clock, | ||
6 | it displays also the frequency. | ||
7 | |||
8 | This is based on the original work of Frederic Konrad. | ||
9 | |||
10 | Here follows a sample of `info qtree` output on xilinx_zynq machine | ||
11 | after linux boot with only one uart clocked: | ||
12 | > bus: main-system-bus | ||
13 | > type System | ||
14 | > [...] | ||
15 | > dev: cadence_uart, id "" | ||
16 | > gpio-out "sysbus-irq" 1 | ||
17 | > clock-in "refclk" freq_hz=0.000000e+00 | ||
18 | > chardev = "" | ||
19 | > mmio 00000000e0001000/0000000000001000 | ||
20 | > dev: cadence_uart, id "" | ||
21 | > gpio-out "sysbus-irq" 1 | ||
22 | > clock-in "refclk" freq_hz=1.375661e+07 | ||
23 | > chardev = "serial0" | ||
24 | > mmio 00000000e0000000/0000000000001000 | ||
25 | > [...] | ||
26 | > dev: xilinx,zynq_slcr, id "" | ||
27 | > clock-out "uart1_ref_clk" freq_hz=0.000000e+00 | ||
28 | > clock-out "uart0_ref_clk" freq_hz=1.375661e+07 | ||
29 | > clock-in "ps_clk" freq_hz=3.333333e+07 | ||
30 | > mmio 00000000f8000000/0000000000001000 | ||
31 | |||
32 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
33 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
34 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
36 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
37 | Message-id: 20200406135251.157596-10-damien.hedde@greensocs.com | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 38 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20180220180325.29818-8-peter.maydell@linaro.org | ||
7 | --- | 39 | --- |
8 | include/hw/arm/armv7m.h | 2 ++ | 40 | qdev-monitor.c | 9 +++++++++ |
9 | hw/arm/armv7m.c | 9 +++++++++ | 41 | 1 file changed, 9 insertions(+) |
10 | 2 files changed, 11 insertions(+) | ||
11 | 42 | ||
12 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | 43 | diff --git a/qdev-monitor.c b/qdev-monitor.c |
13 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/arm/armv7m.h | 45 | --- a/qdev-monitor.c |
15 | +++ b/include/hw/arm/armv7m.h | 46 | +++ b/qdev-monitor.c |
16 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 47 | @@ -XXX,XX +XXX,XX @@ |
17 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | 48 | #include "migration/misc.h" |
18 | * devices will be automatically layered on top of this view.) | 49 | #include "migration/migration.h" |
19 | * + Property "idau": IDAU interface (forwarded to CPU object) | 50 | #include "qemu/cutils.h" |
20 | + * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) | 51 | +#include "hw/clock.h" |
21 | */ | 52 | |
22 | typedef struct ARMv7MState { | 53 | /* |
23 | /*< private >*/ | 54 | * Aliases were a bad idea from the start. Let's keep them |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | 55 | @@ -XXX,XX +XXX,XX @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent) |
25 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | 56 | ObjectClass *class; |
26 | MemoryRegion *board_memory; | 57 | BusState *child; |
27 | Object *idau; | 58 | NamedGPIOList *ngl; |
28 | + uint32_t init_svtor; | 59 | + NamedClockList *ncl; |
29 | } ARMv7MState; | 60 | |
30 | 61 | qdev_printf("dev: %s, id \"%s\"\n", object_get_typename(OBJECT(dev)), | |
31 | #endif | 62 | dev->id ? dev->id : ""); |
32 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 63 | @@ -XXX,XX +XXX,XX @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent) |
33 | index XXXXXXX..XXXXXXX 100644 | 64 | ngl->num_out); |
34 | --- a/hw/arm/armv7m.c | ||
35 | +++ b/hw/arm/armv7m.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
37 | return; | ||
38 | } | 65 | } |
39 | } | 66 | } |
40 | + if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { | 67 | + QLIST_FOREACH(ncl, &dev->clocks, node) { |
41 | + object_property_set_uint(OBJECT(s->cpu), s->init_svtor, | 68 | + qdev_printf("clock-%s%s \"%s\" freq_hz=%e\n", |
42 | + "init-svtor", &err); | 69 | + ncl->output ? "out" : "in", |
43 | + if (err != NULL) { | 70 | + ncl->alias ? " (alias)" : "", |
44 | + error_propagate(errp, err); | 71 | + ncl->name, |
45 | + return; | 72 | + CLOCK_PERIOD_TO_HZ(1.0 * clock_get(ncl->clock))); |
46 | + } | ||
47 | + } | 73 | + } |
48 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | 74 | class = object_get_class(OBJECT(dev)); |
49 | if (err != NULL) { | 75 | do { |
50 | error_propagate(errp, err); | 76 | qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent); |
51 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
52 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
53 | MemoryRegion *), | ||
54 | DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
55 | + DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), | ||
56 | DEFINE_PROP_END_OF_LIST(), | ||
57 | }; | ||
58 | |||
59 | -- | 77 | -- |
60 | 2.16.2 | 78 | 2.20.1 |
61 | 79 | ||
62 | 80 | diff view generated by jsdifflib |
1 | Create an "idau" property on the armv7m container object which | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | we can forward to the CPU object. Annoyingly, we can't use | ||
3 | object_property_add_alias() because the CPU object we want to | ||
4 | forward to doesn't exist until the armv7m container is realized. | ||
5 | 2 | ||
3 | Setup the ADMA with 128bit bus-width. This matters when | ||
4 | FIXED BURST mode is used. | ||
5 | |||
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
9 | Message-id: 20200417153800.27399-2-edgar.iglesias@gmail.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-6-peter.maydell@linaro.org | ||
9 | --- | 11 | --- |
10 | include/hw/arm/armv7m.h | 3 +++ | 12 | hw/arm/xlnx-versal.c | 2 ++ |
11 | hw/arm/armv7m.c | 9 +++++++++ | 13 | 1 file changed, 2 insertions(+) |
12 | 2 files changed, 12 insertions(+) | ||
13 | 14 | ||
14 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | 15 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/armv7m.h | 17 | --- a/hw/arm/xlnx-versal.c |
17 | +++ b/include/hw/arm/armv7m.h | 18 | +++ b/hw/arm/xlnx-versal.c |
18 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic) |
19 | 20 | ||
20 | #include "hw/sysbus.h" | 21 | dev = qdev_create(NULL, "xlnx.zdma"); |
21 | #include "hw/intc/armv7m_nvic.h" | 22 | s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev); |
22 | +#include "target/arm/idau.h" | 23 | + object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width", |
23 | 24 | + &error_abort); | |
24 | #define TYPE_BITBAND "ARM,bitband-memory" | 25 | object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); |
25 | #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | 26 | qdev_init_nofail(dev); |
26 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
27 | * + Property "memory": MemoryRegion defining the physical address space | ||
28 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
29 | * devices will be automatically layered on top of this view.) | ||
30 | + * + Property "idau": IDAU interface (forwarded to CPU object) | ||
31 | */ | ||
32 | typedef struct ARMv7MState { | ||
33 | /*< private >*/ | ||
34 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
35 | char *cpu_type; | ||
36 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
37 | MemoryRegion *board_memory; | ||
38 | + Object *idau; | ||
39 | } ARMv7MState; | ||
40 | |||
41 | #endif | ||
42 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/armv7m.c | ||
45 | +++ b/hw/arm/armv7m.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #include "sysemu/qtest.h" | ||
48 | #include "qemu/error-report.h" | ||
49 | #include "exec/address-spaces.h" | ||
50 | +#include "target/arm/idau.h" | ||
51 | |||
52 | /* Bitbanded IO. Each word corresponds to a single bit. */ | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
55 | |||
56 | object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", | ||
57 | &error_abort); | ||
58 | + if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { | ||
59 | + object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); | ||
60 | + if (err != NULL) { | ||
61 | + error_propagate(errp, err); | ||
62 | + return; | ||
63 | + } | ||
64 | + } | ||
65 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
66 | if (err != NULL) { | ||
67 | error_propagate(errp, err); | ||
68 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
69 | DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), | ||
70 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
71 | MemoryRegion *), | ||
72 | + DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
73 | DEFINE_PROP_END_OF_LIST(), | ||
74 | }; | ||
75 | 27 | ||
76 | -- | 28 | -- |
77 | 2.16.2 | 29 | 2.20.1 |
78 | 30 | ||
79 | 31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Ramon Fried <rfried.dev@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Wraparound of TX descriptor cyclic buffer only updated |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | the low 32 bits of the descriptor. |
5 | Message-id: 20180228193125.20577-7-richard.henderson@linaro.org | 5 | Fix that by checking if we're working with 64bit descriptors. |
6 | |||
7 | Signed-off-by: Ramon Fried <rfried.dev@gmail.com> | ||
8 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
9 | Message-id: 20200417171736.441607-1-rfried.dev@gmail.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ | 12 | hw/net/cadence_gem.c | 9 ++++++++- |
9 | 1 file changed, 29 insertions(+) | 13 | 1 file changed, 8 insertions(+), 1 deletion(-) |
10 | 14 | ||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 15 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-a64.c | 17 | --- a/hw/net/cadence_gem.c |
14 | +++ b/target/arm/translate-a64.c | 18 | +++ b/hw/net/cadence_gem.c |
15 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) |
16 | case 0x19: /* FMULX */ | 20 | /* read next descriptor */ |
17 | is_fp = true; | 21 | if (tx_desc_get_wrap(desc)) { |
18 | break; | 22 | tx_desc_set_last(desc); |
19 | + case 0x1d: /* SQRDMLAH */ | 23 | - packet_desc_addr = s->regs[GEM_TXQBASE]; |
20 | + case 0x1f: /* SQRDMLSH */ | 24 | + |
21 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | 25 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { |
22 | + unallocated_encoding(s); | 26 | + packet_desc_addr = s->regs[GEM_TBQPH]; |
23 | + return; | 27 | + packet_desc_addr <<= 32; |
24 | + } | ||
25 | + break; | ||
26 | default: | ||
27 | unallocated_encoding(s); | ||
28 | return; | ||
29 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
30 | tcg_op, tcg_idx); | ||
31 | } | ||
32 | break; | ||
33 | + case 0x1d: /* SQRDMLAH */ | ||
34 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
35 | + is_scalar ? size : MO_32); | ||
36 | + if (size == 1) { | ||
37 | + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | ||
38 | + tcg_op, tcg_idx, tcg_res); | ||
39 | + } else { | 28 | + } else { |
40 | + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | 29 | + packet_desc_addr = 0; |
41 | + tcg_op, tcg_idx, tcg_res); | ||
42 | + } | 30 | + } |
43 | + break; | 31 | + packet_desc_addr |= s->regs[GEM_TXQBASE]; |
44 | + case 0x1f: /* SQRDMLSH */ | 32 | } else { |
45 | + read_vec_element_i32(s, tcg_res, rd, pass, | 33 | packet_desc_addr += 4 * gem_get_desc_len(s, false); |
46 | + is_scalar ? size : MO_32); | ||
47 | + if (size == 1) { | ||
48 | + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | ||
49 | + tcg_op, tcg_idx, tcg_res); | ||
50 | + } else { | ||
51 | + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | ||
52 | + tcg_op, tcg_idx, tcg_res); | ||
53 | + } | ||
54 | + break; | ||
55 | default: | ||
56 | g_assert_not_reached(); | ||
57 | } | 34 | } |
58 | -- | 35 | -- |
59 | 2.16.2 | 36 | 2.20.1 |
60 | 37 | ||
61 | 38 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Ramon Fried <rfried.dev@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | The RX ring descriptors control field is used for setting |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | SOF and EOF (start of frame and end of frame). |
5 | Message-id: 20180228193125.20577-12-richard.henderson@linaro.org | 5 | The SOF and EOF weren't cleared from the previous descriptors, |
6 | causing inconsistencies in ring buffer. | ||
7 | Fix that by clearing the control field of every descriptors we're | ||
8 | processing. | ||
9 | |||
10 | Signed-off-by: Ramon Fried <rfried.dev@gmail.com> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
12 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
13 | Message-id: 20200418085145.489726-1-rfried.dev@gmail.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 15 | --- |
8 | target/arm/helper.h | 7 ++++ | 16 | hw/net/cadence_gem.c | 7 +++++++ |
9 | target/arm/translate-a64.c | 48 ++++++++++++++++++++++- | 17 | 1 file changed, 7 insertions(+) |
10 | target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ | ||
11 | 3 files changed, 151 insertions(+), 1 deletion(-) | ||
12 | 18 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 19 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c |
14 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 21 | --- a/hw/net/cadence_gem.c |
16 | +++ b/target/arm/helper.h | 22 | +++ b/hw/net/cadence_gem.c |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 23 | @@ -XXX,XX +XXX,XX @@ static inline void rx_desc_set_sof(uint32_t *desc) |
18 | DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 24 | desc[1] |= DESC_1_RX_SOF; |
19 | void, ptr, ptr, ptr, ptr, i32) | ||
20 | |||
21 | +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, | ||
22 | + void, ptr, ptr, ptr, ptr, i32) | ||
23 | +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | + | ||
28 | #ifdef TARGET_AARCH64 | ||
29 | #include "helper-a64.h" | ||
30 | #endif | ||
31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate-a64.c | ||
34 | +++ b/target/arm/translate-a64.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
36 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
37 | } | 25 | } |
38 | 26 | ||
39 | +/* Expand a 3-operand + fpstatus pointer + simd data value operation using | 27 | +static inline void rx_desc_clear_control(uint32_t *desc) |
40 | + * an out-of-line helper. | ||
41 | + */ | ||
42 | +static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | ||
43 | + int rm, bool is_fp16, int data, | ||
44 | + gen_helper_gvec_3_ptr *fn) | ||
45 | +{ | 28 | +{ |
46 | + TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | 29 | + desc[1] = 0; |
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
48 | + vec_full_reg_offset(s, rn), | ||
49 | + vec_full_reg_offset(s, rm), fpst, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | ||
51 | + tcg_temp_free_ptr(fpst); | ||
52 | +} | 30 | +} |
53 | + | 31 | + |
54 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | 32 | static inline void rx_desc_set_eof(uint32_t *desc) |
55 | * than the 32 bit equivalent. | 33 | { |
56 | */ | 34 | desc[1] |= DESC_1_RX_EOF; |
57 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | 35 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
58 | int size = extract32(insn, 22, 2); | 36 | rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); |
59 | bool u = extract32(insn, 29, 1); | 37 | bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); |
60 | bool is_q = extract32(insn, 30, 1); | 38 | |
61 | - int feature; | 39 | + rx_desc_clear_control(s->rx_desc[q]); |
62 | + int feature, rot; | ||
63 | |||
64 | switch (u * 16 + opcode) { | ||
65 | case 0x10: /* SQRDMLAH (vector) */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | } | ||
68 | feature = ARM_FEATURE_V8_RDM; | ||
69 | break; | ||
70 | + case 0xc: /* FCADD, #90 */ | ||
71 | + case 0xe: /* FCADD, #270 */ | ||
72 | + if (size == 0 | ||
73 | + || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) | ||
74 | + || (size == 3 && !is_q)) { | ||
75 | + unallocated_encoding(s); | ||
76 | + return; | ||
77 | + } | ||
78 | + feature = ARM_FEATURE_V8_FCMA; | ||
79 | + break; | ||
80 | default: | ||
81 | unallocated_encoding(s); | ||
82 | return; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
84 | } | ||
85 | return; | ||
86 | |||
87 | + case 0xc: /* FCADD, #90 */ | ||
88 | + case 0xe: /* FCADD, #270 */ | ||
89 | + rot = extract32(opcode, 1, 1); | ||
90 | + switch (size) { | ||
91 | + case 1: | ||
92 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
93 | + gen_helper_gvec_fcaddh); | ||
94 | + break; | ||
95 | + case 2: | ||
96 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
97 | + gen_helper_gvec_fcadds); | ||
98 | + break; | ||
99 | + case 3: | ||
100 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
101 | + gen_helper_gvec_fcaddd); | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | + } | ||
106 | + return; | ||
107 | + | 40 | + |
108 | default: | 41 | /* Update the descriptor. */ |
109 | g_assert_not_reached(); | 42 | if (first_desc) { |
110 | } | 43 | rx_desc_set_sof(s->rx_desc[q]); |
111 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/vec_helper.c | ||
114 | +++ b/target/arm/vec_helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | #include "exec/exec-all.h" | ||
117 | #include "exec/helper-proto.h" | ||
118 | #include "tcg/tcg-gvec-desc.h" | ||
119 | +#include "fpu/softfloat.h" | ||
120 | |||
121 | |||
122 | +/* Note that vector data is stored in host-endian 64-bit chunks, | ||
123 | + so addressing units smaller than that needs a host-endian fixup. */ | ||
124 | +#ifdef HOST_WORDS_BIGENDIAN | ||
125 | +#define H1(x) ((x) ^ 7) | ||
126 | +#define H2(x) ((x) ^ 3) | ||
127 | +#define H4(x) ((x) ^ 1) | ||
128 | +#else | ||
129 | +#define H1(x) (x) | ||
130 | +#define H2(x) (x) | ||
131 | +#define H4(x) (x) | ||
132 | +#endif | ||
133 | + | ||
134 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
135 | |||
136 | static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
137 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
138 | } | ||
139 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
140 | } | ||
141 | + | ||
142 | +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, | ||
143 | + void *vfpst, uint32_t desc) | ||
144 | +{ | ||
145 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
146 | + float16 *d = vd; | ||
147 | + float16 *n = vn; | ||
148 | + float16 *m = vm; | ||
149 | + float_status *fpst = vfpst; | ||
150 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
151 | + uint32_t neg_imag = neg_real ^ 1; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
155 | + neg_real <<= 15; | ||
156 | + neg_imag <<= 15; | ||
157 | + | ||
158 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
159 | + float16 e0 = n[H2(i)]; | ||
160 | + float16 e1 = m[H2(i + 1)] ^ neg_imag; | ||
161 | + float16 e2 = n[H2(i + 1)]; | ||
162 | + float16 e3 = m[H2(i)] ^ neg_real; | ||
163 | + | ||
164 | + d[H2(i)] = float16_add(e0, e1, fpst); | ||
165 | + d[H2(i + 1)] = float16_add(e2, e3, fpst); | ||
166 | + } | ||
167 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
168 | +} | ||
169 | + | ||
170 | +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, | ||
171 | + void *vfpst, uint32_t desc) | ||
172 | +{ | ||
173 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
174 | + float32 *d = vd; | ||
175 | + float32 *n = vn; | ||
176 | + float32 *m = vm; | ||
177 | + float_status *fpst = vfpst; | ||
178 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
179 | + uint32_t neg_imag = neg_real ^ 1; | ||
180 | + uintptr_t i; | ||
181 | + | ||
182 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
183 | + neg_real <<= 31; | ||
184 | + neg_imag <<= 31; | ||
185 | + | ||
186 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
187 | + float32 e0 = n[H4(i)]; | ||
188 | + float32 e1 = m[H4(i + 1)] ^ neg_imag; | ||
189 | + float32 e2 = n[H4(i + 1)]; | ||
190 | + float32 e3 = m[H4(i)] ^ neg_real; | ||
191 | + | ||
192 | + d[H4(i)] = float32_add(e0, e1, fpst); | ||
193 | + d[H4(i + 1)] = float32_add(e2, e3, fpst); | ||
194 | + } | ||
195 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
196 | +} | ||
197 | + | ||
198 | +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
199 | + void *vfpst, uint32_t desc) | ||
200 | +{ | ||
201 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
202 | + float64 *d = vd; | ||
203 | + float64 *n = vn; | ||
204 | + float64 *m = vm; | ||
205 | + float_status *fpst = vfpst; | ||
206 | + uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); | ||
207 | + uint64_t neg_imag = neg_real ^ 1; | ||
208 | + uintptr_t i; | ||
209 | + | ||
210 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
211 | + neg_real <<= 63; | ||
212 | + neg_imag <<= 63; | ||
213 | + | ||
214 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
215 | + float64 e0 = n[i]; | ||
216 | + float64 e1 = m[i + 1] ^ neg_imag; | ||
217 | + float64 e2 = n[i + 1]; | ||
218 | + float64 e3 = m[i] ^ neg_real; | ||
219 | + | ||
220 | + d[i] = float64_add(e0, e1, fpst); | ||
221 | + d[i + 1] = float64_add(e2, e3, fpst); | ||
222 | + } | ||
223 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
224 | +} | ||
225 | -- | 44 | -- |
226 | 2.16.2 | 45 | 2.20.1 |
227 | 46 | ||
228 | 47 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These instructions are often used in glibc's string routines. | ||
4 | They were the final uses of the 32-bit at a time neon helpers. | ||
5 | |||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Message-id: 20180228193125.20577-13-richard.henderson@linaro.org | 7 | Message-id: 20200418162808.4680-1-richard.henderson@linaro.org |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | [PMM: renamed e1/e2/e3/e4 to use the same naming as the version | ||
7 | of the pseudocode in the Arm ARM] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | 10 | --- |
10 | target/arm/helper.h | 11 ++++ | 11 | target/arm/helper.h | 27 ++-- |
11 | target/arm/translate-a64.c | 94 +++++++++++++++++++++++++--- | 12 | target/arm/translate.h | 5 + |
12 | target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ | 13 | target/arm/neon_helper.c | 24 ---- |
13 | 3 files changed, 246 insertions(+), 8 deletions(-) | 14 | target/arm/translate-a64.c | 64 +++------- |
15 | target/arm/translate.c | 256 +++++++++++++++++++++++++++++++------ | ||
16 | target/arm/vec_helper.c | 25 ++++ | ||
17 | 6 files changed, 278 insertions(+), 123 deletions(-) | ||
14 | 18 | ||
15 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 19 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.h | 21 | --- a/target/arm/helper.h |
18 | +++ b/target/arm/helper.h | 22 | +++ b/target/arm/helper.h |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | 23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) |
20 | DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | 24 | DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) |
21 | void, ptr, ptr, ptr, ptr, i32) | 25 | DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) |
22 | 26 | ||
23 | +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, | 27 | -DEF_HELPER_2(neon_cgt_u8, i32, i32, i32) |
24 | + void, ptr, ptr, ptr, ptr, i32) | 28 | -DEF_HELPER_2(neon_cgt_s8, i32, i32, i32) |
25 | +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, | 29 | -DEF_HELPER_2(neon_cgt_u16, i32, i32, i32) |
26 | + void, ptr, ptr, ptr, ptr, i32) | 30 | -DEF_HELPER_2(neon_cgt_s16, i32, i32, i32) |
27 | +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, | 31 | -DEF_HELPER_2(neon_cgt_u32, i32, i32, i32) |
28 | + void, ptr, ptr, ptr, ptr, i32) | 32 | -DEF_HELPER_2(neon_cgt_s32, i32, i32, i32) |
29 | +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, | 33 | -DEF_HELPER_2(neon_cge_u8, i32, i32, i32) |
30 | + void, ptr, ptr, ptr, ptr, i32) | 34 | -DEF_HELPER_2(neon_cge_s8, i32, i32, i32) |
31 | +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, | 35 | -DEF_HELPER_2(neon_cge_u16, i32, i32, i32) |
32 | + void, ptr, ptr, ptr, ptr, i32) | 36 | -DEF_HELPER_2(neon_cge_s16, i32, i32, i32) |
33 | + | 37 | -DEF_HELPER_2(neon_cge_u32, i32, i32, i32) |
34 | #ifdef TARGET_AARCH64 | 38 | -DEF_HELPER_2(neon_cge_s32, i32, i32, i32) |
35 | #include "helper-a64.h" | 39 | - |
36 | #endif | 40 | DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) |
41 | DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) | ||
42 | DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) | ||
43 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(neon_mul_u16, i32, i32, i32) | ||
44 | DEF_HELPER_2(neon_tst_u8, i32, i32, i32) | ||
45 | DEF_HELPER_2(neon_tst_u16, i32, i32, i32) | ||
46 | DEF_HELPER_2(neon_tst_u32, i32, i32, i32) | ||
47 | -DEF_HELPER_2(neon_ceq_u8, i32, i32, i32) | ||
48 | -DEF_HELPER_2(neon_ceq_u16, i32, i32, i32) | ||
49 | -DEF_HELPER_2(neon_ceq_u32, i32, i32, i32) | ||
50 | |||
51 | DEF_HELPER_1(neon_clz_u8, i32, i32) | ||
52 | DEF_HELPER_1(neon_clz_u16, i32, i32) | ||
53 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr) | ||
54 | DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) | ||
55 | DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) | ||
56 | |||
57 | +DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
58 | +DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
59 | +DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
60 | +DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
61 | +DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
62 | +DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
63 | +DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
64 | +DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
65 | +DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
66 | +DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
67 | + | ||
68 | DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
69 | DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
70 | DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
71 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/translate.h | ||
74 | +++ b/target/arm/translate.h | ||
75 | @@ -XXX,XX +XXX,XX @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) | ||
76 | uint64_t vfp_expand_imm(int size, uint8_t imm8); | ||
77 | |||
78 | /* Vector operations shared between ARM and AArch64. */ | ||
79 | +extern const GVecGen2 ceq0_op[4]; | ||
80 | +extern const GVecGen2 clt0_op[4]; | ||
81 | +extern const GVecGen2 cgt0_op[4]; | ||
82 | +extern const GVecGen2 cle0_op[4]; | ||
83 | +extern const GVecGen2 cge0_op[4]; | ||
84 | extern const GVecGen3 mla_op[4]; | ||
85 | extern const GVecGen3 mls_op[4]; | ||
86 | extern const GVecGen3 cmtst_op[4]; | ||
87 | diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c | ||
88 | index XXXXXXX..XXXXXXX 100644 | ||
89 | --- a/target/arm/neon_helper.c | ||
90 | +++ b/target/arm/neon_helper.c | ||
91 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_hsub_u32)(uint32_t src1, uint32_t src2) | ||
92 | return dest; | ||
93 | } | ||
94 | |||
95 | -#define NEON_FN(dest, src1, src2) dest = (src1 > src2) ? ~0 : 0 | ||
96 | -NEON_VOP(cgt_s8, neon_s8, 4) | ||
97 | -NEON_VOP(cgt_u8, neon_u8, 4) | ||
98 | -NEON_VOP(cgt_s16, neon_s16, 2) | ||
99 | -NEON_VOP(cgt_u16, neon_u16, 2) | ||
100 | -NEON_VOP(cgt_s32, neon_s32, 1) | ||
101 | -NEON_VOP(cgt_u32, neon_u32, 1) | ||
102 | -#undef NEON_FN | ||
103 | - | ||
104 | -#define NEON_FN(dest, src1, src2) dest = (src1 >= src2) ? ~0 : 0 | ||
105 | -NEON_VOP(cge_s8, neon_s8, 4) | ||
106 | -NEON_VOP(cge_u8, neon_u8, 4) | ||
107 | -NEON_VOP(cge_s16, neon_s16, 2) | ||
108 | -NEON_VOP(cge_u16, neon_u16, 2) | ||
109 | -NEON_VOP(cge_s32, neon_s32, 1) | ||
110 | -NEON_VOP(cge_u32, neon_u32, 1) | ||
111 | -#undef NEON_FN | ||
112 | - | ||
113 | #define NEON_FN(dest, src1, src2) dest = (src1 < src2) ? src1 : src2 | ||
114 | NEON_POP(pmin_s8, neon_s8, 4) | ||
115 | NEON_POP(pmin_u8, neon_u8, 4) | ||
116 | @@ -XXX,XX +XXX,XX @@ NEON_VOP(tst_u16, neon_u16, 2) | ||
117 | NEON_VOP(tst_u32, neon_u32, 1) | ||
118 | #undef NEON_FN | ||
119 | |||
120 | -#define NEON_FN(dest, src1, src2) dest = (src1 == src2) ? -1 : 0 | ||
121 | -NEON_VOP(ceq_u8, neon_u8, 4) | ||
122 | -NEON_VOP(ceq_u16, neon_u16, 2) | ||
123 | -NEON_VOP(ceq_u32, neon_u32, 1) | ||
124 | -#undef NEON_FN | ||
125 | - | ||
126 | /* Count Leading Sign/Zero Bits. */ | ||
127 | static inline int do_clz8(uint8_t x) | ||
128 | { | ||
37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 129 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
38 | index XXXXXXX..XXXXXXX 100644 | 130 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/translate-a64.c | 131 | --- a/target/arm/translate-a64.c |
40 | +++ b/target/arm/translate-a64.c | 132 | +++ b/target/arm/translate-a64.c |
41 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | 133 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, |
42 | } | 134 | is_q ? 16 : 8, vec_full_reg_size(s)); |
43 | feature = ARM_FEATURE_V8_RDM; | 135 | } |
44 | break; | 136 | |
45 | + case 0x8: /* FCMLA, #0 */ | 137 | +/* Expand a 2-operand AdvSIMD vector operation using an op descriptor. */ |
46 | + case 0x9: /* FCMLA, #90 */ | 138 | +static void gen_gvec_op2(DisasContext *s, bool is_q, int rd, |
47 | + case 0xa: /* FCMLA, #180 */ | 139 | + int rn, const GVecGen2 *gvec_op) |
48 | + case 0xb: /* FCMLA, #270 */ | 140 | +{ |
49 | case 0xc: /* FCADD, #90 */ | 141 | + tcg_gen_gvec_2(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), |
50 | case 0xe: /* FCADD, #270 */ | 142 | + is_q ? 16 : 8, vec_full_reg_size(s), gvec_op); |
51 | if (size == 0 | 143 | +} |
52 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | 144 | + |
53 | } | 145 | /* Expand a 2-operand + immediate AdvSIMD vector operation using |
54 | return; | 146 | * an op descriptor. |
55 | 147 | */ | |
56 | + case 0x8: /* FCMLA, #0 */ | 148 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) |
57 | + case 0x9: /* FCMLA, #90 */ | ||
58 | + case 0xa: /* FCMLA, #180 */ | ||
59 | + case 0xb: /* FCMLA, #270 */ | ||
60 | + rot = extract32(opcode, 0, 2); | ||
61 | + switch (size) { | ||
62 | + case 1: | ||
63 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | ||
64 | + gen_helper_gvec_fcmlah); | ||
65 | + break; | ||
66 | + case 2: | ||
67 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
68 | + gen_helper_gvec_fcmlas); | ||
69 | + break; | ||
70 | + case 3: | ||
71 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
72 | + gen_helper_gvec_fcmlad); | ||
73 | + break; | ||
74 | + default: | ||
75 | + g_assert_not_reached(); | ||
76 | + } | ||
77 | + return; | ||
78 | + | ||
79 | case 0xc: /* FCADD, #90 */ | ||
80 | case 0xe: /* FCADD, #270 */ | ||
81 | rot = extract32(opcode, 1, 1); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
83 | int rn = extract32(insn, 5, 5); | ||
84 | int rd = extract32(insn, 0, 5); | ||
85 | bool is_long = false; | ||
86 | - bool is_fp = false; | ||
87 | + int is_fp = 0; | ||
88 | bool is_fp16 = false; | ||
89 | int index; | ||
90 | TCGv_ptr fpst; | ||
91 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
92 | case 0x05: /* FMLS */ | ||
93 | case 0x09: /* FMUL */ | ||
94 | case 0x19: /* FMULX */ | ||
95 | - is_fp = true; | ||
96 | + is_fp = 1; | ||
97 | break; | ||
98 | case 0x1d: /* SQRDMLAH */ | ||
99 | case 0x1f: /* SQRDMLSH */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
101 | return; | 149 | return; |
102 | } | 150 | } |
103 | break; | 151 | break; |
104 | + case 0x11: /* FCMLA #0 */ | 152 | + case 0x8: /* CMGT, CMGE */ |
105 | + case 0x13: /* FCMLA #90 */ | 153 | + gen_gvec_op2(s, is_q, rd, rn, u ? &cge0_op[size] : &cgt0_op[size]); |
106 | + case 0x15: /* FCMLA #180 */ | ||
107 | + case 0x17: /* FCMLA #270 */ | ||
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { | ||
109 | + unallocated_encoding(s); | ||
110 | + return; | ||
111 | + } | ||
112 | + is_fp = 2; | ||
113 | + break; | ||
114 | default: | ||
115 | unallocated_encoding(s); | ||
116 | return; | ||
117 | } | ||
118 | |||
119 | - if (is_fp) { | ||
120 | + switch (is_fp) { | ||
121 | + case 1: /* normal fp */ | ||
122 | /* convert insn encoded size to TCGMemOp size */ | ||
123 | switch (size) { | ||
124 | case 0: /* half-precision */ | ||
125 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
126 | - unallocated_encoding(s); | ||
127 | - return; | ||
128 | - } | ||
129 | size = MO_16; | ||
130 | + is_fp16 = true; | ||
131 | break; | ||
132 | case MO_32: /* single precision */ | ||
133 | case MO_64: /* double precision */ | ||
134 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
135 | unallocated_encoding(s); | ||
136 | return; | ||
137 | } | ||
138 | - } else { | ||
139 | + break; | ||
140 | + | ||
141 | + case 2: /* complex fp */ | ||
142 | + /* Each indexable element is a complex pair. */ | ||
143 | + size <<= 1; | ||
144 | + switch (size) { | ||
145 | + case MO_32: | ||
146 | + if (h && !is_q) { | ||
147 | + unallocated_encoding(s); | ||
148 | + return; | ||
149 | + } | ||
150 | + is_fp16 = true; | ||
151 | + break; | ||
152 | + case MO_64: | ||
153 | + break; | ||
154 | + default: | ||
155 | + unallocated_encoding(s); | ||
156 | + return; | ||
157 | + } | ||
158 | + break; | ||
159 | + | ||
160 | + default: /* integer */ | ||
161 | switch (size) { | ||
162 | case MO_8: | ||
163 | case MO_64: | ||
164 | unallocated_encoding(s); | ||
165 | return; | ||
166 | } | ||
167 | + break; | ||
168 | + } | ||
169 | + if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
170 | + unallocated_encoding(s); | ||
171 | + return; | 154 | + return; |
172 | } | 155 | + case 0x9: /* CMEQ, CMLE */ |
173 | 156 | + gen_gvec_op2(s, is_q, rd, rn, u ? &cle0_op[size] : &ceq0_op[size]); | |
174 | /* Given TCGMemOp size, adjust register and indexing. */ | ||
175 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
176 | fpst = NULL; | ||
177 | } | ||
178 | |||
179 | + switch (16 * u + opcode) { | ||
180 | + case 0x11: /* FCMLA #0 */ | ||
181 | + case 0x13: /* FCMLA #90 */ | ||
182 | + case 0x15: /* FCMLA #180 */ | ||
183 | + case 0x17: /* FCMLA #270 */ | ||
184 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
185 | + vec_full_reg_offset(s, rn), | ||
186 | + vec_reg_offset(s, rm, index, size), fpst, | ||
187 | + is_q ? 16 : 8, vec_full_reg_size(s), | ||
188 | + extract32(insn, 13, 2), /* rot */ | ||
189 | + size == MO_64 | ||
190 | + ? gen_helper_gvec_fcmlas_idx | ||
191 | + : gen_helper_gvec_fcmlah_idx); | ||
192 | + tcg_temp_free_ptr(fpst); | ||
193 | + return; | 157 | + return; |
194 | + } | 158 | + case 0xa: /* CMLT */ |
195 | + | 159 | + gen_gvec_op2(s, is_q, rd, rn, &clt0_op[size]); |
196 | if (size == 3) { | 160 | + return; |
197 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | 161 | case 0xb: |
198 | int pass; | 162 | if (u) { /* ABS, NEG */ |
163 | gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); | ||
164 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | ||
165 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | ||
166 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
167 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
168 | - TCGCond cond; | ||
169 | |||
170 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | ||
171 | |||
172 | if (size == 2) { | ||
173 | /* Special cases for 32 bit elements */ | ||
174 | switch (opcode) { | ||
175 | - case 0xa: /* CMLT */ | ||
176 | - /* 32 bit integer comparison against zero, result is | ||
177 | - * test ? (2^32 - 1) : 0. We implement via setcond(test) | ||
178 | - * and inverting. | ||
179 | - */ | ||
180 | - cond = TCG_COND_LT; | ||
181 | - do_cmop: | ||
182 | - tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0); | ||
183 | - tcg_gen_neg_i32(tcg_res, tcg_res); | ||
184 | - break; | ||
185 | - case 0x8: /* CMGT, CMGE */ | ||
186 | - cond = u ? TCG_COND_GE : TCG_COND_GT; | ||
187 | - goto do_cmop; | ||
188 | - case 0x9: /* CMEQ, CMLE */ | ||
189 | - cond = u ? TCG_COND_LE : TCG_COND_EQ; | ||
190 | - goto do_cmop; | ||
191 | case 0x4: /* CLS */ | ||
192 | if (u) { | ||
193 | tcg_gen_clzi_i32(tcg_res, tcg_op, 32); | ||
194 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | ||
195 | genfn(tcg_res, cpu_env, tcg_op); | ||
196 | break; | ||
197 | } | ||
198 | - case 0x8: /* CMGT, CMGE */ | ||
199 | - case 0x9: /* CMEQ, CMLE */ | ||
200 | - case 0xa: /* CMLT */ | ||
201 | - { | ||
202 | - static NeonGenTwoOpFn * const fns[3][2] = { | ||
203 | - { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 }, | ||
204 | - { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 }, | ||
205 | - { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 }, | ||
206 | - }; | ||
207 | - NeonGenTwoOpFn *genfn; | ||
208 | - int comp; | ||
209 | - bool reverse; | ||
210 | - TCGv_i32 tcg_zero = tcg_const_i32(0); | ||
211 | - | ||
212 | - /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */ | ||
213 | - comp = (opcode - 0x8) * 2 + u; | ||
214 | - /* ...but LE, LT are implemented as reverse GE, GT */ | ||
215 | - reverse = (comp > 2); | ||
216 | - if (reverse) { | ||
217 | - comp = 4 - comp; | ||
218 | - } | ||
219 | - genfn = fns[comp][size]; | ||
220 | - if (reverse) { | ||
221 | - genfn(tcg_res, tcg_zero, tcg_op); | ||
222 | - } else { | ||
223 | - genfn(tcg_res, tcg_op, tcg_zero); | ||
224 | - } | ||
225 | - tcg_temp_free_i32(tcg_zero); | ||
226 | - break; | ||
227 | - } | ||
228 | case 0x4: /* CLS, CLZ */ | ||
229 | if (u) { | ||
230 | if (size == 0) { | ||
231 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
232 | index XXXXXXX..XXXXXXX 100644 | ||
233 | --- a/target/arm/translate.c | ||
234 | +++ b/target/arm/translate.c | ||
235 | @@ -XXX,XX +XXX,XX @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, | ||
236 | return 1; | ||
237 | } | ||
238 | |||
239 | +static void gen_ceq0_i32(TCGv_i32 d, TCGv_i32 a) | ||
240 | +{ | ||
241 | + tcg_gen_setcondi_i32(TCG_COND_EQ, d, a, 0); | ||
242 | + tcg_gen_neg_i32(d, d); | ||
243 | +} | ||
244 | + | ||
245 | +static void gen_ceq0_i64(TCGv_i64 d, TCGv_i64 a) | ||
246 | +{ | ||
247 | + tcg_gen_setcondi_i64(TCG_COND_EQ, d, a, 0); | ||
248 | + tcg_gen_neg_i64(d, d); | ||
249 | +} | ||
250 | + | ||
251 | +static void gen_ceq0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) | ||
252 | +{ | ||
253 | + TCGv_vec zero = tcg_const_zeros_vec_matching(d); | ||
254 | + tcg_gen_cmp_vec(TCG_COND_EQ, vece, d, a, zero); | ||
255 | + tcg_temp_free_vec(zero); | ||
256 | +} | ||
257 | + | ||
258 | +static const TCGOpcode vecop_list_cmp[] = { | ||
259 | + INDEX_op_cmp_vec, 0 | ||
260 | +}; | ||
261 | + | ||
262 | +const GVecGen2 ceq0_op[4] = { | ||
263 | + { .fno = gen_helper_gvec_ceq0_b, | ||
264 | + .fniv = gen_ceq0_vec, | ||
265 | + .opt_opc = vecop_list_cmp, | ||
266 | + .vece = MO_8 }, | ||
267 | + { .fno = gen_helper_gvec_ceq0_h, | ||
268 | + .fniv = gen_ceq0_vec, | ||
269 | + .opt_opc = vecop_list_cmp, | ||
270 | + .vece = MO_16 }, | ||
271 | + { .fni4 = gen_ceq0_i32, | ||
272 | + .fniv = gen_ceq0_vec, | ||
273 | + .opt_opc = vecop_list_cmp, | ||
274 | + .vece = MO_32 }, | ||
275 | + { .fni8 = gen_ceq0_i64, | ||
276 | + .fniv = gen_ceq0_vec, | ||
277 | + .opt_opc = vecop_list_cmp, | ||
278 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
279 | + .vece = MO_64 }, | ||
280 | +}; | ||
281 | + | ||
282 | +static void gen_cle0_i32(TCGv_i32 d, TCGv_i32 a) | ||
283 | +{ | ||
284 | + tcg_gen_setcondi_i32(TCG_COND_LE, d, a, 0); | ||
285 | + tcg_gen_neg_i32(d, d); | ||
286 | +} | ||
287 | + | ||
288 | +static void gen_cle0_i64(TCGv_i64 d, TCGv_i64 a) | ||
289 | +{ | ||
290 | + tcg_gen_setcondi_i64(TCG_COND_LE, d, a, 0); | ||
291 | + tcg_gen_neg_i64(d, d); | ||
292 | +} | ||
293 | + | ||
294 | +static void gen_cle0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) | ||
295 | +{ | ||
296 | + TCGv_vec zero = tcg_const_zeros_vec_matching(d); | ||
297 | + tcg_gen_cmp_vec(TCG_COND_LE, vece, d, a, zero); | ||
298 | + tcg_temp_free_vec(zero); | ||
299 | +} | ||
300 | + | ||
301 | +const GVecGen2 cle0_op[4] = { | ||
302 | + { .fno = gen_helper_gvec_cle0_b, | ||
303 | + .fniv = gen_cle0_vec, | ||
304 | + .opt_opc = vecop_list_cmp, | ||
305 | + .vece = MO_8 }, | ||
306 | + { .fno = gen_helper_gvec_cle0_h, | ||
307 | + .fniv = gen_cle0_vec, | ||
308 | + .opt_opc = vecop_list_cmp, | ||
309 | + .vece = MO_16 }, | ||
310 | + { .fni4 = gen_cle0_i32, | ||
311 | + .fniv = gen_cle0_vec, | ||
312 | + .opt_opc = vecop_list_cmp, | ||
313 | + .vece = MO_32 }, | ||
314 | + { .fni8 = gen_cle0_i64, | ||
315 | + .fniv = gen_cle0_vec, | ||
316 | + .opt_opc = vecop_list_cmp, | ||
317 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
318 | + .vece = MO_64 }, | ||
319 | +}; | ||
320 | + | ||
321 | +static void gen_cge0_i32(TCGv_i32 d, TCGv_i32 a) | ||
322 | +{ | ||
323 | + tcg_gen_setcondi_i32(TCG_COND_GE, d, a, 0); | ||
324 | + tcg_gen_neg_i32(d, d); | ||
325 | +} | ||
326 | + | ||
327 | +static void gen_cge0_i64(TCGv_i64 d, TCGv_i64 a) | ||
328 | +{ | ||
329 | + tcg_gen_setcondi_i64(TCG_COND_GE, d, a, 0); | ||
330 | + tcg_gen_neg_i64(d, d); | ||
331 | +} | ||
332 | + | ||
333 | +static void gen_cge0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) | ||
334 | +{ | ||
335 | + TCGv_vec zero = tcg_const_zeros_vec_matching(d); | ||
336 | + tcg_gen_cmp_vec(TCG_COND_GE, vece, d, a, zero); | ||
337 | + tcg_temp_free_vec(zero); | ||
338 | +} | ||
339 | + | ||
340 | +const GVecGen2 cge0_op[4] = { | ||
341 | + { .fno = gen_helper_gvec_cge0_b, | ||
342 | + .fniv = gen_cge0_vec, | ||
343 | + .opt_opc = vecop_list_cmp, | ||
344 | + .vece = MO_8 }, | ||
345 | + { .fno = gen_helper_gvec_cge0_h, | ||
346 | + .fniv = gen_cge0_vec, | ||
347 | + .opt_opc = vecop_list_cmp, | ||
348 | + .vece = MO_16 }, | ||
349 | + { .fni4 = gen_cge0_i32, | ||
350 | + .fniv = gen_cge0_vec, | ||
351 | + .opt_opc = vecop_list_cmp, | ||
352 | + .vece = MO_32 }, | ||
353 | + { .fni8 = gen_cge0_i64, | ||
354 | + .fniv = gen_cge0_vec, | ||
355 | + .opt_opc = vecop_list_cmp, | ||
356 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
357 | + .vece = MO_64 }, | ||
358 | +}; | ||
359 | + | ||
360 | +static void gen_clt0_i32(TCGv_i32 d, TCGv_i32 a) | ||
361 | +{ | ||
362 | + tcg_gen_setcondi_i32(TCG_COND_LT, d, a, 0); | ||
363 | + tcg_gen_neg_i32(d, d); | ||
364 | +} | ||
365 | + | ||
366 | +static void gen_clt0_i64(TCGv_i64 d, TCGv_i64 a) | ||
367 | +{ | ||
368 | + tcg_gen_setcondi_i64(TCG_COND_LT, d, a, 0); | ||
369 | + tcg_gen_neg_i64(d, d); | ||
370 | +} | ||
371 | + | ||
372 | +static void gen_clt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) | ||
373 | +{ | ||
374 | + TCGv_vec zero = tcg_const_zeros_vec_matching(d); | ||
375 | + tcg_gen_cmp_vec(TCG_COND_LT, vece, d, a, zero); | ||
376 | + tcg_temp_free_vec(zero); | ||
377 | +} | ||
378 | + | ||
379 | +const GVecGen2 clt0_op[4] = { | ||
380 | + { .fno = gen_helper_gvec_clt0_b, | ||
381 | + .fniv = gen_clt0_vec, | ||
382 | + .opt_opc = vecop_list_cmp, | ||
383 | + .vece = MO_8 }, | ||
384 | + { .fno = gen_helper_gvec_clt0_h, | ||
385 | + .fniv = gen_clt0_vec, | ||
386 | + .opt_opc = vecop_list_cmp, | ||
387 | + .vece = MO_16 }, | ||
388 | + { .fni4 = gen_clt0_i32, | ||
389 | + .fniv = gen_clt0_vec, | ||
390 | + .opt_opc = vecop_list_cmp, | ||
391 | + .vece = MO_32 }, | ||
392 | + { .fni8 = gen_clt0_i64, | ||
393 | + .fniv = gen_clt0_vec, | ||
394 | + .opt_opc = vecop_list_cmp, | ||
395 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
396 | + .vece = MO_64 }, | ||
397 | +}; | ||
398 | + | ||
399 | +static void gen_cgt0_i32(TCGv_i32 d, TCGv_i32 a) | ||
400 | +{ | ||
401 | + tcg_gen_setcondi_i32(TCG_COND_GT, d, a, 0); | ||
402 | + tcg_gen_neg_i32(d, d); | ||
403 | +} | ||
404 | + | ||
405 | +static void gen_cgt0_i64(TCGv_i64 d, TCGv_i64 a) | ||
406 | +{ | ||
407 | + tcg_gen_setcondi_i64(TCG_COND_GT, d, a, 0); | ||
408 | + tcg_gen_neg_i64(d, d); | ||
409 | +} | ||
410 | + | ||
411 | +static void gen_cgt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) | ||
412 | +{ | ||
413 | + TCGv_vec zero = tcg_const_zeros_vec_matching(d); | ||
414 | + tcg_gen_cmp_vec(TCG_COND_GT, vece, d, a, zero); | ||
415 | + tcg_temp_free_vec(zero); | ||
416 | +} | ||
417 | + | ||
418 | +const GVecGen2 cgt0_op[4] = { | ||
419 | + { .fno = gen_helper_gvec_cgt0_b, | ||
420 | + .fniv = gen_cgt0_vec, | ||
421 | + .opt_opc = vecop_list_cmp, | ||
422 | + .vece = MO_8 }, | ||
423 | + { .fno = gen_helper_gvec_cgt0_h, | ||
424 | + .fniv = gen_cgt0_vec, | ||
425 | + .opt_opc = vecop_list_cmp, | ||
426 | + .vece = MO_16 }, | ||
427 | + { .fni4 = gen_cgt0_i32, | ||
428 | + .fniv = gen_cgt0_vec, | ||
429 | + .opt_opc = vecop_list_cmp, | ||
430 | + .vece = MO_32 }, | ||
431 | + { .fni8 = gen_cgt0_i64, | ||
432 | + .fniv = gen_cgt0_vec, | ||
433 | + .opt_opc = vecop_list_cmp, | ||
434 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
435 | + .vece = MO_64 }, | ||
436 | +}; | ||
437 | + | ||
438 | static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) | ||
439 | { | ||
440 | tcg_gen_vec_sar8i_i64(a, a, shift); | ||
441 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
442 | tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
443 | break; | ||
444 | |||
445 | + case NEON_2RM_VCEQ0: | ||
446 | + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, | ||
447 | + vec_size, &ceq0_op[size]); | ||
448 | + break; | ||
449 | + case NEON_2RM_VCGT0: | ||
450 | + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, | ||
451 | + vec_size, &cgt0_op[size]); | ||
452 | + break; | ||
453 | + case NEON_2RM_VCLE0: | ||
454 | + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, | ||
455 | + vec_size, &cle0_op[size]); | ||
456 | + break; | ||
457 | + case NEON_2RM_VCGE0: | ||
458 | + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, | ||
459 | + vec_size, &cge0_op[size]); | ||
460 | + break; | ||
461 | + case NEON_2RM_VCLT0: | ||
462 | + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, | ||
463 | + vec_size, &clt0_op[size]); | ||
464 | + break; | ||
465 | + | ||
466 | default: | ||
467 | elementwise: | ||
468 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
469 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
470 | default: abort(); | ||
471 | } | ||
472 | break; | ||
473 | - case NEON_2RM_VCGT0: case NEON_2RM_VCLE0: | ||
474 | - tmp2 = tcg_const_i32(0); | ||
475 | - switch(size) { | ||
476 | - case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break; | ||
477 | - case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break; | ||
478 | - case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break; | ||
479 | - default: abort(); | ||
480 | - } | ||
481 | - tcg_temp_free_i32(tmp2); | ||
482 | - if (op == NEON_2RM_VCLE0) { | ||
483 | - tcg_gen_not_i32(tmp, tmp); | ||
484 | - } | ||
485 | - break; | ||
486 | - case NEON_2RM_VCGE0: case NEON_2RM_VCLT0: | ||
487 | - tmp2 = tcg_const_i32(0); | ||
488 | - switch(size) { | ||
489 | - case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break; | ||
490 | - case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break; | ||
491 | - case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break; | ||
492 | - default: abort(); | ||
493 | - } | ||
494 | - tcg_temp_free_i32(tmp2); | ||
495 | - if (op == NEON_2RM_VCLT0) { | ||
496 | - tcg_gen_not_i32(tmp, tmp); | ||
497 | - } | ||
498 | - break; | ||
499 | - case NEON_2RM_VCEQ0: | ||
500 | - tmp2 = tcg_const_i32(0); | ||
501 | - switch(size) { | ||
502 | - case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break; | ||
503 | - case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break; | ||
504 | - case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break; | ||
505 | - default: abort(); | ||
506 | - } | ||
507 | - tcg_temp_free_i32(tmp2); | ||
508 | - break; | ||
509 | case NEON_2RM_VCGT0_F: | ||
510 | { | ||
511 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
199 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | 512 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c |
200 | index XXXXXXX..XXXXXXX 100644 | 513 | index XXXXXXX..XXXXXXX 100644 |
201 | --- a/target/arm/vec_helper.c | 514 | --- a/target/arm/vec_helper.c |
202 | +++ b/target/arm/vec_helper.c | 515 | +++ b/target/arm/vec_helper.c |
203 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | 516 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) |
204 | } | 517 | } |
205 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
206 | } | 518 | } |
207 | + | 519 | #endif |
208 | +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, | 520 | + |
209 | + void *vfpst, uint32_t desc) | 521 | +#define DO_CMP0(NAME, TYPE, OP) \ |
210 | +{ | 522 | +void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ |
211 | + uintptr_t opr_sz = simd_oprsz(desc); | 523 | +{ \ |
212 | + float16 *d = vd; | 524 | + intptr_t i, opr_sz = simd_oprsz(desc); \ |
213 | + float16 *n = vn; | 525 | + for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \ |
214 | + float16 *m = vm; | 526 | + TYPE nn = *(TYPE *)(vn + i); \ |
215 | + float_status *fpst = vfpst; | 527 | + *(TYPE *)(vd + i) = -(nn OP 0); \ |
216 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | 528 | + } \ |
217 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | 529 | + clear_tail(vd, opr_sz, simd_maxsz(desc)); \ |
218 | + uint32_t neg_real = flip ^ neg_imag; | 530 | +} |
219 | + uintptr_t i; | 531 | + |
220 | + | 532 | +DO_CMP0(gvec_ceq0_b, int8_t, ==) |
221 | + /* Shift boolean to the sign bit so we can xor to negate. */ | 533 | +DO_CMP0(gvec_clt0_b, int8_t, <) |
222 | + neg_real <<= 15; | 534 | +DO_CMP0(gvec_cle0_b, int8_t, <=) |
223 | + neg_imag <<= 15; | 535 | +DO_CMP0(gvec_cgt0_b, int8_t, >) |
224 | + | 536 | +DO_CMP0(gvec_cge0_b, int8_t, >=) |
225 | + for (i = 0; i < opr_sz / 2; i += 2) { | 537 | + |
226 | + float16 e2 = n[H2(i + flip)]; | 538 | +DO_CMP0(gvec_ceq0_h, int16_t, ==) |
227 | + float16 e1 = m[H2(i + flip)] ^ neg_real; | 539 | +DO_CMP0(gvec_clt0_h, int16_t, <) |
228 | + float16 e4 = e2; | 540 | +DO_CMP0(gvec_cle0_h, int16_t, <=) |
229 | + float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; | 541 | +DO_CMP0(gvec_cgt0_h, int16_t, >) |
230 | + | 542 | +DO_CMP0(gvec_cge0_h, int16_t, >=) |
231 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | 543 | + |
232 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | 544 | +#undef DO_CMP0 |
233 | + } | ||
234 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
235 | +} | ||
236 | + | ||
237 | +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, | ||
238 | + void *vfpst, uint32_t desc) | ||
239 | +{ | ||
240 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
241 | + float16 *d = vd; | ||
242 | + float16 *n = vn; | ||
243 | + float16 *m = vm; | ||
244 | + float_status *fpst = vfpst; | ||
245 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
246 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
247 | + uint32_t neg_real = flip ^ neg_imag; | ||
248 | + uintptr_t i; | ||
249 | + float16 e1 = m[H2(flip)]; | ||
250 | + float16 e3 = m[H2(1 - flip)]; | ||
251 | + | ||
252 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
253 | + neg_real <<= 15; | ||
254 | + neg_imag <<= 15; | ||
255 | + e1 ^= neg_real; | ||
256 | + e3 ^= neg_imag; | ||
257 | + | ||
258 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
259 | + float16 e2 = n[H2(i + flip)]; | ||
260 | + float16 e4 = e2; | ||
261 | + | ||
262 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
263 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
264 | + } | ||
265 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
266 | +} | ||
267 | + | ||
268 | +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, | ||
269 | + void *vfpst, uint32_t desc) | ||
270 | +{ | ||
271 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
272 | + float32 *d = vd; | ||
273 | + float32 *n = vn; | ||
274 | + float32 *m = vm; | ||
275 | + float_status *fpst = vfpst; | ||
276 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
277 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
278 | + uint32_t neg_real = flip ^ neg_imag; | ||
279 | + uintptr_t i; | ||
280 | + | ||
281 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
282 | + neg_real <<= 31; | ||
283 | + neg_imag <<= 31; | ||
284 | + | ||
285 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
286 | + float32 e2 = n[H4(i + flip)]; | ||
287 | + float32 e1 = m[H4(i + flip)] ^ neg_real; | ||
288 | + float32 e4 = e2; | ||
289 | + float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; | ||
290 | + | ||
291 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
292 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
293 | + } | ||
294 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
295 | +} | ||
296 | + | ||
297 | +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, | ||
298 | + void *vfpst, uint32_t desc) | ||
299 | +{ | ||
300 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
301 | + float32 *d = vd; | ||
302 | + float32 *n = vn; | ||
303 | + float32 *m = vm; | ||
304 | + float_status *fpst = vfpst; | ||
305 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
306 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
307 | + uint32_t neg_real = flip ^ neg_imag; | ||
308 | + uintptr_t i; | ||
309 | + float32 e1 = m[H4(flip)]; | ||
310 | + float32 e3 = m[H4(1 - flip)]; | ||
311 | + | ||
312 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
313 | + neg_real <<= 31; | ||
314 | + neg_imag <<= 31; | ||
315 | + e1 ^= neg_real; | ||
316 | + e3 ^= neg_imag; | ||
317 | + | ||
318 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
319 | + float32 e2 = n[H4(i + flip)]; | ||
320 | + float32 e4 = e2; | ||
321 | + | ||
322 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
323 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
324 | + } | ||
325 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
326 | +} | ||
327 | + | ||
328 | +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, | ||
329 | + void *vfpst, uint32_t desc) | ||
330 | +{ | ||
331 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
332 | + float64 *d = vd; | ||
333 | + float64 *n = vn; | ||
334 | + float64 *m = vm; | ||
335 | + float_status *fpst = vfpst; | ||
336 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
337 | + uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
338 | + uint64_t neg_real = flip ^ neg_imag; | ||
339 | + uintptr_t i; | ||
340 | + | ||
341 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
342 | + neg_real <<= 63; | ||
343 | + neg_imag <<= 63; | ||
344 | + | ||
345 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
346 | + float64 e2 = n[i + flip]; | ||
347 | + float64 e1 = m[i + flip] ^ neg_real; | ||
348 | + float64 e4 = e2; | ||
349 | + float64 e3 = m[i + 1 - flip] ^ neg_imag; | ||
350 | + | ||
351 | + d[i] = float64_muladd(e2, e1, d[i], 0, fpst); | ||
352 | + d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); | ||
353 | + } | ||
354 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
355 | +} | ||
356 | -- | 545 | -- |
357 | 2.16.2 | 546 | 2.20.1 |
358 | 547 | ||
359 | 548 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jerome Forissier <jerome@forissier.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | The /secure-chosen node is currently used only by create_uart(), but |
4 | Message-id: 20180228193125.20577-15-richard.henderson@linaro.org | 4 | this will change. Therefore move the creation of this node to |
5 | create_fdt(). | ||
6 | |||
7 | Signed-off-by: Jerome Forissier <jerome@forissier.org> | ||
8 | Message-id: 20200420121807.8204-2-jerome@forissier.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 12 | hw/arm/virt.c | 5 ++++- |
9 | 1 file changed, 61 insertions(+) | 13 | 1 file changed, 4 insertions(+), 1 deletion(-) |
10 | 14 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 15 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 17 | --- a/hw/arm/virt.c |
14 | +++ b/target/arm/translate.c | 18 | +++ b/hw/arm/virt.c |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms) |
16 | return 0; | 20 | /* /chosen must exist for load_dtb to fill in necessary properties later */ |
17 | } | 21 | qemu_fdt_add_subnode(fdt, "/chosen"); |
18 | 22 | ||
19 | +/* Advanced SIMD two registers and a scalar extension. | 23 | + if (vms->secure) { |
20 | + * 31 24 23 22 20 16 12 11 10 9 8 3 0 | 24 | + qemu_fdt_add_subnode(fdt, "/secure-chosen"); |
21 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
22 | + * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
23 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
24 | + * | ||
25 | + */ | ||
26 | + | ||
27 | +static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | ||
28 | +{ | ||
29 | + int rd, rn, rm, rot, size, opr_sz; | ||
30 | + TCGv_ptr fpst; | ||
31 | + bool q; | ||
32 | + | ||
33 | + q = extract32(insn, 6, 1); | ||
34 | + VFP_DREG_D(rd, insn); | ||
35 | + VFP_DREG_N(rn, insn); | ||
36 | + VFP_DREG_M(rm, insn); | ||
37 | + if ((rd | rn) & q) { | ||
38 | + return 1; | ||
39 | + } | 25 | + } |
40 | + | 26 | + |
41 | + if ((insn & 0xff000f10) == 0xfe000800) { | 27 | /* Clock node, for the benefit of the UART. The kernel device tree |
42 | + /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ | 28 | * binding documentation claims the PL011 node clock properties are |
43 | + rot = extract32(insn, 20, 2); | 29 | * optional but in practice if you omit them the kernel refuses to |
44 | + size = extract32(insn, 23, 1); | 30 | @@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, int uart, |
45 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | 31 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); |
46 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | 32 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); |
47 | + return 1; | 33 | |
48 | + } | 34 | - qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); |
49 | + } else { | 35 | qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", |
50 | + return 1; | 36 | nodename); |
51 | + } | 37 | } |
52 | + | ||
53 | + if (s->fp_excp_el) { | ||
54 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
55 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
56 | + return 0; | ||
57 | + } | ||
58 | + if (!s->vfp_enabled) { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + opr_sz = (1 + q) * 8; | ||
63 | + fpst = get_fpstatus_ptr(1); | ||
64 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
65 | + vfp_reg_offset(1, rn), | ||
66 | + vfp_reg_offset(1, rm), fpst, | ||
67 | + opr_sz, opr_sz, rot, | ||
68 | + size ? gen_helper_gvec_fcmlas_idx | ||
69 | + : gen_helper_gvec_fcmlah_idx); | ||
70 | + tcg_temp_free_ptr(fpst); | ||
71 | + return 0; | ||
72 | +} | ||
73 | + | ||
74 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | ||
75 | { | ||
76 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
77 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
78 | goto illegal_op; | ||
79 | } | ||
80 | return; | ||
81 | + } else if ((insn & 0x0f000a00) == 0x0e000800 | ||
82 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
83 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
84 | + goto illegal_op; | ||
85 | + } | ||
86 | + return; | ||
87 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
88 | /* Coprocessor double register transfer. */ | ||
89 | ARCH(5TE); | ||
90 | -- | 38 | -- |
91 | 2.16.2 | 39 | 2.20.1 |
92 | 40 | ||
93 | 41 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jerome Forissier <jerome@forissier.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Generate random seeds to be used by the non-secure and/or secure OSes |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | for ASLR. The seeds are 64-bit random values exported via the DT |
5 | Message-id: 20180228193125.20577-5-richard.henderson@linaro.org | 5 | properties /chosen/kaslr-seed [1] and /secure-chosen/kaslr-seed, the |
6 | latter being used by OP-TEE [2]. | ||
7 | |||
8 | [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5bc0c37c97e1 | ||
9 | [2] https://github.com/OP-TEE/optee_os/commit/ef262691fe0e | ||
10 | |||
11 | Signed-off-by: Jerome Forissier <jerome@forissier.org> | ||
12 | Message-id: 20200420121807.8204-3-jerome@forissier.org | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 15 | --- |
8 | target/arm/Makefile.objs | 2 +- | 16 | hw/arm/virt.c | 15 +++++++++++++++ |
9 | target/arm/helper.h | 4 ++ | 17 | 1 file changed, 15 insertions(+) |
10 | target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ | ||
12 | 4 files changed, 198 insertions(+), 1 deletion(-) | ||
13 | create mode 100644 target/arm/vec_helper.c | ||
14 | 18 | ||
15 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | 19 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/Makefile.objs | 21 | --- a/hw/arm/virt.c |
18 | +++ b/target/arm/Makefile.objs | 22 | +++ b/hw/arm/virt.c |
19 | @@ -XXX,XX +XXX,XX @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o | 23 | @@ -XXX,XX +XXX,XX @@ |
20 | obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o | 24 | #include "hw/acpi/generic_event_device.h" |
21 | obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o | 25 | #include "hw/virtio/virtio-iommu.h" |
22 | obj-y += translate.o op_helper.o helper.o cpu.o | 26 | #include "hw/char/pl011.h" |
23 | -obj-y += neon_helper.o iwmmxt_helper.o | 27 | +#include "qemu/guest-random.h" |
24 | +obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o | 28 | |
25 | obj-y += gdbstub.o | 29 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ |
26 | obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o | 30 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ |
27 | obj-y += crypto_helper.o | 31 | @@ -XXX,XX +XXX,XX @@ static bool cpu_type_valid(const char *cpu) |
28 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 32 | return false; |
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/helper.h | ||
31 | +++ b/target/arm/helper.h | ||
32 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) | ||
33 | |||
34 | DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) | ||
36 | +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) | ||
37 | +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) | ||
38 | DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) | ||
39 | DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) | ||
40 | +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) | ||
41 | +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) | ||
42 | |||
43 | DEF_HELPER_1(neon_narrow_u8, i32, i64) | ||
44 | DEF_HELPER_1(neon_narrow_u16, i32, i64) | ||
45 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-a64.c | ||
48 | +++ b/target/arm/translate-a64.c | ||
49 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | ||
50 | tcg_temp_free_ptr(fpst); | ||
51 | } | 33 | } |
52 | 34 | ||
53 | +/* AdvSIMD scalar three same extra | 35 | +static void create_kaslr_seed(VirtMachineState *vms, const char *node) |
54 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
55 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
56 | + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
57 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
58 | + */ | ||
59 | +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | ||
60 | + uint32_t insn) | ||
61 | +{ | 36 | +{ |
62 | + int rd = extract32(insn, 0, 5); | 37 | + Error *err = NULL; |
63 | + int rn = extract32(insn, 5, 5); | 38 | + uint64_t seed; |
64 | + int opcode = extract32(insn, 11, 4); | ||
65 | + int rm = extract32(insn, 16, 5); | ||
66 | + int size = extract32(insn, 22, 2); | ||
67 | + bool u = extract32(insn, 29, 1); | ||
68 | + TCGv_i32 ele1, ele2, ele3; | ||
69 | + TCGv_i64 res; | ||
70 | + int feature; | ||
71 | + | 39 | + |
72 | + switch (u * 16 + opcode) { | 40 | + if (qemu_guest_getrandom(&seed, sizeof(seed), &err)) { |
73 | + case 0x10: /* SQRDMLAH (vector) */ | 41 | + error_free(err); |
74 | + case 0x11: /* SQRDMLSH (vector) */ | ||
75 | + if (size != 1 && size != 2) { | ||
76 | + unallocated_encoding(s); | ||
77 | + return; | ||
78 | + } | ||
79 | + feature = ARM_FEATURE_V8_RDM; | ||
80 | + break; | ||
81 | + default: | ||
82 | + unallocated_encoding(s); | ||
83 | + return; | 42 | + return; |
84 | + } | 43 | + } |
85 | + if (!arm_dc_feature(s, feature)) { | 44 | + qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed); |
86 | + unallocated_encoding(s); | ||
87 | + return; | ||
88 | + } | ||
89 | + if (!fp_access_check(s)) { | ||
90 | + return; | ||
91 | + } | ||
92 | + | ||
93 | + /* Do a single operation on the lowest element in the vector. | ||
94 | + * We use the standard Neon helpers and rely on 0 OP 0 == 0 | ||
95 | + * with no side effects for all these operations. | ||
96 | + * OPTME: special-purpose helpers would avoid doing some | ||
97 | + * unnecessary work in the helper for the 16 bit cases. | ||
98 | + */ | ||
99 | + ele1 = tcg_temp_new_i32(); | ||
100 | + ele2 = tcg_temp_new_i32(); | ||
101 | + ele3 = tcg_temp_new_i32(); | ||
102 | + | ||
103 | + read_vec_element_i32(s, ele1, rn, 0, size); | ||
104 | + read_vec_element_i32(s, ele2, rm, 0, size); | ||
105 | + read_vec_element_i32(s, ele3, rd, 0, size); | ||
106 | + | ||
107 | + switch (opcode) { | ||
108 | + case 0x0: /* SQRDMLAH */ | ||
109 | + if (size == 1) { | ||
110 | + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
111 | + } else { | ||
112 | + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
113 | + } | ||
114 | + break; | ||
115 | + case 0x1: /* SQRDMLSH */ | ||
116 | + if (size == 1) { | ||
117 | + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
118 | + } else { | ||
119 | + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
120 | + } | ||
121 | + break; | ||
122 | + default: | ||
123 | + g_assert_not_reached(); | ||
124 | + } | ||
125 | + tcg_temp_free_i32(ele1); | ||
126 | + tcg_temp_free_i32(ele2); | ||
127 | + | ||
128 | + res = tcg_temp_new_i64(); | ||
129 | + tcg_gen_extu_i32_i64(res, ele3); | ||
130 | + tcg_temp_free_i32(ele3); | ||
131 | + | ||
132 | + write_fp_dreg(s, rd, res); | ||
133 | + tcg_temp_free_i64(res); | ||
134 | +} | 45 | +} |
135 | + | 46 | + |
136 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, | 47 | static void create_fdt(VirtMachineState *vms) |
137 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, | 48 | { |
138 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | 49 | MachineState *ms = MACHINE(vms); |
139 | @@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = { | 50 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms) |
140 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | 51 | |
141 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | 52 | /* /chosen must exist for load_dtb to fill in necessary properties later */ |
142 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | 53 | qemu_fdt_add_subnode(fdt, "/chosen"); |
143 | + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, | 54 | + create_kaslr_seed(vms, "/chosen"); |
144 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | 55 | |
145 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | 56 | if (vms->secure) { |
146 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | 57 | qemu_fdt_add_subnode(fdt, "/secure-chosen"); |
147 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | 58 | + create_kaslr_seed(vms, "/secure-chosen"); |
148 | new file mode 100644 | 59 | } |
149 | index XXXXXXX..XXXXXXX | 60 | |
150 | --- /dev/null | 61 | /* Clock node, for the benefit of the UART. The kernel device tree |
151 | +++ b/target/arm/vec_helper.c | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | +/* | ||
154 | + * ARM AdvSIMD / SVE Vector Operations | ||
155 | + * | ||
156 | + * Copyright (c) 2018 Linaro | ||
157 | + * | ||
158 | + * This library is free software; you can redistribute it and/or | ||
159 | + * modify it under the terms of the GNU Lesser General Public | ||
160 | + * License as published by the Free Software Foundation; either | ||
161 | + * version 2 of the License, or (at your option) any later version. | ||
162 | + * | ||
163 | + * This library is distributed in the hope that it will be useful, | ||
164 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
165 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
166 | + * Lesser General Public License for more details. | ||
167 | + * | ||
168 | + * You should have received a copy of the GNU Lesser General Public | ||
169 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
170 | + */ | ||
171 | + | ||
172 | +#include "qemu/osdep.h" | ||
173 | +#include "cpu.h" | ||
174 | +#include "exec/exec-all.h" | ||
175 | +#include "exec/helper-proto.h" | ||
176 | +#include "tcg/tcg-gvec-desc.h" | ||
177 | + | ||
178 | + | ||
179 | +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
180 | + | ||
181 | +/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
182 | +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
183 | + int16_t src2, int16_t src3) | ||
184 | +{ | ||
185 | + /* Simplify: | ||
186 | + * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
187 | + * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 | ||
188 | + */ | ||
189 | + int32_t ret = (int32_t)src1 * src2; | ||
190 | + ret = ((int32_t)src3 << 15) + ret + (1 << 14); | ||
191 | + ret >>= 15; | ||
192 | + if (ret != (int16_t)ret) { | ||
193 | + SET_QC(); | ||
194 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
195 | + } | ||
196 | + return ret; | ||
197 | +} | ||
198 | + | ||
199 | +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
200 | + uint32_t src2, uint32_t src3) | ||
201 | +{ | ||
202 | + uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3); | ||
203 | + uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
204 | + return deposit32(e1, 16, 16, e2); | ||
205 | +} | ||
206 | + | ||
207 | +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | ||
208 | +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | ||
209 | + int16_t src2, int16_t src3) | ||
210 | +{ | ||
211 | + /* Similarly, using subtraction: | ||
212 | + * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
213 | + * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 | ||
214 | + */ | ||
215 | + int32_t ret = (int32_t)src1 * src2; | ||
216 | + ret = ((int32_t)src3 << 15) - ret + (1 << 14); | ||
217 | + ret >>= 15; | ||
218 | + if (ret != (int16_t)ret) { | ||
219 | + SET_QC(); | ||
220 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
221 | + } | ||
222 | + return ret; | ||
223 | +} | ||
224 | + | ||
225 | +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
226 | + uint32_t src2, uint32_t src3) | ||
227 | +{ | ||
228 | + uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3); | ||
229 | + uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
230 | + return deposit32(e1, 16, 16, e2); | ||
231 | +} | ||
232 | + | ||
233 | +/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
234 | +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
235 | + int32_t src2, int32_t src3) | ||
236 | +{ | ||
237 | + /* Simplify similarly to int_qrdmlah_s16 above. */ | ||
238 | + int64_t ret = (int64_t)src1 * src2; | ||
239 | + ret = ((int64_t)src3 << 31) + ret + (1 << 30); | ||
240 | + ret >>= 31; | ||
241 | + if (ret != (int32_t)ret) { | ||
242 | + SET_QC(); | ||
243 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
244 | + } | ||
245 | + return ret; | ||
246 | +} | ||
247 | + | ||
248 | +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
249 | +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
250 | + int32_t src2, int32_t src3) | ||
251 | +{ | ||
252 | + /* Simplify similarly to int_qrdmlsh_s16 above. */ | ||
253 | + int64_t ret = (int64_t)src1 * src2; | ||
254 | + ret = ((int64_t)src3 << 31) - ret + (1 << 30); | ||
255 | + ret >>= 31; | ||
256 | + if (ret != (int32_t)ret) { | ||
257 | + SET_QC(); | ||
258 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
259 | + } | ||
260 | + return ret; | ||
261 | +} | ||
262 | -- | 62 | -- |
263 | 2.16.2 | 63 | 2.20.1 |
264 | 64 | ||
265 | 65 | diff view generated by jsdifflib |
1 | In v8M, the Implementation Defined Attribution Unit (IDAU) is | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | a small piece of hardware typically implemented in the SoC | ||
3 | which provides board or SoC specific security attribution | ||
4 | information for each address that the CPU performs MPU/SAU | ||
5 | checks on. For QEMU, we model this with a QOM interface which | ||
6 | is implemented by the board or SoC object and connected to | ||
7 | the CPU using a link property. | ||
8 | 2 | ||
9 | This commit defines the new interface class, adds the link | 3 | Under KVM these registers are written by the hardware. |
10 | property to the CPU object, and makes the SAU checking | 4 | Restrict the writefn handlers to TCG to avoid when building |
11 | code call the IDAU interface if one is present. | 5 | without TCG: |
12 | 6 | ||
7 | LINK aarch64-softmmu/qemu-system-aarch64 | ||
8 | target/arm/helper.o: In function `do_ats_write': | ||
9 | target/arm/helper.c:3524: undefined reference to `raise_exception' | ||
10 | |||
11 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
14 | Message-id: 20200423073358.27155-2-philmd@redhat.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20180220180325.29818-5-peter.maydell@linaro.org | ||
16 | --- | 16 | --- |
17 | target/arm/cpu.h | 3 +++ | 17 | target/arm/helper.c | 17 +++++++++++++++++ |
18 | target/arm/idau.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++ | 18 | 1 file changed, 17 insertions(+) |
19 | target/arm/cpu.c | 15 +++++++++++++ | ||
20 | target/arm/helper.c | 28 +++++++++++++++++++++--- | ||
21 | 4 files changed, 104 insertions(+), 3 deletions(-) | ||
22 | create mode 100644 target/arm/idau.h | ||
23 | 19 | ||
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/cpu.h | ||
27 | +++ b/target/arm/cpu.h | ||
28 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
29 | /* MemoryRegion to use for secure physical accesses */ | ||
30 | MemoryRegion *secure_memory; | ||
31 | |||
32 | + /* For v8M, pointer to the IDAU interface provided by board/SoC */ | ||
33 | + Object *idau; | ||
34 | + | ||
35 | /* 'compatible' string for this CPU for Linux device trees */ | ||
36 | const char *dtb_compatible; | ||
37 | |||
38 | diff --git a/target/arm/idau.h b/target/arm/idau.h | ||
39 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | ||
41 | --- /dev/null | ||
42 | +++ b/target/arm/idau.h | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +/* | ||
45 | + * QEMU ARM CPU -- interface for the Arm v8M IDAU | ||
46 | + * | ||
47 | + * Copyright (c) 2018 Linaro Ltd | ||
48 | + * | ||
49 | + * This program is free software; you can redistribute it and/or | ||
50 | + * modify it under the terms of the GNU General Public License | ||
51 | + * as published by the Free Software Foundation; either version 2 | ||
52 | + * of the License, or (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program; if not, see | ||
61 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
62 | + * | ||
63 | + * In the v8M architecture, the IDAU is a small piece of hardware | ||
64 | + * typically implemented in the SoC which provides board or SoC | ||
65 | + * specific security attribution information for each address that | ||
66 | + * the CPU performs MPU/SAU checks on. For QEMU, we model this with a | ||
67 | + * QOM interface which is implemented by the board or SoC object and | ||
68 | + * connected to the CPU using a link property. | ||
69 | + */ | ||
70 | + | ||
71 | +#ifndef TARGET_ARM_IDAU_H | ||
72 | +#define TARGET_ARM_IDAU_H | ||
73 | + | ||
74 | +#include "qom/object.h" | ||
75 | + | ||
76 | +#define TYPE_IDAU_INTERFACE "idau-interface" | ||
77 | +#define IDAU_INTERFACE(obj) \ | ||
78 | + INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE) | ||
79 | +#define IDAU_INTERFACE_CLASS(class) \ | ||
80 | + OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE) | ||
81 | +#define IDAU_INTERFACE_GET_CLASS(obj) \ | ||
82 | + OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE) | ||
83 | + | ||
84 | +typedef struct IDAUInterface { | ||
85 | + Object parent; | ||
86 | +} IDAUInterface; | ||
87 | + | ||
88 | +#define IREGION_NOTVALID -1 | ||
89 | + | ||
90 | +typedef struct IDAUInterfaceClass { | ||
91 | + InterfaceClass parent; | ||
92 | + | ||
93 | + /* Check the specified address and return the IDAU security information | ||
94 | + * for it by filling in iregion, exempt, ns and nsc: | ||
95 | + * iregion: IDAU region number, or IREGION_NOTVALID if not valid | ||
96 | + * exempt: true if address is exempt from security attribution | ||
97 | + * ns: true if the address is NonSecure | ||
98 | + * nsc: true if the address is NonSecure-callable | ||
99 | + */ | ||
100 | + void (*check)(IDAUInterface *ii, uint32_t address, int *iregion, | ||
101 | + bool *exempt, bool *ns, bool *nsc); | ||
102 | +} IDAUInterfaceClass; | ||
103 | + | ||
104 | +#endif | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/cpu.c | ||
108 | +++ b/target/arm/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ | ||
110 | */ | ||
111 | |||
112 | #include "qemu/osdep.h" | ||
113 | +#include "target/arm/idau.h" | ||
114 | #include "qemu/error-report.h" | ||
115 | #include "qapi/error.h" | ||
116 | #include "cpu.h" | ||
117 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | ||
118 | } | ||
119 | } | ||
120 | |||
121 | + if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { | ||
122 | + object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | ||
123 | + qdev_prop_allow_set_link_before_realize, | ||
124 | + OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
125 | + &error_abort); | ||
126 | + } | ||
127 | + | ||
128 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
129 | &error_abort); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { | ||
132 | .class_init = arm_cpu_class_init, | ||
133 | }; | ||
134 | |||
135 | +static const TypeInfo idau_interface_type_info = { | ||
136 | + .name = TYPE_IDAU_INTERFACE, | ||
137 | + .parent = TYPE_INTERFACE, | ||
138 | + .class_size = sizeof(IDAUInterfaceClass), | ||
139 | +}; | ||
140 | + | ||
141 | static void arm_cpu_register_types(void) | ||
142 | { | ||
143 | const ARMCPUInfo *info = arm_cpus; | ||
144 | |||
145 | type_register_static(&arm_cpu_type_info); | ||
146 | + type_register_static(&idau_interface_type_info); | ||
147 | |||
148 | while (info->name) { | ||
149 | cpu_register(info); | ||
150 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 20 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
151 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
152 | --- a/target/arm/helper.c | 22 | --- a/target/arm/helper.c |
153 | +++ b/target/arm/helper.c | 23 | +++ b/target/arm/helper.c |
154 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
155 | #include "qemu/osdep.h" | 25 | return CP_ACCESS_OK; |
156 | +#include "target/arm/idau.h" | 26 | } |
157 | #include "trace.h" | 27 | |
158 | #include "cpu.h" | 28 | +#ifdef CONFIG_TCG |
159 | #include "internals.h" | 29 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
160 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 30 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
161 | */ | 31 | { |
162 | ARMCPU *cpu = arm_env_get_cpu(env); | 32 | @@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
163 | int r; | ||
164 | + bool idau_exempt = false, idau_ns = true, idau_nsc = true; | ||
165 | + int idau_region = IREGION_NOTVALID; | ||
166 | |||
167 | - /* TODO: implement IDAU */ | ||
168 | + if (cpu->idau) { | ||
169 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | ||
170 | + IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | ||
171 | + | ||
172 | + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | ||
173 | + &idau_nsc); | ||
174 | + } | ||
175 | |||
176 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | ||
177 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | ||
178 | return; | ||
179 | } | 33 | } |
180 | 34 | return par64; | |
181 | - if (v8m_is_sau_exempt(env, address, access_type)) { | 35 | } |
182 | + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { | 36 | +#endif /* CONFIG_TCG */ |
183 | sattrs->ns = !regime_is_secure(env, mmu_idx); | 37 | |
184 | return; | 38 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
39 | { | ||
40 | +#ifdef CONFIG_TCG | ||
41 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; | ||
42 | uint64_t par64; | ||
43 | ARMMMUIdx mmu_idx; | ||
44 | @@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
45 | par64 = do_ats_write(env, value, access_type, mmu_idx); | ||
46 | |||
47 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | ||
48 | +#else | ||
49 | + /* Handled by hardware accelerator. */ | ||
50 | + g_assert_not_reached(); | ||
51 | +#endif /* CONFIG_TCG */ | ||
52 | } | ||
53 | |||
54 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
55 | uint64_t value) | ||
56 | { | ||
57 | +#ifdef CONFIG_TCG | ||
58 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; | ||
59 | uint64_t par64; | ||
60 | |||
61 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); | ||
62 | |||
63 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | ||
64 | +#else | ||
65 | + /* Handled by hardware accelerator. */ | ||
66 | + g_assert_not_reached(); | ||
67 | +#endif /* CONFIG_TCG */ | ||
68 | } | ||
69 | |||
70 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
71 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
72 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, | ||
73 | uint64_t value) | ||
74 | { | ||
75 | +#ifdef CONFIG_TCG | ||
76 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; | ||
77 | ARMMMUIdx mmu_idx; | ||
78 | int secure = arm_is_secure_below_el3(env); | ||
79 | @@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, | ||
185 | } | 80 | } |
186 | 81 | ||
187 | + if (idau_region != IREGION_NOTVALID) { | 82 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
188 | + sattrs->irvalid = true; | 83 | +#else |
189 | + sattrs->iregion = idau_region; | 84 | + /* Handled by hardware accelerator. */ |
190 | + } | 85 | + g_assert_not_reached(); |
191 | + | 86 | +#endif /* CONFIG_TCG */ |
192 | switch (env->sau.ctrl & 3) { | ||
193 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | ||
194 | break; | ||
195 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | ||
196 | } | ||
197 | } | ||
198 | |||
199 | - /* TODO when we support the IDAU then it may override the result here */ | ||
200 | + /* The IDAU will override the SAU lookup results if it specifies | ||
201 | + * higher security than the SAU does. | ||
202 | + */ | ||
203 | + if (!idau_ns) { | ||
204 | + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | ||
205 | + sattrs->ns = false; | ||
206 | + sattrs->nsc = idau_nsc; | ||
207 | + } | ||
208 | + } | ||
209 | break; | ||
210 | } | ||
211 | } | 87 | } |
88 | #endif | ||
89 | |||
212 | -- | 90 | -- |
213 | 2.16.2 | 91 | 2.20.1 |
214 | 92 | ||
215 | 93 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | 3 | Make cpu_register() (renamed to arm_cpu_register()) available |
4 | from internals.h so we can register CPUs also from other files | ||
5 | in the future. | ||
4 | 6 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180228193125.20577-10-richard.henderson@linaro.org | 9 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
10 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
11 | Message-id: 20200423073358.27155-3-philmd@redhat.com | ||
12 | Message-ID: <20190921150420.30743-2-thuth@redhat.com> | ||
13 | [PMD: Only take cpu_register() from Thomas's patch] | ||
14 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 16 | --- |
10 | target/arm/cpu.c | 1 + | 17 | target/arm/cpu-qom.h | 9 ++++++++- |
11 | target/arm/cpu64.c | 1 + | 18 | target/arm/cpu.c | 10 ++-------- |
12 | 2 files changed, 2 insertions(+) | 19 | target/arm/cpu64.c | 8 +------- |
20 | 3 files changed, 11 insertions(+), 16 deletions(-) | ||
13 | 21 | ||
22 | diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/cpu-qom.h | ||
25 | +++ b/target/arm/cpu-qom.h | ||
26 | @@ -XXX,XX +XXX,XX @@ struct arm_boot_info; | ||
27 | |||
28 | #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU | ||
29 | |||
30 | -typedef struct ARMCPUInfo ARMCPUInfo; | ||
31 | +typedef struct ARMCPUInfo { | ||
32 | + const char *name; | ||
33 | + void (*initfn)(Object *obj); | ||
34 | + void (*class_init)(ObjectClass *oc, void *data); | ||
35 | +} ARMCPUInfo; | ||
36 | + | ||
37 | +void arm_cpu_register(const ARMCPUInfo *info); | ||
38 | +void aarch64_cpu_register(const ARMCPUInfo *info); | ||
39 | |||
40 | /** | ||
41 | * ARMCPUClass: | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 42 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 44 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 45 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 46 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | 47 | |
20 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 48 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
21 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 49 | |
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 50 | -struct ARMCPUInfo { |
23 | cpu->midr = 0xffffffff; | 51 | - const char *name; |
52 | - void (*initfn)(Object *obj); | ||
53 | - void (*class_init)(ObjectClass *oc, void *data); | ||
54 | -}; | ||
55 | - | ||
56 | static const ARMCPUInfo arm_cpus[] = { | ||
57 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
58 | { .name = "arm926", .initfn = arm926_initfn }, | ||
59 | @@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data) | ||
60 | acc->info = data; | ||
24 | } | 61 | } |
25 | #endif | 62 | |
63 | -static void cpu_register(const ARMCPUInfo *info) | ||
64 | +void arm_cpu_register(const ARMCPUInfo *info) | ||
65 | { | ||
66 | TypeInfo type_info = { | ||
67 | .parent = TYPE_ARM_CPU, | ||
68 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void) | ||
69 | type_register_static(&idau_interface_type_info); | ||
70 | |||
71 | while (info->name) { | ||
72 | - cpu_register(info); | ||
73 | + arm_cpu_register(info); | ||
74 | info++; | ||
75 | } | ||
76 | |||
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 77 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
27 | index XXXXXXX..XXXXXXX 100644 | 78 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/cpu64.c | 79 | --- a/target/arm/cpu64.c |
29 | +++ b/target/arm/cpu64.c | 80 | +++ b/target/arm/cpu64.c |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 81 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
31 | set_feature(&cpu->env, ARM_FEATURE_V8_SM4); | 82 | cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 83 | } |
33 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 84 | |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 85 | -struct ARMCPUInfo { |
35 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 86 | - const char *name; |
36 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 87 | - void (*initfn)(Object *obj); |
37 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 88 | - void (*class_init)(ObjectClass *oc, void *data); |
89 | -}; | ||
90 | - | ||
91 | static const ARMCPUInfo aarch64_cpus[] = { | ||
92 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | ||
93 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | ||
94 | @@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data) | ||
95 | acc->info = data; | ||
96 | } | ||
97 | |||
98 | -static void aarch64_cpu_register(const ARMCPUInfo *info) | ||
99 | +void aarch64_cpu_register(const ARMCPUInfo *info) | ||
100 | { | ||
101 | TypeInfo type_info = { | ||
102 | .parent = TYPE_AARCH64_CPU, | ||
38 | -- | 103 | -- |
39 | 2.16.2 | 104 | 2.20.1 |
40 | 105 | ||
41 | 106 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | 3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
4 | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Message-id: 20200423073358.27155-4-philmd@redhat.com |
7 | Message-id: 20180228193125.20577-17-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 8 | --- |
10 | target/arm/cpu.c | 1 + | 9 | target/arm/cpu.c | 8 +++----- |
11 | target/arm/cpu64.c | 1 + | 10 | target/arm/cpu64.c | 8 +++----- |
12 | 2 files changed, 2 insertions(+) | 11 | 2 files changed, 6 insertions(+), 10 deletions(-) |
13 | 12 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 15 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 16 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 18 | { .name = "any", .initfn = arm_max_initfn }, |
20 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
21 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | ||
23 | cpu->midr = 0xffffffff; | ||
24 | } | ||
25 | #endif | 19 | #endif |
20 | #endif | ||
21 | - { .name = NULL } | ||
22 | }; | ||
23 | |||
24 | static Property arm_cpu_properties[] = { | ||
25 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo idau_interface_type_info = { | ||
26 | |||
27 | static void arm_cpu_register_types(void) | ||
28 | { | ||
29 | - const ARMCPUInfo *info = arm_cpus; | ||
30 | + size_t i; | ||
31 | |||
32 | type_register_static(&arm_cpu_type_info); | ||
33 | type_register_static(&idau_interface_type_info); | ||
34 | |||
35 | - while (info->name) { | ||
36 | - arm_cpu_register(info); | ||
37 | - info++; | ||
38 | + for (i = 0; i < ARRAY_SIZE(arm_cpus); ++i) { | ||
39 | + arm_cpu_register(&arm_cpus[i]); | ||
40 | } | ||
41 | |||
42 | #ifdef CONFIG_KVM | ||
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 43 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
27 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/cpu64.c | 45 | --- a/target/arm/cpu64.c |
29 | +++ b/target/arm/cpu64.c | 46 | +++ b/target/arm/cpu64.c |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 47 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { |
31 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 48 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 49 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, |
33 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 50 | { .name = "max", .initfn = aarch64_max_initfn }, |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 51 | - { .name = NULL } |
35 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 52 | }; |
36 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 53 | |
54 | static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) | ||
55 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aarch64_cpu_type_info = { | ||
56 | |||
57 | static void aarch64_cpu_register_types(void) | ||
58 | { | ||
59 | - const ARMCPUInfo *info = aarch64_cpus; | ||
60 | + size_t i; | ||
61 | |||
62 | type_register_static(&aarch64_cpu_type_info); | ||
63 | |||
64 | - while (info->name) { | ||
65 | - aarch64_cpu_register(info); | ||
66 | - info++; | ||
67 | + for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { | ||
68 | + aarch64_cpu_register(&aarch64_cpus[i]); | ||
69 | } | ||
37 | } | 70 | } |
71 | |||
38 | -- | 72 | -- |
39 | 2.16.2 | 73 | 2.20.1 |
40 | 74 | ||
41 | 75 | diff view generated by jsdifflib |
1 | Add a Cortex-M33 definition. The M33 is an M profile CPU | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | which implements the ARM v8M architecture, including the | ||
3 | M profile Security Extension. | ||
4 | 2 | ||
3 | We will move this code in the next commit. Clean it up | ||
4 | first to avoid checkpatch.pl errors. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Message-id: 20200423073358.27155-5-philmd@redhat.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-9-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++ | 11 | target/arm/cpu.c | 9 ++++++--- |
10 | 1 file changed, 31 insertions(+) | 12 | 1 file changed, 6 insertions(+), 3 deletions(-) |
11 | 13 | ||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/cpu.c | 16 | --- a/target/arm/cpu.c |
15 | +++ b/target/arm/cpu.c | 17 | +++ b/target/arm/cpu.c |
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
17 | cpu->id_isar5 = 0x00000000; | 19 | CPUARMState *env = &cpu->env; |
18 | } | 20 | bool ret = false; |
19 | 21 | ||
20 | +static void cortex_m33_initfn(Object *obj) | 22 | - /* ARMv7-M interrupt masking works differently than -A or -R. |
21 | +{ | 23 | + /* |
22 | + ARMCPU *cpu = ARM_CPU(obj); | 24 | + * ARMv7-M interrupt masking works differently than -A or -R. |
23 | + | 25 | * There is no FIQ/IRQ distinction. Instead of I and F bits |
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 26 | * masking FIQ and IRQ interrupts, an exception is taken only |
25 | + set_feature(&cpu->env, ARM_FEATURE_M); | 27 | * if it is higher priority than the current execution priority |
26 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | 28 | @@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj) |
27 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 29 | static void arm1136_r2_initfn(Object *obj) |
28 | + cpu->midr = 0x410fd213; /* r0p3 */ | ||
29 | + cpu->pmsav7_dregion = 16; | ||
30 | + cpu->sau_sregion = 8; | ||
31 | + cpu->id_pfr0 = 0x00000030; | ||
32 | + cpu->id_pfr1 = 0x00000210; | ||
33 | + cpu->id_dfr0 = 0x00200000; | ||
34 | + cpu->id_afr0 = 0x00000000; | ||
35 | + cpu->id_mmfr0 = 0x00101F40; | ||
36 | + cpu->id_mmfr1 = 0x00000000; | ||
37 | + cpu->id_mmfr2 = 0x01000000; | ||
38 | + cpu->id_mmfr3 = 0x00000000; | ||
39 | + cpu->id_isar0 = 0x01101110; | ||
40 | + cpu->id_isar1 = 0x02212000; | ||
41 | + cpu->id_isar2 = 0x20232232; | ||
42 | + cpu->id_isar3 = 0x01111131; | ||
43 | + cpu->id_isar4 = 0x01310132; | ||
44 | + cpu->id_isar5 = 0x00000000; | ||
45 | + cpu->clidr = 0x00000000; | ||
46 | + cpu->ctr = 0x8000c000; | ||
47 | +} | ||
48 | + | ||
49 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
50 | { | 30 | { |
51 | CPUClass *cc = CPU_CLASS(oc); | 31 | ARMCPU *cpu = ARM_CPU(obj); |
32 | - /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an | ||
33 | + /* | ||
34 | + * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an | ||
35 | * older core than plain "arm1136". In particular this does not | ||
36 | * have the v6K features. | ||
37 | * These ID register values are correct for 1136 but may be wrong | ||
52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | 38 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { |
53 | .class_init = arm_v7m_class_init }, | 39 | { .name = "arm926", .initfn = arm926_initfn }, |
54 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, | 40 | { .name = "arm946", .initfn = arm946_initfn }, |
55 | .class_init = arm_v7m_class_init }, | 41 | { .name = "arm1026", .initfn = arm1026_initfn }, |
56 | + { .name = "cortex-m33", .initfn = cortex_m33_initfn, | 42 | - /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an |
57 | + .class_init = arm_v7m_class_init }, | 43 | + /* |
58 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | 44 | + * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an |
59 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, | 45 | * older core than plain "arm1136". In particular this does not |
60 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | 46 | * have the v6K features. |
47 | */ | ||
61 | -- | 48 | -- |
62 | 2.16.2 | 49 | 2.20.1 |
63 | 50 | ||
64 | 51 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Happily, the bits are in the same places compared to a32. | 3 | Allow name wildcards in qemu_fdt_node_path(). This is useful |
4 | to find all nodes with a given compatibility string. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
6 | Message-id: 20180228193125.20577-16-richard.henderson@linaro.org | 7 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Message-id: 20200423121114.4274-2-edgar.iglesias@gmail.com |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/translate.c | 14 +++++++++++++- | 11 | include/sysemu/device_tree.h | 3 +++ |
11 | 1 file changed, 13 insertions(+), 1 deletion(-) | 12 | device_tree.c | 2 +- |
13 | 2 files changed, 4 insertions(+), 1 deletion(-) | ||
12 | 14 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 15 | diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 17 | --- a/include/sysemu/device_tree.h |
16 | +++ b/target/arm/translate.c | 18 | +++ b/include/sysemu/device_tree.h |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ void *load_device_tree_from_sysfs(void); |
18 | default_exception_el(s)); | 20 | * NULL. If there is no error but no matching node was found, the |
21 | * returned array contains a single element equal to NULL. If an error | ||
22 | * was encountered when parsing the blob, the function returns NULL | ||
23 | + * | ||
24 | + * @name may be NULL to wildcard names and only match compatibility | ||
25 | + * strings. | ||
26 | */ | ||
27 | char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, | ||
28 | Error **errp); | ||
29 | diff --git a/device_tree.c b/device_tree.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/device_tree.c | ||
32 | +++ b/device_tree.c | ||
33 | @@ -XXX,XX +XXX,XX @@ char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, | ||
34 | offset = len; | ||
19 | break; | 35 | break; |
20 | } | 36 | } |
21 | - if (((insn >> 24) & 3) == 3) { | 37 | - if (!strcmp(iter_name, name)) { |
22 | + if ((insn & 0xfe000a00) == 0xfc000800 | 38 | + if (!name || !strcmp(iter_name, name)) { |
23 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 39 | char *path; |
24 | + /* The Thumb2 and ARM encodings are identical. */ | 40 | |
25 | + if (disas_neon_insn_3same_ext(s, insn)) { | 41 | path = g_malloc(path_len); |
26 | + goto illegal_op; | ||
27 | + } | ||
28 | + } else if ((insn & 0xff000a00) == 0xfe000800 | ||
29 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
30 | + /* The Thumb2 and ARM encodings are identical. */ | ||
31 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
32 | + goto illegal_op; | ||
33 | + } | ||
34 | + } else if (((insn >> 24) & 3) == 3) { | ||
35 | /* Translate into the equivalent ARM encoding. */ | ||
36 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | ||
37 | if (disas_neon_data_insn(s, insn)) { | ||
38 | -- | 42 | -- |
39 | 2.16.2 | 43 | 2.20.1 |
40 | 44 | ||
41 | 45 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@xilinx.com> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Allow the guest to determine the time set from the QEMU command line. | 3 | Make compat in qemu_fdt_node_path() const char *. |
4 | 4 | ||
5 | This includes adding a trace event to debug the new time. | 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
6 | 6 | Message-id: 20200423121114.4274-3-edgar.iglesias@gmail.com | |
7 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 9 | --- |
12 | include/hw/timer/xlnx-zynqmp-rtc.h | 2 ++ | 10 | include/sysemu/device_tree.h | 2 +- |
13 | hw/timer/xlnx-zynqmp-rtc.c | 58 ++++++++++++++++++++++++++++++++++++++ | 11 | device_tree.c | 2 +- |
14 | hw/timer/trace-events | 3 ++ | 12 | 2 files changed, 2 insertions(+), 2 deletions(-) |
15 | 3 files changed, 63 insertions(+) | ||
16 | 13 | ||
17 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | 14 | diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/timer/xlnx-zynqmp-rtc.h | 16 | --- a/include/sysemu/device_tree.h |
20 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | 17 | +++ b/include/sysemu/device_tree.h |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPRTC { | 18 | @@ -XXX,XX +XXX,XX @@ void *load_device_tree_from_sysfs(void); |
22 | qemu_irq irq_rtc_int; | 19 | * @name may be NULL to wildcard names and only match compatibility |
23 | qemu_irq irq_addr_error_int; | 20 | * strings. |
24 | 21 | */ | |
25 | + uint32_t tick_offset; | 22 | -char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, |
26 | + | 23 | +char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat, |
27 | uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | 24 | Error **errp); |
28 | RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | 25 | |
29 | } XlnxZynqMPRTC; | 26 | /** |
30 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | 27 | diff --git a/device_tree.c b/device_tree.c |
31 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/timer/xlnx-zynqmp-rtc.c | 29 | --- a/device_tree.c |
33 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | 30 | +++ b/device_tree.c |
34 | @@ -XXX,XX +XXX,XX @@ | 31 | @@ -XXX,XX +XXX,XX @@ char **qemu_fdt_node_unit_path(void *fdt, const char *name, Error **errp) |
35 | #include "hw/register.h" | 32 | return path_array; |
36 | #include "qemu/bitops.h" | ||
37 | #include "qemu/log.h" | ||
38 | +#include "hw/ptimer.h" | ||
39 | +#include "qemu/cutils.h" | ||
40 | +#include "sysemu/sysemu.h" | ||
41 | +#include "trace.h" | ||
42 | #include "hw/timer/xlnx-zynqmp-rtc.h" | ||
43 | |||
44 | #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
45 | @@ -XXX,XX +XXX,XX @@ static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
46 | qemu_set_irq(s->irq_addr_error_int, pending); | ||
47 | } | 33 | } |
48 | 34 | ||
49 | +static uint32_t rtc_get_count(XlnxZynqMPRTC *s) | 35 | -char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, |
50 | +{ | 36 | +char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat, |
51 | + int64_t now = qemu_clock_get_ns(rtc_clock); | 37 | Error **errp) |
52 | + return s->tick_offset + now / NANOSECONDS_PER_SECOND; | ||
53 | +} | ||
54 | + | ||
55 | +static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64) | ||
56 | +{ | ||
57 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
58 | + | ||
59 | + return rtc_get_count(s); | ||
60 | +} | ||
61 | + | ||
62 | static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
63 | { | 38 | { |
64 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | 39 | int offset, len, ret; |
65 | @@ -XXX,XX +XXX,XX @@ static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
66 | |||
67 | static const RegisterAccessInfo rtc_regs_info[] = { | ||
68 | { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
69 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
70 | },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
71 | .ro = 0xffffffff, | ||
72 | + .post_read = current_time_postr, | ||
73 | },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
74 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
75 | },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
76 | .ro = 0x1fffff, | ||
77 | },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
78 | .ro = 0xffffffff, | ||
79 | + .post_read = current_time_postr, | ||
80 | },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
81 | .ro = 0xffff, | ||
82 | },{ .name = "ALARM", .addr = A_ALARM, | ||
83 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
84 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
85 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
86 | RegisterInfoArray *reg_array; | ||
87 | + struct tm current_tm; | ||
88 | |||
89 | memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
90 | XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
91 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
92 | sysbus_init_mmio(sbd, &s->iomem); | ||
93 | sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
94 | sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
95 | + | ||
96 | + qemu_get_timedate(¤t_tm, 0); | ||
97 | + s->tick_offset = mktimegm(¤t_tm) - | ||
98 | + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
99 | + | ||
100 | + trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon, | ||
101 | + current_tm.tm_mday, current_tm.tm_hour, | ||
102 | + current_tm.tm_min, current_tm.tm_sec); | ||
103 | +} | ||
104 | + | ||
105 | +static int rtc_pre_save(void *opaque) | ||
106 | +{ | ||
107 | + XlnxZynqMPRTC *s = opaque; | ||
108 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
109 | + | ||
110 | + /* Add the time at migration */ | ||
111 | + s->tick_offset = s->tick_offset + now; | ||
112 | + | ||
113 | + return 0; | ||
114 | +} | ||
115 | + | ||
116 | +static int rtc_post_load(void *opaque, int version_id) | ||
117 | +{ | ||
118 | + XlnxZynqMPRTC *s = opaque; | ||
119 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
120 | + | ||
121 | + /* Subtract the time after migration. This combined with the pre_save | ||
122 | + * action results in us having subtracted the time that the guest was | ||
123 | + * stopped to the offset. | ||
124 | + */ | ||
125 | + s->tick_offset = s->tick_offset - now; | ||
126 | + | ||
127 | + return 0; | ||
128 | } | ||
129 | |||
130 | static const VMStateDescription vmstate_rtc = { | ||
131 | .name = TYPE_XLNX_ZYNQMP_RTC, | ||
132 | .version_id = 1, | ||
133 | .minimum_version_id = 1, | ||
134 | + .pre_save = rtc_pre_save, | ||
135 | + .post_load = rtc_post_load, | ||
136 | .fields = (VMStateField[]) { | ||
137 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
138 | + VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC), | ||
139 | VMSTATE_END_OF_LIST(), | ||
140 | } | ||
141 | }; | ||
142 | diff --git a/hw/timer/trace-events b/hw/timer/trace-events | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/hw/timer/trace-events | ||
145 | +++ b/hw/timer/trace-events | ||
146 | @@ -XXX,XX +XXX,XX @@ systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr | ||
147 | cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
148 | cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
149 | cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" | ||
150 | + | ||
151 | +# hw/timer/xlnx-zynqmp-rtc.c | ||
152 | +xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" | ||
153 | -- | 40 | -- |
154 | 2.16.2 | 41 | 2.20.1 |
155 | 42 | ||
156 | 43 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add a function load_ramdisk_as() which behaves like the existing | ||
2 | load_ramdisk() but allows the caller to specify the AddressSpace | ||
3 | to use. This matches the pattern we have already for various | ||
4 | other loader functions. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/hw/loader.h | 12 +++++++++++- | ||
12 | hw/core/loader.c | 8 +++++++- | ||
13 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/loader.h b/include/hw/loader.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/loader.h | ||
18 | +++ b/include/hw/loader.h | ||
19 | @@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep, | ||
20 | void *translate_opaque); | ||
21 | |||
22 | /** | ||
23 | - * load_ramdisk: | ||
24 | + * load_ramdisk_as: | ||
25 | * @filename: Path to the ramdisk image | ||
26 | * @addr: Memory address to load the ramdisk to | ||
27 | * @max_sz: Maximum allowed ramdisk size (for non-u-boot ramdisks) | ||
28 | + * @as: The AddressSpace to load the ELF to. The value of address_space_memory | ||
29 | + * is used if nothing is supplied here. | ||
30 | * | ||
31 | * Load a ramdisk image with U-Boot header to the specified memory | ||
32 | * address. | ||
33 | * | ||
34 | * Returns the size of the loaded image on success, -1 otherwise. | ||
35 | */ | ||
36 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
37 | + AddressSpace *as); | ||
38 | + | ||
39 | +/** | ||
40 | + * load_ramdisk: | ||
41 | + * Same as load_ramdisk_as(), but doesn't allow the caller to specify | ||
42 | + * an AddressSpace. | ||
43 | + */ | ||
44 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz); | ||
45 | |||
46 | ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen); | ||
47 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/core/loader.c | ||
50 | +++ b/hw/core/loader.c | ||
51 | @@ -XXX,XX +XXX,XX @@ int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr, | ||
52 | |||
53 | /* Load a ramdisk. */ | ||
54 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz) | ||
55 | +{ | ||
56 | + return load_ramdisk_as(filename, addr, max_sz, NULL); | ||
57 | +} | ||
58 | + | ||
59 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
60 | + AddressSpace *as) | ||
61 | { | ||
62 | return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK, | ||
63 | - NULL, NULL, NULL); | ||
64 | + NULL, NULL, as); | ||
65 | } | ||
66 | |||
67 | /* Load a gzip-compressed kernel to a dynamically allocated buffer. */ | ||
68 | -- | ||
69 | 2.16.2 | ||
70 | |||
71 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Instead of loading guest images to the system address space, use the | ||
2 | CPU's address space. This is important if we're trying to load the | ||
3 | file to memory or via an alias memory region that is provided by an | ||
4 | SoC object and thus not mapped into the system address space. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/arm/armv7m.c | 17 ++++++++++++++--- | ||
12 | 1 file changed, 14 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/armv7m.c | ||
17 | +++ b/hw/arm/armv7m.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
19 | uint64_t entry; | ||
20 | uint64_t lowaddr; | ||
21 | int big_endian; | ||
22 | + AddressSpace *as; | ||
23 | + int asidx; | ||
24 | + CPUState *cs = CPU(cpu); | ||
25 | |||
26 | #ifdef TARGET_WORDS_BIGENDIAN | ||
27 | big_endian = 1; | ||
28 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
29 | exit(1); | ||
30 | } | ||
31 | |||
32 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | ||
33 | + asidx = ARMASIdx_S; | ||
34 | + } else { | ||
35 | + asidx = ARMASIdx_NS; | ||
36 | + } | ||
37 | + as = cpu_get_address_space(cs, asidx); | ||
38 | + | ||
39 | if (kernel_filename) { | ||
40 | - image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
41 | - NULL, big_endian, EM_ARM, 1, 0); | ||
42 | + image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
43 | + NULL, big_endian, EM_ARM, 1, 0, as); | ||
44 | if (image_size < 0) { | ||
45 | - image_size = load_image_targphys(kernel_filename, 0, mem_size); | ||
46 | + image_size = load_image_targphys_as(kernel_filename, 0, | ||
47 | + mem_size, as); | ||
48 | lowaddr = 0; | ||
49 | } | ||
50 | if (image_size < 0) { | ||
51 | -- | ||
52 | 2.16.2 | ||
53 | |||
54 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The Cortex-M33 allows the system to specify the reset value of the | ||
2 | secure Vector Table Offset Register (VTOR) by asserting config | ||
3 | signals. In particular, guest images for the MPS2 AN505 board rely | ||
4 | on the MPS2's initial VTOR being correct for that board. | ||
5 | Implement a QEMU property so board and SoC code can set the reset | ||
6 | value to the correct value. | ||
7 | 1 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-7-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/cpu.h | 3 +++ | ||
13 | target/arm/cpu.c | 18 ++++++++++++++---- | ||
14 | 2 files changed, 17 insertions(+), 4 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu.h | ||
19 | +++ b/target/arm/cpu.h | ||
20 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
21 | */ | ||
22 | uint32_t psci_conduit; | ||
23 | |||
24 | + /* For v8M, initial value of the Secure VTOR */ | ||
25 | + uint32_t init_svtor; | ||
26 | + | ||
27 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or | ||
28 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | ||
29 | */ | ||
30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/cpu.c | ||
33 | +++ b/target/arm/cpu.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
35 | uint32_t initial_msp; /* Loaded from 0x0 */ | ||
36 | uint32_t initial_pc; /* Loaded from 0x4 */ | ||
37 | uint8_t *rom; | ||
38 | + uint32_t vecbase; | ||
39 | |||
40 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
41 | env->v7m.secure = true; | ||
42 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
43 | /* Unlike A/R profile, M profile defines the reset LR value */ | ||
44 | env->regs[14] = 0xffffffff; | ||
45 | |||
46 | - /* Load the initial SP and PC from the vector table at address 0 */ | ||
47 | - rom = rom_ptr(0); | ||
48 | + env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; | ||
49 | + | ||
50 | + /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | ||
51 | + vecbase = env->v7m.vecbase[env->v7m.secure]; | ||
52 | + rom = rom_ptr(vecbase); | ||
53 | if (rom) { | ||
54 | /* Address zero is covered by ROM which hasn't yet been | ||
55 | * copied into physical memory. | ||
56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
57 | * it got copied into memory. In the latter case, rom_ptr | ||
58 | * will return a NULL pointer and we should use ldl_phys instead. | ||
59 | */ | ||
60 | - initial_msp = ldl_phys(s->as, 0); | ||
61 | - initial_pc = ldl_phys(s->as, 4); | ||
62 | + initial_msp = ldl_phys(s->as, vecbase); | ||
63 | + initial_pc = ldl_phys(s->as, vecbase + 4); | ||
64 | } | ||
65 | |||
66 | env->regs[13] = initial_msp & 0xFFFFFFFC; | ||
67 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property = | ||
68 | pmsav7_dregion, | ||
69 | qdev_prop_uint32, uint32_t); | ||
70 | |||
71 | +/* M profile: initial value of the Secure VTOR */ | ||
72 | +static Property arm_cpu_initsvtor_property = | ||
73 | + DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | ||
74 | + | ||
75 | static void arm_cpu_post_init(Object *obj) | ||
76 | { | ||
77 | ARMCPU *cpu = ARM_CPU(obj); | ||
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | ||
79 | qdev_prop_allow_set_link_before_realize, | ||
80 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
81 | &error_abort); | ||
82 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, | ||
83 | + &error_abort); | ||
84 | } | ||
85 | |||
86 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
87 | -- | ||
88 | 2.16.2 | ||
89 | |||
90 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the definition of the struct for the unimplemented-device | ||
2 | from unimp.c to unimp.h, so that users can embed the struct | ||
3 | in their own device structs if they prefer. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-10-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/misc/unimp.h | 10 ++++++++++ | ||
11 | hw/misc/unimp.c | 10 ---------- | ||
12 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/misc/unimp.h | ||
17 | +++ b/include/hw/misc/unimp.h | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" | ||
21 | |||
22 | +#define UNIMPLEMENTED_DEVICE(obj) \ | ||
23 | + OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
24 | + | ||
25 | +typedef struct { | ||
26 | + SysBusDevice parent_obj; | ||
27 | + MemoryRegion iomem; | ||
28 | + char *name; | ||
29 | + uint64_t size; | ||
30 | +} UnimplementedDeviceState; | ||
31 | + | ||
32 | /** | ||
33 | * create_unimplemented_device: create and map a dummy device | ||
34 | * @name: name of the device for debug logging | ||
35 | diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/misc/unimp.c | ||
38 | +++ b/hw/misc/unimp.c | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | #include "qemu/log.h" | ||
41 | #include "qapi/error.h" | ||
42 | |||
43 | -#define UNIMPLEMENTED_DEVICE(obj) \ | ||
44 | - OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
45 | - | ||
46 | -typedef struct { | ||
47 | - SysBusDevice parent_obj; | ||
48 | - MemoryRegion iomem; | ||
49 | - char *name; | ||
50 | - uint64_t size; | ||
51 | -} UnimplementedDeviceState; | ||
52 | - | ||
53 | static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size) | ||
54 | { | ||
55 | UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
56 | -- | ||
57 | 2.16.2 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The or-irq.h header file is missing the customary guard against | ||
2 | multiple inclusion, which means compilation fails if it gets | ||
3 | included twice. Fix the omission. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-11-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/or-irq.h | 5 +++++ | ||
11 | 1 file changed, 5 insertions(+) | ||
12 | |||
13 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/or-irq.h | ||
16 | +++ b/include/hw/or-irq.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * THE SOFTWARE. | ||
19 | */ | ||
20 | |||
21 | +#ifndef HW_OR_IRQ_H | ||
22 | +#define HW_OR_IRQ_H | ||
23 | + | ||
24 | #include "hw/irq.h" | ||
25 | #include "hw/sysbus.h" | ||
26 | #include "qom/object.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct OrIRQState { | ||
28 | bool levels[MAX_OR_LINES]; | ||
29 | uint16_t num_lines; | ||
30 | }; | ||
31 | + | ||
32 | +#endif | ||
33 | -- | ||
34 | 2.16.2 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The function qdev_init_gpio_in_named() passes the DeviceState pointer | ||
2 | as the opaque data pointor for the irq handler function. Usually | ||
3 | this is what you want, but in some cases it would be helpful to use | ||
4 | some other data pointer. | ||
5 | 1 | ||
6 | Add a new function qdev_init_gpio_in_named_with_opaque() which allows | ||
7 | the caller to specify the data pointer they want. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180220180325.29818-12-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/hw/qdev-core.h | 30 ++++++++++++++++++++++++++++-- | ||
15 | hw/core/qdev.c | 8 +++++--- | ||
16 | 2 files changed, 33 insertions(+), 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/qdev-core.h | ||
21 | +++ b/include/hw/qdev-core.h | ||
22 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
23 | /* GPIO inputs also double as IRQ sinks. */ | ||
24 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
25 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
26 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
27 | - const char *name, int n); | ||
28 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
29 | const char *name, int n); | ||
30 | +/** | ||
31 | + * qdev_init_gpio_in_named_with_opaque: create an array of input GPIO lines | ||
32 | + * for the specified device | ||
33 | + * | ||
34 | + * @dev: Device to create input GPIOs for | ||
35 | + * @handler: Function to call when GPIO line value is set | ||
36 | + * @opaque: Opaque data pointer to pass to @handler | ||
37 | + * @name: Name of the GPIO input (must be unique for this device) | ||
38 | + * @n: Number of GPIO lines in this input set | ||
39 | + */ | ||
40 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
41 | + qemu_irq_handler handler, | ||
42 | + void *opaque, | ||
43 | + const char *name, int n); | ||
44 | + | ||
45 | +/** | ||
46 | + * qdev_init_gpio_in_named: create an array of input GPIO lines | ||
47 | + * for the specified device | ||
48 | + * | ||
49 | + * Like qdev_init_gpio_in_named_with_opaque(), but the opaque pointer | ||
50 | + * passed to the handler is @dev (which is the most commonly desired behaviour). | ||
51 | + */ | ||
52 | +static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
53 | + qemu_irq_handler handler, | ||
54 | + const char *name, int n) | ||
55 | +{ | ||
56 | + qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
57 | +} | ||
58 | |||
59 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
60 | const char *name); | ||
61 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/core/qdev.c | ||
64 | +++ b/hw/core/qdev.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, | ||
66 | return ngl; | ||
67 | } | ||
68 | |||
69 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
70 | - const char *name, int n) | ||
71 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
72 | + qemu_irq_handler handler, | ||
73 | + void *opaque, | ||
74 | + const char *name, int n) | ||
75 | { | ||
76 | int i; | ||
77 | NamedGPIOList *gpio_list = qdev_get_named_gpio_list(dev, name); | ||
78 | |||
79 | assert(gpio_list->num_out == 0 || !name); | ||
80 | gpio_list->in = qemu_extend_irqs(gpio_list->in, gpio_list->num_in, handler, | ||
81 | - dev, n); | ||
82 | + opaque, n); | ||
83 | |||
84 | if (!name) { | ||
85 | name = "unnamed-gpio-in"; | ||
86 | -- | ||
87 | 2.16.2 | ||
88 | |||
89 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | |||
3 | Move arm_boot_info into XlnxZCU102. | ||
2 | 4 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
5 | Message-id: 20180228193125.20577-9-richard.henderson@linaro.org | 7 | Message-id: 20200423121114.4274-4-edgar.iglesias@gmail.com |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- | 10 | hw/arm/xlnx-zcu102.c | 9 +++++---- |
9 | 1 file changed, 42 insertions(+), 4 deletions(-) | 11 | 1 file changed, 5 insertions(+), 4 deletions(-) |
10 | 12 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 15 | --- a/hw/arm/xlnx-zcu102.c |
14 | +++ b/target/arm/translate.c | 16 | +++ b/hw/arm/xlnx-zcu102.c |
15 | @@ -XXX,XX +XXX,XX @@ static const char *regnames[] = | 17 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 { |
16 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | 18 | |
17 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | 19 | bool secure; |
18 | 20 | bool virt; | |
19 | +/* Function prototypes for gen_ functions calling Neon helpers. */ | ||
20 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
21 | + TCGv_i32, TCGv_i32); | ||
22 | + | 21 | + |
23 | /* initialize TCG globals. */ | 22 | + struct arm_boot_info binfo; |
24 | void arm_translate_init(void) | 23 | } XlnxZCU102; |
24 | |||
25 | #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") | ||
26 | #define ZCU102_MACHINE(obj) \ | ||
27 | OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) | ||
28 | |||
29 | -static struct arm_boot_info xlnx_zcu102_binfo; | ||
30 | |||
31 | static bool zcu102_get_secure(Object *obj, Error **errp) | ||
25 | { | 32 | { |
26 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 33 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) |
27 | } | 34 | |
28 | neon_store_reg64(cpu_V0, rd + pass); | 35 | /* TODO create and connect IDE devices for ide_drive_get() */ |
29 | } | 36 | |
30 | - | 37 | - xlnx_zcu102_binfo.ram_size = ram_size; |
31 | - | 38 | - xlnx_zcu102_binfo.loader_start = 0; |
32 | break; | 39 | - arm_load_kernel(s->soc.boot_cpu_ptr, machine, &xlnx_zcu102_binfo); |
33 | - default: /* 14 and 15 are RESERVED */ | 40 | + s->binfo.ram_size = ram_size; |
34 | - return 1; | 41 | + s->binfo.loader_start = 0; |
35 | + case 14: /* VQRDMLAH scalar */ | 42 | + arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); |
36 | + case 15: /* VQRDMLSH scalar */ | 43 | } |
37 | + { | 44 | |
38 | + NeonGenThreeOpEnvFn *fn; | 45 | static void xlnx_zcu102_machine_instance_init(Object *obj) |
39 | + | ||
40 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
41 | + return 1; | ||
42 | + } | ||
43 | + if (u && ((rd | rn) & 1)) { | ||
44 | + return 1; | ||
45 | + } | ||
46 | + if (op == 14) { | ||
47 | + if (size == 1) { | ||
48 | + fn = gen_helper_neon_qrdmlah_s16; | ||
49 | + } else { | ||
50 | + fn = gen_helper_neon_qrdmlah_s32; | ||
51 | + } | ||
52 | + } else { | ||
53 | + if (size == 1) { | ||
54 | + fn = gen_helper_neon_qrdmlsh_s16; | ||
55 | + } else { | ||
56 | + fn = gen_helper_neon_qrdmlsh_s32; | ||
57 | + } | ||
58 | + } | ||
59 | + | ||
60 | + tmp2 = neon_get_scalar(size, rm); | ||
61 | + for (pass = 0; pass < (u ? 4 : 2); pass++) { | ||
62 | + tmp = neon_load_reg(rn, pass); | ||
63 | + tmp3 = neon_load_reg(rd, pass); | ||
64 | + fn(tmp, cpu_env, tmp, tmp2, tmp3); | ||
65 | + tcg_temp_free_i32(tmp3); | ||
66 | + neon_store_reg(rd, pass, tmp); | ||
67 | + } | ||
68 | + tcg_temp_free_i32(tmp2); | ||
69 | + } | ||
70 | + break; | ||
71 | + default: | ||
72 | + g_assert_not_reached(); | ||
73 | } | ||
74 | } | ||
75 | } else { /* size == 3 */ | ||
76 | -- | 46 | -- |
77 | 2.16.2 | 47 | 2.20.1 |
78 | 48 | ||
79 | 49 | diff view generated by jsdifflib |
1 | The IoTKit Security Controller includes various registers | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | that expose to software the controls for the Peripheral | ||
3 | Protection Controllers in the system. Implement these. | ||
4 | 2 | ||
3 | Disable unsupported FDT firmware nodes if a user passes us | ||
4 | a DTB with nodes enabled that the machine cannot support | ||
5 | due to lack of EL3 or EL2 support. | ||
6 | |||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
9 | Message-id: 20200423121114.4274-5-edgar.iglesias@gmail.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-17-peter.maydell@linaro.org | ||
8 | --- | 11 | --- |
9 | include/hw/misc/iotkit-secctl.h | 64 +++++++++- | 12 | hw/arm/xlnx-zcu102.c | 30 ++++++++++++++++++++++++++++++ |
10 | hw/misc/iotkit-secctl.c | 270 +++++++++++++++++++++++++++++++++++++--- | 13 | 1 file changed, 30 insertions(+) |
11 | 2 files changed, 315 insertions(+), 19 deletions(-) | ||
12 | 14 | ||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 15 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/misc/iotkit-secctl.h | 17 | --- a/hw/arm/xlnx-zcu102.c |
16 | +++ b/include/hw/misc/iotkit-secctl.h | 18 | +++ b/hw/arm/xlnx-zcu102.c |
17 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
18 | * QEMU interface: | 20 | #include "qemu/error-report.h" |
19 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | 21 | #include "qemu/log.h" |
20 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 22 | #include "sysemu/qtest.h" |
21 | + * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | 23 | +#include "sysemu/device_tree.h" |
22 | + * should RAZ/WI or bus error | 24 | |
23 | + * Controlling the 2 APB PPCs in the IoTKit: | 25 | typedef struct XlnxZCU102 { |
24 | + * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | 26 | MachineState parent_obj; |
25 | + * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | 27 | @@ -XXX,XX +XXX,XX @@ static void zcu102_set_virt(Object *obj, bool value, Error **errp) |
26 | + * + named GPIO outputs apb_ppc{0,1}_irq_enable | 28 | s->virt = value; |
27 | + * + named GPIO outputs apb_ppc{0,1}_irq_clear | 29 | } |
28 | + * + named GPIO inputs apb_ppc{0,1}_irq_status | 30 | |
29 | + * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit | 31 | +static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt) |
30 | + * might provide: | ||
31 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
32 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
33 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
34 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
35 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
36 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
37 | + * might provide: | ||
38 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
39 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
40 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
41 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
42 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
43 | */ | ||
44 | |||
45 | #ifndef IOTKIT_SECCTL_H | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
48 | #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
49 | |||
50 | -typedef struct IoTKitSecCtl { | ||
51 | +#define IOTS_APB_PPC0_NUM_PORTS 3 | ||
52 | +#define IOTS_APB_PPC1_NUM_PORTS 1 | ||
53 | +#define IOTS_PPC_NUM_PORTS 16 | ||
54 | +#define IOTS_NUM_APB_PPC 2 | ||
55 | +#define IOTS_NUM_APB_EXP_PPC 4 | ||
56 | +#define IOTS_NUM_AHB_EXP_PPC 4 | ||
57 | + | ||
58 | +typedef struct IoTKitSecCtl IoTKitSecCtl; | ||
59 | + | ||
60 | +/* State and IRQ lines relating to a PPC. For the | ||
61 | + * PPCs in the IoTKit not all the IRQ lines are used. | ||
62 | + */ | ||
63 | +typedef struct IoTKitSecCtlPPC { | ||
64 | + qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; | ||
65 | + qemu_irq ap[IOTS_PPC_NUM_PORTS]; | ||
66 | + qemu_irq irq_enable; | ||
67 | + qemu_irq irq_clear; | ||
68 | + | ||
69 | + uint32_t ns; | ||
70 | + uint32_t sp; | ||
71 | + uint32_t nsp; | ||
72 | + | ||
73 | + /* Number of ports actually present */ | ||
74 | + int numports; | ||
75 | + /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ | ||
76 | + int irq_bit_offset; | ||
77 | + IoTKitSecCtl *parent; | ||
78 | +} IoTKitSecCtlPPC; | ||
79 | + | ||
80 | +struct IoTKitSecCtl { | ||
81 | /*< private >*/ | ||
82 | SysBusDevice parent_obj; | ||
83 | |||
84 | /*< public >*/ | ||
85 | + qemu_irq sec_resp_cfg; | ||
86 | |||
87 | MemoryRegion s_regs; | ||
88 | MemoryRegion ns_regs; | ||
89 | -} IoTKitSecCtl; | ||
90 | + | ||
91 | + uint32_t secppcintstat; | ||
92 | + uint32_t secppcinten; | ||
93 | + uint32_t secrespcfg; | ||
94 | + | ||
95 | + IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
96 | + IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
97 | + IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; | ||
98 | +}; | ||
99 | |||
100 | #endif | ||
101 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/hw/misc/iotkit-secctl.c | ||
104 | +++ b/hw/misc/iotkit-secctl.c | ||
105 | @@ -XXX,XX +XXX,XX @@ static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
106 | 0x0d, 0xf0, 0x05, 0xb1, | ||
107 | }; | ||
108 | |||
109 | +/* The register sets for the various PPCs (AHB internal, APB internal, | ||
110 | + * AHB expansion, APB expansion) are all set up so that they are | ||
111 | + * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs | ||
112 | + * 0, 1, 2, 3 of that type, so we can convert a register address offset | ||
113 | + * into an an index into a PPC array easily. | ||
114 | + */ | ||
115 | +static inline int offset_to_ppc_idx(uint32_t offset) | ||
116 | +{ | 32 | +{ |
117 | + return extract32(offset, 2, 2); | 33 | + XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo); |
118 | +} | 34 | + bool method_is_hvc; |
119 | + | 35 | + char **node_path; |
120 | +typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc); | 36 | + const char *r; |
121 | + | 37 | + int prop_len; |
122 | +static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn) | ||
123 | +{ | ||
124 | + int i; | 38 | + int i; |
125 | + | 39 | + |
126 | + for (i = 0; i < IOTS_NUM_APB_PPC; i++) { | 40 | + /* If EL3 is enabled, we keep all firmware nodes active. */ |
127 | + fn(&s->apb[i]); | 41 | + if (!s->secure) { |
128 | + } | 42 | + node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware", |
129 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | 43 | + &error_fatal); |
130 | + fn(&s->apbexp[i]); | 44 | + |
131 | + } | 45 | + for (i = 0; node_path && node_path[i]; i++) { |
132 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | 46 | + r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL); |
133 | + fn(&s->ahbexp[i]); | 47 | + method_is_hvc = r && !strcmp("hvc", r); |
48 | + | ||
49 | + /* Allow HVC based firmware if EL2 is enabled. */ | ||
50 | + if (method_is_hvc && s->virt) { | ||
51 | + continue; | ||
52 | + } | ||
53 | + qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled"); | ||
54 | + } | ||
55 | + g_strfreev(node_path); | ||
134 | + } | 56 | + } |
135 | +} | 57 | +} |
136 | + | 58 | + |
137 | static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | 59 | static void xlnx_zcu102_init(MachineState *machine) |
138 | uint64_t *pdata, | ||
139 | unsigned size, MemTxAttrs attrs) | ||
140 | { | 60 | { |
141 | uint64_t r; | 61 | XlnxZCU102 *s = ZCU102_MACHINE(machine); |
142 | uint32_t offset = addr & ~0x3; | 62 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) |
143 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | 63 | |
144 | 64 | s->binfo.ram_size = ram_size; | |
145 | switch (offset) { | 65 | s->binfo.loader_start = 0; |
146 | case A_AHBNSPPC0: | 66 | + s->binfo.modify_dtb = zcu102_modify_dtb; |
147 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | 67 | arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); |
148 | r = 0; | ||
149 | break; | ||
150 | case A_SECRESPCFG: | ||
151 | - case A_NSCCFG: | ||
152 | - case A_SECMPCINTSTATUS: | ||
153 | + r = s->secrespcfg; | ||
154 | + break; | ||
155 | case A_SECPPCINTSTAT: | ||
156 | + r = s->secppcintstat; | ||
157 | + break; | ||
158 | case A_SECPPCINTEN: | ||
159 | - case A_SECMSCINTSTAT: | ||
160 | - case A_SECMSCINTEN: | ||
161 | - case A_BRGINTSTAT: | ||
162 | - case A_BRGINTEN: | ||
163 | + r = s->secppcinten; | ||
164 | + break; | ||
165 | case A_AHBNSPPCEXP0: | ||
166 | case A_AHBNSPPCEXP1: | ||
167 | case A_AHBNSPPCEXP2: | ||
168 | case A_AHBNSPPCEXP3: | ||
169 | + r = s->ahbexp[offset_to_ppc_idx(offset)].ns; | ||
170 | + break; | ||
171 | case A_APBNSPPC0: | ||
172 | case A_APBNSPPC1: | ||
173 | + r = s->apb[offset_to_ppc_idx(offset)].ns; | ||
174 | + break; | ||
175 | case A_APBNSPPCEXP0: | ||
176 | case A_APBNSPPCEXP1: | ||
177 | case A_APBNSPPCEXP2: | ||
178 | case A_APBNSPPCEXP3: | ||
179 | + r = s->apbexp[offset_to_ppc_idx(offset)].ns; | ||
180 | + break; | ||
181 | case A_AHBSPPPCEXP0: | ||
182 | case A_AHBSPPPCEXP1: | ||
183 | case A_AHBSPPPCEXP2: | ||
184 | case A_AHBSPPPCEXP3: | ||
185 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
186 | + break; | ||
187 | case A_APBSPPPC0: | ||
188 | case A_APBSPPPC1: | ||
189 | + r = s->apb[offset_to_ppc_idx(offset)].sp; | ||
190 | + break; | ||
191 | case A_APBSPPPCEXP0: | ||
192 | case A_APBSPPPCEXP1: | ||
193 | case A_APBSPPPCEXP2: | ||
194 | case A_APBSPPPCEXP3: | ||
195 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
196 | + break; | ||
197 | + case A_NSCCFG: | ||
198 | + case A_SECMPCINTSTATUS: | ||
199 | + case A_SECMSCINTSTAT: | ||
200 | + case A_SECMSCINTEN: | ||
201 | + case A_BRGINTSTAT: | ||
202 | + case A_BRGINTEN: | ||
203 | case A_NSMSCEXP: | ||
204 | qemu_log_mask(LOG_UNIMP, | ||
205 | "IoTKit SecCtl S block read: " | ||
206 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
207 | return MEMTX_OK; | ||
208 | } | 68 | } |
209 | 69 | ||
210 | +static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc) | ||
211 | +{ | ||
212 | + int i; | ||
213 | + | ||
214 | + for (i = 0; i < ppc->numports; i++) { | ||
215 | + bool v; | ||
216 | + | ||
217 | + if (extract32(ppc->ns, i, 1)) { | ||
218 | + v = extract32(ppc->nsp, i, 1); | ||
219 | + } else { | ||
220 | + v = extract32(ppc->sp, i, 1); | ||
221 | + } | ||
222 | + qemu_set_irq(ppc->ap[i], v); | ||
223 | + } | ||
224 | +} | ||
225 | + | ||
226 | +static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
227 | +{ | ||
228 | + int i; | ||
229 | + | ||
230 | + ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
231 | + for (i = 0; i < ppc->numports; i++) { | ||
232 | + qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); | ||
233 | + } | ||
234 | + iotkit_secctl_update_ppc_ap(ppc); | ||
235 | +} | ||
236 | + | ||
237 | +static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
238 | +{ | ||
239 | + ppc->sp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
240 | + iotkit_secctl_update_ppc_ap(ppc); | ||
241 | +} | ||
242 | + | ||
243 | +static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
244 | +{ | ||
245 | + ppc->nsp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
246 | + iotkit_secctl_update_ppc_ap(ppc); | ||
247 | +} | ||
248 | + | ||
249 | +static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc) | ||
250 | +{ | ||
251 | + uint32_t value = ppc->parent->secppcintstat; | ||
252 | + | ||
253 | + qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1)); | ||
254 | +} | ||
255 | + | ||
256 | +static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc) | ||
257 | +{ | ||
258 | + uint32_t value = ppc->parent->secppcinten; | ||
259 | + | ||
260 | + qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)); | ||
261 | +} | ||
262 | + | ||
263 | static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
264 | uint64_t value, | ||
265 | unsigned size, MemTxAttrs attrs) | ||
266 | { | ||
267 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
268 | uint32_t offset = addr; | ||
269 | + IoTKitSecCtlPPC *ppc; | ||
270 | |||
271 | trace_iotkit_secctl_s_write(offset, value, size); | ||
272 | |||
273 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
274 | |||
275 | switch (offset) { | ||
276 | case A_SECRESPCFG: | ||
277 | - case A_NSCCFG: | ||
278 | + value &= 1; | ||
279 | + s->secrespcfg = value; | ||
280 | + qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); | ||
281 | + break; | ||
282 | case A_SECPPCINTCLR: | ||
283 | + value &= 0x00f000f3; | ||
284 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear); | ||
285 | + break; | ||
286 | case A_SECPPCINTEN: | ||
287 | - case A_SECMSCINTCLR: | ||
288 | - case A_SECMSCINTEN: | ||
289 | - case A_BRGINTCLR: | ||
290 | - case A_BRGINTEN: | ||
291 | + s->secppcinten = value & 0x00f000f3; | ||
292 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
293 | + break; | ||
294 | case A_AHBNSPPCEXP0: | ||
295 | case A_AHBNSPPCEXP1: | ||
296 | case A_AHBNSPPCEXP2: | ||
297 | case A_AHBNSPPCEXP3: | ||
298 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
299 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
300 | + break; | ||
301 | case A_APBNSPPC0: | ||
302 | case A_APBNSPPC1: | ||
303 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
304 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
305 | + break; | ||
306 | case A_APBNSPPCEXP0: | ||
307 | case A_APBNSPPCEXP1: | ||
308 | case A_APBNSPPCEXP2: | ||
309 | case A_APBNSPPCEXP3: | ||
310 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
311 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
312 | + break; | ||
313 | case A_AHBSPPPCEXP0: | ||
314 | case A_AHBSPPPCEXP1: | ||
315 | case A_AHBSPPPCEXP2: | ||
316 | case A_AHBSPPPCEXP3: | ||
317 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
318 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
319 | + break; | ||
320 | case A_APBSPPPC0: | ||
321 | case A_APBSPPPC1: | ||
322 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
323 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
324 | + break; | ||
325 | case A_APBSPPPCEXP0: | ||
326 | case A_APBSPPPCEXP1: | ||
327 | case A_APBSPPPCEXP2: | ||
328 | case A_APBSPPPCEXP3: | ||
329 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
330 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
331 | + break; | ||
332 | + case A_NSCCFG: | ||
333 | + case A_SECMSCINTCLR: | ||
334 | + case A_SECMSCINTEN: | ||
335 | + case A_BRGINTCLR: | ||
336 | + case A_BRGINTEN: | ||
337 | qemu_log_mask(LOG_UNIMP, | ||
338 | "IoTKit SecCtl S block write: " | ||
339 | "unimplemented offset 0x%x\n", offset); | ||
340 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
341 | uint64_t *pdata, | ||
342 | unsigned size, MemTxAttrs attrs) | ||
343 | { | ||
344 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
345 | uint64_t r; | ||
346 | uint32_t offset = addr & ~0x3; | ||
347 | |||
348 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
349 | case A_AHBNSPPPCEXP1: | ||
350 | case A_AHBNSPPPCEXP2: | ||
351 | case A_AHBNSPPPCEXP3: | ||
352 | + r = s->ahbexp[offset_to_ppc_idx(offset)].nsp; | ||
353 | + break; | ||
354 | case A_APBNSPPPC0: | ||
355 | case A_APBNSPPPC1: | ||
356 | + r = s->apb[offset_to_ppc_idx(offset)].nsp; | ||
357 | + break; | ||
358 | case A_APBNSPPPCEXP0: | ||
359 | case A_APBNSPPPCEXP1: | ||
360 | case A_APBNSPPPCEXP2: | ||
361 | case A_APBNSPPPCEXP3: | ||
362 | - qemu_log_mask(LOG_UNIMP, | ||
363 | - "IoTKit SecCtl NS block read: " | ||
364 | - "unimplemented offset 0x%x\n", offset); | ||
365 | + r = s->apbexp[offset_to_ppc_idx(offset)].nsp; | ||
366 | break; | ||
367 | case A_PID4: | ||
368 | case A_PID5: | ||
369 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
370 | uint64_t value, | ||
371 | unsigned size, MemTxAttrs attrs) | ||
372 | { | ||
373 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
374 | uint32_t offset = addr; | ||
375 | + IoTKitSecCtlPPC *ppc; | ||
376 | |||
377 | trace_iotkit_secctl_ns_write(offset, value, size); | ||
378 | |||
379 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
380 | case A_AHBNSPPPCEXP1: | ||
381 | case A_AHBNSPPPCEXP2: | ||
382 | case A_AHBNSPPPCEXP3: | ||
383 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
384 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
385 | + break; | ||
386 | case A_APBNSPPPC0: | ||
387 | case A_APBNSPPPC1: | ||
388 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
389 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
390 | + break; | ||
391 | case A_APBNSPPPCEXP0: | ||
392 | case A_APBNSPPPCEXP1: | ||
393 | case A_APBNSPPPCEXP2: | ||
394 | case A_APBNSPPPCEXP3: | ||
395 | - qemu_log_mask(LOG_UNIMP, | ||
396 | - "IoTKit SecCtl NS block write: " | ||
397 | - "unimplemented offset 0x%x\n", offset); | ||
398 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
399 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
400 | break; | ||
401 | case A_AHBNSPPPC0: | ||
402 | case A_PID4: | ||
403 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
404 | .impl.max_access_size = 4, | ||
405 | }; | ||
406 | |||
407 | +static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc) | ||
408 | +{ | ||
409 | + ppc->ns = 0; | ||
410 | + ppc->sp = 0; | ||
411 | + ppc->nsp = 0; | ||
412 | +} | ||
413 | + | ||
414 | static void iotkit_secctl_reset(DeviceState *dev) | ||
415 | { | ||
416 | + IoTKitSecCtl *s = IOTKIT_SECCTL(dev); | ||
417 | |||
418 | + s->secppcintstat = 0; | ||
419 | + s->secppcinten = 0; | ||
420 | + s->secrespcfg = 0; | ||
421 | + | ||
422 | + foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
423 | +} | ||
424 | + | ||
425 | +static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level) | ||
426 | +{ | ||
427 | + IoTKitSecCtlPPC *ppc = opaque; | ||
428 | + IoTKitSecCtl *s = IOTKIT_SECCTL(ppc->parent); | ||
429 | + int irqbit = ppc->irq_bit_offset + n; | ||
430 | + | ||
431 | + s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level); | ||
432 | +} | ||
433 | + | ||
434 | +static void iotkit_secctl_init_ppc(IoTKitSecCtl *s, | ||
435 | + IoTKitSecCtlPPC *ppc, | ||
436 | + const char *name, | ||
437 | + int numports, | ||
438 | + int irq_bit_offset) | ||
439 | +{ | ||
440 | + char *gpioname; | ||
441 | + DeviceState *dev = DEVICE(s); | ||
442 | + | ||
443 | + ppc->numports = numports; | ||
444 | + ppc->irq_bit_offset = irq_bit_offset; | ||
445 | + ppc->parent = s; | ||
446 | + | ||
447 | + gpioname = g_strdup_printf("%s_nonsec", name); | ||
448 | + qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports); | ||
449 | + g_free(gpioname); | ||
450 | + gpioname = g_strdup_printf("%s_ap", name); | ||
451 | + qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports); | ||
452 | + g_free(gpioname); | ||
453 | + gpioname = g_strdup_printf("%s_irq_enable", name); | ||
454 | + qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_irq_clear", name); | ||
457 | + qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1); | ||
458 | + g_free(gpioname); | ||
459 | + gpioname = g_strdup_printf("%s_irq_status", name); | ||
460 | + qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus, | ||
461 | + ppc, gpioname, 1); | ||
462 | + g_free(gpioname); | ||
463 | } | ||
464 | |||
465 | static void iotkit_secctl_init(Object *obj) | ||
466 | { | ||
467 | IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
468 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
469 | + DeviceState *dev = DEVICE(obj); | ||
470 | + int i; | ||
471 | + | ||
472 | + iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0", | ||
473 | + IOTS_APB_PPC0_NUM_PORTS, 0); | ||
474 | + iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1", | ||
475 | + IOTS_APB_PPC1_NUM_PORTS, 1); | ||
476 | + | ||
477 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
478 | + IoTKitSecCtlPPC *ppc = &s->apbexp[i]; | ||
479 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
480 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i); | ||
481 | + g_free(ppcname); | ||
482 | + } | ||
483 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
484 | + IoTKitSecCtlPPC *ppc = &s->ahbexp[i]; | ||
485 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
486 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i); | ||
487 | + g_free(ppcname); | ||
488 | + } | ||
489 | + | ||
490 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
491 | |||
492 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
495 | sysbus_init_mmio(sbd, &s->ns_regs); | ||
496 | } | ||
497 | |||
498 | +static const VMStateDescription iotkit_secctl_ppc_vmstate = { | ||
499 | + .name = "iotkit-secctl-ppc", | ||
500 | + .version_id = 1, | ||
501 | + .minimum_version_id = 1, | ||
502 | + .fields = (VMStateField[]) { | ||
503 | + VMSTATE_UINT32(ns, IoTKitSecCtlPPC), | ||
504 | + VMSTATE_UINT32(sp, IoTKitSecCtlPPC), | ||
505 | + VMSTATE_UINT32(nsp, IoTKitSecCtlPPC), | ||
506 | + VMSTATE_END_OF_LIST() | ||
507 | + } | ||
508 | +}; | ||
509 | + | ||
510 | static const VMStateDescription iotkit_secctl_vmstate = { | ||
511 | .name = "iotkit-secctl", | ||
512 | .version_id = 1, | ||
513 | .minimum_version_id = 1, | ||
514 | .fields = (VMStateField[]) { | ||
515 | + VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
516 | + VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
517 | + VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
518 | + VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
519 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
520 | + VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
521 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
522 | + VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1, | ||
523 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
524 | VMSTATE_END_OF_LIST() | ||
525 | } | ||
526 | }; | ||
527 | -- | 70 | -- |
528 | 2.16.2 | 71 | 2.20.1 |
529 | 72 | ||
530 | 73 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add remaining easy registers to iotkit-secctl: | ||
2 | * NSCCFG just routes its two bits out to external GPIO lines | ||
3 | * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's | ||
4 | bus fabric can never report errors | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180220180325.29818-18-peter.maydell@linaro.org | ||
8 | --- | ||
9 | include/hw/misc/iotkit-secctl.h | 4 ++++ | ||
10 | hw/misc/iotkit-secctl.c | 32 ++++++++++++++++++++++++++------ | ||
11 | 2 files changed, 30 insertions(+), 6 deletions(-) | ||
12 | |||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/misc/iotkit-secctl.h | ||
16 | +++ b/include/hw/misc/iotkit-secctl.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
19 | * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | ||
20 | * should RAZ/WI or bus error | ||
21 | + * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value | ||
22 | * Controlling the 2 APB PPCs in the IoTKit: | ||
23 | * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
24 | * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
25 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
26 | |||
27 | /*< public >*/ | ||
28 | qemu_irq sec_resp_cfg; | ||
29 | + qemu_irq nsc_cfg_irq; | ||
30 | |||
31 | MemoryRegion s_regs; | ||
32 | MemoryRegion ns_regs; | ||
33 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
34 | uint32_t secppcintstat; | ||
35 | uint32_t secppcinten; | ||
36 | uint32_t secrespcfg; | ||
37 | + uint32_t nsccfg; | ||
38 | + uint32_t brginten; | ||
39 | |||
40 | IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
41 | IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
42 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/misc/iotkit-secctl.c | ||
45 | +++ b/hw/misc/iotkit-secctl.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
47 | case A_SECRESPCFG: | ||
48 | r = s->secrespcfg; | ||
49 | break; | ||
50 | + case A_NSCCFG: | ||
51 | + r = s->nsccfg; | ||
52 | + break; | ||
53 | case A_SECPPCINTSTAT: | ||
54 | r = s->secppcintstat; | ||
55 | break; | ||
56 | case A_SECPPCINTEN: | ||
57 | r = s->secppcinten; | ||
58 | break; | ||
59 | + case A_BRGINTSTAT: | ||
60 | + /* QEMU's bus fabric can never report errors as it doesn't buffer | ||
61 | + * writes, so we never report bridge interrupts. | ||
62 | + */ | ||
63 | + r = 0; | ||
64 | + break; | ||
65 | + case A_BRGINTEN: | ||
66 | + r = s->brginten; | ||
67 | + break; | ||
68 | case A_AHBNSPPCEXP0: | ||
69 | case A_AHBNSPPCEXP1: | ||
70 | case A_AHBNSPPCEXP2: | ||
71 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
72 | case A_APBSPPPCEXP3: | ||
73 | r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
74 | break; | ||
75 | - case A_NSCCFG: | ||
76 | case A_SECMPCINTSTATUS: | ||
77 | case A_SECMSCINTSTAT: | ||
78 | case A_SECMSCINTEN: | ||
79 | - case A_BRGINTSTAT: | ||
80 | - case A_BRGINTEN: | ||
81 | case A_NSMSCEXP: | ||
82 | qemu_log_mask(LOG_UNIMP, | ||
83 | "IoTKit SecCtl S block read: " | ||
84 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
85 | } | ||
86 | |||
87 | switch (offset) { | ||
88 | + case A_NSCCFG: | ||
89 | + s->nsccfg = value & 3; | ||
90 | + qemu_set_irq(s->nsc_cfg_irq, s->nsccfg); | ||
91 | + break; | ||
92 | case A_SECRESPCFG: | ||
93 | value &= 1; | ||
94 | s->secrespcfg = value; | ||
95 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
96 | s->secppcinten = value & 0x00f000f3; | ||
97 | foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
98 | break; | ||
99 | + case A_BRGINTCLR: | ||
100 | + break; | ||
101 | + case A_BRGINTEN: | ||
102 | + s->brginten = value & 0xffff0000; | ||
103 | + break; | ||
104 | case A_AHBNSPPCEXP0: | ||
105 | case A_AHBNSPPCEXP1: | ||
106 | case A_AHBNSPPCEXP2: | ||
107 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
108 | ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
109 | iotkit_secctl_ppc_sp_write(ppc, value); | ||
110 | break; | ||
111 | - case A_NSCCFG: | ||
112 | case A_SECMSCINTCLR: | ||
113 | case A_SECMSCINTEN: | ||
114 | - case A_BRGINTCLR: | ||
115 | - case A_BRGINTEN: | ||
116 | qemu_log_mask(LOG_UNIMP, | ||
117 | "IoTKit SecCtl S block write: " | ||
118 | "unimplemented offset 0x%x\n", offset); | ||
119 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_reset(DeviceState *dev) | ||
120 | s->secppcintstat = 0; | ||
121 | s->secppcinten = 0; | ||
122 | s->secrespcfg = 0; | ||
123 | + s->nsccfg = 0; | ||
124 | + s->brginten = 0; | ||
125 | |||
126 | foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
127 | } | ||
128 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
129 | } | ||
130 | |||
131 | qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
132 | + qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); | ||
133 | |||
134 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
135 | s, "iotkit-secctl-s-regs", 0x1000); | ||
136 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_vmstate = { | ||
137 | VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
138 | VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
139 | VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
140 | + VMSTATE_UINT32(nsccfg, IoTKitSecCtl), | ||
141 | + VMSTATE_UINT32(brginten, IoTKitSecCtl), | ||
142 | VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
143 | iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
144 | VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
145 | -- | ||
146 | 2.16.2 | ||
147 | |||
148 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Define a new board model for the MPS2 with an AN505 FPGA image | ||
2 | containing a Cortex-M33. Since the FPGA images for TrustZone | ||
3 | cores (AN505, and the similar AN519 for Cortex-M23) have a | ||
4 | significantly different layout of devices to the non-TrustZone | ||
5 | images, we use a new source file rather than shoehorning them | ||
6 | into the existing mps2.c. | ||
7 | 1 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-20-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/arm/Makefile.objs | 1 + | ||
13 | hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
14 | 2 files changed, 504 insertions(+) | ||
15 | create mode 100644 hw/arm/mps2-tz.c | ||
16 | |||
17 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/Makefile.objs | ||
20 | +++ b/hw/arm/Makefile.objs | ||
21 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | ||
22 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | ||
23 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | ||
24 | obj-$(CONFIG_MPS2) += mps2.o | ||
25 | +obj-$(CONFIG_MPS2) += mps2-tz.o | ||
26 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | ||
27 | obj-$(CONFIG_IOTKIT) += iotkit.o | ||
28 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/hw/arm/mps2-tz.c | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * ARM V2M MPS2 board emulation, trustzone aware FPGA images | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Linaro Limited | ||
38 | + * Written by Peter Maydell | ||
39 | + * | ||
40 | + * This program is free software; you can redistribute it and/or modify | ||
41 | + * it under the terms of the GNU General Public License version 2 or | ||
42 | + * (at your option) any later version. | ||
43 | + */ | ||
44 | + | ||
45 | +/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | ||
46 | + * FPGA but is otherwise the same as the 2). Since the CPU itself | ||
47 | + * and most of the devices are in the FPGA, the details of the board | ||
48 | + * as seen by the guest depend significantly on the FPGA image. | ||
49 | + * This source file covers the following FPGA images, for TrustZone cores: | ||
50 | + * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 | ||
51 | + * | ||
52 | + * Links to the TRM for the board itself and to the various Application | ||
53 | + * Notes which document the FPGA images can be found here: | ||
54 | + * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | ||
55 | + * | ||
56 | + * Board TRM: | ||
57 | + * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | ||
58 | + * Application Note AN505: | ||
59 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
60 | + * | ||
61 | + * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | ||
62 | + * (ARM ECM0601256) for the details of some of the device layout: | ||
63 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
64 | + */ | ||
65 | + | ||
66 | +#include "qemu/osdep.h" | ||
67 | +#include "qapi/error.h" | ||
68 | +#include "qemu/error-report.h" | ||
69 | +#include "hw/arm/arm.h" | ||
70 | +#include "hw/arm/armv7m.h" | ||
71 | +#include "hw/or-irq.h" | ||
72 | +#include "hw/boards.h" | ||
73 | +#include "exec/address-spaces.h" | ||
74 | +#include "sysemu/sysemu.h" | ||
75 | +#include "hw/misc/unimp.h" | ||
76 | +#include "hw/char/cmsdk-apb-uart.h" | ||
77 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
78 | +#include "hw/misc/mps2-scc.h" | ||
79 | +#include "hw/misc/mps2-fpgaio.h" | ||
80 | +#include "hw/arm/iotkit.h" | ||
81 | +#include "hw/devices.h" | ||
82 | +#include "net/net.h" | ||
83 | +#include "hw/core/split-irq.h" | ||
84 | + | ||
85 | +typedef enum MPS2TZFPGAType { | ||
86 | + FPGA_AN505, | ||
87 | +} MPS2TZFPGAType; | ||
88 | + | ||
89 | +typedef struct { | ||
90 | + MachineClass parent; | ||
91 | + MPS2TZFPGAType fpga_type; | ||
92 | + uint32_t scc_id; | ||
93 | +} MPS2TZMachineClass; | ||
94 | + | ||
95 | +typedef struct { | ||
96 | + MachineState parent; | ||
97 | + | ||
98 | + IoTKit iotkit; | ||
99 | + MemoryRegion psram; | ||
100 | + MemoryRegion ssram1; | ||
101 | + MemoryRegion ssram1_m; | ||
102 | + MemoryRegion ssram23; | ||
103 | + MPS2SCC scc; | ||
104 | + MPS2FPGAIO fpgaio; | ||
105 | + TZPPC ppc[5]; | ||
106 | + UnimplementedDeviceState ssram_mpc[3]; | ||
107 | + UnimplementedDeviceState spi[5]; | ||
108 | + UnimplementedDeviceState i2c[4]; | ||
109 | + UnimplementedDeviceState i2s_audio; | ||
110 | + UnimplementedDeviceState gpio[5]; | ||
111 | + UnimplementedDeviceState dma[4]; | ||
112 | + UnimplementedDeviceState gfx; | ||
113 | + CMSDKAPBUART uart[5]; | ||
114 | + SplitIRQ sec_resp_splitter; | ||
115 | + qemu_or_irq uart_irq_orgate; | ||
116 | +} MPS2TZMachineState; | ||
117 | + | ||
118 | +#define TYPE_MPS2TZ_MACHINE "mps2tz" | ||
119 | +#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") | ||
120 | + | ||
121 | +#define MPS2TZ_MACHINE(obj) \ | ||
122 | + OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) | ||
123 | +#define MPS2TZ_MACHINE_GET_CLASS(obj) \ | ||
124 | + OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) | ||
125 | +#define MPS2TZ_MACHINE_CLASS(klass) \ | ||
126 | + OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) | ||
127 | + | ||
128 | +/* Main SYSCLK frequency in Hz */ | ||
129 | +#define SYSCLK_FRQ 20000000 | ||
130 | + | ||
131 | +/* Initialize the auxiliary RAM region @mr and map it into | ||
132 | + * the memory map at @base. | ||
133 | + */ | ||
134 | +static void make_ram(MemoryRegion *mr, const char *name, | ||
135 | + hwaddr base, hwaddr size) | ||
136 | +{ | ||
137 | + memory_region_init_ram(mr, NULL, name, size, &error_fatal); | ||
138 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
139 | +} | ||
140 | + | ||
141 | +/* Create an alias of an entire original MemoryRegion @orig | ||
142 | + * located at @base in the memory map. | ||
143 | + */ | ||
144 | +static void make_ram_alias(MemoryRegion *mr, const char *name, | ||
145 | + MemoryRegion *orig, hwaddr base) | ||
146 | +{ | ||
147 | + memory_region_init_alias(mr, NULL, name, orig, 0, | ||
148 | + memory_region_size(orig)); | ||
149 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
150 | +} | ||
151 | + | ||
152 | +static void init_sysbus_child(Object *parent, const char *childname, | ||
153 | + void *child, size_t childsize, | ||
154 | + const char *childtype) | ||
155 | +{ | ||
156 | + object_initialize(child, childsize, childtype); | ||
157 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | ||
158 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
159 | + | ||
160 | +} | ||
161 | + | ||
162 | +/* Most of the devices in the AN505 FPGA image sit behind | ||
163 | + * Peripheral Protection Controllers. These data structures | ||
164 | + * define the layout of which devices sit behind which PPCs. | ||
165 | + * The devfn for each port is a function which creates, configures | ||
166 | + * and initializes the device, returning the MemoryRegion which | ||
167 | + * needs to be plugged into the downstream end of the PPC port. | ||
168 | + */ | ||
169 | +typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, | ||
170 | + const char *name, hwaddr size); | ||
171 | + | ||
172 | +typedef struct PPCPortInfo { | ||
173 | + const char *name; | ||
174 | + MakeDevFn *devfn; | ||
175 | + void *opaque; | ||
176 | + hwaddr addr; | ||
177 | + hwaddr size; | ||
178 | +} PPCPortInfo; | ||
179 | + | ||
180 | +typedef struct PPCInfo { | ||
181 | + const char *name; | ||
182 | + PPCPortInfo ports[TZ_NUM_PORTS]; | ||
183 | +} PPCInfo; | ||
184 | + | ||
185 | +static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | ||
186 | + void *opaque, | ||
187 | + const char *name, hwaddr size) | ||
188 | +{ | ||
189 | + /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | ||
190 | + * and return a pointer to its MemoryRegion. | ||
191 | + */ | ||
192 | + UnimplementedDeviceState *uds = opaque; | ||
193 | + | ||
194 | + init_sysbus_child(OBJECT(mms), name, uds, | ||
195 | + sizeof(UnimplementedDeviceState), | ||
196 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
197 | + qdev_prop_set_string(DEVICE(uds), "name", name); | ||
198 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | ||
199 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | ||
200 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); | ||
201 | +} | ||
202 | + | ||
203 | +static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | ||
204 | + const char *name, hwaddr size) | ||
205 | +{ | ||
206 | + CMSDKAPBUART *uart = opaque; | ||
207 | + int i = uart - &mms->uart[0]; | ||
208 | + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; | ||
209 | + int rxirqno = i * 2; | ||
210 | + int txirqno = i * 2 + 1; | ||
211 | + int combirqno = i + 10; | ||
212 | + SysBusDevice *s; | ||
213 | + DeviceState *iotkitdev = DEVICE(&mms->iotkit); | ||
214 | + DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | ||
215 | + | ||
216 | + init_sysbus_child(OBJECT(mms), name, uart, | ||
217 | + sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); | ||
218 | + qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); | ||
219 | + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); | ||
220 | + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | ||
221 | + s = SYS_BUS_DEVICE(uart); | ||
222 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, | ||
223 | + "EXP_IRQ", txirqno)); | ||
224 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, | ||
225 | + "EXP_IRQ", rxirqno)); | ||
226 | + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); | ||
227 | + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | ||
228 | + sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, | ||
229 | + "EXP_IRQ", combirqno)); | ||
230 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); | ||
231 | +} | ||
232 | + | ||
233 | +static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | ||
234 | + const char *name, hwaddr size) | ||
235 | +{ | ||
236 | + MPS2SCC *scc = opaque; | ||
237 | + DeviceState *sccdev; | ||
238 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
239 | + | ||
240 | + object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); | ||
241 | + sccdev = DEVICE(scc); | ||
242 | + qdev_set_parent_bus(sccdev, sysbus_get_default()); | ||
243 | + qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | ||
244 | + qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); | ||
245 | + qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | ||
246 | + object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); | ||
247 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); | ||
248 | +} | ||
249 | + | ||
250 | +static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | ||
251 | + const char *name, hwaddr size) | ||
252 | +{ | ||
253 | + MPS2FPGAIO *fpgaio = opaque; | ||
254 | + | ||
255 | + object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); | ||
256 | + qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); | ||
257 | + object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); | ||
258 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
259 | +} | ||
260 | + | ||
261 | +static void mps2tz_common_init(MachineState *machine) | ||
262 | +{ | ||
263 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
264 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
265 | + MemoryRegion *system_memory = get_system_memory(); | ||
266 | + DeviceState *iotkitdev; | ||
267 | + DeviceState *dev_splitter; | ||
268 | + int i; | ||
269 | + | ||
270 | + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | ||
271 | + error_report("This board can only be used with CPU %s", | ||
272 | + mc->default_cpu_type); | ||
273 | + exit(1); | ||
274 | + } | ||
275 | + | ||
276 | + init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, | ||
277 | + sizeof(mms->iotkit), TYPE_IOTKIT); | ||
278 | + iotkitdev = DEVICE(&mms->iotkit); | ||
279 | + object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | ||
280 | + "memory", &error_abort); | ||
281 | + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); | ||
282 | + qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); | ||
283 | + object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", | ||
284 | + &error_fatal); | ||
285 | + | ||
286 | + /* The sec_resp_cfg output from the IoTKit must be split into multiple | ||
287 | + * lines, one for each of the PPCs we create here. | ||
288 | + */ | ||
289 | + object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), | ||
290 | + TYPE_SPLIT_IRQ); | ||
291 | + object_property_add_child(OBJECT(machine), "sec-resp-splitter", | ||
292 | + OBJECT(&mms->sec_resp_splitter), &error_abort); | ||
293 | + object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, | ||
294 | + "num-lines", &error_fatal); | ||
295 | + object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, | ||
296 | + "realized", &error_fatal); | ||
297 | + dev_splitter = DEVICE(&mms->sec_resp_splitter); | ||
298 | + qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, | ||
299 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
300 | + | ||
301 | + /* The IoTKit sets up much of the memory layout, including | ||
302 | + * the aliases between secure and non-secure regions in the | ||
303 | + * address space. The FPGA itself contains: | ||
304 | + * | ||
305 | + * 0x00000000..0x003fffff SSRAM1 | ||
306 | + * 0x00400000..0x007fffff alias of SSRAM1 | ||
307 | + * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 | ||
308 | + * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices | ||
309 | + * 0x80000000..0x80ffffff 16MB PSRAM | ||
310 | + */ | ||
311 | + | ||
312 | + /* The FPGA images have an odd combination of different RAMs, | ||
313 | + * because in hardware they are different implementations and | ||
314 | + * connected to different buses, giving varying performance/size | ||
315 | + * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | ||
316 | + * call the 16MB our "system memory", as it's the largest lump. | ||
317 | + */ | ||
318 | + memory_region_allocate_system_memory(&mms->psram, | ||
319 | + NULL, "mps.ram", 0x01000000); | ||
320 | + memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); | ||
321 | + | ||
322 | + /* The SSRAM memories should all be behind Memory Protection Controllers, | ||
323 | + * but we don't implement that yet. | ||
324 | + */ | ||
325 | + make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000); | ||
326 | + make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000); | ||
327 | + | ||
328 | + make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000); | ||
329 | + | ||
330 | + /* The overflow IRQs for all UARTs are ORed together. | ||
331 | + * Tx, Rx and "combined" IRQs are sent to the NVIC separately. | ||
332 | + * Create the OR gate for this. | ||
333 | + */ | ||
334 | + object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), | ||
335 | + TYPE_OR_IRQ); | ||
336 | + object_property_add_child(OBJECT(mms), "uart-irq-orgate", | ||
337 | + OBJECT(&mms->uart_irq_orgate), &error_abort); | ||
338 | + object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", | ||
339 | + &error_fatal); | ||
340 | + object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, | ||
341 | + "realized", &error_fatal); | ||
342 | + qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | ||
343 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); | ||
344 | + | ||
345 | + /* Most of the devices in the FPGA are behind Peripheral Protection | ||
346 | + * Controllers. The required order for initializing things is: | ||
347 | + * + initialize the PPC | ||
348 | + * + initialize, configure and realize downstream devices | ||
349 | + * + connect downstream device MemoryRegions to the PPC | ||
350 | + * + realize the PPC | ||
351 | + * + map the PPC's MemoryRegions to the places in the address map | ||
352 | + * where the downstream devices should appear | ||
353 | + * + wire up the PPC's control lines to the IoTKit object | ||
354 | + */ | ||
355 | + | ||
356 | + const PPCInfo ppcs[] = { { | ||
357 | + .name = "apb_ppcexp0", | ||
358 | + .ports = { | ||
359 | + { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0], | ||
360 | + 0x58007000, 0x1000 }, | ||
361 | + { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1], | ||
362 | + 0x58008000, 0x1000 }, | ||
363 | + { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2], | ||
364 | + 0x58009000, 0x1000 }, | ||
365 | + }, | ||
366 | + }, { | ||
367 | + .name = "apb_ppcexp1", | ||
368 | + .ports = { | ||
369 | + { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, | ||
370 | + { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, | ||
371 | + { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, | ||
372 | + { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, | ||
373 | + { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, | ||
374 | + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, | ||
375 | + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | ||
376 | + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | ||
377 | + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | ||
378 | + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | ||
379 | + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
380 | + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
381 | + { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
382 | + { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | ||
383 | + }, | ||
384 | + }, { | ||
385 | + .name = "apb_ppcexp2", | ||
386 | + .ports = { | ||
387 | + { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, | ||
388 | + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, | ||
389 | + 0x40301000, 0x1000 }, | ||
390 | + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, | ||
391 | + }, | ||
392 | + }, { | ||
393 | + .name = "ahb_ppcexp0", | ||
394 | + .ports = { | ||
395 | + { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, | ||
396 | + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, | ||
397 | + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
398 | + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
399 | + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
400 | + { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, | ||
401 | + }, | ||
402 | + }, { | ||
403 | + .name = "ahb_ppcexp1", | ||
404 | + .ports = { | ||
405 | + { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, | ||
406 | + { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, | ||
407 | + { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, | ||
408 | + { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, | ||
409 | + }, | ||
410 | + }, | ||
411 | + }; | ||
412 | + | ||
413 | + for (i = 0; i < ARRAY_SIZE(ppcs); i++) { | ||
414 | + const PPCInfo *ppcinfo = &ppcs[i]; | ||
415 | + TZPPC *ppc = &mms->ppc[i]; | ||
416 | + DeviceState *ppcdev; | ||
417 | + int port; | ||
418 | + char *gpioname; | ||
419 | + | ||
420 | + init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, | ||
421 | + sizeof(TZPPC), TYPE_TZ_PPC); | ||
422 | + ppcdev = DEVICE(ppc); | ||
423 | + | ||
424 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
425 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
426 | + MemoryRegion *mr; | ||
427 | + char *portname; | ||
428 | + | ||
429 | + if (!pinfo->devfn) { | ||
430 | + continue; | ||
431 | + } | ||
432 | + | ||
433 | + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | ||
434 | + portname = g_strdup_printf("port[%d]", port); | ||
435 | + object_property_set_link(OBJECT(ppc), OBJECT(mr), | ||
436 | + portname, &error_fatal); | ||
437 | + g_free(portname); | ||
438 | + } | ||
439 | + | ||
440 | + object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); | ||
441 | + | ||
442 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
443 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
444 | + | ||
445 | + if (!pinfo->devfn) { | ||
446 | + continue; | ||
447 | + } | ||
448 | + sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); | ||
449 | + | ||
450 | + gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); | ||
451 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
452 | + qdev_get_gpio_in_named(ppcdev, | ||
453 | + "cfg_nonsec", | ||
454 | + port)); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_ap", ppcinfo->name); | ||
457 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
458 | + qdev_get_gpio_in_named(ppcdev, | ||
459 | + "cfg_ap", port)); | ||
460 | + g_free(gpioname); | ||
461 | + } | ||
462 | + | ||
463 | + gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); | ||
464 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | ||
465 | + qdev_get_gpio_in_named(ppcdev, | ||
466 | + "irq_enable", 0)); | ||
467 | + g_free(gpioname); | ||
468 | + gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); | ||
469 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | ||
470 | + qdev_get_gpio_in_named(ppcdev, | ||
471 | + "irq_clear", 0)); | ||
472 | + g_free(gpioname); | ||
473 | + gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); | ||
474 | + qdev_connect_gpio_out_named(ppcdev, "irq", 0, | ||
475 | + qdev_get_gpio_in_named(iotkitdev, | ||
476 | + gpioname, 0)); | ||
477 | + g_free(gpioname); | ||
478 | + | ||
479 | + qdev_connect_gpio_out(dev_splitter, i, | ||
480 | + qdev_get_gpio_in_named(ppcdev, | ||
481 | + "cfg_sec_resp", 0)); | ||
482 | + } | ||
483 | + | ||
484 | + /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
485 | + * except that it doesn't support the checksum-offload feature. | ||
486 | + * The ethernet controller is not behind a PPC. | ||
487 | + */ | ||
488 | + lan9118_init(&nd_table[0], 0x42000000, | ||
489 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | ||
490 | + | ||
491 | + create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); | ||
492 | + | ||
493 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | ||
494 | +} | ||
495 | + | ||
496 | +static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
497 | +{ | ||
498 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
499 | + | ||
500 | + mc->init = mps2tz_common_init; | ||
501 | + mc->max_cpus = 1; | ||
502 | +} | ||
503 | + | ||
504 | +static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | ||
505 | +{ | ||
506 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
507 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
508 | + | ||
509 | + mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; | ||
510 | + mmc->fpga_type = FPGA_AN505; | ||
511 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | ||
512 | + mmc->scc_id = 0x41040000 | (505 << 4); | ||
513 | +} | ||
514 | + | ||
515 | +static const TypeInfo mps2tz_info = { | ||
516 | + .name = TYPE_MPS2TZ_MACHINE, | ||
517 | + .parent = TYPE_MACHINE, | ||
518 | + .abstract = true, | ||
519 | + .instance_size = sizeof(MPS2TZMachineState), | ||
520 | + .class_size = sizeof(MPS2TZMachineClass), | ||
521 | + .class_init = mps2tz_class_init, | ||
522 | +}; | ||
523 | + | ||
524 | +static const TypeInfo mps2tz_an505_info = { | ||
525 | + .name = TYPE_MPS2TZ_AN505_MACHINE, | ||
526 | + .parent = TYPE_MPS2TZ_MACHINE, | ||
527 | + .class_init = mps2tz_an505_class_init, | ||
528 | +}; | ||
529 | + | ||
530 | +static void mps2tz_machine_init(void) | ||
531 | +{ | ||
532 | + type_register_static(&mps2tz_info); | ||
533 | + type_register_static(&mps2tz_an505_info); | ||
534 | +} | ||
535 | + | ||
536 | +type_init(mps2tz_machine_init); | ||
537 | -- | ||
538 | 2.16.2 | ||
539 | |||
540 | diff view generated by jsdifflib |