Second pull request of the week; mostly RTH's support for some

new-in-v8.1/v8.3 instructions, and my v8M board model.

The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302

for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078:

target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000)

* implement FCMA and RDM v8.1 and v8.3 instructions

* enable Cortex-M33 v8M core, and provide new mps2-an505 board model

that uses it

* decodetree: Propagate return value from translate subroutines

* xlnx-zynqmp: Implement the RTC device

Alistair Francis (3):

xlnx-zynqmp-rtc: Initial commit

xlnx-zynqmp-rtc: Add basic time support

xlnx-zynqmp: Connect the RTC device

Peter Maydell (19):

loader: Add new load_ramdisk_as()

hw/arm/boot: Honour CPU's address space for image loads

hw/arm/armv7m: Honour CPU's address space for image loads

target/arm: Define an IDAU interface

armv7m: Forward idau property to CPU object

target/arm: Define init-svtor property for the reset secure VTOR value

armv7m: Forward init-svtor property to CPU object

target/arm: Add Cortex-M33

hw/misc/unimp: Move struct to header file

include/hw/or-irq.h: Add missing include guard

qdev: Add new qdev_init_gpio_in_named_with_opaque()

hw/core/split-irq: Device that splits IRQ lines

hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505

hw/misc/tz-ppc: Model TrustZone peripheral protection controller

hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton

hw/misc/iotkit-secctl: Add handling for PPCs

hw/misc/iotkit-secctl: Add remaining simple registers

hw/arm/iotkit: Model Arm IOT Kit

mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image

Instead of loading kernels, device trees, and the like to

the system address space, use the CPU's address space. This

is important if we're trying to load the file to memory or

via an alias memory region that is provided by an SoC

object and thus not mapped into the system address space.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180220180325.29818-3-peter.maydell@linaro.org

hw/arm/boot.c | 119 +++++++++++++++++++++++++++++++++++++---------------------

1 file changed, 76 insertions(+), 43 deletions(-)

@@ -XXX,XX +XXX,XX @@

#define ARM64_TEXT_OFFSET_OFFSET 8

#define ARM64_MAGIC_OFFSET 56

+static AddressSpace *arm_boot_address_space(ARMCPU *cpu,

+ const struct arm_boot_info *info)

+{

+ /* Return the address space to use for bootloader reads and writes.

+ * We prefer the secure address space if the CPU has it and we're

+ * going to boot the guest into it.

+ */

+ int asidx;

+ CPUState *cs = CPU(cpu);

+

+ if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {

+ asidx = ARMASIdx_S;

+ } else {

+ asidx = ARMASIdx_NS;

+ }

+

+ return cpu_get_address_space(cs, asidx);

+}

+

typedef enum {

FIXUP_NONE = 0, /* do nothing */

FIXUP_TERMINATOR, /* end of insns */

@@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup smpboot[] = {

};

static void write_bootloader(const char *name, hwaddr addr,

- const ARMInsnFixup *insns, uint32_t *fixupcontext)

+ const ARMInsnFixup *insns, uint32_t *fixupcontext,

+ AddressSpace *as)

{

/* Fix up the specified bootloader fragment and write it into

* guest memory using rom_add_blob_fixed(). fixupcontext is

@@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr,

code[i] = tswap32(insn);

}

- rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr);

+ rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);

g_free(code);

}

@@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu,

const struct arm_boot_info *info)

{

uint32_t fixupcontext[FIXUP_MAX];

+ AddressSpace *as = arm_boot_address_space(cpu, info);

fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;

fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;

@@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu,

}

write_bootloader("smpboot", info->smp_loader_start,

- smpboot, fixupcontext);

+ smpboot, fixupcontext, as);

}

void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,

const struct arm_boot_info *info,

hwaddr mvbar_addr)

{

+ AddressSpace *as = arm_boot_address_space(cpu, info);

int n;

uint32_t mvbar_blob[] = {

/* mvbar_addr: secure monitor vectors

@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,

for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {

mvbar_blob[n] = tswap32(mvbar_blob[n]);

}

- rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),

- mvbar_addr);

+ rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),

+ mvbar_addr, as);

for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {

board_setup_blob[n] = tswap32(board_setup_blob[n]);

}

- rom_add_blob_fixed("board-setup", board_setup_blob,

- sizeof(board_setup_blob), info->board_setup_addr);

+ rom_add_blob_fixed_as("board-setup", board_setup_blob,

+ sizeof(board_setup_blob), info->board_setup_addr, as);

}

static void default_reset_secondary(ARMCPU *cpu,

const struct arm_boot_info *info)

{

+ AddressSpace *as = arm_boot_address_space(cpu, info);

CPUState *cs = CPU(cpu);

- address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr,

+ address_space_stl_notdirty(as, info->smp_bootreg_addr,

0, MEMTXATTRS_UNSPECIFIED, NULL);

cpu_set_pc(cs, info->smp_loader_start);

}

@@ -XXX,XX +XXX,XX @@ static inline bool have_dtb(const struct arm_boot_info *info)

}

#define WRITE_WORD(p, value) do { \

- address_space_stl_notdirty(&address_space_memory, p, value, \

+ address_space_stl_notdirty(as, p, value, \

MEMTXATTRS_UNSPECIFIED, NULL); \

p += 4; \

} while (0)

-static void set_kernel_args(const struct arm_boot_info *info)

+static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)

{

int initrd_size = info->initrd_size;

hwaddr base = info->loader_start;

@@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info)

int cmdline_size;

cmdline_size = strlen(info->kernel_cmdline);

- cpu_physical_memory_write(p + 8, info->kernel_cmdline,

- cmdline_size + 1);

+ address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,

+ (const uint8_t *)info->kernel_cmdline,

+ cmdline_size + 1);

cmdline_size = (cmdline_size >> 2) + 1;

WRITE_WORD(p, cmdline_size + 2);

WRITE_WORD(p, 0x54410009);

@@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info)

atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;

WRITE_WORD(p, (atag_board_len + 8) >> 2);

WRITE_WORD(p, 0x414f4d50);

- cpu_physical_memory_write(p, atag_board_buf, atag_board_len);

+ address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,

+ atag_board_buf, atag_board_len);

p += atag_board_len;

}

/* ATAG_END */

@@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info)

WRITE_WORD(p, 0);

}

-static void set_kernel_args_old(const struct arm_boot_info *info)

+static void set_kernel_args_old(const struct arm_boot_info *info,

+ AddressSpace *as)

{

hwaddr p;

const char *s;

@@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info)

}

s = info->kernel_cmdline;

if (s) {

- cpu_physical_memory_write(p, s, strlen(s) + 1);

+ address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,

+ (const uint8_t *)s, strlen(s) + 1);

} else {

WRITE_WORD(p, 0);

}

@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)

* @addr: the address to load the image at

* @binfo: struct describing the boot environment

* @addr_limit: upper limit of the available memory area at @addr

+ * @as: address space to load image to

*

* Load a device tree supplied by the machine or by the user with the

* '-dtb' command line option, and put it at offset @addr in target

@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)

* Note: Must not be called unless have_dtb(binfo) is true.

*/

static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,

- hwaddr addr_limit)

+ hwaddr addr_limit, AddressSpace *as)

{

void *fdt = NULL;

int size, rc;

@@ -XXX,XX +XXX,XX @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,

/* Put the DTB into the memory map as a ROM image: this will ensure

* the DTB is copied again upon reset, even if addr points into RAM.

*/

- rom_add_blob_fixed("dtb", fdt, size, addr);

+ rom_add_blob_fixed_as("dtb", fdt, size, addr, as);

g_free(fdt);

@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)

}

if (cs == first_cpu) {

+ AddressSpace *as = arm_boot_address_space(cpu, info);

+

cpu_set_pc(cs, info->loader_start);

if (!have_dtb(info)) {

if (old_param) {

- set_kernel_args_old(info);

+ set_kernel_args_old(info, as);

} else {

- set_kernel_args(info);

+ set_kernel_args(info, as);

}

}

} else {

@@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque)

static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,

uint64_t *lowaddr, uint64_t *highaddr,

- int elf_machine)

+ int elf_machine, AddressSpace *as)

{

bool elf_is64;

union {

@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,

}

}

- ret = load_elf(info->kernel_filename, NULL, NULL,

- pentry, lowaddr, highaddr, big_endian, elf_machine,

- 1, data_swab);

+ ret = load_elf_as(info->kernel_filename, NULL, NULL,

+ pentry, lowaddr, highaddr, big_endian, elf_machine,

+ 1, data_swab, as);

if (ret <= 0) {

/* The header loaded but the image didn't */

exit(1);

@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,

}

static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,

- hwaddr *entry)

+ hwaddr *entry, AddressSpace *as)

{

hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;

uint8_t *buffer;

@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,

}

*entry = mem_base + kernel_load_offset;

- rom_add_blob_fixed(filename, buffer, size, *entry);

+ rom_add_blob_fixed_as(filename, buffer, size, *entry, as);

g_free(buffer);

@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)

ARMCPU *cpu = n->cpu;

struct arm_boot_info *info =

container_of(n, struct arm_boot_info, load_kernel_notifier);

+ AddressSpace *as = arm_boot_address_space(cpu, info);

/* The board code is not supposed to set secure_board_setup unless

* running its code in secure mode is actually possible, and KVM

@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)

* the kernel is supposed to be loaded by the bootloader), copy the

* DTB to the base of RAM for the bootloader to pick up.

*/

- if (load_dtb(info->loader_start, info, 0) < 0) {

+ if (load_dtb(info->loader_start, info, 0, as) < 0) {

exit(1);

}

}

@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)

/* Assume that raw images are linux kernels, and ELF images are not. */

kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,

- &elf_high_addr, elf_machine);

+ &elf_high_addr, elf_machine, as);

if (kernel_size > 0 && have_dtb(info)) {

/* If there is still some room left at the base of RAM, try and put

* the DTB there like we do for images loaded with -bios or -pflash.

@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)

if (elf_low_addr < info->loader_start) {

elf_low_addr = 0;

}

- if (load_dtb(info->loader_start, info, elf_low_addr) < 0) {

+ if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) {

exit(1);

}

}

}

entry = elf_entry;

if (kernel_size < 0) {

- kernel_size = load_uimage(info->kernel_filename, &entry, NULL,

- &is_linux, NULL, NULL);

+ kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL,

+ &is_linux, NULL, NULL, as);

}

if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {

kernel_size = load_aarch64_image(info->kernel_filename,

- info->loader_start, &entry);

+ info->loader_start, &entry, as);

is_linux = 1;

} else if (kernel_size < 0) {

- kernel_size = load_image_targphys(info->kernel_filename, entry,

- info->ram_size - KERNEL_LOAD_ADDR);

+ kernel_size = load_image_targphys_as(info->kernel_filename, entry,

+ info->ram_size - KERNEL_LOAD_ADDR,

+ as);

@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)

uint32_t fixupcontext[FIXUP_MAX];

- initrd_size = load_ramdisk(info->initrd_filename,

- info->initrd_start,

- info->ram_size -

- info->initrd_start);

+ initrd_size = load_ramdisk_as(info->initrd_filename,

+ info->initrd_start,

+ info->ram_size - info->initrd_start,

+ as);

- initrd_size = load_image_targphys(info->initrd_filename,

- info->initrd_start,

- info->ram_size -

- info->initrd_start);

+ initrd_size = load_image_targphys_as(info->initrd_filename,

+ info->initrd_start,

+ info->ram_size -

+ info->initrd_start,

+ as);

2.16.2

Define a new board model for the MPS2 with an AN505 FPGA image

containing a Cortex-M33. Since the FPGA images for TrustZone

cores (AN505, and the similar AN519 for Cortex-M23) have a

significantly different layout of devices to the non-TrustZone

images, we use a new source file rather than shoehorning them

into the existing mps2.c.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180220180325.29818-20-peter.maydell@linaro.org

hw/arm/Makefile.objs | 1 +

hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 504 insertions(+)

create mode 100644 hw/arm/mps2-tz.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

obj-$(CONFIG_MPS2) += mps2.o

+obj-$(CONFIG_MPS2) += mps2-tz.o

obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

obj-$(CONFIG_IOTKIT) += iotkit.o

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * ARM V2M MPS2 board emulation, trustzone aware FPGA images

+ *

+ * Copyright (c) 2017 Linaro Limited

+ * Written by Peter Maydell

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+ */

+/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger

+ * FPGA but is otherwise the same as the 2). Since the CPU itself

+ * and most of the devices are in the FPGA, the details of the board

+ * as seen by the guest depend significantly on the FPGA image.

+ * This source file covers the following FPGA images, for TrustZone cores:

+ * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505

+ *

+ * Links to the TRM for the board itself and to the various Application

+ * Notes which document the FPGA images can be found here:

+ * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2

+ *

+ * Board TRM:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf

+ * Application Note AN505:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html

+ *

+ * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide

+ * (ARM ECM0601256) for the details of some of the device layout:

+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu/error-report.h"

+#include "hw/arm/arm.h"

+#include "hw/arm/armv7m.h"

+#include "hw/or-irq.h"

+#include "hw/boards.h"

+#include "exec/address-spaces.h"

+#include "sysemu/sysemu.h"