1 | Second pull request of the week; mostly RTH's support for some | 1 | Arm stuff, mostly patches from RTH. |
---|---|---|---|
2 | new-in-v8.1/v8.3 instructions, and my v8M board model. | ||
3 | 2 | ||
4 | thanks | 3 | thanks |
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 427cbc7e4136a061628cb4315cc8182ea36d772f: | 6 | The following changes since commit 01a9a51ffaf4699827ea6425cb2b834a356e159d: |
8 | 7 | ||
9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2018-03-01 18:46:41 +0000) | 8 | Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190205-pull-request' into staging (2019-02-05 14:01:29 +0000) |
10 | 9 | ||
11 | are available in the Git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180302 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190205 |
14 | 13 | ||
15 | for you to fetch changes up to e66a67bf28e1b4fce2e3d72a2610dbd48d9d3078: | 14 | for you to fetch changes up to a15945d98d3a3390c3da344d1b47218e91e49d8b: |
16 | 15 | ||
17 | target/arm: Enable ARM_FEATURE_V8_FCMA (2018-03-02 11:03:45 +0000) | 16 | target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI (2019-02-05 16:52:42 +0000) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | target-arm queue: | 19 | target-arm queue: |
21 | * implement FCMA and RDM v8.1 and v8.3 instructions | 20 | * Implement Armv8.5-BTI extension for system emulation mode |
22 | * enable Cortex-M33 v8M core, and provide new mps2-an505 board model | 21 | * Implement the PR_PAC_RESET_KEYS prctl() for linux-user mode's Armv8.3-PAuth support |
23 | that uses it | 22 | * Support TBI (top-byte-ignore) properly for linux-user mode |
24 | * decodetree: Propagate return value from translate subroutines | 23 | * gdbstub: allow killing QEMU via vKill command |
25 | * xlnx-zynqmp: Implement the RTC device | 24 | * hw/arm/boot: Support DTB autoload for firmware-only boots |
25 | * target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI | ||
26 | 26 | ||
27 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
28 | Alistair Francis (3): | 28 | Max Filippov (1): |
29 | xlnx-zynqmp-rtc: Initial commit | 29 | gdbstub: allow killing QEMU via vKill command |
30 | xlnx-zynqmp-rtc: Add basic time support | ||
31 | xlnx-zynqmp: Connect the RTC device | ||
32 | 30 | ||
33 | Peter Maydell (19): | 31 | Peter Maydell (7): |
34 | loader: Add new load_ramdisk_as() | 32 | target/arm: Compute TB_FLAGS for TBI for user-only |
35 | hw/arm/boot: Honour CPU's address space for image loads | 33 | hw/arm/boot: Fix block comment style in arm_load_kernel() |
36 | hw/arm/armv7m: Honour CPU's address space for image loads | 34 | hw/arm/boot: Factor out "direct kernel boot" code into its own function |
37 | target/arm: Define an IDAU interface | 35 | hw/arm/boot: Factor out "set up firmware boot" code |
38 | armv7m: Forward idau property to CPU object | 36 | hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info |
39 | target/arm: Define init-svtor property for the reset secure VTOR value | 37 | hw/arm/boot: Support DTB autoload for firmware-only boots |
40 | armv7m: Forward init-svtor property to CPU object | 38 | target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI |
41 | target/arm: Add Cortex-M33 | ||
42 | hw/misc/unimp: Move struct to header file | ||
43 | include/hw/or-irq.h: Add missing include guard | ||
44 | qdev: Add new qdev_init_gpio_in_named_with_opaque() | ||
45 | hw/core/split-irq: Device that splits IRQ lines | ||
46 | hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505 | ||
47 | hw/misc/tz-ppc: Model TrustZone peripheral protection controller | ||
48 | hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton | ||
49 | hw/misc/iotkit-secctl: Add handling for PPCs | ||
50 | hw/misc/iotkit-secctl: Add remaining simple registers | ||
51 | hw/arm/iotkit: Model Arm IOT Kit | ||
52 | mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image | ||
53 | 39 | ||
54 | Richard Henderson (17): | 40 | Richard Henderson (14): |
55 | decodetree: Propagate return value from translate subroutines | 41 | target/arm: Introduce isar_feature_aa64_bti |
56 | target/arm: Add ARM_FEATURE_V8_RDM | 42 | target/arm: Add PSTATE.BTYPE |
57 | target/arm: Refactor disas_simd_indexed decode | 43 | target/arm: Add BT and BTYPE to tb->flags |
58 | target/arm: Refactor disas_simd_indexed size checks | 44 | exec: Add target-specific tlb bits to MemTxAttrs |
59 | target/arm: Decode aa64 armv8.1 scalar three same extra | 45 | target/arm: Cache the GP bit for a page in MemTxAttrs |
60 | target/arm: Decode aa64 armv8.1 three same extra | 46 | target/arm: Default handling of BTYPE during translation |
61 | target/arm: Decode aa64 armv8.1 scalar/vector x indexed element | 47 | target/arm: Reset btype for direct branches |
62 | target/arm: Decode aa32 armv8.1 three same | 48 | target/arm: Set btype for indirect branches |
63 | target/arm: Decode aa32 armv8.1 two reg and a scalar | 49 | target/arm: Enable BTI for -cpu max |
64 | target/arm: Enable ARM_FEATURE_V8_RDM | 50 | linux-user: Implement PR_PAC_RESET_KEYS |
65 | target/arm: Add ARM_FEATURE_V8_FCMA | 51 | tests/tcg/aarch64: Add pauth smoke test |
66 | target/arm: Decode aa64 armv8.3 fcadd | 52 | target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore |
67 | target/arm: Decode aa64 armv8.3 fcmla | 53 | target/arm: Clean TBI for data operations in the translator |
68 | target/arm: Decode aa32 armv8.3 3-same | 54 | target/arm: Enable TBI for user-only |
69 | target/arm: Decode aa32 armv8.3 2-reg-index | ||
70 | target/arm: Decode t32 simd 3reg and 2reg_scalar extension | ||
71 | target/arm: Enable ARM_FEATURE_V8_FCMA | ||
72 | 55 | ||
73 | hw/arm/Makefile.objs | 2 + | 56 | tests/tcg/aarch64/Makefile.target | 6 +- |
74 | hw/core/Makefile.objs | 1 + | 57 | include/exec/memattrs.h | 10 + |
75 | hw/misc/Makefile.objs | 4 + | 58 | linux-user/aarch64/target_syscall.h | 7 + |
76 | hw/timer/Makefile.objs | 1 + | 59 | target/arm/cpu.h | 27 +- |
77 | target/arm/Makefile.objs | 2 +- | 60 | target/arm/internals.h | 27 +- |
78 | include/hw/arm/armv7m.h | 5 + | 61 | target/arm/translate.h | 12 +- |
79 | include/hw/arm/iotkit.h | 109 ++++++ | 62 | gdbstub.c | 4 + |
80 | include/hw/arm/xlnx-zynqmp.h | 2 + | 63 | hw/arm/boot.c | 166 +++++++------ |
81 | include/hw/core/split-irq.h | 57 +++ | 64 | linux-user/syscall.c | 36 +++ |
82 | include/hw/irq.h | 4 +- | 65 | target/arm/cpu.c | 6 + |
83 | include/hw/loader.h | 12 +- | 66 | target/arm/cpu64.c | 4 + |
84 | include/hw/misc/iotkit-secctl.h | 103 ++++++ | 67 | target/arm/helper.c | 80 +++--- |
85 | include/hw/misc/mps2-fpgaio.h | 43 +++ | 68 | target/arm/translate-a64.c | 476 +++++++++++++++++++++++++----------- |
86 | include/hw/misc/tz-ppc.h | 101 ++++++ | 69 | tests/tcg/aarch64/pauth-1.c | 23 ++ |
87 | include/hw/misc/unimp.h | 10 + | 70 | 14 files changed, 623 insertions(+), 261 deletions(-) |
88 | include/hw/or-irq.h | 5 + | 71 | create mode 100644 tests/tcg/aarch64/pauth-1.c |
89 | include/hw/qdev-core.h | 30 +- | ||
90 | include/hw/timer/xlnx-zynqmp-rtc.h | 86 +++++ | ||
91 | target/arm/cpu.h | 8 + | ||
92 | target/arm/helper.h | 31 ++ | ||
93 | target/arm/idau.h | 61 ++++ | ||
94 | hw/arm/armv7m.c | 35 +- | ||
95 | hw/arm/boot.c | 119 ++++--- | ||
96 | hw/arm/iotkit.c | 598 +++++++++++++++++++++++++++++++ | ||
97 | hw/arm/mps2-tz.c | 503 ++++++++++++++++++++++++++ | ||
98 | hw/arm/xlnx-zynqmp.c | 14 + | ||
99 | hw/core/loader.c | 8 +- | ||
100 | hw/core/qdev.c | 8 +- | ||
101 | hw/core/split-irq.c | 89 +++++ | ||
102 | hw/misc/iotkit-secctl.c | 704 +++++++++++++++++++++++++++++++++++++ | ||
103 | hw/misc/mps2-fpgaio.c | 176 ++++++++++ | ||
104 | hw/misc/tz-ppc.c | 302 ++++++++++++++++ | ||
105 | hw/misc/unimp.c | 10 - | ||
106 | hw/timer/xlnx-zynqmp-rtc.c | 272 ++++++++++++++ | ||
107 | linux-user/elfload.c | 2 + | ||
108 | target/arm/cpu.c | 66 +++- | ||
109 | target/arm/cpu64.c | 2 + | ||
110 | target/arm/helper.c | 28 +- | ||
111 | target/arm/translate-a64.c | 514 +++++++++++++++++++++------ | ||
112 | target/arm/translate.c | 275 +++++++++++++-- | ||
113 | target/arm/vec_helper.c | 429 ++++++++++++++++++++++ | ||
114 | default-configs/arm-softmmu.mak | 5 + | ||
115 | hw/misc/trace-events | 24 ++ | ||
116 | hw/timer/trace-events | 3 + | ||
117 | scripts/decodetree.py | 5 +- | ||
118 | 45 files changed, 4668 insertions(+), 200 deletions(-) | ||
119 | create mode 100644 include/hw/arm/iotkit.h | ||
120 | create mode 100644 include/hw/core/split-irq.h | ||
121 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
122 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
123 | create mode 100644 include/hw/misc/tz-ppc.h | ||
124 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
125 | create mode 100644 target/arm/idau.h | ||
126 | create mode 100644 hw/arm/iotkit.c | ||
127 | create mode 100644 hw/arm/mps2-tz.c | ||
128 | create mode 100644 hw/core/split-irq.c | ||
129 | create mode 100644 hw/misc/iotkit-secctl.c | ||
130 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
131 | create mode 100644 hw/misc/tz-ppc.c | ||
132 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
133 | create mode 100644 target/arm/vec_helper.c | ||
134 | 72 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Initial commit of the ZynqMP RTC device. | ||
4 | |||
5 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/timer/Makefile.objs | 1 + | ||
10 | include/hw/timer/xlnx-zynqmp-rtc.h | 84 +++++++++++++++ | ||
11 | hw/timer/xlnx-zynqmp-rtc.c | 214 +++++++++++++++++++++++++++++++++++++ | ||
12 | 3 files changed, 299 insertions(+) | ||
13 | create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h | ||
14 | create mode 100644 hw/timer/xlnx-zynqmp-rtc.c | ||
15 | |||
16 | diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/timer/Makefile.objs | ||
19 | +++ b/hw/timer/Makefile.objs | ||
20 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_IMX) += imx_epit.o | ||
21 | common-obj-$(CONFIG_IMX) += imx_gpt.o | ||
22 | common-obj-$(CONFIG_LM32) += lm32_timer.o | ||
23 | common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o | ||
24 | +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o | ||
25 | |||
26 | obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o | ||
27 | obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o | ||
28 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
36 | + * | ||
37 | + * Copyright (c) 2017 Xilinx Inc. | ||
38 | + * | ||
39 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
40 | + * | ||
41 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
42 | + * of this software and associated documentation files (the "Software"), to deal | ||
43 | + * in the Software without restriction, including without limitation the rights | ||
44 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
45 | + * copies of the Software, and to permit persons to whom the Software is | ||
46 | + * furnished to do so, subject to the following conditions: | ||
47 | + * | ||
48 | + * The above copyright notice and this permission notice shall be included in | ||
49 | + * all copies or substantial portions of the Software. | ||
50 | + * | ||
51 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
52 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
53 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
54 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
55 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
56 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
57 | + * THE SOFTWARE. | ||
58 | + */ | ||
59 | + | ||
60 | +#include "hw/register.h" | ||
61 | + | ||
62 | +#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc" | ||
63 | + | ||
64 | +#define XLNX_ZYNQMP_RTC(obj) \ | ||
65 | + OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC) | ||
66 | + | ||
67 | +REG32(SET_TIME_WRITE, 0x0) | ||
68 | +REG32(SET_TIME_READ, 0x4) | ||
69 | +REG32(CALIB_WRITE, 0x8) | ||
70 | + FIELD(CALIB_WRITE, FRACTION_EN, 20, 1) | ||
71 | + FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4) | ||
72 | + FIELD(CALIB_WRITE, MAX_TICK, 0, 16) | ||
73 | +REG32(CALIB_READ, 0xc) | ||
74 | + FIELD(CALIB_READ, FRACTION_EN, 20, 1) | ||
75 | + FIELD(CALIB_READ, FRACTION_DATA, 16, 4) | ||
76 | + FIELD(CALIB_READ, MAX_TICK, 0, 16) | ||
77 | +REG32(CURRENT_TIME, 0x10) | ||
78 | +REG32(CURRENT_TICK, 0x14) | ||
79 | + FIELD(CURRENT_TICK, VALUE, 0, 16) | ||
80 | +REG32(ALARM, 0x18) | ||
81 | +REG32(RTC_INT_STATUS, 0x20) | ||
82 | + FIELD(RTC_INT_STATUS, ALARM, 1, 1) | ||
83 | + FIELD(RTC_INT_STATUS, SECONDS, 0, 1) | ||
84 | +REG32(RTC_INT_MASK, 0x24) | ||
85 | + FIELD(RTC_INT_MASK, ALARM, 1, 1) | ||
86 | + FIELD(RTC_INT_MASK, SECONDS, 0, 1) | ||
87 | +REG32(RTC_INT_EN, 0x28) | ||
88 | + FIELD(RTC_INT_EN, ALARM, 1, 1) | ||
89 | + FIELD(RTC_INT_EN, SECONDS, 0, 1) | ||
90 | +REG32(RTC_INT_DIS, 0x2c) | ||
91 | + FIELD(RTC_INT_DIS, ALARM, 1, 1) | ||
92 | + FIELD(RTC_INT_DIS, SECONDS, 0, 1) | ||
93 | +REG32(ADDR_ERROR, 0x30) | ||
94 | + FIELD(ADDR_ERROR, STATUS, 0, 1) | ||
95 | +REG32(ADDR_ERROR_INT_MASK, 0x34) | ||
96 | + FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1) | ||
97 | +REG32(ADDR_ERROR_INT_EN, 0x38) | ||
98 | + FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1) | ||
99 | +REG32(ADDR_ERROR_INT_DIS, 0x3c) | ||
100 | + FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1) | ||
101 | +REG32(CONTROL, 0x40) | ||
102 | + FIELD(CONTROL, BATTERY_DISABLE, 31, 1) | ||
103 | + FIELD(CONTROL, OSC_CNTRL, 24, 4) | ||
104 | + FIELD(CONTROL, SLVERR_ENABLE, 0, 1) | ||
105 | +REG32(SAFETY_CHK, 0x50) | ||
106 | + | ||
107 | +#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1) | ||
108 | + | ||
109 | +typedef struct XlnxZynqMPRTC { | ||
110 | + SysBusDevice parent_obj; | ||
111 | + MemoryRegion iomem; | ||
112 | + qemu_irq irq_rtc_int; | ||
113 | + qemu_irq irq_addr_error_int; | ||
114 | + | ||
115 | + uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
116 | + RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
117 | +} XlnxZynqMPRTC; | ||
118 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
119 | new file mode 100644 | ||
120 | index XXXXXXX..XXXXXXX | ||
121 | --- /dev/null | ||
122 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | ||
123 | @@ -XXX,XX +XXX,XX @@ | ||
124 | +/* | ||
125 | + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC). | ||
126 | + * | ||
127 | + * Copyright (c) 2017 Xilinx Inc. | ||
128 | + * | ||
129 | + * Written-by: Alistair Francis <alistair.francis@xilinx.com> | ||
130 | + * | ||
131 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
132 | + * of this software and associated documentation files (the "Software"), to deal | ||
133 | + * in the Software without restriction, including without limitation the rights | ||
134 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
135 | + * copies of the Software, and to permit persons to whom the Software is | ||
136 | + * furnished to do so, subject to the following conditions: | ||
137 | + * | ||
138 | + * The above copyright notice and this permission notice shall be included in | ||
139 | + * all copies or substantial portions of the Software. | ||
140 | + * | ||
141 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
142 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
143 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
144 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
145 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
146 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
147 | + * THE SOFTWARE. | ||
148 | + */ | ||
149 | + | ||
150 | +#include "qemu/osdep.h" | ||
151 | +#include "hw/sysbus.h" | ||
152 | +#include "hw/register.h" | ||
153 | +#include "qemu/bitops.h" | ||
154 | +#include "qemu/log.h" | ||
155 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
156 | + | ||
157 | +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
158 | +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0 | ||
159 | +#endif | ||
160 | + | ||
161 | +static void rtc_int_update_irq(XlnxZynqMPRTC *s) | ||
162 | +{ | ||
163 | + bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; | ||
164 | + qemu_set_irq(s->irq_rtc_int, pending); | ||
165 | +} | ||
166 | + | ||
167 | +static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
168 | +{ | ||
169 | + bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; | ||
170 | + qemu_set_irq(s->irq_addr_error_int, pending); | ||
171 | +} | ||
172 | + | ||
173 | +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
174 | +{ | ||
175 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
176 | + rtc_int_update_irq(s); | ||
177 | +} | ||
178 | + | ||
179 | +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
180 | +{ | ||
181 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
182 | + | ||
183 | + s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64; | ||
184 | + rtc_int_update_irq(s); | ||
185 | + return 0; | ||
186 | +} | ||
187 | + | ||
188 | +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
189 | +{ | ||
190 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
191 | + | ||
192 | + s->regs[R_RTC_INT_MASK] |= (uint32_t) val64; | ||
193 | + rtc_int_update_irq(s); | ||
194 | + return 0; | ||
195 | +} | ||
196 | + | ||
197 | +static void addr_error_postw(RegisterInfo *reg, uint64_t val64) | ||
198 | +{ | ||
199 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
200 | + addr_error_int_update_irq(s); | ||
201 | +} | ||
202 | + | ||
203 | +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64) | ||
204 | +{ | ||
205 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
206 | + | ||
207 | + s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64; | ||
208 | + addr_error_int_update_irq(s); | ||
209 | + return 0; | ||
210 | +} | ||
211 | + | ||
212 | +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
213 | +{ | ||
214 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
215 | + | ||
216 | + s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64; | ||
217 | + addr_error_int_update_irq(s); | ||
218 | + return 0; | ||
219 | +} | ||
220 | + | ||
221 | +static const RegisterAccessInfo rtc_regs_info[] = { | ||
222 | + { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
223 | + },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
224 | + .ro = 0xffffffff, | ||
225 | + },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
226 | + },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
227 | + .ro = 0x1fffff, | ||
228 | + },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
229 | + .ro = 0xffffffff, | ||
230 | + },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
231 | + .ro = 0xffff, | ||
232 | + },{ .name = "ALARM", .addr = A_ALARM, | ||
233 | + },{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS, | ||
234 | + .w1c = 0x3, | ||
235 | + .post_write = rtc_int_status_postw, | ||
236 | + },{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK, | ||
237 | + .reset = 0x3, | ||
238 | + .ro = 0x3, | ||
239 | + },{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN, | ||
240 | + .pre_write = rtc_int_en_prew, | ||
241 | + },{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS, | ||
242 | + .pre_write = rtc_int_dis_prew, | ||
243 | + },{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR, | ||
244 | + .w1c = 0x1, | ||
245 | + .post_write = addr_error_postw, | ||
246 | + },{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK, | ||
247 | + .reset = 0x1, | ||
248 | + .ro = 0x1, | ||
249 | + },{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN, | ||
250 | + .pre_write = addr_error_int_en_prew, | ||
251 | + },{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS, | ||
252 | + .pre_write = addr_error_int_dis_prew, | ||
253 | + },{ .name = "CONTROL", .addr = A_CONTROL, | ||
254 | + .reset = 0x1000000, | ||
255 | + .rsvd = 0x70fffffe, | ||
256 | + },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK, | ||
257 | + } | ||
258 | +}; | ||
259 | + | ||
260 | +static void rtc_reset(DeviceState *dev) | ||
261 | +{ | ||
262 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev); | ||
263 | + unsigned int i; | ||
264 | + | ||
265 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
266 | + register_reset(&s->regs_info[i]); | ||
267 | + } | ||
268 | + | ||
269 | + rtc_int_update_irq(s); | ||
270 | + addr_error_int_update_irq(s); | ||
271 | +} | ||
272 | + | ||
273 | +static const MemoryRegionOps rtc_ops = { | ||
274 | + .read = register_read_memory, | ||
275 | + .write = register_write_memory, | ||
276 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
277 | + .valid = { | ||
278 | + .min_access_size = 4, | ||
279 | + .max_access_size = 4, | ||
280 | + }, | ||
281 | +}; | ||
282 | + | ||
283 | +static void rtc_init(Object *obj) | ||
284 | +{ | ||
285 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
286 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
287 | + RegisterInfoArray *reg_array; | ||
288 | + | ||
289 | + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
290 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
291 | + reg_array = | ||
292 | + register_init_block32(DEVICE(obj), rtc_regs_info, | ||
293 | + ARRAY_SIZE(rtc_regs_info), | ||
294 | + s->regs_info, s->regs, | ||
295 | + &rtc_ops, | ||
296 | + XLNX_ZYNQMP_RTC_ERR_DEBUG, | ||
297 | + XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
298 | + memory_region_add_subregion(&s->iomem, | ||
299 | + 0x0, | ||
300 | + ®_array->mem); | ||
301 | + sysbus_init_mmio(sbd, &s->iomem); | ||
302 | + sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
303 | + sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
304 | +} | ||
305 | + | ||
306 | +static const VMStateDescription vmstate_rtc = { | ||
307 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
308 | + .version_id = 1, | ||
309 | + .minimum_version_id = 1, | ||
310 | + .fields = (VMStateField[]) { | ||
311 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
312 | + VMSTATE_END_OF_LIST(), | ||
313 | + } | ||
314 | +}; | ||
315 | + | ||
316 | +static void rtc_class_init(ObjectClass *klass, void *data) | ||
317 | +{ | ||
318 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
319 | + | ||
320 | + dc->reset = rtc_reset; | ||
321 | + dc->vmsd = &vmstate_rtc; | ||
322 | +} | ||
323 | + | ||
324 | +static const TypeInfo rtc_info = { | ||
325 | + .name = TYPE_XLNX_ZYNQMP_RTC, | ||
326 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
327 | + .instance_size = sizeof(XlnxZynqMPRTC), | ||
328 | + .class_init = rtc_class_init, | ||
329 | + .instance_init = rtc_init, | ||
330 | +}; | ||
331 | + | ||
332 | +static void rtc_register_types(void) | ||
333 | +{ | ||
334 | + type_register_static(&rtc_info); | ||
335 | +} | ||
336 | + | ||
337 | +type_init(rtc_register_types) | ||
338 | -- | ||
339 | 2.16.2 | ||
340 | |||
341 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Allow the guest to determine the time set from the QEMU command line. | ||
4 | |||
5 | This includes adding a trace event to debug the new time. | ||
6 | |||
7 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/timer/xlnx-zynqmp-rtc.h | 2 ++ | ||
13 | hw/timer/xlnx-zynqmp-rtc.c | 58 ++++++++++++++++++++++++++++++++++++++ | ||
14 | hw/timer/trace-events | 3 ++ | ||
15 | 3 files changed, 63 insertions(+) | ||
16 | |||
17 | diff --git a/include/hw/timer/xlnx-zynqmp-rtc.h b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/timer/xlnx-zynqmp-rtc.h | ||
20 | +++ b/include/hw/timer/xlnx-zynqmp-rtc.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPRTC { | ||
22 | qemu_irq irq_rtc_int; | ||
23 | qemu_irq irq_addr_error_int; | ||
24 | |||
25 | + uint32_t tick_offset; | ||
26 | + | ||
27 | uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX]; | ||
28 | RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX]; | ||
29 | } XlnxZynqMPRTC; | ||
30 | diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/timer/xlnx-zynqmp-rtc.c | ||
33 | +++ b/hw/timer/xlnx-zynqmp-rtc.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #include "hw/register.h" | ||
36 | #include "qemu/bitops.h" | ||
37 | #include "qemu/log.h" | ||
38 | +#include "hw/ptimer.h" | ||
39 | +#include "qemu/cutils.h" | ||
40 | +#include "sysemu/sysemu.h" | ||
41 | +#include "trace.h" | ||
42 | #include "hw/timer/xlnx-zynqmp-rtc.h" | ||
43 | |||
44 | #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG | ||
45 | @@ -XXX,XX +XXX,XX @@ static void addr_error_int_update_irq(XlnxZynqMPRTC *s) | ||
46 | qemu_set_irq(s->irq_addr_error_int, pending); | ||
47 | } | ||
48 | |||
49 | +static uint32_t rtc_get_count(XlnxZynqMPRTC *s) | ||
50 | +{ | ||
51 | + int64_t now = qemu_clock_get_ns(rtc_clock); | ||
52 | + return s->tick_offset + now / NANOSECONDS_PER_SECOND; | ||
53 | +} | ||
54 | + | ||
55 | +static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64) | ||
56 | +{ | ||
57 | + XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
58 | + | ||
59 | + return rtc_get_count(s); | ||
60 | +} | ||
61 | + | ||
62 | static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64) | ||
63 | { | ||
64 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); | ||
65 | @@ -XXX,XX +XXX,XX @@ static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64) | ||
66 | |||
67 | static const RegisterAccessInfo rtc_regs_info[] = { | ||
68 | { .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE, | ||
69 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
70 | },{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ, | ||
71 | .ro = 0xffffffff, | ||
72 | + .post_read = current_time_postr, | ||
73 | },{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE, | ||
74 | + .unimp = MAKE_64BIT_MASK(0, 32), | ||
75 | },{ .name = "CALIB_READ", .addr = A_CALIB_READ, | ||
76 | .ro = 0x1fffff, | ||
77 | },{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME, | ||
78 | .ro = 0xffffffff, | ||
79 | + .post_read = current_time_postr, | ||
80 | },{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK, | ||
81 | .ro = 0xffff, | ||
82 | },{ .name = "ALARM", .addr = A_ALARM, | ||
83 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
84 | XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj); | ||
85 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
86 | RegisterInfoArray *reg_array; | ||
87 | + struct tm current_tm; | ||
88 | |||
89 | memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC, | ||
90 | XLNX_ZYNQMP_RTC_R_MAX * 4); | ||
91 | @@ -XXX,XX +XXX,XX @@ static void rtc_init(Object *obj) | ||
92 | sysbus_init_mmio(sbd, &s->iomem); | ||
93 | sysbus_init_irq(sbd, &s->irq_rtc_int); | ||
94 | sysbus_init_irq(sbd, &s->irq_addr_error_int); | ||
95 | + | ||
96 | + qemu_get_timedate(¤t_tm, 0); | ||
97 | + s->tick_offset = mktimegm(¤t_tm) - | ||
98 | + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
99 | + | ||
100 | + trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon, | ||
101 | + current_tm.tm_mday, current_tm.tm_hour, | ||
102 | + current_tm.tm_min, current_tm.tm_sec); | ||
103 | +} | ||
104 | + | ||
105 | +static int rtc_pre_save(void *opaque) | ||
106 | +{ | ||
107 | + XlnxZynqMPRTC *s = opaque; | ||
108 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
109 | + | ||
110 | + /* Add the time at migration */ | ||
111 | + s->tick_offset = s->tick_offset + now; | ||
112 | + | ||
113 | + return 0; | ||
114 | +} | ||
115 | + | ||
116 | +static int rtc_post_load(void *opaque, int version_id) | ||
117 | +{ | ||
118 | + XlnxZynqMPRTC *s = opaque; | ||
119 | + int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; | ||
120 | + | ||
121 | + /* Subtract the time after migration. This combined with the pre_save | ||
122 | + * action results in us having subtracted the time that the guest was | ||
123 | + * stopped to the offset. | ||
124 | + */ | ||
125 | + s->tick_offset = s->tick_offset - now; | ||
126 | + | ||
127 | + return 0; | ||
128 | } | ||
129 | |||
130 | static const VMStateDescription vmstate_rtc = { | ||
131 | .name = TYPE_XLNX_ZYNQMP_RTC, | ||
132 | .version_id = 1, | ||
133 | .minimum_version_id = 1, | ||
134 | + .pre_save = rtc_pre_save, | ||
135 | + .post_load = rtc_post_load, | ||
136 | .fields = (VMStateField[]) { | ||
137 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX), | ||
138 | + VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC), | ||
139 | VMSTATE_END_OF_LIST(), | ||
140 | } | ||
141 | }; | ||
142 | diff --git a/hw/timer/trace-events b/hw/timer/trace-events | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/hw/timer/trace-events | ||
145 | +++ b/hw/timer/trace-events | ||
146 | @@ -XXX,XX +XXX,XX @@ systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr | ||
147 | cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
148 | cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
149 | cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" | ||
150 | + | ||
151 | +# hw/timer/xlnx-zynqmp-rtc.c | ||
152 | +xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" | ||
153 | -- | ||
154 | 2.16.2 | ||
155 | |||
156 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
2 | 1 | ||
3 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | ||
9 | hw/arm/xlnx-zynqmp.c | 14 ++++++++++++++ | ||
10 | 2 files changed, 16 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
15 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | #include "hw/dma/xlnx_dpdma.h" | ||
18 | #include "hw/display/xlnx_dp.h" | ||
19 | #include "hw/intc/xlnx-zynqmp-ipi.h" | ||
20 | +#include "hw/timer/xlnx-zynqmp-rtc.h" | ||
21 | |||
22 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | ||
23 | #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState { | ||
25 | XlnxDPState dp; | ||
26 | XlnxDPDMAState dpdma; | ||
27 | XlnxZynqMPIPI ipi; | ||
28 | + XlnxZynqMPRTC rtc; | ||
29 | |||
30 | char *boot_cpu; | ||
31 | ARMCPU *boot_cpu_ptr; | ||
32 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/xlnx-zynqmp.c | ||
35 | +++ b/hw/arm/xlnx-zynqmp.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #define IPI_ADDR 0xFF300000 | ||
38 | #define IPI_IRQ 64 | ||
39 | |||
40 | +#define RTC_ADDR 0xffa60000 | ||
41 | +#define RTC_IRQ 26 | ||
42 | + | ||
43 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | ||
44 | |||
45 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | ||
46 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | ||
47 | |||
48 | object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI); | ||
49 | qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default()); | ||
50 | + | ||
51 | + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC); | ||
52 | + qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default()); | ||
53 | } | ||
54 | |||
55 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
56 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
57 | } | ||
58 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | ||
59 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | ||
60 | + | ||
61 | + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | ||
62 | + if (err) { | ||
63 | + error_propagate(errp, err); | ||
64 | + return; | ||
65 | + } | ||
66 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | ||
67 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | ||
68 | } | ||
69 | |||
70 | static Property xlnx_zynqmp_props[] = { | ||
71 | -- | ||
72 | 2.16.2 | ||
73 | |||
74 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Also create field definitions for id_aa64pfr1 from ARMv8.5. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Message-id: 20190128223118.5255-2-richard.henderson@linaro.org |
5 | Message-id: 20180228193125.20577-14-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/cpu.h | 10 ++++++++++ |
9 | 1 file changed, 68 insertions(+) | 11 | 1 file changed, 10 insertions(+) |
10 | 12 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 15 | --- a/target/arm/cpu.h |
14 | +++ b/target/arm/translate.c | 16 | +++ b/target/arm/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 17 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, GIC, 24, 4) |
16 | return 0; | 18 | FIELD(ID_AA64PFR0, RAS, 28, 4) |
19 | FIELD(ID_AA64PFR0, SVE, 32, 4) | ||
20 | |||
21 | +FIELD(ID_AA64PFR1, BT, 0, 4) | ||
22 | +FIELD(ID_AA64PFR1, SBSS, 4, 4) | ||
23 | +FIELD(ID_AA64PFR1, MTE, 8, 4) | ||
24 | +FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | ||
25 | + | ||
26 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) | ||
27 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | ||
28 | FIELD(ID_AA64MMFR0, BIGEND, 8, 4) | ||
29 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) | ||
30 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; | ||
17 | } | 31 | } |
18 | 32 | ||
19 | +/* Advanced SIMD three registers of the same length extension. | 33 | +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) |
20 | + * 31 25 23 22 20 16 12 11 10 9 8 3 0 | ||
21 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
22 | + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
23 | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
24 | + */ | ||
25 | +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
26 | +{ | 34 | +{ |
27 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | 35 | + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; |
28 | + int rd, rn, rm, rot, size, opr_sz; | ||
29 | + TCGv_ptr fpst; | ||
30 | + bool q; | ||
31 | + | ||
32 | + q = extract32(insn, 6, 1); | ||
33 | + VFP_DREG_D(rd, insn); | ||
34 | + VFP_DREG_N(rn, insn); | ||
35 | + VFP_DREG_M(rm, insn); | ||
36 | + if ((rd | rn | rm) & q) { | ||
37 | + return 1; | ||
38 | + } | ||
39 | + | ||
40 | + if ((insn & 0xfe200f10) == 0xfc200800) { | ||
41 | + /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ | ||
42 | + size = extract32(insn, 20, 1); | ||
43 | + rot = extract32(insn, 23, 2); | ||
44 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
45 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
46 | + return 1; | ||
47 | + } | ||
48 | + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | ||
49 | + } else if ((insn & 0xfea00f10) == 0xfc800800) { | ||
50 | + /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | ||
51 | + size = extract32(insn, 20, 1); | ||
52 | + rot = extract32(insn, 24, 1); | ||
53 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
54 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
55 | + return 1; | ||
56 | + } | ||
57 | + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
58 | + } else { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + if (s->fp_excp_el) { | ||
63 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
64 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
65 | + return 0; | ||
66 | + } | ||
67 | + if (!s->vfp_enabled) { | ||
68 | + return 1; | ||
69 | + } | ||
70 | + | ||
71 | + opr_sz = (1 + q) * 8; | ||
72 | + fpst = get_fpstatus_ptr(1); | ||
73 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
74 | + vfp_reg_offset(1, rn), | ||
75 | + vfp_reg_offset(1, rm), fpst, | ||
76 | + opr_sz, opr_sz, rot, fn_gvec_ptr); | ||
77 | + tcg_temp_free_ptr(fpst); | ||
78 | + return 0; | ||
79 | +} | 36 | +} |
80 | + | 37 | + |
81 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 38 | /* |
82 | { | 39 | * Forward to the above feature tests given an ARMCPU pointer. |
83 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | 40 | */ |
84 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
85 | } | ||
86 | } | ||
87 | } | ||
88 | + } else if ((insn & 0x0e000a00) == 0x0c000800 | ||
89 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
90 | + if (disas_neon_insn_3same_ext(s, insn)) { | ||
91 | + goto illegal_op; | ||
92 | + } | ||
93 | + return; | ||
94 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
95 | /* Coprocessor double register transfer. */ | ||
96 | ARCH(5TE); | ||
97 | -- | 41 | -- |
98 | 2.16.2 | 42 | 2.20.1 |
99 | 43 | ||
100 | 44 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Not enabled anywhere yet. | 3 | Place this in its own field within ENV, as that will |
4 | make it easier to reset from within TCG generated code. | ||
4 | 5 | ||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 6 | With the change to pstate_read/write, exception entry |
7 | and return are automatically handled. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180228193125.20577-11-richard.henderson@linaro.org | 11 | Message-id: 20190128223118.5255-3-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 13 | --- |
10 | target/arm/cpu.h | 1 + | 14 | target/arm/cpu.h | 8 ++++++-- |
11 | linux-user/elfload.c | 1 + | 15 | target/arm/translate-a64.c | 3 +++ |
12 | 2 files changed, 2 insertions(+) | 16 | 2 files changed, 9 insertions(+), 2 deletions(-) |
13 | 17 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 20 | --- a/target/arm/cpu.h |
17 | +++ b/target/arm/cpu.h | 21 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { |
19 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | 23 | * semantics as for AArch32, as described in the comments on each field) |
20 | ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | 24 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 |
21 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | 25 | * DAIF (exception masks) are kept in env->daif |
22 | + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ | 26 | + * BTYPE is kept in env->btype |
23 | }; | 27 | * all other bits are stored in their correct places in env->pstate |
24 | 28 | */ | |
25 | static inline int arm_feature(CPUARMState *env, int feature) | 29 | uint32_t pstate; |
26 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { |
31 | uint32_t GE; /* cpsr[19:16] */ | ||
32 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ | ||
33 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ | ||
34 | + uint32_t btype; /* BTI branch type. spsr[11:10]. */ | ||
35 | uint64_t daif; /* exception masks, in the bits they are in PSTATE */ | ||
36 | |||
37 | uint64_t elr_el[4]; /* AArch64 exception link regs */ | ||
38 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
39 | #define PSTATE_I (1U << 7) | ||
40 | #define PSTATE_A (1U << 8) | ||
41 | #define PSTATE_D (1U << 9) | ||
42 | +#define PSTATE_BTYPE (3U << 10) | ||
43 | #define PSTATE_IL (1U << 20) | ||
44 | #define PSTATE_SS (1U << 21) | ||
45 | #define PSTATE_V (1U << 28) | ||
46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
47 | #define PSTATE_N (1U << 31) | ||
48 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | ||
49 | #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) | ||
50 | -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) | ||
51 | +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) | ||
52 | /* Mode values for AArch64 */ | ||
53 | #define PSTATE_MODE_EL3h 13 | ||
54 | #define PSTATE_MODE_EL3t 12 | ||
55 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t pstate_read(CPUARMState *env) | ||
56 | ZF = (env->ZF == 0); | ||
57 | return (env->NF & 0x80000000) | (ZF << 30) | ||
58 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | ||
59 | - | env->pstate | env->daif; | ||
60 | + | env->pstate | env->daif | (env->btype << 10); | ||
61 | } | ||
62 | |||
63 | static inline void pstate_write(CPUARMState *env, uint32_t val) | ||
64 | @@ -XXX,XX +XXX,XX @@ static inline void pstate_write(CPUARMState *env, uint32_t val) | ||
65 | env->CF = (val >> 29) & 1; | ||
66 | env->VF = (val << 3) & 0x80000000; | ||
67 | env->daif = val & PSTATE_DAIF; | ||
68 | + env->btype = (val >> 10) & 3; | ||
69 | env->pstate = val & ~CACHED_PSTATE_BITS; | ||
70 | } | ||
71 | |||
72 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 73 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/linux-user/elfload.c | 74 | --- a/target/arm/translate-a64.c |
29 | +++ b/linux-user/elfload.c | 75 | +++ b/target/arm/translate-a64.c |
30 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | 76 | @@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
31 | GET_FEATURE(ARM_FEATURE_V8_FP16, | 77 | el, |
32 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | 78 | psr & PSTATE_SP ? 'h' : 't'); |
33 | GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | 79 | |
34 | + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); | 80 | + if (cpu_isar_feature(aa64_bti, cpu)) { |
35 | #undef GET_FEATURE | 81 | + cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); |
36 | 82 | + } | |
37 | return hwcaps; | 83 | if (!(flags & CPU_DUMP_FPU)) { |
84 | cpu_fprintf(f, "\n"); | ||
85 | return; | ||
38 | -- | 86 | -- |
39 | 2.16.2 | 87 | 2.20.1 |
40 | 88 | ||
41 | 89 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Not enabled anywhere yet. | ||
4 | |||
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180228193125.20577-2-richard.henderson@linaro.org | 5 | Message-id: 20190128223118.5255-4-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 7 | --- |
11 | target/arm/cpu.h | 1 + | 8 | target/arm/cpu.h | 2 ++ |
12 | linux-user/elfload.c | 1 + | 9 | target/arm/translate.h | 4 ++++ |
13 | 2 files changed, 2 insertions(+) | 10 | target/arm/helper.c | 22 +++++++++++++++------- |
11 | target/arm/translate-a64.c | 2 ++ | ||
12 | 4 files changed, 23 insertions(+), 7 deletions(-) | ||
14 | 13 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/cpu.h |
18 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/cpu.h |
19 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 18 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, TBII, 0, 2) |
20 | ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ | 19 | FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) |
21 | ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ | 20 | FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) |
22 | ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ | 21 | FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) |
23 | + ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ | 22 | +FIELD(TBFLAG_A64, BT, 9, 1) |
24 | ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ | 23 | +FIELD(TBFLAG_A64, BTYPE, 10, 2) |
25 | }; | 24 | |
26 | 25 | static inline bool bswap_code(bool sctlr_b) | |
27 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 26 | { |
27 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/linux-user/elfload.c | 29 | --- a/target/arm/translate.h |
30 | +++ b/linux-user/elfload.c | 30 | +++ b/target/arm/translate.h |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | 31 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
32 | GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); | 32 | bool ss_same_el; |
33 | GET_FEATURE(ARM_FEATURE_V8_FP16, | 33 | /* True if v8.3-PAuth is active. */ |
34 | ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); | 34 | bool pauth_active; |
35 | + GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); | 35 | + /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ |
36 | #undef GET_FEATURE | 36 | + bool bt; |
37 | 37 | + /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ | |
38 | return hwcaps; | 38 | + uint8_t btype; |
39 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
40 | int c15_cpar; | ||
41 | /* TCG op of the current insn_start. */ | ||
42 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/helper.c | ||
45 | +++ b/target/arm/helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
47 | |||
48 | if (is_a64(env)) { | ||
49 | ARMCPU *cpu = arm_env_get_cpu(env); | ||
50 | + uint64_t sctlr; | ||
51 | |||
52 | *pc = env->pc; | ||
53 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); | ||
54 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
55 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | ||
56 | } | ||
57 | |||
58 | + if (current_el == 0) { | ||
59 | + /* FIXME: ARMv8.1-VHE S2 translation regime. */ | ||
60 | + sctlr = env->cp15.sctlr_el[1]; | ||
61 | + } else { | ||
62 | + sctlr = env->cp15.sctlr_el[current_el]; | ||
63 | + } | ||
64 | if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
65 | /* | ||
66 | * In order to save space in flags, we record only whether | ||
67 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
68 | * a nop, or "active" when some action must be performed. | ||
69 | * The decision of which action to take is left to a helper. | ||
70 | */ | ||
71 | - uint64_t sctlr; | ||
72 | - if (current_el == 0) { | ||
73 | - /* FIXME: ARMv8.1-VHE S2 translation regime. */ | ||
74 | - sctlr = env->cp15.sctlr_el[1]; | ||
75 | - } else { | ||
76 | - sctlr = env->cp15.sctlr_el[current_el]; | ||
77 | - } | ||
78 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | ||
79 | flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); | ||
80 | } | ||
81 | } | ||
82 | + | ||
83 | + if (cpu_isar_feature(aa64_bti, cpu)) { | ||
84 | + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | ||
85 | + if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | ||
86 | + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); | ||
87 | + } | ||
88 | + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); | ||
89 | + } | ||
90 | } else { | ||
91 | *pc = env->regs[15]; | ||
92 | flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); | ||
93 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/translate-a64.c | ||
96 | +++ b/target/arm/translate-a64.c | ||
97 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
98 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | ||
99 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | ||
100 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); | ||
101 | + dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); | ||
102 | + dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | ||
103 | dc->vec_len = 0; | ||
104 | dc->vec_stride = 0; | ||
105 | dc->cp_regs = arm_cpu->cp_regs; | ||
39 | -- | 106 | -- |
40 | 2.16.2 | 107 | 2.20.1 |
41 | 108 | ||
42 | 109 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Happily, the bits are in the same places compared to a32. | 3 | These bits can be used to cache target-specific data in cputlb |
4 | read from the page tables. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20180228193125.20577-16-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20190128223118.5255-5-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/translate.c | 14 +++++++++++++- | 11 | include/exec/memattrs.h | 10 ++++++++++ |
11 | 1 file changed, 13 insertions(+), 1 deletion(-) | 12 | 1 file changed, 10 insertions(+) |
12 | 13 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 16 | --- a/include/exec/memattrs.h |
16 | +++ b/target/arm/translate.c | 17 | +++ b/include/exec/memattrs.h |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 18 | @@ -XXX,XX +XXX,XX @@ typedef struct MemTxAttrs { |
18 | default_exception_el(s)); | 19 | unsigned int user:1; |
19 | break; | 20 | /* Requester ID (for MSI for example) */ |
20 | } | 21 | unsigned int requester_id:16; |
21 | - if (((insn >> 24) & 3) == 3) { | 22 | + /* |
22 | + if ((insn & 0xfe000a00) == 0xfc000800 | 23 | + * The following are target-specific page-table bits. These are not |
23 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 24 | + * related to actual memory transactions at all. However, this structure |
24 | + /* The Thumb2 and ARM encodings are identical. */ | 25 | + * is part of the tlb_fill interface, cached in the cputlb structure, |
25 | + if (disas_neon_insn_3same_ext(s, insn)) { | 26 | + * and has unused bits. These fields will be read by target-specific |
26 | + goto illegal_op; | 27 | + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. |
27 | + } | 28 | + */ |
28 | + } else if ((insn & 0xff000a00) == 0xfe000800 | 29 | + unsigned int target_tlb_bit0 : 1; |
29 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | 30 | + unsigned int target_tlb_bit1 : 1; |
30 | + /* The Thumb2 and ARM encodings are identical. */ | 31 | + unsigned int target_tlb_bit2 : 1; |
31 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | 32 | } MemTxAttrs; |
32 | + goto illegal_op; | 33 | |
33 | + } | 34 | /* Bus masters which don't specify any attributes will get this, |
34 | + } else if (((insn >> 24) & 3) == 3) { | ||
35 | /* Translate into the equivalent ARM encoding. */ | ||
36 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | ||
37 | if (disas_neon_data_insn(s, insn)) { | ||
38 | -- | 35 | -- |
39 | 2.16.2 | 36 | 2.20.1 |
40 | 37 | ||
41 | 38 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Allow the translate subroutines to return false for invalid insns. | 3 | Caching the bit means that we will not have to re-walk the |
4 | 4 | page tables to look up the bit during translation. | |
5 | At present we can of course invoke an invalid insn exception from within | ||
6 | the translate subroutine, but in the short term this consolidates code. | ||
7 | In the long term it would allow the decodetree language to support | ||
8 | overlapping patterns for ISA extensions. | ||
9 | 5 | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20180227232618.2908-1-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20190128223118.5255-6-richard.henderson@linaro.org | ||
9 | [PMM: no need to OR in guarded bit status] | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 11 | --- |
15 | scripts/decodetree.py | 5 ++--- | 12 | target/arm/helper.c | 6 ++++++ |
16 | 1 file changed, 2 insertions(+), 3 deletions(-) | 13 | 1 file changed, 6 insertions(+) |
17 | 14 | ||
18 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
19 | index XXXXXXX..XXXXXXX 100755 | 16 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/scripts/decodetree.py | 17 | --- a/target/arm/helper.c |
21 | +++ b/scripts/decodetree.py | 18 | +++ b/target/arm/helper.c |
22 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | 19 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
23 | global translate_prefix | 20 | bool ttbr1_valid; |
24 | output('typedef ', self.base.base.struct_name(), | 21 | uint64_t descaddrmask; |
25 | ' arg_', self.name, ';\n') | 22 | bool aarch64 = arm_el_is_aa64(env, el); |
26 | - output(translate_scope, 'void ', translate_prefix, '_', self.name, | 23 | + bool guarded = false; |
27 | + output(translate_scope, 'bool ', translate_prefix, '_', self.name, | 24 | |
28 | '(DisasContext *ctx, arg_', self.name, | 25 | /* TODO: |
29 | ' *a, ', insntype, ' insn);\n') | 26 | * This code does not handle the different format TCR for VTCR_EL2. |
30 | 27 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | |
31 | @@ -XXX,XX +XXX,XX @@ class Pattern(General): | 28 | } |
32 | output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n') | 29 | /* Merge in attributes from table descriptors */ |
33 | for n, f in self.fields.items(): | 30 | attrs |= nstable << 3; /* NS */ |
34 | output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') | 31 | + guarded = extract64(descriptor, 50, 1); /* GP */ |
35 | - output(ind, translate_prefix, '_', self.name, | 32 | if (param.hpd) { |
36 | + output(ind, 'return ', translate_prefix, '_', self.name, | 33 | /* HPD disables all the table attributes except NSTable. */ |
37 | '(ctx, &u.f_', arg, ', insn);\n') | 34 | break; |
38 | - output(ind, 'return true;\n') | 35 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
39 | # end Pattern | 36 | */ |
40 | 37 | txattrs->secure = false; | |
41 | 38 | } | |
39 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ | ||
40 | + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | ||
41 | + txattrs->target_tlb_bit0 = true; | ||
42 | + } | ||
43 | |||
44 | if (cacheattrs != NULL) { | ||
45 | if (mmu_idx == ARMMMUIdx_S2NS) { | ||
42 | -- | 46 | -- |
43 | 2.16.2 | 47 | 2.20.1 |
44 | 48 | ||
45 | 49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add a function load_ramdisk_as() which behaves like the existing | ||
2 | load_ramdisk() but allows the caller to specify the AddressSpace | ||
3 | to use. This matches the pattern we have already for various | ||
4 | other loader functions. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/hw/loader.h | 12 +++++++++++- | ||
12 | hw/core/loader.c | 8 +++++++- | ||
13 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/loader.h b/include/hw/loader.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/loader.h | ||
18 | +++ b/include/hw/loader.h | ||
19 | @@ -XXX,XX +XXX,XX @@ int load_uimage(const char *filename, hwaddr *ep, | ||
20 | void *translate_opaque); | ||
21 | |||
22 | /** | ||
23 | - * load_ramdisk: | ||
24 | + * load_ramdisk_as: | ||
25 | * @filename: Path to the ramdisk image | ||
26 | * @addr: Memory address to load the ramdisk to | ||
27 | * @max_sz: Maximum allowed ramdisk size (for non-u-boot ramdisks) | ||
28 | + * @as: The AddressSpace to load the ELF to. The value of address_space_memory | ||
29 | + * is used if nothing is supplied here. | ||
30 | * | ||
31 | * Load a ramdisk image with U-Boot header to the specified memory | ||
32 | * address. | ||
33 | * | ||
34 | * Returns the size of the loaded image on success, -1 otherwise. | ||
35 | */ | ||
36 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
37 | + AddressSpace *as); | ||
38 | + | ||
39 | +/** | ||
40 | + * load_ramdisk: | ||
41 | + * Same as load_ramdisk_as(), but doesn't allow the caller to specify | ||
42 | + * an AddressSpace. | ||
43 | + */ | ||
44 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz); | ||
45 | |||
46 | ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen); | ||
47 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/core/loader.c | ||
50 | +++ b/hw/core/loader.c | ||
51 | @@ -XXX,XX +XXX,XX @@ int load_uimage_as(const char *filename, hwaddr *ep, hwaddr *loadaddr, | ||
52 | |||
53 | /* Load a ramdisk. */ | ||
54 | int load_ramdisk(const char *filename, hwaddr addr, uint64_t max_sz) | ||
55 | +{ | ||
56 | + return load_ramdisk_as(filename, addr, max_sz, NULL); | ||
57 | +} | ||
58 | + | ||
59 | +int load_ramdisk_as(const char *filename, hwaddr addr, uint64_t max_sz, | ||
60 | + AddressSpace *as) | ||
61 | { | ||
62 | return load_uboot_image(filename, NULL, &addr, NULL, IH_TYPE_RAMDISK, | ||
63 | - NULL, NULL, NULL); | ||
64 | + NULL, NULL, as); | ||
65 | } | ||
66 | |||
67 | /* Load a gzip-compressed kernel to a dynamically allocated buffer. */ | ||
68 | -- | ||
69 | 2.16.2 | ||
70 | |||
71 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | The branch target exception for guarded pages has high priority, |
4 | and only 8 instructions are valid for that case. Perform this | ||
5 | check before doing any other decode. | ||
6 | |||
7 | Clear BTYPE after all insns that neither set BTYPE nor exit via | ||
8 | exception (DISAS_NORETURN). | ||
9 | |||
10 | Not yet handled are insns that exit via DISAS_NORETURN for some | ||
11 | other reason, like direct branches. | ||
12 | |||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180228193125.20577-7-richard.henderson@linaro.org | 15 | Message-id: 20190128223118.5255-7-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 17 | --- |
8 | target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ | 18 | target/arm/internals.h | 6 ++ |
9 | 1 file changed, 29 insertions(+) | 19 | target/arm/translate.h | 9 ++- |
10 | 20 | target/arm/translate-a64.c | 139 +++++++++++++++++++++++++++++++++++++ | |
21 | 3 files changed, 152 insertions(+), 2 deletions(-) | ||
22 | |||
23 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/arm/internals.h | ||
26 | +++ b/target/arm/internals.h | ||
27 | @@ -XXX,XX +XXX,XX @@ enum arm_exception_class { | ||
28 | EC_FPIDTRAP = 0x08, | ||
29 | EC_PACTRAP = 0x09, | ||
30 | EC_CP14RRTTRAP = 0x0c, | ||
31 | + EC_BTITRAP = 0x0d, | ||
32 | EC_ILLEGALSTATE = 0x0e, | ||
33 | EC_AA32_SVC = 0x11, | ||
34 | EC_AA32_HVC = 0x12, | ||
35 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pactrap(void) | ||
36 | return EC_PACTRAP << ARM_EL_EC_SHIFT; | ||
37 | } | ||
38 | |||
39 | +static inline uint32_t syn_btitrap(int btype) | ||
40 | +{ | ||
41 | + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; | ||
42 | +} | ||
43 | + | ||
44 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | ||
45 | { | ||
46 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | ||
47 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/translate.h | ||
50 | +++ b/target/arm/translate.h | ||
51 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
52 | bool pauth_active; | ||
53 | /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ | ||
54 | bool bt; | ||
55 | - /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ | ||
56 | - uint8_t btype; | ||
57 | + /* | ||
58 | + * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. | ||
59 | + * < 0, set by the current instruction. | ||
60 | + */ | ||
61 | + int8_t btype; | ||
62 | + /* True if this page is guarded. */ | ||
63 | + bool guarded_page; | ||
64 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
65 | int c15_cpar; | ||
66 | /* TCG op of the current insn_start. */ | ||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 67 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
12 | index XXXXXXX..XXXXXXX 100644 | 68 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-a64.c | 69 | --- a/target/arm/translate-a64.c |
14 | +++ b/target/arm/translate-a64.c | 70 | +++ b/target/arm/translate-a64.c |
15 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 71 | @@ -XXX,XX +XXX,XX @@ static inline int get_a64_user_mem_index(DisasContext *s) |
16 | case 0x19: /* FMULX */ | 72 | return arm_to_core_mmu_idx(useridx); |
17 | is_fp = true; | 73 | } |
18 | break; | 74 | |
19 | + case 0x1d: /* SQRDMLAH */ | 75 | +static void reset_btype(DisasContext *s) |
20 | + case 0x1f: /* SQRDMLSH */ | 76 | +{ |
21 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | 77 | + if (s->btype != 0) { |
22 | + unallocated_encoding(s); | 78 | + TCGv_i32 zero = tcg_const_i32(0); |
23 | + return; | 79 | + tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); |
80 | + tcg_temp_free_i32(zero); | ||
81 | + s->btype = 0; | ||
82 | + } | ||
83 | +} | ||
84 | + | ||
85 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | ||
86 | fprintf_function cpu_fprintf, int flags) | ||
87 | { | ||
88 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | ||
89 | } | ||
90 | } | ||
91 | |||
92 | +/** | ||
93 | + * is_guarded_page: | ||
94 | + * @env: The cpu environment | ||
95 | + * @s: The DisasContext | ||
96 | + * | ||
97 | + * Return true if the page is guarded. | ||
98 | + */ | ||
99 | +static bool is_guarded_page(CPUARMState *env, DisasContext *s) | ||
100 | +{ | ||
101 | +#ifdef CONFIG_USER_ONLY | ||
102 | + return false; /* FIXME */ | ||
103 | +#else | ||
104 | + uint64_t addr = s->base.pc_first; | ||
105 | + int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); | ||
106 | + unsigned int index = tlb_index(env, mmu_idx, addr); | ||
107 | + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | ||
108 | + | ||
109 | + /* | ||
110 | + * We test this immediately after reading an insn, which means | ||
111 | + * that any normal page must be in the TLB. The only exception | ||
112 | + * would be for executing from flash or device memory, which | ||
113 | + * does not retain the TLB entry. | ||
114 | + * | ||
115 | + * FIXME: Assume false for those, for now. We could use | ||
116 | + * arm_cpu_get_phys_page_attrs_debug to re-read the page | ||
117 | + * table entry even for that case. | ||
118 | + */ | ||
119 | + return (tlb_hit(entry->addr_code, addr) && | ||
120 | + env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); | ||
121 | +#endif | ||
122 | +} | ||
123 | + | ||
124 | +/** | ||
125 | + * btype_destination_ok: | ||
126 | + * @insn: The instruction at the branch destination | ||
127 | + * @bt: SCTLR_ELx.BT | ||
128 | + * @btype: PSTATE.BTYPE, and is non-zero | ||
129 | + * | ||
130 | + * On a guarded page, there are a limited number of insns | ||
131 | + * that may be present at the branch target: | ||
132 | + * - branch target identifiers, | ||
133 | + * - paciasp, pacibsp, | ||
134 | + * - BRK insn | ||
135 | + * - HLT insn | ||
136 | + * Anything else causes a Branch Target Exception. | ||
137 | + * | ||
138 | + * Return true if the branch is compatible, false to raise BTITRAP. | ||
139 | + */ | ||
140 | +static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | ||
141 | +{ | ||
142 | + if ((insn & 0xfffff01fu) == 0xd503201fu) { | ||
143 | + /* HINT space */ | ||
144 | + switch (extract32(insn, 5, 7)) { | ||
145 | + case 0b011001: /* PACIASP */ | ||
146 | + case 0b011011: /* PACIBSP */ | ||
147 | + /* | ||
148 | + * If SCTLR_ELx.BT, then PACI*SP are not compatible | ||
149 | + * with btype == 3. Otherwise all btype are ok. | ||
150 | + */ | ||
151 | + return !bt || btype != 3; | ||
152 | + case 0b100000: /* BTI */ | ||
153 | + /* Not compatible with any btype. */ | ||
154 | + return false; | ||
155 | + case 0b100010: /* BTI c */ | ||
156 | + /* Not compatible with btype == 3 */ | ||
157 | + return btype != 3; | ||
158 | + case 0b100100: /* BTI j */ | ||
159 | + /* Not compatible with btype == 2 */ | ||
160 | + return btype != 2; | ||
161 | + case 0b100110: /* BTI jc */ | ||
162 | + /* Compatible with any btype. */ | ||
163 | + return true; | ||
24 | + } | 164 | + } |
25 | + break; | 165 | + } else { |
26 | default: | 166 | + switch (insn & 0xffe0001fu) { |
167 | + case 0xd4200000u: /* BRK */ | ||
168 | + case 0xd4400000u: /* HLT */ | ||
169 | + /* Give priority to the breakpoint exception. */ | ||
170 | + return true; | ||
171 | + } | ||
172 | + } | ||
173 | + return false; | ||
174 | +} | ||
175 | + | ||
176 | /* C3.1 A64 instruction index by encoding */ | ||
177 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) | ||
178 | { | ||
179 | @@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) | ||
180 | |||
181 | s->fp_access_checked = false; | ||
182 | |||
183 | + if (dc_isar_feature(aa64_bti, s)) { | ||
184 | + if (s->base.num_insns == 1) { | ||
185 | + /* | ||
186 | + * At the first insn of the TB, compute s->guarded_page. | ||
187 | + * We delayed computing this until successfully reading | ||
188 | + * the first insn of the TB, above. This (mostly) ensures | ||
189 | + * that the softmmu tlb entry has been populated, and the | ||
190 | + * page table GP bit is available. | ||
191 | + * | ||
192 | + * Note that we need to compute this even if btype == 0, | ||
193 | + * because this value is used for BR instructions later | ||
194 | + * where ENV is not available. | ||
195 | + */ | ||
196 | + s->guarded_page = is_guarded_page(env, s); | ||
197 | + | ||
198 | + /* First insn can have btype set to non-zero. */ | ||
199 | + tcg_debug_assert(s->btype >= 0); | ||
200 | + | ||
201 | + /* | ||
202 | + * Note that the Branch Target Exception has fairly high | ||
203 | + * priority -- below debugging exceptions but above most | ||
204 | + * everything else. This allows us to handle this now | ||
205 | + * instead of waiting until the insn is otherwise decoded. | ||
206 | + */ | ||
207 | + if (s->btype != 0 | ||
208 | + && s->guarded_page | ||
209 | + && !btype_destination_ok(insn, s->bt, s->btype)) { | ||
210 | + gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype), | ||
211 | + default_exception_el(s)); | ||
212 | + return; | ||
213 | + } | ||
214 | + } else { | ||
215 | + /* Not the first insn: btype must be 0. */ | ||
216 | + tcg_debug_assert(s->btype == 0); | ||
217 | + } | ||
218 | + } | ||
219 | + | ||
220 | switch (extract32(insn, 25, 4)) { | ||
221 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ | ||
27 | unallocated_encoding(s); | 222 | unallocated_encoding(s); |
28 | return; | 223 | @@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
29 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 224 | |
30 | tcg_op, tcg_idx); | 225 | /* if we allocated any temporaries, free them here */ |
31 | } | 226 | free_tmp_a64(s); |
32 | break; | 227 | + |
33 | + case 0x1d: /* SQRDMLAH */ | 228 | + /* |
34 | + read_vec_element_i32(s, tcg_res, rd, pass, | 229 | + * After execution of most insns, btype is reset to 0. |
35 | + is_scalar ? size : MO_32); | 230 | + * Note that we set btype == -1 when the insn sets btype. |
36 | + if (size == 1) { | 231 | + */ |
37 | + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, | 232 | + if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { |
38 | + tcg_op, tcg_idx, tcg_res); | 233 | + reset_btype(s); |
39 | + } else { | 234 | + } |
40 | + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, | 235 | } |
41 | + tcg_op, tcg_idx, tcg_res); | 236 | |
42 | + } | 237 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
43 | + break; | ||
44 | + case 0x1f: /* SQRDMLSH */ | ||
45 | + read_vec_element_i32(s, tcg_res, rd, pass, | ||
46 | + is_scalar ? size : MO_32); | ||
47 | + if (size == 1) { | ||
48 | + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, | ||
49 | + tcg_op, tcg_idx, tcg_res); | ||
50 | + } else { | ||
51 | + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, | ||
52 | + tcg_op, tcg_idx, tcg_res); | ||
53 | + } | ||
54 | + break; | ||
55 | default: | ||
56 | g_assert_not_reached(); | ||
57 | } | ||
58 | -- | 238 | -- |
59 | 2.16.2 | 239 | 2.20.1 |
60 | 240 | ||
61 | 241 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The integer size check was already outside of the opcode switch; | 3 | This is all of the non-exception cases of DISAS_NORETURN. |
4 | move the floating-point size check outside as well. Unify the | ||
5 | size vs index adjustment between fp and integer paths. | ||
6 | 4 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20180228193125.20577-4-richard.henderson@linaro.org | 7 | Message-id: 20190128223118.5255-8-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 9 | --- |
12 | target/arm/translate-a64.c | 65 +++++++++++++++++++++++----------------------- | 10 | target/arm/translate-a64.c | 6 ++++++ |
13 | 1 file changed, 32 insertions(+), 33 deletions(-) | 11 | 1 file changed, 6 insertions(+) |
14 | 12 | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 15 | --- a/target/arm/translate-a64.c |
18 | +++ b/target/arm/translate-a64.c | 16 | +++ b/target/arm/translate-a64.c |
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 17 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
20 | case 0x05: /* FMLS */ | 18 | } |
21 | case 0x09: /* FMUL */ | 19 | |
22 | case 0x19: /* FMULX */ | 20 | /* B Branch / BL Branch with link */ |
23 | - if (size == 1) { | 21 | + reset_btype(s); |
24 | - unallocated_encoding(s); | 22 | gen_goto_tb(s, 0, addr); |
25 | - return; | 23 | } |
26 | - } | 24 | |
27 | is_fp = true; | 25 | @@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
28 | break; | 26 | tcg_cmp = read_cpu_reg(s, rt, sf); |
27 | label_match = gen_new_label(); | ||
28 | |||
29 | + reset_btype(s); | ||
30 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | ||
31 | tcg_cmp, 0, label_match); | ||
32 | |||
33 | @@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) | ||
34 | tcg_cmp = tcg_temp_new_i64(); | ||
35 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | ||
36 | label_match = gen_new_label(); | ||
37 | + | ||
38 | + reset_btype(s); | ||
39 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | ||
40 | tcg_cmp, 0, label_match); | ||
41 | tcg_temp_free_i64(tcg_cmp); | ||
42 | @@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) | ||
43 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | ||
44 | cond = extract32(insn, 0, 4); | ||
45 | |||
46 | + reset_btype(s); | ||
47 | if (cond < 0x0e) { | ||
48 | /* genuinely conditional branches */ | ||
49 | TCGLabel *label_match = gen_new_label(); | ||
50 | @@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn, | ||
51 | * a self-modified code correctly and also to take | ||
52 | * any pending interrupts immediately. | ||
53 | */ | ||
54 | + reset_btype(s); | ||
55 | gen_goto_tb(s, 0, s->pc); | ||
56 | return; | ||
29 | default: | 57 | default: |
30 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
31 | if (is_fp) { | ||
32 | /* convert insn encoded size to TCGMemOp size */ | ||
33 | switch (size) { | ||
34 | - case 2: /* single precision */ | ||
35 | - size = MO_32; | ||
36 | - index = h << 1 | l; | ||
37 | - rm |= (m << 4); | ||
38 | - break; | ||
39 | - case 3: /* double precision */ | ||
40 | - size = MO_64; | ||
41 | - if (l || !is_q) { | ||
42 | + case 0: /* half-precision */ | ||
43 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | - index = h; | ||
48 | - rm |= (m << 4); | ||
49 | - break; | ||
50 | - case 0: /* half precision */ | ||
51 | size = MO_16; | ||
52 | - index = h << 2 | l << 1 | m; | ||
53 | - is_fp16 = true; | ||
54 | - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
55 | - break; | ||
56 | - } | ||
57 | - /* fallthru */ | ||
58 | - default: /* unallocated */ | ||
59 | - unallocated_encoding(s); | ||
60 | - return; | ||
61 | - } | ||
62 | - } else { | ||
63 | - switch (size) { | ||
64 | - case 1: | ||
65 | - index = h << 2 | l << 1 | m; | ||
66 | break; | ||
67 | - case 2: | ||
68 | - index = h << 1 | l; | ||
69 | - rm |= (m << 4); | ||
70 | + case MO_32: /* single precision */ | ||
71 | + case MO_64: /* double precision */ | ||
72 | break; | ||
73 | default: | ||
74 | unallocated_encoding(s); | ||
75 | return; | ||
76 | } | ||
77 | + } else { | ||
78 | + switch (size) { | ||
79 | + case MO_8: | ||
80 | + case MO_64: | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + } | ||
85 | + | ||
86 | + /* Given TCGMemOp size, adjust register and indexing. */ | ||
87 | + switch (size) { | ||
88 | + case MO_16: | ||
89 | + index = h << 2 | l << 1 | m; | ||
90 | + break; | ||
91 | + case MO_32: | ||
92 | + index = h << 1 | l; | ||
93 | + rm |= m << 4; | ||
94 | + break; | ||
95 | + case MO_64: | ||
96 | + if (l || !is_q) { | ||
97 | + unallocated_encoding(s); | ||
98 | + return; | ||
99 | + } | ||
100 | + index = h; | ||
101 | + rm |= m << 4; | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | } | ||
106 | |||
107 | if (!fp_access_check(s)) { | ||
108 | -- | 58 | -- |
109 | 2.16.2 | 59 | 2.20.1 |
110 | 60 | ||
111 | 61 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Message-id: 20180228193125.20577-13-richard.henderson@linaro.org | 5 | Message-id: 20190128223118.5255-9-richard.henderson@linaro.org |
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | [PMM: renamed e1/e2/e3/e4 to use the same naming as the version | ||
7 | of the pseudocode in the Arm ARM] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | 7 | --- |
10 | target/arm/helper.h | 11 ++++ | 8 | target/arm/translate-a64.c | 37 ++++++++++++++++++++++++++++++++++++- |
11 | target/arm/translate-a64.c | 94 +++++++++++++++++++++++++--- | 9 | 1 file changed, 36 insertions(+), 1 deletion(-) |
12 | target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 246 insertions(+), 8 deletions(-) | ||
14 | 10 | ||
15 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.h | ||
18 | +++ b/target/arm/helper.h | ||
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | ||
20 | DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | ||
21 | void, ptr, ptr, ptr, ptr, i32) | ||
22 | |||
23 | +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, | ||
24 | + void, ptr, ptr, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, | ||
26 | + void, ptr, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, | ||
28 | + void, ptr, ptr, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, | ||
30 | + void, ptr, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, | ||
32 | + void, ptr, ptr, ptr, ptr, i32) | ||
33 | + | ||
34 | #ifdef TARGET_AARCH64 | ||
35 | #include "helper-a64.h" | ||
36 | #endif | ||
37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
38 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/translate-a64.c | 13 | --- a/target/arm/translate-a64.c |
40 | +++ b/target/arm/translate-a64.c | 14 | +++ b/target/arm/translate-a64.c |
41 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | 15 | @@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s) |
16 | } | ||
17 | } | ||
18 | |||
19 | +static void set_btype(DisasContext *s, int val) | ||
20 | +{ | ||
21 | + TCGv_i32 tcg_val; | ||
22 | + | ||
23 | + /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | ||
24 | + tcg_debug_assert(val >= 1 && val <= 3); | ||
25 | + | ||
26 | + tcg_val = tcg_const_i32(val); | ||
27 | + tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | ||
28 | + tcg_temp_free_i32(tcg_val); | ||
29 | + s->btype = -1; | ||
30 | +} | ||
31 | + | ||
32 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | ||
33 | fprintf_function cpu_fprintf, int flags) | ||
34 | { | ||
35 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
36 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
37 | { | ||
38 | unsigned int opc, op2, op3, rn, op4; | ||
39 | + unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ | ||
40 | TCGv_i64 dst; | ||
41 | TCGv_i64 modifier; | ||
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
44 | case 0: /* BR */ | ||
45 | case 1: /* BLR */ | ||
46 | case 2: /* RET */ | ||
47 | + btype_mod = opc; | ||
48 | switch (op3) { | ||
49 | case 0: | ||
50 | /* BR, BLR, RET */ | ||
51 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
52 | default: | ||
53 | goto do_unallocated; | ||
42 | } | 54 | } |
43 | feature = ARM_FEATURE_V8_RDM; | 55 | - |
44 | break; | 56 | gen_a64_set_pc(s, dst); |
45 | + case 0x8: /* FCMLA, #0 */ | 57 | /* BLR also needs to load return address */ |
46 | + case 0x9: /* FCMLA, #90 */ | 58 | if (opc == 1) { |
47 | + case 0xa: /* FCMLA, #180 */ | 59 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
48 | + case 0xb: /* FCMLA, #270 */ | 60 | if ((op3 & ~1) != 2) { |
49 | case 0xc: /* FCADD, #90 */ | 61 | goto do_unallocated; |
50 | case 0xe: /* FCADD, #270 */ | ||
51 | if (size == 0 | ||
52 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
53 | } | 62 | } |
54 | return; | 63 | + btype_mod = opc & 1; |
55 | 64 | if (s->pauth_active) { | |
56 | + case 0x8: /* FCMLA, #0 */ | 65 | dst = new_tmp_a64(s); |
57 | + case 0x9: /* FCMLA, #90 */ | 66 | modifier = cpu_reg_sp(s, op4); |
58 | + case 0xa: /* FCMLA, #180 */ | 67 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
59 | + case 0xb: /* FCMLA, #270 */ | ||
60 | + rot = extract32(opcode, 0, 2); | ||
61 | + switch (size) { | ||
62 | + case 1: | ||
63 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, | ||
64 | + gen_helper_gvec_fcmlah); | ||
65 | + break; | ||
66 | + case 2: | ||
67 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
68 | + gen_helper_gvec_fcmlas); | ||
69 | + break; | ||
70 | + case 3: | ||
71 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, | ||
72 | + gen_helper_gvec_fcmlad); | ||
73 | + break; | ||
74 | + default: | ||
75 | + g_assert_not_reached(); | ||
76 | + } | ||
77 | + return; | ||
78 | + | ||
79 | case 0xc: /* FCADD, #90 */ | ||
80 | case 0xe: /* FCADD, #270 */ | ||
81 | rot = extract32(opcode, 1, 1); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
83 | int rn = extract32(insn, 5, 5); | ||
84 | int rd = extract32(insn, 0, 5); | ||
85 | bool is_long = false; | ||
86 | - bool is_fp = false; | ||
87 | + int is_fp = 0; | ||
88 | bool is_fp16 = false; | ||
89 | int index; | ||
90 | TCGv_ptr fpst; | ||
91 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
92 | case 0x05: /* FMLS */ | ||
93 | case 0x09: /* FMUL */ | ||
94 | case 0x19: /* FMULX */ | ||
95 | - is_fp = true; | ||
96 | + is_fp = 1; | ||
97 | break; | ||
98 | case 0x1d: /* SQRDMLAH */ | ||
99 | case 0x1f: /* SQRDMLSH */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
101 | return; | ||
102 | } | ||
103 | break; | ||
104 | + case 0x11: /* FCMLA #0 */ | ||
105 | + case 0x13: /* FCMLA #90 */ | ||
106 | + case 0x15: /* FCMLA #180 */ | ||
107 | + case 0x17: /* FCMLA #270 */ | ||
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { | ||
109 | + unallocated_encoding(s); | ||
110 | + return; | ||
111 | + } | ||
112 | + is_fp = 2; | ||
113 | + break; | ||
114 | default: | ||
115 | unallocated_encoding(s); | ||
116 | return; | 68 | return; |
117 | } | 69 | } |
118 | 70 | ||
119 | - if (is_fp) { | 71 | + switch (btype_mod) { |
120 | + switch (is_fp) { | 72 | + case 0: /* BR */ |
121 | + case 1: /* normal fp */ | 73 | + if (dc_isar_feature(aa64_bti, s)) { |
122 | /* convert insn encoded size to TCGMemOp size */ | 74 | + /* BR to {x16,x17} or !guard -> 1, else 3. */ |
123 | switch (size) { | 75 | + set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); |
124 | case 0: /* half-precision */ | ||
125 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
126 | - unallocated_encoding(s); | ||
127 | - return; | ||
128 | - } | ||
129 | size = MO_16; | ||
130 | + is_fp16 = true; | ||
131 | break; | ||
132 | case MO_32: /* single precision */ | ||
133 | case MO_64: /* double precision */ | ||
134 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
135 | unallocated_encoding(s); | ||
136 | return; | ||
137 | } | ||
138 | - } else { | ||
139 | + break; | ||
140 | + | ||
141 | + case 2: /* complex fp */ | ||
142 | + /* Each indexable element is a complex pair. */ | ||
143 | + size <<= 1; | ||
144 | + switch (size) { | ||
145 | + case MO_32: | ||
146 | + if (h && !is_q) { | ||
147 | + unallocated_encoding(s); | ||
148 | + return; | ||
149 | + } | ||
150 | + is_fp16 = true; | ||
151 | + break; | ||
152 | + case MO_64: | ||
153 | + break; | ||
154 | + default: | ||
155 | + unallocated_encoding(s); | ||
156 | + return; | ||
157 | + } | 76 | + } |
158 | + break; | 77 | + break; |
159 | + | 78 | + |
160 | + default: /* integer */ | 79 | + case 1: /* BLR */ |
161 | switch (size) { | 80 | + if (dc_isar_feature(aa64_bti, s)) { |
162 | case MO_8: | 81 | + /* BLR sets BTYPE to 2, regardless of source guarded page. */ |
163 | case MO_64: | 82 | + set_btype(s, 2); |
164 | unallocated_encoding(s); | 83 | + } |
165 | return; | 84 | + break; |
166 | } | 85 | + |
86 | + default: /* RET or none of the above. */ | ||
87 | + /* BTYPE will be set to 0 by normal end-of-insn processing. */ | ||
167 | + break; | 88 | + break; |
168 | + } | 89 | + } |
169 | + if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
170 | + unallocated_encoding(s); | ||
171 | + return; | ||
172 | } | ||
173 | |||
174 | /* Given TCGMemOp size, adjust register and indexing. */ | ||
175 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
176 | fpst = NULL; | ||
177 | } | ||
178 | |||
179 | + switch (16 * u + opcode) { | ||
180 | + case 0x11: /* FCMLA #0 */ | ||
181 | + case 0x13: /* FCMLA #90 */ | ||
182 | + case 0x15: /* FCMLA #180 */ | ||
183 | + case 0x17: /* FCMLA #270 */ | ||
184 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | ||
185 | + vec_full_reg_offset(s, rn), | ||
186 | + vec_reg_offset(s, rm, index, size), fpst, | ||
187 | + is_q ? 16 : 8, vec_full_reg_size(s), | ||
188 | + extract32(insn, 13, 2), /* rot */ | ||
189 | + size == MO_64 | ||
190 | + ? gen_helper_gvec_fcmlas_idx | ||
191 | + : gen_helper_gvec_fcmlah_idx); | ||
192 | + tcg_temp_free_ptr(fpst); | ||
193 | + return; | ||
194 | + } | ||
195 | + | 90 | + |
196 | if (size == 3) { | 91 | s->base.is_jmp = DISAS_JUMP; |
197 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | ||
198 | int pass; | ||
199 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/target/arm/vec_helper.c | ||
202 | +++ b/target/arm/vec_helper.c | ||
203 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
204 | } | ||
205 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
206 | } | 92 | } |
207 | + | 93 | |
208 | +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, | ||
209 | + void *vfpst, uint32_t desc) | ||
210 | +{ | ||
211 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
212 | + float16 *d = vd; | ||
213 | + float16 *n = vn; | ||
214 | + float16 *m = vm; | ||
215 | + float_status *fpst = vfpst; | ||
216 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
217 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
218 | + uint32_t neg_real = flip ^ neg_imag; | ||
219 | + uintptr_t i; | ||
220 | + | ||
221 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
222 | + neg_real <<= 15; | ||
223 | + neg_imag <<= 15; | ||
224 | + | ||
225 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
226 | + float16 e2 = n[H2(i + flip)]; | ||
227 | + float16 e1 = m[H2(i + flip)] ^ neg_real; | ||
228 | + float16 e4 = e2; | ||
229 | + float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; | ||
230 | + | ||
231 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
232 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
233 | + } | ||
234 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
235 | +} | ||
236 | + | ||
237 | +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, | ||
238 | + void *vfpst, uint32_t desc) | ||
239 | +{ | ||
240 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
241 | + float16 *d = vd; | ||
242 | + float16 *n = vn; | ||
243 | + float16 *m = vm; | ||
244 | + float_status *fpst = vfpst; | ||
245 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
246 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
247 | + uint32_t neg_real = flip ^ neg_imag; | ||
248 | + uintptr_t i; | ||
249 | + float16 e1 = m[H2(flip)]; | ||
250 | + float16 e3 = m[H2(1 - flip)]; | ||
251 | + | ||
252 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
253 | + neg_real <<= 15; | ||
254 | + neg_imag <<= 15; | ||
255 | + e1 ^= neg_real; | ||
256 | + e3 ^= neg_imag; | ||
257 | + | ||
258 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
259 | + float16 e2 = n[H2(i + flip)]; | ||
260 | + float16 e4 = e2; | ||
261 | + | ||
262 | + d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); | ||
263 | + d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); | ||
264 | + } | ||
265 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
266 | +} | ||
267 | + | ||
268 | +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, | ||
269 | + void *vfpst, uint32_t desc) | ||
270 | +{ | ||
271 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
272 | + float32 *d = vd; | ||
273 | + float32 *n = vn; | ||
274 | + float32 *m = vm; | ||
275 | + float_status *fpst = vfpst; | ||
276 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
277 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
278 | + uint32_t neg_real = flip ^ neg_imag; | ||
279 | + uintptr_t i; | ||
280 | + | ||
281 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
282 | + neg_real <<= 31; | ||
283 | + neg_imag <<= 31; | ||
284 | + | ||
285 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
286 | + float32 e2 = n[H4(i + flip)]; | ||
287 | + float32 e1 = m[H4(i + flip)] ^ neg_real; | ||
288 | + float32 e4 = e2; | ||
289 | + float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; | ||
290 | + | ||
291 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
292 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
293 | + } | ||
294 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
295 | +} | ||
296 | + | ||
297 | +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, | ||
298 | + void *vfpst, uint32_t desc) | ||
299 | +{ | ||
300 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
301 | + float32 *d = vd; | ||
302 | + float32 *n = vn; | ||
303 | + float32 *m = vm; | ||
304 | + float_status *fpst = vfpst; | ||
305 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
306 | + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
307 | + uint32_t neg_real = flip ^ neg_imag; | ||
308 | + uintptr_t i; | ||
309 | + float32 e1 = m[H4(flip)]; | ||
310 | + float32 e3 = m[H4(1 - flip)]; | ||
311 | + | ||
312 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
313 | + neg_real <<= 31; | ||
314 | + neg_imag <<= 31; | ||
315 | + e1 ^= neg_real; | ||
316 | + e3 ^= neg_imag; | ||
317 | + | ||
318 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
319 | + float32 e2 = n[H4(i + flip)]; | ||
320 | + float32 e4 = e2; | ||
321 | + | ||
322 | + d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); | ||
323 | + d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); | ||
324 | + } | ||
325 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
326 | +} | ||
327 | + | ||
328 | +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, | ||
329 | + void *vfpst, uint32_t desc) | ||
330 | +{ | ||
331 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
332 | + float64 *d = vd; | ||
333 | + float64 *n = vn; | ||
334 | + float64 *m = vm; | ||
335 | + float_status *fpst = vfpst; | ||
336 | + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
337 | + uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); | ||
338 | + uint64_t neg_real = flip ^ neg_imag; | ||
339 | + uintptr_t i; | ||
340 | + | ||
341 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
342 | + neg_real <<= 63; | ||
343 | + neg_imag <<= 63; | ||
344 | + | ||
345 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
346 | + float64 e2 = n[i + flip]; | ||
347 | + float64 e1 = m[i + flip] ^ neg_real; | ||
348 | + float64 e4 = e2; | ||
349 | + float64 e3 = m[i + 1 - flip] ^ neg_imag; | ||
350 | + | ||
351 | + d[i] = float64_muladd(e2, e1, d[i], 0, fpst); | ||
352 | + d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); | ||
353 | + } | ||
354 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
355 | +} | ||
356 | -- | 94 | -- |
357 | 2.16.2 | 95 | 2.20.1 |
358 | 96 | ||
359 | 97 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Message-id: 20190128223118.5255-11-richard.henderson@linaro.org |
7 | Message-id: 20180228193125.20577-17-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 7 | --- |
10 | target/arm/cpu.c | 1 + | 8 | target/arm/cpu64.c | 4 ++++ |
11 | target/arm/cpu64.c | 1 + | 9 | 1 file changed, 4 insertions(+) |
12 | 2 files changed, 2 insertions(+) | ||
13 | 10 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | ||
19 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
20 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
21 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | ||
23 | cpu->midr = 0xffffffff; | ||
24 | } | ||
25 | #endif | ||
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 11 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
27 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/cpu64.c | 13 | --- a/target/arm/cpu64.c |
29 | +++ b/target/arm/cpu64.c | 14 | +++ b/target/arm/cpu64.c |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 15 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
31 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 16 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); |
32 | set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 17 | cpu->isar.id_aa64pfr0 = t; |
33 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | 18 | |
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); | 19 | + t = cpu->isar.id_aa64pfr1; |
35 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 20 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); |
36 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 21 | + cpu->isar.id_aa64pfr1 = t; |
37 | } | 22 | + |
23 | t = cpu->isar.id_aa64mmfr1; | ||
24 | t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | ||
25 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | ||
38 | -- | 26 | -- |
39 | 2.16.2 | 27 | 2.20.1 |
40 | 28 | ||
41 | 29 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180228193125.20577-8-richard.henderson@linaro.org | 5 | Message-id: 20190201195404.30486-2-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++----------- | 8 | linux-user/aarch64/target_syscall.h | 7 ++++++ |
9 | 1 file changed, 67 insertions(+), 19 deletions(-) | 9 | linux-user/syscall.c | 36 +++++++++++++++++++++++++++++ |
10 | 2 files changed, 43 insertions(+) | ||
10 | 11 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 12 | diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 14 | --- a/linux-user/aarch64/target_syscall.h |
14 | +++ b/target/arm/translate.c | 15 | +++ b/linux-user/aarch64/target_syscall.h |
15 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ struct target_pt_regs { |
16 | #include "disas/disas.h" | 17 | #define TARGET_PR_SVE_SET_VL 50 |
17 | #include "exec/exec-all.h" | 18 | #define TARGET_PR_SVE_GET_VL 51 |
18 | #include "tcg-op.h" | 19 | |
19 | +#include "tcg-op-gvec.h" | 20 | +#define TARGET_PR_PAC_RESET_KEYS 54 |
20 | #include "qemu/log.h" | 21 | +# define TARGET_PR_PAC_APIAKEY (1 << 0) |
21 | #include "qemu/bitops.h" | 22 | +# define TARGET_PR_PAC_APIBKEY (1 << 1) |
22 | #include "arm_ldst.h" | 23 | +# define TARGET_PR_PAC_APDAKEY (1 << 2) |
23 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_narrow_op(int op, int u, int size, | 24 | +# define TARGET_PR_PAC_APDBKEY (1 << 3) |
24 | #define NEON_3R_VPMAX 20 | 25 | +# define TARGET_PR_PAC_APGAKEY (1 << 4) |
25 | #define NEON_3R_VPMIN 21 | ||
26 | #define NEON_3R_VQDMULH_VQRDMULH 22 | ||
27 | -#define NEON_3R_VPADD 23 | ||
28 | +#define NEON_3R_VPADD_VQRDMLAH 23 | ||
29 | #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ | ||
30 | -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ | ||
31 | +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ | ||
32 | #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ | ||
33 | #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ | ||
34 | #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ | ||
35 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_3r_sizes[] = { | ||
36 | [NEON_3R_VPMAX] = 0x7, | ||
37 | [NEON_3R_VPMIN] = 0x7, | ||
38 | [NEON_3R_VQDMULH_VQRDMULH] = 0x6, | ||
39 | - [NEON_3R_VPADD] = 0x7, | ||
40 | + [NEON_3R_VPADD_VQRDMLAH] = 0x7, | ||
41 | [NEON_3R_SHA] = 0xf, /* size field encodes op type */ | ||
42 | - [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */ | ||
43 | + [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ | ||
44 | [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ | ||
45 | [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ | ||
46 | [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ | ||
47 | @@ -XXX,XX +XXX,XX @@ static const uint8_t neon_2rm_sizes[] = { | ||
48 | [NEON_2RM_VCVT_UF] = 0x4, | ||
49 | }; | ||
50 | |||
51 | + | 26 | + |
52 | +/* Expand v8.1 simd helper. */ | 27 | void arm_init_pauth_key(ARMPACKey *key); |
53 | +static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, | 28 | |
54 | + int q, int rd, int rn, int rm) | 29 | #endif /* AARCH64_TARGET_SYSCALL_H */ |
55 | +{ | 30 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c |
56 | + if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | 31 | index XXXXXXX..XXXXXXX 100644 |
57 | + int opr_sz = (1 + q) * 8; | 32 | --- a/linux-user/syscall.c |
58 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | 33 | +++ b/linux-user/syscall.c |
59 | + vfp_reg_offset(1, rn), | 34 | @@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, |
60 | + vfp_reg_offset(1, rm), cpu_env, | ||
61 | + opr_sz, opr_sz, 0, fn); | ||
62 | + return 0; | ||
63 | + } | ||
64 | + return 1; | ||
65 | +} | ||
66 | + | ||
67 | /* Translate a NEON data processing instruction. Return nonzero if the | ||
68 | instruction is invalid. | ||
69 | We process data in a mixture of 32-bit and 64-bit chunks. | ||
70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
71 | if (q && ((rd | rn | rm) & 1)) { | ||
72 | return 1; | ||
73 | } | ||
74 | - /* | ||
75 | - * The SHA-1/SHA-256 3-register instructions require special treatment | ||
76 | - * here, as their size field is overloaded as an op type selector, and | ||
77 | - * they all consume their input in a single pass. | ||
78 | - */ | ||
79 | - if (op == NEON_3R_SHA) { | ||
80 | + switch (op) { | ||
81 | + case NEON_3R_SHA: | ||
82 | + /* The SHA-1/SHA-256 3-register instructions require special | ||
83 | + * treatment here, as their size field is overloaded as an | ||
84 | + * op type selector, and they all consume their input in a | ||
85 | + * single pass. | ||
86 | + */ | ||
87 | if (!q) { | ||
88 | return 1; | ||
89 | } | ||
90 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
91 | tcg_temp_free_ptr(ptr2); | ||
92 | tcg_temp_free_ptr(ptr3); | ||
93 | return 0; | ||
94 | + | ||
95 | + case NEON_3R_VPADD_VQRDMLAH: | ||
96 | + if (!u) { | ||
97 | + break; /* VPADD */ | ||
98 | + } | ||
99 | + /* VQRDMLAH */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16, | ||
103 | + q, rd, rn, rm); | ||
104 | + case 2: | ||
105 | + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32, | ||
106 | + q, rd, rn, rm); | ||
107 | + } | ||
108 | + return 1; | ||
109 | + | ||
110 | + case NEON_3R_VFM_VQRDMLSH: | ||
111 | + if (!u) { | ||
112 | + /* VFM, VFMS */ | ||
113 | + if (size == 1) { | ||
114 | + return 1; | ||
115 | + } | ||
116 | + break; | ||
117 | + } | ||
118 | + /* VQRDMLSH */ | ||
119 | + switch (size) { | ||
120 | + case 1: | ||
121 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16, | ||
122 | + q, rd, rn, rm); | ||
123 | + case 2: | ||
124 | + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32, | ||
125 | + q, rd, rn, rm); | ||
126 | + } | ||
127 | + return 1; | ||
128 | } | ||
129 | if (size == 3 && op != NEON_3R_LOGIC) { | ||
130 | /* 64-bit element instructions. */ | ||
131 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
132 | rm = rtmp; | ||
133 | } | ||
134 | break; | ||
135 | - case NEON_3R_VPADD: | ||
136 | - if (u) { | ||
137 | - return 1; | ||
138 | - } | ||
139 | - /* Fall through */ | ||
140 | + case NEON_3R_VPADD_VQRDMLAH: | ||
141 | case NEON_3R_VPMAX: | ||
142 | case NEON_3R_VPMIN: | ||
143 | pairwise = 1; | ||
144 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
145 | return 1; | ||
146 | } | ||
147 | break; | ||
148 | - case NEON_3R_VFM: | ||
149 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { | ||
150 | + case NEON_3R_VFM_VQRDMLSH: | ||
151 | + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { | ||
152 | return 1; | ||
153 | } | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
156 | } | 35 | } |
157 | } | 36 | } |
158 | break; | 37 | return ret; |
159 | - case NEON_3R_VPADD: | 38 | + case TARGET_PR_PAC_RESET_KEYS: |
160 | + case NEON_3R_VPADD_VQRDMLAH: | 39 | + { |
161 | switch (size) { | 40 | + CPUARMState *env = cpu_env; |
162 | case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; | 41 | + ARMCPU *cpu = arm_env_get_cpu(env); |
163 | case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; | 42 | + |
164 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 43 | + if (arg3 || arg4 || arg5) { |
165 | } | 44 | + return -TARGET_EINVAL; |
166 | } | 45 | + } |
167 | break; | 46 | + if (cpu_isar_feature(aa64_pauth, cpu)) { |
168 | - case NEON_3R_VFM: | 47 | + int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY | |
169 | + case NEON_3R_VFM_VQRDMLSH: | 48 | + TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY | |
170 | { | 49 | + TARGET_PR_PAC_APGAKEY); |
171 | /* VFMA, VFMS: fused multiply-add */ | 50 | + if (arg2 == 0) { |
172 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | 51 | + arg2 = all; |
52 | + } else if (arg2 & ~all) { | ||
53 | + return -TARGET_EINVAL; | ||
54 | + } | ||
55 | + if (arg2 & TARGET_PR_PAC_APIAKEY) { | ||
56 | + arm_init_pauth_key(&env->apia_key); | ||
57 | + } | ||
58 | + if (arg2 & TARGET_PR_PAC_APIBKEY) { | ||
59 | + arm_init_pauth_key(&env->apib_key); | ||
60 | + } | ||
61 | + if (arg2 & TARGET_PR_PAC_APDAKEY) { | ||
62 | + arm_init_pauth_key(&env->apda_key); | ||
63 | + } | ||
64 | + if (arg2 & TARGET_PR_PAC_APDBKEY) { | ||
65 | + arm_init_pauth_key(&env->apdb_key); | ||
66 | + } | ||
67 | + if (arg2 & TARGET_PR_PAC_APGAKEY) { | ||
68 | + arm_init_pauth_key(&env->apga_key); | ||
69 | + } | ||
70 | + return 0; | ||
71 | + } | ||
72 | + } | ||
73 | + return -TARGET_EINVAL; | ||
74 | #endif /* AARCH64 */ | ||
75 | case PR_GET_SECCOMP: | ||
76 | case PR_SET_SECCOMP: | ||
173 | -- | 77 | -- |
174 | 2.16.2 | 78 | 2.20.1 |
175 | 79 | ||
176 | 80 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180228193125.20577-5-richard.henderson@linaro.org | 5 | Message-id: 20190201195404.30486-3-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | target/arm/Makefile.objs | 2 +- | 8 | tests/tcg/aarch64/Makefile.target | 6 +++++- |
9 | target/arm/helper.h | 4 ++ | 9 | tests/tcg/aarch64/pauth-1.c | 23 +++++++++++++++++++++++ |
10 | target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++ | 10 | 2 files changed, 28 insertions(+), 1 deletion(-) |
11 | target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ | 11 | create mode 100644 tests/tcg/aarch64/pauth-1.c |
12 | 4 files changed, 198 insertions(+), 1 deletion(-) | ||
13 | create mode 100644 target/arm/vec_helper.c | ||
14 | 12 | ||
15 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | 13 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target |
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/Makefile.objs | 15 | --- a/tests/tcg/aarch64/Makefile.target |
18 | +++ b/target/arm/Makefile.objs | 16 | +++ b/tests/tcg/aarch64/Makefile.target |
19 | @@ -XXX,XX +XXX,XX @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o | 17 | @@ -XXX,XX +XXX,XX @@ VPATH += $(AARCH64_SRC) |
20 | obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o | 18 | # we don't build any of the ARM tests |
21 | obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o | 19 | AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) |
22 | obj-y += translate.o op_helper.o helper.o cpu.o | 20 | AARCH64_TESTS+=fcvt |
23 | -obj-y += neon_helper.o iwmmxt_helper.o | 21 | -TESTS:=$(AARCH64_TESTS) |
24 | +obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o | 22 | |
25 | obj-y += gdbstub.o | 23 | fcvt: LDFLAGS+=-lm |
26 | obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o | 24 | |
27 | obj-y += crypto_helper.o | 25 | run-fcvt: fcvt |
28 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 26 | $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") |
29 | index XXXXXXX..XXXXXXX 100644 | 27 | $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) |
30 | --- a/target/arm/helper.h | ||
31 | +++ b/target/arm/helper.h | ||
32 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) | ||
33 | |||
34 | DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) | ||
36 | +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) | ||
37 | +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) | ||
38 | DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) | ||
39 | DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) | ||
40 | +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) | ||
41 | +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) | ||
42 | |||
43 | DEF_HELPER_1(neon_narrow_u8, i32, i64) | ||
44 | DEF_HELPER_1(neon_narrow_u16, i32, i64) | ||
45 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-a64.c | ||
48 | +++ b/target/arm/translate-a64.c | ||
49 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | ||
50 | tcg_temp_free_ptr(fpst); | ||
51 | } | ||
52 | |||
53 | +/* AdvSIMD scalar three same extra | ||
54 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
55 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
56 | + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
57 | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ | ||
58 | + */ | ||
59 | +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, | ||
60 | + uint32_t insn) | ||
61 | +{ | ||
62 | + int rd = extract32(insn, 0, 5); | ||
63 | + int rn = extract32(insn, 5, 5); | ||
64 | + int opcode = extract32(insn, 11, 4); | ||
65 | + int rm = extract32(insn, 16, 5); | ||
66 | + int size = extract32(insn, 22, 2); | ||
67 | + bool u = extract32(insn, 29, 1); | ||
68 | + TCGv_i32 ele1, ele2, ele3; | ||
69 | + TCGv_i64 res; | ||
70 | + int feature; | ||
71 | + | 28 | + |
72 | + switch (u * 16 + opcode) { | 29 | +AARCH64_TESTS += pauth-1 |
73 | + case 0x10: /* SQRDMLAH (vector) */ | 30 | +run-pauth-%: QEMU += -cpu max |
74 | + case 0x11: /* SQRDMLSH (vector) */ | ||
75 | + if (size != 1 && size != 2) { | ||
76 | + unallocated_encoding(s); | ||
77 | + return; | ||
78 | + } | ||
79 | + feature = ARM_FEATURE_V8_RDM; | ||
80 | + break; | ||
81 | + default: | ||
82 | + unallocated_encoding(s); | ||
83 | + return; | ||
84 | + } | ||
85 | + if (!arm_dc_feature(s, feature)) { | ||
86 | + unallocated_encoding(s); | ||
87 | + return; | ||
88 | + } | ||
89 | + if (!fp_access_check(s)) { | ||
90 | + return; | ||
91 | + } | ||
92 | + | 31 | + |
93 | + /* Do a single operation on the lowest element in the vector. | 32 | +TESTS:=$(AARCH64_TESTS) |
94 | + * We use the standard Neon helpers and rely on 0 OP 0 == 0 | 33 | diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c |
95 | + * with no side effects for all these operations. | ||
96 | + * OPTME: special-purpose helpers would avoid doing some | ||
97 | + * unnecessary work in the helper for the 16 bit cases. | ||
98 | + */ | ||
99 | + ele1 = tcg_temp_new_i32(); | ||
100 | + ele2 = tcg_temp_new_i32(); | ||
101 | + ele3 = tcg_temp_new_i32(); | ||
102 | + | ||
103 | + read_vec_element_i32(s, ele1, rn, 0, size); | ||
104 | + read_vec_element_i32(s, ele2, rm, 0, size); | ||
105 | + read_vec_element_i32(s, ele3, rd, 0, size); | ||
106 | + | ||
107 | + switch (opcode) { | ||
108 | + case 0x0: /* SQRDMLAH */ | ||
109 | + if (size == 1) { | ||
110 | + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
111 | + } else { | ||
112 | + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
113 | + } | ||
114 | + break; | ||
115 | + case 0x1: /* SQRDMLSH */ | ||
116 | + if (size == 1) { | ||
117 | + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); | ||
118 | + } else { | ||
119 | + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); | ||
120 | + } | ||
121 | + break; | ||
122 | + default: | ||
123 | + g_assert_not_reached(); | ||
124 | + } | ||
125 | + tcg_temp_free_i32(ele1); | ||
126 | + tcg_temp_free_i32(ele2); | ||
127 | + | ||
128 | + res = tcg_temp_new_i64(); | ||
129 | + tcg_gen_extu_i32_i64(res, ele3); | ||
130 | + tcg_temp_free_i32(ele3); | ||
131 | + | ||
132 | + write_fp_dreg(s, rd, res); | ||
133 | + tcg_temp_free_i64(res); | ||
134 | +} | ||
135 | + | ||
136 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, | ||
137 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, | ||
138 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | ||
139 | @@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = { | ||
140 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | ||
141 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | ||
142 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | ||
143 | + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, | ||
144 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | ||
145 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | ||
146 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | ||
147 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
148 | new file mode 100644 | 34 | new file mode 100644 |
149 | index XXXXXXX..XXXXXXX | 35 | index XXXXXXX..XXXXXXX |
150 | --- /dev/null | 36 | --- /dev/null |
151 | +++ b/target/arm/vec_helper.c | 37 | +++ b/tests/tcg/aarch64/pauth-1.c |
152 | @@ -XXX,XX +XXX,XX @@ | 38 | @@ -XXX,XX +XXX,XX @@ |
153 | +/* | 39 | +#include <assert.h> |
154 | + * ARM AdvSIMD / SVE Vector Operations | 40 | +#include <sys/prctl.h> |
155 | + * | ||
156 | + * Copyright (c) 2018 Linaro | ||
157 | + * | ||
158 | + * This library is free software; you can redistribute it and/or | ||
159 | + * modify it under the terms of the GNU Lesser General Public | ||
160 | + * License as published by the Free Software Foundation; either | ||
161 | + * version 2 of the License, or (at your option) any later version. | ||
162 | + * | ||
163 | + * This library is distributed in the hope that it will be useful, | ||
164 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
165 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
166 | + * Lesser General Public License for more details. | ||
167 | + * | ||
168 | + * You should have received a copy of the GNU Lesser General Public | ||
169 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
170 | + */ | ||
171 | + | 41 | + |
172 | +#include "qemu/osdep.h" | 42 | +asm(".arch armv8.4-a"); |
173 | +#include "cpu.h" | ||
174 | +#include "exec/exec-all.h" | ||
175 | +#include "exec/helper-proto.h" | ||
176 | +#include "tcg/tcg-gvec-desc.h" | ||
177 | + | 43 | + |
44 | +#ifndef PR_PAC_RESET_KEYS | ||
45 | +#define PR_PAC_RESET_KEYS 54 | ||
46 | +#define PR_PAC_APDAKEY (1 << 2) | ||
47 | +#endif | ||
178 | + | 48 | + |
179 | +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | 49 | +int main() |
50 | +{ | ||
51 | + int x; | ||
52 | + void *p0 = &x, *p1, *p2; | ||
180 | + | 53 | + |
181 | +/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | 54 | + asm volatile("pacdza %0" : "=r"(p1) : "0"(p0)); |
182 | +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | 55 | + prctl(PR_PAC_RESET_KEYS, PR_PAC_APDAKEY, 0, 0, 0); |
183 | + int16_t src2, int16_t src3) | 56 | + asm volatile("pacdza %0" : "=r"(p2) : "0"(p0)); |
184 | +{ | ||
185 | + /* Simplify: | ||
186 | + * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
187 | + * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 | ||
188 | + */ | ||
189 | + int32_t ret = (int32_t)src1 * src2; | ||
190 | + ret = ((int32_t)src3 << 15) + ret + (1 << 14); | ||
191 | + ret >>= 15; | ||
192 | + if (ret != (int16_t)ret) { | ||
193 | + SET_QC(); | ||
194 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
195 | + } | ||
196 | + return ret; | ||
197 | +} | ||
198 | + | 57 | + |
199 | +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | 58 | + assert(p1 != p0); |
200 | + uint32_t src2, uint32_t src3) | 59 | + assert(p1 != p2); |
201 | +{ | 60 | + return 0; |
202 | + uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3); | ||
203 | + uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
204 | + return deposit32(e1, 16, 16, e2); | ||
205 | +} | ||
206 | + | ||
207 | +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | ||
208 | +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | ||
209 | + int16_t src2, int16_t src3) | ||
210 | +{ | ||
211 | + /* Similarly, using subtraction: | ||
212 | + * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 | ||
213 | + * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 | ||
214 | + */ | ||
215 | + int32_t ret = (int32_t)src1 * src2; | ||
216 | + ret = ((int32_t)src3 << 15) - ret + (1 << 14); | ||
217 | + ret >>= 15; | ||
218 | + if (ret != (int16_t)ret) { | ||
219 | + SET_QC(); | ||
220 | + ret = (ret < 0 ? -0x8000 : 0x7fff); | ||
221 | + } | ||
222 | + return ret; | ||
223 | +} | ||
224 | + | ||
225 | +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
226 | + uint32_t src2, uint32_t src3) | ||
227 | +{ | ||
228 | + uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3); | ||
229 | + uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); | ||
230 | + return deposit32(e1, 16, 16, e2); | ||
231 | +} | ||
232 | + | ||
233 | +/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
234 | +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
235 | + int32_t src2, int32_t src3) | ||
236 | +{ | ||
237 | + /* Simplify similarly to int_qrdmlah_s16 above. */ | ||
238 | + int64_t ret = (int64_t)src1 * src2; | ||
239 | + ret = ((int64_t)src3 << 31) + ret + (1 << 30); | ||
240 | + ret >>= 31; | ||
241 | + if (ret != (int32_t)ret) { | ||
242 | + SET_QC(); | ||
243 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
244 | + } | ||
245 | + return ret; | ||
246 | +} | ||
247 | + | ||
248 | +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | ||
249 | +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | ||
250 | + int32_t src2, int32_t src3) | ||
251 | +{ | ||
252 | + /* Simplify similarly to int_qrdmlsh_s16 above. */ | ||
253 | + int64_t ret = (int64_t)src1 * src2; | ||
254 | + ret = ((int64_t)src3 << 31) - ret + (1 << 30); | ||
255 | + ret >>= 31; | ||
256 | + if (ret != (int32_t)ret) { | ||
257 | + SET_QC(); | ||
258 | + ret = (ret < 0 ? INT32_MIN : INT32_MAX); | ||
259 | + } | ||
260 | + return ret; | ||
261 | +} | 61 | +} |
262 | -- | 62 | -- |
263 | 2.16.2 | 63 | 2.20.1 |
264 | 64 | ||
265 | 65 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Split out gen_top_byte_ignore in preparation of handling these |
4 | data accesses; the new tbflags field is not yet honored. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180228193125.20577-12-richard.henderson@linaro.org | 8 | Message-id: 20190204132126.3255-2-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | target/arm/helper.h | 7 ++++ | 11 | target/arm/cpu.h | 1 + |
9 | target/arm/translate-a64.c | 48 ++++++++++++++++++++++- | 12 | target/arm/translate.h | 3 +- |
10 | target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ | 13 | target/arm/helper.c | 1 + |
11 | 3 files changed, 151 insertions(+), 1 deletion(-) | 14 | target/arm/translate-a64.c | 72 +++++++++++++++++++------------------- |
15 | 4 files changed, 40 insertions(+), 37 deletions(-) | ||
12 | 16 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 19 | --- a/target/arm/cpu.h |
16 | +++ b/target/arm/helper.h | 20 | +++ b/target/arm/cpu.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 21 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) |
18 | DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 22 | FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) |
19 | void, ptr, ptr, ptr, ptr, i32) | 23 | FIELD(TBFLAG_A64, BT, 9, 1) |
20 | 24 | FIELD(TBFLAG_A64, BTYPE, 10, 2) | |
21 | +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, | 25 | +FIELD(TBFLAG_A64, TBID, 12, 2) |
22 | + void, ptr, ptr, ptr, ptr, i32) | 26 | |
23 | +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, | 27 | static inline bool bswap_code(bool sctlr_b) |
24 | + void, ptr, ptr, ptr, ptr, i32) | 28 | { |
25 | +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, | 29 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
26 | + void, ptr, ptr, ptr, ptr, i32) | 30 | index XXXXXXX..XXXXXXX 100644 |
27 | + | 31 | --- a/target/arm/translate.h |
28 | #ifdef TARGET_AARCH64 | 32 | +++ b/target/arm/translate.h |
29 | #include "helper-a64.h" | 33 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
34 | int user; | ||
30 | #endif | 35 | #endif |
36 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ | ||
37 | - uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ | ||
38 | + uint8_t tbii; /* TBI1|TBI0 for insns */ | ||
39 | + uint8_t tbid; /* TBI1|TBI0 for data */ | ||
40 | bool ns; /* Use non-secure CPREG bank on access */ | ||
41 | int fp_excp_el; /* FP exception EL or 0 if enabled */ | ||
42 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ | ||
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/helper.c | ||
46 | +++ b/target/arm/helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
48 | } | ||
49 | |||
50 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); | ||
51 | + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); | ||
52 | } | ||
53 | #endif | ||
54 | |||
31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 55 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
32 | index XXXXXXX..XXXXXXX 100644 | 56 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/translate-a64.c | 57 | --- a/target/arm/translate-a64.c |
34 | +++ b/target/arm/translate-a64.c | 58 | +++ b/target/arm/translate-a64.c |
35 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | 59 | @@ -XXX,XX +XXX,XX @@ void gen_a64_set_pc_im(uint64_t val) |
36 | is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | 60 | tcg_gen_movi_i64(cpu_pc, val); |
37 | } | 61 | } |
38 | 62 | ||
39 | +/* Expand a 3-operand + fpstatus pointer + simd data value operation using | 63 | -/* Load the PC from a generic TCG variable. |
40 | + * an out-of-line helper. | 64 | +/* |
41 | + */ | 65 | + * Handle Top Byte Ignore (TBI) bits. |
42 | +static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, | 66 | * |
43 | + int rm, bool is_fp16, int data, | 67 | - * If address tagging is enabled via the TCR TBI bits, then loading |
44 | + gen_helper_gvec_3_ptr *fn) | 68 | - * an address into the PC will clear out any tag in it: |
69 | + * If address tagging is enabled via the TCR TBI bits: | ||
70 | * + for EL2 and EL3 there is only one TBI bit, and if it is set | ||
71 | * then the address is zero-extended, clearing bits [63:56] | ||
72 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | ||
73 | @@ -XXX,XX +XXX,XX @@ void gen_a64_set_pc_im(uint64_t val) | ||
74 | * If the appropriate TBI bit is set for the address then | ||
75 | * the address is sign-extended from bit 55 into bits [63:56] | ||
76 | * | ||
77 | - * We can avoid doing this for relative-branches, because the | ||
78 | - * PC + offset can never overflow into the tag bits (assuming | ||
79 | - * that virtual addresses are less than 56 bits wide, as they | ||
80 | - * are currently), but we must handle it for branch-to-register. | ||
81 | + * Here We have concatenated TBI{1,0} into tbi. | ||
82 | */ | ||
83 | -static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | ||
84 | +static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, | ||
85 | + TCGv_i64 src, int tbi) | ||
86 | { | ||
87 | - /* Note that TBII is TBI1:TBI0. */ | ||
88 | - int tbi = s->tbii; | ||
89 | - | ||
90 | - if (s->current_el <= 1) { | ||
91 | - if (tbi != 0) { | ||
92 | - /* Sign-extend from bit 55. */ | ||
93 | - tcg_gen_sextract_i64(cpu_pc, src, 0, 56); | ||
94 | - | ||
95 | - if (tbi != 3) { | ||
96 | - TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
97 | - | ||
98 | - /* | ||
99 | - * The two TBI bits differ. | ||
100 | - * If tbi0, then !tbi1: only use the extension if positive. | ||
101 | - * if !tbi0, then tbi1: only use the extension if negative. | ||
102 | - */ | ||
103 | - tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | ||
104 | - cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); | ||
105 | - tcg_temp_free_i64(tcg_zero); | ||
106 | - } | ||
107 | - return; | ||
108 | - } | ||
109 | + if (tbi == 0) { | ||
110 | + /* Load unmodified address */ | ||
111 | + tcg_gen_mov_i64(dst, src); | ||
112 | + } else if (s->current_el >= 2) { | ||
113 | + /* FIXME: ARMv8.1-VHE S2 translation regime. */ | ||
114 | + /* Force tag byte to all zero */ | ||
115 | + tcg_gen_extract_i64(dst, src, 0, 56); | ||
116 | } else { | ||
117 | - if (tbi != 0) { | ||
118 | - /* Force tag byte to all zero */ | ||
119 | - tcg_gen_extract_i64(cpu_pc, src, 0, 56); | ||
120 | - return; | ||
121 | + /* Sign-extend from bit 55. */ | ||
122 | + tcg_gen_sextract_i64(dst, src, 0, 56); | ||
123 | + | ||
124 | + if (tbi != 3) { | ||
125 | + TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
126 | + | ||
127 | + /* | ||
128 | + * The two TBI bits differ. | ||
129 | + * If tbi0, then !tbi1: only use the extension if positive. | ||
130 | + * if !tbi0, then tbi1: only use the extension if negative. | ||
131 | + */ | ||
132 | + tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | ||
133 | + dst, dst, tcg_zero, dst, src); | ||
134 | + tcg_temp_free_i64(tcg_zero); | ||
135 | } | ||
136 | } | ||
137 | +} | ||
138 | |||
139 | - /* Load unmodified address */ | ||
140 | - tcg_gen_mov_i64(cpu_pc, src); | ||
141 | +static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | ||
45 | +{ | 142 | +{ |
46 | + TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); | 143 | + /* |
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | 144 | + * If address tagging is enabled for instructions via the TCR TBI bits, |
48 | + vec_full_reg_offset(s, rn), | 145 | + * then loading an address into the PC will clear out any tag. |
49 | + vec_full_reg_offset(s, rm), fpst, | 146 | + */ |
50 | + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | 147 | + gen_top_byte_ignore(s, cpu_pc, src, s->tbii); |
51 | + tcg_temp_free_ptr(fpst); | ||
52 | +} | ||
53 | + | ||
54 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | ||
55 | * than the 32 bit equivalent. | ||
56 | */ | ||
57 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
58 | int size = extract32(insn, 22, 2); | ||
59 | bool u = extract32(insn, 29, 1); | ||
60 | bool is_q = extract32(insn, 30, 1); | ||
61 | - int feature; | ||
62 | + int feature, rot; | ||
63 | |||
64 | switch (u * 16 + opcode) { | ||
65 | case 0x10: /* SQRDMLAH (vector) */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | } | ||
68 | feature = ARM_FEATURE_V8_RDM; | ||
69 | break; | ||
70 | + case 0xc: /* FCADD, #90 */ | ||
71 | + case 0xe: /* FCADD, #270 */ | ||
72 | + if (size == 0 | ||
73 | + || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) | ||
74 | + || (size == 3 && !is_q)) { | ||
75 | + unallocated_encoding(s); | ||
76 | + return; | ||
77 | + } | ||
78 | + feature = ARM_FEATURE_V8_FCMA; | ||
79 | + break; | ||
80 | default: | ||
81 | unallocated_encoding(s); | ||
82 | return; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
84 | } | ||
85 | return; | ||
86 | |||
87 | + case 0xc: /* FCADD, #90 */ | ||
88 | + case 0xe: /* FCADD, #270 */ | ||
89 | + rot = extract32(opcode, 1, 1); | ||
90 | + switch (size) { | ||
91 | + case 1: | ||
92 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
93 | + gen_helper_gvec_fcaddh); | ||
94 | + break; | ||
95 | + case 2: | ||
96 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
97 | + gen_helper_gvec_fcadds); | ||
98 | + break; | ||
99 | + case 3: | ||
100 | + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, | ||
101 | + gen_helper_gvec_fcaddd); | ||
102 | + break; | ||
103 | + default: | ||
104 | + g_assert_not_reached(); | ||
105 | + } | ||
106 | + return; | ||
107 | + | ||
108 | default: | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/vec_helper.c | ||
114 | +++ b/target/arm/vec_helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | #include "exec/exec-all.h" | ||
117 | #include "exec/helper-proto.h" | ||
118 | #include "tcg/tcg-gvec-desc.h" | ||
119 | +#include "fpu/softfloat.h" | ||
120 | |||
121 | |||
122 | +/* Note that vector data is stored in host-endian 64-bit chunks, | ||
123 | + so addressing units smaller than that needs a host-endian fixup. */ | ||
124 | +#ifdef HOST_WORDS_BIGENDIAN | ||
125 | +#define H1(x) ((x) ^ 7) | ||
126 | +#define H2(x) ((x) ^ 3) | ||
127 | +#define H4(x) ((x) ^ 1) | ||
128 | +#else | ||
129 | +#define H1(x) (x) | ||
130 | +#define H2(x) (x) | ||
131 | +#define H4(x) (x) | ||
132 | +#endif | ||
133 | + | ||
134 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
135 | |||
136 | static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
137 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | ||
138 | } | ||
139 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
140 | } | 148 | } |
141 | + | 149 | |
142 | +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, | 150 | typedef struct DisasCompare64 { |
143 | + void *vfpst, uint32_t desc) | 151 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
144 | +{ | 152 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); |
145 | + uintptr_t opr_sz = simd_oprsz(desc); | 153 | dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); |
146 | + float16 *d = vd; | 154 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); |
147 | + float16 *n = vn; | 155 | + dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); |
148 | + float16 *m = vm; | 156 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); |
149 | + float_status *fpst = vfpst; | 157 | #if !defined(CONFIG_USER_ONLY) |
150 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | 158 | dc->user = (dc->current_el == 0); |
151 | + uint32_t neg_imag = neg_real ^ 1; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
155 | + neg_real <<= 15; | ||
156 | + neg_imag <<= 15; | ||
157 | + | ||
158 | + for (i = 0; i < opr_sz / 2; i += 2) { | ||
159 | + float16 e0 = n[H2(i)]; | ||
160 | + float16 e1 = m[H2(i + 1)] ^ neg_imag; | ||
161 | + float16 e2 = n[H2(i + 1)]; | ||
162 | + float16 e3 = m[H2(i)] ^ neg_real; | ||
163 | + | ||
164 | + d[H2(i)] = float16_add(e0, e1, fpst); | ||
165 | + d[H2(i + 1)] = float16_add(e2, e3, fpst); | ||
166 | + } | ||
167 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
168 | +} | ||
169 | + | ||
170 | +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, | ||
171 | + void *vfpst, uint32_t desc) | ||
172 | +{ | ||
173 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
174 | + float32 *d = vd; | ||
175 | + float32 *n = vn; | ||
176 | + float32 *m = vm; | ||
177 | + float_status *fpst = vfpst; | ||
178 | + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); | ||
179 | + uint32_t neg_imag = neg_real ^ 1; | ||
180 | + uintptr_t i; | ||
181 | + | ||
182 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
183 | + neg_real <<= 31; | ||
184 | + neg_imag <<= 31; | ||
185 | + | ||
186 | + for (i = 0; i < opr_sz / 4; i += 2) { | ||
187 | + float32 e0 = n[H4(i)]; | ||
188 | + float32 e1 = m[H4(i + 1)] ^ neg_imag; | ||
189 | + float32 e2 = n[H4(i + 1)]; | ||
190 | + float32 e3 = m[H4(i)] ^ neg_real; | ||
191 | + | ||
192 | + d[H4(i)] = float32_add(e0, e1, fpst); | ||
193 | + d[H4(i + 1)] = float32_add(e2, e3, fpst); | ||
194 | + } | ||
195 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
196 | +} | ||
197 | + | ||
198 | +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, | ||
199 | + void *vfpst, uint32_t desc) | ||
200 | +{ | ||
201 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
202 | + float64 *d = vd; | ||
203 | + float64 *n = vn; | ||
204 | + float64 *m = vm; | ||
205 | + float_status *fpst = vfpst; | ||
206 | + uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); | ||
207 | + uint64_t neg_imag = neg_real ^ 1; | ||
208 | + uintptr_t i; | ||
209 | + | ||
210 | + /* Shift boolean to the sign bit so we can xor to negate. */ | ||
211 | + neg_real <<= 63; | ||
212 | + neg_imag <<= 63; | ||
213 | + | ||
214 | + for (i = 0; i < opr_sz / 8; i += 2) { | ||
215 | + float64 e0 = n[i]; | ||
216 | + float64 e1 = m[i + 1] ^ neg_imag; | ||
217 | + float64 e2 = n[i + 1]; | ||
218 | + float64 e3 = m[i] ^ neg_real; | ||
219 | + | ||
220 | + d[i] = float64_add(e0, e1, fpst); | ||
221 | + d[i + 1] = float64_add(e2, e3, fpst); | ||
222 | + } | ||
223 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
224 | +} | ||
225 | -- | 159 | -- |
226 | 2.16.2 | 160 | 2.20.1 |
227 | 161 | ||
228 | 162 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Include the U bit in the switches rather than testing separately. | 3 | This will allow TBI to be used in user-only mode, as well as |
4 | avoid ping-ponging the softmmu TLB when TBI is in use. It | ||
5 | will also enable other armv8 extensions. | ||
4 | 6 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: 20190204132126.3255-3-richard.henderson@linaro.org |
7 | Message-id: 20180228193125.20577-3-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------ | 12 | target/arm/translate-a64.c | 217 ++++++++++++++++++++----------------- |
11 | 1 file changed, 61 insertions(+), 68 deletions(-) | 13 | 1 file changed, 116 insertions(+), 101 deletions(-) |
12 | 14 | ||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a64.c | 17 | --- a/target/arm/translate-a64.c |
16 | +++ b/target/arm/translate-a64.c | 18 | +++ b/target/arm/translate-a64.c |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) |
18 | int index; | 20 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); |
19 | TCGv_ptr fpst; | 21 | } |
20 | 22 | ||
21 | - switch (opcode) { | 23 | +/* |
22 | - case 0x0: /* MLA */ | 24 | + * Return a "clean" address for ADDR according to TBID. |
23 | - case 0x4: /* MLS */ | 25 | + * This is always a fresh temporary, as we need to be able to |
24 | - if (!u || is_scalar) { | 26 | + * increment this independently of a dirty write-back address. |
25 | + switch (16 * u + opcode) { | 27 | + */ |
26 | + case 0x08: /* MUL */ | 28 | +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) |
27 | + case 0x10: /* MLA */ | 29 | +{ |
28 | + case 0x14: /* MLS */ | 30 | + TCGv_i64 clean = new_tmp_a64(s); |
29 | + if (is_scalar) { | 31 | + gen_top_byte_ignore(s, clean, addr, s->tbid); |
30 | unallocated_encoding(s); | 32 | + return clean; |
33 | +} | ||
34 | + | ||
35 | typedef struct DisasCompare64 { | ||
36 | TCGCond cond; | ||
37 | TCGv_i64 value; | ||
38 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, | ||
39 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | ||
40 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
41 | int memidx = get_mem_index(s); | ||
42 | - TCGv_i64 addr = cpu_reg_sp(s, rn); | ||
43 | + TCGv_i64 clean_addr; | ||
44 | |||
45 | if (rn == 31) { | ||
46 | gen_check_sp_alignment(s); | ||
47 | } | ||
48 | - tcg_gen_atomic_cmpxchg_i64(tcg_rs, addr, tcg_rs, tcg_rt, memidx, | ||
49 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
50 | + tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, | ||
51 | size | MO_ALIGN | s->be_data); | ||
52 | } | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
55 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | ||
56 | TCGv_i64 t1 = cpu_reg(s, rt); | ||
57 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | ||
58 | - TCGv_i64 addr = cpu_reg_sp(s, rn); | ||
59 | + TCGv_i64 clean_addr; | ||
60 | int memidx = get_mem_index(s); | ||
61 | |||
62 | if (rn == 31) { | ||
63 | gen_check_sp_alignment(s); | ||
64 | } | ||
65 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
66 | |||
67 | if (size == 2) { | ||
68 | TCGv_i64 cmp = tcg_temp_new_i64(); | ||
69 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
70 | tcg_gen_concat32_i64(cmp, s2, s1); | ||
71 | } | ||
72 | |||
73 | - tcg_gen_atomic_cmpxchg_i64(cmp, addr, cmp, val, memidx, | ||
74 | + tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, | ||
75 | MO_64 | MO_ALIGN | s->be_data); | ||
76 | tcg_temp_free_i64(val); | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
79 | if (HAVE_CMPXCHG128) { | ||
80 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | ||
81 | if (s->be_data == MO_LE) { | ||
82 | - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); | ||
83 | + gen_helper_casp_le_parallel(cpu_env, tcg_rs, | ||
84 | + clean_addr, t1, t2); | ||
85 | } else { | ||
86 | - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); | ||
87 | + gen_helper_casp_be_parallel(cpu_env, tcg_rs, | ||
88 | + clean_addr, t1, t2); | ||
89 | } | ||
90 | tcg_temp_free_i32(tcg_rs); | ||
91 | } else { | ||
92 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
93 | TCGv_i64 zero = tcg_const_i64(0); | ||
94 | |||
95 | /* Load the two words, in memory order. */ | ||
96 | - tcg_gen_qemu_ld_i64(d1, addr, memidx, | ||
97 | + tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, | ||
98 | MO_64 | MO_ALIGN_16 | s->be_data); | ||
99 | - tcg_gen_addi_i64(a2, addr, 8); | ||
100 | - tcg_gen_qemu_ld_i64(d2, addr, memidx, MO_64 | s->be_data); | ||
101 | + tcg_gen_addi_i64(a2, clean_addr, 8); | ||
102 | + tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data); | ||
103 | |||
104 | /* Compare the two words, also in memory order. */ | ||
105 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | ||
106 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
107 | /* If compare equal, write back new data, else write back old data. */ | ||
108 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | ||
109 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | ||
110 | - tcg_gen_qemu_st_i64(c1, addr, memidx, MO_64 | s->be_data); | ||
111 | + tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); | ||
112 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); | ||
113 | tcg_temp_free_i64(a2); | ||
114 | tcg_temp_free_i64(c1); | ||
115 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
116 | int is_lasr = extract32(insn, 15, 1); | ||
117 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | ||
118 | int size = extract32(insn, 30, 2); | ||
119 | - TCGv_i64 tcg_addr; | ||
120 | + TCGv_i64 clean_addr; | ||
121 | |||
122 | switch (o2_L_o1_o0) { | ||
123 | case 0x0: /* STXR */ | ||
124 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
125 | if (is_lasr) { | ||
126 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
127 | } | ||
128 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
129 | - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, false); | ||
130 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
131 | + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); | ||
132 | return; | ||
133 | |||
134 | case 0x4: /* LDXR */ | ||
135 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
136 | if (rn == 31) { | ||
137 | gen_check_sp_alignment(s); | ||
138 | } | ||
139 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
140 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
141 | s->is_ldex = true; | ||
142 | - gen_load_exclusive(s, rt, rt2, tcg_addr, size, false); | ||
143 | + gen_load_exclusive(s, rt, rt2, clean_addr, size, false); | ||
144 | if (is_lasr) { | ||
145 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
146 | } | ||
147 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
148 | gen_check_sp_alignment(s); | ||
149 | } | ||
150 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
151 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
152 | - do_gpr_st(s, cpu_reg(s, rt), tcg_addr, size, true, rt, | ||
153 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
154 | + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, | ||
155 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
156 | return; | ||
157 | |||
158 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
159 | if (rn == 31) { | ||
160 | gen_check_sp_alignment(s); | ||
161 | } | ||
162 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
163 | - do_gpr_ld(s, cpu_reg(s, rt), tcg_addr, size, false, false, true, rt, | ||
164 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
165 | + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, | ||
166 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
167 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
168 | return; | ||
169 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
170 | if (is_lasr) { | ||
171 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
172 | } | ||
173 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
174 | - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, true); | ||
175 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
176 | + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); | ||
31 | return; | 177 | return; |
32 | } | 178 | } |
33 | break; | 179 | if (rt2 == 31 |
34 | - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | 180 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
35 | - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | 181 | if (rn == 31) { |
36 | - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | 182 | gen_check_sp_alignment(s); |
37 | + case 0x02: /* SMLAL, SMLAL2 */ | ||
38 | + case 0x12: /* UMLAL, UMLAL2 */ | ||
39 | + case 0x06: /* SMLSL, SMLSL2 */ | ||
40 | + case 0x16: /* UMLSL, UMLSL2 */ | ||
41 | + case 0x0a: /* SMULL, SMULL2 */ | ||
42 | + case 0x1a: /* UMULL, UMULL2 */ | ||
43 | if (is_scalar) { | ||
44 | unallocated_encoding(s); | ||
45 | return; | ||
46 | } | ||
47 | is_long = true; | ||
48 | break; | ||
49 | - case 0x3: /* SQDMLAL, SQDMLAL2 */ | ||
50 | - case 0x7: /* SQDMLSL, SQDMLSL2 */ | ||
51 | - case 0xb: /* SQDMULL, SQDMULL2 */ | ||
52 | + case 0x03: /* SQDMLAL, SQDMLAL2 */ | ||
53 | + case 0x07: /* SQDMLSL, SQDMLSL2 */ | ||
54 | + case 0x0b: /* SQDMULL, SQDMULL2 */ | ||
55 | is_long = true; | ||
56 | - /* fall through */ | ||
57 | - case 0xc: /* SQDMULH */ | ||
58 | - case 0xd: /* SQRDMULH */ | ||
59 | - if (u) { | ||
60 | - unallocated_encoding(s); | ||
61 | - return; | ||
62 | - } | ||
63 | break; | ||
64 | - case 0x8: /* MUL */ | ||
65 | - if (u || is_scalar) { | ||
66 | - unallocated_encoding(s); | ||
67 | - return; | ||
68 | - } | ||
69 | + case 0x0c: /* SQDMULH */ | ||
70 | + case 0x0d: /* SQRDMULH */ | ||
71 | break; | ||
72 | - case 0x1: /* FMLA */ | ||
73 | - case 0x5: /* FMLS */ | ||
74 | - if (u) { | ||
75 | - unallocated_encoding(s); | ||
76 | - return; | ||
77 | - } | ||
78 | - /* fall through */ | ||
79 | - case 0x9: /* FMUL, FMULX */ | ||
80 | + case 0x01: /* FMLA */ | ||
81 | + case 0x05: /* FMLS */ | ||
82 | + case 0x09: /* FMUL */ | ||
83 | + case 0x19: /* FMULX */ | ||
84 | if (size == 1) { | ||
85 | unallocated_encoding(s); | ||
86 | return; | ||
87 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
88 | |||
89 | read_vec_element(s, tcg_op, rn, pass, MO_64); | ||
90 | |||
91 | - switch (opcode) { | ||
92 | - case 0x5: /* FMLS */ | ||
93 | + switch (16 * u + opcode) { | ||
94 | + case 0x05: /* FMLS */ | ||
95 | /* As usual for ARM, separate negation for fused multiply-add */ | ||
96 | gen_helper_vfp_negd(tcg_op, tcg_op); | ||
97 | /* fall through */ | ||
98 | - case 0x1: /* FMLA */ | ||
99 | + case 0x01: /* FMLA */ | ||
100 | read_vec_element(s, tcg_res, rd, pass, MO_64); | ||
101 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | ||
102 | break; | ||
103 | - case 0x9: /* FMUL, FMULX */ | ||
104 | - if (u) { | ||
105 | - gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
106 | - } else { | ||
107 | - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
108 | - } | ||
109 | + case 0x09: /* FMUL */ | ||
110 | + gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | ||
111 | + break; | ||
112 | + case 0x19: /* FMULX */ | ||
113 | + gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | ||
114 | break; | ||
115 | default: | ||
116 | g_assert_not_reached(); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
118 | |||
119 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); | ||
120 | |||
121 | - switch (opcode) { | ||
122 | - case 0x0: /* MLA */ | ||
123 | - case 0x4: /* MLS */ | ||
124 | - case 0x8: /* MUL */ | ||
125 | + switch (16 * u + opcode) { | ||
126 | + case 0x08: /* MUL */ | ||
127 | + case 0x10: /* MLA */ | ||
128 | + case 0x14: /* MLS */ | ||
129 | { | ||
130 | static NeonGenTwoOpFn * const fns[2][2] = { | ||
131 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | ||
132 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
133 | genfn(tcg_res, tcg_op, tcg_res); | ||
134 | break; | ||
135 | } | 183 | } |
136 | - case 0x5: /* FMLS */ | 184 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); |
137 | - case 0x1: /* FMLA */ | 185 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); |
138 | + case 0x05: /* FMLS */ | 186 | s->is_ldex = true; |
139 | + case 0x01: /* FMLA */ | 187 | - gen_load_exclusive(s, rt, rt2, tcg_addr, size, true); |
140 | read_vec_element_i32(s, tcg_res, rd, pass, | 188 | + gen_load_exclusive(s, rt, rt2, clean_addr, size, true); |
141 | is_scalar ? size : MO_32); | 189 | if (is_lasr) { |
142 | switch (size) { | 190 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); |
143 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 191 | } |
144 | g_assert_not_reached(); | 192 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) |
193 | int opc = extract32(insn, 30, 2); | ||
194 | bool is_signed = false; | ||
195 | int size = 2; | ||
196 | - TCGv_i64 tcg_rt, tcg_addr; | ||
197 | + TCGv_i64 tcg_rt, clean_addr; | ||
198 | |||
199 | if (is_vector) { | ||
200 | if (opc == 3) { | ||
201 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) | ||
202 | |||
203 | tcg_rt = cpu_reg(s, rt); | ||
204 | |||
205 | - tcg_addr = tcg_const_i64((s->pc - 4) + imm); | ||
206 | + clean_addr = tcg_const_i64((s->pc - 4) + imm); | ||
207 | if (is_vector) { | ||
208 | - do_fp_ld(s, rt, tcg_addr, size); | ||
209 | + do_fp_ld(s, rt, clean_addr, size); | ||
210 | } else { | ||
211 | /* Only unsigned 32bit loads target 32bit registers. */ | ||
212 | bool iss_sf = opc != 0; | ||
213 | |||
214 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, | ||
215 | + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, | ||
216 | true, rt, iss_sf, false); | ||
217 | } | ||
218 | - tcg_temp_free_i64(tcg_addr); | ||
219 | + tcg_temp_free_i64(clean_addr); | ||
220 | } | ||
221 | |||
222 | /* | ||
223 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
224 | bool postindex = false; | ||
225 | bool wback = false; | ||
226 | |||
227 | - TCGv_i64 tcg_addr; /* calculated address */ | ||
228 | + TCGv_i64 clean_addr, dirty_addr; | ||
229 | + | ||
230 | int size; | ||
231 | |||
232 | if (opc == 3) { | ||
233 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
234 | gen_check_sp_alignment(s); | ||
235 | } | ||
236 | |||
237 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
238 | - | ||
239 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
240 | if (!postindex) { | ||
241 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | ||
242 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
243 | } | ||
244 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
245 | |||
246 | if (is_vector) { | ||
247 | if (is_load) { | ||
248 | - do_fp_ld(s, rt, tcg_addr, size); | ||
249 | + do_fp_ld(s, rt, clean_addr, size); | ||
250 | } else { | ||
251 | - do_fp_st(s, rt, tcg_addr, size); | ||
252 | + do_fp_st(s, rt, clean_addr, size); | ||
253 | } | ||
254 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | ||
255 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
256 | if (is_load) { | ||
257 | - do_fp_ld(s, rt2, tcg_addr, size); | ||
258 | + do_fp_ld(s, rt2, clean_addr, size); | ||
259 | } else { | ||
260 | - do_fp_st(s, rt2, tcg_addr, size); | ||
261 | + do_fp_st(s, rt2, clean_addr, size); | ||
262 | } | ||
263 | } else { | ||
264 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
265 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
266 | /* Do not modify tcg_rt before recognizing any exception | ||
267 | * from the second load. | ||
268 | */ | ||
269 | - do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false, | ||
270 | + do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, | ||
271 | false, 0, false, false); | ||
272 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | ||
273 | - do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, | ||
274 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
275 | + do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | ||
276 | false, 0, false, false); | ||
277 | |||
278 | tcg_gen_mov_i64(tcg_rt, tmp); | ||
279 | tcg_temp_free_i64(tmp); | ||
280 | } else { | ||
281 | - do_gpr_st(s, tcg_rt, tcg_addr, size, | ||
282 | + do_gpr_st(s, tcg_rt, clean_addr, size, | ||
283 | false, 0, false, false); | ||
284 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | ||
285 | - do_gpr_st(s, tcg_rt2, tcg_addr, size, | ||
286 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
287 | + do_gpr_st(s, tcg_rt2, clean_addr, size, | ||
288 | false, 0, false, false); | ||
289 | } | ||
290 | } | ||
291 | |||
292 | if (wback) { | ||
293 | if (postindex) { | ||
294 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); | ||
295 | - } else { | ||
296 | - tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); | ||
297 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
298 | } | ||
299 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | ||
300 | + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); | ||
301 | } | ||
302 | } | ||
303 | |||
304 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
305 | bool post_index; | ||
306 | bool writeback; | ||
307 | |||
308 | - TCGv_i64 tcg_addr; | ||
309 | + TCGv_i64 clean_addr, dirty_addr; | ||
310 | |||
311 | if (is_vector) { | ||
312 | size |= (opc & 2) << 1; | ||
313 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
314 | if (rn == 31) { | ||
315 | gen_check_sp_alignment(s); | ||
316 | } | ||
317 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
318 | |||
319 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
320 | if (!post_index) { | ||
321 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | ||
322 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); | ||
323 | } | ||
324 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
325 | |||
326 | if (is_vector) { | ||
327 | if (is_store) { | ||
328 | - do_fp_st(s, rt, tcg_addr, size); | ||
329 | + do_fp_st(s, rt, clean_addr, size); | ||
330 | } else { | ||
331 | - do_fp_ld(s, rt, tcg_addr, size); | ||
332 | + do_fp_ld(s, rt, clean_addr, size); | ||
333 | } | ||
334 | } else { | ||
335 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
336 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
337 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
338 | |||
339 | if (is_store) { | ||
340 | - do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx, | ||
341 | + do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, | ||
342 | iss_valid, rt, iss_sf, false); | ||
343 | } else { | ||
344 | - do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, | ||
345 | + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, | ||
346 | is_signed, is_extended, memidx, | ||
347 | iss_valid, rt, iss_sf, false); | ||
348 | } | ||
349 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
350 | if (writeback) { | ||
351 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | ||
352 | if (post_index) { | ||
353 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | ||
354 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); | ||
355 | } | ||
356 | - tcg_gen_mov_i64(tcg_rn, tcg_addr); | ||
357 | + tcg_gen_mov_i64(tcg_rn, dirty_addr); | ||
358 | } | ||
359 | } | ||
360 | |||
361 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, | ||
362 | bool is_store = false; | ||
363 | bool is_extended = false; | ||
364 | |||
365 | - TCGv_i64 tcg_rm; | ||
366 | - TCGv_i64 tcg_addr; | ||
367 | + TCGv_i64 tcg_rm, clean_addr, dirty_addr; | ||
368 | |||
369 | if (extract32(opt, 1, 1) == 0) { | ||
370 | unallocated_encoding(s); | ||
371 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, | ||
372 | if (rn == 31) { | ||
373 | gen_check_sp_alignment(s); | ||
374 | } | ||
375 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
376 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
377 | |||
378 | tcg_rm = read_cpu_reg(s, rm, 1); | ||
379 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | ||
380 | |||
381 | - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); | ||
382 | + tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); | ||
383 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
384 | |||
385 | if (is_vector) { | ||
386 | if (is_store) { | ||
387 | - do_fp_st(s, rt, tcg_addr, size); | ||
388 | + do_fp_st(s, rt, clean_addr, size); | ||
389 | } else { | ||
390 | - do_fp_ld(s, rt, tcg_addr, size); | ||
391 | + do_fp_ld(s, rt, clean_addr, size); | ||
392 | } | ||
393 | } else { | ||
394 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
395 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
396 | if (is_store) { | ||
397 | - do_gpr_st(s, tcg_rt, tcg_addr, size, | ||
398 | + do_gpr_st(s, tcg_rt, clean_addr, size, | ||
399 | true, rt, iss_sf, false); | ||
400 | } else { | ||
401 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, | ||
402 | + do_gpr_ld(s, tcg_rt, clean_addr, size, | ||
403 | is_signed, is_extended, | ||
404 | true, rt, iss_sf, false); | ||
405 | } | ||
406 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, | ||
407 | unsigned int imm12 = extract32(insn, 10, 12); | ||
408 | unsigned int offset; | ||
409 | |||
410 | - TCGv_i64 tcg_addr; | ||
411 | + TCGv_i64 clean_addr, dirty_addr; | ||
412 | |||
413 | bool is_store; | ||
414 | bool is_signed = false; | ||
415 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, | ||
416 | if (rn == 31) { | ||
417 | gen_check_sp_alignment(s); | ||
418 | } | ||
419 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
420 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
421 | offset = imm12 << size; | ||
422 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | ||
423 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
424 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
425 | |||
426 | if (is_vector) { | ||
427 | if (is_store) { | ||
428 | - do_fp_st(s, rt, tcg_addr, size); | ||
429 | + do_fp_st(s, rt, clean_addr, size); | ||
430 | } else { | ||
431 | - do_fp_ld(s, rt, tcg_addr, size); | ||
432 | + do_fp_ld(s, rt, clean_addr, size); | ||
433 | } | ||
434 | } else { | ||
435 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
436 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
437 | if (is_store) { | ||
438 | - do_gpr_st(s, tcg_rt, tcg_addr, size, | ||
439 | + do_gpr_st(s, tcg_rt, clean_addr, size, | ||
440 | true, rt, iss_sf, false); | ||
441 | } else { | ||
442 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended, | ||
443 | + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, | ||
444 | true, rt, iss_sf, false); | ||
445 | } | ||
446 | } | ||
447 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
448 | int rs = extract32(insn, 16, 5); | ||
449 | int rn = extract32(insn, 5, 5); | ||
450 | int o3_opc = extract32(insn, 12, 4); | ||
451 | - TCGv_i64 tcg_rn, tcg_rs; | ||
452 | + TCGv_i64 tcg_rs, clean_addr; | ||
453 | AtomicThreeOpFn *fn; | ||
454 | |||
455 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { | ||
456 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
457 | if (rn == 31) { | ||
458 | gen_check_sp_alignment(s); | ||
459 | } | ||
460 | - tcg_rn = cpu_reg_sp(s, rn); | ||
461 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
462 | tcg_rs = read_cpu_reg(s, rs, true); | ||
463 | |||
464 | if (o3_opc == 1) { /* LDCLR */ | ||
465 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
466 | /* The tcg atomic primitives are all full barriers. Therefore we | ||
467 | * can ignore the Acquire and Release bits of this instruction. | ||
468 | */ | ||
469 | - fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s), | ||
470 | + fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), | ||
471 | s->be_data | size | MO_ALIGN); | ||
472 | } | ||
473 | |||
474 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
475 | bool is_wback = extract32(insn, 11, 1); | ||
476 | bool use_key_a = !extract32(insn, 23, 1); | ||
477 | int offset; | ||
478 | - TCGv_i64 tcg_addr, tcg_rt; | ||
479 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
480 | |||
481 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | ||
482 | unallocated_encoding(s); | ||
483 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
484 | if (rn == 31) { | ||
485 | gen_check_sp_alignment(s); | ||
486 | } | ||
487 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
488 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
489 | |||
490 | if (s->pauth_active) { | ||
491 | if (use_key_a) { | ||
492 | - gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); | ||
493 | + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
494 | } else { | ||
495 | - gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); | ||
496 | + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
497 | } | ||
498 | } | ||
499 | |||
500 | /* Form the 10-bit signed, scaled offset. */ | ||
501 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | ||
502 | offset = sextract32(offset << size, 0, 10 + size); | ||
503 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | ||
504 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
505 | + | ||
506 | + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ | ||
507 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
508 | |||
509 | tcg_rt = cpu_reg(s, rt); | ||
510 | - | ||
511 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, | ||
512 | + do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | ||
513 | /* extend */ false, /* iss_valid */ !is_wback, | ||
514 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | ||
515 | |||
516 | if (is_wback) { | ||
517 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | ||
518 | + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); | ||
519 | } | ||
520 | } | ||
521 | |||
522 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
523 | bool is_store = !extract32(insn, 22, 1); | ||
524 | bool is_postidx = extract32(insn, 23, 1); | ||
525 | bool is_q = extract32(insn, 30, 1); | ||
526 | - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; | ||
527 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | ||
528 | TCGMemOp endian = s->be_data; | ||
529 | |||
530 | int ebytes; /* bytes per element */ | ||
531 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
532 | elements = (is_q ? 16 : 8) / ebytes; | ||
533 | |||
534 | tcg_rn = cpu_reg_sp(s, rn); | ||
535 | - tcg_addr = tcg_temp_new_i64(); | ||
536 | - tcg_gen_mov_i64(tcg_addr, tcg_rn); | ||
537 | + clean_addr = clean_data_tbi(s, tcg_rn); | ||
538 | tcg_ebytes = tcg_const_i64(ebytes); | ||
539 | |||
540 | for (r = 0; r < rpt; r++) { | ||
541 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
542 | for (xs = 0; xs < selem; xs++) { | ||
543 | int tt = (rt + r + xs) % 32; | ||
544 | if (is_store) { | ||
545 | - do_vec_st(s, tt, e, tcg_addr, size, endian); | ||
546 | + do_vec_st(s, tt, e, clean_addr, size, endian); | ||
547 | } else { | ||
548 | - do_vec_ld(s, tt, e, tcg_addr, size, endian); | ||
549 | + do_vec_ld(s, tt, e, clean_addr, size, endian); | ||
145 | } | 550 | } |
146 | break; | 551 | - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); |
147 | - case 0x9: /* FMUL, FMULX */ | 552 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
148 | + case 0x09: /* FMUL */ | 553 | } |
149 | switch (size) { | 554 | } |
150 | case 1: | 555 | } |
151 | - if (u) { | 556 | + tcg_temp_free_i64(tcg_ebytes); |
152 | - if (is_scalar) { | 557 | |
153 | - gen_helper_advsimd_mulxh(tcg_res, tcg_op, | 558 | if (!is_store) { |
154 | - tcg_idx, fpst); | 559 | /* For non-quad operations, setting a slice of the low |
155 | - } else { | 560 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
156 | - gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | 561 | |
157 | - tcg_idx, fpst); | 562 | if (is_postidx) { |
158 | - } | 563 | if (rm == 31) { |
159 | + if (is_scalar) { | 564 | - tcg_gen_mov_i64(tcg_rn, tcg_addr); |
160 | + gen_helper_advsimd_mulh(tcg_res, tcg_op, | 565 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes); |
161 | + tcg_idx, fpst); | 566 | } else { |
162 | } else { | 567 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); |
163 | - if (is_scalar) { | 568 | } |
164 | - gen_helper_advsimd_mulh(tcg_res, tcg_op, | 569 | } |
165 | - tcg_idx, fpst); | 570 | - tcg_temp_free_i64(tcg_ebytes); |
166 | - } else { | 571 | - tcg_temp_free_i64(tcg_addr); |
167 | - gen_helper_advsimd_mul2h(tcg_res, tcg_op, | 572 | } |
168 | - tcg_idx, fpst); | 573 | |
169 | - } | 574 | /* AdvSIMD load/store single structure |
170 | + gen_helper_advsimd_mul2h(tcg_res, tcg_op, | 575 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
171 | + tcg_idx, fpst); | 576 | bool replicate = false; |
172 | } | 577 | int index = is_q << 3 | S << 2 | size; |
173 | break; | 578 | int ebytes, xs; |
174 | case 2: | 579 | - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; |
175 | - if (u) { | 580 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; |
176 | - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | 581 | |
177 | - } else { | 582 | if (extract32(insn, 31, 1)) { |
178 | - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | 583 | unallocated_encoding(s); |
179 | - } | 584 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
180 | + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | 585 | } |
181 | break; | 586 | |
182 | default: | 587 | tcg_rn = cpu_reg_sp(s, rn); |
183 | g_assert_not_reached(); | 588 | - tcg_addr = tcg_temp_new_i64(); |
184 | } | 589 | - tcg_gen_mov_i64(tcg_addr, tcg_rn); |
185 | break; | 590 | + clean_addr = clean_data_tbi(s, tcg_rn); |
186 | - case 0xc: /* SQDMULH */ | 591 | tcg_ebytes = tcg_const_i64(ebytes); |
187 | + case 0x19: /* FMULX */ | 592 | |
188 | + switch (size) { | 593 | for (xs = 0; xs < selem; xs++) { |
189 | + case 1: | 594 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
190 | + if (is_scalar) { | 595 | /* Load and replicate to all elements */ |
191 | + gen_helper_advsimd_mulxh(tcg_res, tcg_op, | 596 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
192 | + tcg_idx, fpst); | 597 | |
193 | + } else { | 598 | - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, |
194 | + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, | 599 | + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, |
195 | + tcg_idx, fpst); | 600 | get_mem_index(s), s->be_data + scale); |
196 | + } | 601 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), |
197 | + break; | 602 | (is_q + 1) * 8, vec_full_reg_size(s), |
198 | + case 2: | 603 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
199 | + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | 604 | } else { |
200 | + break; | 605 | /* Load/store one element per register */ |
201 | + default: | 606 | if (is_load) { |
202 | + g_assert_not_reached(); | 607 | - do_vec_ld(s, rt, index, tcg_addr, scale, s->be_data); |
203 | + } | 608 | + do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); |
204 | + break; | 609 | } else { |
205 | + case 0x0c: /* SQDMULH */ | 610 | - do_vec_st(s, rt, index, tcg_addr, scale, s->be_data); |
206 | if (size == 1) { | 611 | + do_vec_st(s, rt, index, clean_addr, scale, s->be_data); |
207 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | 612 | } |
208 | tcg_op, tcg_idx); | 613 | } |
209 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | 614 | - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); |
210 | tcg_op, tcg_idx); | 615 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); |
211 | } | 616 | rt = (rt + 1) % 32; |
212 | break; | 617 | } |
213 | - case 0xd: /* SQRDMULH */ | 618 | + tcg_temp_free_i64(tcg_ebytes); |
214 | + case 0x0d: /* SQRDMULH */ | 619 | |
215 | if (size == 1) { | 620 | if (is_postidx) { |
216 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | 621 | if (rm == 31) { |
217 | tcg_op, tcg_idx); | 622 | - tcg_gen_mov_i64(tcg_rn, tcg_addr); |
623 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); | ||
624 | } else { | ||
625 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | ||
626 | } | ||
627 | } | ||
628 | - tcg_temp_free_i64(tcg_ebytes); | ||
629 | - tcg_temp_free_i64(tcg_addr); | ||
630 | } | ||
631 | |||
632 | /* Loads and stores */ | ||
218 | -- | 633 | -- |
219 | 2.16.2 | 634 | 2.20.1 |
220 | 635 | ||
221 | 636 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Enables, but does not turn on, TBI for CONFIG_USER_ONLY. |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180228193125.20577-6-richard.henderson@linaro.org | 5 | Message-id: 20190204132126.3255-4-richard.henderson@linaro.org |
6 | [PMM: adjusted #ifdeffery to placate clang, which otherwise complains | ||
7 | about static functions that are unused in the CONFIG_USER_ONLY build] | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/helper.h | 9 +++++ | 10 | target/arm/internals.h | 21 -------------------- |
9 | target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ | 11 | target/arm/helper.c | 45 ++++++++++++++++++++++-------------------- |
10 | target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++ | 12 | 2 files changed, 24 insertions(+), 42 deletions(-) |
11 | 3 files changed, 166 insertions(+) | ||
12 | 13 | ||
13 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 14 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.h | 16 | --- a/target/arm/internals.h |
16 | +++ b/target/arm/helper.h | 17 | +++ b/target/arm/internals.h |
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(dc_zva, void, env, i64) | 18 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { |
18 | DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 19 | bool using64k : 1; |
19 | DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) | 20 | } ARMVAParameters; |
20 | 21 | ||
21 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, | 22 | -#ifdef CONFIG_USER_ONLY |
22 | + void, ptr, ptr, ptr, ptr, i32) | 23 | -static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, |
23 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, | 24 | - uint64_t va, |
24 | + void, ptr, ptr, ptr, ptr, i32) | 25 | - ARMMMUIdx mmu_idx) |
25 | +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, | 26 | -{ |
26 | + void, ptr, ptr, ptr, ptr, i32) | 27 | - return (ARMVAParameters) { |
27 | +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, | 28 | - /* 48-bit address space */ |
28 | + void, ptr, ptr, ptr, ptr, i32) | 29 | - .tsz = 16, |
30 | - /* We can't handle tagged addresses properly in user-only mode */ | ||
31 | - .tbi = false, | ||
32 | - }; | ||
33 | -} | ||
34 | - | ||
35 | -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, | ||
36 | - uint64_t va, | ||
37 | - ARMMMUIdx mmu_idx, bool data) | ||
38 | -{ | ||
39 | - return aa64_va_parameters_both(env, va, mmu_idx); | ||
40 | -} | ||
41 | -#else | ||
42 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, | ||
43 | ARMMMUIdx mmu_idx); | ||
44 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
45 | ARMMMUIdx mmu_idx, bool data); | ||
46 | -#endif | ||
47 | |||
48 | #endif | ||
49 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/helper.c | ||
52 | +++ b/target/arm/helper.c | ||
53 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rbit)(uint32_t x) | ||
54 | return revbit32(x); | ||
55 | } | ||
56 | |||
57 | -#if defined(CONFIG_USER_ONLY) | ||
58 | +#ifdef CONFIG_USER_ONLY | ||
59 | |||
60 | /* These should probably raise undefined insn exceptions. */ | ||
61 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) | ||
62 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
63 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | ||
64 | } | ||
65 | } | ||
66 | +#endif /* !CONFIG_USER_ONLY */ | ||
67 | |||
68 | /* Return the exception level which controls this address translation regime */ | ||
69 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
70 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
71 | } | ||
72 | } | ||
73 | |||
74 | +#ifndef CONFIG_USER_ONLY | ||
29 | + | 75 | + |
30 | #ifdef TARGET_AARCH64 | 76 | /* Return the SCTLR value which controls this address translation regime */ |
31 | #include "helper-a64.h" | 77 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) |
32 | #endif | 78 | { |
33 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 79 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_big_endian(CPUARMState *env, |
34 | index XXXXXXX..XXXXXXX 100644 | 80 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; |
35 | --- a/target/arm/translate-a64.c | ||
36 | +++ b/target/arm/translate-a64.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, | ||
38 | vec_full_reg_size(s), gvec_op); | ||
39 | } | 81 | } |
40 | 82 | ||
41 | +/* Expand a 3-operand + env pointer operation using | 83 | +/* Return the TTBR associated with this translation regime */ |
42 | + * an out-of-line helper. | 84 | +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, |
43 | + */ | 85 | + int ttbrn) |
44 | +static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, | ||
45 | + int rn, int rm, gen_helper_gvec_3_ptr *fn) | ||
46 | +{ | 86 | +{ |
47 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), | 87 | + if (mmu_idx == ARMMMUIdx_S2NS) { |
48 | + vec_full_reg_offset(s, rn), | 88 | + return env->cp15.vttbr_el2; |
49 | + vec_full_reg_offset(s, rm), cpu_env, | ||
50 | + is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); | ||
51 | +} | ||
52 | + | ||
53 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier | ||
54 | * than the 32 bit equivalent. | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | ||
57 | clear_vec_high(s, is_q, rd); | ||
58 | } | ||
59 | |||
60 | +/* AdvSIMD three same extra | ||
61 | + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | ||
62 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
63 | + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | | ||
64 | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ | ||
65 | + */ | ||
66 | +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | ||
67 | +{ | ||
68 | + int rd = extract32(insn, 0, 5); | ||
69 | + int rn = extract32(insn, 5, 5); | ||
70 | + int opcode = extract32(insn, 11, 4); | ||
71 | + int rm = extract32(insn, 16, 5); | ||
72 | + int size = extract32(insn, 22, 2); | ||
73 | + bool u = extract32(insn, 29, 1); | ||
74 | + bool is_q = extract32(insn, 30, 1); | ||
75 | + int feature; | ||
76 | + | ||
77 | + switch (u * 16 + opcode) { | ||
78 | + case 0x10: /* SQRDMLAH (vector) */ | ||
79 | + case 0x11: /* SQRDMLSH (vector) */ | ||
80 | + if (size != 1 && size != 2) { | ||
81 | + unallocated_encoding(s); | ||
82 | + return; | ||
83 | + } | ||
84 | + feature = ARM_FEATURE_V8_RDM; | ||
85 | + break; | ||
86 | + default: | ||
87 | + unallocated_encoding(s); | ||
88 | + return; | ||
89 | + } | 89 | + } |
90 | + if (!arm_dc_feature(s, feature)) { | 90 | + if (ttbrn == 0) { |
91 | + unallocated_encoding(s); | 91 | + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; |
92 | + return; | 92 | + } else { |
93 | + } | 93 | + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; |
94 | + if (!fp_access_check(s)) { | ||
95 | + return; | ||
96 | + } | ||
97 | + | ||
98 | + switch (opcode) { | ||
99 | + case 0x0: /* SQRDMLAH (vector) */ | ||
100 | + switch (size) { | ||
101 | + case 1: | ||
102 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); | ||
103 | + break; | ||
104 | + case 2: | ||
105 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); | ||
106 | + break; | ||
107 | + default: | ||
108 | + g_assert_not_reached(); | ||
109 | + } | ||
110 | + return; | ||
111 | + | ||
112 | + case 0x1: /* SQRDMLSH (vector) */ | ||
113 | + switch (size) { | ||
114 | + case 1: | ||
115 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); | ||
116 | + break; | ||
117 | + case 2: | ||
118 | + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); | ||
119 | + break; | ||
120 | + default: | ||
121 | + g_assert_not_reached(); | ||
122 | + } | ||
123 | + return; | ||
124 | + | ||
125 | + default: | ||
126 | + g_assert_not_reached(); | ||
127 | + } | 94 | + } |
128 | +} | 95 | +} |
129 | + | 96 | + |
130 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, | 97 | +#endif /* !CONFIG_USER_ONLY */ |
131 | int size, int rn, int rd) | 98 | + |
99 | /* Return the TCR controlling this translation regime */ | ||
100 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
132 | { | 101 | { |
133 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) | 102 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) |
134 | static const AArch64DecodeTable data_proc_simd[] = { | 103 | return mmu_idx; |
135 | /* pattern , mask , fn */ | ||
136 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | ||
137 | + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, | ||
138 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | ||
139 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | ||
140 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | ||
141 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/target/arm/vec_helper.c | ||
144 | +++ b/target/arm/vec_helper.c | ||
145 | @@ -XXX,XX +XXX,XX @@ | ||
146 | |||
147 | #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q | ||
148 | |||
149 | +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
150 | +{ | ||
151 | + uint64_t *d = vd + opr_sz; | ||
152 | + uintptr_t i; | ||
153 | + | ||
154 | + for (i = opr_sz; i < max_sz; i += 8) { | ||
155 | + *d++ = 0; | ||
156 | + } | ||
157 | +} | ||
158 | + | ||
159 | /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
160 | static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, | ||
161 | int16_t src2, int16_t src3) | ||
162 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, | ||
163 | return deposit32(e1, 16, 16, e2); | ||
164 | } | 104 | } |
165 | 105 | ||
166 | +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, | 106 | -/* Return the TTBR associated with this translation regime */ |
167 | + void *ve, uint32_t desc) | 107 | -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, |
168 | +{ | 108 | - int ttbrn) |
169 | + uintptr_t opr_sz = simd_oprsz(desc); | 109 | -{ |
170 | + int16_t *d = vd; | 110 | - if (mmu_idx == ARMMMUIdx_S2NS) { |
171 | + int16_t *n = vn; | 111 | - return env->cp15.vttbr_el2; |
172 | + int16_t *m = vm; | 112 | - } |
173 | + CPUARMState *env = ve; | 113 | - if (ttbrn == 0) { |
174 | + uintptr_t i; | 114 | - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; |
175 | + | 115 | - } else { |
176 | + for (i = 0; i < opr_sz / 2; ++i) { | 116 | - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; |
177 | + d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); | 117 | - } |
178 | + } | 118 | -} |
179 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 119 | - |
180 | +} | 120 | /* Return true if the translation regime is using LPAE format page tables */ |
181 | + | 121 | static inline bool regime_using_lpae_format(CPUARMState *env, |
182 | /* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ | 122 | ARMMMUIdx mmu_idx) |
183 | static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, | 123 | @@ -XXX,XX +XXX,XX @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) |
184 | int16_t src2, int16_t src3) | 124 | return regime_using_lpae_format(env, mmu_idx); |
185 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, | ||
186 | return deposit32(e1, 16, 16, e2); | ||
187 | } | 125 | } |
188 | 126 | ||
189 | +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, | 127 | +#ifndef CONFIG_USER_ONLY |
190 | + void *ve, uint32_t desc) | 128 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
191 | +{ | 129 | { |
192 | + uintptr_t opr_sz = simd_oprsz(desc); | 130 | switch (mmu_idx) { |
193 | + int16_t *d = vd; | 131 | @@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) |
194 | + int16_t *n = vn; | 132 | |
195 | + int16_t *m = vm; | 133 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; |
196 | + CPUARMState *env = ve; | 134 | } |
197 | + uintptr_t i; | 135 | +#endif /* !CONFIG_USER_ONLY */ |
198 | + | 136 | |
199 | + for (i = 0; i < opr_sz / 2; ++i) { | 137 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, |
200 | + d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]); | 138 | ARMMMUIdx mmu_idx) |
201 | + } | 139 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
202 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
203 | +} | ||
204 | + | ||
205 | /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ | ||
206 | uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
207 | int32_t src2, int32_t src3) | ||
208 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, | ||
209 | return ret; | 140 | return ret; |
210 | } | 141 | } |
211 | 142 | ||
212 | +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, | 143 | +#ifndef CONFIG_USER_ONLY |
213 | + void *ve, uint32_t desc) | 144 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
214 | +{ | 145 | ARMMMUIdx mmu_idx) |
215 | + uintptr_t opr_sz = simd_oprsz(desc); | 146 | { |
216 | + int32_t *d = vd; | 147 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
217 | + int32_t *n = vn; | 148 | *pc = env->pc; |
218 | + int32_t *m = vm; | 149 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); |
219 | + CPUARMState *env = ve; | 150 | |
220 | + uintptr_t i; | 151 | -#ifndef CONFIG_USER_ONLY |
221 | + | 152 | - /* |
222 | + for (i = 0; i < opr_sz / 4; ++i) { | 153 | - * Get control bits for tagged addresses. Note that the |
223 | + d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); | 154 | - * translator only uses this for instruction addresses. |
224 | + } | 155 | - */ |
225 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | 156 | + /* Get control bits for tagged addresses. */ |
226 | +} | 157 | { |
227 | + | 158 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
228 | /* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ | 159 | ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); |
229 | uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | 160 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
230 | int32_t src2, int32_t src3) | 161 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); |
231 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, | 162 | flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); |
232 | } | 163 | } |
233 | return ret; | 164 | -#endif |
234 | } | 165 | |
235 | + | 166 | if (cpu_isar_feature(aa64_sve, cpu)) { |
236 | +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, | 167 | int sve_el = sve_exception_el(env, current_el); |
237 | + void *ve, uint32_t desc) | ||
238 | +{ | ||
239 | + uintptr_t opr_sz = simd_oprsz(desc); | ||
240 | + int32_t *d = vd; | ||
241 | + int32_t *n = vn; | ||
242 | + int32_t *m = vm; | ||
243 | + CPUARMState *env = ve; | ||
244 | + uintptr_t i; | ||
245 | + | ||
246 | + for (i = 0; i < opr_sz / 4; ++i) { | ||
247 | + d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); | ||
248 | + } | ||
249 | + clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
250 | +} | ||
251 | -- | 168 | -- |
252 | 2.16.2 | 169 | 2.20.1 |
253 | 170 | ||
254 | 171 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable it for the "any" CPU used by *-linux-user. | 3 | This has been enabled in the linux kernel since v3.11 |
4 | (commit d50240a5f6cea, 2013-09-03, | ||
5 | "arm64: mm: permit use of tagged pointers at EL0"). | ||
4 | 6 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: 20190204132126.3255-5-richard.henderson@linaro.org |
7 | Message-id: 20180228193125.20577-10-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | target/arm/cpu.c | 1 + | 12 | target/arm/cpu.c | 6 ++++++ |
11 | target/arm/cpu64.c | 1 + | 13 | 1 file changed, 6 insertions(+) |
12 | 2 files changed, 2 insertions(+) | ||
13 | 14 | ||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 15 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.c | 17 | --- a/target/arm/cpu.c |
17 | +++ b/target/arm/cpu.c | 18 | +++ b/target/arm/cpu.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_any_initfn(Object *obj) | 19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) |
19 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | 20 | env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; |
20 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | 21 | env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; |
21 | set_feature(&cpu->env, ARM_FEATURE_CRC); | 22 | env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; |
22 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | 23 | + /* |
23 | cpu->midr = 0xffffffff; | 24 | + * Enable TBI0 and TBI1. While the real kernel only enables TBI0, |
24 | } | 25 | + * turning on both here will produce smaller code and otherwise |
25 | #endif | 26 | + * make no difference to the user-level emulation. |
26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 27 | + */ |
27 | index XXXXXXX..XXXXXXX 100644 | 28 | + env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); |
28 | --- a/target/arm/cpu64.c | 29 | #else |
29 | +++ b/target/arm/cpu64.c | 30 | /* Reset into the highest available EL */ |
30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj) | 31 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
31 | set_feature(&cpu->env, ARM_FEATURE_V8_SM4); | ||
32 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
33 | set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
34 | + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); | ||
35 | set_feature(&cpu->env, ARM_FEATURE_V8_FP16); | ||
36 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
37 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
38 | -- | 32 | -- |
39 | 2.16.2 | 33 | 2.20.1 |
40 | 34 | ||
41 | 35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Max Filippov <jcmvbkbc@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | With multiprocess extensions gdb uses 'vKill' packet instead of 'k' to |
4 | Message-id: 20180228193125.20577-15-richard.henderson@linaro.org | 4 | kill the inferior. Handle 'vKill' the same way 'k' was handled in the |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | presence of single process. |
6 | |||
7 | Fixes: 7cf48f6752e5 ("gdbstub: add multiprocess support to | ||
8 | (f|s)ThreadInfo and ThreadExtraInfo") | ||
9 | |||
10 | Cc: Luc Michel <luc.michel@greensocs.com> | ||
11 | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | ||
12 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
13 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
14 | Tested-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
15 | Message-id: 20190130192403.13754-1-jcmvbkbc@gmail.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 17 | --- |
8 | target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 18 | gdbstub.c | 4 ++++ |
9 | 1 file changed, 61 insertions(+) | 19 | 1 file changed, 4 insertions(+) |
10 | 20 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 21 | diff --git a/gdbstub.c b/gdbstub.c |
12 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 23 | --- a/gdbstub.c |
14 | +++ b/target/arm/translate.c | 24 | +++ b/gdbstub.c |
15 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | 25 | @@ -XXX,XX +XXX,XX @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) |
16 | return 0; | 26 | |
17 | } | 27 | put_packet(s, buf); |
18 | 28 | break; | |
19 | +/* Advanced SIMD two registers and a scalar extension. | 29 | + } else if (strncmp(p, "Kill;", 5) == 0) { |
20 | + * 31 24 23 22 20 16 12 11 10 9 8 3 0 | 30 | + /* Kill the target */ |
21 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | 31 | + error_report("QEMU: Terminated via GDBstub"); |
22 | + * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | 32 | + exit(0); |
23 | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | 33 | } else { |
24 | + * | 34 | goto unknown_command; |
25 | + */ | 35 | } |
26 | + | ||
27 | +static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | ||
28 | +{ | ||
29 | + int rd, rn, rm, rot, size, opr_sz; | ||
30 | + TCGv_ptr fpst; | ||
31 | + bool q; | ||
32 | + | ||
33 | + q = extract32(insn, 6, 1); | ||
34 | + VFP_DREG_D(rd, insn); | ||
35 | + VFP_DREG_N(rn, insn); | ||
36 | + VFP_DREG_M(rm, insn); | ||
37 | + if ((rd | rn) & q) { | ||
38 | + return 1; | ||
39 | + } | ||
40 | + | ||
41 | + if ((insn & 0xff000f10) == 0xfe000800) { | ||
42 | + /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ | ||
43 | + rot = extract32(insn, 20, 2); | ||
44 | + size = extract32(insn, 23, 1); | ||
45 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) | ||
46 | + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { | ||
47 | + return 1; | ||
48 | + } | ||
49 | + } else { | ||
50 | + return 1; | ||
51 | + } | ||
52 | + | ||
53 | + if (s->fp_excp_el) { | ||
54 | + gen_exception_insn(s, 4, EXCP_UDEF, | ||
55 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
56 | + return 0; | ||
57 | + } | ||
58 | + if (!s->vfp_enabled) { | ||
59 | + return 1; | ||
60 | + } | ||
61 | + | ||
62 | + opr_sz = (1 + q) * 8; | ||
63 | + fpst = get_fpstatus_ptr(1); | ||
64 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), | ||
65 | + vfp_reg_offset(1, rn), | ||
66 | + vfp_reg_offset(1, rm), fpst, | ||
67 | + opr_sz, opr_sz, rot, | ||
68 | + size ? gen_helper_gvec_fcmlas_idx | ||
69 | + : gen_helper_gvec_fcmlah_idx); | ||
70 | + tcg_temp_free_ptr(fpst); | ||
71 | + return 0; | ||
72 | +} | ||
73 | + | ||
74 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | ||
75 | { | ||
76 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
77 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
78 | goto illegal_op; | ||
79 | } | ||
80 | return; | ||
81 | + } else if ((insn & 0x0f000a00) == 0x0e000800 | ||
82 | + && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
83 | + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
84 | + goto illegal_op; | ||
85 | + } | ||
86 | + return; | ||
87 | } else if ((insn & 0x0fe00000) == 0x0c400000) { | ||
88 | /* Coprocessor double register transfer. */ | ||
89 | ARCH(5TE); | ||
90 | -- | 36 | -- |
91 | 2.16.2 | 37 | 2.20.1 |
92 | 38 | ||
93 | 39 | diff view generated by jsdifflib |
1 | Instead of loading kernels, device trees, and the like to | 1 | Fix the block comment style in arm_load_kernel() to QEMU's |
---|---|---|---|
2 | the system address space, use the CPU's address space. This | 2 | current style preferences. This will allow us to do some |
3 | is important if we're trying to load the file to memory or | 3 | refactoring of this function without checkpatch complaining |
4 | via an alias memory region that is provided by an SoC | 4 | about the code-motion patches. |
5 | object and thus not mapped into the system address space. | ||
6 | 5 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-3-peter.maydell@linaro.org | 8 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
9 | Message-id: 20190131112240.8395-2-peter.maydell@linaro.org | ||
11 | --- | 10 | --- |
12 | hw/arm/boot.c | 119 +++++++++++++++++++++++++++++++++++++--------------------- | 11 | hw/arm/boot.c | 30 ++++++++++++++++++++---------- |
13 | 1 file changed, 76 insertions(+), 43 deletions(-) | 12 | 1 file changed, 20 insertions(+), 10 deletions(-) |
14 | 13 | ||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/boot.c | 16 | --- a/hw/arm/boot.c |
18 | +++ b/hw/arm/boot.c | 17 | +++ b/hw/arm/boot.c |
19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
20 | #define ARM64_TEXT_OFFSET_OFFSET 8 | 19 | static const ARMInsnFixup *primary_loader; |
21 | #define ARM64_MAGIC_OFFSET 56 | 20 | AddressSpace *as = arm_boot_address_space(cpu, info); |
22 | 21 | ||
23 | +static AddressSpace *arm_boot_address_space(ARMCPU *cpu, | 22 | - /* CPU objects (unlike devices) are not automatically reset on system |
24 | + const struct arm_boot_info *info) | 23 | + /* |
25 | +{ | 24 | + * CPU objects (unlike devices) are not automatically reset on system |
26 | + /* Return the address space to use for bootloader reads and writes. | 25 | * reset, so we must always register a handler to do so. If we're |
27 | + * We prefer the secure address space if the CPU has it and we're | 26 | * actually loading a kernel, the handler is also responsible for |
28 | + * going to boot the guest into it. | 27 | * arranging that we start it correctly. |
29 | + */ | 28 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
30 | + int asidx; | 29 | qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); |
31 | + CPUState *cs = CPU(cpu); | ||
32 | + | ||
33 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { | ||
34 | + asidx = ARMASIdx_S; | ||
35 | + } else { | ||
36 | + asidx = ARMASIdx_NS; | ||
37 | + } | ||
38 | + | ||
39 | + return cpu_get_address_space(cs, asidx); | ||
40 | +} | ||
41 | + | ||
42 | typedef enum { | ||
43 | FIXUP_NONE = 0, /* do nothing */ | ||
44 | FIXUP_TERMINATOR, /* end of insns */ | ||
45 | @@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup smpboot[] = { | ||
46 | }; | ||
47 | |||
48 | static void write_bootloader(const char *name, hwaddr addr, | ||
49 | - const ARMInsnFixup *insns, uint32_t *fixupcontext) | ||
50 | + const ARMInsnFixup *insns, uint32_t *fixupcontext, | ||
51 | + AddressSpace *as) | ||
52 | { | ||
53 | /* Fix up the specified bootloader fragment and write it into | ||
54 | * guest memory using rom_add_blob_fixed(). fixupcontext is | ||
55 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr, | ||
56 | code[i] = tswap32(insn); | ||
57 | } | 30 | } |
58 | 31 | ||
59 | - rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr); | 32 | - /* The board code is not supposed to set secure_board_setup unless |
60 | + rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); | 33 | + /* |
61 | 34 | + * The board code is not supposed to set secure_board_setup unless | |
62 | g_free(code); | 35 | * running its code in secure mode is actually possible, and KVM |
63 | } | 36 | * doesn't support secure. |
64 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
65 | const struct arm_boot_info *info) | ||
66 | { | ||
67 | uint32_t fixupcontext[FIXUP_MAX]; | ||
68 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
69 | |||
70 | fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; | ||
71 | fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; | ||
72 | @@ -XXX,XX +XXX,XX @@ static void default_write_secondary(ARMCPU *cpu, | ||
73 | } | ||
74 | |||
75 | write_bootloader("smpboot", info->smp_loader_start, | ||
76 | - smpboot, fixupcontext); | ||
77 | + smpboot, fixupcontext, as); | ||
78 | } | ||
79 | |||
80 | void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
81 | const struct arm_boot_info *info, | ||
82 | hwaddr mvbar_addr) | ||
83 | { | ||
84 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
85 | int n; | ||
86 | uint32_t mvbar_blob[] = { | ||
87 | /* mvbar_addr: secure monitor vectors | ||
88 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
89 | for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { | ||
90 | mvbar_blob[n] = tswap32(mvbar_blob[n]); | ||
91 | } | ||
92 | - rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
93 | - mvbar_addr); | ||
94 | + rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), | ||
95 | + mvbar_addr, as); | ||
96 | |||
97 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | ||
98 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | ||
99 | } | ||
100 | - rom_add_blob_fixed("board-setup", board_setup_blob, | ||
101 | - sizeof(board_setup_blob), info->board_setup_addr); | ||
102 | + rom_add_blob_fixed_as("board-setup", board_setup_blob, | ||
103 | + sizeof(board_setup_blob), info->board_setup_addr, as); | ||
104 | } | ||
105 | |||
106 | static void default_reset_secondary(ARMCPU *cpu, | ||
107 | const struct arm_boot_info *info) | ||
108 | { | ||
109 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
110 | CPUState *cs = CPU(cpu); | ||
111 | |||
112 | - address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, | ||
113 | + address_space_stl_notdirty(as, info->smp_bootreg_addr, | ||
114 | 0, MEMTXATTRS_UNSPECIFIED, NULL); | ||
115 | cpu_set_pc(cs, info->smp_loader_start); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static inline bool have_dtb(const struct arm_boot_info *info) | ||
118 | } | ||
119 | |||
120 | #define WRITE_WORD(p, value) do { \ | ||
121 | - address_space_stl_notdirty(&address_space_memory, p, value, \ | ||
122 | + address_space_stl_notdirty(as, p, value, \ | ||
123 | MEMTXATTRS_UNSPECIFIED, NULL); \ | ||
124 | p += 4; \ | ||
125 | } while (0) | ||
126 | |||
127 | -static void set_kernel_args(const struct arm_boot_info *info) | ||
128 | +static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) | ||
129 | { | ||
130 | int initrd_size = info->initrd_size; | ||
131 | hwaddr base = info->loader_start; | ||
132 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
133 | int cmdline_size; | ||
134 | |||
135 | cmdline_size = strlen(info->kernel_cmdline); | ||
136 | - cpu_physical_memory_write(p + 8, info->kernel_cmdline, | ||
137 | - cmdline_size + 1); | ||
138 | + address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, | ||
139 | + (const uint8_t *)info->kernel_cmdline, | ||
140 | + cmdline_size + 1); | ||
141 | cmdline_size = (cmdline_size >> 2) + 1; | ||
142 | WRITE_WORD(p, cmdline_size + 2); | ||
143 | WRITE_WORD(p, 0x54410009); | ||
144 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
145 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; | ||
146 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | ||
147 | WRITE_WORD(p, 0x414f4d50); | ||
148 | - cpu_physical_memory_write(p, atag_board_buf, atag_board_len); | ||
149 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
150 | + atag_board_buf, atag_board_len); | ||
151 | p += atag_board_len; | ||
152 | } | ||
153 | /* ATAG_END */ | ||
154 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args(const struct arm_boot_info *info) | ||
155 | WRITE_WORD(p, 0); | ||
156 | } | ||
157 | |||
158 | -static void set_kernel_args_old(const struct arm_boot_info *info) | ||
159 | +static void set_kernel_args_old(const struct arm_boot_info *info, | ||
160 | + AddressSpace *as) | ||
161 | { | ||
162 | hwaddr p; | ||
163 | const char *s; | ||
164 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info) | ||
165 | } | ||
166 | s = info->kernel_cmdline; | ||
167 | if (s) { | ||
168 | - cpu_physical_memory_write(p, s, strlen(s) + 1); | ||
169 | + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, | ||
170 | + (const uint8_t *)s, strlen(s) + 1); | ||
171 | } else { | ||
172 | WRITE_WORD(p, 0); | ||
173 | } | ||
174 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
175 | * @addr: the address to load the image at | ||
176 | * @binfo: struct describing the boot environment | ||
177 | * @addr_limit: upper limit of the available memory area at @addr | ||
178 | + * @as: address space to load image to | ||
179 | * | ||
180 | * Load a device tree supplied by the machine or by the user with the | ||
181 | * '-dtb' command line option, and put it at offset @addr in target | ||
182 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
183 | * Note: Must not be called unless have_dtb(binfo) is true. | ||
184 | */ | ||
185 | static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
186 | - hwaddr addr_limit) | ||
187 | + hwaddr addr_limit, AddressSpace *as) | ||
188 | { | ||
189 | void *fdt = NULL; | ||
190 | int size, rc; | ||
191 | @@ -XXX,XX +XXX,XX @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
192 | /* Put the DTB into the memory map as a ROM image: this will ensure | ||
193 | * the DTB is copied again upon reset, even if addr points into RAM. | ||
194 | */ | 37 | */ |
195 | - rom_add_blob_fixed("dtb", fdt, size, addr); | 38 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
196 | + rom_add_blob_fixed_as("dtb", fdt, size, addr, as); | 39 | if (!info->kernel_filename || info->firmware_loaded) { |
197 | 40 | ||
198 | g_free(fdt); | 41 | if (have_dtb(info)) { |
199 | 42 | - /* If we have a device tree blob, but no kernel to supply it to (or | |
200 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | 43 | + /* |
201 | } | 44 | + * If we have a device tree blob, but no kernel to supply it to (or |
202 | |||
203 | if (cs == first_cpu) { | ||
204 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
205 | + | ||
206 | cpu_set_pc(cs, info->loader_start); | ||
207 | |||
208 | if (!have_dtb(info)) { | ||
209 | if (old_param) { | ||
210 | - set_kernel_args_old(info); | ||
211 | + set_kernel_args_old(info, as); | ||
212 | } else { | ||
213 | - set_kernel_args(info); | ||
214 | + set_kernel_args(info, as); | ||
215 | } | ||
216 | } | ||
217 | } else { | ||
218 | @@ -XXX,XX +XXX,XX @@ static int do_arm_linux_init(Object *obj, void *opaque) | ||
219 | |||
220 | static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
221 | uint64_t *lowaddr, uint64_t *highaddr, | ||
222 | - int elf_machine) | ||
223 | + int elf_machine, AddressSpace *as) | ||
224 | { | ||
225 | bool elf_is64; | ||
226 | union { | ||
227 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
228 | } | ||
229 | } | ||
230 | |||
231 | - ret = load_elf(info->kernel_filename, NULL, NULL, | ||
232 | - pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
233 | - 1, data_swab); | ||
234 | + ret = load_elf_as(info->kernel_filename, NULL, NULL, | ||
235 | + pentry, lowaddr, highaddr, big_endian, elf_machine, | ||
236 | + 1, data_swab, as); | ||
237 | if (ret <= 0) { | ||
238 | /* The header loaded but the image didn't */ | ||
239 | exit(1); | ||
240 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, | ||
241 | } | ||
242 | |||
243 | static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
244 | - hwaddr *entry) | ||
245 | + hwaddr *entry, AddressSpace *as) | ||
246 | { | ||
247 | hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; | ||
248 | uint8_t *buffer; | ||
249 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
250 | } | ||
251 | |||
252 | *entry = mem_base + kernel_load_offset; | ||
253 | - rom_add_blob_fixed(filename, buffer, size, *entry); | ||
254 | + rom_add_blob_fixed_as(filename, buffer, size, *entry, as); | ||
255 | |||
256 | g_free(buffer); | ||
257 | |||
258 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
259 | ARMCPU *cpu = n->cpu; | ||
260 | struct arm_boot_info *info = | ||
261 | container_of(n, struct arm_boot_info, load_kernel_notifier); | ||
262 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
263 | |||
264 | /* The board code is not supposed to set secure_board_setup unless | ||
265 | * running its code in secure mode is actually possible, and KVM | ||
266 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
267 | * the kernel is supposed to be loaded by the bootloader), copy the | 45 | * the kernel is supposed to be loaded by the bootloader), copy the |
268 | * DTB to the base of RAM for the bootloader to pick up. | 46 | * DTB to the base of RAM for the bootloader to pick up. |
269 | */ | 47 | */ |
270 | - if (load_dtb(info->loader_start, info, 0) < 0) { | 48 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
271 | + if (load_dtb(info->loader_start, info, 0, as) < 0) { | 49 | try_decompressing_kernel = arm_feature(&cpu->env, |
272 | exit(1); | 50 | ARM_FEATURE_AARCH64); |
51 | |||
52 | - /* Expose the kernel, the command line, and the initrd in fw_cfg. | ||
53 | + /* | ||
54 | + * Expose the kernel, the command line, and the initrd in fw_cfg. | ||
55 | * We don't process them here at all, it's all left to the | ||
56 | * firmware. | ||
57 | */ | ||
58 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
273 | } | 59 | } |
274 | } | 60 | } |
275 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | 61 | |
276 | 62 | - /* We will start from address 0 (typically a boot ROM image) in the | |
277 | /* Assume that raw images are linux kernels, and ELF images are not. */ | 63 | + /* |
64 | + * We will start from address 0 (typically a boot ROM image) in the | ||
65 | * same way as hardware. | ||
66 | */ | ||
67 | return; | ||
68 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
69 | if (info->nb_cpus == 0) | ||
70 | info->nb_cpus = 1; | ||
71 | |||
72 | - /* We want to put the initrd far enough into RAM that when the | ||
73 | + /* | ||
74 | + * We want to put the initrd far enough into RAM that when the | ||
75 | * kernel is uncompressed it will not clobber the initrd. However | ||
76 | * on boards without much RAM we must ensure that we still leave | ||
77 | * enough room for a decent sized initrd, and on boards with large | ||
78 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
278 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | 79 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, |
279 | - &elf_high_addr, elf_machine); | 80 | &elf_high_addr, elf_machine, as); |
280 | + &elf_high_addr, elf_machine, as); | ||
281 | if (kernel_size > 0 && have_dtb(info)) { | 81 | if (kernel_size > 0 && have_dtb(info)) { |
282 | /* If there is still some room left at the base of RAM, try and put | 82 | - /* If there is still some room left at the base of RAM, try and put |
83 | + /* | ||
84 | + * If there is still some room left at the base of RAM, try and put | ||
283 | * the DTB there like we do for images loaded with -bios or -pflash. | 85 | * the DTB there like we do for images loaded with -bios or -pflash. |
284 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | 86 | */ |
87 | if (elf_low_addr > info->loader_start | ||
88 | || elf_high_addr < info->loader_start) { | ||
89 | - /* Set elf_low_addr as address limit for arm_load_dtb if it may be | ||
90 | + /* | ||
91 | + * Set elf_low_addr as address limit for arm_load_dtb if it may be | ||
92 | * pointing into RAM, otherwise pass '0' (no limit) | ||
93 | */ | ||
285 | if (elf_low_addr < info->loader_start) { | 94 | if (elf_low_addr < info->loader_start) { |
286 | elf_low_addr = 0; | 95 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
287 | } | 96 | fixupcontext[FIXUP_BOARDID] = info->board_id; |
288 | - if (load_dtb(info->loader_start, info, elf_low_addr) < 0) { | 97 | fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; |
289 | + if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) { | 98 | |
290 | exit(1); | 99 | - /* for device tree boot, we pass the DTB directly in r2. Otherwise |
291 | } | 100 | + /* |
101 | + * for device tree boot, we pass the DTB directly in r2. Otherwise | ||
102 | * we point to the kernel args. | ||
103 | */ | ||
104 | if (have_dtb(info)) { | ||
105 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
106 | info->write_board_setup(cpu, info); | ||
292 | } | 107 | } |
293 | } | 108 | |
294 | entry = elf_entry; | 109 | - /* Notify devices which need to fake up firmware initialization |
295 | if (kernel_size < 0) { | 110 | + /* |
296 | - kernel_size = load_uimage(info->kernel_filename, &entry, NULL, | 111 | + * Notify devices which need to fake up firmware initialization |
297 | - &is_linux, NULL, NULL); | 112 | * that we're doing a direct kernel boot. |
298 | + kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, | 113 | */ |
299 | + &is_linux, NULL, NULL, as); | 114 | object_child_foreach_recursive(object_get_root(), |
300 | } | ||
301 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { | ||
302 | kernel_size = load_aarch64_image(info->kernel_filename, | ||
303 | - info->loader_start, &entry); | ||
304 | + info->loader_start, &entry, as); | ||
305 | is_linux = 1; | ||
306 | } else if (kernel_size < 0) { | ||
307 | /* 32-bit ARM */ | ||
308 | entry = info->loader_start + KERNEL_LOAD_ADDR; | ||
309 | - kernel_size = load_image_targphys(info->kernel_filename, entry, | ||
310 | - info->ram_size - KERNEL_LOAD_ADDR); | ||
311 | + kernel_size = load_image_targphys_as(info->kernel_filename, entry, | ||
312 | + info->ram_size - KERNEL_LOAD_ADDR, | ||
313 | + as); | ||
314 | is_linux = 1; | ||
315 | } | ||
316 | if (kernel_size < 0) { | ||
317 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
318 | uint32_t fixupcontext[FIXUP_MAX]; | ||
319 | |||
320 | if (info->initrd_filename) { | ||
321 | - initrd_size = load_ramdisk(info->initrd_filename, | ||
322 | - info->initrd_start, | ||
323 | - info->ram_size - | ||
324 | - info->initrd_start); | ||
325 | + initrd_size = load_ramdisk_as(info->initrd_filename, | ||
326 | + info->initrd_start, | ||
327 | + info->ram_size - info->initrd_start, | ||
328 | + as); | ||
329 | if (initrd_size < 0) { | ||
330 | - initrd_size = load_image_targphys(info->initrd_filename, | ||
331 | - info->initrd_start, | ||
332 | - info->ram_size - | ||
333 | - info->initrd_start); | ||
334 | + initrd_size = load_image_targphys_as(info->initrd_filename, | ||
335 | + info->initrd_start, | ||
336 | + info->ram_size - | ||
337 | + info->initrd_start, | ||
338 | + as); | ||
339 | } | ||
340 | if (initrd_size < 0) { | ||
341 | error_report("could not load initrd '%s'", | ||
342 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
343 | |||
344 | /* Place the DTB after the initrd in memory with alignment. */ | ||
345 | dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); | ||
346 | - if (load_dtb(dtb_start, info, 0) < 0) { | ||
347 | + if (load_dtb(dtb_start, info, 0, as) < 0) { | ||
348 | exit(1); | ||
349 | } | ||
350 | fixupcontext[FIXUP_ARGPTR] = dtb_start; | ||
351 | @@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) | ||
352 | fixupcontext[FIXUP_ENTRYPOINT] = entry; | ||
353 | |||
354 | write_bootloader("bootloader", info->loader_start, | ||
355 | - primary_loader, fixupcontext); | ||
356 | + primary_loader, fixupcontext, as); | ||
357 | |||
358 | if (info->nb_cpus > 1) { | ||
359 | info->write_secondary_boot(cpu, info); | ||
360 | -- | 115 | -- |
361 | 2.16.2 | 116 | 2.20.1 |
362 | 117 | ||
363 | 118 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Instead of loading guest images to the system address space, use the | ||
2 | CPU's address space. This is important if we're trying to load the | ||
3 | file to memory or via an alias memory region that is provided by an | ||
4 | SoC object and thus not mapped into the system address space. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/arm/armv7m.c | 17 ++++++++++++++--- | ||
12 | 1 file changed, 14 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/armv7m.c | ||
17 | +++ b/hw/arm/armv7m.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
19 | uint64_t entry; | ||
20 | uint64_t lowaddr; | ||
21 | int big_endian; | ||
22 | + AddressSpace *as; | ||
23 | + int asidx; | ||
24 | + CPUState *cs = CPU(cpu); | ||
25 | |||
26 | #ifdef TARGET_WORDS_BIGENDIAN | ||
27 | big_endian = 1; | ||
28 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
29 | exit(1); | ||
30 | } | ||
31 | |||
32 | + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | ||
33 | + asidx = ARMASIdx_S; | ||
34 | + } else { | ||
35 | + asidx = ARMASIdx_NS; | ||
36 | + } | ||
37 | + as = cpu_get_address_space(cs, asidx); | ||
38 | + | ||
39 | if (kernel_filename) { | ||
40 | - image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
41 | - NULL, big_endian, EM_ARM, 1, 0); | ||
42 | + image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr, | ||
43 | + NULL, big_endian, EM_ARM, 1, 0, as); | ||
44 | if (image_size < 0) { | ||
45 | - image_size = load_image_targphys(kernel_filename, 0, mem_size); | ||
46 | + image_size = load_image_targphys_as(kernel_filename, 0, | ||
47 | + mem_size, as); | ||
48 | lowaddr = 0; | ||
49 | } | ||
50 | if (image_size < 0) { | ||
51 | -- | ||
52 | 2.16.2 | ||
53 | |||
54 | diff view generated by jsdifflib |
1 | Define a new board model for the MPS2 with an AN505 FPGA image | 1 | Factor out the "direct kernel boot" code path from arm_load_kernel() |
---|---|---|---|
2 | containing a Cortex-M33. Since the FPGA images for TrustZone | 2 | into its own function; this function is getting long enough that |
3 | cores (AN505, and the similar AN519 for Cortex-M23) have a | 3 | the code flow is a bit confusing. |
4 | significantly different layout of devices to the non-TrustZone | 4 | |
5 | images, we use a new source file rather than shoehorning them | 5 | This commit only moves code around; no semantic changes. |
6 | into the existing mps2.c. | 6 | |
7 | We leave the "load the dtb" code in arm_load_kernel() -- this | ||
8 | is currently only used by the "direct kernel boot" path, but | ||
9 | this is a bug which we will fix shortly. | ||
7 | 10 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180220180325.29818-20-peter.maydell@linaro.org | 13 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
14 | Message-id: 20190131112240.8395-3-peter.maydell@linaro.org | ||
11 | --- | 15 | --- |
12 | hw/arm/Makefile.objs | 1 + | 16 | hw/arm/boot.c | 150 +++++++++++++++++++++++++++----------------------- |
13 | hw/arm/mps2-tz.c | 503 +++++++++++++++++++++++++++++++++++++++++++++++++++ | 17 | 1 file changed, 80 insertions(+), 70 deletions(-) |
14 | 2 files changed, 504 insertions(+) | ||
15 | create mode 100644 hw/arm/mps2-tz.c | ||
16 | 18 | ||
17 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 19 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/Makefile.objs | 21 | --- a/hw/arm/boot.c |
20 | +++ b/hw/arm/Makefile.objs | 22 | +++ b/hw/arm/boot.c |
21 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | 23 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, |
22 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 24 | return size; |
23 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 25 | } |
24 | obj-$(CONFIG_MPS2) += mps2.o | 26 | |
25 | +obj-$(CONFIG_MPS2) += mps2-tz.o | 27 | -void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
26 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 28 | +static void arm_setup_direct_kernel_boot(ARMCPU *cpu, |
27 | obj-$(CONFIG_IOTKIT) += iotkit.o | 29 | + struct arm_boot_info *info) |
28 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 30 | { |
29 | new file mode 100644 | 31 | + /* Set up for a direct boot of a kernel image file. */ |
30 | index XXXXXXX..XXXXXXX | 32 | CPUState *cs; |
31 | --- /dev/null | 33 | + AddressSpace *as = arm_boot_address_space(cpu, info); |
32 | +++ b/hw/arm/mps2-tz.c | 34 | int kernel_size; |
33 | @@ -XXX,XX +XXX,XX @@ | 35 | int initrd_size; |
34 | +/* | 36 | int is_linux = 0; |
35 | + * ARM V2M MPS2 board emulation, trustzone aware FPGA images | 37 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
36 | + * | 38 | int elf_machine; |
37 | + * Copyright (c) 2017 Linaro Limited | 39 | hwaddr entry; |
38 | + * Written by Peter Maydell | 40 | static const ARMInsnFixup *primary_loader; |
39 | + * | 41 | - AddressSpace *as = arm_boot_address_space(cpu, info); |
40 | + * This program is free software; you can redistribute it and/or modify | 42 | - |
41 | + * it under the terms of the GNU General Public License version 2 or | 43 | - /* |
42 | + * (at your option) any later version. | 44 | - * CPU objects (unlike devices) are not automatically reset on system |
43 | + */ | 45 | - * reset, so we must always register a handler to do so. If we're |
44 | + | 46 | - * actually loading a kernel, the handler is also responsible for |
45 | +/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | 47 | - * arranging that we start it correctly. |
46 | + * FPGA but is otherwise the same as the 2). Since the CPU itself | 48 | - */ |
47 | + * and most of the devices are in the FPGA, the details of the board | 49 | - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { |
48 | + * as seen by the guest depend significantly on the FPGA image. | 50 | - qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); |
49 | + * This source file covers the following FPGA images, for TrustZone cores: | 51 | - } |
50 | + * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 | 52 | - |
51 | + * | 53 | - /* |
52 | + * Links to the TRM for the board itself and to the various Application | 54 | - * The board code is not supposed to set secure_board_setup unless |
53 | + * Notes which document the FPGA images can be found here: | 55 | - * running its code in secure mode is actually possible, and KVM |
54 | + * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | 56 | - * doesn't support secure. |
55 | + * | 57 | - */ |
56 | + * Board TRM: | 58 | - assert(!(info->secure_board_setup && kvm_enabled())); |
57 | + * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | 59 | - |
58 | + * Application Note AN505: | 60 | - info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); |
59 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | 61 | - info->dtb_limit = 0; |
60 | + * | 62 | - |
61 | + * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | 63 | - /* Load the kernel. */ |
62 | + * (ARM ECM0601256) for the details of some of the device layout: | 64 | - if (!info->kernel_filename || info->firmware_loaded) { |
63 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 65 | - |
64 | + */ | 66 | - if (have_dtb(info)) { |
65 | + | 67 | - /* |
66 | +#include "qemu/osdep.h" | 68 | - * If we have a device tree blob, but no kernel to supply it to (or |
67 | +#include "qapi/error.h" | 69 | - * the kernel is supposed to be loaded by the bootloader), copy the |
68 | +#include "qemu/error-report.h" | 70 | - * DTB to the base of RAM for the bootloader to pick up. |
69 | +#include "hw/arm/arm.h" | 71 | - */ |
70 | +#include "hw/arm/armv7m.h" | 72 | - info->dtb_start = info->loader_start; |
71 | +#include "hw/or-irq.h" | 73 | - } |
72 | +#include "hw/boards.h" | 74 | - |
73 | +#include "exec/address-spaces.h" | 75 | - if (info->kernel_filename) { |
74 | +#include "sysemu/sysemu.h" | 76 | - FWCfgState *fw_cfg; |
75 | +#include "hw/misc/unimp.h" | 77 | - bool try_decompressing_kernel; |
76 | +#include "hw/char/cmsdk-apb-uart.h" | 78 | - |
77 | +#include "hw/timer/cmsdk-apb-timer.h" | 79 | - fw_cfg = fw_cfg_find(); |
78 | +#include "hw/misc/mps2-scc.h" | 80 | - try_decompressing_kernel = arm_feature(&cpu->env, |
79 | +#include "hw/misc/mps2-fpgaio.h" | 81 | - ARM_FEATURE_AARCH64); |
80 | +#include "hw/arm/iotkit.h" | 82 | - |
81 | +#include "hw/devices.h" | 83 | - /* |
82 | +#include "net/net.h" | 84 | - * Expose the kernel, the command line, and the initrd in fw_cfg. |
83 | +#include "hw/core/split-irq.h" | 85 | - * We don't process them here at all, it's all left to the |
84 | + | 86 | - * firmware. |
85 | +typedef enum MPS2TZFPGAType { | 87 | - */ |
86 | + FPGA_AN505, | 88 | - load_image_to_fw_cfg(fw_cfg, |
87 | +} MPS2TZFPGAType; | 89 | - FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, |
88 | + | 90 | - info->kernel_filename, |
89 | +typedef struct { | 91 | - try_decompressing_kernel); |
90 | + MachineClass parent; | 92 | - load_image_to_fw_cfg(fw_cfg, |
91 | + MPS2TZFPGAType fpga_type; | 93 | - FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, |
92 | + uint32_t scc_id; | 94 | - info->initrd_filename, false); |
93 | +} MPS2TZMachineClass; | 95 | - |
94 | + | 96 | - if (info->kernel_cmdline) { |
95 | +typedef struct { | 97 | - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
96 | + MachineState parent; | 98 | - strlen(info->kernel_cmdline) + 1); |
97 | + | 99 | - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, |
98 | + IoTKit iotkit; | 100 | - info->kernel_cmdline); |
99 | + MemoryRegion psram; | 101 | - } |
100 | + MemoryRegion ssram1; | 102 | - } |
101 | + MemoryRegion ssram1_m; | 103 | - |
102 | + MemoryRegion ssram23; | 104 | - /* |
103 | + MPS2SCC scc; | 105 | - * We will start from address 0 (typically a boot ROM image) in the |
104 | + MPS2FPGAIO fpgaio; | 106 | - * same way as hardware. |
105 | + TZPPC ppc[5]; | 107 | - */ |
106 | + UnimplementedDeviceState ssram_mpc[3]; | 108 | - return; |
107 | + UnimplementedDeviceState spi[5]; | 109 | - } |
108 | + UnimplementedDeviceState i2c[4]; | 110 | |
109 | + UnimplementedDeviceState i2s_audio; | 111 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
110 | + UnimplementedDeviceState gpio[5]; | 112 | primary_loader = bootloader_aarch64; |
111 | + UnimplementedDeviceState dma[4]; | 113 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
112 | + UnimplementedDeviceState gfx; | 114 | for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { |
113 | + CMSDKAPBUART uart[5]; | 115 | ARM_CPU(cs)->env.boot_info = info; |
114 | + SplitIRQ sec_resp_splitter; | 116 | } |
115 | + qemu_or_irq uart_irq_orgate; | ||
116 | +} MPS2TZMachineState; | ||
117 | + | ||
118 | +#define TYPE_MPS2TZ_MACHINE "mps2tz" | ||
119 | +#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") | ||
120 | + | ||
121 | +#define MPS2TZ_MACHINE(obj) \ | ||
122 | + OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) | ||
123 | +#define MPS2TZ_MACHINE_GET_CLASS(obj) \ | ||
124 | + OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) | ||
125 | +#define MPS2TZ_MACHINE_CLASS(klass) \ | ||
126 | + OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) | ||
127 | + | ||
128 | +/* Main SYSCLK frequency in Hz */ | ||
129 | +#define SYSCLK_FRQ 20000000 | ||
130 | + | ||
131 | +/* Initialize the auxiliary RAM region @mr and map it into | ||
132 | + * the memory map at @base. | ||
133 | + */ | ||
134 | +static void make_ram(MemoryRegion *mr, const char *name, | ||
135 | + hwaddr base, hwaddr size) | ||
136 | +{ | ||
137 | + memory_region_init_ram(mr, NULL, name, size, &error_fatal); | ||
138 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
139 | +} | 117 | +} |
140 | + | 118 | + |
141 | +/* Create an alias of an entire original MemoryRegion @orig | 119 | +void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
142 | + * located at @base in the memory map. | ||
143 | + */ | ||
144 | +static void make_ram_alias(MemoryRegion *mr, const char *name, | ||
145 | + MemoryRegion *orig, hwaddr base) | ||
146 | +{ | 120 | +{ |
147 | + memory_region_init_alias(mr, NULL, name, orig, 0, | 121 | + CPUState *cs; |
148 | + memory_region_size(orig)); | 122 | + AddressSpace *as = arm_boot_address_space(cpu, info); |
149 | + memory_region_add_subregion(get_system_memory(), base, mr); | ||
150 | +} | ||
151 | + | 123 | + |
152 | +static void init_sysbus_child(Object *parent, const char *childname, | 124 | + /* |
153 | + void *child, size_t childsize, | 125 | + * CPU objects (unlike devices) are not automatically reset on system |
154 | + const char *childtype) | 126 | + * reset, so we must always register a handler to do so. If we're |
155 | +{ | 127 | + * actually loading a kernel, the handler is also responsible for |
156 | + object_initialize(child, childsize, childtype); | 128 | + * arranging that we start it correctly. |
157 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | ||
158 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
159 | + | ||
160 | +} | ||
161 | + | ||
162 | +/* Most of the devices in the AN505 FPGA image sit behind | ||
163 | + * Peripheral Protection Controllers. These data structures | ||
164 | + * define the layout of which devices sit behind which PPCs. | ||
165 | + * The devfn for each port is a function which creates, configures | ||
166 | + * and initializes the device, returning the MemoryRegion which | ||
167 | + * needs to be plugged into the downstream end of the PPC port. | ||
168 | + */ | ||
169 | +typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, | ||
170 | + const char *name, hwaddr size); | ||
171 | + | ||
172 | +typedef struct PPCPortInfo { | ||
173 | + const char *name; | ||
174 | + MakeDevFn *devfn; | ||
175 | + void *opaque; | ||
176 | + hwaddr addr; | ||
177 | + hwaddr size; | ||
178 | +} PPCPortInfo; | ||
179 | + | ||
180 | +typedef struct PPCInfo { | ||
181 | + const char *name; | ||
182 | + PPCPortInfo ports[TZ_NUM_PORTS]; | ||
183 | +} PPCInfo; | ||
184 | + | ||
185 | +static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | ||
186 | + void *opaque, | ||
187 | + const char *name, hwaddr size) | ||
188 | +{ | ||
189 | + /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | ||
190 | + * and return a pointer to its MemoryRegion. | ||
191 | + */ | 129 | + */ |
192 | + UnimplementedDeviceState *uds = opaque; | 130 | + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { |
193 | + | 131 | + qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); |
194 | + init_sysbus_child(OBJECT(mms), name, uds, | ||
195 | + sizeof(UnimplementedDeviceState), | ||
196 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
197 | + qdev_prop_set_string(DEVICE(uds), "name", name); | ||
198 | + qdev_prop_set_uint64(DEVICE(uds), "size", size); | ||
199 | + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | ||
200 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); | ||
201 | +} | ||
202 | + | ||
203 | +static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | ||
204 | + const char *name, hwaddr size) | ||
205 | +{ | ||
206 | + CMSDKAPBUART *uart = opaque; | ||
207 | + int i = uart - &mms->uart[0]; | ||
208 | + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; | ||
209 | + int rxirqno = i * 2; | ||
210 | + int txirqno = i * 2 + 1; | ||
211 | + int combirqno = i + 10; | ||
212 | + SysBusDevice *s; | ||
213 | + DeviceState *iotkitdev = DEVICE(&mms->iotkit); | ||
214 | + DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | ||
215 | + | ||
216 | + init_sysbus_child(OBJECT(mms), name, uart, | ||
217 | + sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); | ||
218 | + qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); | ||
219 | + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); | ||
220 | + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | ||
221 | + s = SYS_BUS_DEVICE(uart); | ||
222 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, | ||
223 | + "EXP_IRQ", txirqno)); | ||
224 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, | ||
225 | + "EXP_IRQ", rxirqno)); | ||
226 | + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); | ||
227 | + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | ||
228 | + sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, | ||
229 | + "EXP_IRQ", combirqno)); | ||
230 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); | ||
231 | +} | ||
232 | + | ||
233 | +static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | ||
234 | + const char *name, hwaddr size) | ||
235 | +{ | ||
236 | + MPS2SCC *scc = opaque; | ||
237 | + DeviceState *sccdev; | ||
238 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
239 | + | ||
240 | + object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); | ||
241 | + sccdev = DEVICE(scc); | ||
242 | + qdev_set_parent_bus(sccdev, sysbus_get_default()); | ||
243 | + qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | ||
244 | + qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); | ||
245 | + qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | ||
246 | + object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); | ||
247 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); | ||
248 | +} | ||
249 | + | ||
250 | +static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | ||
251 | + const char *name, hwaddr size) | ||
252 | +{ | ||
253 | + MPS2FPGAIO *fpgaio = opaque; | ||
254 | + | ||
255 | + object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); | ||
256 | + qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); | ||
257 | + object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); | ||
258 | + return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
259 | +} | ||
260 | + | ||
261 | +static void mps2tz_common_init(MachineState *machine) | ||
262 | +{ | ||
263 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
264 | + MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
265 | + MemoryRegion *system_memory = get_system_memory(); | ||
266 | + DeviceState *iotkitdev; | ||
267 | + DeviceState *dev_splitter; | ||
268 | + int i; | ||
269 | + | ||
270 | + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | ||
271 | + error_report("This board can only be used with CPU %s", | ||
272 | + mc->default_cpu_type); | ||
273 | + exit(1); | ||
274 | + } | 132 | + } |
275 | + | 133 | + |
276 | + init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, | 134 | + /* |
277 | + sizeof(mms->iotkit), TYPE_IOTKIT); | 135 | + * The board code is not supposed to set secure_board_setup unless |
278 | + iotkitdev = DEVICE(&mms->iotkit); | 136 | + * running its code in secure mode is actually possible, and KVM |
279 | + object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | 137 | + * doesn't support secure. |
280 | + "memory", &error_abort); | 138 | + */ |
281 | + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); | 139 | + assert(!(info->secure_board_setup && kvm_enabled())); |
282 | + qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); | ||
283 | + object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", | ||
284 | + &error_fatal); | ||
285 | + | 140 | + |
286 | + /* The sec_resp_cfg output from the IoTKit must be split into multiple | 141 | + info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); |
287 | + * lines, one for each of the PPCs we create here. | 142 | + info->dtb_limit = 0; |
288 | + */ | ||
289 | + object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), | ||
290 | + TYPE_SPLIT_IRQ); | ||
291 | + object_property_add_child(OBJECT(machine), "sec-resp-splitter", | ||
292 | + OBJECT(&mms->sec_resp_splitter), &error_abort); | ||
293 | + object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5, | ||
294 | + "num-lines", &error_fatal); | ||
295 | + object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, | ||
296 | + "realized", &error_fatal); | ||
297 | + dev_splitter = DEVICE(&mms->sec_resp_splitter); | ||
298 | + qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, | ||
299 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
300 | + | 143 | + |
301 | + /* The IoTKit sets up much of the memory layout, including | 144 | + /* Load the kernel. */ |
302 | + * the aliases between secure and non-secure regions in the | 145 | + if (!info->kernel_filename || info->firmware_loaded) { |
303 | + * address space. The FPGA itself contains: | ||
304 | + * | ||
305 | + * 0x00000000..0x003fffff SSRAM1 | ||
306 | + * 0x00400000..0x007fffff alias of SSRAM1 | ||
307 | + * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 | ||
308 | + * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices | ||
309 | + * 0x80000000..0x80ffffff 16MB PSRAM | ||
310 | + */ | ||
311 | + | 146 | + |
312 | + /* The FPGA images have an odd combination of different RAMs, | 147 | + if (have_dtb(info)) { |
313 | + * because in hardware they are different implementations and | 148 | + /* |
314 | + * connected to different buses, giving varying performance/size | 149 | + * If we have a device tree blob, but no kernel to supply it to (or |
315 | + * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | 150 | + * the kernel is supposed to be loaded by the bootloader), copy the |
316 | + * call the 16MB our "system memory", as it's the largest lump. | 151 | + * DTB to the base of RAM for the bootloader to pick up. |
317 | + */ | 152 | + */ |
318 | + memory_region_allocate_system_memory(&mms->psram, | 153 | + info->dtb_start = info->loader_start; |
319 | + NULL, "mps.ram", 0x01000000); | ||
320 | + memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); | ||
321 | + | ||
322 | + /* The SSRAM memories should all be behind Memory Protection Controllers, | ||
323 | + * but we don't implement that yet. | ||
324 | + */ | ||
325 | + make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000); | ||
326 | + make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000); | ||
327 | + | ||
328 | + make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000); | ||
329 | + | ||
330 | + /* The overflow IRQs for all UARTs are ORed together. | ||
331 | + * Tx, Rx and "combined" IRQs are sent to the NVIC separately. | ||
332 | + * Create the OR gate for this. | ||
333 | + */ | ||
334 | + object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), | ||
335 | + TYPE_OR_IRQ); | ||
336 | + object_property_add_child(OBJECT(mms), "uart-irq-orgate", | ||
337 | + OBJECT(&mms->uart_irq_orgate), &error_abort); | ||
338 | + object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", | ||
339 | + &error_fatal); | ||
340 | + object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, | ||
341 | + "realized", &error_fatal); | ||
342 | + qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | ||
343 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)); | ||
344 | + | ||
345 | + /* Most of the devices in the FPGA are behind Peripheral Protection | ||
346 | + * Controllers. The required order for initializing things is: | ||
347 | + * + initialize the PPC | ||
348 | + * + initialize, configure and realize downstream devices | ||
349 | + * + connect downstream device MemoryRegions to the PPC | ||
350 | + * + realize the PPC | ||
351 | + * + map the PPC's MemoryRegions to the places in the address map | ||
352 | + * where the downstream devices should appear | ||
353 | + * + wire up the PPC's control lines to the IoTKit object | ||
354 | + */ | ||
355 | + | ||
356 | + const PPCInfo ppcs[] = { { | ||
357 | + .name = "apb_ppcexp0", | ||
358 | + .ports = { | ||
359 | + { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0], | ||
360 | + 0x58007000, 0x1000 }, | ||
361 | + { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1], | ||
362 | + 0x58008000, 0x1000 }, | ||
363 | + { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2], | ||
364 | + 0x58009000, 0x1000 }, | ||
365 | + }, | ||
366 | + }, { | ||
367 | + .name = "apb_ppcexp1", | ||
368 | + .ports = { | ||
369 | + { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 }, | ||
370 | + { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 }, | ||
371 | + { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 }, | ||
372 | + { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 }, | ||
373 | + { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 }, | ||
374 | + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, | ||
375 | + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | ||
376 | + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | ||
377 | + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | ||
378 | + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | ||
379 | + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
380 | + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
381 | + { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
382 | + { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | ||
383 | + }, | ||
384 | + }, { | ||
385 | + .name = "apb_ppcexp2", | ||
386 | + .ports = { | ||
387 | + { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, | ||
388 | + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, | ||
389 | + 0x40301000, 0x1000 }, | ||
390 | + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, | ||
391 | + }, | ||
392 | + }, { | ||
393 | + .name = "ahb_ppcexp0", | ||
394 | + .ports = { | ||
395 | + { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, | ||
396 | + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, | ||
397 | + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
398 | + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
399 | + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
400 | + { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, | ||
401 | + }, | ||
402 | + }, { | ||
403 | + .name = "ahb_ppcexp1", | ||
404 | + .ports = { | ||
405 | + { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 }, | ||
406 | + { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 }, | ||
407 | + { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 }, | ||
408 | + { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 }, | ||
409 | + }, | ||
410 | + }, | ||
411 | + }; | ||
412 | + | ||
413 | + for (i = 0; i < ARRAY_SIZE(ppcs); i++) { | ||
414 | + const PPCInfo *ppcinfo = &ppcs[i]; | ||
415 | + TZPPC *ppc = &mms->ppc[i]; | ||
416 | + DeviceState *ppcdev; | ||
417 | + int port; | ||
418 | + char *gpioname; | ||
419 | + | ||
420 | + init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, | ||
421 | + sizeof(TZPPC), TYPE_TZ_PPC); | ||
422 | + ppcdev = DEVICE(ppc); | ||
423 | + | ||
424 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
425 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | ||
426 | + MemoryRegion *mr; | ||
427 | + char *portname; | ||
428 | + | ||
429 | + if (!pinfo->devfn) { | ||
430 | + continue; | ||
431 | + } | ||
432 | + | ||
433 | + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | ||
434 | + portname = g_strdup_printf("port[%d]", port); | ||
435 | + object_property_set_link(OBJECT(ppc), OBJECT(mr), | ||
436 | + portname, &error_fatal); | ||
437 | + g_free(portname); | ||
438 | + } | 154 | + } |
439 | + | 155 | + |
440 | + object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); | 156 | + if (info->kernel_filename) { |
157 | + FWCfgState *fw_cfg; | ||
158 | + bool try_decompressing_kernel; | ||
441 | + | 159 | + |
442 | + for (port = 0; port < TZ_NUM_PORTS; port++) { | 160 | + fw_cfg = fw_cfg_find(); |
443 | + const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | 161 | + try_decompressing_kernel = arm_feature(&cpu->env, |
162 | + ARM_FEATURE_AARCH64); | ||
444 | + | 163 | + |
445 | + if (!pinfo->devfn) { | 164 | + /* |
446 | + continue; | 165 | + * Expose the kernel, the command line, and the initrd in fw_cfg. |
166 | + * We don't process them here at all, it's all left to the | ||
167 | + * firmware. | ||
168 | + */ | ||
169 | + load_image_to_fw_cfg(fw_cfg, | ||
170 | + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | ||
171 | + info->kernel_filename, | ||
172 | + try_decompressing_kernel); | ||
173 | + load_image_to_fw_cfg(fw_cfg, | ||
174 | + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | ||
175 | + info->initrd_filename, false); | ||
176 | + | ||
177 | + if (info->kernel_cmdline) { | ||
178 | + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | ||
179 | + strlen(info->kernel_cmdline) + 1); | ||
180 | + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | ||
181 | + info->kernel_cmdline); | ||
447 | + } | 182 | + } |
448 | + sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); | ||
449 | + | ||
450 | + gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); | ||
451 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
452 | + qdev_get_gpio_in_named(ppcdev, | ||
453 | + "cfg_nonsec", | ||
454 | + port)); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_ap", ppcinfo->name); | ||
457 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | ||
458 | + qdev_get_gpio_in_named(ppcdev, | ||
459 | + "cfg_ap", port)); | ||
460 | + g_free(gpioname); | ||
461 | + } | 183 | + } |
462 | + | 184 | + |
463 | + gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); | 185 | + /* |
464 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | 186 | + * We will start from address 0 (typically a boot ROM image) in the |
465 | + qdev_get_gpio_in_named(ppcdev, | 187 | + * same way as hardware. |
466 | + "irq_enable", 0)); | 188 | + */ |
467 | + g_free(gpioname); | 189 | + return; |
468 | + gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); | 190 | + } else { |
469 | + qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | 191 | + arm_setup_direct_kernel_boot(cpu, info); |
470 | + qdev_get_gpio_in_named(ppcdev, | ||
471 | + "irq_clear", 0)); | ||
472 | + g_free(gpioname); | ||
473 | + gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); | ||
474 | + qdev_connect_gpio_out_named(ppcdev, "irq", 0, | ||
475 | + qdev_get_gpio_in_named(iotkitdev, | ||
476 | + gpioname, 0)); | ||
477 | + g_free(gpioname); | ||
478 | + | ||
479 | + qdev_connect_gpio_out(dev_splitter, i, | ||
480 | + qdev_get_gpio_in_named(ppcdev, | ||
481 | + "cfg_sec_resp", 0)); | ||
482 | + } | 192 | + } |
483 | + | 193 | |
484 | + /* In hardware this is a LAN9220; the LAN9118 is software compatible | 194 | if (!info->skip_dtb_autoload && have_dtb(info)) { |
485 | + * except that it doesn't support the checksum-offload feature. | 195 | if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { |
486 | + * The ethernet controller is not behind a PPC. | ||
487 | + */ | ||
488 | + lan9118_init(&nd_table[0], 0x42000000, | ||
489 | + qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | ||
490 | + | ||
491 | + create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); | ||
492 | + | ||
493 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | ||
494 | +} | ||
495 | + | ||
496 | +static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
497 | +{ | ||
498 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
499 | + | ||
500 | + mc->init = mps2tz_common_init; | ||
501 | + mc->max_cpus = 1; | ||
502 | +} | ||
503 | + | ||
504 | +static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | ||
505 | +{ | ||
506 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
507 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
508 | + | ||
509 | + mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; | ||
510 | + mmc->fpga_type = FPGA_AN505; | ||
511 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | ||
512 | + mmc->scc_id = 0x41040000 | (505 << 4); | ||
513 | +} | ||
514 | + | ||
515 | +static const TypeInfo mps2tz_info = { | ||
516 | + .name = TYPE_MPS2TZ_MACHINE, | ||
517 | + .parent = TYPE_MACHINE, | ||
518 | + .abstract = true, | ||
519 | + .instance_size = sizeof(MPS2TZMachineState), | ||
520 | + .class_size = sizeof(MPS2TZMachineClass), | ||
521 | + .class_init = mps2tz_class_init, | ||
522 | +}; | ||
523 | + | ||
524 | +static const TypeInfo mps2tz_an505_info = { | ||
525 | + .name = TYPE_MPS2TZ_AN505_MACHINE, | ||
526 | + .parent = TYPE_MPS2TZ_MACHINE, | ||
527 | + .class_init = mps2tz_an505_class_init, | ||
528 | +}; | ||
529 | + | ||
530 | +static void mps2tz_machine_init(void) | ||
531 | +{ | ||
532 | + type_register_static(&mps2tz_info); | ||
533 | + type_register_static(&mps2tz_an505_info); | ||
534 | +} | ||
535 | + | ||
536 | +type_init(mps2tz_machine_init); | ||
537 | -- | 196 | -- |
538 | 2.16.2 | 197 | 2.20.1 |
539 | 198 | ||
540 | 199 | diff view generated by jsdifflib |
1 | Model the Arm IoT Kit documented in | 1 | Factor out the "boot via firmware" code path from arm_load_kernel() |
---|---|---|---|
2 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 2 | into its own function. |
3 | 3 | ||
4 | The Arm IoT Kit is a subsystem which includes a CPU and some devices, | 4 | This commit only moves code around; no semantic changes. |
5 | and is intended be extended by adding extra devices to form a | ||
6 | complete system. It is used in the MPS2 board's AN505 image for the | ||
7 | Cortex-M33. | ||
8 | 5 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20180220180325.29818-19-peter.maydell@linaro.org | 8 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
9 | Message-id: 20190131112240.8395-4-peter.maydell@linaro.org | ||
12 | --- | 10 | --- |
13 | hw/arm/Makefile.objs | 1 + | 11 | hw/arm/boot.c | 92 +++++++++++++++++++++++++++------------------------ |
14 | include/hw/arm/iotkit.h | 109 ++++++++ | 12 | 1 file changed, 49 insertions(+), 43 deletions(-) |
15 | hw/arm/iotkit.c | 598 ++++++++++++++++++++++++++++++++++++++++ | ||
16 | default-configs/arm-softmmu.mak | 1 + | ||
17 | 4 files changed, 709 insertions(+) | ||
18 | create mode 100644 include/hw/arm/iotkit.h | ||
19 | create mode 100644 hw/arm/iotkit.c | ||
20 | 13 | ||
21 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
22 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/Makefile.objs | 16 | --- a/hw/arm/boot.c |
24 | +++ b/hw/arm/Makefile.objs | 17 | +++ b/hw/arm/boot.c |
25 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, |
26 | obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o | 19 | } |
27 | obj-$(CONFIG_MPS2) += mps2.o | 20 | } |
28 | obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 21 | |
29 | +obj-$(CONFIG_IOTKIT) += iotkit.o | 22 | +static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) |
30 | diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h | 23 | +{ |
31 | new file mode 100644 | 24 | + /* Set up for booting firmware (which might load a kernel via fw_cfg) */ |
32 | index XXXXXXX..XXXXXXX | ||
33 | --- /dev/null | ||
34 | +++ b/include/hw/arm/iotkit.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | +/* | ||
37 | + * ARM IoT Kit | ||
38 | + * | ||
39 | + * Copyright (c) 2018 Linaro Limited | ||
40 | + * Written by Peter Maydell | ||
41 | + * | ||
42 | + * This program is free software; you can redistribute it and/or modify | ||
43 | + * it under the terms of the GNU General Public License version 2 or | ||
44 | + * (at your option) any later version. | ||
45 | + */ | ||
46 | + | 25 | + |
47 | +/* This is a model of the Arm IoT Kit which is documented in | 26 | + if (have_dtb(info)) { |
48 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | 27 | + /* |
49 | + * It contains: | 28 | + * If we have a device tree blob, but no kernel to supply it to (or |
50 | + * a Cortex-M33 | 29 | + * the kernel is supposed to be loaded by the bootloader), copy the |
51 | + * the IDAU | 30 | + * DTB to the base of RAM for the bootloader to pick up. |
52 | + * some timers and watchdogs | 31 | + */ |
53 | + * two peripheral protection controllers | 32 | + info->dtb_start = info->loader_start; |
54 | + * a memory protection controller | ||
55 | + * a security controller | ||
56 | + * a bus fabric which arranges that some parts of the address | ||
57 | + * space are secure and non-secure aliases of each other | ||
58 | + * | ||
59 | + * QEMU interface: | ||
60 | + * + QOM property "memory" is a MemoryRegion containing the devices provided | ||
61 | + * by the board model. | ||
62 | + * + QOM property "MAINCLK" is the frequency of the main system clock | ||
63 | + * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts | ||
64 | + * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which | ||
65 | + * are wired to the NVIC lines 32 .. n+32 | ||
66 | + * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit | ||
67 | + * might provide: | ||
68 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
69 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
70 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
71 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
72 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
73 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
74 | + * might provide: | ||
75 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
76 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
77 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
78 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
79 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
80 | + */ | ||
81 | + | ||
82 | +#ifndef IOTKIT_H | ||
83 | +#define IOTKIT_H | ||
84 | + | ||
85 | +#include "hw/sysbus.h" | ||
86 | +#include "hw/arm/armv7m.h" | ||
87 | +#include "hw/misc/iotkit-secctl.h" | ||
88 | +#include "hw/misc/tz-ppc.h" | ||
89 | +#include "hw/timer/cmsdk-apb-timer.h" | ||
90 | +#include "hw/misc/unimp.h" | ||
91 | +#include "hw/or-irq.h" | ||
92 | +#include "hw/core/split-irq.h" | ||
93 | + | ||
94 | +#define TYPE_IOTKIT "iotkit" | ||
95 | +#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) | ||
96 | + | ||
97 | +/* We have an IRQ splitter and an OR gate input for each external PPC | ||
98 | + * and the 2 internal PPCs | ||
99 | + */ | ||
100 | +#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) | ||
101 | +#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) | ||
102 | + | ||
103 | +typedef struct IoTKit { | ||
104 | + /*< private >*/ | ||
105 | + SysBusDevice parent_obj; | ||
106 | + | ||
107 | + /*< public >*/ | ||
108 | + ARMv7MState armv7m; | ||
109 | + IoTKitSecCtl secctl; | ||
110 | + TZPPC apb_ppc0; | ||
111 | + TZPPC apb_ppc1; | ||
112 | + CMSDKAPBTIMER timer0; | ||
113 | + CMSDKAPBTIMER timer1; | ||
114 | + qemu_or_irq ppc_irq_orgate; | ||
115 | + SplitIRQ sec_resp_splitter; | ||
116 | + SplitIRQ ppc_irq_splitter[NUM_PPCS]; | ||
117 | + | ||
118 | + UnimplementedDeviceState dualtimer; | ||
119 | + UnimplementedDeviceState s32ktimer; | ||
120 | + | ||
121 | + MemoryRegion container; | ||
122 | + MemoryRegion alias1; | ||
123 | + MemoryRegion alias2; | ||
124 | + MemoryRegion alias3; | ||
125 | + MemoryRegion sram0; | ||
126 | + | ||
127 | + qemu_irq *exp_irqs; | ||
128 | + qemu_irq ppc0_irq; | ||
129 | + qemu_irq ppc1_irq; | ||
130 | + qemu_irq sec_resp_cfg; | ||
131 | + qemu_irq sec_resp_cfg_in; | ||
132 | + qemu_irq nsc_cfg_in; | ||
133 | + | ||
134 | + qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; | ||
135 | + | ||
136 | + uint32_t nsccfg; | ||
137 | + | ||
138 | + /* Properties */ | ||
139 | + MemoryRegion *board_memory; | ||
140 | + uint32_t exp_numirq; | ||
141 | + uint32_t mainclk_frq; | ||
142 | +} IoTKit; | ||
143 | + | ||
144 | +#endif | ||
145 | diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c | ||
146 | new file mode 100644 | ||
147 | index XXXXXXX..XXXXXXX | ||
148 | --- /dev/null | ||
149 | +++ b/hw/arm/iotkit.c | ||
150 | @@ -XXX,XX +XXX,XX @@ | ||
151 | +/* | ||
152 | + * Arm IoT Kit | ||
153 | + * | ||
154 | + * Copyright (c) 2018 Linaro Limited | ||
155 | + * Written by Peter Maydell | ||
156 | + * | ||
157 | + * This program is free software; you can redistribute it and/or modify | ||
158 | + * it under the terms of the GNU General Public License version 2 or | ||
159 | + * (at your option) any later version. | ||
160 | + */ | ||
161 | + | ||
162 | +#include "qemu/osdep.h" | ||
163 | +#include "qemu/log.h" | ||
164 | +#include "qapi/error.h" | ||
165 | +#include "trace.h" | ||
166 | +#include "hw/sysbus.h" | ||
167 | +#include "hw/registerfields.h" | ||
168 | +#include "hw/arm/iotkit.h" | ||
169 | +#include "hw/misc/unimp.h" | ||
170 | +#include "hw/arm/arm.h" | ||
171 | + | ||
172 | +/* Create an alias region of @size bytes starting at @base | ||
173 | + * which mirrors the memory starting at @orig. | ||
174 | + */ | ||
175 | +static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, | ||
176 | + hwaddr base, hwaddr size, hwaddr orig) | ||
177 | +{ | ||
178 | + memory_region_init_alias(mr, NULL, name, &s->container, orig, size); | ||
179 | + /* The alias is even lower priority than unimplemented_device regions */ | ||
180 | + memory_region_add_subregion_overlap(&s->container, base, mr, -1500); | ||
181 | +} | ||
182 | + | ||
183 | +static void init_sysbus_child(Object *parent, const char *childname, | ||
184 | + void *child, size_t childsize, | ||
185 | + const char *childtype) | ||
186 | +{ | ||
187 | + object_initialize(child, childsize, childtype); | ||
188 | + object_property_add_child(parent, childname, OBJECT(child), &error_abort); | ||
189 | + qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | ||
190 | +} | ||
191 | + | ||
192 | +static void irq_status_forwarder(void *opaque, int n, int level) | ||
193 | +{ | ||
194 | + qemu_irq destirq = opaque; | ||
195 | + | ||
196 | + qemu_set_irq(destirq, level); | ||
197 | +} | ||
198 | + | ||
199 | +static void nsccfg_handler(void *opaque, int n, int level) | ||
200 | +{ | ||
201 | + IoTKit *s = IOTKIT(opaque); | ||
202 | + | ||
203 | + s->nsccfg = level; | ||
204 | +} | ||
205 | + | ||
206 | +static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) | ||
207 | +{ | ||
208 | + /* Each of the 4 AHB and 4 APB PPCs that might be present in a | ||
209 | + * system using the IoTKit has a collection of control lines which | ||
210 | + * are provided by the security controller and which we want to | ||
211 | + * expose as control lines on the IoTKit device itself, so the | ||
212 | + * code using the IoTKit can wire them up to the PPCs. | ||
213 | + */ | ||
214 | + SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; | ||
215 | + DeviceState *iotkitdev = DEVICE(s); | ||
216 | + DeviceState *dev_secctl = DEVICE(&s->secctl); | ||
217 | + DeviceState *dev_splitter = DEVICE(splitter); | ||
218 | + char *name; | ||
219 | + | ||
220 | + name = g_strdup_printf("%s_nonsec", ppcname); | ||
221 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
222 | + g_free(name); | ||
223 | + name = g_strdup_printf("%s_ap", ppcname); | ||
224 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
225 | + g_free(name); | ||
226 | + name = g_strdup_printf("%s_irq_enable", ppcname); | ||
227 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
228 | + g_free(name); | ||
229 | + name = g_strdup_printf("%s_irq_clear", ppcname); | ||
230 | + qdev_pass_gpios(dev_secctl, iotkitdev, name); | ||
231 | + g_free(name); | ||
232 | + | ||
233 | + /* irq_status is a little more tricky, because we need to | ||
234 | + * split it so we can send it both to the security controller | ||
235 | + * and to our OR gate for the NVIC interrupt line. | ||
236 | + * Connect up the splitter's outputs, and create a GPIO input | ||
237 | + * which will pass the line state to the input splitter. | ||
238 | + */ | ||
239 | + name = g_strdup_printf("%s_irq_status", ppcname); | ||
240 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
241 | + qdev_get_gpio_in_named(dev_secctl, | ||
242 | + name, 0)); | ||
243 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
244 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); | ||
245 | + s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); | ||
246 | + qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, | ||
247 | + s->irq_status_in[ppcnum], name, 1); | ||
248 | + g_free(name); | ||
249 | +} | ||
250 | + | ||
251 | +static void iotkit_forward_sec_resp_cfg(IoTKit *s) | ||
252 | +{ | ||
253 | + /* Forward the 3rd output from the splitter device as a | ||
254 | + * named GPIO output of the iotkit object. | ||
255 | + */ | ||
256 | + DeviceState *dev = DEVICE(s); | ||
257 | + DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
258 | + | ||
259 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
260 | + s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, | ||
261 | + s->sec_resp_cfg, 1); | ||
262 | + qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); | ||
263 | +} | ||
264 | + | ||
265 | +static void iotkit_init(Object *obj) | ||
266 | +{ | ||
267 | + IoTKit *s = IOTKIT(obj); | ||
268 | + int i; | ||
269 | + | ||
270 | + memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); | ||
271 | + | ||
272 | + init_sysbus_child(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), | ||
273 | + TYPE_ARMV7M); | ||
274 | + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", | ||
275 | + ARM_CPU_TYPE_NAME("cortex-m33")); | ||
276 | + | ||
277 | + init_sysbus_child(obj, "secctl", &s->secctl, sizeof(s->secctl), | ||
278 | + TYPE_IOTKIT_SECCTL); | ||
279 | + init_sysbus_child(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), | ||
280 | + TYPE_TZ_PPC); | ||
281 | + init_sysbus_child(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), | ||
282 | + TYPE_TZ_PPC); | ||
283 | + init_sysbus_child(obj, "timer0", &s->timer0, sizeof(s->timer0), | ||
284 | + TYPE_CMSDK_APB_TIMER); | ||
285 | + init_sysbus_child(obj, "timer1", &s->timer1, sizeof(s->timer1), | ||
286 | + TYPE_CMSDK_APB_TIMER); | ||
287 | + init_sysbus_child(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), | ||
288 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
289 | + object_initialize(&s->ppc_irq_orgate, sizeof(s->ppc_irq_orgate), | ||
290 | + TYPE_OR_IRQ); | ||
291 | + object_property_add_child(obj, "ppc-irq-orgate", | ||
292 | + OBJECT(&s->ppc_irq_orgate), &error_abort); | ||
293 | + object_initialize(&s->sec_resp_splitter, sizeof(s->sec_resp_splitter), | ||
294 | + TYPE_SPLIT_IRQ); | ||
295 | + object_property_add_child(obj, "sec-resp-splitter", | ||
296 | + OBJECT(&s->sec_resp_splitter), &error_abort); | ||
297 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
298 | + char *name = g_strdup_printf("ppc-irq-splitter-%d", i); | ||
299 | + SplitIRQ *splitter = &s->ppc_irq_splitter[i]; | ||
300 | + | ||
301 | + object_initialize(splitter, sizeof(*splitter), TYPE_SPLIT_IRQ); | ||
302 | + object_property_add_child(obj, name, OBJECT(splitter), &error_abort); | ||
303 | + } | ||
304 | + init_sysbus_child(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), | ||
305 | + TYPE_UNIMPLEMENTED_DEVICE); | ||
306 | +} | ||
307 | + | ||
308 | +static void iotkit_exp_irq(void *opaque, int n, int level) | ||
309 | +{ | ||
310 | + IoTKit *s = IOTKIT(opaque); | ||
311 | + | ||
312 | + qemu_set_irq(s->exp_irqs[n], level); | ||
313 | +} | ||
314 | + | ||
315 | +static void iotkit_realize(DeviceState *dev, Error **errp) | ||
316 | +{ | ||
317 | + IoTKit *s = IOTKIT(dev); | ||
318 | + int i; | ||
319 | + MemoryRegion *mr; | ||
320 | + Error *err = NULL; | ||
321 | + SysBusDevice *sbd_apb_ppc0; | ||
322 | + SysBusDevice *sbd_secctl; | ||
323 | + DeviceState *dev_apb_ppc0; | ||
324 | + DeviceState *dev_apb_ppc1; | ||
325 | + DeviceState *dev_secctl; | ||
326 | + DeviceState *dev_splitter; | ||
327 | + | ||
328 | + if (!s->board_memory) { | ||
329 | + error_setg(errp, "memory property was not set"); | ||
330 | + return; | ||
331 | + } | 33 | + } |
332 | + | 34 | + |
333 | + if (!s->mainclk_frq) { | 35 | + if (info->kernel_filename) { |
334 | + error_setg(errp, "MAINCLK property was not set"); | 36 | + FWCfgState *fw_cfg; |
335 | + return; | 37 | + bool try_decompressing_kernel; |
336 | + } | ||
337 | + | 38 | + |
338 | + /* Handling of which devices should be available only to secure | 39 | + fw_cfg = fw_cfg_find(); |
339 | + * code is usually done differently for M profile than for A profile. | 40 | + try_decompressing_kernel = arm_feature(&cpu->env, |
340 | + * Instead of putting some devices only into the secure address space, | 41 | + ARM_FEATURE_AARCH64); |
341 | + * devices exist in both address spaces but with hard-wired security | ||
342 | + * permissions that will cause the CPU to fault for non-secure accesses. | ||
343 | + * | ||
344 | + * The IoTKit has an IDAU (Implementation Defined Access Unit), | ||
345 | + * which specifies hard-wired security permissions for different | ||
346 | + * areas of the physical address space. For the IoTKit IDAU, the | ||
347 | + * top 4 bits of the physical address are the IDAU region ID, and | ||
348 | + * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS | ||
349 | + * region, otherwise it is an S region. | ||
350 | + * | ||
351 | + * The various devices and RAMs are generally all mapped twice, | ||
352 | + * once into a region that the IDAU defines as secure and once | ||
353 | + * into a non-secure region. They sit behind either a Memory | ||
354 | + * Protection Controller (for RAM) or a Peripheral Protection | ||
355 | + * Controller (for devices), which allow a more fine grained | ||
356 | + * configuration of whether non-secure accesses are permitted. | ||
357 | + * | ||
358 | + * (The other place that guest software can configure security | ||
359 | + * permissions is in the architected SAU (Security Attribution | ||
360 | + * Unit), which is entirely inside the CPU. The IDAU can upgrade | ||
361 | + * the security attributes for a region to more restrictive than | ||
362 | + * the SAU specifies, but cannot downgrade them.) | ||
363 | + * | ||
364 | + * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff | ||
365 | + * 0x20000000..0x2007ffff 32KB FPGA block RAM | ||
366 | + * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff | ||
367 | + * 0x40000000..0x4000ffff base peripheral region 1 | ||
368 | + * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) | ||
369 | + * 0x40020000..0x4002ffff system control element peripherals | ||
370 | + * 0x40080000..0x400fffff base peripheral region 2 | ||
371 | + * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff | ||
372 | + */ | ||
373 | + | 42 | + |
374 | + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | 43 | + /* |
44 | + * Expose the kernel, the command line, and the initrd in fw_cfg. | ||
45 | + * We don't process them here at all, it's all left to the | ||
46 | + * firmware. | ||
47 | + */ | ||
48 | + load_image_to_fw_cfg(fw_cfg, | ||
49 | + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | ||
50 | + info->kernel_filename, | ||
51 | + try_decompressing_kernel); | ||
52 | + load_image_to_fw_cfg(fw_cfg, | ||
53 | + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | ||
54 | + info->initrd_filename, false); | ||
375 | + | 55 | + |
376 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32); | 56 | + if (info->kernel_cmdline) { |
377 | + /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 | 57 | + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
378 | + * register in the IoT Kit System Control Register block, and the | 58 | + strlen(info->kernel_cmdline) + 1); |
379 | + * initial value of that is in turn specifiable by the FPGA that | 59 | + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, |
380 | + * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, | 60 | + info->kernel_cmdline); |
381 | + * and simply set the CPU's init-svtor to the IoT Kit default value. | ||
382 | + */ | ||
383 | + qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); | ||
384 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), | ||
385 | + "memory", &err); | ||
386 | + if (err) { | ||
387 | + error_propagate(errp, err); | ||
388 | + return; | ||
389 | + } | ||
390 | + object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); | ||
391 | + if (err) { | ||
392 | + error_propagate(errp, err); | ||
393 | + return; | ||
394 | + } | ||
395 | + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | ||
396 | + if (err) { | ||
397 | + error_propagate(errp, err); | ||
398 | + return; | ||
399 | + } | ||
400 | + | ||
401 | + /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ | ||
402 | + s->exp_irqs = g_new(qemu_irq, s->exp_numirq); | ||
403 | + for (i = 0; i < s->exp_numirq; i++) { | ||
404 | + s->exp_irqs[i] = qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); | ||
405 | + } | ||
406 | + qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); | ||
407 | + | ||
408 | + /* Set up the big aliases first */ | ||
409 | + make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); | ||
410 | + make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); | ||
411 | + /* The 0x50000000..0x5fffffff region is not a pure alias: it has | ||
412 | + * a few extra devices that only appear there (generally the | ||
413 | + * control interfaces for the protection controllers). | ||
414 | + * We implement this by mapping those devices over the top of this | ||
415 | + * alias MR at a higher priority. | ||
416 | + */ | ||
417 | + make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); | ||
418 | + | ||
419 | + /* This RAM should be behind a Memory Protection Controller, but we | ||
420 | + * don't implement that yet. | ||
421 | + */ | ||
422 | + memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &err); | ||
423 | + if (err) { | ||
424 | + error_propagate(errp, err); | ||
425 | + return; | ||
426 | + } | ||
427 | + memory_region_add_subregion(&s->container, 0x20000000, &s->sram0); | ||
428 | + | ||
429 | + /* Security controller */ | ||
430 | + object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); | ||
431 | + if (err) { | ||
432 | + error_propagate(errp, err); | ||
433 | + return; | ||
434 | + } | ||
435 | + sbd_secctl = SYS_BUS_DEVICE(&s->secctl); | ||
436 | + dev_secctl = DEVICE(&s->secctl); | ||
437 | + sysbus_mmio_map(sbd_secctl, 0, 0x50080000); | ||
438 | + sysbus_mmio_map(sbd_secctl, 1, 0x40080000); | ||
439 | + | ||
440 | + s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); | ||
441 | + qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); | ||
442 | + | ||
443 | + /* The sec_resp_cfg output from the security controller must be split into | ||
444 | + * multiple lines, one for each of the PPCs within the IoTKit and one | ||
445 | + * that will be an output from the IoTKit to the system. | ||
446 | + */ | ||
447 | + object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, | ||
448 | + "num-lines", &err); | ||
449 | + if (err) { | ||
450 | + error_propagate(errp, err); | ||
451 | + return; | ||
452 | + } | ||
453 | + object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, | ||
454 | + "realized", &err); | ||
455 | + if (err) { | ||
456 | + error_propagate(errp, err); | ||
457 | + return; | ||
458 | + } | ||
459 | + dev_splitter = DEVICE(&s->sec_resp_splitter); | ||
460 | + qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, | ||
461 | + qdev_get_gpio_in(dev_splitter, 0)); | ||
462 | + | ||
463 | + /* Devices behind APB PPC0: | ||
464 | + * 0x40000000: timer0 | ||
465 | + * 0x40001000: timer1 | ||
466 | + * 0x40002000: dual timer | ||
467 | + * We must configure and realize each downstream device and connect | ||
468 | + * it to the appropriate PPC port; then we can realize the PPC and | ||
469 | + * map its upstream ends to the right place in the container. | ||
470 | + */ | ||
471 | + qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); | ||
472 | + object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); | ||
473 | + if (err) { | ||
474 | + error_propagate(errp, err); | ||
475 | + return; | ||
476 | + } | ||
477 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, | ||
478 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
479 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); | ||
480 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); | ||
481 | + if (err) { | ||
482 | + error_propagate(errp, err); | ||
483 | + return; | ||
484 | + } | ||
485 | + | ||
486 | + qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); | ||
487 | + object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); | ||
488 | + if (err) { | ||
489 | + error_propagate(errp, err); | ||
490 | + return; | ||
491 | + } | ||
492 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, | ||
493 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); | ||
494 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); | ||
495 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); | ||
496 | + if (err) { | ||
497 | + error_propagate(errp, err); | ||
498 | + return; | ||
499 | + } | ||
500 | + | ||
501 | + qdev_prop_set_string(DEVICE(&s->dualtimer), "name", "Dual timer"); | ||
502 | + qdev_prop_set_uint64(DEVICE(&s->dualtimer), "size", 0x1000); | ||
503 | + object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); | ||
504 | + if (err) { | ||
505 | + error_propagate(errp, err); | ||
506 | + return; | ||
507 | + } | ||
508 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); | ||
509 | + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); | ||
510 | + if (err) { | ||
511 | + error_propagate(errp, err); | ||
512 | + return; | ||
513 | + } | ||
514 | + | ||
515 | + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); | ||
516 | + if (err) { | ||
517 | + error_propagate(errp, err); | ||
518 | + return; | ||
519 | + } | ||
520 | + | ||
521 | + sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); | ||
522 | + dev_apb_ppc0 = DEVICE(&s->apb_ppc0); | ||
523 | + | ||
524 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); | ||
525 | + memory_region_add_subregion(&s->container, 0x40000000, mr); | ||
526 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); | ||
527 | + memory_region_add_subregion(&s->container, 0x40001000, mr); | ||
528 | + mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); | ||
529 | + memory_region_add_subregion(&s->container, 0x40002000, mr); | ||
530 | + for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { | ||
531 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, | ||
532 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
533 | + "cfg_nonsec", i)); | ||
534 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, | ||
535 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
536 | + "cfg_ap", i)); | ||
537 | + } | ||
538 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, | ||
539 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
540 | + "irq_enable", 0)); | ||
541 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, | ||
542 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
543 | + "irq_clear", 0)); | ||
544 | + qdev_connect_gpio_out(dev_splitter, 0, | ||
545 | + qdev_get_gpio_in_named(dev_apb_ppc0, | ||
546 | + "cfg_sec_resp", 0)); | ||
547 | + | ||
548 | + /* All the PPC irq lines (from the 2 internal PPCs and the 8 external | ||
549 | + * ones) are sent individually to the security controller, and also | ||
550 | + * ORed together to give a single combined PPC interrupt to the NVIC. | ||
551 | + */ | ||
552 | + object_property_set_int(OBJECT(&s->ppc_irq_orgate), | ||
553 | + NUM_PPCS, "num-lines", &err); | ||
554 | + if (err) { | ||
555 | + error_propagate(errp, err); | ||
556 | + return; | ||
557 | + } | ||
558 | + object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, | ||
559 | + "realized", &err); | ||
560 | + if (err) { | ||
561 | + error_propagate(errp, err); | ||
562 | + return; | ||
563 | + } | ||
564 | + qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, | ||
565 | + qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); | ||
566 | + | ||
567 | + /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ | ||
568 | + | ||
569 | + /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */ | ||
570 | + /* Devices behind APB PPC1: | ||
571 | + * 0x4002f000: S32K timer | ||
572 | + */ | ||
573 | + qdev_prop_set_string(DEVICE(&s->s32ktimer), "name", "S32KTIMER"); | ||
574 | + qdev_prop_set_uint64(DEVICE(&s->s32ktimer), "size", 0x1000); | ||
575 | + object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); | ||
576 | + if (err) { | ||
577 | + error_propagate(errp, err); | ||
578 | + return; | ||
579 | + } | ||
580 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); | ||
581 | + object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); | ||
582 | + if (err) { | ||
583 | + error_propagate(errp, err); | ||
584 | + return; | ||
585 | + } | ||
586 | + | ||
587 | + object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); | ||
588 | + if (err) { | ||
589 | + error_propagate(errp, err); | ||
590 | + return; | ||
591 | + } | ||
592 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); | ||
593 | + memory_region_add_subregion(&s->container, 0x4002f000, mr); | ||
594 | + | ||
595 | + dev_apb_ppc1 = DEVICE(&s->apb_ppc1); | ||
596 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, | ||
597 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
598 | + "cfg_nonsec", 0)); | ||
599 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, | ||
600 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
601 | + "cfg_ap", 0)); | ||
602 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, | ||
603 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
604 | + "irq_enable", 0)); | ||
605 | + qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, | ||
606 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
607 | + "irq_clear", 0)); | ||
608 | + qdev_connect_gpio_out(dev_splitter, 1, | ||
609 | + qdev_get_gpio_in_named(dev_apb_ppc1, | ||
610 | + "cfg_sec_resp", 0)); | ||
611 | + | ||
612 | + /* Using create_unimplemented_device() maps the stub into the | ||
613 | + * system address space rather than into our container, but the | ||
614 | + * overall effect to the guest is the same. | ||
615 | + */ | ||
616 | + create_unimplemented_device("SYSINFO", 0x40020000, 0x1000); | ||
617 | + | ||
618 | + create_unimplemented_device("SYSCONTROL", 0x50021000, 0x1000); | ||
619 | + create_unimplemented_device("S32KWATCHDOG", 0x5002e000, 0x1000); | ||
620 | + | ||
621 | + /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ | ||
622 | + | ||
623 | + create_unimplemented_device("NS watchdog", 0x40081000, 0x1000); | ||
624 | + create_unimplemented_device("S watchdog", 0x50081000, 0x1000); | ||
625 | + | ||
626 | + create_unimplemented_device("SRAM0 MPC", 0x50083000, 0x1000); | ||
627 | + | ||
628 | + for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { | ||
629 | + Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); | ||
630 | + | ||
631 | + object_property_set_int(splitter, 2, "num-lines", &err); | ||
632 | + if (err) { | ||
633 | + error_propagate(errp, err); | ||
634 | + return; | ||
635 | + } | ||
636 | + object_property_set_bool(splitter, true, "realized", &err); | ||
637 | + if (err) { | ||
638 | + error_propagate(errp, err); | ||
639 | + return; | ||
640 | + } | 61 | + } |
641 | + } | 62 | + } |
642 | + | 63 | + |
643 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | 64 | + /* |
644 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | 65 | + * We will start from address 0 (typically a boot ROM image) in the |
645 | + | 66 | + * same way as hardware. |
646 | + iotkit_forward_ppc(s, ppcname, i); | 67 | + */ |
647 | + g_free(ppcname); | ||
648 | + } | ||
649 | + | ||
650 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
651 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
652 | + | ||
653 | + iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); | ||
654 | + g_free(ppcname); | ||
655 | + } | ||
656 | + | ||
657 | + for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { | ||
658 | + /* Wire up IRQ splitter for internal PPCs */ | ||
659 | + DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); | ||
660 | + char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", | ||
661 | + i - NUM_EXTERNAL_PPCS); | ||
662 | + TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; | ||
663 | + | ||
664 | + qdev_connect_gpio_out(devs, 0, | ||
665 | + qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); | ||
666 | + qdev_connect_gpio_out(devs, 1, | ||
667 | + qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); | ||
668 | + qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, | ||
669 | + qdev_get_gpio_in(devs, 0)); | ||
670 | + } | ||
671 | + | ||
672 | + iotkit_forward_sec_resp_cfg(s); | ||
673 | + | ||
674 | + system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; | ||
675 | +} | 68 | +} |
676 | + | 69 | + |
677 | +static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, | 70 | void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
678 | + int *iregion, bool *exempt, bool *ns, bool *nsc) | 71 | { |
679 | +{ | 72 | CPUState *cs; |
680 | + /* For IoTKit systems the IDAU responses are simple logical functions | 73 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
681 | + * of the address bits. The NSC attribute is guest-adjustable via the | 74 | |
682 | + * NSCCFG register in the security controller. | 75 | /* Load the kernel. */ |
683 | + */ | 76 | if (!info->kernel_filename || info->firmware_loaded) { |
684 | + IoTKit *s = IOTKIT(ii); | 77 | - |
685 | + int region = extract32(address, 28, 4); | 78 | - if (have_dtb(info)) { |
686 | + | 79 | - /* |
687 | + *ns = !(region & 1); | 80 | - * If we have a device tree blob, but no kernel to supply it to (or |
688 | + *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); | 81 | - * the kernel is supposed to be loaded by the bootloader), copy the |
689 | + /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | 82 | - * DTB to the base of RAM for the bootloader to pick up. |
690 | + *exempt = (address & 0xeff00000) == 0xe0000000; | 83 | - */ |
691 | + *iregion = region; | 84 | - info->dtb_start = info->loader_start; |
692 | +} | 85 | - } |
693 | + | 86 | - |
694 | +static const VMStateDescription iotkit_vmstate = { | 87 | - if (info->kernel_filename) { |
695 | + .name = "iotkit", | 88 | - FWCfgState *fw_cfg; |
696 | + .version_id = 1, | 89 | - bool try_decompressing_kernel; |
697 | + .minimum_version_id = 1, | 90 | - |
698 | + .fields = (VMStateField[]) { | 91 | - fw_cfg = fw_cfg_find(); |
699 | + VMSTATE_UINT32(nsccfg, IoTKit), | 92 | - try_decompressing_kernel = arm_feature(&cpu->env, |
700 | + VMSTATE_END_OF_LIST() | 93 | - ARM_FEATURE_AARCH64); |
701 | + } | 94 | - |
702 | +}; | 95 | - /* |
703 | + | 96 | - * Expose the kernel, the command line, and the initrd in fw_cfg. |
704 | +static Property iotkit_properties[] = { | 97 | - * We don't process them here at all, it's all left to the |
705 | + DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, | 98 | - * firmware. |
706 | + MemoryRegion *), | 99 | - */ |
707 | + DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), | 100 | - load_image_to_fw_cfg(fw_cfg, |
708 | + DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), | 101 | - FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, |
709 | + DEFINE_PROP_END_OF_LIST() | 102 | - info->kernel_filename, |
710 | +}; | 103 | - try_decompressing_kernel); |
711 | + | 104 | - load_image_to_fw_cfg(fw_cfg, |
712 | +static void iotkit_reset(DeviceState *dev) | 105 | - FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, |
713 | +{ | 106 | - info->initrd_filename, false); |
714 | + IoTKit *s = IOTKIT(dev); | 107 | - |
715 | + | 108 | - if (info->kernel_cmdline) { |
716 | + s->nsccfg = 0; | 109 | - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
717 | +} | 110 | - strlen(info->kernel_cmdline) + 1); |
718 | + | 111 | - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, |
719 | +static void iotkit_class_init(ObjectClass *klass, void *data) | 112 | - info->kernel_cmdline); |
720 | +{ | 113 | - } |
721 | + DeviceClass *dc = DEVICE_CLASS(klass); | 114 | - } |
722 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); | 115 | - |
723 | + | 116 | - /* |
724 | + dc->realize = iotkit_realize; | 117 | - * We will start from address 0 (typically a boot ROM image) in the |
725 | + dc->vmsd = &iotkit_vmstate; | 118 | - * same way as hardware. |
726 | + dc->props = iotkit_properties; | 119 | - */ |
727 | + dc->reset = iotkit_reset; | 120 | + arm_setup_firmware_boot(cpu, info); |
728 | + iic->check = iotkit_idau_check; | 121 | return; |
729 | +} | 122 | } else { |
730 | + | 123 | arm_setup_direct_kernel_boot(cpu, info); |
731 | +static const TypeInfo iotkit_info = { | ||
732 | + .name = TYPE_IOTKIT, | ||
733 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
734 | + .instance_size = sizeof(IoTKit), | ||
735 | + .instance_init = iotkit_init, | ||
736 | + .class_init = iotkit_class_init, | ||
737 | + .interfaces = (InterfaceInfo[]) { | ||
738 | + { TYPE_IDAU_INTERFACE }, | ||
739 | + { } | ||
740 | + } | ||
741 | +}; | ||
742 | + | ||
743 | +static void iotkit_register_types(void) | ||
744 | +{ | ||
745 | + type_register_static(&iotkit_info); | ||
746 | +} | ||
747 | + | ||
748 | +type_init(iotkit_register_types); | ||
749 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
750 | index XXXXXXX..XXXXXXX 100644 | ||
751 | --- a/default-configs/arm-softmmu.mak | ||
752 | +++ b/default-configs/arm-softmmu.mak | ||
753 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
754 | CONFIG_MPS2_SCC=y | ||
755 | |||
756 | CONFIG_TZ_PPC=y | ||
757 | +CONFIG_IOTKIT=y | ||
758 | CONFIG_IOTKIT_SECCTL=y | ||
759 | |||
760 | CONFIG_VERSATILE_PCI=y | ||
761 | -- | 124 | -- |
762 | 2.16.2 | 125 | 2.20.1 |
763 | 126 | ||
764 | 127 | diff view generated by jsdifflib |
1 | The IoTKit Security Controller includes various registers | 1 | The code path for booting firmware doesn't set env->boot_info. At |
---|---|---|---|
2 | that expose to software the controls for the Peripheral | 2 | first sight this looks odd, so add a comment saying why we don't. |
3 | Protection Controllers in the system. Implement these. | ||
4 | 3 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180220180325.29818-17-peter.maydell@linaro.org | 6 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
7 | Message-id: 20190131112240.8395-5-peter.maydell@linaro.org | ||
8 | --- | 8 | --- |
9 | include/hw/misc/iotkit-secctl.h | 64 +++++++++- | 9 | hw/arm/boot.c | 3 ++- |
10 | hw/misc/iotkit-secctl.c | 270 +++++++++++++++++++++++++++++++++++++--- | 10 | 1 file changed, 2 insertions(+), 1 deletion(-) |
11 | 2 files changed, 315 insertions(+), 19 deletions(-) | ||
12 | 11 | ||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | 12 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
14 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/misc/iotkit-secctl.h | 14 | --- a/hw/arm/boot.c |
16 | +++ b/include/hw/misc/iotkit-secctl.h | 15 | +++ b/hw/arm/boot.c |
17 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) |
18 | * QEMU interface: | 17 | |
19 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | 18 | /* |
20 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | 19 | * We will start from address 0 (typically a boot ROM image) in the |
21 | + * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | 20 | - * same way as hardware. |
22 | + * should RAZ/WI or bus error | 21 | + * same way as hardware. Leave env->boot_info NULL, so that |
23 | + * Controlling the 2 APB PPCs in the IoTKit: | 22 | + * do_cpu_reset() knows it does not need to alter the PC on reset. |
24 | + * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | 23 | */ |
25 | + * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
26 | + * + named GPIO outputs apb_ppc{0,1}_irq_enable | ||
27 | + * + named GPIO outputs apb_ppc{0,1}_irq_clear | ||
28 | + * + named GPIO inputs apb_ppc{0,1}_irq_status | ||
29 | + * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit | ||
30 | + * might provide: | ||
31 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
32 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | ||
33 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | ||
34 | + * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | ||
35 | + * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | ||
36 | + * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | ||
37 | + * might provide: | ||
38 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | ||
39 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | ||
40 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | ||
41 | + * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | ||
42 | + * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | ||
43 | */ | ||
44 | |||
45 | #ifndef IOTKIT_SECCTL_H | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
48 | #define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
49 | |||
50 | -typedef struct IoTKitSecCtl { | ||
51 | +#define IOTS_APB_PPC0_NUM_PORTS 3 | ||
52 | +#define IOTS_APB_PPC1_NUM_PORTS 1 | ||
53 | +#define IOTS_PPC_NUM_PORTS 16 | ||
54 | +#define IOTS_NUM_APB_PPC 2 | ||
55 | +#define IOTS_NUM_APB_EXP_PPC 4 | ||
56 | +#define IOTS_NUM_AHB_EXP_PPC 4 | ||
57 | + | ||
58 | +typedef struct IoTKitSecCtl IoTKitSecCtl; | ||
59 | + | ||
60 | +/* State and IRQ lines relating to a PPC. For the | ||
61 | + * PPCs in the IoTKit not all the IRQ lines are used. | ||
62 | + */ | ||
63 | +typedef struct IoTKitSecCtlPPC { | ||
64 | + qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; | ||
65 | + qemu_irq ap[IOTS_PPC_NUM_PORTS]; | ||
66 | + qemu_irq irq_enable; | ||
67 | + qemu_irq irq_clear; | ||
68 | + | ||
69 | + uint32_t ns; | ||
70 | + uint32_t sp; | ||
71 | + uint32_t nsp; | ||
72 | + | ||
73 | + /* Number of ports actually present */ | ||
74 | + int numports; | ||
75 | + /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ | ||
76 | + int irq_bit_offset; | ||
77 | + IoTKitSecCtl *parent; | ||
78 | +} IoTKitSecCtlPPC; | ||
79 | + | ||
80 | +struct IoTKitSecCtl { | ||
81 | /*< private >*/ | ||
82 | SysBusDevice parent_obj; | ||
83 | |||
84 | /*< public >*/ | ||
85 | + qemu_irq sec_resp_cfg; | ||
86 | |||
87 | MemoryRegion s_regs; | ||
88 | MemoryRegion ns_regs; | ||
89 | -} IoTKitSecCtl; | ||
90 | + | ||
91 | + uint32_t secppcintstat; | ||
92 | + uint32_t secppcinten; | ||
93 | + uint32_t secrespcfg; | ||
94 | + | ||
95 | + IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
96 | + IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
97 | + IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; | ||
98 | +}; | ||
99 | |||
100 | #endif | ||
101 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/hw/misc/iotkit-secctl.c | ||
104 | +++ b/hw/misc/iotkit-secctl.c | ||
105 | @@ -XXX,XX +XXX,XX @@ static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
106 | 0x0d, 0xf0, 0x05, 0xb1, | ||
107 | }; | ||
108 | |||
109 | +/* The register sets for the various PPCs (AHB internal, APB internal, | ||
110 | + * AHB expansion, APB expansion) are all set up so that they are | ||
111 | + * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs | ||
112 | + * 0, 1, 2, 3 of that type, so we can convert a register address offset | ||
113 | + * into an an index into a PPC array easily. | ||
114 | + */ | ||
115 | +static inline int offset_to_ppc_idx(uint32_t offset) | ||
116 | +{ | ||
117 | + return extract32(offset, 2, 2); | ||
118 | +} | ||
119 | + | ||
120 | +typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc); | ||
121 | + | ||
122 | +static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn) | ||
123 | +{ | ||
124 | + int i; | ||
125 | + | ||
126 | + for (i = 0; i < IOTS_NUM_APB_PPC; i++) { | ||
127 | + fn(&s->apb[i]); | ||
128 | + } | ||
129 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
130 | + fn(&s->apbexp[i]); | ||
131 | + } | ||
132 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
133 | + fn(&s->ahbexp[i]); | ||
134 | + } | ||
135 | +} | ||
136 | + | ||
137 | static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
138 | uint64_t *pdata, | ||
139 | unsigned size, MemTxAttrs attrs) | ||
140 | { | ||
141 | uint64_t r; | ||
142 | uint32_t offset = addr & ~0x3; | ||
143 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
144 | |||
145 | switch (offset) { | ||
146 | case A_AHBNSPPC0: | ||
147 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
148 | r = 0; | ||
149 | break; | ||
150 | case A_SECRESPCFG: | ||
151 | - case A_NSCCFG: | ||
152 | - case A_SECMPCINTSTATUS: | ||
153 | + r = s->secrespcfg; | ||
154 | + break; | ||
155 | case A_SECPPCINTSTAT: | ||
156 | + r = s->secppcintstat; | ||
157 | + break; | ||
158 | case A_SECPPCINTEN: | ||
159 | - case A_SECMSCINTSTAT: | ||
160 | - case A_SECMSCINTEN: | ||
161 | - case A_BRGINTSTAT: | ||
162 | - case A_BRGINTEN: | ||
163 | + r = s->secppcinten; | ||
164 | + break; | ||
165 | case A_AHBNSPPCEXP0: | ||
166 | case A_AHBNSPPCEXP1: | ||
167 | case A_AHBNSPPCEXP2: | ||
168 | case A_AHBNSPPCEXP3: | ||
169 | + r = s->ahbexp[offset_to_ppc_idx(offset)].ns; | ||
170 | + break; | ||
171 | case A_APBNSPPC0: | ||
172 | case A_APBNSPPC1: | ||
173 | + r = s->apb[offset_to_ppc_idx(offset)].ns; | ||
174 | + break; | ||
175 | case A_APBNSPPCEXP0: | ||
176 | case A_APBNSPPCEXP1: | ||
177 | case A_APBNSPPCEXP2: | ||
178 | case A_APBNSPPCEXP3: | ||
179 | + r = s->apbexp[offset_to_ppc_idx(offset)].ns; | ||
180 | + break; | ||
181 | case A_AHBSPPPCEXP0: | ||
182 | case A_AHBSPPPCEXP1: | ||
183 | case A_AHBSPPPCEXP2: | ||
184 | case A_AHBSPPPCEXP3: | ||
185 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
186 | + break; | ||
187 | case A_APBSPPPC0: | ||
188 | case A_APBSPPPC1: | ||
189 | + r = s->apb[offset_to_ppc_idx(offset)].sp; | ||
190 | + break; | ||
191 | case A_APBSPPPCEXP0: | ||
192 | case A_APBSPPPCEXP1: | ||
193 | case A_APBSPPPCEXP2: | ||
194 | case A_APBSPPPCEXP3: | ||
195 | + r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
196 | + break; | ||
197 | + case A_NSCCFG: | ||
198 | + case A_SECMPCINTSTATUS: | ||
199 | + case A_SECMSCINTSTAT: | ||
200 | + case A_SECMSCINTEN: | ||
201 | + case A_BRGINTSTAT: | ||
202 | + case A_BRGINTEN: | ||
203 | case A_NSMSCEXP: | ||
204 | qemu_log_mask(LOG_UNIMP, | ||
205 | "IoTKit SecCtl S block read: " | ||
206 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
207 | return MEMTX_OK; | ||
208 | } | 24 | } |
209 | 25 | ||
210 | +static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc) | ||
211 | +{ | ||
212 | + int i; | ||
213 | + | ||
214 | + for (i = 0; i < ppc->numports; i++) { | ||
215 | + bool v; | ||
216 | + | ||
217 | + if (extract32(ppc->ns, i, 1)) { | ||
218 | + v = extract32(ppc->nsp, i, 1); | ||
219 | + } else { | ||
220 | + v = extract32(ppc->sp, i, 1); | ||
221 | + } | ||
222 | + qemu_set_irq(ppc->ap[i], v); | ||
223 | + } | ||
224 | +} | ||
225 | + | ||
226 | +static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
227 | +{ | ||
228 | + int i; | ||
229 | + | ||
230 | + ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
231 | + for (i = 0; i < ppc->numports; i++) { | ||
232 | + qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); | ||
233 | + } | ||
234 | + iotkit_secctl_update_ppc_ap(ppc); | ||
235 | +} | ||
236 | + | ||
237 | +static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
238 | +{ | ||
239 | + ppc->sp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
240 | + iotkit_secctl_update_ppc_ap(ppc); | ||
241 | +} | ||
242 | + | ||
243 | +static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t value) | ||
244 | +{ | ||
245 | + ppc->nsp = value & MAKE_64BIT_MASK(0, ppc->numports); | ||
246 | + iotkit_secctl_update_ppc_ap(ppc); | ||
247 | +} | ||
248 | + | ||
249 | +static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc) | ||
250 | +{ | ||
251 | + uint32_t value = ppc->parent->secppcintstat; | ||
252 | + | ||
253 | + qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1)); | ||
254 | +} | ||
255 | + | ||
256 | +static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc) | ||
257 | +{ | ||
258 | + uint32_t value = ppc->parent->secppcinten; | ||
259 | + | ||
260 | + qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)); | ||
261 | +} | ||
262 | + | ||
263 | static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
264 | uint64_t value, | ||
265 | unsigned size, MemTxAttrs attrs) | ||
266 | { | ||
267 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
268 | uint32_t offset = addr; | ||
269 | + IoTKitSecCtlPPC *ppc; | ||
270 | |||
271 | trace_iotkit_secctl_s_write(offset, value, size); | ||
272 | |||
273 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
274 | |||
275 | switch (offset) { | ||
276 | case A_SECRESPCFG: | ||
277 | - case A_NSCCFG: | ||
278 | + value &= 1; | ||
279 | + s->secrespcfg = value; | ||
280 | + qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); | ||
281 | + break; | ||
282 | case A_SECPPCINTCLR: | ||
283 | + value &= 0x00f000f3; | ||
284 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear); | ||
285 | + break; | ||
286 | case A_SECPPCINTEN: | ||
287 | - case A_SECMSCINTCLR: | ||
288 | - case A_SECMSCINTEN: | ||
289 | - case A_BRGINTCLR: | ||
290 | - case A_BRGINTEN: | ||
291 | + s->secppcinten = value & 0x00f000f3; | ||
292 | + foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
293 | + break; | ||
294 | case A_AHBNSPPCEXP0: | ||
295 | case A_AHBNSPPCEXP1: | ||
296 | case A_AHBNSPPCEXP2: | ||
297 | case A_AHBNSPPCEXP3: | ||
298 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
299 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
300 | + break; | ||
301 | case A_APBNSPPC0: | ||
302 | case A_APBNSPPC1: | ||
303 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
304 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
305 | + break; | ||
306 | case A_APBNSPPCEXP0: | ||
307 | case A_APBNSPPCEXP1: | ||
308 | case A_APBNSPPCEXP2: | ||
309 | case A_APBNSPPCEXP3: | ||
310 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
311 | + iotkit_secctl_ppc_ns_write(ppc, value); | ||
312 | + break; | ||
313 | case A_AHBSPPPCEXP0: | ||
314 | case A_AHBSPPPCEXP1: | ||
315 | case A_AHBSPPPCEXP2: | ||
316 | case A_AHBSPPPCEXP3: | ||
317 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
318 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
319 | + break; | ||
320 | case A_APBSPPPC0: | ||
321 | case A_APBSPPPC1: | ||
322 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
323 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
324 | + break; | ||
325 | case A_APBSPPPCEXP0: | ||
326 | case A_APBSPPPCEXP1: | ||
327 | case A_APBSPPPCEXP2: | ||
328 | case A_APBSPPPCEXP3: | ||
329 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
330 | + iotkit_secctl_ppc_sp_write(ppc, value); | ||
331 | + break; | ||
332 | + case A_NSCCFG: | ||
333 | + case A_SECMSCINTCLR: | ||
334 | + case A_SECMSCINTEN: | ||
335 | + case A_BRGINTCLR: | ||
336 | + case A_BRGINTEN: | ||
337 | qemu_log_mask(LOG_UNIMP, | ||
338 | "IoTKit SecCtl S block write: " | ||
339 | "unimplemented offset 0x%x\n", offset); | ||
340 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
341 | uint64_t *pdata, | ||
342 | unsigned size, MemTxAttrs attrs) | ||
343 | { | ||
344 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
345 | uint64_t r; | ||
346 | uint32_t offset = addr & ~0x3; | ||
347 | |||
348 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
349 | case A_AHBNSPPPCEXP1: | ||
350 | case A_AHBNSPPPCEXP2: | ||
351 | case A_AHBNSPPPCEXP3: | ||
352 | + r = s->ahbexp[offset_to_ppc_idx(offset)].nsp; | ||
353 | + break; | ||
354 | case A_APBNSPPPC0: | ||
355 | case A_APBNSPPPC1: | ||
356 | + r = s->apb[offset_to_ppc_idx(offset)].nsp; | ||
357 | + break; | ||
358 | case A_APBNSPPPCEXP0: | ||
359 | case A_APBNSPPPCEXP1: | ||
360 | case A_APBNSPPPCEXP2: | ||
361 | case A_APBNSPPPCEXP3: | ||
362 | - qemu_log_mask(LOG_UNIMP, | ||
363 | - "IoTKit SecCtl NS block read: " | ||
364 | - "unimplemented offset 0x%x\n", offset); | ||
365 | + r = s->apbexp[offset_to_ppc_idx(offset)].nsp; | ||
366 | break; | ||
367 | case A_PID4: | ||
368 | case A_PID5: | ||
369 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
370 | uint64_t value, | ||
371 | unsigned size, MemTxAttrs attrs) | ||
372 | { | ||
373 | + IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); | ||
374 | uint32_t offset = addr; | ||
375 | + IoTKitSecCtlPPC *ppc; | ||
376 | |||
377 | trace_iotkit_secctl_ns_write(offset, value, size); | ||
378 | |||
379 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
380 | case A_AHBNSPPPCEXP1: | ||
381 | case A_AHBNSPPPCEXP2: | ||
382 | case A_AHBNSPPPCEXP3: | ||
383 | + ppc = &s->ahbexp[offset_to_ppc_idx(offset)]; | ||
384 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
385 | + break; | ||
386 | case A_APBNSPPPC0: | ||
387 | case A_APBNSPPPC1: | ||
388 | + ppc = &s->apb[offset_to_ppc_idx(offset)]; | ||
389 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
390 | + break; | ||
391 | case A_APBNSPPPCEXP0: | ||
392 | case A_APBNSPPPCEXP1: | ||
393 | case A_APBNSPPPCEXP2: | ||
394 | case A_APBNSPPPCEXP3: | ||
395 | - qemu_log_mask(LOG_UNIMP, | ||
396 | - "IoTKit SecCtl NS block write: " | ||
397 | - "unimplemented offset 0x%x\n", offset); | ||
398 | + ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
399 | + iotkit_secctl_ppc_nsp_write(ppc, value); | ||
400 | break; | ||
401 | case A_AHBNSPPPC0: | ||
402 | case A_PID4: | ||
403 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
404 | .impl.max_access_size = 4, | ||
405 | }; | ||
406 | |||
407 | +static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc) | ||
408 | +{ | ||
409 | + ppc->ns = 0; | ||
410 | + ppc->sp = 0; | ||
411 | + ppc->nsp = 0; | ||
412 | +} | ||
413 | + | ||
414 | static void iotkit_secctl_reset(DeviceState *dev) | ||
415 | { | ||
416 | + IoTKitSecCtl *s = IOTKIT_SECCTL(dev); | ||
417 | |||
418 | + s->secppcintstat = 0; | ||
419 | + s->secppcinten = 0; | ||
420 | + s->secrespcfg = 0; | ||
421 | + | ||
422 | + foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
423 | +} | ||
424 | + | ||
425 | +static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level) | ||
426 | +{ | ||
427 | + IoTKitSecCtlPPC *ppc = opaque; | ||
428 | + IoTKitSecCtl *s = IOTKIT_SECCTL(ppc->parent); | ||
429 | + int irqbit = ppc->irq_bit_offset + n; | ||
430 | + | ||
431 | + s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level); | ||
432 | +} | ||
433 | + | ||
434 | +static void iotkit_secctl_init_ppc(IoTKitSecCtl *s, | ||
435 | + IoTKitSecCtlPPC *ppc, | ||
436 | + const char *name, | ||
437 | + int numports, | ||
438 | + int irq_bit_offset) | ||
439 | +{ | ||
440 | + char *gpioname; | ||
441 | + DeviceState *dev = DEVICE(s); | ||
442 | + | ||
443 | + ppc->numports = numports; | ||
444 | + ppc->irq_bit_offset = irq_bit_offset; | ||
445 | + ppc->parent = s; | ||
446 | + | ||
447 | + gpioname = g_strdup_printf("%s_nonsec", name); | ||
448 | + qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports); | ||
449 | + g_free(gpioname); | ||
450 | + gpioname = g_strdup_printf("%s_ap", name); | ||
451 | + qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports); | ||
452 | + g_free(gpioname); | ||
453 | + gpioname = g_strdup_printf("%s_irq_enable", name); | ||
454 | + qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1); | ||
455 | + g_free(gpioname); | ||
456 | + gpioname = g_strdup_printf("%s_irq_clear", name); | ||
457 | + qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1); | ||
458 | + g_free(gpioname); | ||
459 | + gpioname = g_strdup_printf("%s_irq_status", name); | ||
460 | + qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus, | ||
461 | + ppc, gpioname, 1); | ||
462 | + g_free(gpioname); | ||
463 | } | ||
464 | |||
465 | static void iotkit_secctl_init(Object *obj) | ||
466 | { | ||
467 | IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
468 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
469 | + DeviceState *dev = DEVICE(obj); | ||
470 | + int i; | ||
471 | + | ||
472 | + iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0", | ||
473 | + IOTS_APB_PPC0_NUM_PORTS, 0); | ||
474 | + iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1", | ||
475 | + IOTS_APB_PPC1_NUM_PORTS, 1); | ||
476 | + | ||
477 | + for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | ||
478 | + IoTKitSecCtlPPC *ppc = &s->apbexp[i]; | ||
479 | + char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | ||
480 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i); | ||
481 | + g_free(ppcname); | ||
482 | + } | ||
483 | + for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | ||
484 | + IoTKitSecCtlPPC *ppc = &s->ahbexp[i]; | ||
485 | + char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | ||
486 | + iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i); | ||
487 | + g_free(ppcname); | ||
488 | + } | ||
489 | + | ||
490 | + qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
491 | |||
492 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
495 | sysbus_init_mmio(sbd, &s->ns_regs); | ||
496 | } | ||
497 | |||
498 | +static const VMStateDescription iotkit_secctl_ppc_vmstate = { | ||
499 | + .name = "iotkit-secctl-ppc", | ||
500 | + .version_id = 1, | ||
501 | + .minimum_version_id = 1, | ||
502 | + .fields = (VMStateField[]) { | ||
503 | + VMSTATE_UINT32(ns, IoTKitSecCtlPPC), | ||
504 | + VMSTATE_UINT32(sp, IoTKitSecCtlPPC), | ||
505 | + VMSTATE_UINT32(nsp, IoTKitSecCtlPPC), | ||
506 | + VMSTATE_END_OF_LIST() | ||
507 | + } | ||
508 | +}; | ||
509 | + | ||
510 | static const VMStateDescription iotkit_secctl_vmstate = { | ||
511 | .name = "iotkit-secctl", | ||
512 | .version_id = 1, | ||
513 | .minimum_version_id = 1, | ||
514 | .fields = (VMStateField[]) { | ||
515 | + VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
516 | + VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
517 | + VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
518 | + VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
519 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
520 | + VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
521 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
522 | + VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1, | ||
523 | + iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
524 | VMSTATE_END_OF_LIST() | ||
525 | } | ||
526 | }; | ||
527 | -- | 26 | -- |
528 | 2.16.2 | 27 | 2.20.1 |
529 | 28 | ||
530 | 29 | diff view generated by jsdifflib |
1 | Create an "idau" property on the armv7m container object which | 1 | The arm_boot_info struct has a skip_dtb_autoload flag: if this is |
---|---|---|---|
2 | we can forward to the CPU object. Annoyingly, we can't use | 2 | set to true by the board code then arm_load_kernel() will not |
3 | object_property_add_alias() because the CPU object we want to | 3 | load the DTB itself, but will leave this for the board code to |
4 | forward to doesn't exist until the armv7m container is realized. | 4 | do itself later. However, the check for this is done in a |
5 | code path which is only executed for the case where we load | ||
6 | a kernel image file. If we're taking the "boot via firmware" | ||
7 | code path then the flag isn't honoured and the DTB is never | ||
8 | loaded. | ||
9 | |||
10 | We didn't notice this because the only real user of "boot | ||
11 | via firmware" that cares about the DTB is the virt board | ||
12 | (for UEFI boot), and that always wants skip_dtb_autoload | ||
13 | anyway. But the SBSA reference board model we're planning to | ||
14 | add will want the flag to behave correctly. | ||
15 | |||
16 | Now we've refactored the arm_load_kernel() function, the | ||
17 | fix is simple: drop the early 'return' so we fall into | ||
18 | the same "load the DTB" code the boot-direct-kernel path uses. | ||
5 | 19 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180220180325.29818-6-peter.maydell@linaro.org | 22 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> |
23 | Message-id: 20190131112240.8395-6-peter.maydell@linaro.org | ||
9 | --- | 24 | --- |
10 | include/hw/arm/armv7m.h | 3 +++ | 25 | hw/arm/boot.c | 1 - |
11 | hw/arm/armv7m.c | 9 +++++++++ | 26 | 1 file changed, 1 deletion(-) |
12 | 2 files changed, 12 insertions(+) | ||
13 | 27 | ||
14 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | 28 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
15 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/armv7m.h | 30 | --- a/hw/arm/boot.c |
17 | +++ b/include/hw/arm/armv7m.h | 31 | +++ b/hw/arm/boot.c |
18 | @@ -XXX,XX +XXX,XX @@ | 32 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
19 | 33 | /* Load the kernel. */ | |
20 | #include "hw/sysbus.h" | 34 | if (!info->kernel_filename || info->firmware_loaded) { |
21 | #include "hw/intc/armv7m_nvic.h" | 35 | arm_setup_firmware_boot(cpu, info); |
22 | +#include "target/arm/idau.h" | 36 | - return; |
23 | 37 | } else { | |
24 | #define TYPE_BITBAND "ARM,bitband-memory" | 38 | arm_setup_direct_kernel_boot(cpu, info); |
25 | #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | 39 | } |
26 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
27 | * + Property "memory": MemoryRegion defining the physical address space | ||
28 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
29 | * devices will be automatically layered on top of this view.) | ||
30 | + * + Property "idau": IDAU interface (forwarded to CPU object) | ||
31 | */ | ||
32 | typedef struct ARMv7MState { | ||
33 | /*< private >*/ | ||
34 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
35 | char *cpu_type; | ||
36 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
37 | MemoryRegion *board_memory; | ||
38 | + Object *idau; | ||
39 | } ARMv7MState; | ||
40 | |||
41 | #endif | ||
42 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/armv7m.c | ||
45 | +++ b/hw/arm/armv7m.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | #include "sysemu/qtest.h" | ||
48 | #include "qemu/error-report.h" | ||
49 | #include "exec/address-spaces.h" | ||
50 | +#include "target/arm/idau.h" | ||
51 | |||
52 | /* Bitbanded IO. Each word corresponds to a single bit. */ | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
55 | |||
56 | object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", | ||
57 | &error_abort); | ||
58 | + if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { | ||
59 | + object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err); | ||
60 | + if (err != NULL) { | ||
61 | + error_propagate(errp, err); | ||
62 | + return; | ||
63 | + } | ||
64 | + } | ||
65 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
66 | if (err != NULL) { | ||
67 | error_propagate(errp, err); | ||
68 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
69 | DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), | ||
70 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
71 | MemoryRegion *), | ||
72 | + DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
73 | DEFINE_PROP_END_OF_LIST(), | ||
74 | }; | ||
75 | |||
76 | -- | 40 | -- |
77 | 2.16.2 | 41 | 2.20.1 |
78 | 42 | ||
79 | 43 | diff view generated by jsdifflib |
1 | In v8M, the Implementation Defined Attribution Unit (IDAU) is | 1 | The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for |
---|---|---|---|
2 | a small piece of hardware typically implemented in the SoC | 2 | enabling trapped IEEE floating point exceptions (where IEEE exception |
3 | which provides board or SoC specific security attribution | 3 | conditions cause a CPU exception rather than updating the FPSR status |
4 | information for each address that the CPU performs MPU/SAU | 4 | bits). QEMU doesn't implement this (and nor does the hardware we're |
5 | checks on. For QEMU, we model this with a QOM interface which | 5 | modelling), but for implementations which don't implement trapped |
6 | is implemented by the board or SoC object and connected to | 6 | exception handling these control bits are supposed to be RAZ/WI. |
7 | the CPU using a link property. | 7 | This allows guest code to test for whether the feature is present |
8 | by trying to write to the bit and checking whether it sticks. | ||
8 | 9 | ||
9 | This commit defines the new interface class, adds the link | 10 | QEMU is incorrectly making these bits read as written. Make them |
10 | property to the CPU object, and makes the SAU checking | 11 | RAZ/WI as the architecture requires. |
11 | code call the IDAU interface if one is present. | ||
12 | 12 | ||
13 | In particular this was causing problems for the NetBSD automatic | ||
14 | test suite. | ||
15 | |||
16 | Reported-by: Martin Husemann <martin@netbsd.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20180220180325.29818-5-peter.maydell@linaro.org | 19 | Message-id: 20190131130700.28392-1-peter.maydell@linaro.org |
16 | --- | 20 | --- |
17 | target/arm/cpu.h | 3 +++ | 21 | target/arm/cpu.h | 6 ++++++ |
18 | target/arm/idau.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++ | 22 | target/arm/helper.c | 6 ++++++ |
19 | target/arm/cpu.c | 15 +++++++++++++ | 23 | 2 files changed, 12 insertions(+) |
20 | target/arm/helper.c | 28 +++++++++++++++++++++--- | ||
21 | 4 files changed, 104 insertions(+), 3 deletions(-) | ||
22 | create mode 100644 target/arm/idau.h | ||
23 | 24 | ||
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
25 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpu.h | 27 | --- a/target/arm/cpu.h |
27 | +++ b/target/arm/cpu.h | 28 | +++ b/target/arm/cpu.h |
28 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 29 | @@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); |
29 | /* MemoryRegion to use for secure physical accesses */ | 30 | #define FPSR_MASK 0xf800009f |
30 | MemoryRegion *secure_memory; | 31 | #define FPCR_MASK 0x07ff9f00 |
31 | 32 | ||
32 | + /* For v8M, pointer to the IDAU interface provided by board/SoC */ | 33 | +#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ |
33 | + Object *idau; | 34 | +#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ |
34 | + | 35 | +#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ |
35 | /* 'compatible' string for this CPU for Linux device trees */ | 36 | +#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ |
36 | const char *dtb_compatible; | 37 | +#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ |
37 | 38 | +#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ | |
38 | diff --git a/target/arm/idau.h b/target/arm/idau.h | 39 | #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ |
39 | new file mode 100644 | 40 | #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ |
40 | index XXXXXXX..XXXXXXX | 41 | #define FPCR_DN (1 << 25) /* Default NaN enable bit */ |
41 | --- /dev/null | ||
42 | +++ b/target/arm/idau.h | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +/* | ||
45 | + * QEMU ARM CPU -- interface for the Arm v8M IDAU | ||
46 | + * | ||
47 | + * Copyright (c) 2018 Linaro Ltd | ||
48 | + * | ||
49 | + * This program is free software; you can redistribute it and/or | ||
50 | + * modify it under the terms of the GNU General Public License | ||
51 | + * as published by the Free Software Foundation; either version 2 | ||
52 | + * of the License, or (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, | ||
55 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
56 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
57 | + * GNU General Public License for more details. | ||
58 | + * | ||
59 | + * You should have received a copy of the GNU General Public License | ||
60 | + * along with this program; if not, see | ||
61 | + * <http://www.gnu.org/licenses/gpl-2.0.html> | ||
62 | + * | ||
63 | + * In the v8M architecture, the IDAU is a small piece of hardware | ||
64 | + * typically implemented in the SoC which provides board or SoC | ||
65 | + * specific security attribution information for each address that | ||
66 | + * the CPU performs MPU/SAU checks on. For QEMU, we model this with a | ||
67 | + * QOM interface which is implemented by the board or SoC object and | ||
68 | + * connected to the CPU using a link property. | ||
69 | + */ | ||
70 | + | ||
71 | +#ifndef TARGET_ARM_IDAU_H | ||
72 | +#define TARGET_ARM_IDAU_H | ||
73 | + | ||
74 | +#include "qom/object.h" | ||
75 | + | ||
76 | +#define TYPE_IDAU_INTERFACE "idau-interface" | ||
77 | +#define IDAU_INTERFACE(obj) \ | ||
78 | + INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE) | ||
79 | +#define IDAU_INTERFACE_CLASS(class) \ | ||
80 | + OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE) | ||
81 | +#define IDAU_INTERFACE_GET_CLASS(obj) \ | ||
82 | + OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE) | ||
83 | + | ||
84 | +typedef struct IDAUInterface { | ||
85 | + Object parent; | ||
86 | +} IDAUInterface; | ||
87 | + | ||
88 | +#define IREGION_NOTVALID -1 | ||
89 | + | ||
90 | +typedef struct IDAUInterfaceClass { | ||
91 | + InterfaceClass parent; | ||
92 | + | ||
93 | + /* Check the specified address and return the IDAU security information | ||
94 | + * for it by filling in iregion, exempt, ns and nsc: | ||
95 | + * iregion: IDAU region number, or IREGION_NOTVALID if not valid | ||
96 | + * exempt: true if address is exempt from security attribution | ||
97 | + * ns: true if the address is NonSecure | ||
98 | + * nsc: true if the address is NonSecure-callable | ||
99 | + */ | ||
100 | + void (*check)(IDAUInterface *ii, uint32_t address, int *iregion, | ||
101 | + bool *exempt, bool *ns, bool *nsc); | ||
102 | +} IDAUInterfaceClass; | ||
103 | + | ||
104 | +#endif | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/cpu.c | ||
108 | +++ b/target/arm/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ | ||
110 | */ | ||
111 | |||
112 | #include "qemu/osdep.h" | ||
113 | +#include "target/arm/idau.h" | ||
114 | #include "qemu/error-report.h" | ||
115 | #include "qapi/error.h" | ||
116 | #include "cpu.h" | ||
117 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | ||
118 | } | ||
119 | } | ||
120 | |||
121 | + if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { | ||
122 | + object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | ||
123 | + qdev_prop_allow_set_link_before_realize, | ||
124 | + OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
125 | + &error_abort); | ||
126 | + } | ||
127 | + | ||
128 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
129 | &error_abort); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = { | ||
132 | .class_init = arm_cpu_class_init, | ||
133 | }; | ||
134 | |||
135 | +static const TypeInfo idau_interface_type_info = { | ||
136 | + .name = TYPE_IDAU_INTERFACE, | ||
137 | + .parent = TYPE_INTERFACE, | ||
138 | + .class_size = sizeof(IDAUInterfaceClass), | ||
139 | +}; | ||
140 | + | ||
141 | static void arm_cpu_register_types(void) | ||
142 | { | ||
143 | const ARMCPUInfo *info = arm_cpus; | ||
144 | |||
145 | type_register_static(&arm_cpu_type_info); | ||
146 | + type_register_static(&idau_interface_type_info); | ||
147 | |||
148 | while (info->name) { | ||
149 | cpu_register(info); | ||
150 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 42 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
151 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
152 | --- a/target/arm/helper.c | 44 | --- a/target/arm/helper.c |
153 | +++ b/target/arm/helper.c | 45 | +++ b/target/arm/helper.c |
154 | @@ -XXX,XX +XXX,XX @@ | 46 | @@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
155 | #include "qemu/osdep.h" | 47 | val &= ~FPCR_FZ16; |
156 | +#include "target/arm/idau.h" | 48 | } |
157 | #include "trace.h" | 49 | |
158 | #include "cpu.h" | 50 | + /* |
159 | #include "internals.h" | 51 | + * We don't implement trapped exception handling, so the |
160 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | 52 | + * trap enable bits are all RAZ/WI (not RES0!) |
161 | */ | 53 | + */ |
162 | ARMCPU *cpu = arm_env_get_cpu(env); | 54 | + val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE); |
163 | int r; | ||
164 | + bool idau_exempt = false, idau_ns = true, idau_nsc = true; | ||
165 | + int idau_region = IREGION_NOTVALID; | ||
166 | |||
167 | - /* TODO: implement IDAU */ | ||
168 | + if (cpu->idau) { | ||
169 | + IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | ||
170 | + IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | ||
171 | + | 55 | + |
172 | + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | 56 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
173 | + &idau_nsc); | 57 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); |
174 | + } | 58 | env->vfp.vec_len = (val >> 16) & 7; |
175 | |||
176 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | ||
177 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | ||
178 | return; | ||
179 | } | ||
180 | |||
181 | - if (v8m_is_sau_exempt(env, address, access_type)) { | ||
182 | + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { | ||
183 | sattrs->ns = !regime_is_secure(env, mmu_idx); | ||
184 | return; | ||
185 | } | ||
186 | |||
187 | + if (idau_region != IREGION_NOTVALID) { | ||
188 | + sattrs->irvalid = true; | ||
189 | + sattrs->iregion = idau_region; | ||
190 | + } | ||
191 | + | ||
192 | switch (env->sau.ctrl & 3) { | ||
193 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | ||
194 | break; | ||
195 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | ||
196 | } | ||
197 | } | ||
198 | |||
199 | - /* TODO when we support the IDAU then it may override the result here */ | ||
200 | + /* The IDAU will override the SAU lookup results if it specifies | ||
201 | + * higher security than the SAU does. | ||
202 | + */ | ||
203 | + if (!idau_ns) { | ||
204 | + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | ||
205 | + sattrs->ns = false; | ||
206 | + sattrs->nsc = idau_nsc; | ||
207 | + } | ||
208 | + } | ||
209 | break; | ||
210 | } | ||
211 | } | ||
212 | -- | 59 | -- |
213 | 2.16.2 | 60 | 2.20.1 |
214 | 61 | ||
215 | 62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The Cortex-M33 allows the system to specify the reset value of the | ||
2 | secure Vector Table Offset Register (VTOR) by asserting config | ||
3 | signals. In particular, guest images for the MPS2 AN505 board rely | ||
4 | on the MPS2's initial VTOR being correct for that board. | ||
5 | Implement a QEMU property so board and SoC code can set the reset | ||
6 | value to the correct value. | ||
7 | 1 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20180220180325.29818-7-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/cpu.h | 3 +++ | ||
13 | target/arm/cpu.c | 18 ++++++++++++++---- | ||
14 | 2 files changed, 17 insertions(+), 4 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu.h | ||
19 | +++ b/target/arm/cpu.h | ||
20 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
21 | */ | ||
22 | uint32_t psci_conduit; | ||
23 | |||
24 | + /* For v8M, initial value of the Secure VTOR */ | ||
25 | + uint32_t init_svtor; | ||
26 | + | ||
27 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or | ||
28 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | ||
29 | */ | ||
30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/cpu.c | ||
33 | +++ b/target/arm/cpu.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
35 | uint32_t initial_msp; /* Loaded from 0x0 */ | ||
36 | uint32_t initial_pc; /* Loaded from 0x4 */ | ||
37 | uint8_t *rom; | ||
38 | + uint32_t vecbase; | ||
39 | |||
40 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
41 | env->v7m.secure = true; | ||
42 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
43 | /* Unlike A/R profile, M profile defines the reset LR value */ | ||
44 | env->regs[14] = 0xffffffff; | ||
45 | |||
46 | - /* Load the initial SP and PC from the vector table at address 0 */ | ||
47 | - rom = rom_ptr(0); | ||
48 | + env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; | ||
49 | + | ||
50 | + /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | ||
51 | + vecbase = env->v7m.vecbase[env->v7m.secure]; | ||
52 | + rom = rom_ptr(vecbase); | ||
53 | if (rom) { | ||
54 | /* Address zero is covered by ROM which hasn't yet been | ||
55 | * copied into physical memory. | ||
56 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
57 | * it got copied into memory. In the latter case, rom_ptr | ||
58 | * will return a NULL pointer and we should use ldl_phys instead. | ||
59 | */ | ||
60 | - initial_msp = ldl_phys(s->as, 0); | ||
61 | - initial_pc = ldl_phys(s->as, 4); | ||
62 | + initial_msp = ldl_phys(s->as, vecbase); | ||
63 | + initial_pc = ldl_phys(s->as, vecbase + 4); | ||
64 | } | ||
65 | |||
66 | env->regs[13] = initial_msp & 0xFFFFFFFC; | ||
67 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property = | ||
68 | pmsav7_dregion, | ||
69 | qdev_prop_uint32, uint32_t); | ||
70 | |||
71 | +/* M profile: initial value of the Secure VTOR */ | ||
72 | +static Property arm_cpu_initsvtor_property = | ||
73 | + DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | ||
74 | + | ||
75 | static void arm_cpu_post_init(Object *obj) | ||
76 | { | ||
77 | ARMCPU *cpu = ARM_CPU(obj); | ||
78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | ||
79 | qdev_prop_allow_set_link_before_realize, | ||
80 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
81 | &error_abort); | ||
82 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, | ||
83 | + &error_abort); | ||
84 | } | ||
85 | |||
86 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | ||
87 | -- | ||
88 | 2.16.2 | ||
89 | |||
90 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Create an "init-svtor" property on the armv7m container | ||
2 | object which we can forward to the CPU object. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20180220180325.29818-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | include/hw/arm/armv7m.h | 2 ++ | ||
9 | hw/arm/armv7m.c | 9 +++++++++ | ||
10 | 2 files changed, 11 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/arm/armv7m.h | ||
15 | +++ b/include/hw/arm/armv7m.h | ||
16 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
17 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | ||
18 | * devices will be automatically layered on top of this view.) | ||
19 | * + Property "idau": IDAU interface (forwarded to CPU object) | ||
20 | + * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) | ||
21 | */ | ||
22 | typedef struct ARMv7MState { | ||
23 | /*< private >*/ | ||
24 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | ||
25 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ | ||
26 | MemoryRegion *board_memory; | ||
27 | Object *idau; | ||
28 | + uint32_t init_svtor; | ||
29 | } ARMv7MState; | ||
30 | |||
31 | #endif | ||
32 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/armv7m.c | ||
35 | +++ b/hw/arm/armv7m.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
37 | return; | ||
38 | } | ||
39 | } | ||
40 | + if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { | ||
41 | + object_property_set_uint(OBJECT(s->cpu), s->init_svtor, | ||
42 | + "init-svtor", &err); | ||
43 | + if (err != NULL) { | ||
44 | + error_propagate(errp, err); | ||
45 | + return; | ||
46 | + } | ||
47 | + } | ||
48 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | ||
49 | if (err != NULL) { | ||
50 | error_propagate(errp, err); | ||
51 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
52 | DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | ||
53 | MemoryRegion *), | ||
54 | DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | ||
55 | + DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), | ||
56 | DEFINE_PROP_END_OF_LIST(), | ||
57 | }; | ||
58 | |||
59 | -- | ||
60 | 2.16.2 | ||
61 | |||
62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add a Cortex-M33 definition. The M33 is an M profile CPU | ||
2 | which implements the ARM v8M architecture, including the | ||
3 | M profile Security Extension. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-9-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++ | ||
10 | 1 file changed, 31 insertions(+) | ||
11 | |||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/cpu.c | ||
15 | +++ b/target/arm/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | ||
17 | cpu->id_isar5 = 0x00000000; | ||
18 | } | ||
19 | |||
20 | +static void cortex_m33_initfn(Object *obj) | ||
21 | +{ | ||
22 | + ARMCPU *cpu = ARM_CPU(obj); | ||
23 | + | ||
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
25 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
26 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
27 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
28 | + cpu->midr = 0x410fd213; /* r0p3 */ | ||
29 | + cpu->pmsav7_dregion = 16; | ||
30 | + cpu->sau_sregion = 8; | ||
31 | + cpu->id_pfr0 = 0x00000030; | ||
32 | + cpu->id_pfr1 = 0x00000210; | ||
33 | + cpu->id_dfr0 = 0x00200000; | ||
34 | + cpu->id_afr0 = 0x00000000; | ||
35 | + cpu->id_mmfr0 = 0x00101F40; | ||
36 | + cpu->id_mmfr1 = 0x00000000; | ||
37 | + cpu->id_mmfr2 = 0x01000000; | ||
38 | + cpu->id_mmfr3 = 0x00000000; | ||
39 | + cpu->id_isar0 = 0x01101110; | ||
40 | + cpu->id_isar1 = 0x02212000; | ||
41 | + cpu->id_isar2 = 0x20232232; | ||
42 | + cpu->id_isar3 = 0x01111131; | ||
43 | + cpu->id_isar4 = 0x01310132; | ||
44 | + cpu->id_isar5 = 0x00000000; | ||
45 | + cpu->clidr = 0x00000000; | ||
46 | + cpu->ctr = 0x8000c000; | ||
47 | +} | ||
48 | + | ||
49 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
50 | { | ||
51 | CPUClass *cc = CPU_CLASS(oc); | ||
52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | ||
53 | .class_init = arm_v7m_class_init }, | ||
54 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, | ||
55 | .class_init = arm_v7m_class_init }, | ||
56 | + { .name = "cortex-m33", .initfn = cortex_m33_initfn, | ||
57 | + .class_init = arm_v7m_class_init }, | ||
58 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | ||
59 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, | ||
60 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | ||
61 | -- | ||
62 | 2.16.2 | ||
63 | |||
64 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Move the definition of the struct for the unimplemented-device | ||
2 | from unimp.c to unimp.h, so that users can embed the struct | ||
3 | in their own device structs if they prefer. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-10-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/misc/unimp.h | 10 ++++++++++ | ||
11 | hw/misc/unimp.c | 10 ---------- | ||
12 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/misc/unimp.h | ||
17 | +++ b/include/hw/misc/unimp.h | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" | ||
21 | |||
22 | +#define UNIMPLEMENTED_DEVICE(obj) \ | ||
23 | + OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
24 | + | ||
25 | +typedef struct { | ||
26 | + SysBusDevice parent_obj; | ||
27 | + MemoryRegion iomem; | ||
28 | + char *name; | ||
29 | + uint64_t size; | ||
30 | +} UnimplementedDeviceState; | ||
31 | + | ||
32 | /** | ||
33 | * create_unimplemented_device: create and map a dummy device | ||
34 | * @name: name of the device for debug logging | ||
35 | diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/misc/unimp.c | ||
38 | +++ b/hw/misc/unimp.c | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | #include "qemu/log.h" | ||
41 | #include "qapi/error.h" | ||
42 | |||
43 | -#define UNIMPLEMENTED_DEVICE(obj) \ | ||
44 | - OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
45 | - | ||
46 | -typedef struct { | ||
47 | - SysBusDevice parent_obj; | ||
48 | - MemoryRegion iomem; | ||
49 | - char *name; | ||
50 | - uint64_t size; | ||
51 | -} UnimplementedDeviceState; | ||
52 | - | ||
53 | static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size) | ||
54 | { | ||
55 | UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
56 | -- | ||
57 | 2.16.2 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The or-irq.h header file is missing the customary guard against | ||
2 | multiple inclusion, which means compilation fails if it gets | ||
3 | included twice. Fix the omission. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-11-peter.maydell@linaro.org | ||
9 | --- | ||
10 | include/hw/or-irq.h | 5 +++++ | ||
11 | 1 file changed, 5 insertions(+) | ||
12 | |||
13 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/or-irq.h | ||
16 | +++ b/include/hw/or-irq.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * THE SOFTWARE. | ||
19 | */ | ||
20 | |||
21 | +#ifndef HW_OR_IRQ_H | ||
22 | +#define HW_OR_IRQ_H | ||
23 | + | ||
24 | #include "hw/irq.h" | ||
25 | #include "hw/sysbus.h" | ||
26 | #include "qom/object.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct OrIRQState { | ||
28 | bool levels[MAX_OR_LINES]; | ||
29 | uint16_t num_lines; | ||
30 | }; | ||
31 | + | ||
32 | +#endif | ||
33 | -- | ||
34 | 2.16.2 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The function qdev_init_gpio_in_named() passes the DeviceState pointer | ||
2 | as the opaque data pointor for the irq handler function. Usually | ||
3 | this is what you want, but in some cases it would be helpful to use | ||
4 | some other data pointer. | ||
5 | 1 | ||
6 | Add a new function qdev_init_gpio_in_named_with_opaque() which allows | ||
7 | the caller to specify the data pointer they want. | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180220180325.29818-12-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/hw/qdev-core.h | 30 ++++++++++++++++++++++++++++-- | ||
15 | hw/core/qdev.c | 8 +++++--- | ||
16 | 2 files changed, 33 insertions(+), 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/qdev-core.h | ||
21 | +++ b/include/hw/qdev-core.h | ||
22 | @@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); | ||
23 | /* GPIO inputs also double as IRQ sinks. */ | ||
24 | void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); | ||
25 | void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); | ||
26 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
27 | - const char *name, int n); | ||
28 | void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, | ||
29 | const char *name, int n); | ||
30 | +/** | ||
31 | + * qdev_init_gpio_in_named_with_opaque: create an array of input GPIO lines | ||
32 | + * for the specified device | ||
33 | + * | ||
34 | + * @dev: Device to create input GPIOs for | ||
35 | + * @handler: Function to call when GPIO line value is set | ||
36 | + * @opaque: Opaque data pointer to pass to @handler | ||
37 | + * @name: Name of the GPIO input (must be unique for this device) | ||
38 | + * @n: Number of GPIO lines in this input set | ||
39 | + */ | ||
40 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
41 | + qemu_irq_handler handler, | ||
42 | + void *opaque, | ||
43 | + const char *name, int n); | ||
44 | + | ||
45 | +/** | ||
46 | + * qdev_init_gpio_in_named: create an array of input GPIO lines | ||
47 | + * for the specified device | ||
48 | + * | ||
49 | + * Like qdev_init_gpio_in_named_with_opaque(), but the opaque pointer | ||
50 | + * passed to the handler is @dev (which is the most commonly desired behaviour). | ||
51 | + */ | ||
52 | +static inline void qdev_init_gpio_in_named(DeviceState *dev, | ||
53 | + qemu_irq_handler handler, | ||
54 | + const char *name, int n) | ||
55 | +{ | ||
56 | + qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); | ||
57 | +} | ||
58 | |||
59 | void qdev_pass_gpios(DeviceState *dev, DeviceState *container, | ||
60 | const char *name); | ||
61 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/core/qdev.c | ||
64 | +++ b/hw/core/qdev.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, | ||
66 | return ngl; | ||
67 | } | ||
68 | |||
69 | -void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler, | ||
70 | - const char *name, int n) | ||
71 | +void qdev_init_gpio_in_named_with_opaque(DeviceState *dev, | ||
72 | + qemu_irq_handler handler, | ||
73 | + void *opaque, | ||
74 | + const char *name, int n) | ||
75 | { | ||
76 | int i; | ||
77 | NamedGPIOList *gpio_list = qdev_get_named_gpio_list(dev, name); | ||
78 | |||
79 | assert(gpio_list->num_out == 0 || !name); | ||
80 | gpio_list->in = qemu_extend_irqs(gpio_list->in, gpio_list->num_in, handler, | ||
81 | - dev, n); | ||
82 | + opaque, n); | ||
83 | |||
84 | if (!name) { | ||
85 | name = "unnamed-gpio-in"; | ||
86 | -- | ||
87 | 2.16.2 | ||
88 | |||
89 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In some board or SoC models it is necessary to split a qemu_irq line | ||
2 | so that one input can feed multiple outputs. We currently have | ||
3 | qemu_irq_split() for this, but that has several deficiencies: | ||
4 | * it can only handle splitting a line into two | ||
5 | * it unavoidably leaks memory, so it can't be used | ||
6 | in a device that can be deleted | ||
7 | 1 | ||
8 | Implement a qdev device that encapsulates splitting of IRQs, with a | ||
9 | configurable number of outputs. (This is in some ways the inverse of | ||
10 | the TYPE_OR_IRQ device.) | ||
11 | |||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20180220180325.29818-13-peter.maydell@linaro.org | ||
15 | --- | ||
16 | hw/core/Makefile.objs | 1 + | ||
17 | include/hw/core/split-irq.h | 57 +++++++++++++++++++++++++++++ | ||
18 | include/hw/irq.h | 4 +- | ||
19 | hw/core/split-irq.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ | ||
20 | 4 files changed, 150 insertions(+), 1 deletion(-) | ||
21 | create mode 100644 include/hw/core/split-irq.h | ||
22 | create mode 100644 hw/core/split-irq.c | ||
23 | |||
24 | diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/hw/core/Makefile.objs | ||
27 | +++ b/hw/core/Makefile.objs | ||
28 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_FITLOADER) += loader-fit.o | ||
29 | common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o | ||
30 | common-obj-$(CONFIG_SOFTMMU) += register.o | ||
31 | common-obj-$(CONFIG_SOFTMMU) += or-irq.o | ||
32 | +common-obj-$(CONFIG_SOFTMMU) += split-irq.o | ||
33 | common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o | ||
34 | |||
35 | obj-$(CONFIG_SOFTMMU) += generic-loader.o | ||
36 | diff --git a/include/hw/core/split-irq.h b/include/hw/core/split-irq.h | ||
37 | new file mode 100644 | ||
38 | index XXXXXXX..XXXXXXX | ||
39 | --- /dev/null | ||
40 | +++ b/include/hw/core/split-irq.h | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | +/* | ||
43 | + * IRQ splitter device. | ||
44 | + * | ||
45 | + * Copyright (c) 2018 Linaro Limited. | ||
46 | + * Written by Peter Maydell | ||
47 | + * | ||
48 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
49 | + * of this software and associated documentation files (the "Software"), to deal | ||
50 | + * in the Software without restriction, including without limitation the rights | ||
51 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
52 | + * copies of the Software, and to permit persons to whom the Software is | ||
53 | + * furnished to do so, subject to the following conditions: | ||
54 | + * | ||
55 | + * The above copyright notice and this permission notice shall be included in | ||
56 | + * all copies or substantial portions of the Software. | ||
57 | + * | ||
58 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
59 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
60 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
61 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
62 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
63 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
64 | + * THE SOFTWARE. | ||
65 | + */ | ||
66 | + | ||
67 | +/* This is a simple device which has one GPIO input line and multiple | ||
68 | + * GPIO output lines. Any change on the input line is forwarded to all | ||
69 | + * of the outputs. | ||
70 | + * | ||
71 | + * QEMU interface: | ||
72 | + * + one unnamed GPIO input: the input line | ||
73 | + * + N unnamed GPIO outputs: the output lines | ||
74 | + * + QOM property "num-lines": sets the number of output lines | ||
75 | + */ | ||
76 | +#ifndef HW_SPLIT_IRQ_H | ||
77 | +#define HW_SPLIT_IRQ_H | ||
78 | + | ||
79 | +#include "hw/irq.h" | ||
80 | +#include "hw/sysbus.h" | ||
81 | +#include "qom/object.h" | ||
82 | + | ||
83 | +#define TYPE_SPLIT_IRQ "split-irq" | ||
84 | + | ||
85 | +#define MAX_SPLIT_LINES 16 | ||
86 | + | ||
87 | +typedef struct SplitIRQ SplitIRQ; | ||
88 | + | ||
89 | +#define SPLIT_IRQ(obj) OBJECT_CHECK(SplitIRQ, (obj), TYPE_SPLIT_IRQ) | ||
90 | + | ||
91 | +struct SplitIRQ { | ||
92 | + DeviceState parent_obj; | ||
93 | + | ||
94 | + qemu_irq out_irq[MAX_SPLIT_LINES]; | ||
95 | + uint16_t num_lines; | ||
96 | +}; | ||
97 | + | ||
98 | +#endif | ||
99 | diff --git a/include/hw/irq.h b/include/hw/irq.h | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/include/hw/irq.h | ||
102 | +++ b/include/hw/irq.h | ||
103 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | ||
104 | /* Returns a new IRQ with opposite polarity. */ | ||
105 | qemu_irq qemu_irq_invert(qemu_irq irq); | ||
106 | |||
107 | -/* Returns a new IRQ which feeds into both the passed IRQs */ | ||
108 | +/* Returns a new IRQ which feeds into both the passed IRQs. | ||
109 | + * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
110 | + */ | ||
111 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | ||
112 | |||
113 | /* Returns a new IRQ set which connects 1:1 to another IRQ set, which | ||
114 | diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c | ||
115 | new file mode 100644 | ||
116 | index XXXXXXX..XXXXXXX | ||
117 | --- /dev/null | ||
118 | +++ b/hw/core/split-irq.c | ||
119 | @@ -XXX,XX +XXX,XX @@ | ||
120 | +/* | ||
121 | + * IRQ splitter device. | ||
122 | + * | ||
123 | + * Copyright (c) 2018 Linaro Limited. | ||
124 | + * Written by Peter Maydell | ||
125 | + * | ||
126 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
127 | + * of this software and associated documentation files (the "Software"), to deal | ||
128 | + * in the Software without restriction, including without limitation the rights | ||
129 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
130 | + * copies of the Software, and to permit persons to whom the Software is | ||
131 | + * furnished to do so, subject to the following conditions: | ||
132 | + * | ||
133 | + * The above copyright notice and this permission notice shall be included in | ||
134 | + * all copies or substantial portions of the Software. | ||
135 | + * | ||
136 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
137 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
138 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
139 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
140 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
141 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
142 | + * THE SOFTWARE. | ||
143 | + */ | ||
144 | + | ||
145 | +#include "qemu/osdep.h" | ||
146 | +#include "hw/core/split-irq.h" | ||
147 | +#include "qapi/error.h" | ||
148 | + | ||
149 | +static void split_irq_handler(void *opaque, int n, int level) | ||
150 | +{ | ||
151 | + SplitIRQ *s = SPLIT_IRQ(opaque); | ||
152 | + int i; | ||
153 | + | ||
154 | + for (i = 0; i < s->num_lines; i++) { | ||
155 | + qemu_set_irq(s->out_irq[i], level); | ||
156 | + } | ||
157 | +} | ||
158 | + | ||
159 | +static void split_irq_init(Object *obj) | ||
160 | +{ | ||
161 | + qdev_init_gpio_in(DEVICE(obj), split_irq_handler, 1); | ||
162 | +} | ||
163 | + | ||
164 | +static void split_irq_realize(DeviceState *dev, Error **errp) | ||
165 | +{ | ||
166 | + SplitIRQ *s = SPLIT_IRQ(dev); | ||
167 | + | ||
168 | + if (s->num_lines < 1 || s->num_lines >= MAX_SPLIT_LINES) { | ||
169 | + error_setg(errp, | ||
170 | + "IRQ splitter number of lines %d is not between 1 and %d", | ||
171 | + s->num_lines, MAX_SPLIT_LINES); | ||
172 | + return; | ||
173 | + } | ||
174 | + | ||
175 | + qdev_init_gpio_out(dev, s->out_irq, s->num_lines); | ||
176 | +} | ||
177 | + | ||
178 | +static Property split_irq_properties[] = { | ||
179 | + DEFINE_PROP_UINT16("num-lines", SplitIRQ, num_lines, 1), | ||
180 | + DEFINE_PROP_END_OF_LIST(), | ||
181 | +}; | ||
182 | + | ||
183 | +static void split_irq_class_init(ObjectClass *klass, void *data) | ||
184 | +{ | ||
185 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
186 | + | ||
187 | + /* No state to reset or migrate */ | ||
188 | + dc->props = split_irq_properties; | ||
189 | + dc->realize = split_irq_realize; | ||
190 | + | ||
191 | + /* Reason: Needs to be wired up to work */ | ||
192 | + dc->user_creatable = false; | ||
193 | +} | ||
194 | + | ||
195 | +static const TypeInfo split_irq_type_info = { | ||
196 | + .name = TYPE_SPLIT_IRQ, | ||
197 | + .parent = TYPE_DEVICE, | ||
198 | + .instance_size = sizeof(SplitIRQ), | ||
199 | + .instance_init = split_irq_init, | ||
200 | + .class_init = split_irq_class_init, | ||
201 | +}; | ||
202 | + | ||
203 | +static void split_irq_register_types(void) | ||
204 | +{ | ||
205 | + type_register_static(&split_irq_type_info); | ||
206 | +} | ||
207 | + | ||
208 | +type_init(split_irq_register_types) | ||
209 | -- | ||
210 | 2.16.2 | ||
211 | |||
212 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The MPS2 AN505 FPGA image includes a "FPGA control block" | ||
2 | which is a small set of registers handling LEDs, buttons | ||
3 | and some counters. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180220180325.29818-14-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/misc/Makefile.objs | 1 + | ||
10 | include/hw/misc/mps2-fpgaio.h | 43 ++++++++++ | ||
11 | hw/misc/mps2-fpgaio.c | 176 ++++++++++++++++++++++++++++++++++++++++ | ||
12 | default-configs/arm-softmmu.mak | 1 + | ||
13 | hw/misc/trace-events | 6 ++ | ||
14 | 5 files changed, 227 insertions(+) | ||
15 | create mode 100644 include/hw/misc/mps2-fpgaio.h | ||
16 | create mode 100644 hw/misc/mps2-fpgaio.c | ||
17 | |||
18 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/misc/Makefile.objs | ||
21 | +++ b/hw/misc/Makefile.objs | ||
22 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o | ||
23 | obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o | ||
24 | obj-$(CONFIG_MIPS_CPS) += mips_cpc.o | ||
25 | obj-$(CONFIG_MIPS_ITU) += mips_itu.o | ||
26 | +obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | ||
27 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | ||
28 | |||
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | ||
30 | diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h | ||
31 | new file mode 100644 | ||
32 | index XXXXXXX..XXXXXXX | ||
33 | --- /dev/null | ||
34 | +++ b/include/hw/misc/mps2-fpgaio.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | +/* | ||
37 | + * ARM MPS2 FPGAIO emulation | ||
38 | + * | ||
39 | + * Copyright (c) 2018 Linaro Limited | ||
40 | + * Written by Peter Maydell | ||
41 | + * | ||
42 | + * This program is free software; you can redistribute it and/or modify | ||
43 | + * it under the terms of the GNU General Public License version 2 or | ||
44 | + * (at your option) any later version. | ||
45 | + */ | ||
46 | + | ||
47 | +/* This is a model of the FPGAIO register block in the AN505 | ||
48 | + * FPGA image for the MPS2 dev board; it is documented in the | ||
49 | + * application note: | ||
50 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
51 | + * | ||
52 | + * QEMU interface: | ||
53 | + * + sysbus MMIO region 0: the register bank | ||
54 | + */ | ||
55 | + | ||
56 | +#ifndef MPS2_FPGAIO_H | ||
57 | +#define MPS2_FPGAIO_H | ||
58 | + | ||
59 | +#include "hw/sysbus.h" | ||
60 | + | ||
61 | +#define TYPE_MPS2_FPGAIO "mps2-fpgaio" | ||
62 | +#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO) | ||
63 | + | ||
64 | +typedef struct { | ||
65 | + /*< private >*/ | ||
66 | + SysBusDevice parent_obj; | ||
67 | + | ||
68 | + /*< public >*/ | ||
69 | + MemoryRegion iomem; | ||
70 | + | ||
71 | + uint32_t led0; | ||
72 | + uint32_t prescale; | ||
73 | + uint32_t misc; | ||
74 | + | ||
75 | + uint32_t prescale_clk; | ||
76 | +} MPS2FPGAIO; | ||
77 | + | ||
78 | +#endif | ||
79 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | ||
80 | new file mode 100644 | ||
81 | index XXXXXXX..XXXXXXX | ||
82 | --- /dev/null | ||
83 | +++ b/hw/misc/mps2-fpgaio.c | ||
84 | @@ -XXX,XX +XXX,XX @@ | ||
85 | +/* | ||
86 | + * ARM MPS2 AN505 FPGAIO emulation | ||
87 | + * | ||
88 | + * Copyright (c) 2018 Linaro Limited | ||
89 | + * Written by Peter Maydell | ||
90 | + * | ||
91 | + * This program is free software; you can redistribute it and/or modify | ||
92 | + * it under the terms of the GNU General Public License version 2 or | ||
93 | + * (at your option) any later version. | ||
94 | + */ | ||
95 | + | ||
96 | +/* This is a model of the "FPGA system control and I/O" block found | ||
97 | + * in the AN505 FPGA image for the MPS2 devboard. | ||
98 | + * It is documented in AN505: | ||
99 | + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | ||
100 | + */ | ||
101 | + | ||
102 | +#include "qemu/osdep.h" | ||
103 | +#include "qemu/log.h" | ||
104 | +#include "qapi/error.h" | ||
105 | +#include "trace.h" | ||
106 | +#include "hw/sysbus.h" | ||
107 | +#include "hw/registerfields.h" | ||
108 | +#include "hw/misc/mps2-fpgaio.h" | ||
109 | + | ||
110 | +REG32(LED0, 0) | ||
111 | +REG32(BUTTON, 8) | ||
112 | +REG32(CLK1HZ, 0x10) | ||
113 | +REG32(CLK100HZ, 0x14) | ||
114 | +REG32(COUNTER, 0x18) | ||
115 | +REG32(PRESCALE, 0x1c) | ||
116 | +REG32(PSCNTR, 0x20) | ||
117 | +REG32(MISC, 0x4c) | ||
118 | + | ||
119 | +static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) | ||
120 | +{ | ||
121 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | ||
122 | + uint64_t r; | ||
123 | + | ||
124 | + switch (offset) { | ||
125 | + case A_LED0: | ||
126 | + r = s->led0; | ||
127 | + break; | ||
128 | + case A_BUTTON: | ||
129 | + /* User-pressable board buttons. We don't model that, so just return | ||
130 | + * zeroes. | ||
131 | + */ | ||
132 | + r = 0; | ||
133 | + break; | ||
134 | + case A_PRESCALE: | ||
135 | + r = s->prescale; | ||
136 | + break; | ||
137 | + case A_MISC: | ||
138 | + r = s->misc; | ||
139 | + break; | ||
140 | + case A_CLK1HZ: | ||
141 | + case A_CLK100HZ: | ||
142 | + case A_COUNTER: | ||
143 | + case A_PSCNTR: | ||
144 | + /* These are all upcounters of various frequencies. */ | ||
145 | + qemu_log_mask(LOG_UNIMP, "MPS2 FPGAIO: counters unimplemented\n"); | ||
146 | + r = 0; | ||
147 | + break; | ||
148 | + default: | ||
149 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
150 | + "MPS2 FPGAIO read: bad offset %x\n", (int) offset); | ||
151 | + r = 0; | ||
152 | + break; | ||
153 | + } | ||
154 | + | ||
155 | + trace_mps2_fpgaio_read(offset, r, size); | ||
156 | + return r; | ||
157 | +} | ||
158 | + | ||
159 | +static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, | ||
160 | + unsigned size) | ||
161 | +{ | ||
162 | + MPS2FPGAIO *s = MPS2_FPGAIO(opaque); | ||
163 | + | ||
164 | + trace_mps2_fpgaio_write(offset, value, size); | ||
165 | + | ||
166 | + switch (offset) { | ||
167 | + case A_LED0: | ||
168 | + /* LED bits [1:0] control board LEDs. We don't currently have | ||
169 | + * a mechanism for displaying this graphically, so use a trace event. | ||
170 | + */ | ||
171 | + trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', | ||
172 | + value & 0x01 ? '*' : '.'); | ||
173 | + s->led0 = value & 0x3; | ||
174 | + break; | ||
175 | + case A_PRESCALE: | ||
176 | + s->prescale = value; | ||
177 | + break; | ||
178 | + case A_MISC: | ||
179 | + /* These are control bits for some of the other devices on the | ||
180 | + * board (SPI, CLCD, etc). We don't implement that yet, so just | ||
181 | + * make the bits read as written. | ||
182 | + */ | ||
183 | + qemu_log_mask(LOG_UNIMP, | ||
184 | + "MPS2 FPGAIO: MISC control bits unimplemented\n"); | ||
185 | + s->misc = value; | ||
186 | + break; | ||
187 | + default: | ||
188 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
189 | + "MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset); | ||
190 | + break; | ||
191 | + } | ||
192 | +} | ||
193 | + | ||
194 | +static const MemoryRegionOps mps2_fpgaio_ops = { | ||
195 | + .read = mps2_fpgaio_read, | ||
196 | + .write = mps2_fpgaio_write, | ||
197 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
198 | +}; | ||
199 | + | ||
200 | +static void mps2_fpgaio_reset(DeviceState *dev) | ||
201 | +{ | ||
202 | + MPS2FPGAIO *s = MPS2_FPGAIO(dev); | ||
203 | + | ||
204 | + trace_mps2_fpgaio_reset(); | ||
205 | + s->led0 = 0; | ||
206 | + s->prescale = 0; | ||
207 | + s->misc = 0; | ||
208 | +} | ||
209 | + | ||
210 | +static void mps2_fpgaio_init(Object *obj) | ||
211 | +{ | ||
212 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
213 | + MPS2FPGAIO *s = MPS2_FPGAIO(obj); | ||
214 | + | ||
215 | + memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, | ||
216 | + "mps2-fpgaio", 0x1000); | ||
217 | + sysbus_init_mmio(sbd, &s->iomem); | ||
218 | +} | ||
219 | + | ||
220 | +static const VMStateDescription mps2_fpgaio_vmstate = { | ||
221 | + .name = "mps2-fpgaio", | ||
222 | + .version_id = 1, | ||
223 | + .minimum_version_id = 1, | ||
224 | + .fields = (VMStateField[]) { | ||
225 | + VMSTATE_UINT32(led0, MPS2FPGAIO), | ||
226 | + VMSTATE_UINT32(prescale, MPS2FPGAIO), | ||
227 | + VMSTATE_UINT32(misc, MPS2FPGAIO), | ||
228 | + VMSTATE_END_OF_LIST() | ||
229 | + } | ||
230 | +}; | ||
231 | + | ||
232 | +static Property mps2_fpgaio_properties[] = { | ||
233 | + /* Frequency of the prescale counter */ | ||
234 | + DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), | ||
235 | + DEFINE_PROP_END_OF_LIST(), | ||
236 | +}; | ||
237 | + | ||
238 | +static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) | ||
239 | +{ | ||
240 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
241 | + | ||
242 | + dc->vmsd = &mps2_fpgaio_vmstate; | ||
243 | + dc->reset = mps2_fpgaio_reset; | ||
244 | + dc->props = mps2_fpgaio_properties; | ||
245 | +} | ||
246 | + | ||
247 | +static const TypeInfo mps2_fpgaio_info = { | ||
248 | + .name = TYPE_MPS2_FPGAIO, | ||
249 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
250 | + .instance_size = sizeof(MPS2FPGAIO), | ||
251 | + .instance_init = mps2_fpgaio_init, | ||
252 | + .class_init = mps2_fpgaio_class_init, | ||
253 | +}; | ||
254 | + | ||
255 | +static void mps2_fpgaio_register_types(void) | ||
256 | +{ | ||
257 | + type_register_static(&mps2_fpgaio_info); | ||
258 | +} | ||
259 | + | ||
260 | +type_init(mps2_fpgaio_register_types); | ||
261 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
262 | index XXXXXXX..XXXXXXX 100644 | ||
263 | --- a/default-configs/arm-softmmu.mak | ||
264 | +++ b/default-configs/arm-softmmu.mak | ||
265 | @@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y | ||
266 | CONFIG_CMSDK_APB_TIMER=y | ||
267 | CONFIG_CMSDK_APB_UART=y | ||
268 | |||
269 | +CONFIG_MPS2_FPGAIO=y | ||
270 | CONFIG_MPS2_SCC=y | ||
271 | |||
272 | CONFIG_VERSATILE_PCI=y | ||
273 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
274 | index XXXXXXX..XXXXXXX 100644 | ||
275 | --- a/hw/misc/trace-events | ||
276 | +++ b/hw/misc/trace-events | ||
277 | @@ -XXX,XX +XXX,XX @@ mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, | ||
278 | mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 | ||
279 | mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 | ||
280 | |||
281 | +# hw/misc/mps2_fpgaio.c | ||
282 | +mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
283 | +mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
284 | +mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset" | ||
285 | +mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c" | ||
286 | + | ||
287 | # hw/misc/msf2-sysreg.c | ||
288 | msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 | ||
289 | msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32 | ||
290 | -- | ||
291 | 2.16.2 | ||
292 | |||
293 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add a model of the TrustZone peripheral protection controller (PPC), | ||
2 | which is used to gate transactions to non-TZ-aware peripherals so | ||
3 | that secure software can configure them to not be accessible to | ||
4 | non-secure software. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180220180325.29818-15-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/misc/Makefile.objs | 2 + | ||
11 | include/hw/misc/tz-ppc.h | 101 ++++++++++++++ | ||
12 | hw/misc/tz-ppc.c | 302 ++++++++++++++++++++++++++++++++++++++++ | ||
13 | default-configs/arm-softmmu.mak | 2 + | ||
14 | hw/misc/trace-events | 11 ++ | ||
15 | 5 files changed, 418 insertions(+) | ||
16 | create mode 100644 include/hw/misc/tz-ppc.h | ||
17 | create mode 100644 hw/misc/tz-ppc.c | ||
18 | |||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/misc/Makefile.objs | ||
22 | +++ b/hw/misc/Makefile.objs | ||
23 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o | ||
24 | obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | ||
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | ||
26 | |||
27 | +obj-$(CONFIG_TZ_PPC) += tz-ppc.o | ||
28 | + | ||
29 | obj-$(CONFIG_PVPANIC) += pvpanic.o | ||
30 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | ||
31 | obj-$(CONFIG_AUX) += auxbus.o | ||
32 | diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h | ||
33 | new file mode 100644 | ||
34 | index XXXXXXX..XXXXXXX | ||
35 | --- /dev/null | ||
36 | +++ b/include/hw/misc/tz-ppc.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | +/* | ||
39 | + * ARM TrustZone peripheral protection controller emulation | ||
40 | + * | ||
41 | + * Copyright (c) 2018 Linaro Limited | ||
42 | + * Written by Peter Maydell | ||
43 | + * | ||
44 | + * This program is free software; you can redistribute it and/or modify | ||
45 | + * it under the terms of the GNU General Public License version 2 or | ||
46 | + * (at your option) any later version. | ||
47 | + */ | ||
48 | + | ||
49 | +/* This is a model of the TrustZone peripheral protection controller (PPC). | ||
50 | + * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM | ||
51 | + * (DDI 0571G): | ||
52 | + * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g | ||
53 | + * | ||
54 | + * The PPC sits in front of peripherals and allows secure software to | ||
55 | + * configure it to either pass through or reject transactions. | ||
56 | + * Rejected transactions may be configured to either be aborted, or to | ||
57 | + * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. | ||
58 | + * | ||
59 | + * The PPC has no register interface -- it is configured purely by a | ||
60 | + * collection of input signals from other hardware in the system. Typically | ||
61 | + * they are either hardwired or exposed in an ad-hoc register interface by | ||
62 | + * the SoC that uses the PPC. | ||
63 | + * | ||
64 | + * This QEMU model can be used to model either the AHB5 or APB4 TZ PPC, | ||
65 | + * since the only difference between them is that the AHB version has a | ||
66 | + * "default" port which has no security checks applied. In QEMU the default | ||
67 | + * port can be emulated simply by wiring its downstream devices directly | ||
68 | + * into the parent address space, since the PPC does not need to intercept | ||
69 | + * transactions there. | ||
70 | + * | ||
71 | + * In the hardware, selection of which downstream port to use is done by | ||
72 | + * the user's decode logic asserting one of the hsel[] signals. In QEMU, | ||
73 | + * we provide 16 MMIO regions, one per port, and the user maps these into | ||
74 | + * the desired addresses to implement the address decode. | ||
75 | + * | ||
76 | + * QEMU interface: | ||
77 | + * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end | ||
78 | + * of each of the 16 ports of the PPC | ||
79 | + * + Property "port[0..15]": MemoryRegion defining the downstream device(s) | ||
80 | + * for each of the 16 ports of the PPC | ||
81 | + * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be | ||
82 | + * accessible to NonSecure transactions | ||
83 | + * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be | ||
84 | + * accessible to non-privileged transactions | ||
85 | + * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should | ||
86 | + * result in a transaction error, or 0 for the transaction to RAZ/WI | ||
87 | + * + Named GPIO input "irq_enable": set to 1 to enable interrupts | ||
88 | + * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt | ||
89 | + * + Named GPIO output "irq": set for a transaction-failed interrupt | ||
90 | + * + Property "NONSEC_MASK": if a bit is set in this mask then accesses to | ||
91 | + * the associated port do not have the TZ security check performed. (This | ||
92 | + * corresponds to the hardware allowing this to be set as a Verilog | ||
93 | + * parameter.) | ||
94 | + */ | ||
95 | + | ||
96 | +#ifndef TZ_PPC_H | ||
97 | +#define TZ_PPC_H | ||
98 | + | ||
99 | +#include "hw/sysbus.h" | ||
100 | + | ||
101 | +#define TYPE_TZ_PPC "tz-ppc" | ||
102 | +#define TZ_PPC(obj) OBJECT_CHECK(TZPPC, (obj), TYPE_TZ_PPC) | ||
103 | + | ||
104 | +#define TZ_NUM_PORTS 16 | ||
105 | + | ||
106 | +typedef struct TZPPC TZPPC; | ||
107 | + | ||
108 | +typedef struct TZPPCPort { | ||
109 | + TZPPC *ppc; | ||
110 | + MemoryRegion upstream; | ||
111 | + AddressSpace downstream_as; | ||
112 | + MemoryRegion *downstream; | ||
113 | +} TZPPCPort; | ||
114 | + | ||
115 | +struct TZPPC { | ||
116 | + /*< private >*/ | ||
117 | + SysBusDevice parent_obj; | ||
118 | + | ||
119 | + /*< public >*/ | ||
120 | + | ||
121 | + /* State: these just track the values of our input signals */ | ||
122 | + bool cfg_nonsec[TZ_NUM_PORTS]; | ||
123 | + bool cfg_ap[TZ_NUM_PORTS]; | ||
124 | + bool cfg_sec_resp; | ||
125 | + bool irq_enable; | ||
126 | + bool irq_clear; | ||
127 | + /* State: are we asserting irq ? */ | ||
128 | + bool irq_status; | ||
129 | + | ||
130 | + qemu_irq irq; | ||
131 | + | ||
132 | + /* Properties */ | ||
133 | + uint32_t nonsec_mask; | ||
134 | + | ||
135 | + TZPPCPort port[TZ_NUM_PORTS]; | ||
136 | +}; | ||
137 | + | ||
138 | +#endif | ||
139 | diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c | ||
140 | new file mode 100644 | ||
141 | index XXXXXXX..XXXXXXX | ||
142 | --- /dev/null | ||
143 | +++ b/hw/misc/tz-ppc.c | ||
144 | @@ -XXX,XX +XXX,XX @@ | ||
145 | +/* | ||
146 | + * ARM TrustZone peripheral protection controller emulation | ||
147 | + * | ||
148 | + * Copyright (c) 2018 Linaro Limited | ||
149 | + * Written by Peter Maydell | ||
150 | + * | ||
151 | + * This program is free software; you can redistribute it and/or modify | ||
152 | + * it under the terms of the GNU General Public License version 2 or | ||
153 | + * (at your option) any later version. | ||
154 | + */ | ||
155 | + | ||
156 | +#include "qemu/osdep.h" | ||
157 | +#include "qemu/log.h" | ||
158 | +#include "qapi/error.h" | ||
159 | +#include "trace.h" | ||
160 | +#include "hw/sysbus.h" | ||
161 | +#include "hw/registerfields.h" | ||
162 | +#include "hw/misc/tz-ppc.h" | ||
163 | + | ||
164 | +static void tz_ppc_update_irq(TZPPC *s) | ||
165 | +{ | ||
166 | + bool level = s->irq_status && s->irq_enable; | ||
167 | + | ||
168 | + trace_tz_ppc_update_irq(level); | ||
169 | + qemu_set_irq(s->irq, level); | ||
170 | +} | ||
171 | + | ||
172 | +static void tz_ppc_cfg_nonsec(void *opaque, int n, int level) | ||
173 | +{ | ||
174 | + TZPPC *s = TZ_PPC(opaque); | ||
175 | + | ||
176 | + assert(n < TZ_NUM_PORTS); | ||
177 | + trace_tz_ppc_cfg_nonsec(n, level); | ||
178 | + s->cfg_nonsec[n] = level; | ||
179 | +} | ||
180 | + | ||
181 | +static void tz_ppc_cfg_ap(void *opaque, int n, int level) | ||
182 | +{ | ||
183 | + TZPPC *s = TZ_PPC(opaque); | ||
184 | + | ||
185 | + assert(n < TZ_NUM_PORTS); | ||
186 | + trace_tz_ppc_cfg_ap(n, level); | ||
187 | + s->cfg_ap[n] = level; | ||
188 | +} | ||
189 | + | ||
190 | +static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level) | ||
191 | +{ | ||
192 | + TZPPC *s = TZ_PPC(opaque); | ||
193 | + | ||
194 | + trace_tz_ppc_cfg_sec_resp(level); | ||
195 | + s->cfg_sec_resp = level; | ||
196 | +} | ||
197 | + | ||
198 | +static void tz_ppc_irq_enable(void *opaque, int n, int level) | ||
199 | +{ | ||
200 | + TZPPC *s = TZ_PPC(opaque); | ||
201 | + | ||
202 | + trace_tz_ppc_irq_enable(level); | ||
203 | + s->irq_enable = level; | ||
204 | + tz_ppc_update_irq(s); | ||
205 | +} | ||
206 | + | ||
207 | +static void tz_ppc_irq_clear(void *opaque, int n, int level) | ||
208 | +{ | ||
209 | + TZPPC *s = TZ_PPC(opaque); | ||
210 | + | ||
211 | + trace_tz_ppc_irq_clear(level); | ||
212 | + | ||
213 | + s->irq_clear = level; | ||
214 | + if (level) { | ||
215 | + s->irq_status = false; | ||
216 | + tz_ppc_update_irq(s); | ||
217 | + } | ||
218 | +} | ||
219 | + | ||
220 | +static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs) | ||
221 | +{ | ||
222 | + /* Check whether to allow an access to port n; return true if | ||
223 | + * the check passes, and false if the transaction must be blocked. | ||
224 | + * If the latter, the caller must check cfg_sec_resp to determine | ||
225 | + * whether to abort or RAZ/WI the transaction. | ||
226 | + * The checks are: | ||
227 | + * + nonsec_mask suppresses any check of the secure attribute | ||
228 | + * + otherwise, block if cfg_nonsec is 1 and transaction is secure, | ||
229 | + * or if cfg_nonsec is 0 and transaction is non-secure | ||
230 | + * + block if transaction is usermode and cfg_ap is 0 | ||
231 | + */ | ||
232 | + if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) || | ||
233 | + (attrs.user && !s->cfg_ap[n])) { | ||
234 | + /* Block the transaction. */ | ||
235 | + if (!s->irq_clear) { | ||
236 | + /* Note that holding irq_clear high suppresses interrupts */ | ||
237 | + s->irq_status = true; | ||
238 | + tz_ppc_update_irq(s); | ||
239 | + } | ||
240 | + return false; | ||
241 | + } | ||
242 | + return true; | ||
243 | +} | ||
244 | + | ||
245 | +static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata, | ||
246 | + unsigned size, MemTxAttrs attrs) | ||
247 | +{ | ||
248 | + TZPPCPort *p = opaque; | ||
249 | + TZPPC *s = p->ppc; | ||
250 | + int n = p - s->port; | ||
251 | + AddressSpace *as = &p->downstream_as; | ||
252 | + uint64_t data; | ||
253 | + MemTxResult res; | ||
254 | + | ||
255 | + if (!tz_ppc_check(s, n, attrs)) { | ||
256 | + trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user); | ||
257 | + if (s->cfg_sec_resp) { | ||
258 | + return MEMTX_ERROR; | ||
259 | + } else { | ||
260 | + *pdata = 0; | ||
261 | + return MEMTX_OK; | ||
262 | + } | ||
263 | + } | ||
264 | + | ||
265 | + switch (size) { | ||
266 | + case 1: | ||
267 | + data = address_space_ldub(as, addr, attrs, &res); | ||
268 | + break; | ||
269 | + case 2: | ||
270 | + data = address_space_lduw_le(as, addr, attrs, &res); | ||
271 | + break; | ||
272 | + case 4: | ||
273 | + data = address_space_ldl_le(as, addr, attrs, &res); | ||
274 | + break; | ||
275 | + case 8: | ||
276 | + data = address_space_ldq_le(as, addr, attrs, &res); | ||
277 | + break; | ||
278 | + default: | ||
279 | + g_assert_not_reached(); | ||
280 | + } | ||
281 | + *pdata = data; | ||
282 | + return res; | ||
283 | +} | ||
284 | + | ||
285 | +static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val, | ||
286 | + unsigned size, MemTxAttrs attrs) | ||
287 | +{ | ||
288 | + TZPPCPort *p = opaque; | ||
289 | + TZPPC *s = p->ppc; | ||
290 | + AddressSpace *as = &p->downstream_as; | ||
291 | + int n = p - s->port; | ||
292 | + MemTxResult res; | ||
293 | + | ||
294 | + if (!tz_ppc_check(s, n, attrs)) { | ||
295 | + trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user); | ||
296 | + if (s->cfg_sec_resp) { | ||
297 | + return MEMTX_ERROR; | ||
298 | + } else { | ||
299 | + return MEMTX_OK; | ||
300 | + } | ||
301 | + } | ||
302 | + | ||
303 | + switch (size) { | ||
304 | + case 1: | ||
305 | + address_space_stb(as, addr, val, attrs, &res); | ||
306 | + break; | ||
307 | + case 2: | ||
308 | + address_space_stw_le(as, addr, val, attrs, &res); | ||
309 | + break; | ||
310 | + case 4: | ||
311 | + address_space_stl_le(as, addr, val, attrs, &res); | ||
312 | + break; | ||
313 | + case 8: | ||
314 | + address_space_stq_le(as, addr, val, attrs, &res); | ||
315 | + break; | ||
316 | + default: | ||
317 | + g_assert_not_reached(); | ||
318 | + } | ||
319 | + return res; | ||
320 | +} | ||
321 | + | ||
322 | +static const MemoryRegionOps tz_ppc_ops = { | ||
323 | + .read_with_attrs = tz_ppc_read, | ||
324 | + .write_with_attrs = tz_ppc_write, | ||
325 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
326 | +}; | ||
327 | + | ||
328 | +static void tz_ppc_reset(DeviceState *dev) | ||
329 | +{ | ||
330 | + TZPPC *s = TZ_PPC(dev); | ||
331 | + | ||
332 | + trace_tz_ppc_reset(); | ||
333 | + s->cfg_sec_resp = false; | ||
334 | + memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec)); | ||
335 | + memset(s->cfg_ap, 0, sizeof(s->cfg_ap)); | ||
336 | +} | ||
337 | + | ||
338 | +static void tz_ppc_init(Object *obj) | ||
339 | +{ | ||
340 | + DeviceState *dev = DEVICE(obj); | ||
341 | + TZPPC *s = TZ_PPC(obj); | ||
342 | + | ||
343 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS); | ||
344 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS); | ||
345 | + qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1); | ||
346 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1); | ||
347 | + qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1); | ||
348 | + qdev_init_gpio_out_named(dev, &s->irq, "irq", 1); | ||
349 | +} | ||
350 | + | ||
351 | +static void tz_ppc_realize(DeviceState *dev, Error **errp) | ||
352 | +{ | ||
353 | + Object *obj = OBJECT(dev); | ||
354 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
355 | + TZPPC *s = TZ_PPC(dev); | ||
356 | + int i; | ||
357 | + | ||
358 | + /* We can't create the upstream end of the port until realize, | ||
359 | + * as we don't know the size of the MR used as the downstream until then. | ||
360 | + */ | ||
361 | + for (i = 0; i < TZ_NUM_PORTS; i++) { | ||
362 | + TZPPCPort *port = &s->port[i]; | ||
363 | + char *name; | ||
364 | + uint64_t size; | ||
365 | + | ||
366 | + if (!port->downstream) { | ||
367 | + continue; | ||
368 | + } | ||
369 | + | ||
370 | + name = g_strdup_printf("tz-ppc-port[%d]", i); | ||
371 | + | ||
372 | + port->ppc = s; | ||
373 | + address_space_init(&port->downstream_as, port->downstream, name); | ||
374 | + | ||
375 | + size = memory_region_size(port->downstream); | ||
376 | + memory_region_init_io(&port->upstream, obj, &tz_ppc_ops, | ||
377 | + port, name, size); | ||
378 | + sysbus_init_mmio(sbd, &port->upstream); | ||
379 | + g_free(name); | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +static const VMStateDescription tz_ppc_vmstate = { | ||
384 | + .name = "tz-ppc", | ||
385 | + .version_id = 1, | ||
386 | + .minimum_version_id = 1, | ||
387 | + .fields = (VMStateField[]) { | ||
388 | + VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16), | ||
389 | + VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16), | ||
390 | + VMSTATE_BOOL(cfg_sec_resp, TZPPC), | ||
391 | + VMSTATE_BOOL(irq_enable, TZPPC), | ||
392 | + VMSTATE_BOOL(irq_clear, TZPPC), | ||
393 | + VMSTATE_BOOL(irq_status, TZPPC), | ||
394 | + VMSTATE_END_OF_LIST() | ||
395 | + } | ||
396 | +}; | ||
397 | + | ||
398 | +#define DEFINE_PORT(N) \ | ||
399 | + DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \ | ||
400 | + TYPE_MEMORY_REGION, MemoryRegion *) | ||
401 | + | ||
402 | +static Property tz_ppc_properties[] = { | ||
403 | + DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0), | ||
404 | + DEFINE_PORT(0), | ||
405 | + DEFINE_PORT(1), | ||
406 | + DEFINE_PORT(2), | ||
407 | + DEFINE_PORT(3), | ||
408 | + DEFINE_PORT(4), | ||
409 | + DEFINE_PORT(5), | ||
410 | + DEFINE_PORT(6), | ||
411 | + DEFINE_PORT(7), | ||
412 | + DEFINE_PORT(8), | ||
413 | + DEFINE_PORT(9), | ||
414 | + DEFINE_PORT(10), | ||
415 | + DEFINE_PORT(11), | ||
416 | + DEFINE_PORT(12), | ||
417 | + DEFINE_PORT(13), | ||
418 | + DEFINE_PORT(14), | ||
419 | + DEFINE_PORT(15), | ||
420 | + DEFINE_PROP_END_OF_LIST(), | ||
421 | +}; | ||
422 | + | ||
423 | +static void tz_ppc_class_init(ObjectClass *klass, void *data) | ||
424 | +{ | ||
425 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
426 | + | ||
427 | + dc->realize = tz_ppc_realize; | ||
428 | + dc->vmsd = &tz_ppc_vmstate; | ||
429 | + dc->reset = tz_ppc_reset; | ||
430 | + dc->props = tz_ppc_properties; | ||
431 | +} | ||
432 | + | ||
433 | +static const TypeInfo tz_ppc_info = { | ||
434 | + .name = TYPE_TZ_PPC, | ||
435 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
436 | + .instance_size = sizeof(TZPPC), | ||
437 | + .instance_init = tz_ppc_init, | ||
438 | + .class_init = tz_ppc_class_init, | ||
439 | +}; | ||
440 | + | ||
441 | +static void tz_ppc_register_types(void) | ||
442 | +{ | ||
443 | + type_register_static(&tz_ppc_info); | ||
444 | +} | ||
445 | + | ||
446 | +type_init(tz_ppc_register_types); | ||
447 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
448 | index XXXXXXX..XXXXXXX 100644 | ||
449 | --- a/default-configs/arm-softmmu.mak | ||
450 | +++ b/default-configs/arm-softmmu.mak | ||
451 | @@ -XXX,XX +XXX,XX @@ CONFIG_CMSDK_APB_UART=y | ||
452 | CONFIG_MPS2_FPGAIO=y | ||
453 | CONFIG_MPS2_SCC=y | ||
454 | |||
455 | +CONFIG_TZ_PPC=y | ||
456 | + | ||
457 | CONFIG_VERSATILE_PCI=y | ||
458 | CONFIG_VERSATILE_I2C=y | ||
459 | |||
460 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
461 | index XXXXXXX..XXXXXXX 100644 | ||
462 | --- a/hw/misc/trace-events | ||
463 | +++ b/hw/misc/trace-events | ||
464 | @@ -XXX,XX +XXX,XX @@ mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d co | ||
465 | mos6522_set_sr_int(void) "set sr_int" | ||
466 | mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 | ||
467 | mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" | ||
468 | + | ||
469 | +# hw/misc/tz-ppc.c | ||
470 | +tz_ppc_reset(void) "TZ PPC: reset" | ||
471 | +tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d" | ||
472 | +tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d" | ||
473 | +tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d" | ||
474 | +tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d" | ||
475 | +tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
476 | +tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
477 | +tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
478 | +tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
479 | -- | ||
480 | 2.16.2 | ||
481 | |||
482 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The Arm IoT Kit includes a "security controller" which is largely a | ||
2 | collection of registers for controlling the PPCs and other bits of | ||
3 | glue in the system. This commit provides the initial skeleton of the | ||
4 | device, implementing just the ID registers, and a couple of read-only | ||
5 | read-as-zero registers. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180220180325.29818-16-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/misc/Makefile.objs | 1 + | ||
12 | include/hw/misc/iotkit-secctl.h | 39 ++++ | ||
13 | hw/misc/iotkit-secctl.c | 448 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | default-configs/arm-softmmu.mak | 1 + | ||
15 | hw/misc/trace-events | 7 + | ||
16 | 5 files changed, 496 insertions(+) | ||
17 | create mode 100644 include/hw/misc/iotkit-secctl.h | ||
18 | create mode 100644 hw/misc/iotkit-secctl.c | ||
19 | |||
20 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/misc/Makefile.objs | ||
23 | +++ b/hw/misc/Makefile.objs | ||
24 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o | ||
25 | obj-$(CONFIG_MPS2_SCC) += mps2-scc.o | ||
26 | |||
27 | obj-$(CONFIG_TZ_PPC) += tz-ppc.o | ||
28 | +obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o | ||
29 | |||
30 | obj-$(CONFIG_PVPANIC) += pvpanic.o | ||
31 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | ||
32 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
33 | new file mode 100644 | ||
34 | index XXXXXXX..XXXXXXX | ||
35 | --- /dev/null | ||
36 | +++ b/include/hw/misc/iotkit-secctl.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | +/* | ||
39 | + * ARM IoT Kit security controller | ||
40 | + * | ||
41 | + * Copyright (c) 2018 Linaro Limited | ||
42 | + * Written by Peter Maydell | ||
43 | + * | ||
44 | + * This program is free software; you can redistribute it and/or modify | ||
45 | + * it under the terms of the GNU General Public License version 2 or | ||
46 | + * (at your option) any later version. | ||
47 | + */ | ||
48 | + | ||
49 | +/* This is a model of the security controller which is part of the | ||
50 | + * Arm IoT Kit and documented in | ||
51 | + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | ||
52 | + * | ||
53 | + * QEMU interface: | ||
54 | + * + sysbus MMIO region 0 is the "secure privilege control block" registers | ||
55 | + * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
56 | + */ | ||
57 | + | ||
58 | +#ifndef IOTKIT_SECCTL_H | ||
59 | +#define IOTKIT_SECCTL_H | ||
60 | + | ||
61 | +#include "hw/sysbus.h" | ||
62 | + | ||
63 | +#define TYPE_IOTKIT_SECCTL "iotkit-secctl" | ||
64 | +#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL) | ||
65 | + | ||
66 | +typedef struct IoTKitSecCtl { | ||
67 | + /*< private >*/ | ||
68 | + SysBusDevice parent_obj; | ||
69 | + | ||
70 | + /*< public >*/ | ||
71 | + | ||
72 | + MemoryRegion s_regs; | ||
73 | + MemoryRegion ns_regs; | ||
74 | +} IoTKitSecCtl; | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
78 | new file mode 100644 | ||
79 | index XXXXXXX..XXXXXXX | ||
80 | --- /dev/null | ||
81 | +++ b/hw/misc/iotkit-secctl.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | ||
83 | +/* | ||
84 | + * Arm IoT Kit security controller | ||
85 | + * | ||
86 | + * Copyright (c) 2018 Linaro Limited | ||
87 | + * Written by Peter Maydell | ||
88 | + * | ||
89 | + * This program is free software; you can redistribute it and/or modify | ||
90 | + * it under the terms of the GNU General Public License version 2 or | ||
91 | + * (at your option) any later version. | ||
92 | + */ | ||
93 | + | ||
94 | +#include "qemu/osdep.h" | ||
95 | +#include "qemu/log.h" | ||
96 | +#include "qapi/error.h" | ||
97 | +#include "trace.h" | ||
98 | +#include "hw/sysbus.h" | ||
99 | +#include "hw/registerfields.h" | ||
100 | +#include "hw/misc/iotkit-secctl.h" | ||
101 | + | ||
102 | +/* Registers in the secure privilege control block */ | ||
103 | +REG32(SECRESPCFG, 0x10) | ||
104 | +REG32(NSCCFG, 0x14) | ||
105 | +REG32(SECMPCINTSTATUS, 0x1c) | ||
106 | +REG32(SECPPCINTSTAT, 0x20) | ||
107 | +REG32(SECPPCINTCLR, 0x24) | ||
108 | +REG32(SECPPCINTEN, 0x28) | ||
109 | +REG32(SECMSCINTSTAT, 0x30) | ||
110 | +REG32(SECMSCINTCLR, 0x34) | ||
111 | +REG32(SECMSCINTEN, 0x38) | ||
112 | +REG32(BRGINTSTAT, 0x40) | ||
113 | +REG32(BRGINTCLR, 0x44) | ||
114 | +REG32(BRGINTEN, 0x48) | ||
115 | +REG32(AHBNSPPC0, 0x50) | ||
116 | +REG32(AHBNSPPCEXP0, 0x60) | ||
117 | +REG32(AHBNSPPCEXP1, 0x64) | ||
118 | +REG32(AHBNSPPCEXP2, 0x68) | ||
119 | +REG32(AHBNSPPCEXP3, 0x6c) | ||
120 | +REG32(APBNSPPC0, 0x70) | ||
121 | +REG32(APBNSPPC1, 0x74) | ||
122 | +REG32(APBNSPPCEXP0, 0x80) | ||
123 | +REG32(APBNSPPCEXP1, 0x84) | ||
124 | +REG32(APBNSPPCEXP2, 0x88) | ||
125 | +REG32(APBNSPPCEXP3, 0x8c) | ||
126 | +REG32(AHBSPPPC0, 0x90) | ||
127 | +REG32(AHBSPPPCEXP0, 0xa0) | ||
128 | +REG32(AHBSPPPCEXP1, 0xa4) | ||
129 | +REG32(AHBSPPPCEXP2, 0xa8) | ||
130 | +REG32(AHBSPPPCEXP3, 0xac) | ||
131 | +REG32(APBSPPPC0, 0xb0) | ||
132 | +REG32(APBSPPPC1, 0xb4) | ||
133 | +REG32(APBSPPPCEXP0, 0xc0) | ||
134 | +REG32(APBSPPPCEXP1, 0xc4) | ||
135 | +REG32(APBSPPPCEXP2, 0xc8) | ||
136 | +REG32(APBSPPPCEXP3, 0xcc) | ||
137 | +REG32(NSMSCEXP, 0xd0) | ||
138 | +REG32(PID4, 0xfd0) | ||
139 | +REG32(PID5, 0xfd4) | ||
140 | +REG32(PID6, 0xfd8) | ||
141 | +REG32(PID7, 0xfdc) | ||
142 | +REG32(PID0, 0xfe0) | ||
143 | +REG32(PID1, 0xfe4) | ||
144 | +REG32(PID2, 0xfe8) | ||
145 | +REG32(PID3, 0xfec) | ||
146 | +REG32(CID0, 0xff0) | ||
147 | +REG32(CID1, 0xff4) | ||
148 | +REG32(CID2, 0xff8) | ||
149 | +REG32(CID3, 0xffc) | ||
150 | + | ||
151 | +/* Registers in the non-secure privilege control block */ | ||
152 | +REG32(AHBNSPPPC0, 0x90) | ||
153 | +REG32(AHBNSPPPCEXP0, 0xa0) | ||
154 | +REG32(AHBNSPPPCEXP1, 0xa4) | ||
155 | +REG32(AHBNSPPPCEXP2, 0xa8) | ||
156 | +REG32(AHBNSPPPCEXP3, 0xac) | ||
157 | +REG32(APBNSPPPC0, 0xb0) | ||
158 | +REG32(APBNSPPPC1, 0xb4) | ||
159 | +REG32(APBNSPPPCEXP0, 0xc0) | ||
160 | +REG32(APBNSPPPCEXP1, 0xc4) | ||
161 | +REG32(APBNSPPPCEXP2, 0xc8) | ||
162 | +REG32(APBNSPPPCEXP3, 0xcc) | ||
163 | +/* PID and CID registers are also present in the NS block */ | ||
164 | + | ||
165 | +static const uint8_t iotkit_secctl_s_idregs[] = { | ||
166 | + 0x04, 0x00, 0x00, 0x00, | ||
167 | + 0x52, 0xb8, 0x0b, 0x00, | ||
168 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
169 | +}; | ||
170 | + | ||
171 | +static const uint8_t iotkit_secctl_ns_idregs[] = { | ||
172 | + 0x04, 0x00, 0x00, 0x00, | ||
173 | + 0x53, 0xb8, 0x0b, 0x00, | ||
174 | + 0x0d, 0xf0, 0x05, 0xb1, | ||
175 | +}; | ||
176 | + | ||
177 | +static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
178 | + uint64_t *pdata, | ||
179 | + unsigned size, MemTxAttrs attrs) | ||
180 | +{ | ||
181 | + uint64_t r; | ||
182 | + uint32_t offset = addr & ~0x3; | ||
183 | + | ||
184 | + switch (offset) { | ||
185 | + case A_AHBNSPPC0: | ||
186 | + case A_AHBSPPPC0: | ||
187 | + r = 0; | ||
188 | + break; | ||
189 | + case A_SECRESPCFG: | ||
190 | + case A_NSCCFG: | ||
191 | + case A_SECMPCINTSTATUS: | ||
192 | + case A_SECPPCINTSTAT: | ||
193 | + case A_SECPPCINTEN: | ||
194 | + case A_SECMSCINTSTAT: | ||
195 | + case A_SECMSCINTEN: | ||
196 | + case A_BRGINTSTAT: | ||
197 | + case A_BRGINTEN: | ||
198 | + case A_AHBNSPPCEXP0: | ||
199 | + case A_AHBNSPPCEXP1: | ||
200 | + case A_AHBNSPPCEXP2: | ||
201 | + case A_AHBNSPPCEXP3: | ||
202 | + case A_APBNSPPC0: | ||
203 | + case A_APBNSPPC1: | ||
204 | + case A_APBNSPPCEXP0: | ||
205 | + case A_APBNSPPCEXP1: | ||
206 | + case A_APBNSPPCEXP2: | ||
207 | + case A_APBNSPPCEXP3: | ||
208 | + case A_AHBSPPPCEXP0: | ||
209 | + case A_AHBSPPPCEXP1: | ||
210 | + case A_AHBSPPPCEXP2: | ||
211 | + case A_AHBSPPPCEXP3: | ||
212 | + case A_APBSPPPC0: | ||
213 | + case A_APBSPPPC1: | ||
214 | + case A_APBSPPPCEXP0: | ||
215 | + case A_APBSPPPCEXP1: | ||
216 | + case A_APBSPPPCEXP2: | ||
217 | + case A_APBSPPPCEXP3: | ||
218 | + case A_NSMSCEXP: | ||
219 | + qemu_log_mask(LOG_UNIMP, | ||
220 | + "IoTKit SecCtl S block read: " | ||
221 | + "unimplemented offset 0x%x\n", offset); | ||
222 | + r = 0; | ||
223 | + break; | ||
224 | + case A_PID4: | ||
225 | + case A_PID5: | ||
226 | + case A_PID6: | ||
227 | + case A_PID7: | ||
228 | + case A_PID0: | ||
229 | + case A_PID1: | ||
230 | + case A_PID2: | ||
231 | + case A_PID3: | ||
232 | + case A_CID0: | ||
233 | + case A_CID1: | ||
234 | + case A_CID2: | ||
235 | + case A_CID3: | ||
236 | + r = iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; | ||
237 | + break; | ||
238 | + case A_SECPPCINTCLR: | ||
239 | + case A_SECMSCINTCLR: | ||
240 | + case A_BRGINTCLR: | ||
241 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
242 | + "IotKit SecCtl S block read: write-only offset 0x%x\n", | ||
243 | + offset); | ||
244 | + r = 0; | ||
245 | + break; | ||
246 | + default: | ||
247 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
248 | + "IotKit SecCtl S block read: bad offset 0x%x\n", offset); | ||
249 | + r = 0; | ||
250 | + break; | ||
251 | + } | ||
252 | + | ||
253 | + if (size != 4) { | ||
254 | + /* None of our registers are access-sensitive, so just pull the right | ||
255 | + * byte out of the word read result. | ||
256 | + */ | ||
257 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
258 | + } | ||
259 | + | ||
260 | + trace_iotkit_secctl_s_read(offset, r, size); | ||
261 | + *pdata = r; | ||
262 | + return MEMTX_OK; | ||
263 | +} | ||
264 | + | ||
265 | +static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
266 | + uint64_t value, | ||
267 | + unsigned size, MemTxAttrs attrs) | ||
268 | +{ | ||
269 | + uint32_t offset = addr; | ||
270 | + | ||
271 | + trace_iotkit_secctl_s_write(offset, value, size); | ||
272 | + | ||
273 | + if (size != 4) { | ||
274 | + /* Byte and halfword writes are ignored */ | ||
275 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
276 | + "IotKit SecCtl S block write: bad size, ignored\n"); | ||
277 | + return MEMTX_OK; | ||
278 | + } | ||
279 | + | ||
280 | + switch (offset) { | ||
281 | + case A_SECRESPCFG: | ||
282 | + case A_NSCCFG: | ||
283 | + case A_SECPPCINTCLR: | ||
284 | + case A_SECPPCINTEN: | ||
285 | + case A_SECMSCINTCLR: | ||
286 | + case A_SECMSCINTEN: | ||
287 | + case A_BRGINTCLR: | ||
288 | + case A_BRGINTEN: | ||
289 | + case A_AHBNSPPCEXP0: | ||
290 | + case A_AHBNSPPCEXP1: | ||
291 | + case A_AHBNSPPCEXP2: | ||
292 | + case A_AHBNSPPCEXP3: | ||
293 | + case A_APBNSPPC0: | ||
294 | + case A_APBNSPPC1: | ||
295 | + case A_APBNSPPCEXP0: | ||
296 | + case A_APBNSPPCEXP1: | ||
297 | + case A_APBNSPPCEXP2: | ||
298 | + case A_APBNSPPCEXP3: | ||
299 | + case A_AHBSPPPCEXP0: | ||
300 | + case A_AHBSPPPCEXP1: | ||
301 | + case A_AHBSPPPCEXP2: | ||
302 | + case A_AHBSPPPCEXP3: | ||
303 | + case A_APBSPPPC0: | ||
304 | + case A_APBSPPPC1: | ||
305 | + case A_APBSPPPCEXP0: | ||
306 | + case A_APBSPPPCEXP1: | ||
307 | + case A_APBSPPPCEXP2: | ||
308 | + case A_APBSPPPCEXP3: | ||
309 | + qemu_log_mask(LOG_UNIMP, | ||
310 | + "IoTKit SecCtl S block write: " | ||
311 | + "unimplemented offset 0x%x\n", offset); | ||
312 | + break; | ||
313 | + case A_SECMPCINTSTATUS: | ||
314 | + case A_SECPPCINTSTAT: | ||
315 | + case A_SECMSCINTSTAT: | ||
316 | + case A_BRGINTSTAT: | ||
317 | + case A_AHBNSPPC0: | ||
318 | + case A_AHBSPPPC0: | ||
319 | + case A_NSMSCEXP: | ||
320 | + case A_PID4: | ||
321 | + case A_PID5: | ||
322 | + case A_PID6: | ||
323 | + case A_PID7: | ||
324 | + case A_PID0: | ||
325 | + case A_PID1: | ||
326 | + case A_PID2: | ||
327 | + case A_PID3: | ||
328 | + case A_CID0: | ||
329 | + case A_CID1: | ||
330 | + case A_CID2: | ||
331 | + case A_CID3: | ||
332 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
333 | + "IoTKit SecCtl S block write: " | ||
334 | + "read-only offset 0x%x\n", offset); | ||
335 | + break; | ||
336 | + default: | ||
337 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
338 | + "IotKit SecCtl S block write: bad offset 0x%x\n", | ||
339 | + offset); | ||
340 | + break; | ||
341 | + } | ||
342 | + | ||
343 | + return MEMTX_OK; | ||
344 | +} | ||
345 | + | ||
346 | +static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr, | ||
347 | + uint64_t *pdata, | ||
348 | + unsigned size, MemTxAttrs attrs) | ||
349 | +{ | ||
350 | + uint64_t r; | ||
351 | + uint32_t offset = addr & ~0x3; | ||
352 | + | ||
353 | + switch (offset) { | ||
354 | + case A_AHBNSPPPC0: | ||
355 | + r = 0; | ||
356 | + break; | ||
357 | + case A_AHBNSPPPCEXP0: | ||
358 | + case A_AHBNSPPPCEXP1: | ||
359 | + case A_AHBNSPPPCEXP2: | ||
360 | + case A_AHBNSPPPCEXP3: | ||
361 | + case A_APBNSPPPC0: | ||
362 | + case A_APBNSPPPC1: | ||
363 | + case A_APBNSPPPCEXP0: | ||
364 | + case A_APBNSPPPCEXP1: | ||
365 | + case A_APBNSPPPCEXP2: | ||
366 | + case A_APBNSPPPCEXP3: | ||
367 | + qemu_log_mask(LOG_UNIMP, | ||
368 | + "IoTKit SecCtl NS block read: " | ||
369 | + "unimplemented offset 0x%x\n", offset); | ||
370 | + break; | ||
371 | + case A_PID4: | ||
372 | + case A_PID5: | ||
373 | + case A_PID6: | ||
374 | + case A_PID7: | ||
375 | + case A_PID0: | ||
376 | + case A_PID1: | ||
377 | + case A_PID2: | ||
378 | + case A_PID3: | ||
379 | + case A_CID0: | ||
380 | + case A_CID1: | ||
381 | + case A_CID2: | ||
382 | + case A_CID3: | ||
383 | + r = iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; | ||
384 | + break; | ||
385 | + default: | ||
386 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
387 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
388 | + offset); | ||
389 | + r = 0; | ||
390 | + break; | ||
391 | + } | ||
392 | + | ||
393 | + if (size != 4) { | ||
394 | + /* None of our registers are access-sensitive, so just pull the right | ||
395 | + * byte out of the word read result. | ||
396 | + */ | ||
397 | + r = extract32(r, (addr & 3) * 8, size * 8); | ||
398 | + } | ||
399 | + | ||
400 | + trace_iotkit_secctl_ns_read(offset, r, size); | ||
401 | + *pdata = r; | ||
402 | + return MEMTX_OK; | ||
403 | +} | ||
404 | + | ||
405 | +static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr, | ||
406 | + uint64_t value, | ||
407 | + unsigned size, MemTxAttrs attrs) | ||
408 | +{ | ||
409 | + uint32_t offset = addr; | ||
410 | + | ||
411 | + trace_iotkit_secctl_ns_write(offset, value, size); | ||
412 | + | ||
413 | + if (size != 4) { | ||
414 | + /* Byte and halfword writes are ignored */ | ||
415 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
416 | + "IotKit SecCtl NS block write: bad size, ignored\n"); | ||
417 | + return MEMTX_OK; | ||
418 | + } | ||
419 | + | ||
420 | + switch (offset) { | ||
421 | + case A_AHBNSPPPCEXP0: | ||
422 | + case A_AHBNSPPPCEXP1: | ||
423 | + case A_AHBNSPPPCEXP2: | ||
424 | + case A_AHBNSPPPCEXP3: | ||
425 | + case A_APBNSPPPC0: | ||
426 | + case A_APBNSPPPC1: | ||
427 | + case A_APBNSPPPCEXP0: | ||
428 | + case A_APBNSPPPCEXP1: | ||
429 | + case A_APBNSPPPCEXP2: | ||
430 | + case A_APBNSPPPCEXP3: | ||
431 | + qemu_log_mask(LOG_UNIMP, | ||
432 | + "IoTKit SecCtl NS block write: " | ||
433 | + "unimplemented offset 0x%x\n", offset); | ||
434 | + break; | ||
435 | + case A_AHBNSPPPC0: | ||
436 | + case A_PID4: | ||
437 | + case A_PID5: | ||
438 | + case A_PID6: | ||
439 | + case A_PID7: | ||
440 | + case A_PID0: | ||
441 | + case A_PID1: | ||
442 | + case A_PID2: | ||
443 | + case A_PID3: | ||
444 | + case A_CID0: | ||
445 | + case A_CID1: | ||
446 | + case A_CID2: | ||
447 | + case A_CID3: | ||
448 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
449 | + "IoTKit SecCtl NS block write: " | ||
450 | + "read-only offset 0x%x\n", offset); | ||
451 | + break; | ||
452 | + default: | ||
453 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
454 | + "IotKit SecCtl NS block write: bad offset 0x%x\n", | ||
455 | + offset); | ||
456 | + break; | ||
457 | + } | ||
458 | + | ||
459 | + return MEMTX_OK; | ||
460 | +} | ||
461 | + | ||
462 | +static const MemoryRegionOps iotkit_secctl_s_ops = { | ||
463 | + .read_with_attrs = iotkit_secctl_s_read, | ||
464 | + .write_with_attrs = iotkit_secctl_s_write, | ||
465 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
466 | + .valid.min_access_size = 1, | ||
467 | + .valid.max_access_size = 4, | ||
468 | + .impl.min_access_size = 1, | ||
469 | + .impl.max_access_size = 4, | ||
470 | +}; | ||
471 | + | ||
472 | +static const MemoryRegionOps iotkit_secctl_ns_ops = { | ||
473 | + .read_with_attrs = iotkit_secctl_ns_read, | ||
474 | + .write_with_attrs = iotkit_secctl_ns_write, | ||
475 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
476 | + .valid.min_access_size = 1, | ||
477 | + .valid.max_access_size = 4, | ||
478 | + .impl.min_access_size = 1, | ||
479 | + .impl.max_access_size = 4, | ||
480 | +}; | ||
481 | + | ||
482 | +static void iotkit_secctl_reset(DeviceState *dev) | ||
483 | +{ | ||
484 | + | ||
485 | +} | ||
486 | + | ||
487 | +static void iotkit_secctl_init(Object *obj) | ||
488 | +{ | ||
489 | + IoTKitSecCtl *s = IOTKIT_SECCTL(obj); | ||
490 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
491 | + | ||
492 | + memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
493 | + s, "iotkit-secctl-s-regs", 0x1000); | ||
494 | + memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops, | ||
495 | + s, "iotkit-secctl-ns-regs", 0x1000); | ||
496 | + sysbus_init_mmio(sbd, &s->s_regs); | ||
497 | + sysbus_init_mmio(sbd, &s->ns_regs); | ||
498 | +} | ||
499 | + | ||
500 | +static const VMStateDescription iotkit_secctl_vmstate = { | ||
501 | + .name = "iotkit-secctl", | ||
502 | + .version_id = 1, | ||
503 | + .minimum_version_id = 1, | ||
504 | + .fields = (VMStateField[]) { | ||
505 | + VMSTATE_END_OF_LIST() | ||
506 | + } | ||
507 | +}; | ||
508 | + | ||
509 | +static void iotkit_secctl_class_init(ObjectClass *klass, void *data) | ||
510 | +{ | ||
511 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
512 | + | ||
513 | + dc->vmsd = &iotkit_secctl_vmstate; | ||
514 | + dc->reset = iotkit_secctl_reset; | ||
515 | +} | ||
516 | + | ||
517 | +static const TypeInfo iotkit_secctl_info = { | ||
518 | + .name = TYPE_IOTKIT_SECCTL, | ||
519 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
520 | + .instance_size = sizeof(IoTKitSecCtl), | ||
521 | + .instance_init = iotkit_secctl_init, | ||
522 | + .class_init = iotkit_secctl_class_init, | ||
523 | +}; | ||
524 | + | ||
525 | +static void iotkit_secctl_register_types(void) | ||
526 | +{ | ||
527 | + type_register_static(&iotkit_secctl_info); | ||
528 | +} | ||
529 | + | ||
530 | +type_init(iotkit_secctl_register_types); | ||
531 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
532 | index XXXXXXX..XXXXXXX 100644 | ||
533 | --- a/default-configs/arm-softmmu.mak | ||
534 | +++ b/default-configs/arm-softmmu.mak | ||
535 | @@ -XXX,XX +XXX,XX @@ CONFIG_MPS2_FPGAIO=y | ||
536 | CONFIG_MPS2_SCC=y | ||
537 | |||
538 | CONFIG_TZ_PPC=y | ||
539 | +CONFIG_IOTKIT_SECCTL=y | ||
540 | |||
541 | CONFIG_VERSATILE_PCI=y | ||
542 | CONFIG_VERSATILE_I2C=y | ||
543 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
544 | index XXXXXXX..XXXXXXX 100644 | ||
545 | --- a/hw/misc/trace-events | ||
546 | +++ b/hw/misc/trace-events | ||
547 | @@ -XXX,XX +XXX,XX @@ tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d" | ||
548 | tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d" | ||
549 | tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked" | ||
550 | tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked" | ||
551 | + | ||
552 | +# hw/misc/iotkit-secctl.c | ||
553 | +iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
554 | +iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
555 | +iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | ||
556 | +iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | ||
557 | +iotkit_secctl_reset(void) "IoTKit SecCtl: reset" | ||
558 | -- | ||
559 | 2.16.2 | ||
560 | |||
561 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Add remaining easy registers to iotkit-secctl: | ||
2 | * NSCCFG just routes its two bits out to external GPIO lines | ||
3 | * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's | ||
4 | bus fabric can never report errors | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 20180220180325.29818-18-peter.maydell@linaro.org | ||
8 | --- | ||
9 | include/hw/misc/iotkit-secctl.h | 4 ++++ | ||
10 | hw/misc/iotkit-secctl.c | 32 ++++++++++++++++++++++++++------ | ||
11 | 2 files changed, 30 insertions(+), 6 deletions(-) | ||
12 | |||
13 | diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/misc/iotkit-secctl.h | ||
16 | +++ b/include/hw/misc/iotkit-secctl.h | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | ||
19 | * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses | ||
20 | * should RAZ/WI or bus error | ||
21 | + * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value | ||
22 | * Controlling the 2 APB PPCs in the IoTKit: | ||
23 | * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | ||
24 | * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | ||
25 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
26 | |||
27 | /*< public >*/ | ||
28 | qemu_irq sec_resp_cfg; | ||
29 | + qemu_irq nsc_cfg_irq; | ||
30 | |||
31 | MemoryRegion s_regs; | ||
32 | MemoryRegion ns_regs; | ||
33 | @@ -XXX,XX +XXX,XX @@ struct IoTKitSecCtl { | ||
34 | uint32_t secppcintstat; | ||
35 | uint32_t secppcinten; | ||
36 | uint32_t secrespcfg; | ||
37 | + uint32_t nsccfg; | ||
38 | + uint32_t brginten; | ||
39 | |||
40 | IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; | ||
41 | IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | ||
42 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/misc/iotkit-secctl.c | ||
45 | +++ b/hw/misc/iotkit-secctl.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
47 | case A_SECRESPCFG: | ||
48 | r = s->secrespcfg; | ||
49 | break; | ||
50 | + case A_NSCCFG: | ||
51 | + r = s->nsccfg; | ||
52 | + break; | ||
53 | case A_SECPPCINTSTAT: | ||
54 | r = s->secppcintstat; | ||
55 | break; | ||
56 | case A_SECPPCINTEN: | ||
57 | r = s->secppcinten; | ||
58 | break; | ||
59 | + case A_BRGINTSTAT: | ||
60 | + /* QEMU's bus fabric can never report errors as it doesn't buffer | ||
61 | + * writes, so we never report bridge interrupts. | ||
62 | + */ | ||
63 | + r = 0; | ||
64 | + break; | ||
65 | + case A_BRGINTEN: | ||
66 | + r = s->brginten; | ||
67 | + break; | ||
68 | case A_AHBNSPPCEXP0: | ||
69 | case A_AHBNSPPCEXP1: | ||
70 | case A_AHBNSPPCEXP2: | ||
71 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr, | ||
72 | case A_APBSPPPCEXP3: | ||
73 | r = s->apbexp[offset_to_ppc_idx(offset)].sp; | ||
74 | break; | ||
75 | - case A_NSCCFG: | ||
76 | case A_SECMPCINTSTATUS: | ||
77 | case A_SECMSCINTSTAT: | ||
78 | case A_SECMSCINTEN: | ||
79 | - case A_BRGINTSTAT: | ||
80 | - case A_BRGINTEN: | ||
81 | case A_NSMSCEXP: | ||
82 | qemu_log_mask(LOG_UNIMP, | ||
83 | "IoTKit SecCtl S block read: " | ||
84 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
85 | } | ||
86 | |||
87 | switch (offset) { | ||
88 | + case A_NSCCFG: | ||
89 | + s->nsccfg = value & 3; | ||
90 | + qemu_set_irq(s->nsc_cfg_irq, s->nsccfg); | ||
91 | + break; | ||
92 | case A_SECRESPCFG: | ||
93 | value &= 1; | ||
94 | s->secrespcfg = value; | ||
95 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
96 | s->secppcinten = value & 0x00f000f3; | ||
97 | foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable); | ||
98 | break; | ||
99 | + case A_BRGINTCLR: | ||
100 | + break; | ||
101 | + case A_BRGINTEN: | ||
102 | + s->brginten = value & 0xffff0000; | ||
103 | + break; | ||
104 | case A_AHBNSPPCEXP0: | ||
105 | case A_AHBNSPPCEXP1: | ||
106 | case A_AHBNSPPCEXP2: | ||
107 | @@ -XXX,XX +XXX,XX @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr, | ||
108 | ppc = &s->apbexp[offset_to_ppc_idx(offset)]; | ||
109 | iotkit_secctl_ppc_sp_write(ppc, value); | ||
110 | break; | ||
111 | - case A_NSCCFG: | ||
112 | case A_SECMSCINTCLR: | ||
113 | case A_SECMSCINTEN: | ||
114 | - case A_BRGINTCLR: | ||
115 | - case A_BRGINTEN: | ||
116 | qemu_log_mask(LOG_UNIMP, | ||
117 | "IoTKit SecCtl S block write: " | ||
118 | "unimplemented offset 0x%x\n", offset); | ||
119 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_reset(DeviceState *dev) | ||
120 | s->secppcintstat = 0; | ||
121 | s->secppcinten = 0; | ||
122 | s->secrespcfg = 0; | ||
123 | + s->nsccfg = 0; | ||
124 | + s->brginten = 0; | ||
125 | |||
126 | foreach_ppc(s, iotkit_secctl_reset_ppc); | ||
127 | } | ||
128 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_init(Object *obj) | ||
129 | } | ||
130 | |||
131 | qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | ||
132 | + qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); | ||
133 | |||
134 | memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops, | ||
135 | s, "iotkit-secctl-s-regs", 0x1000); | ||
136 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_secctl_vmstate = { | ||
137 | VMSTATE_UINT32(secppcintstat, IoTKitSecCtl), | ||
138 | VMSTATE_UINT32(secppcinten, IoTKitSecCtl), | ||
139 | VMSTATE_UINT32(secrespcfg, IoTKitSecCtl), | ||
140 | + VMSTATE_UINT32(nsccfg, IoTKitSecCtl), | ||
141 | + VMSTATE_UINT32(brginten, IoTKitSecCtl), | ||
142 | VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1, | ||
143 | iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC), | ||
144 | VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1, | ||
145 | -- | ||
146 | 2.16.2 | ||
147 | |||
148 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180228193125.20577-9-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- | ||
9 | 1 file changed, 42 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static const char *regnames[] = | ||
16 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | ||
17 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | ||
18 | |||
19 | +/* Function prototypes for gen_ functions calling Neon helpers. */ | ||
20 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | ||
21 | + TCGv_i32, TCGv_i32); | ||
22 | + | ||
23 | /* initialize TCG globals. */ | ||
24 | void arm_translate_init(void) | ||
25 | { | ||
26 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
27 | } | ||
28 | neon_store_reg64(cpu_V0, rd + pass); | ||
29 | } | ||
30 | - | ||
31 | - | ||
32 | break; | ||
33 | - default: /* 14 and 15 are RESERVED */ | ||
34 | - return 1; | ||
35 | + case 14: /* VQRDMLAH scalar */ | ||
36 | + case 15: /* VQRDMLSH scalar */ | ||
37 | + { | ||
38 | + NeonGenThreeOpEnvFn *fn; | ||
39 | + | ||
40 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { | ||
41 | + return 1; | ||
42 | + } | ||
43 | + if (u && ((rd | rn) & 1)) { | ||
44 | + return 1; | ||
45 | + } | ||
46 | + if (op == 14) { | ||
47 | + if (size == 1) { | ||
48 | + fn = gen_helper_neon_qrdmlah_s16; | ||
49 | + } else { | ||
50 | + fn = gen_helper_neon_qrdmlah_s32; | ||
51 | + } | ||
52 | + } else { | ||
53 | + if (size == 1) { | ||
54 | + fn = gen_helper_neon_qrdmlsh_s16; | ||
55 | + } else { | ||
56 | + fn = gen_helper_neon_qrdmlsh_s32; | ||
57 | + } | ||
58 | + } | ||
59 | + | ||
60 | + tmp2 = neon_get_scalar(size, rm); | ||
61 | + for (pass = 0; pass < (u ? 4 : 2); pass++) { | ||
62 | + tmp = neon_load_reg(rn, pass); | ||
63 | + tmp3 = neon_load_reg(rd, pass); | ||
64 | + fn(tmp, cpu_env, tmp, tmp2, tmp3); | ||
65 | + tcg_temp_free_i32(tmp3); | ||
66 | + neon_store_reg(rd, pass, tmp); | ||
67 | + } | ||
68 | + tcg_temp_free_i32(tmp2); | ||
69 | + } | ||
70 | + break; | ||
71 | + default: | ||
72 | + g_assert_not_reached(); | ||
73 | } | ||
74 | } | ||
75 | } else { /* size == 3 */ | ||
76 | -- | ||
77 | 2.16.2 | ||
78 | |||
79 | diff view generated by jsdifflib |