1
Arm queue -- I have more stuff pending but I prefer to push
1
Hi; here's the first target-arm pullreq for the 7.0 cycle.
2
this first lot out and keep the pull below 50 patches.
3
Most of this is Alex's FP16 support work.
4
2
3
thanks
5
-- PMM
4
-- PMM
6
5
6
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
7
7
8
The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:
8
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800)
9
10
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215
15
13
16
for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:
14
for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359:
17
15
18
MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)
16
tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* update MAINTAINERS for Alistair's new email address
20
* ITS: error reporting cleanup
23
* add Arm v8.2 FP16 arithmetic extension for linux-user
21
* aspeed: improve documentation
24
* implement display connector emulation for vexpress board
22
* Fix STM32F2XX USART data register readout
25
* xilinx_spips: Enable only two slaves when reading/writing with stripe
23
* allow emulated GICv3 to be disabled in non-TCG builds
26
* xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
24
* fix exception priority for singlestep, misaligned PC, bp, etc
27
* hw: register: Run post_write hook on reset
25
* Correct calculation of tlb range invalidate length
26
* npcm7xx_emc: fix missing queue_flush
27
* virt: Add VIOT ACPI table for virtio-iommu
28
* target/i386: Use assert() to sanity-check b1 in SSE decode
29
* Don't include qemu-common unnecessarily
28
30
29
----------------------------------------------------------------
31
----------------------------------------------------------------
30
Alex Bennée (31):
32
Alex Bennée (1):
31
include/exec/helper-head.h: support f16 in helper calls
33
hw/intc: clean-up error reporting for failed ITS cmd
32
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
33
target/arm/cpu.h: update comment for half-precision values
34
target/arm/cpu.h: add additional float_status flags
35
target/arm/helper: pass explicit fpst to set_rmode
36
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
37
arm/translate-a64: handle_3same_64 comment fix
38
arm/translate-a64: initial decode for simd_three_reg_same_fp16
39
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
40
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
41
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
42
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
43
arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
44
arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
45
arm/translate-a64: add FP16 x2 ops for simd_indexed
46
arm/translate-a64: initial decode for simd_two_reg_misc_fp16
47
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
48
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
49
arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
50
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
51
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
52
arm/helper.c: re-factor recpe and add recepe_f16
53
arm/translate-a64: add FP16 FRECPE
54
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
55
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
56
arm/helper.c: re-factor rsqrte and add rsqrte_f16
57
arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
58
arm/translate-a64: add FP16 FMOV to simd_mod_imm
59
arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
60
arm/translate-a64: implement simd_scalar_three_reg_same_fp16
61
arm/translate-a64: add all single op FP16 to handle_fp_1src_half
62
34
63
Alistair Francis (2):
35
Jean-Philippe Brucker (8):
64
hw: register: Run post_write hook on reset
36
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
65
MAINTAINERS: Update my email address
37
hw/arm/virt: Remove device tree restriction for virtio-iommu
38
hw/arm/virt: Reject instantiation of multiple IOMMUs
39
hw/arm/virt: Use object_property_set instead of qdev_prop_set
40
tests/acpi: allow updates of VIOT expected data files
41
tests/acpi: add test case for VIOT
42
tests/acpi: add expected blobs for VIOT test on q35 machine
43
tests/acpi: add expected blob for VIOT test on virt machine
66
44
67
Corey Minyard (2):
45
Joel Stanley (4):
68
i2c: Fix some brace style issues
46
docs: aspeed: Add new boards
69
i2c: Move the bus class to i2c.h
47
docs: aspeed: Update OpenBMC image URL
48
docs: aspeed: Give an example of booting a kernel
49
docs: aspeed: ADC is now modelled
70
50
71
Francisco Iglesias (2):
51
Olivier Hériveaux (1):
72
xilinx_spips: Enable only two slaves when reading/writing with stripe
52
Fix STM32F2XX USART data register readout
73
xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
74
53
75
Linus Walleij (3):
54
Patrick Venture (1):
76
hw/i2c-ddc: Do not fail writes
55
hw/net: npcm7xx_emc fix missing queue_flush
77
hw/sii9022: Add support for Silicon Image SII9022
78
arm/vexpress: Add proper display connector emulation
79
56
80
Peter Maydell (2):
57
Peter Maydell (6):
81
target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
58
target/i386: Use assert() to sanity-check b1 in SSE decode
82
linux-user: Report AArch64 FP16 support via hwcap bits
59
include/hw/i386: Don't include qemu-common.h in .h files
60
target/hexagon/cpu.h: don't include qemu-common.h
61
target/rx/cpu.h: Don't include qemu-common.h
62
hw/arm: Don't include qemu-common.h unnecessarily
63
target/arm: Correct calculation of tlb range invalidate length
83
64
84
hw/display/Makefile.objs | 1 +
65
Philippe Mathieu-Daudé (2):
85
include/exec/helper-head.h | 3 +
66
hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
86
include/fpu/softfloat.h | 18 +-
67
hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector
87
include/hw/i2c/i2c.h | 23 +-
88
include/hw/register.h | 6 +-
89
target/arm/cpu.h | 34 +-
90
target/arm/helper-a64.h | 33 +
91
target/arm/helper.h | 14 +-
92
hw/arm/vexpress.c | 6 +-
93
hw/core/register.c | 8 +
94
hw/display/sii9022.c | 191 ++++++
95
hw/i2c/core.c | 18 -
96
hw/i2c/i2c-ddc.c | 4 +-
97
hw/ssi/xilinx_spips.c | 43 +-
98
linux-user/elfload.c | 2 +
99
target/arm/cpu64.c | 1 +
100
target/arm/helper-a64.c | 269 +++++++++
101
target/arm/helper.c | 481 ++++++++-------
102
target/arm/translate-a64.c | 1266 +++++++++++++++++++++++++++++++++------
103
target/arm/translate.c | 12 +-
104
MAINTAINERS | 12 +-
105
default-configs/arm-softmmu.mak | 2 +
106
hw/display/trace-events | 5 +
107
23 files changed, 1981 insertions(+), 471 deletions(-)
108
create mode 100644 hw/display/sii9022.c
109
68
69
Richard Henderson (10):
70
target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
71
target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
72
target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
73
target/arm: Split arm_pre_translate_insn
74
target/arm: Advance pc for arch single-step exception
75
target/arm: Split compute_fsr_fsc out of arm_deliver_fault
76
target/arm: Take an exception if PC is misaligned
77
target/arm: Assert thumb pc is aligned
78
target/arm: Suppress bp for exceptions with more priority
79
tests/tcg: Add arm and aarch64 pc alignment tests
80
81
docs/system/arm/aspeed.rst | 26 ++++++++++++----
82
include/hw/i386/microvm.h | 1 -
83
include/hw/i386/x86.h | 1 -
84
target/arm/helper.h | 1 +
85
target/arm/syndrome.h | 5 +++
86
target/hexagon/cpu.h | 1 -
87
target/rx/cpu.h | 1 -
88
hw/arm/boot.c | 1 -
89
hw/arm/digic_boards.c | 1 -
90
hw/arm/highbank.c | 1 -
91
hw/arm/npcm7xx_boards.c | 1 -
92
hw/arm/sbsa-ref.c | 1 -
93
hw/arm/stm32f405_soc.c | 1 -
94
hw/arm/vexpress.c | 1 -
95
hw/arm/virt-acpi-build.c | 7 +++++
96
hw/arm/virt.c | 21 ++++++-------
97
hw/char/stm32f2xx_usart.c | 3 +-
98
hw/intc/arm_gicv3.c | 2 +-
99
hw/intc/arm_gicv3_cpuif.c | 10 +-----
100
hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++
101
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++--------
102
hw/net/npcm7xx_emc.c | 18 +++++------
103
hw/virtio/virtio-iommu-pci.c | 12 ++------
104
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------
105
linux-user/hexagon/cpu_loop.c | 1 +
106
target/arm/debug_helper.c | 23 ++++++++++++++
107
target/arm/gdbstub.c | 9 ++++--
108
target/arm/helper.c | 6 ++--
109
target/arm/machine.c | 10 ++++++
110
target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++----------
111
target/arm/translate-a64.c | 23 ++++++++++++--
112
target/arm/translate.c | 58 ++++++++++++++++++++++++++---------
113
target/i386/tcg/translate.c | 12 ++------
114
tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++
115
tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++
116
tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++
117
hw/arm/Kconfig | 1 +
118
hw/intc/Kconfig | 5 +++
119
hw/intc/meson.build | 11 ++++---
120
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
121
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
122
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
123
tests/tcg/aarch64/Makefile.target | 4 +--
124
tests/tcg/arm/Makefile.target | 4 +++
125
44 files changed, 429 insertions(+), 145 deletions(-)
126
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
127
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
128
create mode 100644 tests/tcg/arm/pcalign-a32.c
129
create mode 100644 tests/data/acpi/q35/DSDT.viot
130
create mode 100644 tests/data/acpi/q35/VIOT.viot
131
create mode 100644 tests/data/acpi/virt/VIOT
132
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Only one half-precision instruction has been added to this group.
3
While trying to debug a GIC ITS failure I saw some guest errors that
4
had poor formatting as well as leaving me confused as to what failed.
5
As most of the checks aren't possible without a valid dte split that
6
check apart and then check the other conditions in steps. This avoids
7
us relying on undefined data.
8
9
I still get a failure with the current kvm-unit-tests but at least I
10
know (partially) why now:
11
12
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
13
PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI
14
ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0
15
INT dev_id=2 event_id=20
16
process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0)
17
PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap
18
SUMMARY: 6 tests, 1 unexpected failures
4
19
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
20
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20180227143852.11175-29-alex.bennee@linaro.org
22
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
23
Cc: Shashi Mallela <shashi.mallela@linaro.org>
24
Cc: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
26
---
10
target/arm/translate-a64.c | 35 +++++++++++++++++++++++++----------
27
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------
11
1 file changed, 25 insertions(+), 10 deletions(-)
28
1 file changed, 27 insertions(+), 12 deletions(-)
12
29
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
14
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
32
--- a/hw/intc/arm_gicv3_its.c
16
+++ b/target/arm/translate-a64.c
33
+++ b/hw/intc/arm_gicv3_its.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
34
@@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset,
18
* MVNI - move inverted (shifted) imm into register
35
if (res != MEMTX_OK) {
19
* ORR - bitwise OR of (shifted) imm with register
36
return result;
20
* BIC - bitwise clear of (shifted) imm with register
37
}
21
+ * With ARMv8.2 we also have:
38
+ } else {
22
+ * FMOV half-precision
39
+ qemu_log_mask(LOG_GUEST_ERROR,
23
*/
40
+ "%s: invalid command attributes: "
24
static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
41
+ "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n",
25
{
42
+ __func__, dte, devid, res);
26
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
43
+ return result;
27
uint64_t imm = 0;
28
29
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
30
- unallocated_encoding(s);
31
- return;
32
+ /* Check for FMOV (vector, immediate) - half-precision */
33
+ if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
34
+ unallocated_encoding(s);
35
+ return;
36
+ }
37
}
44
}
38
45
39
if (!fp_access_check(s)) {
46
- if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
40
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
47
- !cte_valid || (eventid > max_eventid)) {
41
imm |= 0x4000000000000000ULL;
48
+
42
}
49
+ /*
43
} else {
50
+ * In this implementation, in case of guest errors we ignore the
44
- imm = (abcdefgh & 0x3f) << 19;
51
+ * command and move onto the next command in the queue.
45
- if (abcdefgh & 0x80) {
52
+ */
46
- imm |= 0x80000000;
53
+ if (devid > s->dt.maxids.max_devids) {
47
- }
54
qemu_log_mask(LOG_GUEST_ERROR,
48
- if (abcdefgh & 0x40) {
55
- "%s: invalid command attributes "
49
- imm |= 0x3e000000;
56
- "devid %d or eventid %d or invalid dte %d or"
50
+ if (o2) {
57
- "invalid cte %d or invalid ite %d\n",
51
+ /* FMOV (vector, immediate) - half-precision */
58
- __func__, devid, eventid, dte_valid, cte_valid,
52
+ imm = vfp_expand_imm(MO_16, abcdefgh);
59
- ite_valid);
53
+ /* now duplicate across the lanes */
60
- /*
54
+ imm = bitfield_replicate(imm, 16);
61
- * in this implementation, in case of error
55
} else {
62
- * we ignore this command and move onto the next
56
- imm |= 0x40000000;
63
- * command in the queue
57
+ imm = (abcdefgh & 0x3f) << 19;
64
- */
58
+ if (abcdefgh & 0x80) {
65
+ "%s: invalid command attributes: devid %d>%d",
59
+ imm |= 0x80000000;
66
+ __func__, devid, s->dt.maxids.max_devids);
60
+ }
67
+
61
+ if (abcdefgh & 0x40) {
68
+ } else if (!dte_valid || !ite_valid || !cte_valid) {
62
+ imm |= 0x3e000000;
69
+ qemu_log_mask(LOG_GUEST_ERROR,
63
+ } else {
70
+ "%s: invalid command attributes: "
64
+ imm |= 0x40000000;
71
+ "dte: %s, ite: %s, cte: %s\n",
65
+ }
72
+ __func__,
66
+ imm |= (imm << 32);
73
+ dte_valid ? "valid" : "invalid",
67
}
74
+ ite_valid ? "valid" : "invalid",
68
- imm |= (imm << 32);
75
+ cte_valid ? "valid" : "invalid");
69
}
76
+ } else if (eventid > max_eventid) {
70
}
77
+ qemu_log_mask(LOG_GUEST_ERROR,
71
break;
78
+ "%s: invalid command attributes: eventid %d > %d\n",
72
+ default:
79
+ __func__, eventid, max_eventid);
73
+ fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
80
} else {
74
+ g_assert_not_reached();
81
/*
75
}
82
* Current implementation only supports rdbase == procnum
76
77
if (cmode_3_1 != 7 && is_neg) {
78
--
83
--
79
2.16.2
84
2.25.1
80
85
81
86
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
I am leaving Xilinx, so to avoid having an email address that bounces
3
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
4
update my maintainer address to point to my personal email address.
4
removed in v7.0.
5
5
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Signed-off-by: Alistair Francis <alistair@alistair23.me>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20211117065752.330632-2-joel@jms.id.au
9
Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
MAINTAINERS | 12 ++++++------
11
docs/system/arm/aspeed.rst | 7 ++++++-
13
1 file changed, 6 insertions(+), 6 deletions(-)
12
1 file changed, 6 insertions(+), 1 deletion(-)
14
13
15
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/MAINTAINERS
16
--- a/docs/system/arm/aspeed.rst
18
+++ b/MAINTAINERS
17
+++ b/docs/system/arm/aspeed.rst
19
@@ -XXX,XX +XXX,XX @@ F: hw/misc/arm_sysctl.c
18
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
20
19
21
Xilinx Zynq
20
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
22
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
21
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
23
-M: Alistair Francis <alistair.francis@xilinx.com>
22
+- ``supermicrox11-bmc`` Supermicro X11 BMC
24
+M: Alistair Francis <alistair@alistair23.me>
23
25
L: qemu-arm@nongnu.org
24
AST2500 SoC based machines :
26
S: Maintained
25
27
F: hw/*/xilinx_*
26
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
28
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/zynq*
27
- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
29
X: hw/ssi/xilinx_*
28
- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
30
29
- ``sonorapass-bmc`` OCP SonoraPass BMC
31
Xilinx ZynqMP
30
-- ``swift-bmc`` OpenPOWER Swift BMC POWER9
32
-M: Alistair Francis <alistair.francis@xilinx.com>
31
+- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
33
+M: Alistair Francis <alistair@alistair23.me>
32
+- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
34
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
33
+- ``g220a-bmc`` Bytedance G220A BMC
35
L: qemu-arm@nongnu.org
34
36
S: Maintained
35
AST2600 SoC based machines :
37
@@ -XXX,XX +XXX,XX @@ T: git git://github.com/bonzini/qemu.git scsi-next
36
38
37
- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7)
39
SSI
38
- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
40
M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
39
+- ``rainier-bmc`` IBM Rainier POWER10 BMC
41
-M: Alistair Francis <alistair.francis@xilinx.com>
40
+- ``fuji-bmc`` Facebook Fuji BMC
42
+M: Alistair Francis <alistair@alistair23.me>
41
43
S: Maintained
42
Supported devices
44
F: hw/ssi/*
43
-----------------
45
F: hw/block/m25p80.c
46
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
47
F: tests/m25p80-test.c
48
49
Xilinx SPI
50
-M: Alistair Francis <alistair.francis@xilinx.com>
51
+M: Alistair Francis <alistair@alistair23.me>
52
M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
53
S: Maintained
54
F: hw/ssi/xilinx_*
55
@@ -XXX,XX +XXX,XX @@ S: Maintained
56
F: hw/net/eepro100.c
57
58
Generic Loader
59
-M: Alistair Francis <alistair.francis@xilinx.com>
60
+M: Alistair Francis <alistair@alistair23.me>
61
S: Maintained
62
F: hw/core/generic-loader.c
63
F: include/hw/core/generic-loader.h
64
@@ -XXX,XX +XXX,XX @@ F: tests/qmp-test.c
65
T: git git://repo.or.cz/qemu/armbru.git qapi-next
66
67
Register API
68
-M: Alistair Francis <alistair.francis@xilinx.com>
69
+M: Alistair Francis <alistair@alistair23.me>
70
S: Maintained
71
F: hw/core/register.c
72
F: include/hw/register.h
73
--
44
--
74
2.16.2
45
2.25.1
75
46
76
47
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
This covers the encoding group:
3
This is the latest URL for the OpenBMC CI. The old URL still works, but
4
redirects.
4
5
5
Advanced SIMD scalar three same FP16
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
6
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
As all the helpers are already there it is simply a case of calling the
8
Message-id: 20211117065752.330632-3-joel@jms.id.au
8
existing helpers in the scalar context.
9
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20180227143852.11175-31-alex.bennee@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
11
docs/system/arm/aspeed.rst | 2 +-
16
1 file changed, 99 insertions(+)
12
1 file changed, 1 insertion(+), 1 deletion(-)
17
13
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
16
--- a/docs/system/arm/aspeed.rst
21
+++ b/target/arm/translate-a64.c
17
+++ b/docs/system/arm/aspeed.rst
22
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
18
@@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to
23
tcg_temp_free_i64(tcg_rd);
19
load a Linux kernel or from a firmware. Images can be downloaded from
24
}
20
the OpenBMC jenkins :
25
21
26
+/* AdvSIMD scalar three same FP16
22
- https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder
27
+ * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
23
+ https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
28
+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
24
29
+ * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
25
or directly from the OpenBMC GitHub release repository :
30
+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
31
+ * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
32
+ * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
33
+ */
34
+static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
35
+ uint32_t insn)
36
+{
37
+ int rd = extract32(insn, 0, 5);
38
+ int rn = extract32(insn, 5, 5);
39
+ int opcode = extract32(insn, 11, 3);
40
+ int rm = extract32(insn, 16, 5);
41
+ bool u = extract32(insn, 29, 1);
42
+ bool a = extract32(insn, 23, 1);
43
+ int fpopcode = opcode | (a << 3) | (u << 4);
44
+ TCGv_ptr fpst;
45
+ TCGv_i32 tcg_op1;
46
+ TCGv_i32 tcg_op2;
47
+ TCGv_i32 tcg_res;
48
+
49
+ switch (fpopcode) {
50
+ case 0x03: /* FMULX */
51
+ case 0x04: /* FCMEQ (reg) */
52
+ case 0x07: /* FRECPS */
53
+ case 0x0f: /* FRSQRTS */
54
+ case 0x14: /* FCMGE (reg) */
55
+ case 0x15: /* FACGE */
56
+ case 0x1a: /* FABD */
57
+ case 0x1c: /* FCMGT (reg) */
58
+ case 0x1d: /* FACGT */
59
+ break;
60
+ default:
61
+ unallocated_encoding(s);
62
+ return;
63
+ }
64
+
65
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
66
+ unallocated_encoding(s);
67
+ }
68
+
69
+ if (!fp_access_check(s)) {
70
+ return;
71
+ }
72
+
73
+ fpst = get_fpstatus_ptr(true);
74
+
75
+ tcg_op1 = tcg_temp_new_i32();
76
+ tcg_op2 = tcg_temp_new_i32();
77
+ tcg_res = tcg_temp_new_i32();
78
+
79
+ read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
80
+ read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
81
+
82
+ switch (fpopcode) {
83
+ case 0x03: /* FMULX */
84
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
85
+ break;
86
+ case 0x04: /* FCMEQ (reg) */
87
+ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
88
+ break;
89
+ case 0x07: /* FRECPS */
90
+ gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
91
+ break;
92
+ case 0x0f: /* FRSQRTS */
93
+ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
94
+ break;
95
+ case 0x14: /* FCMGE (reg) */
96
+ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
97
+ break;
98
+ case 0x15: /* FACGE */
99
+ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
100
+ break;
101
+ case 0x1a: /* FABD */
102
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
103
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
104
+ break;
105
+ case 0x1c: /* FCMGT (reg) */
106
+ gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
107
+ break;
108
+ case 0x1d: /* FACGT */
109
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
110
+ break;
111
+ default:
112
+ g_assert_not_reached();
113
+ }
114
+
115
+ write_fp_sreg(s, rd, tcg_res);
116
+
117
+
118
+ tcg_temp_free_i32(tcg_res);
119
+ tcg_temp_free_i32(tcg_op1);
120
+ tcg_temp_free_i32(tcg_op2);
121
+ tcg_temp_free_ptr(fpst);
122
+}
123
+
124
static void handle_2misc_64(DisasContext *s, int opcode, bool u,
125
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
126
TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
127
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
128
{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
129
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
130
{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
131
+ { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
132
{ 0x00000000, 0x00000000, NULL }
133
};
134
26
135
--
27
--
136
2.16.2
28
2.25.1
137
29
138
30
diff view generated by jsdifflib
1
Now we have implemented FP16 we can enable it for the "any" CPU.
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
3
A common use case for the ASPEED machine is to boot a Linux kernel.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Provide a full example command line.
5
[PMM: split out from an earlier patch in the series]
5
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20211117065752.330632-4-joel@jms.id.au
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/cpu64.c | 1 +
11
docs/system/arm/aspeed.rst | 15 ++++++++++++---
9
1 file changed, 1 insertion(+)
12
1 file changed, 12 insertions(+), 3 deletions(-)
10
13
11
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu64.c
16
--- a/docs/system/arm/aspeed.rst
14
+++ b/target/arm/cpu64.c
17
+++ b/docs/system/arm/aspeed.rst
15
@@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ Missing devices
16
set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
19
Boot options
17
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
20
------------
18
set_feature(&cpu->env, ARM_FEATURE_CRC);
21
19
+ set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
22
-The Aspeed machines can be started using the ``-kernel`` option to
20
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
23
-load a Linux kernel or from a firmware. Images can be downloaded from
21
cpu->dcz_blocksize = 7; /* 512 bytes */
24
-the OpenBMC jenkins :
22
}
25
+The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options
26
+to load a Linux kernel or from a firmware. Images can be downloaded from the
27
+OpenBMC jenkins :
28
29
https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
30
31
@@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository :
32
33
https://github.com/openbmc/openbmc/releases
34
35
+To boot a kernel directly from a Linux build tree:
36
+
37
+.. code-block:: bash
38
+
39
+ $ qemu-system-arm -M ast2600-evb -nographic \
40
+ -kernel arch/arm/boot/zImage \
41
+ -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
42
+ -initrd rootfs.cpio
43
+
44
The image should be attached as an MTD drive. Run :
45
46
.. code-block:: bash
23
--
47
--
24
2.16.2
48
2.25.1
25
49
26
50
diff view generated by jsdifflib
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
3
Move it to the supported list.
4
for matching what is expected by Micron (Numonyx) flashes (the default target
5
flash type of the QSPI).
6
4
7
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
6
Message-id: 20211117065752.330632-5-joel@jms.id.au
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Message-id: 20180223232233.31482-3-frasse.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
8
---
13
hw/ssi/xilinx_spips.c | 2 +-
9
docs/system/arm/aspeed.rst | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
10
1 file changed, 1 insertion(+), 1 deletion(-)
15
11
16
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
12
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/xilinx_spips.c
14
--- a/docs/system/arm/aspeed.rst
19
+++ b/hw/ssi/xilinx_spips.c
15
+++ b/docs/system/arm/aspeed.rst
20
@@ -XXX,XX +XXX,XX @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
16
@@ -XXX,XX +XXX,XX @@ Supported devices
21
return 2;
17
* Front LEDs (PCA9552 on I2C bus)
22
case QIOR:
18
* LPC Peripheral Controller (a subset of subdevices are supported)
23
case QIOR_4:
19
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
24
- return 5;
20
+ * ADC
25
+ return 4;
21
26
default:
22
27
return -1;
23
Missing devices
28
}
24
---------------
25
26
* Coprocessor support
27
- * ADC (out of tree implementation)
28
* PWM and Fan Controller
29
* Slave GPIO Controller
30
* Super I/O Controller
29
--
31
--
30
2.16.2
32
2.25.1
31
33
32
34
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
2
2
3
This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use
3
Fix issue where the data register may be overwritten by next character
4
existing helpers to achieve this.
4
reception before being read and returned.
5
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180227143852.11175-32-alex.bennee@linaro.org
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
12
hw/char/stm32f2xx_usart.c | 3 ++-
12
1 file changed, 71 insertions(+)
13
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
--- a/hw/char/stm32f2xx_usart.c
17
+++ b/target/arm/translate-a64.c
18
+++ b/hw/char/stm32f2xx_usart.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
19
tcg_temp_free_i64(t_true);
20
return retvalue;
20
}
21
case USART_DR:
21
22
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
22
+/* Floating-point data-processing (1 source) - half precision */
23
+ retvalue = s->usart_dr & 0x3FF;
23
+static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
24
s->usart_sr &= ~USART_SR_RXNE;
24
+{
25
qemu_chr_fe_accept_input(&s->chr);
25
+ TCGv_ptr fpst = NULL;
26
qemu_set_irq(s->irq, 0);
26
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
27
- return s->usart_dr & 0x3FF;
27
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
28
+ return retvalue;
28
+
29
case USART_BRR:
29
+ read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
30
return s->usart_brr;
30
+
31
case USART_CR1:
31
+ switch (opcode) {
32
+ case 0x0: /* FMOV */
33
+ tcg_gen_mov_i32(tcg_res, tcg_op);
34
+ break;
35
+ case 0x1: /* FABS */
36
+ tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
37
+ break;
38
+ case 0x2: /* FNEG */
39
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
40
+ break;
41
+ case 0x3: /* FSQRT */
42
+ gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
43
+ break;
44
+ case 0x8: /* FRINTN */
45
+ case 0x9: /* FRINTP */
46
+ case 0xa: /* FRINTM */
47
+ case 0xb: /* FRINTZ */
48
+ case 0xc: /* FRINTA */
49
+ {
50
+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
51
+ fpst = get_fpstatus_ptr(true);
52
+
53
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
54
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
55
+
56
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
57
+ tcg_temp_free_i32(tcg_rmode);
58
+ break;
59
+ }
60
+ case 0xe: /* FRINTX */
61
+ fpst = get_fpstatus_ptr(true);
62
+ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
63
+ break;
64
+ case 0xf: /* FRINTI */
65
+ fpst = get_fpstatus_ptr(true);
66
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
67
+ break;
68
+ default:
69
+ abort();
70
+ }
71
+
72
+ write_fp_sreg(s, rd, tcg_res);
73
+
74
+ if (fpst) {
75
+ tcg_temp_free_ptr(fpst);
76
+ }
77
+ tcg_temp_free_i32(tcg_op);
78
+ tcg_temp_free_i32(tcg_res);
79
+}
80
+
81
/* Floating-point data-processing (1 source) - single precision */
82
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
83
{
84
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
85
86
handle_fp_1src_double(s, opcode, rd, rn);
87
break;
88
+ case 3:
89
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
90
+ unallocated_encoding(s);
91
+ return;
92
+ }
93
+
94
+ if (!fp_access_check(s)) {
95
+ return;
96
+ }
97
+
98
+ handle_fp_1src_half(s, opcode, rd, rn);
99
+ break;
100
default:
101
unallocated_encoding(s);
102
}
103
--
32
--
104
2.16.2
33
2.25.1
105
34
106
35
diff view generated by jsdifflib
1
From: Linus Walleij <linus.walleij@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
This adds support for emulating the Silicon Image SII9022 DVI/HDMI
3
gicv3_set_gicv3state() is used by arm_gicv3_common.c in
4
bridge. It's not very clever right now, it just acknowledges
4
arm_gicv3_common_realize(). Since we want to restrict
5
the switch into DDC I2C mode and back. Combining this with the
5
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
6
existing DDC I2C emulation gives the right behavior on the Versatile
6
to a new file. Add this file to the meson 'specific'
7
Express emulation passing through the QEMU EDID to the emulated
7
source set, since it needs access to "cpu.h".
8
platform.
9
8
10
Cc: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
12
Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
11
Message-id: 20211115223619.2599282-2-philmd@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
hw/display/Makefile.objs | 1 +
14
hw/intc/arm_gicv3_cpuif.c | 10 +---------
18
hw/display/sii9022.c | 191 +++++++++++++++++++++++++++++++++++++++++++++++
15
hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++
19
hw/display/trace-events | 5 ++
16
hw/intc/meson.build | 1 +
20
3 files changed, 197 insertions(+)
17
3 files changed, 24 insertions(+), 9 deletions(-)
21
create mode 100644 hw/display/sii9022.c
18
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
22
19
23
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
20
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
24
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/display/Makefile.objs
22
--- a/hw/intc/arm_gicv3_cpuif.c
26
+++ b/hw/display/Makefile.objs
23
+++ b/hw/intc/arm_gicv3_cpuif.c
27
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
24
@@ -XXX,XX +XXX,XX @@
28
common-obj-$(CONFIG_G364FB) += g364fb.o
25
/*
29
common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
26
- * ARM Generic Interrupt Controller v3
30
common-obj-$(CONFIG_PL110) += pl110.o
27
+ * ARM Generic Interrupt Controller v3 (emulation)
31
+common-obj-$(CONFIG_SII9022) += sii9022.o
28
*
32
common-obj-$(CONFIG_SSD0303) += ssd0303.o
29
* Copyright (c) 2016 Linaro Limited
33
common-obj-$(CONFIG_SSD0323) += ssd0323.o
30
* Written by Peter Maydell
34
common-obj-$(CONFIG_XEN) += xenfb.o
31
@@ -XXX,XX +XXX,XX @@
35
diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
32
#include "hw/irq.h"
33
#include "cpu.h"
34
35
-void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
36
-{
37
- ARMCPU *arm_cpu = ARM_CPU(cpu);
38
- CPUARMState *env = &arm_cpu->env;
39
-
40
- env->gicv3state = (void *)s;
41
-};
42
-
43
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
44
{
45
return env->gicv3state;
46
diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c
36
new file mode 100644
47
new file mode 100644
37
index XXXXXXX..XXXXXXX
48
index XXXXXXX..XXXXXXX
38
--- /dev/null
49
--- /dev/null
39
+++ b/hw/display/sii9022.c
50
+++ b/hw/intc/arm_gicv3_cpuif_common.c
40
@@ -XXX,XX +XXX,XX @@
51
@@ -XXX,XX +XXX,XX @@
52
+/* SPDX-License-Identifier: GPL-2.0-or-later */
41
+/*
53
+/*
42
+ * Silicon Image SiI9022
54
+ * ARM Generic Interrupt Controller v3
43
+ *
55
+ *
44
+ * This is a pretty hollow emulation: all we do is acknowledge that we
56
+ * Copyright (c) 2016 Linaro Limited
45
+ * exist (chip ID) and confirm that we get switched over into DDC mode
57
+ * Written by Peter Maydell
46
+ * so the emulated host can proceed to read out EDID data. All subsequent
47
+ * set-up of connectors etc will be acknowledged and ignored.
48
+ *
58
+ *
49
+ * Copyright (C) 2018 Linus Walleij
59
+ * This code is licensed under the GPL, version 2 or (at your option)
50
+ *
60
+ * any later version.
51
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
52
+ * See the COPYING file in the top-level directory.
53
+ * SPDX-License-Identifier: GPL-2.0-or-later
54
+ */
61
+ */
55
+
62
+
56
+#include "qemu/osdep.h"
63
+#include "qemu/osdep.h"
57
+#include "qemu-common.h"
64
+#include "gicv3_internal.h"
58
+#include "hw/i2c/i2c.h"
65
+#include "cpu.h"
59
+#include "hw/i2c/i2c-ddc.h"
60
+#include "trace.h"
61
+
66
+
62
+#define SII9022_SYS_CTRL_DATA 0x1a
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
63
+#define SII9022_SYS_CTRL_PWR_DWN 0x10
68
+{
64
+#define SII9022_SYS_CTRL_AV_MUTE 0x08
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
65
+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
70
+ CPUARMState *env = &arm_cpu->env;
66
+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
67
+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
68
+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
69
+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
70
+#define SII9022_REG_CHIPID 0x1b
71
+#define SII9022_INT_ENABLE 0x3c
72
+#define SII9022_INT_STATUS 0x3d
73
+#define SII9022_INT_STATUS_HOTPLUG 0x01;
74
+#define SII9022_INT_STATUS_PLUGGED 0x04;
75
+
71
+
76
+#define TYPE_SII9022 "sii9022"
72
+ env->gicv3state = (void *)s;
77
+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
78
+
79
+typedef struct sii9022_state {
80
+ I2CSlave parent_obj;
81
+ uint8_t ptr;
82
+ bool addr_byte;
83
+ bool ddc_req;
84
+ bool ddc_skip_finish;
85
+ bool ddc;
86
+} sii9022_state;
87
+
88
+static const VMStateDescription vmstate_sii9022 = {
89
+ .name = "sii9022",
90
+ .version_id = 1,
91
+ .minimum_version_id = 1,
92
+ .fields = (VMStateField[]) {
93
+ VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
94
+ VMSTATE_UINT8(ptr, sii9022_state),
95
+ VMSTATE_BOOL(addr_byte, sii9022_state),
96
+ VMSTATE_BOOL(ddc_req, sii9022_state),
97
+ VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
98
+ VMSTATE_BOOL(ddc, sii9022_state),
99
+ VMSTATE_END_OF_LIST()
100
+ }
101
+};
73
+};
102
+
74
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
103
+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
104
+{
105
+ sii9022_state *s = SII9022(i2c);
106
+
107
+ switch (event) {
108
+ case I2C_START_SEND:
109
+ s->addr_byte = true;
110
+ break;
111
+ case I2C_START_RECV:
112
+ break;
113
+ case I2C_FINISH:
114
+ break;
115
+ case I2C_NACK:
116
+ break;
117
+ }
118
+
119
+ return 0;
120
+}
121
+
122
+static int sii9022_rx(I2CSlave *i2c)
123
+{
124
+ sii9022_state *s = SII9022(i2c);
125
+ uint8_t res = 0x00;
126
+
127
+ switch (s->ptr) {
128
+ case SII9022_SYS_CTRL_DATA:
129
+ if (s->ddc_req) {
130
+ /* Acknowledge DDC bus request */
131
+ res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
132
+ }
133
+ break;
134
+ case SII9022_REG_CHIPID:
135
+ res = 0xb0;
136
+ break;
137
+ case SII9022_INT_STATUS:
138
+ /* Something is cold-plugged in, no interrupts */
139
+ res = SII9022_INT_STATUS_PLUGGED;
140
+ break;
141
+ default:
142
+ break;
143
+ }
144
+
145
+ trace_sii9022_read_reg(s->ptr, res);
146
+ s->ptr++;
147
+
148
+ return res;
149
+}
150
+
151
+static int sii9022_tx(I2CSlave *i2c, uint8_t data)
152
+{
153
+ sii9022_state *s = SII9022(i2c);
154
+
155
+ if (s->addr_byte) {
156
+ s->ptr = data;
157
+ s->addr_byte = false;
158
+ return 0;
159
+ }
160
+
161
+ switch (s->ptr) {
162
+ case SII9022_SYS_CTRL_DATA:
163
+ if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
164
+ s->ddc_req = true;
165
+ if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
166
+ s->ddc = true;
167
+ /* Skip this finish since we just switched to DDC */
168
+ s->ddc_skip_finish = true;
169
+ trace_sii9022_switch_mode("DDC");
170
+ }
171
+ } else {
172
+ s->ddc_req = false;
173
+ s->ddc = false;
174
+ trace_sii9022_switch_mode("normal");
175
+ }
176
+ break;
177
+ default:
178
+ break;
179
+ }
180
+
181
+ trace_sii9022_write_reg(s->ptr, data);
182
+ s->ptr++;
183
+
184
+ return 0;
185
+}
186
+
187
+static void sii9022_reset(DeviceState *dev)
188
+{
189
+ sii9022_state *s = SII9022(dev);
190
+
191
+ s->ptr = 0;
192
+ s->addr_byte = false;
193
+ s->ddc_req = false;
194
+ s->ddc_skip_finish = false;
195
+ s->ddc = false;
196
+}
197
+
198
+static void sii9022_realize(DeviceState *dev, Error **errp)
199
+{
200
+ I2CBus *bus;
201
+
202
+ bus = I2C_BUS(qdev_get_parent_bus(dev));
203
+ i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
204
+}
205
+
206
+static void sii9022_class_init(ObjectClass *klass, void *data)
207
+{
208
+ DeviceClass *dc = DEVICE_CLASS(klass);
209
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
210
+
211
+ k->event = sii9022_event;
212
+ k->recv = sii9022_rx;
213
+ k->send = sii9022_tx;
214
+ dc->reset = sii9022_reset;
215
+ dc->realize = sii9022_realize;
216
+ dc->vmsd = &vmstate_sii9022;
217
+}
218
+
219
+static const TypeInfo sii9022_info = {
220
+ .name = TYPE_SII9022,
221
+ .parent = TYPE_I2C_SLAVE,
222
+ .instance_size = sizeof(sii9022_state),
223
+ .class_init = sii9022_class_init,
224
+};
225
+
226
+static void sii9022_register_types(void)
227
+{
228
+ type_register_static(&sii9022_info);
229
+}
230
+
231
+type_init(sii9022_register_types)
232
diff --git a/hw/display/trace-events b/hw/display/trace-events
233
index XXXXXXX..XXXXXXX 100644
75
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/display/trace-events
76
--- a/hw/intc/meson.build
235
+++ b/hw/display/trace-events
77
+++ b/hw/intc/meson.build
236
@@ -XXX,XX +XXX,XX @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
78
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
237
vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
79
238
vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
80
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
239
vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
81
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
240
+
82
+specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
241
+# hw/display/sii9022.c
83
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
242
+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
84
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
243
+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
85
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
244
+sii9022_switch_mode(const char *mode) "mode: %s"
245
--
86
--
246
2.16.2
87
2.25.1
247
88
248
89
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
3
The TYPE_ARM_GICV3 device is an emulated one. When using
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
5
Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
5
(which uses in-kernel support).
6
7
When using --with-devices-FOO, it is possible to build a
8
binary with a specific set of devices. When this binary is
9
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
10
irrelevant, and it is desirable to remove it from the binary.
11
12
Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
13
which select the files required to have the TYPE_ARM_GICV3
14
device, but also allowing to de-select this device.
15
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 20211115223619.2599282-3-philmd@redhat.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
20
---
8
target/arm/translate-a64.c | 7 +++++++
21
hw/intc/arm_gicv3.c | 2 +-
9
1 file changed, 7 insertions(+)
22
hw/intc/Kconfig | 5 +++++
23
hw/intc/meson.build | 10 ++++++----
24
3 files changed, 12 insertions(+), 5 deletions(-)
10
25
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
12
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
28
--- a/hw/intc/arm_gicv3.c
14
+++ b/target/arm/translate-a64.c
29
+++ b/hw/intc/arm_gicv3.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
30
@@ -XXX,XX +XXX,XX @@
16
case 0x6f: /* FNEG */
31
/*
17
need_fpst = false;
32
- * ARM Generic Interrupt Controller v3
18
break;
33
+ * ARM Generic Interrupt Controller v3 (emulation)
19
+ case 0x7d: /* FRSQRTE */
34
*
20
case 0x7f: /* FSQRT (vector) */
35
* Copyright (c) 2015 Huawei.
21
break;
36
* Copyright (c) 2016 Linaro Limited
22
default:
37
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
23
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
38
index XXXXXXX..XXXXXXX 100644
24
case 0x6f: /* FNEG */
39
--- a/hw/intc/Kconfig
25
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
40
+++ b/hw/intc/Kconfig
26
break;
41
@@ -XXX,XX +XXX,XX @@ config APIC
27
+ case 0x7d: /* FRSQRTE */
42
select MSI_NONBROKEN
28
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
43
select I8259
29
+ break;
44
30
default:
45
+config ARM_GIC_TCG
31
g_assert_not_reached();
46
+ bool
32
}
47
+ default y
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
48
+ depends on ARM_GIC && TCG
34
case 0x6f: /* FNEG */
49
+
35
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
50
config ARM_GIC_KVM
36
break;
51
bool
37
+ case 0x7d: /* FRSQRTE */
52
default y
38
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
53
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
39
+ break;
54
index XXXXXXX..XXXXXXX 100644
40
case 0x7f: /* FSQRT */
55
--- a/hw/intc/meson.build
41
gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
56
+++ b/hw/intc/meson.build
42
break;
57
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
58
'arm_gic.c',
59
'arm_gic_common.c',
60
'arm_gicv2m.c',
61
- 'arm_gicv3.c',
62
'arm_gicv3_common.c',
63
- 'arm_gicv3_dist.c',
64
'arm_gicv3_its_common.c',
65
- 'arm_gicv3_redist.c',
66
+))
67
+softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
68
+ 'arm_gicv3.c',
69
+ 'arm_gicv3_dist.c',
70
'arm_gicv3_its.c',
71
+ 'arm_gicv3_redist.c',
72
))
73
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
74
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
75
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
76
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
77
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
78
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
79
-specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
80
+specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
81
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
82
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
83
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
43
--
84
--
44
2.16.2
85
2.25.1
45
86
46
87
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
I only needed to do a little light re-factoring to support the
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
half-precision helpers.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
6
---
11
target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++---------------
7
target/arm/translate-a64.c | 7 ++++---
12
1 file changed, 54 insertions(+), 26 deletions(-)
8
1 file changed, 4 insertions(+), 3 deletions(-)
13
9
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
12
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
13
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
19
case 0xf: /* FMAXP */
15
{
20
case 0x2c: /* FMINNMP */
16
DisasContext *s = container_of(dcbase, DisasContext, base);
21
case 0x2f: /* FMINP */
17
CPUARMState *env = cpu->env_ptr;
22
- /* FP op, size[0] is 32 or 64 bit */
18
+ uint64_t pc = s->base.pc_next;
23
+ /* FP op, size[0] is 32 or 64 bit*/
19
uint32_t insn;
24
if (!u) {
20
25
- unallocated_encoding(s);
21
if (s->ss_active && !s->pstate_ss) {
26
- return;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
27
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
28
+ unallocated_encoding(s);
29
+ return;
30
+ } else {
31
+ size = MO_16;
32
+ }
33
+ } else {
34
+ size = extract32(size, 0, 1) ? MO_64 : MO_32;
35
}
36
+
37
if (!fp_access_check(s)) {
38
return;
39
}
40
41
- size = extract32(size, 0, 1) ? 3 : 2;
42
- fpst = get_fpstatus_ptr(false);
43
+ fpst = get_fpstatus_ptr(size == MO_16);
44
break;
45
default:
46
unallocated_encoding(s);
47
return;
23
return;
48
}
24
}
49
25
50
- if (size == 3) {
26
- s->pc_curr = s->base.pc_next;
51
+ if (size == MO_64) {
27
- insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
52
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
28
+ s->pc_curr = pc;
53
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
29
+ insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
54
TCGv_i64 tcg_res = tcg_temp_new_i64();
30
s->insn = insn;
55
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
31
- s->base.pc_next += 4;
56
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
32
+ s->base.pc_next = pc + 4;
57
TCGv_i32 tcg_res = tcg_temp_new_i32();
33
58
34
s->fp_access_checked = false;
59
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
35
s->sve_access_checked = false;
60
- read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
61
+ read_vec_element_i32(s, tcg_op1, rn, 0, size);
62
+ read_vec_element_i32(s, tcg_op2, rn, 1, size);
63
64
- switch (opcode) {
65
- case 0xc: /* FMAXNMP */
66
- gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
67
- break;
68
- case 0xd: /* FADDP */
69
- gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
70
- break;
71
- case 0xf: /* FMAXP */
72
- gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
73
- break;
74
- case 0x2c: /* FMINNMP */
75
- gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
76
- break;
77
- case 0x2f: /* FMINP */
78
- gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
79
- break;
80
- default:
81
- g_assert_not_reached();
82
+ if (size == MO_16) {
83
+ switch (opcode) {
84
+ case 0xc: /* FMAXNMP */
85
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
86
+ break;
87
+ case 0xd: /* FADDP */
88
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
89
+ break;
90
+ case 0xf: /* FMAXP */
91
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
92
+ break;
93
+ case 0x2c: /* FMINNMP */
94
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
95
+ break;
96
+ case 0x2f: /* FMINP */
97
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
98
+ break;
99
+ default:
100
+ g_assert_not_reached();
101
+ }
102
+ } else {
103
+ switch (opcode) {
104
+ case 0xc: /* FMAXNMP */
105
+ gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
106
+ break;
107
+ case 0xd: /* FADDP */
108
+ gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
109
+ break;
110
+ case 0xf: /* FMAXP */
111
+ gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
112
+ break;
113
+ case 0x2c: /* FMINNMP */
114
+ gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
115
+ break;
116
+ case 0x2f: /* FMINP */
117
+ gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
118
+ break;
119
+ default:
120
+ g_assert_not_reached();
121
+ }
122
}
123
124
write_fp_sreg(s, rd, tcg_res);
125
--
36
--
126
2.16.2
37
2.25.1
127
38
128
39
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Neither of these operations alter the floating point status registers
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
so we can do a pure bitwise operation, either squashing any sign
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
bit (ABS) or inverting it (NEG).
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
6
---
12
target/arm/translate-a64.c | 16 +++++++++++++++-
7
target/arm/translate.c | 9 +++++----
13
1 file changed, 15 insertions(+), 1 deletion(-)
8
1 file changed, 5 insertions(+), 4 deletions(-)
14
9
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
12
--- a/target/arm/translate.c
18
+++ b/target/arm/translate-a64.c
13
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
14
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
20
TCGv_i32 tcg_rmode = NULL;
15
{
21
TCGv_ptr tcg_fpstatus = NULL;
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
22
bool need_rmode = false;
17
CPUARMState *env = cpu->env_ptr;
23
+ bool need_fpst = true;
18
+ uint32_t pc = dc->base.pc_next;
24
int rmode;
19
unsigned int insn;
25
20
26
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
21
if (arm_pre_translate_insn(dc)) {
27
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
22
- dc->base.pc_next += 4;
28
need_rmode = true;
23
+ dc->base.pc_next = pc + 4;
29
rmode = FPROUNDING_ZERO;
30
break;
31
+ case 0x2f: /* FABS */
32
+ case 0x6f: /* FNEG */
33
+ need_fpst = false;
34
+ break;
35
default:
36
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
37
g_assert_not_reached();
38
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
39
return;
24
return;
40
}
25
}
41
26
42
- if (need_rmode) {
27
- dc->pc_curr = dc->base.pc_next;
43
+ if (need_rmode || need_fpst) {
28
- insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
44
tcg_fpstatus = get_fpstatus_ptr(true);
29
+ dc->pc_curr = pc;
45
}
30
+ insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
46
31
dc->insn = insn;
47
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
32
- dc->base.pc_next += 4;
48
case 0x7b: /* FCVTZU */
33
+ dc->base.pc_next = pc + 4;
49
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
34
disas_arm_insn(dc, insn);
50
break;
35
51
+ case 0x6f: /* FNEG */
36
arm_post_translate_insn(dc);
52
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
53
+ break;
54
default:
55
g_assert_not_reached();
56
}
57
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
58
case 0x59: /* FRINTX */
59
gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
60
break;
61
+ case 0x2f: /* FABS */
62
+ tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
63
+ break;
64
+ case 0x6f: /* FNEG */
65
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
66
+ break;
67
default:
68
g_assert_not_reached();
69
}
70
--
37
--
71
2.16.2
38
2.25.1
72
39
73
40
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This adds the full range of half-precision floating point to integral
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
instructions.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
6
---
11
target/arm/helper-a64.h | 2 +
7
target/arm/translate.c | 16 ++++++++--------
12
target/arm/helper-a64.c | 22 ++++++++
8
1 file changed, 8 insertions(+), 8 deletions(-)
13
target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++++--
14
3 files changed, 142 insertions(+), 5 deletions(-)
15
9
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
12
--- a/target/arm/translate.c
19
+++ b/target/arm/helper-a64.h
13
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
14
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
21
DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
22
DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
23
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
24
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
25
+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
26
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/helper-a64.c
29
+++ b/target/arm/helper-a64.c
30
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
31
int compare = float16_compare(f0, f1, fpst);
32
return ADVSIMD_CMPRES(compare == float_relation_greater);
33
}
34
+
35
+/* round to integral */
36
+float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
37
+{
38
+ return float16_round_to_int(x, fp_status);
39
+}
40
+
41
+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
42
+{
43
+ int old_flags = get_float_exception_flags(fp_status), new_flags;
44
+ float16 ret;
45
+
46
+ ret = float16_round_to_int(x, fp_status);
47
+
48
+ /* Suppress any inexact exceptions the conversion produced */
49
+ if (!(old_flags & float_flag_inexact)) {
50
+ new_flags = get_float_exception_flags(fp_status);
51
+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
52
+ }
53
+
54
+ return ret;
55
+}
56
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/translate-a64.c
59
+++ b/target/arm/translate-a64.c
60
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
61
*/
62
static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
63
{
15
{
64
- int fpop, opcode, a;
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
65
+ int fpop, opcode, a, u;
17
CPUARMState *env = cpu->env_ptr;
66
+ int rn, rd;
18
+ uint32_t pc = dc->base.pc_next;
67
+ bool is_q;
19
uint32_t insn;
68
+ bool is_scalar;
20
bool is_16bit;
69
+ bool only_in_vector = false;
21
70
+
22
if (arm_pre_translate_insn(dc)) {
71
+ int pass;
23
- dc->base.pc_next += 2;
72
+ TCGv_i32 tcg_rmode = NULL;
24
+ dc->base.pc_next = pc + 2;
73
+ TCGv_ptr tcg_fpstatus = NULL;
74
+ bool need_rmode = false;
75
+ int rmode;
76
77
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
78
unallocated_encoding(s);
79
return;
25
return;
80
}
26
}
81
27
82
- if (!fp_access_check(s)) {
28
- dc->pc_curr = dc->base.pc_next;
83
- return;
29
- insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
84
- }
30
+ dc->pc_curr = pc;
85
+ rd = extract32(insn, 0, 5);
31
+ insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
86
+ rn = extract32(insn, 5, 5);
32
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
87
33
- dc->base.pc_next += 2;
88
- opcode = extract32(insn, 12, 4);
34
+ pc += 2;
89
a = extract32(insn, 23, 1);
35
if (!is_16bit) {
90
+ u = extract32(insn, 29, 1);
36
- uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
91
+ is_scalar = extract32(insn, 28, 1);
37
- dc->sctlr_b);
92
+ is_q = extract32(insn, 30, 1);
38
-
93
+
39
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
94
+ opcode = extract32(insn, 12, 5);
40
insn = insn << 16 | insn2;
95
fpop = deposit32(opcode, 5, 1, a);
41
- dc->base.pc_next += 2;
96
+ fpop = deposit32(fpop, 6, 1, u);
42
+ pc += 2;
97
98
switch (fpop) {
99
+ case 0x18: /* FRINTN */
100
+ need_rmode = true;
101
+ only_in_vector = true;
102
+ rmode = FPROUNDING_TIEEVEN;
103
+ break;
104
+ case 0x19: /* FRINTM */
105
+ need_rmode = true;
106
+ only_in_vector = true;
107
+ rmode = FPROUNDING_NEGINF;
108
+ break;
109
+ case 0x38: /* FRINTP */
110
+ need_rmode = true;
111
+ only_in_vector = true;
112
+ rmode = FPROUNDING_POSINF;
113
+ break;
114
+ case 0x39: /* FRINTZ */
115
+ need_rmode = true;
116
+ only_in_vector = true;
117
+ rmode = FPROUNDING_ZERO;
118
+ break;
119
+ case 0x58: /* FRINTA */
120
+ need_rmode = true;
121
+ only_in_vector = true;
122
+ rmode = FPROUNDING_TIEAWAY;
123
+ break;
124
+ case 0x59: /* FRINTX */
125
+ case 0x79: /* FRINTI */
126
+ only_in_vector = true;
127
+ /* current rounding mode */
128
+ break;
129
default:
130
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
131
g_assert_not_reached();
132
}
43
}
133
44
+ dc->base.pc_next = pc;
134
+
45
dc->insn = insn;
135
+ /* Check additional constraints for the scalar encoding */
46
136
+ if (is_scalar) {
47
if (dc->pstate_il) {
137
+ if (!is_q) {
138
+ unallocated_encoding(s);
139
+ return;
140
+ }
141
+ /* FRINTxx is only in the vector form */
142
+ if (only_in_vector) {
143
+ unallocated_encoding(s);
144
+ return;
145
+ }
146
+ }
147
+
148
+ if (!fp_access_check(s)) {
149
+ return;
150
+ }
151
+
152
+ if (need_rmode) {
153
+ tcg_fpstatus = get_fpstatus_ptr(true);
154
+ }
155
+
156
+ if (need_rmode) {
157
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
158
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
159
+ }
160
+
161
+ if (is_scalar) {
162
+ /* no operations yet */
163
+ } else {
164
+ for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
165
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
166
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
167
+
168
+ read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
169
+
170
+ switch (fpop) {
171
+ case 0x18: /* FRINTN */
172
+ case 0x19: /* FRINTM */
173
+ case 0x38: /* FRINTP */
174
+ case 0x39: /* FRINTZ */
175
+ case 0x58: /* FRINTA */
176
+ case 0x79: /* FRINTI */
177
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
178
+ break;
179
+ case 0x59: /* FRINTX */
180
+ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
181
+ break;
182
+ default:
183
+ g_assert_not_reached();
184
+ }
185
+
186
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
187
+
188
+ tcg_temp_free_i32(tcg_res);
189
+ tcg_temp_free_i32(tcg_op);
190
+ }
191
+
192
+ clear_vec_high(s, is_q, rd);
193
+ }
194
+
195
+ if (tcg_rmode) {
196
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
197
+ tcg_temp_free_i32(tcg_rmode);
198
+ }
199
+
200
+ if (tcg_fpstatus) {
201
+ tcg_temp_free_ptr(tcg_fpstatus);
202
+ }
203
}
204
205
/* AdvSIMD scalar x indexed element
206
--
48
--
207
2.16.2
49
2.25.1
208
50
209
51
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Half-precision flush to zero behaviour is controlled by a separate
3
Create arm_check_ss_active and arm_check_kernelpage.
4
FZ16 bit in the FPCR. To handle this we pass a pointer to
5
fp_status_fp16 when working on half-precision operations. The value of
6
the presented FPCR is calculated from an amalgam of the two when read.
7
4
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
5
Reverse the order of the tests. While it doesn't matter in practice,
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
because only user-only has a kernel page and user-only never sets
10
Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
7
ss_active, ss_active has priority over execution exceptions and it
8
is best to keep them in the proper order.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
target/arm/cpu.h | 32 ++++++++++++++++++++++------
14
target/arm/translate.c | 10 +++++++---
14
target/arm/helper.c | 26 ++++++++++++++++++-----
15
1 file changed, 7 insertions(+), 3 deletions(-)
15
target/arm/translate-a64.c | 53 +++++++++++++++++++++++++---------------------
16
3 files changed, 75 insertions(+), 36 deletions(-)
17
16
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
19
--- a/target/arm/translate.c
21
+++ b/target/arm/cpu.h
20
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
21
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
23
/* scratch space when Tn are not sufficient. */
22
dc->insn_start = tcg_last_op();
24
uint32_t scratch[8];
23
}
25
24
26
- /* fp_status is the "normal" fp status. standard_fp_status retains
25
-static bool arm_pre_translate_insn(DisasContext *dc)
27
- * values corresponding to the ARM "Standard FPSCR Value", ie
26
+static bool arm_check_kernelpage(DisasContext *dc)
28
- * default-NaN, flush-to-zero, round-to-nearest and is used by
29
- * any operations (generally Neon) which the architecture defines
30
- * as controlled by the standard FPSCR value rather than the FPSCR.
31
+ /* There are a number of distinct float control structures:
32
+ *
33
+ * fp_status: is the "normal" fp status.
34
+ * fp_status_fp16: used for half-precision calculations
35
+ * standard_fp_status : the ARM "Standard FPSCR Value"
36
+ *
37
+ * Half-precision operations are governed by a separate
38
+ * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
39
+ * status structure to control this.
40
+ *
41
+ * The "Standard FPSCR", ie default-NaN, flush-to-zero,
42
+ * round-to-nearest and is used by any operations (generally
43
+ * Neon) which the architecture defines as controlled by the
44
+ * standard FPSCR value rather than the FPSCR.
45
*
46
* To avoid having to transfer exception bits around, we simply
47
* say that the FPSCR cumulative exception flags are the logical
48
- * OR of the flags in the two fp statuses. This relies on the
49
+ * OR of the flags in the three fp statuses. This relies on the
50
* only thing which needs to read the exception flags being
51
* an explicit FPSCR read.
52
*/
53
float_status fp_status;
54
+ float_status fp_status_f16;
55
float_status standard_fp_status;
56
57
/* ZCR_EL[1-3] */
58
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
59
uint32_t vfp_get_fpscr(CPUARMState *env);
60
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
61
62
-/* For A64 the FPSCR is split into two logically distinct registers,
63
+/* FPCR, Floating Point Control Register
64
+ * FPSR, Floating Poiht Status Register
65
+ *
66
+ * For A64 the FPSCR is split into two logically distinct registers,
67
* FPCR and FPSR. However since they still use non-overlapping bits
68
* we store the underlying state in fpscr and just mask on read/write.
69
*/
70
#define FPSR_MASK 0xf800009f
71
#define FPCR_MASK 0x07f79f00
72
+
73
+#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
74
+#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
75
+#define FPCR_DN (1 << 25) /* Default NaN enable bit */
76
+
77
static inline uint32_t vfp_get_fpsr(CPUARMState *env)
78
{
27
{
79
return vfp_get_fpscr(env) & FPSR_MASK;
28
#ifdef CONFIG_USER_ONLY
80
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
/* Intercept jump to the magic kernel page. */
81
index XXXXXXX..XXXXXXX 100644
30
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
82
--- a/target/arm/helper.c
31
return true;
83
+++ b/target/arm/helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
85
| (env->vfp.vec_stride << 20);
86
i = get_float_exception_flags(&env->vfp.fp_status);
87
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
88
+ i |= get_float_exception_flags(&env->vfp.fp_status_f16);
89
fpscr |= vfp_exceptbits_from_host(i);
90
return fpscr;
91
}
92
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
93
break;
94
}
95
set_float_rounding_mode(i, &env->vfp.fp_status);
96
+ set_float_rounding_mode(i, &env->vfp.fp_status_f16);
97
}
32
}
98
- if (changed & (1 << 24)) {
33
#endif
99
- set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
34
+ return false;
100
- set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
35
+}
101
+ if (changed & FPCR_FZ16) {
36
102
+ bool ftz_enabled = val & FPCR_FZ16;
37
+static bool arm_check_ss_active(DisasContext *dc)
103
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
38
+{
104
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
39
if (dc->ss_active && !dc->pstate_ss) {
105
+ }
40
/* Singlestep state is Active-pending.
106
+ if (changed & FPCR_FZ) {
41
* If we're in this state at the start of a TB then either
107
+ bool ftz_enabled = val & FPCR_FZ;
42
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
108
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
43
uint32_t pc = dc->base.pc_next;
109
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
44
unsigned int insn;
110
+ }
45
111
+ if (changed & FPCR_DN) {
46
- if (arm_pre_translate_insn(dc)) {
112
+ bool dnan_enabled = val & FPCR_DN;
47
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
113
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
48
dc->base.pc_next = pc + 4;
114
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
115
}
116
- if (changed & (1 << 25))
117
- set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
118
119
+ /* The exception flags are ORed together when we read fpscr so we
120
+ * only need to preserve the current state in one of our
121
+ * float_status values.
122
+ */
123
i = vfp_exceptbits_to_host(val);
124
set_float_exception_flags(i, &env->vfp.fp_status);
125
+ set_float_exception_flags(0, &env->vfp.fp_status_f16);
126
set_float_exception_flags(0, &env->vfp.standard_fp_status);
127
}
128
129
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/translate-a64.c
132
+++ b/target/arm/translate-a64.c
133
@@ -XXX,XX +XXX,XX @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
134
tcg_temp_free_i64(tmp);
135
}
136
137
-static TCGv_ptr get_fpstatus_ptr(void)
138
+static TCGv_ptr get_fpstatus_ptr(bool is_f16)
139
{
140
TCGv_ptr statusptr = tcg_temp_new_ptr();
141
int offset;
142
143
- /* In A64 all instructions (both FP and Neon) use the FPCR;
144
- * there is no equivalent of the A32 Neon "standard FPSCR value"
145
- * and all operations use vfp.fp_status.
146
+ /* In A64 all instructions (both FP and Neon) use the FPCR; there
147
+ * is no equivalent of the A32 Neon "standard FPSCR value".
148
+ * However half-precision operations operate under a different
149
+ * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
150
*/
151
- offset = offsetof(CPUARMState, vfp.fp_status);
152
+ if (is_f16) {
153
+ offset = offsetof(CPUARMState, vfp.fp_status_f16);
154
+ } else {
155
+ offset = offsetof(CPUARMState, vfp.fp_status);
156
+ }
157
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
158
return statusptr;
159
}
160
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
161
bool cmp_with_zero, bool signal_all_nans)
162
{
163
TCGv_i64 tcg_flags = tcg_temp_new_i64();
164
- TCGv_ptr fpst = get_fpstatus_ptr();
165
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
166
167
if (is_double) {
168
TCGv_i64 tcg_vn, tcg_vm;
169
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
170
TCGv_i32 tcg_op;
171
TCGv_i32 tcg_res;
172
173
- fpst = get_fpstatus_ptr();
174
+ fpst = get_fpstatus_ptr(false);
175
tcg_op = read_fp_sreg(s, rn);
176
tcg_res = tcg_temp_new_i32();
177
178
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
179
return;
49
return;
180
}
50
}
181
51
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
182
- fpst = get_fpstatus_ptr();
52
uint32_t insn;
183
+ fpst = get_fpstatus_ptr(false);
53
bool is_16bit;
184
tcg_op = read_fp_dreg(s, rn);
54
185
tcg_res = tcg_temp_new_i64();
55
- if (arm_pre_translate_insn(dc)) {
186
56
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
187
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
57
dc->base.pc_next = pc + 2;
188
TCGv_ptr fpst;
189
190
tcg_res = tcg_temp_new_i32();
191
- fpst = get_fpstatus_ptr();
192
+ fpst = get_fpstatus_ptr(false);
193
tcg_op1 = read_fp_sreg(s, rn);
194
tcg_op2 = read_fp_sreg(s, rm);
195
196
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
197
TCGv_ptr fpst;
198
199
tcg_res = tcg_temp_new_i64();
200
- fpst = get_fpstatus_ptr();
201
+ fpst = get_fpstatus_ptr(false);
202
tcg_op1 = read_fp_dreg(s, rn);
203
tcg_op2 = read_fp_dreg(s, rm);
204
205
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
206
{
207
TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
208
TCGv_i32 tcg_res = tcg_temp_new_i32();
209
- TCGv_ptr fpst = get_fpstatus_ptr();
210
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
211
212
tcg_op1 = read_fp_sreg(s, rn);
213
tcg_op2 = read_fp_sreg(s, rm);
214
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
215
{
216
TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
217
TCGv_i64 tcg_res = tcg_temp_new_i64();
218
- TCGv_ptr fpst = get_fpstatus_ptr();
219
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
220
221
tcg_op1 = read_fp_dreg(s, rn);
222
tcg_op2 = read_fp_dreg(s, rm);
223
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
224
TCGv_ptr tcg_fpstatus;
225
TCGv_i32 tcg_shift;
226
227
- tcg_fpstatus = get_fpstatus_ptr();
228
+ tcg_fpstatus = get_fpstatus_ptr(false);
229
230
tcg_shift = tcg_const_i32(64 - scale);
231
232
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
233
TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
234
TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
235
TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
236
- TCGv_ptr fpst = get_fpstatus_ptr();
237
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
238
239
assert(esize == 32);
240
assert(elements == 4);
241
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
242
}
243
244
size = extract32(size, 0, 1) ? 3 : 2;
245
- fpst = get_fpstatus_ptr();
246
+ fpst = get_fpstatus_ptr(false);
247
break;
248
default:
249
unallocated_encoding(s);
250
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
251
int fracbits, int size)
252
{
253
bool is_double = size == 3 ? true : false;
254
- TCGv_ptr tcg_fpst = get_fpstatus_ptr();
255
+ TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
256
TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
257
TCGv_i64 tcg_int = tcg_temp_new_i64();
258
TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
259
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
260
261
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
262
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
263
- tcg_fpstatus = get_fpstatus_ptr();
264
+ tcg_fpstatus = get_fpstatus_ptr(false);
265
tcg_shift = tcg_const_i32(fracbits);
266
267
if (is_double) {
268
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
269
int fpopcode, int rd, int rn, int rm)
270
{
271
int pass;
272
- TCGv_ptr fpst = get_fpstatus_ptr();
273
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
274
275
for (pass = 0; pass < elements; pass++) {
276
if (size) {
277
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
278
return;
58
return;
279
}
59
}
280
281
- fpst = get_fpstatus_ptr();
282
+ fpst = get_fpstatus_ptr(false);
283
284
if (is_double) {
285
TCGv_i64 tcg_op = tcg_temp_new_i64();
286
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
287
int size, int rn, int rd)
288
{
289
bool is_double = (size == 3);
290
- TCGv_ptr fpst = get_fpstatus_ptr();
291
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
292
293
if (is_double) {
294
TCGv_i64 tcg_op = tcg_temp_new_i64();
295
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
296
if (is_fcvt) {
297
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
298
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
299
- tcg_fpstatus = get_fpstatus_ptr();
300
+ tcg_fpstatus = get_fpstatus_ptr(false);
301
} else {
302
tcg_rmode = NULL;
303
tcg_fpstatus = NULL;
304
@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
305
306
/* Floating point operations need fpst */
307
if (opcode >= 0x58) {
308
- fpst = get_fpstatus_ptr();
309
+ fpst = get_fpstatus_ptr(false);
310
} else {
311
fpst = NULL;
312
}
313
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
314
}
315
316
if (need_fpstatus) {
317
- tcg_fpstatus = get_fpstatus_ptr();
318
+ tcg_fpstatus = get_fpstatus_ptr(false);
319
} else {
320
tcg_fpstatus = NULL;
321
}
322
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
323
}
324
325
if (is_fp) {
326
- fpst = get_fpstatus_ptr();
327
+ fpst = get_fpstatus_ptr(false);
328
} else {
329
fpst = NULL;
330
}
331
--
60
--
332
2.16.2
61
2.25.1
333
62
334
63
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
3
The size of the code covered by a TranslationBlock cannot be 0;
4
slightly to deal with the half-precision case.
4
this is checked via assert in tb_gen_code.
5
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
9
---
11
target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++-------------
10
target/arm/translate-a64.c | 1 +
12
1 file changed, 57 insertions(+), 23 deletions(-)
11
1 file changed, 1 insertion(+)
13
12
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
15
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
17
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
19
bool is_scalar, bool is_u, bool is_q,
18
assert(s->base.num_insns == 1);
20
int size, int rn, int rd)
19
gen_swstep_exception(s, 0, 0);
21
{
20
s->base.is_jmp = DISAS_NORETURN;
22
- bool is_double = (size == 3);
21
+ s->base.pc_next = pc + 4;
23
+ bool is_double = (size == MO_64);
24
TCGv_ptr fpst;
25
26
if (!fp_access_check(s)) {
27
return;
22
return;
28
}
23
}
29
24
30
- fpst = get_fpstatus_ptr(false);
31
+ fpst = get_fpstatus_ptr(size == MO_16);
32
33
if (is_double) {
34
TCGv_i64 tcg_op = tcg_temp_new_i64();
35
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
36
bool swap = false;
37
int pass, maxpasses;
38
39
- switch (opcode) {
40
- case 0x2e: /* FCMLT (zero) */
41
- swap = true;
42
- /* fall through */
43
- case 0x2c: /* FCMGT (zero) */
44
- genfn = gen_helper_neon_cgt_f32;
45
- break;
46
- case 0x2d: /* FCMEQ (zero) */
47
- genfn = gen_helper_neon_ceq_f32;
48
- break;
49
- case 0x6d: /* FCMLE (zero) */
50
- swap = true;
51
- /* fall through */
52
- case 0x6c: /* FCMGE (zero) */
53
- genfn = gen_helper_neon_cge_f32;
54
- break;
55
- default:
56
- g_assert_not_reached();
57
+ if (size == MO_16) {
58
+ switch (opcode) {
59
+ case 0x2e: /* FCMLT (zero) */
60
+ swap = true;
61
+ /* fall through */
62
+ case 0x2c: /* FCMGT (zero) */
63
+ genfn = gen_helper_advsimd_cgt_f16;
64
+ break;
65
+ case 0x2d: /* FCMEQ (zero) */
66
+ genfn = gen_helper_advsimd_ceq_f16;
67
+ break;
68
+ case 0x6d: /* FCMLE (zero) */
69
+ swap = true;
70
+ /* fall through */
71
+ case 0x6c: /* FCMGE (zero) */
72
+ genfn = gen_helper_advsimd_cge_f16;
73
+ break;
74
+ default:
75
+ g_assert_not_reached();
76
+ }
77
+ } else {
78
+ switch (opcode) {
79
+ case 0x2e: /* FCMLT (zero) */
80
+ swap = true;
81
+ /* fall through */
82
+ case 0x2c: /* FCMGT (zero) */
83
+ genfn = gen_helper_neon_cgt_f32;
84
+ break;
85
+ case 0x2d: /* FCMEQ (zero) */
86
+ genfn = gen_helper_neon_ceq_f32;
87
+ break;
88
+ case 0x6d: /* FCMLE (zero) */
89
+ swap = true;
90
+ /* fall through */
91
+ case 0x6c: /* FCMGE (zero) */
92
+ genfn = gen_helper_neon_cge_f32;
93
+ break;
94
+ default:
95
+ g_assert_not_reached();
96
+ }
97
}
98
99
if (is_scalar) {
100
maxpasses = 1;
101
} else {
102
- maxpasses = is_q ? 4 : 2;
103
+ int vector_size = 8 << is_q;
104
+ maxpasses = vector_size >> size;
105
}
106
107
for (pass = 0; pass < maxpasses; pass++) {
108
- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
109
+ read_vec_element_i32(s, tcg_op, rn, pass, size);
110
if (swap) {
111
genfn(tcg_res, tcg_zero, tcg_op, fpst);
112
} else {
113
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
114
if (is_scalar) {
115
write_fp_sreg(s, rd, tcg_res);
116
} else {
117
- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
118
+ write_vec_element_i32(s, tcg_res, rd, pass, size);
119
}
120
}
121
tcg_temp_free_i32(tcg_res);
122
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
123
fpop = deposit32(opcode, 5, 1, a);
124
fpop = deposit32(fpop, 6, 1, u);
125
126
+ rd = extract32(insn, 0, 5);
127
+ rn = extract32(insn, 5, 5);
128
+
129
switch (fpop) {
130
+ break;
131
+ case 0x2c: /* FCMGT (zero) */
132
+ case 0x2d: /* FCMEQ (zero) */
133
+ case 0x2e: /* FCMLT (zero) */
134
+ case 0x6c: /* FCMGE (zero) */
135
+ case 0x6d: /* FCMLE (zero) */
136
+ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
137
+ return;
138
case 0x18: /* FRINTN */
139
need_rmode = true;
140
only_in_vector = true;
141
--
25
--
142
2.16.2
26
2.25.1
143
27
144
28
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We go with the localised helper.
3
We will reuse this section of arm_deliver_fault for
4
raising pc alignment faults.
4
5
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
target/arm/helper-a64.h | 1 +
10
target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
11
target/arm/helper-a64.c | 29 +++++++++++++++++++++++++++++
11
1 file changed, 28 insertions(+), 17 deletions(-)
12
target/arm/translate-a64.c | 4 ++++
13
3 files changed, 34 insertions(+)
14
12
15
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
13
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.h
15
--- a/target/arm/tlb_helper.c
18
+++ b/target/arm/helper-a64.h
16
+++ b/target/arm/tlb_helper.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
17
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
20
DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
18
return syn;
21
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
22
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
23
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
24
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
25
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
26
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
27
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper-a64.c
30
+++ b/target/arm/helper-a64.c
31
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
32
}
19
}
33
20
34
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
21
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
35
+float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
22
- MMUAccessType access_type,
36
+{
23
- int mmu_idx, ARMMMUFaultInfo *fi)
37
+ float_status *fpst = fpstp;
24
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
38
+ uint16_t val16, sbit;
25
+ int target_el, int mmu_idx, uint32_t *ret_fsc)
39
+ int16_t exp;
26
{
40
+
27
- CPUARMState *env = &cpu->env;
41
+ if (float16_is_any_nan(a)) {
28
- int target_el;
42
+ float16 nan = a;
29
- bool same_el;
43
+ if (float16_is_signaling_nan(a, fpst)) {
30
- uint32_t syn, exc, fsr, fsc;
44
+ float_raise(float_flag_invalid, fpst);
31
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
45
+ nan = float16_maybe_silence_nan(a, fpst);
32
-
46
+ }
33
- target_el = exception_target_el(env);
47
+ if (fpst->default_nan_mode) {
34
- if (fi->stage2) {
48
+ nan = float16_default_nan(fpst);
35
- target_el = 2;
49
+ }
36
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
50
+ return nan;
37
- if (arm_is_secure_below_el3(env) && fi->s1ns) {
51
+ }
38
- env->cp15.hpfar_el2 |= HPFAR_NS;
52
+
39
- }
53
+ val16 = float16_val(a);
40
- }
54
+ sbit = 0x8000 & val16;
41
- same_el = (arm_current_el(env) == target_el);
55
+ exp = extract32(val16, 10, 5);
42
+ uint32_t fsr, fsc;
56
+
43
57
+ if (exp == 0) {
44
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
58
+ return make_float16(deposit32(sbit, 10, 5, 0x1e));
45
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
59
+ } else {
46
@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
60
+ return make_float16(deposit32(sbit, 10, 5, ~exp));
47
fsc = 0x3f;
61
+ }
48
}
49
50
+ *ret_fsc = fsc;
51
+ return fsr;
62
+}
52
+}
63
+
53
+
64
float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
54
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
65
{
55
+ MMUAccessType access_type,
66
float_status *fpst = fpstp;
56
+ int mmu_idx, ARMMMUFaultInfo *fi)
67
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
57
+{
68
index XXXXXXX..XXXXXXX 100644
58
+ CPUARMState *env = &cpu->env;
69
--- a/target/arm/translate-a64.c
59
+ int target_el;
70
+++ b/target/arm/translate-a64.c
60
+ bool same_el;
71
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
61
+ uint32_t syn, exc, fsr, fsc;
72
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
62
+
73
return;
63
+ target_el = exception_target_el(env);
74
case 0x3d: /* FRECPE */
64
+ if (fi->stage2) {
75
+ case 0x3f: /* FRECPX */
65
+ target_el = 2;
76
break;
66
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
77
case 0x18: /* FRINTN */
67
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
78
need_rmode = true;
68
+ env->cp15.hpfar_el2 |= HPFAR_NS;
79
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
69
+ }
80
case 0x3d: /* FRECPE */
70
+ }
81
gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
71
+ same_el = (arm_current_el(env) == target_el);
82
break;
72
+
83
+ case 0x3f: /* FRECPX */
73
+ fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
84
+ gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
74
+
85
+ break;
75
if (access_type == MMU_INST_FETCH) {
86
case 0x5a: /* FCVTNU */
76
syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
87
case 0x5b: /* FCVTMU */
77
exc = EXCP_PREFETCH_ABORT;
88
case 0x5c: /* FCVTAU */
89
--
78
--
90
2.16.2
79
2.25.1
91
80
92
81
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
As the rounding mode is now split between FP16 and the rest of
3
For A64, any input to an indirect branch can cause this.
4
floating point we need to be explicit when tweaking it. Instead of
4
5
passing the CPU env we now pass the appropriate fpst pointer directly.
5
For A32, many indirect branch paths force the branch to be aligned,
6
6
but BXWritePC does not. This includes the BX instruction but also
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
9
Message-id: 20180227143852.11175-6-alex.bennee@linaro.org
9
exception or force align the PC.
10
11
We choose to raise an exception because we have the infrastructure,
12
it makes the generated code for gen_bx simpler, and it has the
13
possibility of catching more guest bugs.
14
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
18
---
12
target/arm/helper.h | 2 +-
19
target/arm/helper.h | 1 +
13
target/arm/helper.c | 4 ++--
20
target/arm/syndrome.h | 5 ++++
14
target/arm/translate-a64.c | 26 +++++++++++++-------------
21
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
15
target/arm/translate.c | 12 ++++++------
22
target/arm/tlb_helper.c | 18 ++++++++++++++
16
4 files changed, 22 insertions(+), 22 deletions(-)
23
target/arm/translate-a64.c | 15 ++++++++++++
24
target/arm/translate.c | 22 ++++++++++++++++-
25
6 files changed, 87 insertions(+), 20 deletions(-)
17
26
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
27
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
29
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
30
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
31
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
23
DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
32
DEF_HELPER_2(exception_internal, void, env, i32)
24
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
33
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
25
34
DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
26
-DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env)
35
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
27
+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
36
DEF_HELPER_1(setend, void, env)
28
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
37
DEF_HELPER_2(wfi, void, env, i32)
29
38
DEF_HELPER_1(wfe, void, env)
30
DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env)
39
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/syndrome.h
33
--- a/target/arm/helper.c
42
+++ b/target/arm/syndrome.h
34
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void)
35
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
44
return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
36
/* Set the current fp rounding mode and return the old one.
45
}
37
* The argument is a softfloat float_round_ value.
46
38
*/
47
+static inline uint32_t syn_pcalignment(void)
39
-uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
48
+{
40
+uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
49
+ return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
41
{
50
+}
42
- float_status *fp_status = &env->vfp.fp_status;
51
+
43
+ float_status *fp_status = fpstp;
52
#endif /* TARGET_ARM_SYNDROME_H */
44
53
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
45
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
54
index XXXXXXX..XXXXXXX 100644
46
set_float_rounding_mode(rmode, fp_status);
55
--- a/linux-user/aarch64/cpu_loop.c
56
+++ b/linux-user/aarch64/cpu_loop.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
58
break;
59
case EXCP_PREFETCH_ABORT:
60
case EXCP_DATA_ABORT:
61
- /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
62
ec = syn_get_ec(env->exception.syndrome);
63
- assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
64
-
65
- /* Both EC have the same format for FSC, or close enough. */
66
- fsc = extract32(env->exception.syndrome, 0, 6);
67
- switch (fsc) {
68
- case 0x04 ... 0x07: /* Translation fault, level {0-3} */
69
- si_signo = TARGET_SIGSEGV;
70
- si_code = TARGET_SEGV_MAPERR;
71
+ switch (ec) {
72
+ case EC_DATAABORT:
73
+ case EC_INSNABORT:
74
+ /* Both EC have the same format for FSC, or close enough. */
75
+ fsc = extract32(env->exception.syndrome, 0, 6);
76
+ switch (fsc) {
77
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
78
+ si_signo = TARGET_SIGSEGV;
79
+ si_code = TARGET_SEGV_MAPERR;
80
+ break;
81
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
82
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
83
+ si_signo = TARGET_SIGSEGV;
84
+ si_code = TARGET_SEGV_ACCERR;
85
+ break;
86
+ case 0x11: /* Synchronous Tag Check Fault */
87
+ si_signo = TARGET_SIGSEGV;
88
+ si_code = TARGET_SEGV_MTESERR;
89
+ break;
90
+ case 0x21: /* Alignment fault */
91
+ si_signo = TARGET_SIGBUS;
92
+ si_code = TARGET_BUS_ADRALN;
93
+ break;
94
+ default:
95
+ g_assert_not_reached();
96
+ }
97
break;
98
- case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
99
- case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
100
- si_signo = TARGET_SIGSEGV;
101
- si_code = TARGET_SEGV_ACCERR;
102
- break;
103
- case 0x11: /* Synchronous Tag Check Fault */
104
- si_signo = TARGET_SIGSEGV;
105
- si_code = TARGET_SEGV_MTESERR;
106
- break;
107
- case 0x21: /* Alignment fault */
108
+ case EC_PCALIGNMENT:
109
si_signo = TARGET_SIGBUS;
110
si_code = TARGET_BUS_ADRALN;
111
break;
112
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/tlb_helper.c
115
+++ b/target/arm/tlb_helper.c
116
@@ -XXX,XX +XXX,XX @@
117
#include "cpu.h"
118
#include "internals.h"
119
#include "exec/exec-all.h"
120
+#include "exec/helper-proto.h"
121
122
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
123
unsigned int target_el,
124
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
125
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
126
}
127
128
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
129
+{
130
+ ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
131
+ int target_el = exception_target_el(env);
132
+ int mmu_idx = cpu_mmu_index(env, true);
133
+ uint32_t fsc;
134
+
135
+ env->exception.vaddress = pc;
136
+
137
+ /*
138
+ * Note that the fsc is not applicable to this exception,
139
+ * since any syndrome is pcalignment not insn_abort.
140
+ */
141
+ env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc);
142
+ raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el);
143
+}
144
+
145
#if !defined(CONFIG_USER_ONLY)
146
147
/*
47
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
148
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
48
index XXXXXXX..XXXXXXX 100644
149
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/translate-a64.c
150
--- a/target/arm/translate-a64.c
50
+++ b/target/arm/translate-a64.c
151
+++ b/target/arm/translate-a64.c
51
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
152
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
52
{
153
uint64_t pc = s->base.pc_next;
53
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
154
uint32_t insn;
54
155
55
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
156
+ /* Singlestep exceptions have the highest priority. */
56
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
157
if (s->ss_active && !s->pstate_ss) {
57
gen_helper_rints(tcg_res, tcg_op, fpst);
158
/* Singlestep state is Active-pending.
58
159
* If we're in this state at the start of a TB then either
59
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
160
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
60
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
61
tcg_temp_free_i32(tcg_rmode);
62
break;
63
}
64
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
65
{
66
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
67
68
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
69
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
70
gen_helper_rintd(tcg_res, tcg_op, fpst);
71
72
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
73
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
74
tcg_temp_free_i32(tcg_rmode);
75
break;
76
}
77
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
78
79
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
80
81
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
82
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
83
84
if (is_double) {
85
TCGv_i64 tcg_double = read_fp_dreg(s, rn);
86
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
87
tcg_temp_free_i32(tcg_single);
88
}
89
90
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
91
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
92
tcg_temp_free_i32(tcg_rmode);
93
94
if (!sf) {
95
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
96
assert(!(is_scalar && is_q));
97
98
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
99
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
100
tcg_fpstatus = get_fpstatus_ptr(false);
101
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
102
tcg_shift = tcg_const_i32(fracbits);
103
104
if (is_double) {
105
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
106
107
tcg_temp_free_ptr(tcg_fpstatus);
108
tcg_temp_free_i32(tcg_shift);
109
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
110
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
111
tcg_temp_free_i32(tcg_rmode);
112
}
113
114
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
115
116
if (is_fcvt) {
117
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
118
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
119
tcg_fpstatus = get_fpstatus_ptr(false);
120
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
121
} else {
122
tcg_rmode = NULL;
123
tcg_fpstatus = NULL;
124
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
125
}
126
127
if (is_fcvt) {
128
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
129
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
130
tcg_temp_free_i32(tcg_rmode);
131
tcg_temp_free_ptr(tcg_fpstatus);
132
}
133
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
134
return;
161
return;
135
}
162
}
136
163
137
- if (need_fpstatus) {
164
+ if (pc & 3) {
138
+ if (need_fpstatus || need_rmode) {
165
+ /*
139
tcg_fpstatus = get_fpstatus_ptr(false);
166
+ * PC alignment fault. This has priority over the instruction abort
140
} else {
167
+ * that we would receive from a translation fault via arm_ldl_code.
141
tcg_fpstatus = NULL;
168
+ * This should only be possible after an indirect branch, at the
142
}
169
+ * start of the TB.
143
if (need_rmode) {
170
+ */
144
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
171
+ assert(s->base.num_insns == 1);
145
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
172
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
146
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
+ s->base.is_jmp = DISAS_NORETURN;
147
} else {
174
+ s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
148
tcg_rmode = NULL;
175
+ return;
149
}
176
+ }
150
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
177
+
151
clear_vec_high(s, is_q, rd);
178
s->pc_curr = pc;
152
179
insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
153
if (need_rmode) {
180
s->insn = insn;
154
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
155
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
156
tcg_temp_free_i32(tcg_rmode);
157
}
158
if (need_fpstatus) {
159
diff --git a/target/arm/translate.c b/target/arm/translate.c
181
diff --git a/target/arm/translate.c b/target/arm/translate.c
160
index XXXXXXX..XXXXXXX 100644
182
index XXXXXXX..XXXXXXX 100644
161
--- a/target/arm/translate.c
183
--- a/target/arm/translate.c
162
+++ b/target/arm/translate.c
184
+++ b/target/arm/translate.c
163
@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
185
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
164
TCGv_i32 tcg_rmode;
186
uint32_t pc = dc->base.pc_next;
165
187
unsigned int insn;
166
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
188
167
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
189
- if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
168
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
190
+ /* Singlestep exceptions have the highest priority. */
169
191
+ if (arm_check_ss_active(dc)) {
170
if (dp) {
192
+ dc->base.pc_next = pc + 4;
171
TCGv_i64 tcg_op;
193
+ return;
172
@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
194
+ }
173
tcg_temp_free_i32(tcg_res);
195
+
196
+ if (pc & 3) {
197
+ /*
198
+ * PC alignment fault. This has priority over the instruction abort
199
+ * that we would receive from a translation fault via arm_ldl_code
200
+ * (or the execution of the kernelpage entrypoint). This should only
201
+ * be possible after an indirect branch, at the start of the TB.
202
+ */
203
+ assert(dc->base.num_insns == 1);
204
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
205
+ dc->base.is_jmp = DISAS_NORETURN;
206
+ dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
207
+ return;
208
+ }
209
+
210
+ if (arm_check_kernelpage(dc)) {
211
dc->base.pc_next = pc + 4;
212
return;
174
}
213
}
175
176
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
177
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
178
tcg_temp_free_i32(tcg_rmode);
179
180
tcg_temp_free_ptr(fpst);
181
@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
182
tcg_shift = tcg_const_i32(0);
183
184
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
185
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
186
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
187
188
if (dp) {
189
TCGv_i64 tcg_double, tcg_res;
190
@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
191
tcg_temp_free_i32(tcg_single);
192
}
193
194
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
195
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
196
tcg_temp_free_i32(tcg_rmode);
197
198
tcg_temp_free_i32(tcg_shift);
199
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
200
TCGv_ptr fpst = get_fpstatus_ptr(0);
201
TCGv_i32 tcg_rmode;
202
tcg_rmode = tcg_const_i32(float_round_to_zero);
203
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
204
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
205
if (dp) {
206
gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
207
} else {
208
gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
209
}
210
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
211
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
212
tcg_temp_free_i32(tcg_rmode);
213
tcg_temp_free_ptr(fpst);
214
break;
215
--
214
--
216
2.16.2
215
2.25.1
217
216
218
217
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
It looks like the ARM ARM has simplified the pseudo code for the
3
Misaligned thumb PC is architecturally impossible.
4
calculation which is done on a fixed point 9 bit integer maths. So
4
Assert is better than proceeding, in case we've missed
5
while adding f16 we can also clean this up to be a little less heavy
5
something somewhere.
6
on the floating point and just return the fractional part and leave
7
the calle's to do the final packing of the result.
8
6
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Expand a comment about aligning the pc in gdbstub.
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Fail an incoming migrate if a thumb pc is misaligned.
11
Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
target/arm/helper.h | 1 +
14
target/arm/gdbstub.c | 9 +++++++--
15
target/arm/helper.c | 226 +++++++++++++++++++++++++++++-----------------------
15
target/arm/machine.c | 10 ++++++++++
16
2 files changed, 129 insertions(+), 98 deletions(-)
16
target/arm/translate.c | 3 +++
17
3 files changed, 20 insertions(+), 2 deletions(-)
17
18
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
--- a/target/arm/gdbstub.c
21
+++ b/target/arm/helper.h
22
+++ b/target/arm/gdbstub.c
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
23
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
23
24
24
DEF_HELPER_3(recps_f32, f32, f32, f32, env)
25
tmp = ldl_p(mem_buf);
25
DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
26
26
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
27
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
27
DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
28
- cause problems if we ever implement the Jazelle DBX extensions. */
28
DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
+ /*
29
DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
30
+ * Mask out low bits of PC to workaround gdb bugs.
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
+ * This avoids an assert in thumb_tr_translate_insn, because it is
32
+ * architecturally impossible to misalign the pc.
33
+ * This will probably cause problems if we ever implement the
34
+ * Jazelle DBX extensions.
35
+ */
36
if (n == 15) {
37
tmp &= ~1;
38
}
39
diff --git a/target/arm/machine.c b/target/arm/machine.c
31
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
41
--- a/target/arm/machine.c
33
+++ b/target/arm/helper.c
42
+++ b/target/arm/machine.c
34
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
43
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
35
* int->float conversions at run-time. */
44
return -1;
36
#define float64_256 make_float64(0x4070000000000000LL)
37
#define float64_512 make_float64(0x4080000000000000LL)
38
+#define float16_maxnorm make_float16(0x7bff)
39
#define float32_maxnorm make_float32(0x7f7fffff)
40
#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
41
42
/* Reciprocal functions
43
*
44
* The algorithm that must be used to calculate the estimate
45
- * is specified by the ARM ARM, see FPRecipEstimate()
46
+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
47
*/
48
49
-static float64 recip_estimate(float64 a, float_status *real_fp_status)
50
+/* See RecipEstimate()
51
+ *
52
+ * input is a 9 bit fixed point number
53
+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
54
+ * result range 256 .. 511 for a number from 1.0 to 511/256.
55
+ */
56
+
57
+static int recip_estimate(int input)
58
{
59
- /* These calculations mustn't set any fp exception flags,
60
- * so we use a local copy of the fp_status.
61
- */
62
- float_status dummy_status = *real_fp_status;
63
- float_status *s = &dummy_status;
64
- /* q = (int)(a * 512.0) */
65
- float64 q = float64_mul(float64_512, a, s);
66
- int64_t q_int = float64_to_int64_round_to_zero(q, s);
67
-
68
- /* r = 1.0 / (((double)q + 0.5) / 512.0) */
69
- q = int64_to_float64(q_int, s);
70
- q = float64_add(q, float64_half, s);
71
- q = float64_div(q, float64_512, s);
72
- q = float64_div(float64_one, q, s);
73
-
74
- /* s = (int)(256.0 * r + 0.5) */
75
- q = float64_mul(q, float64_256, s);
76
- q = float64_add(q, float64_half, s);
77
- q_int = float64_to_int64_round_to_zero(q, s);
78
-
79
- /* return (double)s / 256.0 */
80
- return float64_div(int64_to_float64(q_int, s), float64_256, s);
81
+ int a, b, r;
82
+ assert(256 <= input && input < 512);
83
+ a = (input * 2) + 1;
84
+ b = (1 << 19) / a;
85
+ r = (b + 1) >> 1;
86
+ assert(256 <= r && r < 512);
87
+ return r;
88
}
89
90
-/* Common wrapper to call recip_estimate */
91
-static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
92
-{
93
- uint64_t val64 = float64_val(num);
94
- uint64_t frac = extract64(val64, 0, 52);
95
- int64_t exp = extract64(val64, 52, 11);
96
- uint64_t sbit;
97
- float64 scaled, estimate;
98
+/*
99
+ * Common wrapper to call recip_estimate
100
+ *
101
+ * The parameters are exponent and 64 bit fraction (without implicit
102
+ * bit) where the binary point is nominally at bit 52. Returns a
103
+ * float64 which can then be rounded to the appropriate size by the
104
+ * callee.
105
+ */
106
107
- /* Generate the scaled number for the estimate function */
108
- if (exp == 0) {
109
+static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
110
+{
111
+ uint32_t scaled, estimate;
112
+ uint64_t result_frac;
113
+ int result_exp;
114
+
115
+ /* Handle sub-normals */
116
+ if (*exp == 0) {
117
if (extract64(frac, 51, 1) == 0) {
118
- exp = -1;
119
- frac = extract64(frac, 0, 50) << 2;
120
+ *exp = -1;
121
+ frac <<= 2;
122
} else {
123
- frac = extract64(frac, 0, 51) << 1;
124
+ frac <<= 1;
125
}
45
}
126
}
46
}
127
128
- /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
129
- scaled = make_float64((0x3feULL << 52)
130
- | extract64(frac, 44, 8) << 44);
131
+ /* scaled = UInt('1':fraction<51:44>) */
132
+ scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
133
+ estimate = recip_estimate(scaled);
134
135
- estimate = recip_estimate(scaled, fpst);
136
-
137
- /* Build new result */
138
- val64 = float64_val(estimate);
139
- sbit = 0x8000000000000000ULL & val64;
140
- exp = off - exp;
141
- frac = extract64(val64, 0, 52);
142
-
143
- if (exp == 0) {
144
- frac = 1ULL << 51 | extract64(frac, 1, 51);
145
- } else if (exp == -1) {
146
- frac = 1ULL << 50 | extract64(frac, 2, 50);
147
- exp = 0;
148
+ result_exp = exp_off - *exp;
149
+ result_frac = deposit64(0, 44, 8, estimate);
150
+ if (result_exp == 0) {
151
+ result_frac = deposit64(result_frac >> 1, 51, 1, 1);
152
+ } else if (result_exp == -1) {
153
+ result_frac = deposit64(result_frac >> 2, 50, 2, 1);
154
+ result_exp = 0;
155
}
156
157
- return make_float64(sbit | (exp << 52) | frac);
158
+ *exp = result_exp;
159
+
47
+
160
+ return result_frac;
48
+ /*
161
}
49
+ * Misaligned thumb pc is architecturally impossible.
162
50
+ * We have an assert in thumb_tr_translate_insn to verify this.
163
static bool round_to_inf(float_status *fpst, bool sign_bit)
51
+ * Fail an incoming migrate to avoid this assert.
164
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
52
+ */
165
g_assert_not_reached();
53
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
166
}
54
+ return -1;
167
168
+float16 HELPER(recpe_f16)(float16 input, void *fpstp)
169
+{
170
+ float_status *fpst = fpstp;
171
+ float16 f16 = float16_squash_input_denormal(input, fpst);
172
+ uint32_t f16_val = float16_val(f16);
173
+ uint32_t f16_sign = float16_is_neg(f16);
174
+ int f16_exp = extract32(f16_val, 10, 5);
175
+ uint32_t f16_frac = extract32(f16_val, 0, 10);
176
+ uint64_t f64_frac;
177
+
178
+ if (float16_is_any_nan(f16)) {
179
+ float16 nan = f16;
180
+ if (float16_is_signaling_nan(f16, fpst)) {
181
+ float_raise(float_flag_invalid, fpst);
182
+ nan = float16_maybe_silence_nan(f16, fpst);
183
+ }
184
+ if (fpst->default_nan_mode) {
185
+ nan = float16_default_nan(fpst);
186
+ }
187
+ return nan;
188
+ } else if (float16_is_infinity(f16)) {
189
+ return float16_set_sign(float16_zero, float16_is_neg(f16));
190
+ } else if (float16_is_zero(f16)) {
191
+ float_raise(float_flag_divbyzero, fpst);
192
+ return float16_set_sign(float16_infinity, float16_is_neg(f16));
193
+ } else if (float16_abs(f16) < (1 << 8)) {
194
+ /* Abs(value) < 2.0^-16 */
195
+ float_raise(float_flag_overflow | float_flag_inexact, fpst);
196
+ if (round_to_inf(fpst, f16_sign)) {
197
+ return float16_set_sign(float16_infinity, f16_sign);
198
+ } else {
199
+ return float16_set_sign(float16_maxnorm, f16_sign);
200
+ }
201
+ } else if (f16_exp >= 29 && fpst->flush_to_zero) {
202
+ float_raise(float_flag_underflow, fpst);
203
+ return float16_set_sign(float16_zero, float16_is_neg(f16));
204
+ }
55
+ }
205
+
56
+
206
+ f64_frac = call_recip_estimate(&f16_exp, 29,
57
if (!kvm_enabled()) {
207
+ ((uint64_t) f16_frac) << (52 - 10));
58
pmu_op_finish(&cpu->env);
59
}
60
diff --git a/target/arm/translate.c b/target/arm/translate.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/translate.c
63
+++ b/target/arm/translate.c
64
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
65
uint32_t insn;
66
bool is_16bit;
67
68
+ /* Misaligned thumb PC is architecturally impossible. */
69
+ assert((dc->base.pc_next & 1) == 0);
208
+
70
+
209
+ /* result = sign : result_exp<4:0> : fraction<51:42> */
71
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
210
+ f16_val = deposit32(0, 15, 1, f16_sign);
72
dc->base.pc_next = pc + 2;
211
+ f16_val = deposit32(f16_val, 10, 5, f16_exp);
73
return;
212
+ f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
213
+ return make_float16(f16_val);
214
+}
215
+
216
float32 HELPER(recpe_f32)(float32 input, void *fpstp)
217
{
218
float_status *fpst = fpstp;
219
float32 f32 = float32_squash_input_denormal(input, fpst);
220
uint32_t f32_val = float32_val(f32);
221
- uint32_t f32_sbit = 0x80000000ULL & f32_val;
222
- int32_t f32_exp = extract32(f32_val, 23, 8);
223
+ bool f32_sign = float32_is_neg(f32);
224
+ int f32_exp = extract32(f32_val, 23, 8);
225
uint32_t f32_frac = extract32(f32_val, 0, 23);
226
- float64 f64, r64;
227
- uint64_t r64_val;
228
- int64_t r64_exp;
229
- uint64_t r64_frac;
230
+ uint64_t f64_frac;
231
232
if (float32_is_any_nan(f32)) {
233
float32 nan = f32;
234
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
235
} else if (float32_is_zero(f32)) {
236
float_raise(float_flag_divbyzero, fpst);
237
return float32_set_sign(float32_infinity, float32_is_neg(f32));
238
- } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
239
+ } else if (float32_abs(f32) < (1ULL << 21)) {
240
/* Abs(value) < 2.0^-128 */
241
float_raise(float_flag_overflow | float_flag_inexact, fpst);
242
- if (round_to_inf(fpst, f32_sbit)) {
243
- return float32_set_sign(float32_infinity, float32_is_neg(f32));
244
+ if (round_to_inf(fpst, f32_sign)) {
245
+ return float32_set_sign(float32_infinity, f32_sign);
246
} else {
247
- return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
248
+ return float32_set_sign(float32_maxnorm, f32_sign);
249
}
250
} else if (f32_exp >= 253 && fpst->flush_to_zero) {
251
float_raise(float_flag_underflow, fpst);
252
return float32_set_sign(float32_zero, float32_is_neg(f32));
253
}
254
255
+ f64_frac = call_recip_estimate(&f32_exp, 253,
256
+ ((uint64_t) f32_frac) << (52 - 23));
257
258
- f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
259
- r64 = call_recip_estimate(f64, 253, fpst);
260
- r64_val = float64_val(r64);
261
- r64_exp = extract64(r64_val, 52, 11);
262
- r64_frac = extract64(r64_val, 0, 52);
263
-
264
- /* result = sign : result_exp<7:0> : fraction<51:29>; */
265
- return make_float32(f32_sbit |
266
- (r64_exp & 0xff) << 23 |
267
- extract64(r64_frac, 29, 24));
268
+ /* result = sign : result_exp<7:0> : fraction<51:29> */
269
+ f32_val = deposit32(0, 31, 1, f32_sign);
270
+ f32_val = deposit32(f32_val, 23, 8, f32_exp);
271
+ f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
272
+ return make_float32(f32_val);
273
}
274
275
float64 HELPER(recpe_f64)(float64 input, void *fpstp)
276
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
277
float_status *fpst = fpstp;
278
float64 f64 = float64_squash_input_denormal(input, fpst);
279
uint64_t f64_val = float64_val(f64);
280
- uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
281
- int64_t f64_exp = extract64(f64_val, 52, 11);
282
- float64 r64;
283
- uint64_t r64_val;
284
- int64_t r64_exp;
285
- uint64_t r64_frac;
286
+ bool f64_sign = float64_is_neg(f64);
287
+ int f64_exp = extract64(f64_val, 52, 11);
288
+ uint64_t f64_frac = extract64(f64_val, 0, 52);
289
290
/* Deal with any special cases */
291
if (float64_is_any_nan(f64)) {
292
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
293
} else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
294
/* Abs(value) < 2.0^-1024 */
295
float_raise(float_flag_overflow | float_flag_inexact, fpst);
296
- if (round_to_inf(fpst, f64_sbit)) {
297
- return float64_set_sign(float64_infinity, float64_is_neg(f64));
298
+ if (round_to_inf(fpst, f64_sign)) {
299
+ return float64_set_sign(float64_infinity, f64_sign);
300
} else {
301
- return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
302
+ return float64_set_sign(float64_maxnorm, f64_sign);
303
}
304
} else if (f64_exp >= 2045 && fpst->flush_to_zero) {
305
float_raise(float_flag_underflow, fpst);
306
return float64_set_sign(float64_zero, float64_is_neg(f64));
307
}
308
309
- r64 = call_recip_estimate(f64, 2045, fpst);
310
- r64_val = float64_val(r64);
311
- r64_exp = extract64(r64_val, 52, 11);
312
- r64_frac = extract64(r64_val, 0, 52);
313
+ f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
314
315
- /* result = sign : result_exp<10:0> : fraction<51:0> */
316
- return make_float64(f64_sbit |
317
- ((r64_exp & 0x7ff) << 52) |
318
- r64_frac);
319
+ /* result = sign : result_exp<10:0> : fraction<51:0>; */
320
+ f64_val = deposit64(0, 63, 1, f64_sign);
321
+ f64_val = deposit64(f64_val, 52, 11, f64_exp);
322
+ f64_val = deposit64(f64_val, 0, 52, f64_frac);
323
+ return make_float64(f64_val);
324
}
325
326
/* The algorithm that must be used to calculate the estimate
327
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
328
329
uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
330
{
331
- float_status *s = fpstp;
332
- float64 f64;
333
+ /* float_status *s = fpstp; */
334
+ int input, estimate;
335
336
if ((a & 0x80000000) == 0) {
337
return 0xffffffff;
338
}
339
340
- f64 = make_float64((0x3feULL << 52)
341
- | ((int64_t)(a & 0x7fffffff) << 21));
342
+ input = extract32(a, 23, 9);
343
+ estimate = recip_estimate(input);
344
345
- f64 = recip_estimate(f64, s);
346
-
347
- return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
348
+ return deposit32(0, (32 - 9), 9, estimate);
349
}
350
351
uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
352
--
74
--
353
2.16.2
75
2.25.1
354
76
355
77
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This actually covers two different sections of the encoding table:
3
Both single-step and pc alignment faults have priority over
4
breakpoint exceptions.
4
5
5
Advanced SIMD scalar two-register miscellaneous FP16
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Advanced SIMD two-register miscellaneous (FP16)
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
8
The difference between the two is covered by a combination of Q (bit
9
30) and S (bit 28). Notably the FRINTx instructions are only
10
available in the vector form.
11
12
This is just the decode skeleton which will be filled out by later
13
patches.
14
15
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
9
---
20
target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++
10
target/arm/debug_helper.c | 23 +++++++++++++++++++++++
21
1 file changed, 40 insertions(+)
11
1 file changed, 23 insertions(+)
22
12
23
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
24
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/translate-a64.c
15
--- a/target/arm/debug_helper.c
26
+++ b/target/arm/translate-a64.c
16
+++ b/target/arm/debug_helper.c
27
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
17
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
18
{
19
ARMCPU *cpu = ARM_CPU(cs);
20
CPUARMState *env = &cpu->env;
21
+ target_ulong pc;
22
int n;
23
24
/*
25
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
26
return false;
28
}
27
}
29
}
28
30
29
+ /*
31
+/* AdvSIMD [scalar] two register miscellaneous (FP16)
30
+ * Single-step exceptions have priority over breakpoint exceptions.
32
+ *
31
+ * If single-step state is active-pending, suppress the bp.
33
+ * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
32
+ */
34
+ * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
33
+ if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
35
+ * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
34
+ return false;
36
+ * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
37
+ * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
38
+ * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
39
+ *
40
+ * This actually covers two groups where scalar access is governed by
41
+ * bit 28. A bunch of the instructions (float to integral) only exist
42
+ * in the vector form and are un-allocated for the scalar decode. Also
43
+ * in the scalar decode Q is always 1.
44
+ */
45
+static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
46
+{
47
+ int fpop, opcode, a;
48
+
49
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
50
+ unallocated_encoding(s);
51
+ return;
52
+ }
35
+ }
53
+
36
+
54
+ if (!fp_access_check(s)) {
37
+ /*
55
+ return;
38
+ * PC alignment faults have priority over breakpoint exceptions.
39
+ */
40
+ pc = is_a64(env) ? env->pc : env->regs[15];
41
+ if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
42
+ return false;
56
+ }
43
+ }
57
+
44
+
58
+ opcode = extract32(insn, 12, 4);
45
+ /*
59
+ a = extract32(insn, 23, 1);
46
+ * Instruction aborts have priority over breakpoint exceptions.
60
+ fpop = deposit32(opcode, 5, 1, a);
47
+ * TODO: We would need to look up the page for PC and verify that
48
+ * it is present and executable.
49
+ */
61
+
50
+
62
+ switch (fpop) {
51
for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
63
+ default:
52
if (bp_wp_matches(cpu, n, false)) {
64
+ fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
53
return true;
65
+ g_assert_not_reached();
66
+ }
67
+
68
+}
69
+
70
/* AdvSIMD scalar x indexed element
71
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
72
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
73
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
74
{ 0xce800000, 0xffe00000, disas_crypto_xar },
75
{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
76
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
77
+ { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
78
{ 0x00000000, 0x00000000, NULL }
79
};
80
81
--
54
--
82
2.16.2
55
2.25.1
83
56
84
57
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Much like recpe the ARM ARM has simplified the pseudo code for the
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
calculation which is done on a fixed point 9 bit integer maths. So
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
while adding f16 we can also clean this up to be a little less heavy
6
on the floating point and just return the fractional part and leave
7
the calle's to do the final packing of the result.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180227143852.11175-27-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
6
---
14
target/arm/helper.h | 1 +
7
tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++
15
target/arm/helper.c | 221 ++++++++++++++++++++++++----------------------------
8
tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++
16
2 files changed, 104 insertions(+), 118 deletions(-)
9
tests/tcg/aarch64/Makefile.target | 4 +--
10
tests/tcg/arm/Makefile.target | 4 +++
11
4 files changed, 89 insertions(+), 2 deletions(-)
12
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
13
create mode 100644 tests/tcg/arm/pcalign-a32.c
17
14
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
19
index XXXXXXX..XXXXXXX 100644
16
new file mode 100644
20
--- a/target/arm/helper.h
17
index XXXXXXX..XXXXXXX
21
+++ b/target/arm/helper.h
18
--- /dev/null
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
19
+++ b/tests/tcg/aarch64/pcalign-a64.c
23
DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
20
@@ -XXX,XX +XXX,XX @@
24
DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
21
+/* Test PC misalignment exception */
25
DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
26
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
27
DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_2(recpe_u32, i32, i32, ptr)
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
35
/* The algorithm that must be used to calculate the estimate
36
* is specified by the ARM ARM.
37
*/
38
-static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
39
+
22
+
40
+static int do_recip_sqrt_estimate(int a)
23
+#include <assert.h>
41
{
24
+#include <signal.h>
42
- /* These calculations mustn't set any fp exception flags,
25
+#include <stdlib.h>
43
- * so we use a local copy of the fp_status.
26
+#include <stdio.h>
44
- */
27
+
45
- float_status dummy_status = *real_fp_status;
28
+static void *expected;
46
- float_status *s = &dummy_status;
29
+
47
- float64 q;
30
+static void sigbus(int sig, siginfo_t *info, void *vuc)
48
- int64_t q_int;
31
+{
49
+ int b, estimate;
32
+ assert(info->si_code == BUS_ADRALN);
50
33
+ assert(info->si_addr == expected);
51
- if (float64_lt(a, float64_half, s)) {
34
+ exit(EXIT_SUCCESS);
52
- /* range 0.25 <= a < 0.5 */
53
-
54
- /* a in units of 1/512 rounded down */
55
- /* q0 = (int)(a * 512.0); */
56
- q = float64_mul(float64_512, a, s);
57
- q_int = float64_to_int64_round_to_zero(q, s);
58
-
59
- /* reciprocal root r */
60
- /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
61
- q = int64_to_float64(q_int, s);
62
- q = float64_add(q, float64_half, s);
63
- q = float64_div(q, float64_512, s);
64
- q = float64_sqrt(q, s);
65
- q = float64_div(float64_one, q, s);
66
+ assert(128 <= a && a < 512);
67
+ if (a < 256) {
68
+ a = a * 2 + 1;
69
} else {
70
- /* range 0.5 <= a < 1.0 */
71
-
72
- /* a in units of 1/256 rounded down */
73
- /* q1 = (int)(a * 256.0); */
74
- q = float64_mul(float64_256, a, s);
75
- int64_t q_int = float64_to_int64_round_to_zero(q, s);
76
-
77
- /* reciprocal root r */
78
- /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
79
- q = int64_to_float64(q_int, s);
80
- q = float64_add(q, float64_half, s);
81
- q = float64_div(q, float64_256, s);
82
- q = float64_sqrt(q, s);
83
- q = float64_div(float64_one, q, s);
84
+ a = (a >> 1) << 1;
85
+ a = (a + 1) * 2;
86
}
87
- /* r in units of 1/256 rounded to nearest */
88
- /* s = (int)(256.0 * r + 0.5); */
89
+ b = 512;
90
+ while (a * (b + 1) * (b + 1) < (1 << 28)) {
91
+ b += 1;
92
+ }
93
+ estimate = (b + 1) / 2;
94
+ assert(256 <= estimate && estimate < 512);
95
96
- q = float64_mul(q, float64_256,s );
97
- q = float64_add(q, float64_half, s);
98
- q_int = float64_to_int64_round_to_zero(q, s);
99
+ return estimate;
100
+}
35
+}
101
102
- /* return (double)s / 256.0;*/
103
- return float64_div(int64_to_float64(q_int, s), float64_256, s);
104
+
36
+
105
+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
37
+int main()
106
+{
38
+{
107
+ int estimate;
39
+ void *tmp;
108
+ uint32_t scaled;
109
+
40
+
110
+ if (*exp == 0) {
41
+ struct sigaction sa = {
111
+ while (extract64(frac, 51, 1) == 0) {
42
+ .sa_sigaction = sigbus,
112
+ frac = frac << 1;
43
+ .sa_flags = SA_SIGINFO
113
+ *exp -= 1;
44
+ };
114
+ }
45
+
115
+ frac = extract64(frac, 0, 51) << 1;
46
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
47
+ perror("sigaction");
48
+ return EXIT_FAILURE;
116
+ }
49
+ }
117
+
50
+
118
+ if (*exp & 1) {
51
+ asm volatile("adr %0, 1f + 1\n\t"
119
+ /* scaled = UInt('01':fraction<51:45>) */
52
+ "str %0, %1\n\t"
120
+ scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
53
+ "br %0\n"
121
+ } else {
54
+ "1:"
122
+ /* scaled = UInt('1':fraction<51:44>) */
55
+ : "=&r"(tmp), "=m"(expected));
123
+ scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
56
+ abort();
124
+ }
57
+}
125
+ estimate = do_recip_sqrt_estimate(scaled);
58
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
59
new file mode 100644
60
index XXXXXXX..XXXXXXX
61
--- /dev/null
62
+++ b/tests/tcg/arm/pcalign-a32.c
63
@@ -XXX,XX +XXX,XX @@
64
+/* Test PC misalignment exception */
126
+
65
+
127
+ *exp = (exp_off - *exp) / 2;
66
+#ifdef __thumb__
128
+ return extract64(estimate, 0, 8) << 44;
67
+#error "This test must be compiled for ARM"
68
+#endif
69
+
70
+#include <assert.h>
71
+#include <signal.h>
72
+#include <stdlib.h>
73
+#include <stdio.h>
74
+
75
+static void *expected;
76
+
77
+static void sigbus(int sig, siginfo_t *info, void *vuc)
78
+{
79
+ assert(info->si_code == BUS_ADRALN);
80
+ assert(info->si_addr == expected);
81
+ exit(EXIT_SUCCESS);
129
+}
82
+}
130
+
83
+
131
+float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
84
+int main()
132
+{
85
+{
133
+ float_status *s = fpstp;
86
+ void *tmp;
134
+ float16 f16 = float16_squash_input_denormal(input, s);
135
+ uint16_t val = float16_val(f16);
136
+ bool f16_sign = float16_is_neg(f16);
137
+ int f16_exp = extract32(val, 10, 5);
138
+ uint16_t f16_frac = extract32(val, 0, 10);
139
+ uint64_t f64_frac;
140
+
87
+
141
+ if (float16_is_any_nan(f16)) {
88
+ struct sigaction sa = {
142
+ float16 nan = f16;
89
+ .sa_sigaction = sigbus,
143
+ if (float16_is_signaling_nan(f16, s)) {
90
+ .sa_flags = SA_SIGINFO
144
+ float_raise(float_flag_invalid, s);
91
+ };
145
+ nan = float16_maybe_silence_nan(f16, s);
92
+
146
+ }
93
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
147
+ if (s->default_nan_mode) {
94
+ perror("sigaction");
148
+ nan = float16_default_nan(s);
95
+ return EXIT_FAILURE;
149
+ }
150
+ return nan;
151
+ } else if (float16_is_zero(f16)) {
152
+ float_raise(float_flag_divbyzero, s);
153
+ return float16_set_sign(float16_infinity, f16_sign);
154
+ } else if (f16_sign) {
155
+ float_raise(float_flag_invalid, s);
156
+ return float16_default_nan(s);
157
+ } else if (float16_is_infinity(f16)) {
158
+ return float16_zero;
159
+ }
96
+ }
160
+
97
+
161
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
98
+ asm volatile("adr %0, 1f + 2\n\t"
162
+ * preserving the parity of the exponent. */
99
+ "str %0, %1\n\t"
100
+ "bx %0\n"
101
+ "1:"
102
+ : "=&r"(tmp), "=m"(expected));
163
+
103
+
164
+ f64_frac = ((uint64_t) f16_frac) << (52 - 10);
104
+ /*
105
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
106
+ * the address or not. If so, we can legitimately fall through.
107
+ */
108
+ return EXIT_SUCCESS;
109
+}
110
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
111
index XXXXXXX..XXXXXXX 100644
112
--- a/tests/tcg/aarch64/Makefile.target
113
+++ b/tests/tcg/aarch64/Makefile.target
114
@@ -XXX,XX +XXX,XX @@ VPATH         += $(ARM_SRC)
115
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
116
VPATH         += $(AARCH64_SRC)
117
118
-# Float-convert Tests
119
-AARCH64_TESTS=fcvt
120
+# Base architecture tests
121
+AARCH64_TESTS=fcvt pcalign-a64
122
123
fcvt: LDFLAGS+=-lm
124
125
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
126
index XXXXXXX..XXXXXXX 100644
127
--- a/tests/tcg/arm/Makefile.target
128
+++ b/tests/tcg/arm/Makefile.target
129
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
130
    $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
131
    $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
132
133
+# PC alignment test
134
+ARM_TESTS += pcalign-a32
135
+pcalign-a32: CFLAGS+=-marm
165
+
136
+
166
+ f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
137
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
167
+
138
168
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
139
# Semihosting smoke test for linux-user
169
+ val = deposit32(0, 15, 1, f16_sign);
170
+ val = deposit32(val, 10, 5, f16_exp);
171
+ val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
172
+ return make_float16(val);
173
}
174
175
float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
176
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
177
float_status *s = fpstp;
178
float32 f32 = float32_squash_input_denormal(input, s);
179
uint32_t val = float32_val(f32);
180
- uint32_t f32_sbit = 0x80000000 & val;
181
- int32_t f32_exp = extract32(val, 23, 8);
182
+ uint32_t f32_sign = float32_is_neg(f32);
183
+ int f32_exp = extract32(val, 23, 8);
184
uint32_t f32_frac = extract32(val, 0, 23);
185
uint64_t f64_frac;
186
- uint64_t val64;
187
- int result_exp;
188
- float64 f64;
189
190
if (float32_is_any_nan(f32)) {
191
float32 nan = f32;
192
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
193
* preserving the parity of the exponent. */
194
195
f64_frac = ((uint64_t) f32_frac) << 29;
196
- if (f32_exp == 0) {
197
- while (extract64(f64_frac, 51, 1) == 0) {
198
- f64_frac = f64_frac << 1;
199
- f32_exp = f32_exp-1;
200
- }
201
- f64_frac = extract64(f64_frac, 0, 51) << 1;
202
- }
203
204
- if (extract64(f32_exp, 0, 1) == 0) {
205
- f64 = make_float64(((uint64_t) f32_sbit) << 32
206
- | (0x3feULL << 52)
207
- | f64_frac);
208
- } else {
209
- f64 = make_float64(((uint64_t) f32_sbit) << 32
210
- | (0x3fdULL << 52)
211
- | f64_frac);
212
- }
213
+ f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
214
215
- result_exp = (380 - f32_exp) / 2;
216
-
217
- f64 = recip_sqrt_estimate(f64, s);
218
-
219
- val64 = float64_val(f64);
220
-
221
- val = ((result_exp & 0xff) << 23)
222
- | ((val64 >> 29) & 0x7fffff);
223
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
224
+ val = deposit32(0, 31, 1, f32_sign);
225
+ val = deposit32(val, 23, 8, f32_exp);
226
+ val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
227
return make_float32(val);
228
}
229
230
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
231
float_status *s = fpstp;
232
float64 f64 = float64_squash_input_denormal(input, s);
233
uint64_t val = float64_val(f64);
234
- uint64_t f64_sbit = 0x8000000000000000ULL & val;
235
- int64_t f64_exp = extract64(val, 52, 11);
236
+ bool f64_sign = float64_is_neg(f64);
237
+ int f64_exp = extract64(val, 52, 11);
238
uint64_t f64_frac = extract64(val, 0, 52);
239
- int64_t result_exp;
240
- uint64_t result_frac;
241
242
if (float64_is_any_nan(f64)) {
243
float64 nan = f64;
244
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
245
return float64_zero;
246
}
247
248
- /* Scale and normalize to a double-precision value between 0.25 and 1.0,
249
- * preserving the parity of the exponent. */
250
+ f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
251
252
- if (f64_exp == 0) {
253
- while (extract64(f64_frac, 51, 1) == 0) {
254
- f64_frac = f64_frac << 1;
255
- f64_exp = f64_exp - 1;
256
- }
257
- f64_frac = extract64(f64_frac, 0, 51) << 1;
258
- }
259
-
260
- if (extract64(f64_exp, 0, 1) == 0) {
261
- f64 = make_float64(f64_sbit
262
- | (0x3feULL << 52)
263
- | f64_frac);
264
- } else {
265
- f64 = make_float64(f64_sbit
266
- | (0x3fdULL << 52)
267
- | f64_frac);
268
- }
269
-
270
- result_exp = (3068 - f64_exp) / 2;
271
-
272
- f64 = recip_sqrt_estimate(f64, s);
273
-
274
- result_frac = extract64(float64_val(f64), 0, 52);
275
-
276
- return make_float64(f64_sbit |
277
- ((result_exp & 0x7ff) << 52) |
278
- result_frac);
279
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
280
+ val = deposit64(0, 61, 1, f64_sign);
281
+ val = deposit64(val, 52, 11, f64_exp);
282
+ val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
283
+ return make_float64(val);
284
}
285
286
uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
287
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
288
289
uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
290
{
291
- float_status *fpst = fpstp;
292
- float64 f64;
293
+ int estimate;
294
295
if ((a & 0xc0000000) == 0) {
296
return 0xffffffff;
297
}
298
299
- if (a & 0x80000000) {
300
- f64 = make_float64((0x3feULL << 52)
301
- | ((uint64_t)(a & 0x7fffffff) << 21));
302
- } else { /* bits 31-30 == '01' */
303
- f64 = make_float64((0x3fdULL << 52)
304
- | ((uint64_t)(a & 0x3fffffff) << 22));
305
- }
306
+ estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
307
308
- f64 = recip_sqrt_estimate(f64, fpst);
309
-
310
- return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
311
+ return deposit32(0, 23, 9, estimate);
312
}
313
314
/* VFPv4 fused multiply-accumulate */
315
--
140
--
316
2.16.2
141
2.25.1
317
142
318
143
diff view generated by jsdifflib
1
Set the appropriate Linux hwcap bits to tell the guest binary if we
1
In the SSE decode function gen_sse(), we combine a byte
2
have implemented half-precision floating point support.
2
'b' and a value 'b1' which can be [0..3], and switch on them:
3
b |= (b1 << 8);
4
switch (b) {
5
...
6
default:
7
unknown_op:
8
gen_unknown_opcode(env, s);
9
return;
10
}
3
11
12
In three cases inside this switch, we were then also checking for
13
"if (b1 >= 2) { goto unknown_op; }".
14
However, this can never happen, because the 'case' values in each place
15
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
16
cases to the default already.
17
18
This check was added in commit c045af25a52e9 in 2010; the added code
19
was unnecessary then as well, and was apparently intended only to
20
ensure that we never accidentally ended up indexing off the end
21
of an sse_op_table with only 2 entries as a result of future bugs
22
in the decode logic.
23
24
Change the checks to assert() instead, and make sure they're always
25
immediately before the array access they are protecting.
26
27
Fixes: Coverity CID 1460207
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
---
30
---
7
linux-user/elfload.c | 2 ++
31
target/i386/tcg/translate.c | 12 +++---------
8
1 file changed, 2 insertions(+)
32
1 file changed, 3 insertions(+), 9 deletions(-)
9
33
10
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
34
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
11
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
12
--- a/linux-user/elfload.c
36
--- a/target/i386/tcg/translate.c
13
+++ b/linux-user/elfload.c
37
+++ b/target/i386/tcg/translate.c
14
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
38
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
15
GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
39
case 0x171: /* shift xmm, im */
16
GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
40
case 0x172:
17
GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
41
case 0x173:
18
+ GET_FEATURE(ARM_FEATURE_V8_FP16,
42
- if (b1 >= 2) {
19
+ ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
43
- goto unknown_op;
20
#undef GET_FEATURE
44
- }
21
45
val = x86_ldub_code(env, s);
22
return hwcaps;
46
if (is_xmm) {
47
tcg_gen_movi_tl(s->T0, val);
48
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
49
offsetof(CPUX86State, mmx_t0.MMX_L(1)));
50
op1_offset = offsetof(CPUX86State,mmx_t0);
51
}
52
+ assert(b1 < 2);
53
sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
54
(((modrm >> 3)) & 7)][b1];
55
if (!sse_fn_epp) {
56
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
57
rm = modrm & 7;
58
reg = ((modrm >> 3) & 7) | REX_R(s);
59
mod = (modrm >> 6) & 3;
60
- if (b1 >= 2) {
61
- goto unknown_op;
62
- }
63
64
+ assert(b1 < 2);
65
sse_fn_epp = sse_op_table6[b].op[b1];
66
if (!sse_fn_epp) {
67
goto unknown_op;
68
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
69
rm = modrm & 7;
70
reg = ((modrm >> 3) & 7) | REX_R(s);
71
mod = (modrm >> 6) & 3;
72
- if (b1 >= 2) {
73
- goto unknown_op;
74
- }
75
76
+ assert(b1 < 2);
77
sse_fn_eppi = sse_op_table7[b].op[b1];
78
if (!sse_fn_eppi) {
79
goto unknown_op;
23
--
80
--
24
2.16.2
81
2.25.1
25
82
26
83
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
2
4
3
This is the initial decode skeleton for the Advanced SIMD three same
5
include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
4
instruction group.
6
In fact, the include is not required at all, so we can just drop it
7
from both files.
5
8
6
The fprintf is purely to aid debugging as the additional instructions
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
are added. It will be removed once the group is complete.
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
13
---
14
include/hw/i386/microvm.h | 1 -
15
include/hw/i386/x86.h | 1 -
16
2 files changed, 2 deletions(-)
8
17
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
18
diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180227143852.11175-9-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
15
1 file changed, 73 insertions(+)
16
17
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-a64.c
20
--- a/include/hw/i386/microvm.h
20
+++ b/target/arm/translate-a64.c
21
+++ b/include/hw/i386/microvm.h
21
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
22
@@ -XXX,XX +XXX,XX @@
22
}
23
#ifndef HW_I386_MICROVM_H
23
}
24
#define HW_I386_MICROVM_H
24
25
25
+/*
26
-#include "qemu-common.h"
26
+ * Advanced SIMD three same (ARMv8.2 FP16 variants)
27
#include "exec/hwaddr.h"
27
+ *
28
#include "qemu/notify.h"
28
+ * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
29
29
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
30
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
30
+ * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
31
index XXXXXXX..XXXXXXX 100644
31
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
32
--- a/include/hw/i386/x86.h
32
+ *
33
+++ b/include/hw/i386/x86.h
33
+ * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
34
@@ -XXX,XX +XXX,XX @@
34
+ * (register), FACGE, FABD, FCMGT (register) and FACGT.
35
#ifndef HW_I386_X86_H
35
+ *
36
#define HW_I386_X86_H
36
+ */
37
37
+static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
38
-#include "qemu-common.h"
38
+{
39
#include "exec/hwaddr.h"
39
+ int opcode, fpopcode;
40
#include "qemu/notify.h"
40
+ int is_q, u, a, rm, rn, rd;
41
+ int datasize, elements;
42
+ int pass;
43
+ TCGv_ptr fpst;
44
+
45
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
46
+ unallocated_encoding(s);
47
+ return;
48
+ }
49
+
50
+ if (!fp_access_check(s)) {
51
+ return;
52
+ }
53
+
54
+ /* For these floating point ops, the U, a and opcode bits
55
+ * together indicate the operation.
56
+ */
57
+ opcode = extract32(insn, 11, 3);
58
+ u = extract32(insn, 29, 1);
59
+ a = extract32(insn, 23, 1);
60
+ is_q = extract32(insn, 30, 1);
61
+ rm = extract32(insn, 16, 5);
62
+ rn = extract32(insn, 5, 5);
63
+ rd = extract32(insn, 0, 5);
64
+
65
+ fpopcode = opcode | (a << 3) | (u << 4);
66
+ datasize = is_q ? 128 : 64;
67
+ elements = datasize / 16;
68
+
69
+ fpst = get_fpstatus_ptr(true);
70
+
71
+ for (pass = 0; pass < elements; pass++) {
72
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
73
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
74
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
75
+
76
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
77
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
78
+
79
+ switch (fpopcode) {
80
+ default:
81
+ fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
82
+ __func__, insn, fpopcode, s->pc);
83
+ g_assert_not_reached();
84
+ }
85
+
86
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
87
+ tcg_temp_free_i32(tcg_res);
88
+ tcg_temp_free_i32(tcg_op1);
89
+ tcg_temp_free_i32(tcg_op2);
90
+ }
91
+
92
+ tcg_temp_free_ptr(fpst);
93
+
94
+ clear_vec_high(s, is_q, rd);
95
+}
96
+
97
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
98
int size, int rn, int rd)
99
{
100
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
101
{ 0xce000000, 0xff808000, disas_crypto_four_reg },
102
{ 0xce800000, 0xffe00000, disas_crypto_xar },
103
{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
104
+ { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
105
{ 0x00000000, 0x00000000, NULL }
106
};
107
41
108
--
42
--
109
2.16.2
43
2.25.1
110
44
111
45
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
2
4
3
Ensure that the post write hook is called during reset. This allows us
5
Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
4
to rely on the post write functions instead of having to call them from
6
the declaration of cpu_exec_step_atomic().
5
the reset() function.
6
7
7
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
11
---
13
---
12
include/hw/register.h | 6 +++---
14
target/hexagon/cpu.h | 1 -
13
hw/core/register.c | 8 ++++++++
15
linux-user/hexagon/cpu_loop.c | 1 +
14
2 files changed, 11 insertions(+), 3 deletions(-)
16
2 files changed, 1 insertion(+), 1 deletion(-)
15
17
16
diff --git a/include/hw/register.h b/include/hw/register.h
18
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/register.h
20
--- a/target/hexagon/cpu.h
19
+++ b/include/hw/register.h
21
+++ b/target/hexagon/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct RegisterInfoArray RegisterInfoArray;
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState;
21
* immediately before the actual write. The returned value is what is written,
23
22
* giving the handler a chance to modify the written value.
24
#include "fpu/softfloat-types.h"
23
* @post_write: Post write callback. Passed the written value. Most write side
25
24
- * effects should be implemented here.
26
-#include "qemu-common.h"
25
+ * effects should be implemented here. This is called during device reset.
27
#include "exec/cpu-defs.h"
26
*
28
#include "hex_regs.h"
27
* @post_read: Post read callback. Passes the value that is about to be returned
29
#include "mmvec/mmvec.h"
28
* for a read. The return value from this function is what is ultimately read,
30
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
31
index XXXXXXX..XXXXXXX 100644
30
bool debug);
32
--- a/linux-user/hexagon/cpu_loop.c
31
33
+++ b/linux-user/hexagon/cpu_loop.c
32
/**
34
@@ -XXX,XX +XXX,XX @@
33
- * reset a register
34
- * @reg: register to reset
35
+ * Resets a register. This will also call the post_write hook if it exists.
36
+ * @reg: The register to reset.
37
*/
35
*/
38
36
39
void register_reset(RegisterInfo *reg);
37
#include "qemu/osdep.h"
40
diff --git a/hw/core/register.c b/hw/core/register.c
38
+#include "qemu-common.h"
41
index XXXXXXX..XXXXXXX 100644
39
#include "qemu.h"
42
--- a/hw/core/register.c
40
#include "user-internals.h"
43
+++ b/hw/core/register.c
41
#include "cpu_loop-common.h"
44
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
45
46
void register_reset(RegisterInfo *reg)
47
{
48
+ const RegisterAccessInfo *ac;
49
+
50
g_assert(reg);
51
52
if (!reg->data || !reg->access) {
53
return;
54
}
55
56
+ ac = reg->access;
57
+
58
register_write_val(reg, reg->access->reset);
59
+
60
+ if (ac->post_write) {
61
+ ac->post_write(reg, reg->access->reset);
62
+ }
63
}
64
65
void register_init(RegisterInfo *reg)
66
--
42
--
67
2.16.2
43
2.25.1
68
44
69
45
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
2
4
3
We do implement all the opcodes.
5
Nothing actually relies on target/rx/cpu.h including it, so we can
6
just drop the include.
4
7
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180227143852.11175-8-alex.bennee@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
12
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
13
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
9
---
14
---
10
target/arm/translate-a64.c | 3 +--
15
target/rx/cpu.h | 1 -
11
1 file changed, 1 insertion(+), 2 deletions(-)
16
1 file changed, 1 deletion(-)
12
17
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
20
--- a/target/rx/cpu.h
16
+++ b/target/arm/translate-a64.c
21
+++ b/target/rx/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
22
@@ -XXX,XX +XXX,XX @@
18
/* Handle 64x64->64 opcodes which are shared between the scalar
23
#define RX_CPU_H
19
* and vector 3-same groups. We cover every opcode where size == 3
24
20
* is valid in either the three-reg-same (integer, not pairwise)
25
#include "qemu/bitops.h"
21
- * or scalar-three-reg-same groups. (Some opcodes are not yet
26
-#include "qemu-common.h"
22
- * implemented.)
27
#include "hw/registerfields.h"
23
+ * or scalar-three-reg-same groups.
28
#include "cpu-qom.h"
24
*/
25
TCGCond cond;
26
29
27
--
30
--
28
2.16.2
31
2.25.1
29
32
30
33
diff view generated by jsdifflib
1
From: Linus Walleij <linus.walleij@linaro.org>
1
A lot of C files in hw/arm include qemu-common.h when they don't
2
need anything from it. Drop the include lines.
2
3
3
This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
4
omap1.c, pxa2xx.c and strongarm.c retain the include because they
4
Versatile Express machine, and selects the two I2C devices necessary
5
use it for the prototype of qemu_get_timedate().
5
in the arm-softmmu.mak configuration so everything will build
6
smoothly.
7
6
8
I am implementing proper handling of the graphics in the Linux
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
kernel and adding proper emulation of SiI9022 and EDID makes the
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
driver probe as nicely as before, retrieving the resolutions
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
supported by the "QEMU monitor" and overall just working nice.
10
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
11
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
12
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
13
---
14
hw/arm/boot.c | 1 -
15
hw/arm/digic_boards.c | 1 -
16
hw/arm/highbank.c | 1 -
17
hw/arm/npcm7xx_boards.c | 1 -
18
hw/arm/sbsa-ref.c | 1 -
19
hw/arm/stm32f405_soc.c | 1 -
20
hw/arm/vexpress.c | 1 -
21
hw/arm/virt.c | 1 -
22
8 files changed, 8 deletions(-)
12
23
13
Cc: Peter Maydell <peter.maydell@linaro.org>
24
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
14
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
25
index XXXXXXX..XXXXXXX 100644
15
Message-id: 20180227104903.21353-6-linus.walleij@linaro.org
26
--- a/hw/arm/boot.c
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
+++ b/hw/arm/boot.c
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
@@ -XXX,XX +XXX,XX @@
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
*/
19
---
30
20
hw/arm/vexpress.c | 6 +++++-
31
#include "qemu/osdep.h"
21
default-configs/arm-softmmu.mak | 2 ++
32
-#include "qemu-common.h"
22
2 files changed, 7 insertions(+), 1 deletion(-)
33
#include "qemu/datadir.h"
23
34
#include "qemu/error-report.h"
35
#include "qapi/error.h"
36
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/digic_boards.c
39
+++ b/hw/arm/digic_boards.c
40
@@ -XXX,XX +XXX,XX @@
41
42
#include "qemu/osdep.h"
43
#include "qapi/error.h"
44
-#include "qemu-common.h"
45
#include "qemu/datadir.h"
46
#include "hw/boards.h"
47
#include "qemu/error-report.h"
48
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/highbank.c
51
+++ b/hw/arm/highbank.c
52
@@ -XXX,XX +XXX,XX @@
53
*/
54
55
#include "qemu/osdep.h"
56
-#include "qemu-common.h"
57
#include "qemu/datadir.h"
58
#include "qapi/error.h"
59
#include "hw/sysbus.h"
60
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/arm/npcm7xx_boards.c
63
+++ b/hw/arm/npcm7xx_boards.c
64
@@ -XXX,XX +XXX,XX @@
65
#include "hw/qdev-core.h"
66
#include "hw/qdev-properties.h"
67
#include "qapi/error.h"
68
-#include "qemu-common.h"
69
#include "qemu/datadir.h"
70
#include "qemu/units.h"
71
#include "sysemu/blockdev.h"
72
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/arm/sbsa-ref.c
75
+++ b/hw/arm/sbsa-ref.c
76
@@ -XXX,XX +XXX,XX @@
77
*/
78
79
#include "qemu/osdep.h"
80
-#include "qemu-common.h"
81
#include "qemu/datadir.h"
82
#include "qapi/error.h"
83
#include "qemu/error-report.h"
84
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/stm32f405_soc.c
87
+++ b/hw/arm/stm32f405_soc.c
88
@@ -XXX,XX +XXX,XX @@
89
90
#include "qemu/osdep.h"
91
#include "qapi/error.h"
92
-#include "qemu-common.h"
93
#include "exec/address-spaces.h"
94
#include "sysemu/sysemu.h"
95
#include "hw/arm/stm32f405_soc.h"
24
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
96
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
25
index XXXXXXX..XXXXXXX 100644
97
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/vexpress.c
98
--- a/hw/arm/vexpress.c
27
+++ b/hw/arm/vexpress.c
99
+++ b/hw/arm/vexpress.c
28
@@ -XXX,XX +XXX,XX @@
100
@@ -XXX,XX +XXX,XX @@
29
#include "hw/arm/arm.h"
101
30
#include "hw/arm/primecell.h"
102
#include "qemu/osdep.h"
31
#include "hw/devices.h"
103
#include "qapi/error.h"
32
+#include "hw/i2c/i2c.h"
104
-#include "qemu-common.h"
33
#include "net/net.h"
105
#include "qemu/datadir.h"
34
#include "sysemu/sysemu.h"
106
#include "cpu.h"
35
#include "hw/boards.h"
107
#include "hw/sysbus.h"
36
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
108
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
37
uint32_t sys_id;
38
DriveInfo *dinfo;
39
pflash_t *pflash0;
40
+ I2CBus *i2c;
41
ram_addr_t vram_size, sram_size;
42
MemoryRegion *sysmem = get_system_memory();
43
MemoryRegion *vram = g_new(MemoryRegion, 1);
44
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
45
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
46
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
47
48
- /* VE_SERIALDVI: not modelled */
49
+ dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
50
+ i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
51
+ i2c_create_slave(i2c, "sii9022", 0x39);
52
53
sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
54
55
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
56
index XXXXXXX..XXXXXXX 100644
109
index XXXXXXX..XXXXXXX 100644
57
--- a/default-configs/arm-softmmu.mak
110
--- a/hw/arm/virt.c
58
+++ b/default-configs/arm-softmmu.mak
111
+++ b/hw/arm/virt.c
59
@@ -XXX,XX +XXX,XX @@ CONFIG_STELLARIS_INPUT=y
112
@@ -XXX,XX +XXX,XX @@
60
CONFIG_STELLARIS_ENET=y
113
*/
61
CONFIG_SSD0303=y
114
62
CONFIG_SSD0323=y
115
#include "qemu/osdep.h"
63
+CONFIG_DDC=y
116
-#include "qemu-common.h"
64
+CONFIG_SII9022=y
117
#include "qemu/datadir.h"
65
CONFIG_ADS7846=y
118
#include "qemu/units.h"
66
CONFIG_MAX111X=y
119
#include "qemu/option.h"
67
CONFIG_SSI=y
68
--
120
--
69
2.16.2
121
2.25.1
70
122
71
123
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The calculation of the length of TLB range invalidate operations
2
in tlbi_aa64_range_get_length() is incorrect in two ways:
3
* the NUM field is 5 bits, but we read only 4 bits
4
* we miscalculate the page_shift value, because of an
5
off-by-one error:
6
TG 0b00 is invalid
7
TG 0b01 is 4K granule size == 4096 == 2^12
8
TG 0b10 is 16K granule size == 16384 == 2^14
9
TG 0b11 is 64K granule size == 65536 == 2^16
10
so page_shift should be (TG - 1) * 2 + 12
2
11
3
I've re-factored the handle_simd_intfp_conv helper to properly handle
12
Thanks to the bug report submitter Cha HyunSoo for identifying
4
half-precision as well as call plain conversion helpers when we are
13
both these errors.
5
not doing fixed point conversion.
6
14
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
15
Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
11
---
22
---
12
target/arm/helper.h | 10 ++++
23
target/arm/helper.c | 6 +++---
13
target/arm/helper.c | 4 ++
24
1 file changed, 3 insertions(+), 3 deletions(-)
14
target/arm/translate-a64.c | 122 ++++++++++++++++++++++++++++++++++-----------
15
3 files changed, 108 insertions(+), 28 deletions(-)
16
25
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.h
20
+++ b/target/arm/helper.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
22
DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
23
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
24
25
+DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
26
DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
27
DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
28
+DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
29
DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
30
DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
31
32
+DEF_HELPER_2(vfp_touih, i32, f16, ptr)
33
DEF_HELPER_2(vfp_touis, i32, f32, ptr)
34
DEF_HELPER_2(vfp_touid, i32, f64, ptr)
35
+DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
36
DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
37
DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
38
+DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
39
DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
40
DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
41
+DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
42
DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
43
DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
44
45
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
46
DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
47
DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
48
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
49
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
50
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
51
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
52
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
53
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
55
DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
56
DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
57
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
58
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
59
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
60
61
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
62
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
63
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
diff --git a/target/arm/helper.c b/target/arm/helper.c
64
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/helper.c
28
--- a/target/arm/helper.c
66
+++ b/target/arm/helper.c
29
+++ b/target/arm/helper.c
67
@@ -XXX,XX +XXX,XX @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
30
@@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
68
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
31
uint64_t exponent;
69
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
32
uint64_t length;
70
33
71
+FLOAT_CONVS(si, h, 16, )
34
- num = extract64(value, 39, 4);
72
FLOAT_CONVS(si, s, 32, )
35
+ num = extract64(value, 39, 5);
73
FLOAT_CONVS(si, d, 64, )
36
scale = extract64(value, 44, 2);
74
+FLOAT_CONVS(ui, h, 16, u)
37
page_size_granule = extract64(value, 46, 2);
75
FLOAT_CONVS(ui, s, 32, u)
38
76
FLOAT_CONVS(ui, d, 64, u)
39
- page_shift = page_size_granule * 2 + 12;
77
40
-
78
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
41
if (page_size_granule == 0) {
79
VFP_CONV_FIX(uh, s, 32, 32, uint16)
42
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
80
VFP_CONV_FIX(ul, s, 32, 32, uint32)
43
page_size_granule);
81
VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
44
return 0;
82
+VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
45
}
83
+VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
46
84
#undef VFP_CONV_FIX
47
+ page_shift = (page_size_granule - 1) * 2 + 12;
85
#undef VFP_CONV_FIX_FLOAT
86
#undef VFP_CONV_FLOAT_FIX_ROUND
87
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/translate-a64.c
90
+++ b/target/arm/translate-a64.c
91
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
92
int elements, int is_signed,
93
int fracbits, int size)
94
{
95
- bool is_double = size == 3 ? true : false;
96
- TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
97
- TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
98
- TCGv_i64 tcg_int = tcg_temp_new_i64();
99
+ TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
100
+ TCGv_i32 tcg_shift = NULL;
101
+
48
+
102
TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
49
exponent = (5 * scale) + 1;
103
int pass;
50
length = (num + 1) << (exponent + page_shift);
104
51
105
- for (pass = 0; pass < elements; pass++) {
106
- read_vec_element(s, tcg_int, rn, pass, mop);
107
+ if (fracbits || size == MO_64) {
108
+ tcg_shift = tcg_const_i32(fracbits);
109
+ }
110
+
111
+ if (size == MO_64) {
112
+ TCGv_i64 tcg_int64 = tcg_temp_new_i64();
113
+ TCGv_i64 tcg_double = tcg_temp_new_i64();
114
+
115
+ for (pass = 0; pass < elements; pass++) {
116
+ read_vec_element(s, tcg_int64, rn, pass, mop);
117
118
- if (is_double) {
119
- TCGv_i64 tcg_double = tcg_temp_new_i64();
120
if (is_signed) {
121
- gen_helper_vfp_sqtod(tcg_double, tcg_int,
122
+ gen_helper_vfp_sqtod(tcg_double, tcg_int64,
123
tcg_shift, tcg_fpst);
124
} else {
125
- gen_helper_vfp_uqtod(tcg_double, tcg_int,
126
+ gen_helper_vfp_uqtod(tcg_double, tcg_int64,
127
tcg_shift, tcg_fpst);
128
}
129
if (elements == 1) {
130
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
131
} else {
132
write_vec_element(s, tcg_double, rd, pass, MO_64);
133
}
134
- tcg_temp_free_i64(tcg_double);
135
- } else {
136
- TCGv_i32 tcg_single = tcg_temp_new_i32();
137
- if (is_signed) {
138
- gen_helper_vfp_sqtos(tcg_single, tcg_int,
139
- tcg_shift, tcg_fpst);
140
- } else {
141
- gen_helper_vfp_uqtos(tcg_single, tcg_int,
142
- tcg_shift, tcg_fpst);
143
- }
144
- if (elements == 1) {
145
- write_fp_sreg(s, rd, tcg_single);
146
- } else {
147
- write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
148
- }
149
- tcg_temp_free_i32(tcg_single);
150
}
151
+
152
+ tcg_temp_free_i64(tcg_int64);
153
+ tcg_temp_free_i64(tcg_double);
154
+
155
+ } else {
156
+ TCGv_i32 tcg_int32 = tcg_temp_new_i32();
157
+ TCGv_i32 tcg_float = tcg_temp_new_i32();
158
+
159
+ for (pass = 0; pass < elements; pass++) {
160
+ read_vec_element_i32(s, tcg_int32, rn, pass, mop);
161
+
162
+ switch (size) {
163
+ case MO_32:
164
+ if (fracbits) {
165
+ if (is_signed) {
166
+ gen_helper_vfp_sltos(tcg_float, tcg_int32,
167
+ tcg_shift, tcg_fpst);
168
+ } else {
169
+ gen_helper_vfp_ultos(tcg_float, tcg_int32,
170
+ tcg_shift, tcg_fpst);
171
+ }
172
+ } else {
173
+ if (is_signed) {
174
+ gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
175
+ } else {
176
+ gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
177
+ }
178
+ }
179
+ break;
180
+ case MO_16:
181
+ if (fracbits) {
182
+ if (is_signed) {
183
+ gen_helper_vfp_sltoh(tcg_float, tcg_int32,
184
+ tcg_shift, tcg_fpst);
185
+ } else {
186
+ gen_helper_vfp_ultoh(tcg_float, tcg_int32,
187
+ tcg_shift, tcg_fpst);
188
+ }
189
+ } else {
190
+ if (is_signed) {
191
+ gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
192
+ } else {
193
+ gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
194
+ }
195
+ }
196
+ break;
197
+ default:
198
+ g_assert_not_reached();
199
+ }
200
+
201
+ if (elements == 1) {
202
+ write_fp_sreg(s, rd, tcg_float);
203
+ } else {
204
+ write_vec_element_i32(s, tcg_float, rd, pass, size);
205
+ }
206
+ }
207
+
208
+ tcg_temp_free_i32(tcg_int32);
209
+ tcg_temp_free_i32(tcg_float);
210
}
211
212
- tcg_temp_free_i64(tcg_int);
213
tcg_temp_free_ptr(tcg_fpst);
214
- tcg_temp_free_i32(tcg_shift);
215
+ if (tcg_shift) {
216
+ tcg_temp_free_i32(tcg_shift);
217
+ }
218
219
clear_vec_high(s, elements << size == 16, rd);
220
}
221
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
222
rn = extract32(insn, 5, 5);
223
224
switch (fpop) {
225
+ case 0x1d: /* SCVTF */
226
+ case 0x5d: /* UCVTF */
227
+ {
228
+ int elements;
229
+
230
+ if (is_scalar) {
231
+ elements = 1;
232
+ } else {
233
+ elements = (is_q ? 8 : 4);
234
+ }
235
+
236
+ if (!fp_access_check(s)) {
237
+ return;
238
+ }
239
+ handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
240
+ return;
241
+ }
242
break;
243
case 0x2c: /* FCMGT (zero) */
244
case 0x2d: /* FCMEQ (zero) */
245
--
52
--
246
2.16.2
53
2.25.1
247
54
248
55
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
This implements the half-precision variants of the across vector
3
The rx_active boolean change to true should always trigger a try_read
4
reduction operations. This involves a re-factor of the reduction code
4
call that flushes the queue.
5
which more closely matches the ARM ARM order (and handles 8 element
6
reductions).
7
5
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Patrick Venture <venture@google.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
8
Message-id: 20211203221002.1719306-1-venture@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/helper-a64.h | 4 ++
11
hw/net/npcm7xx_emc.c | 18 ++++++++----------
14
target/arm/helper-a64.c | 18 ++++++
12
1 file changed, 8 insertions(+), 10 deletions(-)
15
target/arm/translate-a64.c | 140 ++++++++++++++++++++++++++++-----------------
16
3 files changed, 109 insertions(+), 53 deletions(-)
17
13
18
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
14
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-a64.h
16
--- a/hw/net/npcm7xx_emc.c
21
+++ b/target/arm/helper-a64.h
17
+++ b/hw/net/npcm7xx_emc.c
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
18
@@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
23
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
19
emc_set_mista(emc, mista_flag);
24
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
25
i64, env, i64, i64, i64)
26
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
27
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
28
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
29
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
30
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper-a64.c
33
+++ b/target/arm/helper-a64.c
34
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
35
{
36
return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
37
}
20
}
38
+
21
39
+/*
22
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
40
+ * AdvSIMD half-precision
23
+{
41
+ */
24
+ emc->rx_active = true;
42
+
25
+ qemu_flush_queued_packets(qemu_get_queue(emc->nic));
43
+#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
44
+
45
+#define ADVSIMD_HALFOP(name) \
46
+float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
47
+{ \
48
+ float_status *fpst = fpstp; \
49
+ return float16_ ## name(a, b, fpst); \
50
+}
26
+}
51
+
27
+
52
+ADVSIMD_HALFOP(min)
28
static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
53
+ADVSIMD_HALFOP(max)
29
const NPCM7xxEMCTxDesc *tx_desc,
54
+ADVSIMD_HALFOP(minnum)
30
uint32_t desc_addr)
55
+ADVSIMD_HALFOP(maxnum)
31
@@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
56
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
return len;
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/translate-a64.c
59
+++ b/target/arm/translate-a64.c
60
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
61
tcg_temp_free_i64(tcg_resh);
62
}
33
}
63
34
64
-static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
35
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
65
- int opc, bool is_min, TCGv_ptr fpst)
36
-{
66
+/*
37
- if (emc_can_receive(qemu_get_queue(emc->nic))) {
67
+ * do_reduction_op helper
38
- qemu_flush_queued_packets(qemu_get_queue(emc->nic));
68
+ *
39
- }
69
+ * This mirrors the Reduce() pseudocode in the ARM ARM. It is
40
-}
70
+ * important for correct NaN propagation that we do these
41
-
71
+ * operations in exactly the order specified by the pseudocode.
42
static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
72
+ *
73
+ * This is a recursive function, TCG temps should be freed by the
74
+ * calling function once it is done with the values.
75
+ */
76
+static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
77
+ int esize, int size, int vmap, TCGv_ptr fpst)
78
{
43
{
79
- /* Helper function for disas_simd_across_lanes: do a single precision
44
NPCM7xxEMCState *emc = opaque;
80
- * min/max operation on the specified two inputs,
45
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
81
- * and return the result in tcg_elt1.
46
emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
82
- */
83
- if (opc == 0xc) {
84
- if (is_min) {
85
- gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
86
- } else {
87
- gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
88
- }
89
+ if (esize == size) {
90
+ int element;
91
+ TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
92
+ TCGv_i32 tcg_elem;
93
+
94
+ /* We should have one register left here */
95
+ assert(ctpop8(vmap) == 1);
96
+ element = ctz32(vmap);
97
+ assert(element < 8);
98
+
99
+ tcg_elem = tcg_temp_new_i32();
100
+ read_vec_element_i32(s, tcg_elem, rn, element, msize);
101
+ return tcg_elem;
102
} else {
103
- assert(opc == 0xf);
104
- if (is_min) {
105
- gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
106
- } else {
107
- gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
108
+ int bits = size / 2;
109
+ int shift = ctpop8(vmap) / 2;
110
+ int vmap_lo = (vmap >> shift) & vmap;
111
+ int vmap_hi = (vmap & ~vmap_lo);
112
+ TCGv_i32 tcg_hi, tcg_lo, tcg_res;
113
+
114
+ tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
115
+ tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
116
+ tcg_res = tcg_temp_new_i32();
117
+
118
+ switch (fpopcode) {
119
+ case 0x0c: /* fmaxnmv half-precision */
120
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
121
+ break;
122
+ case 0x0f: /* fmaxv half-precision */
123
+ gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
124
+ break;
125
+ case 0x1c: /* fminnmv half-precision */
126
+ gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
127
+ break;
128
+ case 0x1f: /* fminv half-precision */
129
+ gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
130
+ break;
131
+ case 0x2c: /* fmaxnmv */
132
+ gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
133
+ break;
134
+ case 0x2f: /* fmaxv */
135
+ gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
136
+ break;
137
+ case 0x3c: /* fminnmv */
138
+ gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
139
+ break;
140
+ case 0x3f: /* fminv */
141
+ gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
142
+ break;
143
+ default:
144
+ g_assert_not_reached();
145
}
47
}
146
+
48
if (value & REG_MCMDR_RXON) {
147
+ tcg_temp_free_i32(tcg_hi);
49
- emc->rx_active = true;
148
+ tcg_temp_free_i32(tcg_lo);
50
+ emc_enable_rx_and_flush(emc);
149
+ return tcg_res;
51
} else {
150
}
52
emc_halt_rx(emc, 0);
151
}
53
}
152
54
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
153
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
154
break;
55
break;
155
case 0xc: /* FMAXNMV, FMINNMV */
56
case REG_RSDR:
156
case 0xf: /* FMAXV, FMINV */
57
if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
157
- if (!is_u || !is_q || extract32(size, 0, 1)) {
58
- emc->rx_active = true;
158
- unallocated_encoding(s);
59
- emc_try_receive_next_packet(emc);
159
- return;
60
+ emc_enable_rx_and_flush(emc);
160
- }
61
}
161
- /* Bit 1 of size field encodes min vs max, and actual size is always
162
- * 32 bits: adjust the size variable so following code can rely on it
163
+ /* Bit 1 of size field encodes min vs max and the actual size
164
+ * depends on the encoding of the U bit. If not set (and FP16
165
+ * enabled) then we do half-precision float instead of single
166
+ * precision.
167
*/
168
is_min = extract32(size, 1, 1);
169
is_fp = true;
170
- size = 2;
171
+ if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
172
+ size = 1;
173
+ } else if (!is_u || !is_q || extract32(size, 0, 1)) {
174
+ unallocated_encoding(s);
175
+ return;
176
+ } else {
177
+ size = 2;
178
+ }
179
break;
62
break;
180
default:
63
case REG_MIIDA:
181
unallocated_encoding(s);
182
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
183
184
}
185
} else {
186
- /* Floating point ops which work on 32 bit (single) intermediates.
187
+ /* Floating point vector reduction ops which work across 32
188
+ * bit (single) or 16 bit (half-precision) intermediates.
189
* Note that correct NaN propagation requires that we do these
190
* operations in exactly the order specified by the pseudocode.
191
*/
192
- TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
193
- TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
194
- TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
195
- TCGv_ptr fpst = get_fpstatus_ptr(false);
196
-
197
- assert(esize == 32);
198
- assert(elements == 4);
199
-
200
- read_vec_element(s, tcg_elt, rn, 0, MO_32);
201
- tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
202
- read_vec_element(s, tcg_elt, rn, 1, MO_32);
203
- tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
204
-
205
- do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
206
-
207
- read_vec_element(s, tcg_elt, rn, 2, MO_32);
208
- tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
209
- read_vec_element(s, tcg_elt, rn, 3, MO_32);
210
- tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
211
-
212
- do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
213
-
214
- do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
215
-
216
- tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
217
- tcg_temp_free_i32(tcg_elt1);
218
- tcg_temp_free_i32(tcg_elt2);
219
- tcg_temp_free_i32(tcg_elt3);
220
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
221
+ int fpopcode = opcode | is_min << 4 | is_u << 5;
222
+ int vmap = (1 << elements) - 1;
223
+ TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
224
+ (is_q ? 128 : 64), vmap, fpst);
225
+ tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
226
+ tcg_temp_free_i32(tcg_res32);
227
tcg_temp_free_ptr(fpst);
228
}
229
230
--
64
--
231
2.16.2
65
2.25.1
232
66
233
67
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.
3
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
4
table.
4
5
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Acked-by: Igor Mammedov <imammedo@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
8
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++----------------
12
hw/arm/virt-acpi-build.c | 7 +++++++
11
1 file changed, 133 insertions(+), 75 deletions(-)
13
hw/arm/Kconfig | 1 +
14
2 files changed, 8 insertions(+)
12
15
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
18
--- a/hw/arm/virt-acpi-build.c
16
+++ b/target/arm/translate-a64.c
19
+++ b/hw/arm/virt-acpi-build.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@
18
int datasize, elements;
21
#include "kvm_arm.h"
19
int pass;
22
#include "migration/vmstate.h"
20
TCGv_ptr fpst;
23
#include "hw/acpi/ghes.h"
21
+ bool pairwise = false;
24
+#include "hw/acpi/viot.h"
22
25
23
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
26
#define ARM_SPI_BASE 32
24
unallocated_encoding(s);
27
25
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
28
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
26
datasize = is_q ? 128 : 64;
29
}
27
elements = datasize / 16;
30
#endif
28
31
29
+ switch (fpopcode) {
32
+ if (vms->iommu == VIRT_IOMMU_VIRTIO) {
30
+ case 0x10: /* FMAXNMP */
33
+ acpi_add_table(table_offsets, tables_blob);
31
+ case 0x12: /* FADDP */
34
+ build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
32
+ case 0x16: /* FMAXP */
35
+ vms->oem_id, vms->oem_table_id);
33
+ case 0x18: /* FMINNMP */
34
+ case 0x1e: /* FMINP */
35
+ pairwise = true;
36
+ break;
37
+ }
36
+ }
38
+
37
+
39
fpst = get_fpstatus_ptr(true);
38
/* XSDT is pointed to by RSDP */
40
39
xsdt = tables_blob->len;
41
- for (pass = 0; pass < elements; pass++) {
40
build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
42
+ if (pairwise) {
41
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
43
+ int maxpass = is_q ? 8 : 4;
42
index XXXXXXX..XXXXXXX 100644
44
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
43
--- a/hw/arm/Kconfig
45
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
44
+++ b/hw/arm/Kconfig
46
- TCGv_i32 tcg_res = tcg_temp_new_i32();
45
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
47
+ TCGv_i32 tcg_res[8];
46
select DIMM
48
47
select ACPI_HW_REDUCED
49
- read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
48
select ACPI_APEI
50
- read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
49
+ select ACPI_VIOT
51
+ for (pass = 0; pass < maxpass; pass++) {
50
52
+ int passreg = pass < (maxpass / 2) ? rn : rm;
51
config CHEETAH
53
+ int passelt = (pass << 1) & (maxpass - 1);
52
bool
54
55
- switch (fpopcode) {
56
- case 0x0: /* FMAXNM */
57
- gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
- break;
59
- case 0x1: /* FMLA */
60
- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
61
- gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
62
- fpst);
63
- break;
64
- case 0x2: /* FADD */
65
- gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
66
- break;
67
- case 0x3: /* FMULX */
68
- gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
69
- break;
70
- case 0x4: /* FCMEQ */
71
- gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
72
- break;
73
- case 0x6: /* FMAX */
74
- gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
75
- break;
76
- case 0x7: /* FRECPS */
77
- gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
78
- break;
79
- case 0x8: /* FMINNM */
80
- gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
81
- break;
82
- case 0x9: /* FMLS */
83
- /* As usual for ARM, separate negation for fused multiply-add */
84
- tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
85
- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
86
- gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
87
- fpst);
88
- break;
89
- case 0xa: /* FSUB */
90
- gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
91
- break;
92
- case 0xe: /* FMIN */
93
- gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
94
- break;
95
- case 0xf: /* FRSQRTS */
96
- gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
97
- break;
98
- case 0x13: /* FMUL */
99
- gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
100
- break;
101
- case 0x14: /* FCMGE */
102
- gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
103
- break;
104
- case 0x15: /* FACGE */
105
- gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
106
- break;
107
- case 0x17: /* FDIV */
108
- gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
109
- break;
110
- case 0x1a: /* FABD */
111
- gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
112
- tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
113
- break;
114
- case 0x1c: /* FCMGT */
115
- gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
116
- break;
117
- case 0x1d: /* FACGT */
118
- gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
119
- break;
120
- default:
121
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
122
- __func__, insn, fpopcode, s->pc);
123
- g_assert_not_reached();
124
+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
125
+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
126
+ tcg_res[pass] = tcg_temp_new_i32();
127
+
128
+ switch (fpopcode) {
129
+ case 0x10: /* FMAXNMP */
130
+ gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
131
+ fpst);
132
+ break;
133
+ case 0x12: /* FADDP */
134
+ gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
135
+ break;
136
+ case 0x16: /* FMAXP */
137
+ gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
138
+ break;
139
+ case 0x18: /* FMINNMP */
140
+ gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
141
+ fpst);
142
+ break;
143
+ case 0x1e: /* FMINP */
144
+ gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
145
+ break;
146
+ default:
147
+ g_assert_not_reached();
148
+ }
149
+ }
150
+
151
+ for (pass = 0; pass < maxpass; pass++) {
152
+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
153
+ tcg_temp_free_i32(tcg_res[pass]);
154
}
155
156
- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
157
- tcg_temp_free_i32(tcg_res);
158
tcg_temp_free_i32(tcg_op1);
159
tcg_temp_free_i32(tcg_op2);
160
+
161
+ } else {
162
+ for (pass = 0; pass < elements; pass++) {
163
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
164
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
165
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
166
+
167
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
168
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
169
+
170
+ switch (fpopcode) {
171
+ case 0x0: /* FMAXNM */
172
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
173
+ break;
174
+ case 0x1: /* FMLA */
175
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
176
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
177
+ fpst);
178
+ break;
179
+ case 0x2: /* FADD */
180
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
181
+ break;
182
+ case 0x3: /* FMULX */
183
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
184
+ break;
185
+ case 0x4: /* FCMEQ */
186
+ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
187
+ break;
188
+ case 0x6: /* FMAX */
189
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
190
+ break;
191
+ case 0x7: /* FRECPS */
192
+ gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
193
+ break;
194
+ case 0x8: /* FMINNM */
195
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
196
+ break;
197
+ case 0x9: /* FMLS */
198
+ /* As usual for ARM, separate negation for fused multiply-add */
199
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
200
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
201
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
202
+ fpst);
203
+ break;
204
+ case 0xa: /* FSUB */
205
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
206
+ break;
207
+ case 0xe: /* FMIN */
208
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
209
+ break;
210
+ case 0xf: /* FRSQRTS */
211
+ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
212
+ break;
213
+ case 0x13: /* FMUL */
214
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
215
+ break;
216
+ case 0x14: /* FCMGE */
217
+ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
218
+ break;
219
+ case 0x15: /* FACGE */
220
+ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
221
+ break;
222
+ case 0x17: /* FDIV */
223
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
224
+ break;
225
+ case 0x1a: /* FABD */
226
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
227
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
228
+ break;
229
+ case 0x1c: /* FCMGT */
230
+ gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
231
+ break;
232
+ case 0x1d: /* FACGT */
233
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
234
+ break;
235
+ default:
236
+ fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
237
+ __func__, insn, fpopcode, s->pc);
238
+ g_assert_not_reached();
239
+ }
240
+
241
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
242
+ tcg_temp_free_i32(tcg_res);
243
+ tcg_temp_free_i32(tcg_op1);
244
+ tcg_temp_free_i32(tcg_op2);
245
+ }
246
}
247
248
tcg_temp_free_ptr(fpst);
249
--
53
--
250
2.16.2
54
2.25.1
251
55
252
56
diff view generated by jsdifflib
1
From: Linus Walleij <linus.walleij@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
The tx function of the DDC I2C slave emulation was returning 1
3
virtio-iommu is now supported with ACPI VIOT as well as device tree.
4
on all writes resulting in NACK in the I2C bus. Changing it to
4
Remove the restriction that prevents from instantiating a virtio-iommu
5
0 makes the DDC I2C work fine with bit-banged I2C such as the
5
device under ACPI.
6
versatile I2C.
7
6
8
I guess it was not affecting whatever I2C controller this was
7
Acked-by: Igor Mammedov <imammedo@redhat.com>
9
used with until now, but with the Versatile I2C it surely
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
does not work.
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
10
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
14
Message-id: 20180227104903.21353-4-linus.walleij@linaro.org
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
12
---
18
hw/i2c/i2c-ddc.c | 4 ++--
13
hw/arm/virt.c | 10 ++--------
19
1 file changed, 2 insertions(+), 2 deletions(-)
14
hw/virtio/virtio-iommu-pci.c | 12 ++----------
15
2 files changed, 4 insertions(+), 18 deletions(-)
20
16
21
diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/i2c/i2c-ddc.c
19
--- a/hw/arm/virt.c
24
+++ b/hw/i2c/i2c-ddc.c
20
+++ b/hw/arm/virt.c
25
@@ -XXX,XX +XXX,XX @@ static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
21
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
26
s->reg = data;
22
MachineClass *mc = MACHINE_GET_CLASS(machine);
27
s->firstbyte = false;
23
28
DPRINTF("[EDID] Written new pointer: %u\n", data);
24
if (device_is_dynamic_sysbus(mc, dev) ||
29
- return 1;
25
- (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
30
+ return 0;
26
+ object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
27
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
28
return HOTPLUG_HANDLER(machine);
31
}
29
}
32
30
- if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
33
/* Ignore all writes */
31
- VirtMachineState *vms = VIRT_MACHINE(machine);
34
s->reg++;
32
-
35
- return 1;
33
- if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
36
+ return 0;
34
- return HOTPLUG_HANDLER(machine);
35
- }
36
- }
37
return NULL;
37
}
38
}
38
39
39
static void i2c_ddc_init(Object *obj)
40
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/virtio-iommu-pci.c
43
+++ b/hw/virtio/virtio-iommu-pci.c
44
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
45
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
46
47
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
48
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
49
-
50
- error_setg(errp,
51
- "%s machine fails to create iommu-map device tree bindings",
52
- mc->name);
53
- error_append_hint(errp,
54
- "Check your machine implements a hotplug handler "
55
- "for the virtio-iommu-pci device\n");
56
- error_append_hint(errp, "Check the guest is booted without FW or with "
57
- "-no-acpi\n");
58
+ error_setg(errp, "Check your machine implements a hotplug handler "
59
+ "for the virtio-iommu-pci device");
60
return;
61
}
62
for (int i = 0; i < s->nb_reserved_regions; i++) {
40
--
63
--
41
2.16.2
64
2.25.1
42
65
43
66
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
This covers all the floating point convert operations.
3
We do not support instantiating multiple IOMMUs. Before adding a
4
virtio-iommu, check that no other IOMMU is present. This will detect
5
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
4
6
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
target/arm/helper-a64.h | 2 ++
14
hw/arm/virt.c | 5 +++++
11
target/arm/helper-a64.c | 32 +++++++++++++++++
15
1 file changed, 5 insertions(+)
12
target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++-
13
3 files changed, 118 insertions(+), 1 deletion(-)
14
16
15
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.h
19
--- a/hw/arm/virt.c
18
+++ b/target/arm/helper-a64.h
20
+++ b/hw/arm/virt.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
20
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
22
hwaddr db_start = 0, db_end = 0;
21
DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
23
char *resv_prop_str;
22
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
24
23
+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
25
+ if (vms->iommu != VIRT_IOMMU_NONE) {
24
+DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
26
+ error_setg(errp, "virt machine does not support multiple IOMMUs");
25
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
27
+ return;
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper-a64.c
28
+++ b/target/arm/helper-a64.c
29
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
30
31
return ret;
32
}
33
+
34
+/*
35
+ * Half-precision floating point conversion functions
36
+ *
37
+ * There are a multitude of conversion functions with various
38
+ * different rounding modes. This is dealt with by the calling code
39
+ * setting the mode appropriately before calling the helper.
40
+ */
41
+
42
+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
43
+{
44
+ float_status *fpst = fpstp;
45
+
46
+ /* Invalid if we are passed a NaN */
47
+ if (float16_is_any_nan(a)) {
48
+ float_raise(float_flag_invalid, fpst);
49
+ return 0;
50
+ }
51
+ return float16_to_int16(a, fpst);
52
+}
53
+
54
+uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
55
+{
56
+ float_status *fpst = fpstp;
57
+
58
+ /* Invalid if we are passed a NaN */
59
+ if (float16_is_any_nan(a)) {
60
+ float_raise(float_flag_invalid, fpst);
61
+ return 0;
62
+ }
63
+ return float16_to_uint16(a, fpst);
64
+}
65
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/translate-a64.c
68
+++ b/target/arm/translate-a64.c
69
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
70
only_in_vector = true;
71
/* current rounding mode */
72
break;
73
+ case 0x1a: /* FCVTNS */
74
+ need_rmode = true;
75
+ rmode = FPROUNDING_TIEEVEN;
76
+ break;
77
+ case 0x1b: /* FCVTMS */
78
+ need_rmode = true;
79
+ rmode = FPROUNDING_NEGINF;
80
+ break;
81
+ case 0x1c: /* FCVTAS */
82
+ need_rmode = true;
83
+ rmode = FPROUNDING_TIEAWAY;
84
+ break;
85
+ case 0x3a: /* FCVTPS */
86
+ need_rmode = true;
87
+ rmode = FPROUNDING_POSINF;
88
+ break;
89
+ case 0x3b: /* FCVTZS */
90
+ need_rmode = true;
91
+ rmode = FPROUNDING_ZERO;
92
+ break;
93
+ case 0x5a: /* FCVTNU */
94
+ need_rmode = true;
95
+ rmode = FPROUNDING_TIEEVEN;
96
+ break;
97
+ case 0x5b: /* FCVTMU */
98
+ need_rmode = true;
99
+ rmode = FPROUNDING_NEGINF;
100
+ break;
101
+ case 0x5c: /* FCVTAU */
102
+ need_rmode = true;
103
+ rmode = FPROUNDING_TIEAWAY;
104
+ break;
105
+ case 0x7a: /* FCVTPU */
106
+ need_rmode = true;
107
+ rmode = FPROUNDING_POSINF;
108
+ break;
109
+ case 0x7b: /* FCVTZU */
110
+ need_rmode = true;
111
+ rmode = FPROUNDING_ZERO;
112
+ break;
113
default:
114
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
115
g_assert_not_reached();
116
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
117
}
118
119
if (is_scalar) {
120
- /* no operations yet */
121
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
122
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
123
+
124
+ read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
125
+
126
+ switch (fpop) {
127
+ case 0x1a: /* FCVTNS */
128
+ case 0x1b: /* FCVTMS */
129
+ case 0x1c: /* FCVTAS */
130
+ case 0x3a: /* FCVTPS */
131
+ case 0x3b: /* FCVTZS */
132
+ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
133
+ break;
134
+ case 0x5a: /* FCVTNU */
135
+ case 0x5b: /* FCVTMU */
136
+ case 0x5c: /* FCVTAU */
137
+ case 0x7a: /* FCVTPU */
138
+ case 0x7b: /* FCVTZU */
139
+ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
140
+ break;
141
+ default:
142
+ g_assert_not_reached();
143
+ }
28
+ }
144
+
29
+
145
+ /* limit any sign extension going on */
30
switch (vms->msi_controller) {
146
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
31
case VIRT_MSI_CTRL_NONE:
147
+ write_fp_sreg(s, rd, tcg_res);
32
return;
148
+
149
+ tcg_temp_free_i32(tcg_res);
150
+ tcg_temp_free_i32(tcg_op);
151
} else {
152
for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
153
TCGv_i32 tcg_op = tcg_temp_new_i32();
154
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
155
read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
156
157
switch (fpop) {
158
+ case 0x1a: /* FCVTNS */
159
+ case 0x1b: /* FCVTMS */
160
+ case 0x1c: /* FCVTAS */
161
+ case 0x3a: /* FCVTPS */
162
+ case 0x3b: /* FCVTZS */
163
+ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
164
+ break;
165
+ case 0x5a: /* FCVTNU */
166
+ case 0x5b: /* FCVTMU */
167
+ case 0x5c: /* FCVTAU */
168
+ case 0x7a: /* FCVTPU */
169
+ case 0x7b: /* FCVTZU */
170
+ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
171
+ break;
172
case 0x18: /* FRINTN */
173
case 0x19: /* FRINTM */
174
case 0x38: /* FRINTP */
175
--
33
--
176
2.16.2
34
2.25.1
177
35
178
36
diff view generated by jsdifflib
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
3
To propagate errors to the caller of the pre_plug callback, use the
4
chip selects are enabled (e.g reading/writing with stripe).
4
object_poperty_set*() functions directly instead of the qdev_prop_set*()
5
helpers.
5
6
6
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Suggested-by: Igor Mammedov <imammedo@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
9
Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++----
14
hw/arm/virt.c | 5 +++--
13
1 file changed, 37 insertions(+), 4 deletions(-)
15
1 file changed, 3 insertions(+), 2 deletions(-)
14
16
15
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/ssi/xilinx_spips.c
19
--- a/hw/arm/virt.c
18
+++ b/hw/ssi/xilinx_spips.c
20
+++ b/hw/arm/virt.c
19
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
20
{
22
db_start, db_end,
21
int i;
23
VIRTIO_IOMMU_RESV_MEM_T_MSI);
22
24
23
- for (i = 0; i < s->num_cs; i++) {
25
- qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
24
+ for (i = 0; i < s->num_cs * s->num_busses; i++) {
26
- qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
25
bool old_state = s->cs_lines_state[i];
27
+ object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
26
bool new_state = field & (1 << i);
28
+ object_property_set_str(OBJECT(dev), "reserved-regions[0]",
27
29
+ resv_prop_str, errp);
28
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
30
g_free(resv_prop_str);
29
}
30
qemu_set_irq(s->cs_lines[i], !new_state);
31
}
32
- if (!(field & ((1 << s->num_cs) - 1))) {
33
+ if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
34
s->snoop_state = SNOOP_CHECKING;
35
s->cmd_dummies = 0;
36
s->link_state = 1;
37
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
38
{
39
if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
40
int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
41
- xilinx_spips_update_cs(XILINX_SPIPS(s), field);
42
+ bool upper_cs_sel = field & (1 << 1);
43
+ bool lower_cs_sel = field & 1;
44
+ bool bus0_enabled;
45
+ bool bus1_enabled;
46
+ uint8_t buses;
47
+ int cs = 0;
48
+
49
+ buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
50
+ bus0_enabled = buses & 1;
51
+ bus1_enabled = buses & (1 << 1);
52
+
53
+ if (bus0_enabled && bus1_enabled) {
54
+ if (lower_cs_sel) {
55
+ cs |= 1;
56
+ }
57
+ if (upper_cs_sel) {
58
+ cs |= 1 << 3;
59
+ }
60
+ } else if (bus0_enabled) {
61
+ if (lower_cs_sel) {
62
+ cs |= 1;
63
+ }
64
+ if (upper_cs_sel) {
65
+ cs |= 1 << 1;
66
+ }
67
+ } else if (bus1_enabled) {
68
+ if (lower_cs_sel) {
69
+ cs |= 1 << 2;
70
+ }
71
+ if (upper_cs_sel) {
72
+ cs |= 1 << 3;
73
+ }
74
+ }
75
+ xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
76
}
31
}
77
}
32
}
78
79
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
80
if (num_effective_busses(s) == 2) {
81
/* Single bit chip-select for qspi */
82
field &= 0x1;
83
- field |= field << 1;
84
+ field |= field << 3;
85
/* Dual stack U-Page */
86
} else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
87
s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
88
--
33
--
89
2.16.2
34
2.25.1
90
35
91
36
diff view generated by jsdifflib
Deleted patch
1
From: Corey Minyard <cminyard@mvista.com>
2
1
3
Signed-off-by: Corey Minyard <cminyard@mvista.com>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6
Message-id: 20180227104903.21353-2-linus.walleij@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/i2c/i2c.h | 6 ++----
10
hw/i2c/core.c | 3 +--
11
2 files changed, 3 insertions(+), 6 deletions(-)
12
13
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/i2c/i2c.h
16
+++ b/include/hw/i2c/i2c.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlave I2CSlave;
18
#define I2C_SLAVE_GET_CLASS(obj) \
19
OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
20
21
-typedef struct I2CSlaveClass
22
-{
23
+typedef struct I2CSlaveClass {
24
DeviceClass parent_class;
25
26
/* Callbacks provided by the device. */
27
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlaveClass
28
int (*event)(I2CSlave *s, enum i2c_event event);
29
} I2CSlaveClass;
30
31
-struct I2CSlave
32
-{
33
+struct I2CSlave {
34
DeviceState qdev;
35
36
/* Remaining fields for internal use by the I2C code. */
37
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/i2c/core.c
40
+++ b/hw/i2c/core.c
41
@@ -XXX,XX +XXX,XX @@ struct I2CNode {
42
43
#define I2C_BROADCAST 0x00
44
45
-struct I2CBus
46
-{
47
+struct I2CBus {
48
BusState qbus;
49
QLIST_HEAD(, I2CNode) current_devs;
50
uint8_t saved_address;
51
--
52
2.16.2
53
54
diff view generated by jsdifflib
Deleted patch
1
From: Corey Minyard <cminyard@mvista.com>
2
1
3
Some devices need access to it.
4
5
Signed-off-by: Corey Minyard <cminyard@mvista.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
8
Message-id: 20180227104903.21353-3-linus.walleij@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/i2c/i2c.h | 17 +++++++++++++++++
12
hw/i2c/core.c | 17 -----------------
13
2 files changed, 17 insertions(+), 17 deletions(-)
14
15
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/i2c/i2c.h
18
+++ b/include/hw/i2c/i2c.h
19
@@ -XXX,XX +XXX,XX @@ struct I2CSlave {
20
uint8_t address;
21
};
22
23
+#define TYPE_I2C_BUS "i2c-bus"
24
+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
25
+
26
+typedef struct I2CNode I2CNode;
27
+
28
+struct I2CNode {
29
+ I2CSlave *elt;
30
+ QLIST_ENTRY(I2CNode) next;
31
+};
32
+
33
+struct I2CBus {
34
+ BusState qbus;
35
+ QLIST_HEAD(, I2CNode) current_devs;
36
+ uint8_t saved_address;
37
+ bool broadcast;
38
+};
39
+
40
I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
41
void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
42
int i2c_bus_busy(I2CBus *bus);
43
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/i2c/core.c
46
+++ b/hw/i2c/core.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "qemu/osdep.h"
49
#include "hw/i2c/i2c.h"
50
51
-typedef struct I2CNode I2CNode;
52
-
53
-struct I2CNode {
54
- I2CSlave *elt;
55
- QLIST_ENTRY(I2CNode) next;
56
-};
57
-
58
#define I2C_BROADCAST 0x00
59
60
-struct I2CBus {
61
- BusState qbus;
62
- QLIST_HEAD(, I2CNode) current_devs;
63
- uint8_t saved_address;
64
- bool broadcast;
65
-};
66
-
67
static Property i2c_props[] = {
68
DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
69
DEFINE_PROP_END_OF_LIST(),
70
};
71
72
-#define TYPE_I2C_BUS "i2c-bus"
73
-#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
74
-
75
static const TypeInfo i2c_bus_info = {
76
.name = TYPE_I2C_BUS,
77
.parent = TYPE_BUS,
78
--
79
2.16.2
80
81
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This allows us to explicitly pass float16 to helpers rather than
4
assuming uint32_t and dealing with the result. Of course they will be
5
passed in i32 sized registers by default.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-2-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/exec/helper-head.h | 3 +++
13
1 file changed, 3 insertions(+)
14
15
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/helper-head.h
18
+++ b/include/exec/helper-head.h
19
@@ -XXX,XX +XXX,XX @@
20
#define dh_alias_int i32
21
#define dh_alias_i64 i64
22
#define dh_alias_s64 i64
23
+#define dh_alias_f16 i32
24
#define dh_alias_f32 i32
25
#define dh_alias_f64 i64
26
#define dh_alias_ptr ptr
27
@@ -XXX,XX +XXX,XX @@
28
#define dh_ctype_int int
29
#define dh_ctype_i64 uint64_t
30
#define dh_ctype_s64 int64_t
31
+#define dh_ctype_f16 float16
32
#define dh_ctype_f32 float32
33
#define dh_ctype_f64 float64
34
#define dh_ctype_ptr void *
35
@@ -XXX,XX +XXX,XX @@
36
#define dh_is_signed_s32 1
37
#define dh_is_signed_i64 0
38
#define dh_is_signed_s64 1
39
+#define dh_is_signed_f16 0
40
#define dh_is_signed_f32 0
41
#define dh_is_signed_f64 0
42
#define dh_is_signed_tl 0
43
--
44
2.16.2
45
46
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-3-alex.bennee@linaro.org
6
[PMM: postpone actually enabling feature until end of the
7
patch series]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ enum arm_features {
18
ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
19
ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
20
ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
21
+ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
22
};
23
24
static inline int arm_feature(CPUARMState *env, int feature)
25
--
26
2.16.2
27
28
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-4-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/cpu.h | 1 +
9
1 file changed, 1 insertion(+)
10
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu.h
14
+++ b/target/arm/cpu.h
15
@@ -XXX,XX +XXX,XX @@ typedef struct {
16
* Qn = regs[n].d[1]:regs[n].d[0]
17
* Dn = regs[n].d[0]
18
* Sn = regs[n].d[0] bits 31..0
19
+ * Hn = regs[n].d[0] bits 15..0
20
*
21
* This corresponds to the architecturally defined mapping between
22
* the two execution states, and means we do not need to explicitly
23
--
24
2.16.2
25
26
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
The fprintf is only there for debugging as the skeleton is added to,
4
it will be removed once the skeleton is complete.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper-a64.h | 4 ++++
12
target/arm/helper-a64.c | 4 ++++
13
target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++
14
3 files changed, 36 insertions(+)
15
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
19
+++ b/target/arm/helper-a64.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
21
DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
22
DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
23
DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
24
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
25
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
26
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
27
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
28
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper-a64.c
31
+++ b/target/arm/helper-a64.c
32
@@ -XXX,XX +XXX,XX @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
33
return float16_ ## name(a, b, fpst); \
34
}
35
36
+ADVSIMD_HALFOP(add)
37
+ADVSIMD_HALFOP(sub)
38
+ADVSIMD_HALFOP(mul)
39
+ADVSIMD_HALFOP(div)
40
ADVSIMD_HALFOP(min)
41
ADVSIMD_HALFOP(max)
42
ADVSIMD_HALFOP(minnum)
43
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/translate-a64.c
46
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
48
read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
49
50
switch (fpopcode) {
51
+ case 0x0: /* FMAXNM */
52
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
53
+ break;
54
+ case 0x2: /* FADD */
55
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
56
+ break;
57
+ case 0x6: /* FMAX */
58
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
59
+ break;
60
+ case 0x8: /* FMINNM */
61
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
62
+ break;
63
+ case 0xa: /* FSUB */
64
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
65
+ break;
66
+ case 0xe: /* FMIN */
67
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
68
+ break;
69
+ case 0x13: /* FMUL */
70
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
71
+ break;
72
+ case 0x17: /* FDIV */
73
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
74
+ break;
75
+ case 0x1a: /* FABD */
76
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
77
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
78
+ break;
79
default:
80
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
81
__func__, insn, fpopcode, s->pc);
82
--
83
2.16.2
84
85
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
These use the generic float16_compare functionality which in turn uses
4
the common float_compare code from the softfloat re-factor.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper-a64.h | 5 +++++
12
target/arm/helper-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++
13
target/arm/translate-a64.c | 15 ++++++++++++++
14
3 files changed, 69 insertions(+)
15
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
19
+++ b/target/arm/helper-a64.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
21
DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
22
DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
23
DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
24
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
25
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
26
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
27
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
28
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
29
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper-a64.c
32
+++ b/target/arm/helper-a64.c
33
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(min)
34
ADVSIMD_HALFOP(max)
35
ADVSIMD_HALFOP(minnum)
36
ADVSIMD_HALFOP(maxnum)
37
+
38
+/*
39
+ * Floating point comparisons produce an integer result. Softfloat
40
+ * routines return float_relation types which we convert to the 0/-1
41
+ * Neon requires.
42
+ */
43
+
44
+#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
45
+
46
+uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
47
+{
48
+ float_status *fpst = fpstp;
49
+ int compare = float16_compare_quiet(a, b, fpst);
50
+ return ADVSIMD_CMPRES(compare == float_relation_equal);
51
+}
52
+
53
+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
54
+{
55
+ float_status *fpst = fpstp;
56
+ int compare = float16_compare(a, b, fpst);
57
+ return ADVSIMD_CMPRES(compare == float_relation_greater ||
58
+ compare == float_relation_equal);
59
+}
60
+
61
+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
62
+{
63
+ float_status *fpst = fpstp;
64
+ int compare = float16_compare(a, b, fpst);
65
+ return ADVSIMD_CMPRES(compare == float_relation_greater);
66
+}
67
+
68
+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
69
+{
70
+ float_status *fpst = fpstp;
71
+ float16 f0 = float16_abs(a);
72
+ float16 f1 = float16_abs(b);
73
+ int compare = float16_compare(f0, f1, fpst);
74
+ return ADVSIMD_CMPRES(compare == float_relation_greater ||
75
+ compare == float_relation_equal);
76
+}
77
+
78
+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
79
+{
80
+ float_status *fpst = fpstp;
81
+ float16 f0 = float16_abs(a);
82
+ float16 f1 = float16_abs(b);
83
+ int compare = float16_compare(f0, f1, fpst);
84
+ return ADVSIMD_CMPRES(compare == float_relation_greater);
85
+}
86
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/translate-a64.c
89
+++ b/target/arm/translate-a64.c
90
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
91
case 0x2: /* FADD */
92
gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
93
break;
94
+ case 0x4: /* FCMEQ */
95
+ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
96
+ break;
97
case 0x6: /* FMAX */
98
gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
99
break;
100
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
101
case 0x13: /* FMUL */
102
gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
103
break;
104
+ case 0x14: /* FCMGE */
105
+ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
106
+ break;
107
+ case 0x15: /* FACGE */
108
+ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
109
+ break;
110
case 0x17: /* FDIV */
111
gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
112
break;
113
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
114
gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
115
tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
116
break;
117
+ case 0x1c: /* FCMGT */
118
+ gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
119
+ break;
120
+ case 0x1d: /* FACGT */
121
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
122
+ break;
123
default:
124
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
125
__func__, insn, fpopcode, s->pc);
126
--
127
2.16.2
128
129
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper-a64.h | 2 ++
9
target/arm/helper-a64.c | 24 ++++++++++++++++++++++++
10
target/arm/translate-a64.c | 15 +++++++++++++++
11
3 files changed, 41 insertions(+)
12
13
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper-a64.h
16
+++ b/target/arm/helper-a64.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
18
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
19
DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
20
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
21
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
22
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
23
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-a64.c
26
+++ b/target/arm/helper-a64.c
27
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
28
ADVSIMD_HALFOP(minnum)
29
ADVSIMD_HALFOP(maxnum)
30
31
+/* Data processing - scalar floating-point and advanced SIMD */
32
+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
33
+{
34
+ float_status *fpst = fpstp;
35
+
36
+ a = float16_squash_input_denormal(a, fpst);
37
+ b = float16_squash_input_denormal(b, fpst);
38
+
39
+ if ((float16_is_zero(a) && float16_is_infinity(b)) ||
40
+ (float16_is_infinity(a) && float16_is_zero(b))) {
41
+ /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
42
+ return make_float16((1U << 14) |
43
+ ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
44
+ }
45
+ return float16_mul(a, b, fpst);
46
+}
47
+
48
+/* fused multiply-accumulate */
49
+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
50
+{
51
+ float_status *fpst = fpstp;
52
+ return float16_muladd(a, b, c, 0, fpst);
53
+}
54
+
55
/*
56
* Floating point comparisons produce an integer result. Softfloat
57
* routines return float_relation types which we convert to the 0/-1
58
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-a64.c
61
+++ b/target/arm/translate-a64.c
62
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
63
case 0x0: /* FMAXNM */
64
gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
65
break;
66
+ case 0x1: /* FMLA */
67
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
68
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
69
+ fpst);
70
+ break;
71
case 0x2: /* FADD */
72
gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
73
break;
74
+ case 0x3: /* FMULX */
75
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
76
+ break;
77
case 0x4: /* FCMEQ */
78
gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
79
break;
80
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
81
case 0x8: /* FMINNM */
82
gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
83
break;
84
+ case 0x9: /* FMLS */
85
+ /* As usual for ARM, separate negation for fused multiply-add */
86
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
87
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
88
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
89
+ fpst);
90
+ break;
91
case 0xa: /* FSUB */
92
gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
93
break;
94
--
95
2.16.2
96
97
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
3
Create empty data files and allow updates for the upcoming VIOT tests.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
5
Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
5
Acked-by: Igor Mammedov <imammedo@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/helper-a64.h | 1 +
11
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
9
target/arm/helper-a64.c | 13 +++++++++++++
12
tests/data/acpi/q35/DSDT.viot | 0
10
target/arm/translate-a64.c | 5 +++++
13
tests/data/acpi/q35/VIOT.viot | 0
11
3 files changed, 19 insertions(+)
14
tests/data/acpi/virt/VIOT | 0
15
4 files changed, 3 insertions(+)
16
create mode 100644 tests/data/acpi/q35/DSDT.viot
17
create mode 100644 tests/data/acpi/q35/VIOT.viot
18
create mode 100644 tests/data/acpi/virt/VIOT
12
19
13
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
20
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper-a64.h
22
--- a/tests/qtest/bios-tables-test-allowed-diff.h
16
+++ b/target/arm/helper-a64.h
23
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
24
@@ -1 +1,4 @@
18
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
25
/* List of comma-separated changed AML files to ignore */
19
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
26
+"tests/data/acpi/virt/VIOT",
20
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
27
+"tests/data/acpi/q35/DSDT.viot",
21
+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
28
+"tests/data/acpi/q35/VIOT.viot",
22
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
29
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
23
index XXXXXXX..XXXXXXX 100644
30
new file mode 100644
24
--- a/target/arm/helper-a64.c
31
index XXXXXXX..XXXXXXX
25
+++ b/target/arm/helper-a64.c
32
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
26
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
33
new file mode 100644
27
}
34
index XXXXXXX..XXXXXXX
28
return float16_to_uint16(a, fpst);
35
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
29
}
36
new file mode 100644
30
+
37
index XXXXXXX..XXXXXXX
31
+/*
32
+ * Square Root and Reciprocal square root
33
+ */
34
+
35
+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
36
+{
37
+ float_status *s = fpstp;
38
+
39
+ return float16_sqrt(a, s);
40
+}
41
+
42
+
43
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/translate-a64.c
46
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
48
case 0x6f: /* FNEG */
49
need_fpst = false;
50
break;
51
+ case 0x7f: /* FSQRT (vector) */
52
+ break;
53
default:
54
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
55
g_assert_not_reached();
56
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
57
case 0x6f: /* FNEG */
58
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
59
break;
60
+ case 0x7f: /* FSQRT */
61
+ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
62
+ break;
63
default:
64
g_assert_not_reached();
65
}
66
--
38
--
67
2.16.2
39
2.25.1
68
40
69
41
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
As some of the constants here will also be needed
3
Add two test cases for VIOT, one on the q35 machine and the other on
4
elsewhere (specifically for the upcoming SVE support) we move them out
4
virt. To test complex topologies the q35 test has two PCIe buses that
5
to softfloat.h.
5
bypass the IOMMU (and are therefore not described by VIOT), and two
6
buses that are translated by virtio-iommu.
6
7
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
9
Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
include/fpu/softfloat.h | 18 +++++++++++++-----
14
tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
13
target/arm/helper-a64.h | 2 ++
15
1 file changed, 38 insertions(+)
14
target/arm/helper-a64.c | 34 ++++++++++++++++++++++++++++++++++
15
target/arm/translate-a64.c | 6 ++++++
16
4 files changed, 55 insertions(+), 5 deletions(-)
17
16
18
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
17
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/include/fpu/softfloat.h
19
--- a/tests/qtest/bios-tables-test.c
21
+++ b/include/fpu/softfloat.h
20
+++ b/tests/qtest/bios-tables-test.c
22
@@ -XXX,XX +XXX,XX @@ static inline float16 float16_set_sign(float16 a, int sign)
21
@@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void)
22
free_test_data(&data);
23
}
23
}
24
24
25
#define float16_zero make_float16(0)
25
+static void test_acpi_q35_viot(void)
26
-#define float16_one make_float16(0x3c00)
26
+{
27
#define float16_half make_float16(0x3800)
27
+ test_data data = {
28
+#define float16_one make_float16(0x3c00)
28
+ .machine = MACHINE_Q35,
29
+#define float16_one_point_five make_float16(0x3e00)
29
+ .variant = ".viot",
30
+#define float16_two make_float16(0x4000)
30
+ };
31
+#define float16_three make_float16(0x4200)
32
#define float16_infinity make_float16(0x7c00)
33
34
/*----------------------------------------------------------------------------
35
@@ -XXX,XX +XXX,XX @@ static inline float32 float32_set_sign(float32 a, int sign)
36
}
37
38
#define float32_zero make_float32(0)
39
-#define float32_one make_float32(0x3f800000)
40
#define float32_half make_float32(0x3f000000)
41
+#define float32_one make_float32(0x3f800000)
42
+#define float32_one_point_five make_float32(0x3fc00000)
43
+#define float32_two make_float32(0x40000000)
44
+#define float32_three make_float32(0x40400000)
45
#define float32_infinity make_float32(0x7f800000)
46
47
-
48
/*----------------------------------------------------------------------------
49
| The pattern for a default generated single-precision NaN.
50
*----------------------------------------------------------------------------*/
51
@@ -XXX,XX +XXX,XX @@ static inline float64 float64_set_sign(float64 a, int sign)
52
}
53
54
#define float64_zero make_float64(0)
55
-#define float64_one make_float64(0x3ff0000000000000LL)
56
-#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
57
#define float64_half make_float64(0x3fe0000000000000LL)
58
+#define float64_one make_float64(0x3ff0000000000000LL)
59
+#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
60
+#define float64_two make_float64(0x4000000000000000ULL)
61
+#define float64_three make_float64(0x4008000000000000ULL)
62
+#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
63
#define float64_infinity make_float64(0x7ff0000000000000LL)
64
65
/*----------------------------------------------------------------------------
66
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/helper-a64.h
69
+++ b/target/arm/helper-a64.h
70
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
71
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
72
DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
73
DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
74
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
75
DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
76
DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
77
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
78
DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
79
DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
80
DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
81
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/helper-a64.c
84
+++ b/target/arm/helper-a64.c
85
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
86
* versions, these do a fully fused multiply-add or
87
* multiply-add-and-halve.
88
*/
89
+#define float16_two make_float16(0x4000)
90
+#define float16_three make_float16(0x4200)
91
+#define float16_one_point_five make_float16(0x3e00)
92
+
31
+
93
#define float32_two make_float32(0x40000000)
32
+ /*
94
#define float32_three make_float32(0x40400000)
33
+ * To keep things interesting, two buses bypass the IOMMU.
95
#define float32_one_point_five make_float32(0x3fc00000)
34
+ * VIOT should only describes the other two buses.
96
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
35
+ */
97
#define float64_three make_float64(0x4008000000000000ULL)
36
+ test_acpi_one("-machine default_bus_bypass_iommu=on "
98
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
37
+ "-device virtio-iommu-pci "
99
38
+ "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 "
100
+float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
39
+ "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on "
101
+{
40
+ "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0",
102
+ float_status *fpst = fpstp;
41
+ &data);
103
+
42
+ free_test_data(&data);
104
+ a = float16_squash_input_denormal(a, fpst);
105
+ b = float16_squash_input_denormal(b, fpst);
106
+
107
+ a = float16_chs(a);
108
+ if ((float16_is_infinity(a) && float16_is_zero(b)) ||
109
+ (float16_is_infinity(b) && float16_is_zero(a))) {
110
+ return float16_two;
111
+ }
112
+ return float16_muladd(a, b, float16_two, 0, fpst);
113
+}
43
+}
114
+
44
+
115
float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
45
+static void test_acpi_virt_viot(void)
116
{
117
float_status *fpst = fpstp;
118
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
119
return float64_muladd(a, b, float64_two, 0, fpst);
120
}
121
122
+float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
123
+{
46
+{
124
+ float_status *fpst = fpstp;
47
+ test_data data = {
48
+ .machine = "virt",
49
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
50
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
51
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
52
+ .ram_start = 0x40000000ULL,
53
+ .scan_len = 128ULL * 1024 * 1024,
54
+ };
125
+
55
+
126
+ a = float16_squash_input_denormal(a, fpst);
56
+ test_acpi_one("-cpu cortex-a57 "
127
+ b = float16_squash_input_denormal(b, fpst);
57
+ "-device virtio-iommu-pci", &data);
128
+
58
+ free_test_data(&data);
129
+ a = float16_chs(a);
130
+ if ((float16_is_infinity(a) && float16_is_zero(b)) ||
131
+ (float16_is_infinity(b) && float16_is_zero(a))) {
132
+ return float16_one_point_five;
133
+ }
134
+ return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
135
+}
59
+}
136
+
60
+
137
float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
61
static void test_oem_fields(test_data *data)
138
{
62
{
139
float_status *fpst = fpstp;
63
int i;
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
64
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
141
index XXXXXXX..XXXXXXX 100644
65
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
142
--- a/target/arm/translate-a64.c
66
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
143
+++ b/target/arm/translate-a64.c
67
}
144
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
68
+ qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
145
case 0x6: /* FMAX */
69
} else if (strcmp(arch, "aarch64") == 0) {
146
gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
70
if (has_tcg) {
147
break;
71
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
148
+ case 0x7: /* FRECPS */
72
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
149
+ gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
73
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
150
+ break;
74
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
151
case 0x8: /* FMINNM */
75
qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt);
152
gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
76
+ qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
153
break;
77
}
154
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
78
}
155
case 0xe: /* FMIN */
79
ret = g_test_run();
156
gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
157
break;
158
+ case 0xf: /* FRSQRTS */
159
+ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
160
+ break;
161
case 0x13: /* FMUL */
162
gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
163
break;
164
--
80
--
165
2.16.2
81
2.25.1
166
82
167
83
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
The helpers use the new re-factored muladd support in SoftFloat for
4
the float16 work.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180227143852.11175-15-alex.bennee@linaro.org
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++---------
12
1 file changed, 66 insertions(+), 16 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
19
int rd = extract32(insn, 0, 5);
20
bool is_long = false;
21
bool is_fp = false;
22
+ bool is_fp16 = false;
23
int index;
24
TCGv_ptr fpst;
25
26
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
27
}
28
/* fall through */
29
case 0x9: /* FMUL, FMULX */
30
- if (!extract32(size, 1, 1)) {
31
+ if (size == 1) {
32
unallocated_encoding(s);
33
return;
34
}
35
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
36
}
37
38
if (is_fp) {
39
- /* low bit of size indicates single/double */
40
- size = extract32(size, 0, 1) ? 3 : 2;
41
- if (size == 2) {
42
+ /* convert insn encoded size to TCGMemOp size */
43
+ switch (size) {
44
+ case 2: /* single precision */
45
+ size = MO_32;
46
index = h << 1 | l;
47
- } else {
48
+ rm |= (m << 4);
49
+ break;
50
+ case 3: /* double precision */
51
+ size = MO_64;
52
if (l || !is_q) {
53
unallocated_encoding(s);
54
return;
55
}
56
index = h;
57
+ rm |= (m << 4);
58
+ break;
59
+ case 0: /* half precision */
60
+ size = MO_16;
61
+ index = h << 2 | l << 1 | m;
62
+ is_fp16 = true;
63
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
64
+ break;
65
+ }
66
+ /* fallthru */
67
+ default: /* unallocated */
68
+ unallocated_encoding(s);
69
+ return;
70
}
71
- rm |= (m << 4);
72
} else {
73
switch (size) {
74
case 1:
75
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
76
}
77
78
if (is_fp) {
79
- fpst = get_fpstatus_ptr(false);
80
+ fpst = get_fpstatus_ptr(is_fp16);
81
} else {
82
fpst = NULL;
83
}
84
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
85
break;
86
}
87
case 0x5: /* FMLS */
88
- /* As usual for ARM, separate negation for fused multiply-add */
89
- gen_helper_vfp_negs(tcg_op, tcg_op);
90
- /* fall through */
91
case 0x1: /* FMLA */
92
- read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
93
- gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
94
+ read_vec_element_i32(s, tcg_res, rd, pass,
95
+ is_scalar ? size : MO_32);
96
+ switch (size) {
97
+ case 1:
98
+ if (opcode == 0x5) {
99
+ /* As usual for ARM, separate negation for fused
100
+ * multiply-add */
101
+ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
102
+ }
103
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
104
+ tcg_res, fpst);
105
+ break;
106
+ case 2:
107
+ if (opcode == 0x5) {
108
+ /* As usual for ARM, separate negation for
109
+ * fused multiply-add */
110
+ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
111
+ }
112
+ gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
113
+ tcg_res, fpst);
114
+ break;
115
+ default:
116
+ g_assert_not_reached();
117
+ }
118
break;
119
case 0x9: /* FMUL, FMULX */
120
- if (u) {
121
- gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
122
- } else {
123
- gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
124
+ switch (size) {
125
+ case 1:
126
+ if (u) {
127
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
128
+ fpst);
129
+ } else {
130
+ g_assert_not_reached();
131
+ }
132
+ break;
133
+ case 2:
134
+ if (u) {
135
+ gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
136
+ } else {
137
+ gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
138
+ }
139
+ break;
140
+ default:
141
+ g_assert_not_reached();
142
}
143
break;
144
case 0xc: /* SQDMULH */
145
--
146
2.16.2
147
148
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Now we have added f16 during the re-factoring we can simply call the
3
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
4
helper.
4
q35 machine.
5
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Since the test instantiates a virtio device and two PCIe expander
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
bridges, DSDT.viot has more blocks than the base DSDT.
8
Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
8
9
The VIOT table generated for the q35 test is:
10
11
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
12
[004h 0004 4] Table Length : 00000070
13
[008h 0008 1] Revision : 00
14
[009h 0009 1] Checksum : 3D
15
[00Ah 0010 6] Oem ID : "BOCHS "
16
[010h 0016 8] Oem Table ID : "BXPC "
17
[018h 0024 4] Oem Revision : 00000001
18
[01Ch 0028 4] Asl Compiler ID : "BXPC"
19
[020h 0032 4] Asl Compiler Revision : 00000001
20
21
[024h 0036 2] Node count : 0003
22
[026h 0038 2] Node offset : 0030
23
[028h 0040 8] Reserved : 0000000000000000
24
25
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
26
[031h 0049 1] Reserved : 00
27
[032h 0050 2] Length : 0010
28
29
[034h 0052 2] PCI Segment : 0000
30
[036h 0054 2] PCI BDF number : 0010
31
[038h 0056 8] Reserved : 0000000000000000
32
33
[040h 0064 1] Type : 01 [PCI Range]
34
[041h 0065 1] Reserved : 00
35
[042h 0066 2] Length : 0018
36
37
[044h 0068 4] Endpoint start : 00003000
38
[048h 0072 2] PCI Segment start : 0000
39
[04Ah 0074 2] PCI Segment end : 0000
40
[04Ch 0076 2] PCI BDF start : 3000
41
[04Eh 0078 2] PCI BDF end : 30FF
42
[050h 0080 2] Output node : 0030
43
[052h 0082 6] Reserved : 000000000000
44
45
[058h 0088 1] Type : 01 [PCI Range]
46
[059h 0089 1] Reserved : 00
47
[05Ah 0090 2] Length : 0018
48
49
[05Ch 0092 4] Endpoint start : 00001000
50
[060h 0096 2] PCI Segment start : 0000
51
[062h 0098 2] PCI Segment end : 0000
52
[064h 0100 2] PCI BDF start : 1000
53
[066h 0102 2] PCI BDF end : 10FF
54
[068h 0104 2] Output node : 0030
55
[06Ah 0106 6] Reserved : 000000000000
56
57
And the DSDT diff is:
58
59
@@ -XXX,XX +XXX,XX @@
60
*
61
* Disassembling to symbolic ASL+ operators
62
*
63
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
64
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
65
*
66
* Original Table Header:
67
* Signature "DSDT"
68
- * Length 0x00002061 (8289)
69
+ * Length 0x000024B6 (9398)
70
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
71
- * Checksum 0xFA
72
+ * Checksum 0xA7
73
* OEM ID "BOCHS "
74
* OEM Table ID "BXPC "
75
* OEM Revision 0x00000001 (1)
76
@@ -XXX,XX +XXX,XX @@
77
}
78
}
79
80
+ Scope (\_SB)
81
+ {
82
+ Device (PC30)
83
+ {
84
+ Name (_UID, 0x30) // _UID: Unique ID
85
+ Name (_BBN, 0x30) // _BBN: BIOS Bus Number
86
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
87
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
88
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
89
+ {
90
+ CreateDWordField (Arg3, Zero, CDW1)
91
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
92
+ {
93
+ CreateDWordField (Arg3, 0x04, CDW2)
94
+ CreateDWordField (Arg3, 0x08, CDW3)
95
+ Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */
96
+ Local0 &= 0x1F
97
+ If ((Arg1 != One))
98
+ {
99
+ CDW1 |= 0x08
100
+ }
101
+
102
+ If ((CDW3 != Local0))
103
+ {
104
+ CDW1 |= 0x10
105
+ }
106
+
107
+ CDW3 = Local0
108
+ }
109
+ Else
110
+ {
111
+ CDW1 |= 0x04
112
+ }
113
+
114
+ Return (Arg3)
115
+ }
116
+
117
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
118
+ {
119
+ Local0 = Package (0x80){}
120
+ Local1 = Zero
121
+ While ((Local1 < 0x80))
122
+ {
123
+ Local2 = (Local1 >> 0x02)
124
+ Local3 = ((Local1 + Local2) & 0x03)
125
+ If ((Local3 == Zero))
126
+ {
127
+ Local4 = Package (0x04)
128
+ {
129
+ Zero,
130
+ Zero,
131
+ LNKD,
132
+ Zero
133
+ }
134
+ }
135
+
136
+ If ((Local3 == One))
137
+ {
138
+ Local4 = Package (0x04)
139
+ {
140
+ Zero,
141
+ Zero,
142
+ LNKA,
143
+ Zero
144
+ }
145
+ }
146
+
147
+ If ((Local3 == 0x02))
148
+ {
149
+ Local4 = Package (0x04)
150
+ {
151
+ Zero,
152
+ Zero,
153
+ LNKB,
154
+ Zero
155
+ }
156
+ }
157
+
158
+ If ((Local3 == 0x03))
159
+ {
160
+ Local4 = Package (0x04)
161
+ {
162
+ Zero,
163
+ Zero,
164
+ LNKC,
165
+ Zero
166
+ }
167
+ }
168
+
169
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
170
+ Local4 [One] = (Local1 & 0x03)
171
+ Local0 [Local1] = Local4
172
+ Local1++
173
+ }
174
+
175
+ Return (Local0)
176
+ }
177
+
178
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
179
+ {
180
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
181
+ 0x0000, // Granularity
182
+ 0x0030, // Range Minimum
183
+ 0x0030, // Range Maximum
184
+ 0x0000, // Translation Offset
185
+ 0x0001, // Length
186
+ ,, )
187
+ })
188
+ }
189
+ }
190
+
191
+ Scope (\_SB)
192
+ {
193
+ Device (PC20)
194
+ {
195
+ Name (_UID, 0x20) // _UID: Unique ID
196
+ Name (_BBN, 0x20) // _BBN: BIOS Bus Number
197
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
198
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
199
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
200
+ {
201
+ CreateDWordField (Arg3, Zero, CDW1)
202
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
203
+ {
204
+ CreateDWordField (Arg3, 0x04, CDW2)
205
+ CreateDWordField (Arg3, 0x08, CDW3)
206
+ Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */
207
+ Local0 &= 0x1F
208
+ If ((Arg1 != One))
209
+ {
210
+ CDW1 |= 0x08
211
+ }
212
+
213
+ If ((CDW3 != Local0))
214
+ {
215
+ CDW1 |= 0x10
216
+ }
217
+
218
+ CDW3 = Local0
219
+ }
220
+ Else
221
+ {
222
+ CDW1 |= 0x04
223
+ }
224
+
225
+ Return (Arg3)
226
+ }
227
+
228
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
229
+ {
230
+ Local0 = Package (0x80){}
231
+ Local1 = Zero
232
+ While ((Local1 < 0x80))
233
+ {
234
+ Local2 = (Local1 >> 0x02)
235
+ Local3 = ((Local1 + Local2) & 0x03)
236
+ If ((Local3 == Zero))
237
+ {
238
+ Local4 = Package (0x04)
239
+ {
240
+ Zero,
241
+ Zero,
242
+ LNKD,
243
+ Zero
244
+ }
245
+ }
246
+
247
+ If ((Local3 == One))
248
+ {
249
+ Local4 = Package (0x04)
250
+ {
251
+ Zero,
252
+ Zero,
253
+ LNKA,
254
+ Zero
255
+ }
256
+ }
257
+
258
+ If ((Local3 == 0x02))
259
+ {
260
+ Local4 = Package (0x04)
261
+ {
262
+ Zero,
263
+ Zero,
264
+ LNKB,
265
+ Zero
266
+ }
267
+ }
268
+
269
+ If ((Local3 == 0x03))
270
+ {
271
+ Local4 = Package (0x04)
272
+ {
273
+ Zero,
274
+ Zero,
275
+ LNKC,
276
+ Zero
277
+ }
278
+ }
279
+
280
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
281
+ Local4 [One] = (Local1 & 0x03)
282
+ Local0 [Local1] = Local4
283
+ Local1++
284
+ }
285
+
286
+ Return (Local0)
287
+ }
288
+
289
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
290
+ {
291
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
292
+ 0x0000, // Granularity
293
+ 0x0020, // Range Minimum
294
+ 0x0020, // Range Maximum
295
+ 0x0000, // Translation Offset
296
+ 0x0001, // Length
297
+ ,, )
298
+ })
299
+ }
300
+ }
301
+
302
+ Scope (\_SB)
303
+ {
304
+ Device (PC10)
305
+ {
306
+ Name (_UID, 0x10) // _UID: Unique ID
307
+ Name (_BBN, 0x10) // _BBN: BIOS Bus Number
308
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
309
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
310
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
311
+ {
312
+ CreateDWordField (Arg3, Zero, CDW1)
313
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
314
+ {
315
+ CreateDWordField (Arg3, 0x04, CDW2)
316
+ CreateDWordField (Arg3, 0x08, CDW3)
317
+ Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */
318
+ Local0 &= 0x1F
319
+ If ((Arg1 != One))
320
+ {
321
+ CDW1 |= 0x08
322
+ }
323
+
324
+ If ((CDW3 != Local0))
325
+ {
326
+ CDW1 |= 0x10
327
+ }
328
+
329
+ CDW3 = Local0
330
+ }
331
+ Else
332
+ {
333
+ CDW1 |= 0x04
334
+ }
335
+
336
+ Return (Arg3)
337
+ }
338
+
339
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
340
+ {
341
+ Local0 = Package (0x80){}
342
+ Local1 = Zero
343
+ While ((Local1 < 0x80))
344
+ {
345
+ Local2 = (Local1 >> 0x02)
346
+ Local3 = ((Local1 + Local2) & 0x03)
347
+ If ((Local3 == Zero))
348
+ {
349
+ Local4 = Package (0x04)
350
+ {
351
+ Zero,
352
+ Zero,
353
+ LNKD,
354
+ Zero
355
+ }
356
+ }
357
+
358
+ If ((Local3 == One))
359
+ {
360
+ Local4 = Package (0x04)
361
+ {
362
+ Zero,
363
+ Zero,
364
+ LNKA,
365
+ Zero
366
+ }
367
+ }
368
+
369
+ If ((Local3 == 0x02))
370
+ {
371
+ Local4 = Package (0x04)
372
+ {
373
+ Zero,
374
+ Zero,
375
+ LNKB,
376
+ Zero
377
+ }
378
+ }
379
+
380
+ If ((Local3 == 0x03))
381
+ {
382
+ Local4 = Package (0x04)
383
+ {
384
+ Zero,
385
+ Zero,
386
+ LNKC,
387
+ Zero
388
+ }
389
+ }
390
+
391
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
392
+ Local4 [One] = (Local1 & 0x03)
393
+ Local0 [Local1] = Local4
394
+ Local1++
395
+ }
396
+
397
+ Return (Local0)
398
+ }
399
+
400
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
401
+ {
402
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
403
+ 0x0000, // Granularity
404
+ 0x0010, // Range Minimum
405
+ 0x0010, // Range Maximum
406
+ 0x0000, // Translation Offset
407
+ 0x0001, // Length
408
+ ,, )
409
+ })
410
+ }
411
+ }
412
+
413
Scope (\_SB.PCI0)
414
{
415
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
416
@@ -XXX,XX +XXX,XX @@
417
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
418
0x0000, // Granularity
419
0x0000, // Range Minimum
420
- 0x00FF, // Range Maximum
421
+ 0x000F, // Range Maximum
422
0x0000, // Translation Offset
423
- 0x0100, // Length
424
+ 0x0010, // Length
425
,, )
426
IO (Decode16,
427
0x0CF8, // Range Minimum
428
@@ -XXX,XX +XXX,XX @@
429
}
430
}
431
432
+ Device (S10)
433
+ {
434
+ Name (_ADR, 0x00020000) // _ADR: Address
435
+ }
436
+
437
+ Device (S18)
438
+ {
439
+ Name (_ADR, 0x00030000) // _ADR: Address
440
+ }
441
+
442
+ Device (S20)
443
+ {
444
+ Name (_ADR, 0x00040000) // _ADR: Address
445
+ }
446
+
447
+ Device (S28)
448
+ {
449
+ Name (_ADR, 0x00050000) // _ADR: Address
450
+ }
451
+
452
Method (PCNT, 0, NotSerialized)
453
{
454
}
455
456
Reviewed-by: Eric Auger <eric.auger@redhat.com>
457
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
458
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
459
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
460
---
11
target/arm/translate-a64.c | 8 ++++++++
461
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
12
1 file changed, 8 insertions(+)
462
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
13
463
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
464
3 files changed, 2 deletions(-)
465
466
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
15
index XXXXXXX..XXXXXXX 100644
467
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
468
--- a/tests/qtest/bios-tables-test-allowed-diff.h
17
+++ b/target/arm/translate-a64.c
469
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
470
@@ -XXX,XX +XXX,XX @@
19
case 0x6d: /* FCMLE (zero) */
471
/* List of comma-separated changed AML files to ignore */
20
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
472
"tests/data/acpi/virt/VIOT",
21
return;
473
-"tests/data/acpi/q35/DSDT.viot",
22
+ case 0x3d: /* FRECPE */
474
-"tests/data/acpi/q35/VIOT.viot",
23
+ break;
475
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
24
case 0x18: /* FRINTN */
476
index XXXXXXX..XXXXXXX 100644
25
need_rmode = true;
477
GIT binary patch
26
only_in_vector = true;
478
literal 9398
27
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
479
zcmeHNO>7&-8J*>iv|O&FB}G~Oi$yp||57BBoWHhc5OS9yDTx$CQgH$r;8Idr*-4Q_
28
case 0x3b: /* FCVTZS */
480
z5(9Az1F`}niVsB-)<KW7p`g9Br(A2Gm-gmc1N78GFS!;)e2V(MnH_0{q<{#yMgn&C
29
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
481
zn|*J-d9yqFhO_H6z19~`FlPL*u<DkZ*}|)JH;X@mF-FI<cPg<fti9tEN*yB^i5czN
30
break;
482
zNq&q?!OZ;BE3B7{KWzJ-`Tn~f`9?Qj8~2^N8{Oc8J%57{==w%rS#;nOCp*nTr@iZ1
31
+ case 0x3d: /* FRECPE */
483
zb+?i;JLQUJ=O0?8*>S~D)a>NF1~WVB6^~_B#yhJ`H+JU@=6aXs`?Yv)J2h=N?drcS
32
+ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
484
zeLZ*n<<Bm^n}6`jfBx#u8&(W}1?)}iF9o#mZ~E2+zwdn7yK3AbIzKnxpZ>JRPm3~#
33
+ break;
485
z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW%
34
case 0x5a: /* FCVTNU */
486
z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^
35
case 0x5b: /* FCVTMU */
487
z;s;dJec!hnzi)ri^I6YN9vtkm{^TdUF8h7gX8-<Qe4p)GQ=)AtYx2VcwdLVAEXEjG
36
case 0x5c: /* FCVTAU */
488
z^Mj|UHPqkj-LsWuzQem1>F3atdZn=zv3$#RmZzSHN+6-yyU#8cJb=YDilX&sl}vNm
37
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
489
znkgAR^O<3kj4if>{ly5fwRfMWuC5=lrlvKPX~i#654Cp}R_d*JS$9laZ$ra6)<ns8
38
case 0x3b: /* FCVTZS */
490
zFZy28G%xP(nit&F>LDi%G<tIc=TY=gl$jSD&Uv!Yat~XR46h%rI$!}a%!|xG7u8Zn
39
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
491
zeY8_|n=K>xz_v_W8VX$W-Fg-qFWcT}7MCyz{%%{ia7hZ>Law-k6NOr}VI&_48U=2l
40
break;
492
zwqDKFE8eTwwozDdms#e?x?5a|v>&JF;2_v0L~z5n%BYU^52<*cWuD4|GYUm@1+?))
41
+ case 0x3d: /* FRECPE */
493
zte^45>Rz)t*<T5V#={r>@t@{%?^i#W{i=HAZ*Dc9y59Va-+#P!jrGs;u38a{fLr`N
42
+ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
494
zvT@rUu>DljxJ?^&Z?-?vyJn3C>3D=qux{Y*bs5|5n)Qmi$TD^Zdn4GU$ocJS2Hh-<
43
+ break;
495
z`xPI^^+v0nUVdjMos8k`WGl7hA`{03ju%<lrgAHSpd^DRf-*}_#Ly0mB!LSfVgWcQ
44
case 0x5a: /* FCVTNU */
496
z&T$@~G9)JI=hz5m0vkrel+Xy{Oh7pkAu-V!j*W7rY(bO}Q$nMH2`FbGB&N)QaV4<4
45
case 0x5b: /* FCVTMU */
497
zo)~9JXiP9=;}NPl<C@MmXG&;XFlFNrsyfFsonxFSp<}vEgsRSQP3O3#b6nSnP}ON_
46
case 0x5c: /* FCVTAU */
498
zI!#Tdsp~|j>ckUB>FI=~GokB5sOq#dotCE4(sd$KbtW~PNlj-`*NIToiD#j5J#9^=
499
zt?NXn>YUJYPG~wObe#xQos*i*NloXZt`niEb4t@WrRki~bs|)CI+{*L)9L6s5vn><
500
zn$DD_Go|Z9sOn5>I@6lYw5}7Os&iV?Ij!lO)^#FOb!If38BJ$K*NIToIiu;E(R9w}
501
zIuWWmPiZ<&X*y5oIuWWmF_XaEC!a&Jn$B5WCqh-{X-(&8P3LJ{Cqh-{8P3dyPr@^t
502
zSqL9?X9Uwd3W@23*s~h*tj0X6GZCuHa~kuU#yqDp5vt7d8uPryJg+kms?5hU=3^T3
503
zF`bD}WnSP+=`t5MQ$FJ_2&Q~+BP6E0f^%BVIW6a$o)e+SX~IDBih-7z6{O~7YTy`&
504
zLjy&Cv?7QikV#>n0>>@MV8oK`Gmun34-FKdlm-J8SZSaNlnhir4-FI{S|bfqV8e)V
505
zss<{chX#reE#g=hsKAC%sF6d-Km}BWs!kZFsFpKfpbC@>6rprQGEjt4Ck#|zITHq|
506
zK*>M_l;<P^MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=xY&!axO<
507
zGhv_#lnhirIg<<&q0|Wj6<E%MfhtfkPyyvkGEjt4Ck#|zITHq|K*>M_lrzad5lWpf
508
zP=V!47^ngz0~JutBm+e#b;3XemNQ|X3X}{~Ksl2P6rt1!0~J`#gn=qhGEf2KOfpb}
509
zQYQ>lU^x>8szAv=1(Y+%KoLrvFi?TzOc<yFB?A>u&LjgxD0RX>1(q{mpbC@>R6seC
510
z3>2Z%2?G^a&V+#~P%=;f<xDbAgi<FARA4z12C6{GKn0XD$v_cGoiI>=<xCi;0wn_#
511
zP|hR+MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=rz^3{+q_69%e4
512
z$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axxz28u{EP=u<1B2)}iVZuNaCK;&0
513
zBm-5LFi?dF167!0pbC==RAItE6($T+VUmF=Ofpb~2?JG_Fi?d_2C6X0Kouqo6p_5T
514
zFi=FeV!SiSKoR0H$dH(_Z(*Q_WZ%L-5y`$K14StNmJAdjmWs}HV4<vU_xO+1efmLq
515
zZ;W>N_U)fP6Qy6Nw5mbt9Y(#emWSi66=>tq#xoh#Ue=0qyhxi8ZOUe5y0V7VfPUhp
516
zwX=;ymc+i5%sg9Ja~lZ&8oAV@mHc>&CHP9v4R(jhtT?un;O4e9#pno)Xkh7OWgK&a
517
zyj=3Iv0OuoK_;5rOr5f(Kb~ZXDBO+V`OWYo#_C08imwChQxnjdd?wZLDou8aj;$SD
518
zGDYiA3<$Tu<JnHL(KPOChi#zrR32t83}naR$+ym4P_h?z_5#|cW-nw$XD_sOtE62l
519
zrD3@*)NVyiklt0&yF9%+klsBey&I<Y2E<!f(E8TuJte)z(|ZHyy<^gQVfx}=`q&B5
520
z7nSryp1wGczIaUfVwiq$Fn#<4=@*ssi#+|}K>EdF(l3VTOM~ghPLRH&q%ZOGrGfON
521
zW73zx^yR_y<0nX8R??Sw`tm^f@-gYlNFSp|*<gA{q?Zp5Oe-+l#rmyYmKozi9y=P>
522
zVReJU*h=ZuVXiS$ohTbw-O#v9>(yZbGE|)?8(H1ZIKvV!jWa0>vy!3eMA^vdhQ>`s
523
zuMSg{q3T50$m)j1!HixV<}X9liL#N^4c*tL^y)CF8LCc{jjV3yKAqL8!%SzWI#H%q
524
z=bSrQ&)%JCRttF5g4Zf`6l?y@>PzD7MA^D>wBlcH6r1ucwJ<p0O%rZ?JzIY3-QdmZ
525
zzs|n>`a5r3e|z)wcUaqS>nqFQ-8x}eCF4u`OWUxqst-@1rSmUs%WmKP5e0dcb?e2N
526
z;Z|x*!);VwF|Yuhqs^khqOM!@u*jY!WYldISF(V6`BoNd&6Qfk3>X#SuD^7J>p_D=
527
zBPa51y^_n#=cpOt#Zf$ya$Ae9Mfz56n|<i!a=ELS@)%a{^NIH3SDuN<R~sah1km#P
528
zU@?*f%<rG=4W1wgfi;C?_n|W@%lm$&8YfvNOJodIg&IcIpIJQRHr<+ej11GQ6)&eF
529
z2Lam*jIH}#y0>KnY%4JQfOYS$*uU%f#@$U6`N8I3N-lV?5ErFCdv~xDmu2(wexld4
530
z4v^;aVAT2k6GJ^m*FD(Wqc(Qg^)6a<?}h$zLoj}4;PP!+(O{@!a1y-hoAhF_7!z+6
531
zslpAmNtYbjHrw-~#SPVk_FUf>-Obg6yV`8o$8_`PyJe_;bY5_EMBfBfWU!Q=*9HsG
532
z%_Cda{@_Krr!oHVhv9+y+T5qR8zZ2aZ>5r!$*|f$^U%yBUYfR&B!+EYy_PwL!BeUi
533
zJH^}r3r9Q+B)X@Z)fk=P13w&7x#wBtXTZ)g>WITPg5r&pQc!nmyrmk#S(>>b9xnNr
534
zx_b#v9Xv-Y><Wb%?S^0Xe&<)bbKl_=Z|3C$tf|F<bYzE*mfHB;uC)`q-?buaBe?l?
535
zcLTpK*k<49Z32`K?|nSBMFqxTK^_IE-li2fEGdK~(ZdoKBl6ab4a;Hler#`xvEXJG
536
zb?<E%EZExfX>jcOVhS*0rS~RS1dA#xhkv@Nct@#q?LyeKS<$uFec!bw>{@uu$gZ6a
537
zyVen1i{1BKd%~`D7|m$;U0a<I*3I7%^N%N%lGYdU_GS!gaR8T$NA@GzFi~z`l7hdl
538
zarZy6590|88pi(1zq;V(>38zM0sT&<zX;R5$1w3;`_JMG`;&I&0Y23DMx1%@(w(R9
539
z4M$j;D5J+Gy%fijRQsctzFKf&cv|BAz#YLq3CZJWDdtL4u1u1|mkdcUp7|sxJC+?Y
540
z_@@s`v3j}Q7*z>6X~cwUxUL8G1KT)_XTp!KAbs;vCp{K3&~_X@+ew=-D}v`2MbFV0
541
zQsVsL=rXi-pI*G|iiz;VTCutgUs)hDzV1+4?8KcoP3xROf<M%qC6lgVdpFt4<-|uM
542
z=#rl_b1#YjSIl6Toj2z_hOZcKupkdE(LozC(fN=FY(x|sk)ym|;Rq2E1xJWD%Z!ol
543
Gu>S+TT-130
544
545
literal 0
546
HcmV?d00001
547
548
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
549
index XXXXXXX..XXXXXXX 100644
550
GIT binary patch
551
literal 112
552
zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj
553
Q0Zb)W9Hva*zW_`e0M!8s0RR91
554
555
literal 0
556
HcmV?d00001
557
47
--
558
--
48
2.16.2
559
2.25.1
49
560
50
561
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
A bunch of the vectorised bitwise operations just operate on larger
3
The VIOT blob contains the following:
4
chunks at a time. We can do the same for the new half-precision
5
operations by introducing some TWOHALFOP helpers which work on each
6
half of a pair of half-precision operations at once.
7
4
8
Hopefully all this hoop jumping will get simpler once we have
5
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
9
generically vectorised helpers here.
6
[004h 0004 4] Table Length : 00000058
7
[008h 0008 1] Revision : 00
8
[009h 0009 1] Checksum : 66
9
[00Ah 0010 6] Oem ID : "BOCHS "
10
[010h 0016 8] Oem Table ID : "BXPC "
11
[018h 0024 4] Oem Revision : 00000001
12
[01Ch 0028 4] Asl Compiler ID : "BXPC"
13
[020h 0032 4] Asl Compiler Revision : 00000001
10
14
11
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
15
[024h 0036 2] Node count : 0002
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
[026h 0038 2] Node offset : 0030
13
Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
17
[028h 0040 8] Reserved : 0000000000000000
18
19
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
20
[031h 0049 1] Reserved : 00
21
[032h 0050 2] Length : 0010
22
23
[034h 0052 2] PCI Segment : 0000
24
[036h 0054 2] PCI BDF number : 0008
25
[038h 0056 8] Reserved : 0000000000000000
26
27
[040h 0064 1] Type : 01 [PCI Range]
28
[041h 0065 1] Reserved : 00
29
[042h 0066 2] Length : 0018
30
31
[044h 0068 4] Endpoint start : 00000000
32
[048h 0072 2] PCI Segment start : 0000
33
[04Ah 0074 2] PCI Segment end : 0000
34
[04Ch 0076 2] PCI BDF start : 0000
35
[04Eh 0078 2] PCI BDF end : 00FF
36
[050h 0080 2] Output node : 0030
37
[052h 0082 6] Reserved : 000000000000
38
39
Acked-by: Ani Sinha <ani@anisinha.ca>
40
Reviewed-by: Eric Auger <eric.auger@redhat.com>
41
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
42
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
44
---
16
target/arm/helper-a64.h | 10 ++++++++++
45
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
17
target/arm/helper-a64.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
46
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
18
target/arm/translate-a64.c | 26 +++++++++++++++++++++-----
47
2 files changed, 1 deletion(-)
19
3 files changed, 76 insertions(+), 6 deletions(-)
20
48
21
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
49
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
22
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper-a64.h
51
--- a/tests/qtest/bios-tables-test-allowed-diff.h
24
+++ b/target/arm/helper-a64.h
52
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
25
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
53
@@ -1,2 +1 @@
26
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
54
/* List of comma-separated changed AML files to ignore */
27
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
55
-"tests/data/acpi/virt/VIOT",
28
DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
56
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
29
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
30
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
31
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
32
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
33
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
34
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
35
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
36
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
37
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
38
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
39
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
40
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper-a64.c
58
GIT binary patch
42
+++ b/target/arm/helper-a64.c
59
literal 88
43
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
60
zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX
44
ADVSIMD_HALFOP(minnum)
61
I{D-Rq0Q5fy0RR91
45
ADVSIMD_HALFOP(maxnum)
62
46
63
literal 0
47
+#define ADVSIMD_TWOHALFOP(name) \
64
HcmV?d00001
48
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
65
49
+{ \
50
+ float16 a1, a2, b1, b2; \
51
+ uint32_t r1, r2; \
52
+ float_status *fpst = fpstp; \
53
+ a1 = extract32(two_a, 0, 16); \
54
+ a2 = extract32(two_a, 16, 16); \
55
+ b1 = extract32(two_b, 0, 16); \
56
+ b2 = extract32(two_b, 16, 16); \
57
+ r1 = float16_ ## name(a1, b1, fpst); \
58
+ r2 = float16_ ## name(a2, b2, fpst); \
59
+ return deposit32(r1, 16, 16, r2); \
60
+}
61
+
62
+ADVSIMD_TWOHALFOP(add)
63
+ADVSIMD_TWOHALFOP(sub)
64
+ADVSIMD_TWOHALFOP(mul)
65
+ADVSIMD_TWOHALFOP(div)
66
+ADVSIMD_TWOHALFOP(min)
67
+ADVSIMD_TWOHALFOP(max)
68
+ADVSIMD_TWOHALFOP(minnum)
69
+ADVSIMD_TWOHALFOP(maxnum)
70
+
71
/* Data processing - scalar floating-point and advanced SIMD */
72
-float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
73
+static float16 float16_mulx(float16 a, float16 b, void *fpstp)
74
{
75
float_status *fpst = fpstp;
76
77
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
78
return float16_mul(a, b, fpst);
79
}
80
81
+ADVSIMD_HALFOP(mulx)
82
+ADVSIMD_TWOHALFOP(mulx)
83
+
84
/* fused multiply-accumulate */
85
float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
86
{
87
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
88
return float16_muladd(a, b, c, 0, fpst);
89
}
90
91
+uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
92
+ uint32_t two_c, void *fpstp)
93
+{
94
+ float_status *fpst = fpstp;
95
+ float16 a1, a2, b1, b2, c1, c2;
96
+ uint32_t r1, r2;
97
+ a1 = extract32(two_a, 0, 16);
98
+ a2 = extract32(two_a, 16, 16);
99
+ b1 = extract32(two_b, 0, 16);
100
+ b2 = extract32(two_b, 16, 16);
101
+ c1 = extract32(two_c, 0, 16);
102
+ c2 = extract32(two_c, 16, 16);
103
+ r1 = float16_muladd(a1, b1, c1, 0, fpst);
104
+ r2 = float16_muladd(a2, b2, c2, 0, fpst);
105
+ return deposit32(r1, 16, 16, r2);
106
+}
107
+
108
/*
109
* Floating point comparisons produce an integer result. Softfloat
110
* routines return float_relation types which we convert to the 0/-1
111
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/translate-a64.c
114
+++ b/target/arm/translate-a64.c
115
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
116
* multiply-add */
117
tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
118
}
119
- gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
120
- tcg_res, fpst);
121
+ if (is_scalar) {
122
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
123
+ tcg_res, fpst);
124
+ } else {
125
+ gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
126
+ tcg_res, fpst);
127
+ }
128
break;
129
case 2:
130
if (opcode == 0x5) {
131
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
132
switch (size) {
133
case 1:
134
if (u) {
135
- gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
136
- fpst);
137
+ if (is_scalar) {
138
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op,
139
+ tcg_idx, fpst);
140
+ } else {
141
+ gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
142
+ tcg_idx, fpst);
143
+ }
144
} else {
145
- g_assert_not_reached();
146
+ if (is_scalar) {
147
+ gen_helper_advsimd_mulh(tcg_res, tcg_op,
148
+ tcg_idx, fpst);
149
+ } else {
150
+ gen_helper_advsimd_mul2h(tcg_res, tcg_op,
151
+ tcg_idx, fpst);
152
+ }
153
}
154
break;
155
case 2:
156
--
66
--
157
2.16.2
67
2.25.1
158
68
159
69
diff view generated by jsdifflib