Series comparison

-[Qemu-devel] [PULL 00/42] target-arm queue
+[PULL 00/24] target-arm queue
-Arm queue -- I have more stuff pending but I prefer to push
+The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
 this first lot out and keep the pull below 50 patches.
 Most of this is Alex's FP16 support work.
--- PMM
+  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
 The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:
   Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
-for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:
+for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
-  MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)
+  target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * update MAINTAINERS for Alistair's new email address
+ * more MVE instructions
- * add Arm v8.2 FP16 arithmetic extension for linux-user
+ * hw/gpio/gpio_pwr: use shutdown function for reboot
- * implement display connector emulation for vexpress board
+ * target/arm: Check NaN mode before silencing NaN
- * xilinx_spips: Enable only two slaves when reading/writing with stripe
+ * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
- * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
+ * hw/arm: Add basic power management to raspi.
- * hw: register: Run post_write hook on reset
+ * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
 ----------------------------------------------------------------
-Alex Bennée (31):
+Joe Komlodi (1):
-      include/exec/helper-head.h: support f16 in helper calls
+      target/arm: Check NaN mode before silencing NaN
       target/arm/cpu64: introduce ARM_V8_FP16 feature bit
       target/arm/cpu.h: update comment for half-precision values
       target/arm/cpu.h: add additional float_status flags
       target/arm/helper: pass explicit fpst to set_rmode
       arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
       arm/translate-a64: handle_3same_64 comment fix
       arm/translate-a64: initial decode for simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
       arm/translate-a64: add FP16 x2 ops for simd_indexed
       arm/translate-a64: initial decode for simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
       arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
       arm/helper.c: re-factor recpe and add recepe_f16
       arm/translate-a64: add FP16 FRECPE
       arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
       arm/helper.c: re-factor rsqrte and add rsqrte_f16
       arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FMOV to simd_mod_imm
       arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
       arm/translate-a64: implement simd_scalar_three_reg_same_fp16
       arm/translate-a64: add all single op FP16 to handle_fp_1src_half
-Alistair Francis (2):
+Maxim Uvarov (1):
-      hw: register: Run post_write hook on reset
+      hw/gpio/gpio_pwr: use shutdown function for reboot
       MAINTAINERS: Update my email address
-Corey Minyard (2):
+Nolan Leake (1):
-      i2c: Fix some brace style issues
+      hw/arm: Add basic power management to raspi.
       i2c: Move the bus class to i2c.h
-Francisco Iglesias (2):
+Patrick Venture (2):
-      xilinx_spips: Enable only two slaves when reading/writing with stripe
+      docs/system/arm: Add quanta-q7l1-bmc reference
-      xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
+      docs/system/arm: Add quanta-gbs-bmc reference
-Linus Walleij (3):
+Peter Maydell (18):
-      hw/i2c-ddc: Do not fail writes
+      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
-      hw/sii9022: Add support for Silicon Image SII9022
+      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
-      arm/vexpress: Add proper display connector emulation
+      target/arm: Make asimd_imm_const() public
       target/arm: Use asimd_imm_const for A64 decode
       target/arm: Use dup_const() instead of bitfield_replicate()
       target/arm: Implement MVE logical immediate insns
       target/arm: Implement MVE vector shift left by immediate insns
       target/arm: Implement MVE vector shift right by immediate insns
       target/arm: Implement MVE VSHLL
       target/arm: Implement MVE VSRI, VSLI
       target/arm: Implement MVE VSHRN, VRSHRN
       target/arm: Implement MVE saturating narrowing shifts
       target/arm: Implement MVE VSHLC
       target/arm: Implement MVE VADDLV
       target/arm: Implement MVE long shifts by immediate
       target/arm: Implement MVE long shifts by register
       target/arm: Implement MVE shifts by immediate
       target/arm: Implement MVE shifts by register
-Peter Maydell (2):
+Philippe Mathieu-Daudé (1):
-      target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
+      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
       linux-user: Report AArch64 FP16 support via hwcap bits
- hw/display/Makefile.objs        |    1 +
+ docs/system/arm/aspeed.rst             |   1 +
- include/exec/helper-head.h      |    3 +
+ docs/system/arm/nuvoton.rst            |   5 +-
- include/fpu/softfloat.h         |   18 +-
+ include/hw/arm/bcm2835_peripherals.h   |   3 +-
- include/hw/i2c/i2c.h            |   23 +-
+ include/hw/misc/bcm2835_powermgt.h     |  29 ++
- include/hw/register.h           |    6 +-
+ target/arm/helper-mve.h                | 108 +++++++
- target/arm/cpu.h                |   34 +-
+ target/arm/translate.h                 |  41 +++
- target/arm/helper-a64.h         |   33 +
+ target/arm/mve.decode                  | 177 ++++++++++-
- target/arm/helper.h             |   14 +-
+ target/arm/t32.decode                  |  71 ++++-
- hw/arm/vexpress.c               |    6 +-
+ hw/arm/bcm2835_peripherals.c           |  13 +-
- hw/core/register.c              |    8 +
+ hw/gpio/gpio_pwr.c                     |   2 +-
- hw/display/sii9022.c            |  191 ++++++
+ hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
- hw/i2c/core.c                   |   18 -
+ target/arm/helper-a64.c                |  12 +-
- hw/i2c/i2c-ddc.c                |    4 +-
+ target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
- hw/ssi/xilinx_spips.c           |   43 +-
+ target/arm/translate-a64.c             |  86 +-----
- linux-user/elfload.c            |    2 +
+ target/arm/translate-mve.c             | 261 +++++++++++++++-
- target/arm/cpu64.c              |    1 +
+ target/arm/translate-neon.c            |  81 -----
- target/arm/helper-a64.c         |  269 +++++++++
+ target/arm/translate.c                 | 327 +++++++++++++++++++-
- target/arm/helper.c             |  481 ++++++++-------
+ target/arm/vfp_helper.c                |  24 +-
- target/arm/translate-a64.c      | 1266 +++++++++++++++++++++++++++++++++------
+ hw/misc/meson.build                    |   1 +
- target/arm/translate.c          |   12 +-
+ tests/acceptance/boot_linux_console.py |  43 +++
- MAINTAINERS                     |   12 +-
+files changed, 1760 insertions(+), 209 deletions(-)
- default-configs/arm-softmmu.mak |    2 +
+ create mode 100644 include/hw/misc/bcm2835_powermgt.h
- hw/display/trace-events         |    5 +
+ create mode 100644 hw/misc/bcm2835_powermgt.c
 files changed, 1981 insertions(+), 471 deletions(-)
  create mode 100644 hw/display/sii9022.c

-[Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
+[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
-Now we have implemented FP16 we can enable it for the "any" CPU.
+From: Patrick Venture <venture@google.com>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Adds a line-item reference to the supported quanta-q71l-bmc aspeed
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+entry.
-[PMM: split out from an earlier patch in the series]
 Signed-off-by: Patrick Venture <venture@google.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 20210615192848.1065297-2-venture@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu64.c | 1 +
+ docs/system/arm/aspeed.rst | 1 +
 file changed, 1 insertion(+)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/docs/system/arm/aspeed.rst
-+++ b/target/arm/cpu64.c
++++ b/docs/system/arm/aspeed.rst
-@@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ etc.
-     set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
+ AST2400 SoC based machines :
-     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
-     set_feature(&cpu->env, ARM_FEATURE_CRC);
+ - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
-+    set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
++- ``quanta-q71l-bmc``      OpenBMC Quanta BMC
-     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
-     cpu->dcz_blocksize = 7; /*  512 bytes */
+ AST2500 SoC based machines :
- }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 42/42] MAINTAINERS: Update my email address
+[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
-From: Alistair Francis <alistair.francis@xilinx.com>
+From: Patrick Venture <venture@google.com>
-I am leaving Xilinx, so to avoid having an email address that bounces
+Add line item reference to quanta-gbs-bmc machine.
 update my maintainer address to point to my personal email address.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Patrick Venture <venture@google.com>
-Signed-off-by: Alistair Francis <alistair@alistair23.me>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20210615192848.1065297-3-venture@google.com
-Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com
+[PMM: fixed underline Sphinx warning]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- MAINTAINERS | 12 ++++++------
+ docs/system/arm/nuvoton.rst | 5 +++--
-file changed, 6 insertions(+), 6 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/docs/system/arm/nuvoton.rst
-+++ b/MAINTAINERS
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ F: hw/misc/arm_sysctl.c
+@@ -XXX,XX +XXX,XX @@
+-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
- Xilinx Zynq
+-=====================================================
- M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
++Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
--M: Alistair Francis <alistair.francis@xilinx.com>
++================================================================
-+M: Alistair Francis <alistair@alistair23.me>
- L: qemu-arm@nongnu.org
+ The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
- S: Maintained
+ designed to be used as Baseboard Management Controllers (BMCs) in various
- F: hw/*/xilinx_*
+@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
-@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/zynq*
+ The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
- X: hw/ssi/xilinx_*
+ Hyperscale applications. The following machines are based on this chip :
- Xilinx ZynqMP
++- ``quanta-gbs-bmc``    Quanta GBS server BMC
--M: Alistair Francis <alistair.francis@xilinx.com>
+ - ``quanta-gsj``        Quanta GSJ server BMC
-+M: Alistair Francis <alistair@alistair23.me>
- M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+ There are also two more SoCs, NPCM710 and NPCM705, which are single-core
  L: qemu-arm@nongnu.org
  S: Maintained
@@ -XXX,XX +XXX,XX @@ T: git git://github.com/bonzini/qemu.git scsi-next
  SSI
  M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
 -M: Alistair Francis <alistair.francis@xilinx.com>
 +M: Alistair Francis <alistair@alistair23.me>
  S: Maintained
  F: hw/ssi/*
  F: hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
  F: tests/m25p80-test.c
  Xilinx SPI
 -M: Alistair Francis <alistair.francis@xilinx.com>
 +M: Alistair Francis <alistair@alistair23.me>
  M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
  S: Maintained
  F: hw/ssi/xilinx_*
@@ -XXX,XX +XXX,XX @@ S: Maintained
  F: hw/net/eepro100.c
  Generic Loader
 -M: Alistair Francis <alistair.francis@xilinx.com>
 +M: Alistair Francis <alistair@alistair23.me>
  S: Maintained
  F: hw/core/generic-loader.c
  F: include/hw/core/generic-loader.h
@@ -XXX,XX +XXX,XX @@ F: tests/qmp-test.c
  T: git git://repo.or.cz/qemu/armbru.git qapi-next
  Register API
 -M: Alistair Francis <alistair.francis@xilinx.com>
 +M: Alistair Francis <alistair@alistair23.me>
  S: Maintained
  F: hw/core/register.c
  F: include/hw/register.h
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 07/42] hw/sii9022: Add support for Silicon Image SII9022
+[PULL 03/24] hw/arm: Add basic power management to raspi.
-From: Linus Walleij <linus.walleij@linaro.org>
+From: Nolan Leake <nolan@sigbus.net>
-This adds support for emulating the Silicon Image SII9022 DVI/HDMI
+This is just enough to make reboot and poweroff work. Works for
-bridge. It's not very clever right now, it just acknowledges
+linux, u-boot, and the arm trusted firmware. Not tested, but should
-the switch into DDC I2C mode and back. Combining this with the
+work for plan9, and bare-metal/hobby OSes, since they seem to generally
-existing DDC I2C emulation gives the right behavior on the Versatile
+do what linux does for reset.
-Express emulation passing through the QEMU EDID to the emulated
-platform.
+The watchdog timer functionality is not yet implemented.
-Cc: Peter Maydell <peter.maydell@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Nolan Leake <nolan@sigbus.net>
-Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
+Message-id: 20210625210209.1870217-1-nolan@sigbus.net
 [PMM: tweaked commit title; fixed region size to 0x200;
  moved header file to include/]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/display/Makefile.objs |   1 +
+ include/hw/arm/bcm2835_peripherals.h |   3 +-
- hw/display/sii9022.c     | 191 +++++++++++++++++++++++++++++++++++++++++++++++
+ include/hw/misc/bcm2835_powermgt.h   |  29 +++++
- hw/display/trace-events  |   5 ++
+ hw/arm/bcm2835_peripherals.c         |  13 ++-
-files changed, 197 insertions(+)
+ hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
- create mode 100644 hw/display/sii9022.c
+ hw/misc/meson.build                  |   1 +
+files changed, 204 insertions(+), 2 deletions(-)
-diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
+ create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/display/Makefile.objs
+--- a/include/hw/arm/bcm2835_peripherals.h
-+++ b/hw/display/Makefile.objs
++++ b/include/hw/arm/bcm2835_peripherals.h
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
+@@ -XXX,XX +XXX,XX @@
- common-obj-$(CONFIG_G364FB) += g364fb.o
+ #include "hw/misc/bcm2835_mphi.h"
- common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
+ #include "hw/misc/bcm2835_thermal.h"
- common-obj-$(CONFIG_PL110) += pl110.o
+ #include "hw/misc/bcm2835_cprman.h"
-+common-obj-$(CONFIG_SII9022) += sii9022.o
++#include "hw/misc/bcm2835_powermgt.h"
- common-obj-$(CONFIG_SSD0303) += ssd0303.o
+ #include "hw/sd/sdhci.h"
- common-obj-$(CONFIG_SSD0323) += ssd0323.o
+ #include "hw/sd/bcm2835_sdhost.h"
- common-obj-$(CONFIG_XEN) += xenfb.o
+ #include "hw/gpio/bcm2835_gpio.h"
-diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
+@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
      BCM2835MphiState mphi;
      UnimplementedDeviceState txp;
      UnimplementedDeviceState armtmr;
 -    UnimplementedDeviceState powermgt;
 +    BCM2835PowerMgtState powermgt;
      BCM2835CprmanState cprman;
      PL011State uart0;
      BCM2835AuxState aux;
 diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/display/sii9022.c
++++ b/include/hw/misc/bcm2835_powermgt.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Silicon Image SiI9022
++ * BCM2835 Power Management emulation
 + *
-+ * This is a pretty hollow emulation: all we do is acknowledge that we
++ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
-+ * exist (chip ID) and confirm that we get switched over into DDC mode
++ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
 + * so the emulated host can proceed to read out EDID data. All subsequent
 + * set-up of connectors etc will be acknowledged and ignored.
 + *
 + * Copyright (C) 2018 Linus Walleij
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
-+ * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
++#ifndef BCM2835_POWERMGT_H
++#define BCM2835_POWERMGT_H
++
++#include "hw/sysbus.h"
++#include "qom/object.h"
++
++#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
++OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
++
++struct BCM2835PowerMgtState {
++    SysBusDevice busdev;
++    MemoryRegion iomem;
++
++    uint32_t rstc;
++    uint32_t rsts;
++    uint32_t wdog;
++};
++
++#endif
+diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/bcm2835_peripherals.c
++++ b/hw/arm/bcm2835_peripherals.c
+@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
+     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
+                                    OBJECT(&s->gpu_bus_mr));
++
++    /* Power Management */
++    object_initialize_child(obj, "powermgt", &s->powermgt,
++                            TYPE_BCM2835_POWERMGT);
+ }
+ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+                                INTERRUPT_USB));
++    /* Power Management */
++    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
++        return;
++    }
++
++    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
++                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
++
+     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
+     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
+-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
+     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
+     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
+     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
+diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/misc/bcm2835_powermgt.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * BCM2835 Power Management emulation
++ *
++ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
++ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
++ *
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * See the COPYING file in the top-level directory.
++ */
++
 +#include "qemu/osdep.h"
-+#include "qemu-common.h"
++#include "qemu/log.h"
-+#include "hw/i2c/i2c.h"
++#include "qemu/module.h"
-+#include "hw/i2c/i2c-ddc.h"
++#include "hw/misc/bcm2835_powermgt.h"
-+#include "trace.h"
++#include "migration/vmstate.h"
-+
++#include "sysemu/runstate.h"
-+#define SII9022_SYS_CTRL_DATA 0x1a
++
-+#define SII9022_SYS_CTRL_PWR_DWN 0x10
++#define PASSWORD 0x5a000000
-+#define SII9022_SYS_CTRL_AV_MUTE 0x08
++#define PASSWORD_MASK 0xff000000
-+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
++
-+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
++#define R_RSTC 0x1c
-+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
++#define V_RSTC_RESET 0x20
-+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
++#define R_RSTS 0x20
-+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
++#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
-+#define SII9022_REG_CHIPID 0x1b
++#define R_WDOG 0x24
-+#define SII9022_INT_ENABLE 0x3c
++
-+#define SII9022_INT_STATUS 0x3d
++static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
-+#define SII9022_INT_STATUS_HOTPLUG 0x01;
++                                      unsigned size)
-+#define SII9022_INT_STATUS_PLUGGED 0x04;
++{
-+
++    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
-+#define TYPE_SII9022 "sii9022"
++    uint32_t res = 0;
-+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
++
-+
++    switch (offset) {
-+typedef struct sii9022_state {
++    case R_RSTC:
-+    I2CSlave parent_obj;
++        res = s->rstc;
-+    uint8_t ptr;
++        break;
-+    bool addr_byte;
++    case R_RSTS:
-+    bool ddc_req;
++        res = s->rsts;
-+    bool ddc_skip_finish;
++        break;
-+    bool ddc;
++    case R_WDOG:
-+} sii9022_state;
++        res = s->wdog;
-+
++        break;
-+static const VMStateDescription vmstate_sii9022 = {
++
-+    .name = "sii9022",
++    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
 +                      "\n", offset);
 +        res = 0;
 +        break;
 +    }
 +
 +    return res;
 +}
 +
 +static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
 +                                   uint64_t value, unsigned size)
 +{
 +    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +
 +    if ((value & PASSWORD_MASK) != PASSWORD) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
 +                      " at offset 0x%08"HWADDR_PRIx"\n",
 +                      value, offset);
 +        return;
 +    }
 +
 +    value = value & ~PASSWORD_MASK;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        s->rstc = value;
 +        if (value & V_RSTC_RESET) {
 +            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
 +                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 +            } else {
 +                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 +            }
 +        }
 +        break;
 +    case R_RSTS:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: RSTS\n");
 +        s->rsts = value;
 +        break;
 +    case R_WDOG:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: WDOG\n");
 +        s->wdog = value;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
 +                      "\n", offset);
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps bcm2835_powermgt_ops = {
 +    .read = bcm2835_powermgt_read,
 +    .write = bcm2835_powermgt_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +};
 +
 +static const VMStateDescription vmstate_bcm2835_powermgt = {
 +    .name = TYPE_BCM2835_POWERMGT,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
-+        VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
++        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
-+        VMSTATE_UINT8(ptr, sii9022_state),
++        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
-+        VMSTATE_BOOL(addr_byte, sii9022_state),
++        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
 +        VMSTATE_BOOL(ddc_req, sii9022_state),
 +        VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
 +        VMSTATE_BOOL(ddc, sii9022_state),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
-+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
++static void bcm2835_powermgt_init(Object *obj)
 +{
-+    sii9022_state *s = SII9022(i2c);
++    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
 +
-+    switch (event) {
++    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
-+    case I2C_START_SEND:
++                          TYPE_BCM2835_POWERMGT, 0x200);
-+        s->addr_byte = true;
++    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
-+        break;
++}
-+    case I2C_START_RECV:
++
-+        break;
++static void bcm2835_powermgt_reset(DeviceState *dev)
-+    case I2C_FINISH:
++{
-+        break;
++    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
-+    case I2C_NACK:
++
-+        break;
++    /* https://elinux.org/BCM2835_registers#PM */
-+    }
++    s->rstc = 0x00000102;
-+
++    s->rsts = 0x00001000;
-+    return 0;
++    s->wdog = 0x00000000;
 +}
 +
-+static int sii9022_rx(I2CSlave *i2c)
++static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
 +{
 +    sii9022_state *s = SII9022(i2c);
 +    uint8_t res = 0x00;
 +
 +    switch (s->ptr) {
 +    case SII9022_SYS_CTRL_DATA:
 +        if (s->ddc_req) {
 +            /* Acknowledge DDC bus request */
 +            res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
 +        }
 +        break;
 +    case SII9022_REG_CHIPID:
 +        res = 0xb0;
 +        break;
 +    case SII9022_INT_STATUS:
 +        /* Something is cold-plugged in, no interrupts */
 +        res = SII9022_INT_STATUS_PLUGGED;
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_sii9022_read_reg(s->ptr, res);
 +    s->ptr++;
 +
 +    return res;
 +}
 +
 +static int sii9022_tx(I2CSlave *i2c, uint8_t data)
 +{
 +    sii9022_state *s = SII9022(i2c);
 +
 +    if (s->addr_byte) {
 +        s->ptr = data;
 +        s->addr_byte = false;
 +        return 0;
 +    }
 +
 +    switch (s->ptr) {
 +    case SII9022_SYS_CTRL_DATA:
 +        if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
 +            s->ddc_req = true;
 +            if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
 +                s->ddc = true;
 +                /* Skip this finish since we just switched to DDC */
 +                s->ddc_skip_finish = true;
 +                trace_sii9022_switch_mode("DDC");
 +            }
 +        } else {
 +            s->ddc_req = false;
 +            s->ddc = false;
 +            trace_sii9022_switch_mode("normal");
 +        }
 +        break;
 +    default:
 +        break;
 +    }
 +
 +    trace_sii9022_write_reg(s->ptr, data);
 +    s->ptr++;
 +
 +    return 0;
 +}
 +
 +static void sii9022_reset(DeviceState *dev)
 +{
 +    sii9022_state *s = SII9022(dev);
 +
 +    s->ptr = 0;
 +    s->addr_byte = false;
 +    s->ddc_req = false;
 +    s->ddc_skip_finish = false;
 +    s->ddc = false;
 +}
 +
 +static void sii9022_realize(DeviceState *dev, Error **errp)
 +{
 +    I2CBus *bus;
 +
 +    bus = I2C_BUS(qdev_get_parent_bus(dev));
 +    i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
 +}
 +
 +static void sii9022_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
-+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
++
-+
++    dc->reset = bcm2835_powermgt_reset;
-+    k->event = sii9022_event;
++    dc->vmsd = &vmstate_bcm2835_powermgt;
-+    k->recv = sii9022_rx;
++}
-+    k->send = sii9022_tx;
++
-+    dc->reset = sii9022_reset;
++static TypeInfo bcm2835_powermgt_info = {
-+    dc->realize = sii9022_realize;
++    .name          = TYPE_BCM2835_POWERMGT,
-+    dc->vmsd = &vmstate_sii9022;
++    .parent        = TYPE_SYS_BUS_DEVICE,
-+}
++    .instance_size = sizeof(BCM2835PowerMgtState),
-+
++    .class_init    = bcm2835_powermgt_class_init,
-+static const TypeInfo sii9022_info = {
++    .instance_init = bcm2835_powermgt_init,
-+    .name          = TYPE_SII9022,
++};
-+    .parent        = TYPE_I2C_SLAVE,
++
-+    .instance_size = sizeof(sii9022_state),
++static void bcm2835_powermgt_register_types(void)
-+    .class_init    = sii9022_class_init,
++{
-+};
++    type_register_static(&bcm2835_powermgt_info);
-+
++}
-+static void sii9022_register_types(void)
++
-+{
++type_init(bcm2835_powermgt_register_types)
-+    type_register_static(&sii9022_info);
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 +}
 +
 +type_init(sii9022_register_types)
 diff --git a/hw/display/trace-events b/hw/display/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/display/trace-events
+--- a/hw/misc/meson.build
-+++ b/hw/display/trace-events
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
- vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
+   'bcm2835_rng.c',
- vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
+   'bcm2835_thermal.c',
- vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
+   'bcm2835_cprman.c',
-+
++  'bcm2835_powermgt.c',
-+# hw/display/sii9022.c
+ ))
-+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
-+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+ softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
 +sii9022_switch_mode(const char *mode) "mode: %s"
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 39/42] arm/translate-a64: add all single op FP16 to handle_fp_1src_half
+[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-This includes FMOV, FABS, FNEG, FSQRT and  FRINT[NPMZAXI]. We re-use
+Add a test booting and quickly shutdown a raspi2 machine,
-existing helpers to achieve this.
+to test the power management model:
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+   (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+  console: [    0.000000] Booting Linux on physical CPU 0xf00
-Message-id: 20180227143852.11175-32-alex.bennee@linaro.org
+  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
   console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
   console: [    0.000000] CPU: div instructions available: patching division code
   console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
   console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
   ...
   console: Boot successful.
   console: cat /proc/cpuinfo
   console: / # cat /proc/cpuinfo
   ...
   console: processor      : 3
   console: model name     : ARMv7 Processor rev 5 (v7l)
   console: BogoMIPS       : 125.00
   console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
   console: CPU implementer        : 0x41
   console: CPU architecture: 7
   console: CPU variant    : 0x0
   console: CPU part       : 0xc07
   console: CPU revision   : 5
   console: Hardware       : BCM2835
   console: Revision       : 0000
   console: Serial         : 0000000000000000
   console: cat /proc/iomem
   console: / # cat /proc/iomem
   console: 00000000-3bffffff : System RAM
   console: 00008000-00afffff : Kernel code
   console: 00c00000-00d468ef : Kernel data
   console: 3f006000-3f006fff : dwc_otg
   console: 3f007000-3f007eff : /soc/dma@7e007000
   console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
   console: 3f100000-3f100027 : /soc/watchdog@7e100000
   console: 3f101000-3f102fff : /soc/cprman@7e101000
   console: 3f200000-3f2000b3 : /soc/gpio@7e200000
   PASS (24.59 s)
   RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
   JOB TIME   : 25.02 s
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
 Message-id: 20210531113837.1689775-1-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
+ tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
-file changed, 71 insertions(+)
+file changed, 43 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/tests/acceptance/boot_linux_console.py
-+++ b/target/arm/translate-a64.c
++++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@
-     tcg_temp_free_i64(t_true);
+ from avocado import skip
- }
+ from avocado import skipUnless
+ from avocado_qemu import Test
-+/* Floating-point data-processing (1 source) - half precision */
++from avocado_qemu import exec_command
-+static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
+ from avocado_qemu import exec_command_and_wait_for_pattern
-+{
+ from avocado_qemu import interrupt_interactive_console_until_pattern
-+    TCGv_ptr fpst = NULL;
+ from avocado_qemu import wait_for_console_pattern
-+    TCGv_i32 tcg_op = tcg_temp_new_i32();
+@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
-+    TCGv_i32 tcg_res = tcg_temp_new_i32();
+         """
          self.do_test_arm_raspi2(0)
 +    def test_arm_raspi2_initrd(self):
 +        """
 +        :avocado: tags=arch:arm
 +        :avocado: tags=machine:raspi2
 +        """
 +        deb_url = ('http://archive.raspberrypi.org/debian/'
 +                   'pool/main/r/raspberrypi-firmware/'
 +                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
 +        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
 +        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
 +        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
 +        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
 +
-+    read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
++        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
 +                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
 +                      'arm/rootfs-armv7a.cpio.gz')
 +        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
 +        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
 +        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
 +        archive.gzip_uncompress(initrd_path_gz, initrd_path)
 +
-+    switch (opcode) {
++        self.vm.set_console()
-+    case 0x0: /* FMOV */
++        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-+        tcg_gen_mov_i32(tcg_res, tcg_op);
++                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
-+        break;
++                               'panic=-1 noreboot ' +
-+    case 0x1: /* FABS */
++                               'dwc_otg.fiq_fsm_enable=0')
-+        tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
++        self.vm.add_args('-kernel', kernel_path,
-+        break;
++                         '-dtb', dtb_path,
-+    case 0x2: /* FNEG */
++                         '-initrd', initrd_path,
-+        tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
++                         '-append', kernel_command_line,
-+        break;
++                         '-no-reboot')
-+    case 0x3: /* FSQRT */
++        self.vm.launch()
-+        gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
++        self.wait_for_console_pattern('Boot successful.')
 +        break;
 +    case 0x8: /* FRINTN */
 +    case 0x9: /* FRINTP */
 +    case 0xa: /* FRINTM */
 +    case 0xb: /* FRINTZ */
 +    case 0xc: /* FRINTA */
 +    {
 +        TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
 +        fpst = get_fpstatus_ptr(true);
 +
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
-+        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
++                                                'BCM2835')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
 +                                                '/soc/cprman@7e101000')
 +        exec_command(self, 'halt')
 +        # Wait for VM to shut down gracefully
 +        self.vm.wait()
 +
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+     def test_arm_exynos4210_initrd(self):
-+        tcg_temp_free_i32(tcg_rmode);
+         """
-+        break;
+         :avocado: tags=arch:arm
 +    }
 +    case 0xe: /* FRINTX */
 +        fpst = get_fpstatus_ptr(true);
 +        gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
 +        break;
 +    case 0xf: /* FRINTI */
 +        fpst = get_fpstatus_ptr(true);
 +        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
 +        break;
 +    default:
 +        abort();
 +    }
 +
 +    write_fp_sreg(s, rd, tcg_res);
 +
 +    if (fpst) {
 +        tcg_temp_free_ptr(fpst);
 +    }
 +    tcg_temp_free_i32(tcg_op);
 +    tcg_temp_free_i32(tcg_res);
 +}
 +
  /* Floating-point data-processing (1 source) - single precision */
  static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
  {
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
              handle_fp_1src_double(s, opcode, rd, rn);
              break;
 +        case 3:
 +            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +                unallocated_encoding(s);
 +                return;
 +            }
 +
 +            if (!fp_access_check(s)) {
 +                return;
 +            }
 +
 +            handle_fp_1src_half(s, opcode, rd, rn);
 +            break;
          default:
              unallocated_encoding(s);
          }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 17/42] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
+[PULL 05/24] target/arm: Check NaN mode before silencing NaN
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Joe Komlodi <joe.komlodi@xilinx.com>
-The fprintf is only there for debugging as the skeleton is added to,
+If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
-it will be removed once the skeleton is complete.
+FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
 assert due to fpst->default_nan_mode being set.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+To avoid this, we check to see what NaN mode we're running in before we call
 floatxx_silence_nan().
 Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
+Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.h    |  4 ++++
+ target/arm/helper-a64.c | 12 +++++++++---
- target/arm/helper-a64.c    |  4 ++++
+ target/arm/vfp_helper.c | 24 ++++++++++++++++++------
- target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++
+files changed, 27 insertions(+), 9 deletions(-)
 files changed, 36 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-a64.c
 +++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
-     return float16_ ## name(a, b, fpst);    \
+         float16 nan = a;
- }
+         if (float16_is_signaling_nan(a, fpst)) {
+             float_raise(float_flag_invalid, fpst);
-+ADVSIMD_HALFOP(add)
+-            nan = float16_silence_nan(a, fpst);
-+ADVSIMD_HALFOP(sub)
++            if (!fpst->default_nan_mode) {
-+ADVSIMD_HALFOP(mul)
++                nan = float16_silence_nan(a, fpst);
-+ADVSIMD_HALFOP(div)
++            }
- ADVSIMD_HALFOP(min)
+         }
- ADVSIMD_HALFOP(max)
+         if (fpst->default_nan_mode) {
- ADVSIMD_HALFOP(minnum)
+             nan = float16_default_nan(fpst);
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
          float32 nan = a;
          if (float32_is_signaling_nan(a, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float32_silence_nan(a, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float32_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
          float64 nan = a;
          if (float64_is_signaling_nan(a, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(a, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float64_default_nan(fpst);
 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/vfp_helper.c
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/vfp_helper.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
-         read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+         float16 nan = f16;
+         if (float16_is_signaling_nan(f16, fpst)) {
-         switch (fpopcode) {
+             float_raise(float_flag_invalid, fpst);
-+        case 0x0: /* FMAXNM */
+-            nan = float16_silence_nan(f16, fpst);
-+            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
++            if (!fpst->default_nan_mode) {
-+            break;
++                nan = float16_silence_nan(f16, fpst);
-+        case 0x2: /* FADD */
++            }
-+            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+         }
-+            break;
+         if (fpst->default_nan_mode) {
-+        case 0x6: /* FMAX */
+             nan =  float16_default_nan(fpst);
-+            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
-+            break;
+         float32 nan = f32;
-+        case 0x8: /* FMINNM */
+         if (float32_is_signaling_nan(f32, fpst)) {
-+            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+             float_raise(float_flag_invalid, fpst);
-+            break;
+-            nan = float32_silence_nan(f32, fpst);
-+        case 0xa: /* FSUB */
++            if (!fpst->default_nan_mode) {
-+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
++                nan = float32_silence_nan(f32, fpst);
-+            break;
++            }
-+        case 0xe: /* FMIN */
+         }
-+            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+         if (fpst->default_nan_mode) {
-+            break;
+             nan =  float32_default_nan(fpst);
-+        case 0x13: /* FMUL */
+@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
-+            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+         float64 nan = f64;
-+            break;
+         if (float64_is_signaling_nan(f64, fpst)) {
-+        case 0x17: /* FDIV */
+             float_raise(float_flag_invalid, fpst);
-+            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+-            nan = float64_silence_nan(f64, fpst);
-+            break;
++            if (!fpst->default_nan_mode) {
-+        case 0x1a: /* FABD */
++                nan = float64_silence_nan(f64, fpst);
-+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
++            }
-+            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
+         }
-+            break;
+         if (fpst->default_nan_mode) {
-         default:
+             nan =  float64_default_nan(fpst);
-             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
-                     __func__, insn, fpopcode, s->pc);
+         float16 nan = f16;
          if (float16_is_signaling_nan(f16, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float16_silence_nan(f16, s);
 +            if (!s->default_nan_mode) {
 +                nan = float16_silence_nan(f16, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float32_silence_nan(f32, s);
 +            if (!s->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float64_silence_nan(f64, s);
 +            if (!s->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float64_default_nan(s);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe
+[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
+From: Maxim Uvarov <maxim.uvarov@linaro.org>
-Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
+qemu has 2 type of functions: shutdown and reboot. Shutdown
-chip selects are enabled (e.g reading/writing with stripe).
+function has to be used for machine shutdown. Otherwise we cause
 a reset with a bogus "cause" value, when we intended a shutdown.
-Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Tested-by: Alistair Francis <alistair.francis@xilinx.com>
+Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
-Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com
+[PMM: tweaked commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++----
+ hw/gpio/gpio_pwr.c | 2 +-
-file changed, 37 insertions(+), 4 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/hw/gpio/gpio_pwr.c
-+++ b/hw/ssi/xilinx_spips.c
++++ b/hw/gpio/gpio_pwr.c
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
+@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
  static void gpio_pwr_shutdown(void *opaque, int n, int level)
  {
-     int i;
+     if (level) {
+-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
--    for (i = 0; i < s->num_cs; i++) {
++        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 +    for (i = 0; i < s->num_cs * s->num_busses; i++) {
          bool old_state = s->cs_lines_state[i];
          bool new_state = field & (1 << i);
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
          }
          qemu_set_irq(s->cs_lines[i], !new_state);
      }
 -    if (!(field & ((1 << s->num_cs) - 1))) {
 +    if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
          s->snoop_state = SNOOP_CHECKING;
          s->cmd_dummies = 0;
          s->link_state = 1;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
  {
      if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
          int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
 -        xilinx_spips_update_cs(XILINX_SPIPS(s), field);
 +        bool upper_cs_sel = field & (1 << 1);
 +        bool lower_cs_sel = field & 1;
 +        bool bus0_enabled;
 +        bool bus1_enabled;
 +        uint8_t buses;
 +        int cs = 0;
 +
 +        buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
 +        bus0_enabled = buses & 1;
 +        bus1_enabled = buses & (1 << 1);
 +
 +        if (bus0_enabled && bus1_enabled) {
 +            if (lower_cs_sel) {
 +                cs |= 1;
 +            }
 +            if (upper_cs_sel) {
 +                cs |= 1 << 3;
 +            }
 +        } else if (bus0_enabled) {
 +            if (lower_cs_sel) {
 +                cs |= 1;
 +            }
 +            if (upper_cs_sel) {
 +                cs |= 1 << 1;
 +            }
 +        } else if (bus1_enabled) {
 +            if (lower_cs_sel) {
 +                cs |= 1 << 2;
 +            }
 +            if (upper_cs_sel) {
 +                cs |= 1 << 3;
 +            }
 +        }
 +        xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
-     if (num_effective_busses(s) == 2) {
-         /* Single bit chip-select for qspi */
-         field &= 0x1;
--        field |= field << 1;
-+        field |= field << 3;
-     /* Dual stack U-Page */
-     } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
-                s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 14/42] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
+[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
-From: Alex Bennée <alex.bennee@linaro.org>
+In do_ldst(), the calculation of the offset needs to be based on the
 size of the memory access, not the size of the elements in the
 vector.  This meant we were getting it wrong for the widening and
 narrowing variants of the various VLDR and VSTR insns.
-This implements the half-precision variants of the across vector
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-reduction operations. This involves a re-factor of the reduction code
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-which more closely matches the ARM ARM order (and handles 8 element
+Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
-reductions).
+---
  target/arm/translate-mve.c | 17 +++++++++--------
 file changed, 9 insertions(+), 8 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper-a64.h    |   4 ++
  target/arm/helper-a64.c    |  18 ++++++
  target/arm/translate-a64.c | 140 ++++++++++++++++++++++++++++-----------------
 files changed, 109 insertions(+), 53 deletions(-)
 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
+--- a/target/arm/translate-mve.c
-+++ b/target/arm/helper-a64.h
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
+@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
  DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
  DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
                     i64, env, i64, i64, i64)
 +DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 +DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 +DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 +DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-a64.c
 +++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
  {
      return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
  }
 +
 +/*
 + * AdvSIMD half-precision
 + */
 +
 +#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
 +
 +#define ADVSIMD_HALFOP(name) \
 +float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
 +{ \
 +    float_status *fpst = fpstp; \
 +    return float16_ ## name(a, b, fpst);    \
 +}
 +
 +ADVSIMD_HALFOP(min)
 +ADVSIMD_HALFOP(max)
 +ADVSIMD_HALFOP(minnum)
 +ADVSIMD_HALFOP(maxnum)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_resh);
  }
 -static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
 -                        int opc, bool is_min, TCGv_ptr fpst)
 +/*
 + * do_reduction_op helper
 + *
 + * This mirrors the Reduce() pseudocode in the ARM ARM. It is
 + * important for correct NaN propagation that we do these
 + * operations in exactly the order specified by the pseudocode.
 + *
 + * This is a recursive function, TCG temps should be freed by the
 + * calling function once it is done with the values.
 + */
 +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
 +                                int esize, int size, int vmap, TCGv_ptr fpst)
  {
 -    /* Helper function for disas_simd_across_lanes: do a single precision
 -     * min/max operation on the specified two inputs,
 -     * and return the result in tcg_elt1.
 -     */
 -    if (opc == 0xc) {
 -        if (is_min) {
 -            gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
 -        } else {
 -            gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
 -        }
 +    if (esize == size) {
 +        int element;
 +        TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
 +        TCGv_i32 tcg_elem;
 +
 +        /* We should have one register left here */
 +        assert(ctpop8(vmap) == 1);
 +        element = ctz32(vmap);
 +        assert(element < 8);
 +
 +        tcg_elem = tcg_temp_new_i32();
 +        read_vec_element_i32(s, tcg_elem, rn, element, msize);
 +        return tcg_elem;
      } else {
 -        assert(opc == 0xf);
 -        if (is_min) {
 -            gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
 -        } else {
 -            gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
 +        int bits = size / 2;
 +        int shift = ctpop8(vmap) / 2;
 +        int vmap_lo = (vmap >> shift) & vmap;
 +        int vmap_hi = (vmap & ~vmap_lo);
 +        TCGv_i32 tcg_hi, tcg_lo, tcg_res;
 +
 +        tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
 +        tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
 +        tcg_res = tcg_temp_new_i32();
 +
 +        switch (fpopcode) {
 +        case 0x0c: /* fmaxnmv half-precision */
 +            gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x0f: /* fmaxv half-precision */
 +            gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x1c: /* fminnmv half-precision */
 +            gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x1f: /* fminv half-precision */
 +            gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x2c: /* fmaxnmv */
 +            gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x2f: /* fmaxv */
 +            gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x3c: /* fminnmv */
 +            gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        case 0x3f: /* fminv */
 +            gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
 +
 +        tcg_temp_free_i32(tcg_hi);
 +        tcg_temp_free_i32(tcg_lo);
 +        return tcg_res;
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
+-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
-         break;
++static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
-     case 0xc: /* FMAXNMV, FMINNMV */
++                    unsigned msize)
-     case 0xf: /* FMAXV, FMINV */
+ {
--        if (!is_u || !is_q || extract32(size, 0, 1)) {
+     TCGv_i32 addr;
--            unallocated_encoding(s);
+     uint32_t offset;
--            return;
+@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
--        }
+         return true;
 -        /* Bit 1 of size field encodes min vs max, and actual size is always
 -         * 32 bits: adjust the size variable so following code can rely on it
 +        /* Bit 1 of size field encodes min vs max and the actual size
 +         * depends on the encoding of the U bit. If not set (and FP16
 +         * enabled) then we do half-precision float instead of single
 +         * precision.
           */
          is_min = extract32(size, 1, 1);
          is_fp = true;
 -        size = 2;
 +        if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +            size = 1;
 +        } else if (!is_u || !is_q || extract32(size, 0, 1)) {
 +            unallocated_encoding(s);
 +            return;
 +        } else {
 +            size = 2;
 +        }
          break;
      default:
          unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
          }
      } else {
 -        /* Floating point ops which work on 32 bit (single) intermediates.
 +        /* Floating point vector reduction ops which work across 32
 +         * bit (single) or 16 bit (half-precision) intermediates.
           * Note that correct NaN propagation requires that we do these
           * operations in exactly the order specified by the pseudocode.
           */
 -        TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
 -        TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
 -        TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
 -        TCGv_ptr fpst = get_fpstatus_ptr(false);
 -
 -        assert(esize == 32);
 -        assert(elements == 4);
 -
 -        read_vec_element(s, tcg_elt, rn, 0, MO_32);
 -        tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
 -        read_vec_element(s, tcg_elt, rn, 1, MO_32);
 -        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
 -
 -        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
 -
 -        read_vec_element(s, tcg_elt, rn, 2, MO_32);
 -        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
 -        read_vec_element(s, tcg_elt, rn, 3, MO_32);
 -        tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
 -
 -        do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
 -
 -        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
 -
 -        tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
 -        tcg_temp_free_i32(tcg_elt1);
 -        tcg_temp_free_i32(tcg_elt2);
 -        tcg_temp_free_i32(tcg_elt3);
 +        TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
 +        int fpopcode = opcode | is_min << 4 | is_u << 5;
 +        int vmap = (1 << elements) - 1;
 +        TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
 +                                             (is_q ? 128 : 64), vmap, fpst);
 +        tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
 +        tcg_temp_free_i32(tcg_res32);
          tcg_temp_free_ptr(fpst);
      }
+-    offset = a->imm << a->size;
++    offset = a->imm << msize;
+     if (!a->a) {
+         offset = -offset;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
+         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
+         { NULL, NULL }
+     };
+-    return do_ldst(s, a, ldstfns[a->size][a->l]);
++    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
+ }
+-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
++#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
+     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
+     {                                                           \
+         static MVEGenLdStFn * const ldstfns[2][2] = {           \
+             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
+             { NULL, gen_helper_mve_##ULD },                     \
+         };                                                      \
+-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
++        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
+     }
+-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
+-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
+-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
++DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
++DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
++DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
+ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
+ {
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset
+[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
-From: Alistair Francis <alistair.francis@xilinx.com>
+The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
 insns had some bugs:
  * the 32x32 multiply of elements was being done as 32x32->32,
    not 32x32->64
  * we were incorrectly maintaining the accumulator in its full
 -bit form across all 4 beats of the insn; in the pseudocode
    it is squashed back into the 64 bits of the RdaHi:RdaLo
    registers after each beat
-Ensure that the post write hook is called during reset. This allows us
+In particular, fixing the second of these allows us to recast
-to rely on the post write functions instead of having to call them from
+the implementation to avoid 128-bit arithmetic entirely.
 the reset() function.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
+Since the element size here is always 4, we can also drop the
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+parameterization of ESIZE to make the code a little more readable.
-Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
 ---
- include/hw/register.h | 6 +++---
+ target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
- hw/core/register.c    | 8 ++++++++
+file changed, 21 insertions(+), 17 deletions(-)
 files changed, 11 insertions(+), 3 deletions(-)
-diff --git a/include/hw/register.h b/include/hw/register.h
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/register.h
+--- a/target/arm/mve_helper.c
-+++ b/include/hw/register.h
++++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct RegisterInfoArray RegisterInfoArray;
+@@ -XXX,XX +XXX,XX @@
   * immediately before the actual write. The returned value is what is written,
   * giving the handler a chance to modify the written value.
   * @post_write: Post write callback. Passed the written value. Most write side
 - * effects should be implemented here.
 + * effects should be implemented here. This is called during device reset.
   *
   * @post_read: Post read callback. Passes the value that is about to be returned
   * for a read. The return value from this function is what is ultimately read,
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
                         bool debug);
  /**
 - * reset a register
 - * @reg: register to reset
 + * Resets a register. This will also call the post_write hook if it exists.
 + * @reg: The register to reset.
   */
- void register_reset(RegisterInfo *reg);
+ #include "qemu/osdep.h"
-diff --git a/hw/core/register.c b/hw/core/register.c
+-#include "qemu/int128.h"
-index XXXXXXX..XXXXXXX 100644
+ #include "cpu.h"
---- a/hw/core/register.c
+ #include "internals.h"
-+++ b/hw/core/register.c
+ #include "vec_internal.h"
-@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
+@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
+ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
- void register_reset(RegisterInfo *reg)
- {
+ /*
-+    const RegisterAccessInfo *ac;
+- * Rounding multiply add long dual accumulate high: we must keep
-+
+- * a 72-bit internal accumulator value and return the top 64 bits.
-     g_assert(reg);
++ * Rounding multiply add long dual accumulate high. In the pseudocode
++ * this is implemented with a 72-bit internal accumulator value of which
-     if (!reg->data || !reg->access) {
++ * the top 64 bits are returned. We optimize this to avoid having to
-         return;
++ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
 + * is squashed back into 64-bits after each beat.
   */
 -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
 +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
      uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                      void *vm, uint64_t a)               \
      {                                                                   \
          uint16_t mask = mve_element_mask(env);                          \
          unsigned e;                                                     \
          TYPE *n = vn, *m = vm;                                          \
 -        Int128 acc = int128_lshift(TO128(a), 8);                        \
 -        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
              if (mask & 1) {                                             \
 +                LTYPE mul;                                              \
                  if (e & 1) {                                            \
 -                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
 -                                            m[H##ESIZE(e)]));           \
 +                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
 +                    if (SUB) {                                          \
 +                        mul = -mul;                                     \
 +                    }                                                   \
                  } else {                                                \
 -                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
 -                                             m[H##ESIZE(e)]));          \
 +                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                  }                                                       \
 -                acc = int128_add(acc, int128_make64(1 << 7));           \
 +                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
 +                a += mul;                                               \
              }                                                           \
          }                                                               \
          mve_advance_vpt(env);                                           \
 -        return int128_getlo(int128_rshift(acc, 8));                     \
 +        return a;                                                       \
      }
-+    ac = reg->access;
+-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-+
+-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
-     register_write_val(reg, reg->access->reset);
++DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
-+
++DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
-+    if (ac->post_write) {
-+        ac->post_write(reg, reg->access->reset);
+-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
-+    }
++DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
- }
+-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
- void register_init(RegisterInfo *reg)
+-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
 +DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
 +DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
  /* Vector add across vector */
  #define DO_VADDV(OP, ESIZE, TYPE)                               \
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
+Deleted patch
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
-Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
-for matching what is expected by Micron (Numonyx) flashes (the default target
-flash type of the QSPI).
-Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Tested-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Message-id: 20180223232233.31482-3-frasse.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/ssi/xilinx_spips.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
-+++ b/hw/ssi/xilinx_spips.c
-@@ -XXX,XX +XXX,XX @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
-         return 2;
-     case QIOR:
-     case QIOR_4:
--        return 5;
-+        return 4;
-     default:
-         return -1;
-     }
---
-.16.2

-[Qemu-devel] [PULL 04/42] i2c: Fix some brace style issues
+Deleted patch
-From: Corey Minyard <cminyard@mvista.com>
-Signed-off-by: Corey Minyard <cminyard@mvista.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-2-linus.walleij@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/i2c/i2c.h | 6 ++----
- hw/i2c/core.c        | 3 +--
-files changed, 3 insertions(+), 6 deletions(-)
-diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/i2c/i2c.h
-+++ b/include/hw/i2c/i2c.h
-@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlave I2CSlave;
- #define I2C_SLAVE_GET_CLASS(obj) \
-      OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
--typedef struct I2CSlaveClass
--{
-+typedef struct I2CSlaveClass {
-     DeviceClass parent_class;
-     /* Callbacks provided by the device.  */
-@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlaveClass
-     int (*event)(I2CSlave *s, enum i2c_event event);
- } I2CSlaveClass;
--struct I2CSlave
--{
-+struct I2CSlave {
-     DeviceState qdev;
-     /* Remaining fields for internal use by the I2C code.  */
-diff --git a/hw/i2c/core.c b/hw/i2c/core.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/core.c
-+++ b/hw/i2c/core.c
-@@ -XXX,XX +XXX,XX @@ struct I2CNode {
- #define I2C_BROADCAST 0x00
--struct I2CBus
--{
-+struct I2CBus {
-     BusState qbus;
-     QLIST_HEAD(, I2CNode) current_devs;
-     uint8_t saved_address;
---
-.16.2

-[Qemu-devel] [PULL 05/42] i2c: Move the bus class to i2c.h
+Deleted patch
-From: Corey Minyard <cminyard@mvista.com>
-Some devices need access to it.
-Signed-off-by: Corey Minyard <cminyard@mvista.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-3-linus.walleij@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/i2c/i2c.h | 17 +++++++++++++++++
- hw/i2c/core.c        | 17 -----------------
-files changed, 17 insertions(+), 17 deletions(-)
-diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/i2c/i2c.h
-+++ b/include/hw/i2c/i2c.h
-@@ -XXX,XX +XXX,XX @@ struct I2CSlave {
-     uint8_t address;
- };
-+#define TYPE_I2C_BUS "i2c-bus"
-+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
-+
-+typedef struct I2CNode I2CNode;
-+
-+struct I2CNode {
-+    I2CSlave *elt;
-+    QLIST_ENTRY(I2CNode) next;
-+};
-+
-+struct I2CBus {
-+    BusState qbus;
-+    QLIST_HEAD(, I2CNode) current_devs;
-+    uint8_t saved_address;
-+    bool broadcast;
-+};
-+
- I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
- void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
- int i2c_bus_busy(I2CBus *bus);
-diff --git a/hw/i2c/core.c b/hw/i2c/core.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/core.c
-+++ b/hw/i2c/core.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "hw/i2c/i2c.h"
--typedef struct I2CNode I2CNode;
--
--struct I2CNode {
--    I2CSlave *elt;
--    QLIST_ENTRY(I2CNode) next;
--};
--
- #define I2C_BROADCAST 0x00
--struct I2CBus {
--    BusState qbus;
--    QLIST_HEAD(, I2CNode) current_devs;
--    uint8_t saved_address;
--    bool broadcast;
--};
--
- static Property i2c_props[] = {
-     DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
-     DEFINE_PROP_END_OF_LIST(),
- };
--#define TYPE_I2C_BUS "i2c-bus"
--#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
--
- static const TypeInfo i2c_bus_info = {
-     .name = TYPE_I2C_BUS,
-     .parent = TYPE_BUS,
---
-.16.2

-[Qemu-devel] [PULL 06/42] hw/i2c-ddc: Do not fail writes
+Deleted patch
-From: Linus Walleij <linus.walleij@linaro.org>
-The tx function of the DDC I2C slave emulation was returning 1
-on all writes resulting in NACK in the I2C bus. Changing it to
-makes the DDC I2C work fine with bit-banged I2C such as the
-versatile I2C.
-I guess it was not affecting whatever I2C controller this was
-used with until now, but with the Versatile I2C it surely
-does not work.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-4-linus.walleij@linaro.org
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/i2c/i2c-ddc.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/i2c-ddc.c
-+++ b/hw/i2c/i2c-ddc.c
-@@ -XXX,XX +XXX,XX @@ static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
-         s->reg = data;
-         s->firstbyte = false;
-         DPRINTF("[EDID] Written new pointer: %u\n", data);
--        return 1;
-+        return 0;
-     }
-     /* Ignore all writes */
-     s->reg++;
--    return 1;
-+    return 0;
- }
- static void i2c_ddc_init(Object *obj)
---
-.16.2

-[Qemu-devel] [PULL 08/42] arm/vexpress: Add proper display connector emulation
+Deleted patch
-From: Linus Walleij <linus.walleij@linaro.org>
-This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
-Versatile Express machine, and selects the two I2C devices necessary
-in the arm-softmmu.mak configuration so everything will build
-smoothly.
-I am implementing proper handling of the graphics in the Linux
-kernel and adding proper emulation of SiI9022 and EDID makes the
-driver probe as nicely as before, retrieving the resolutions
-supported by the "QEMU monitor" and overall just working nice.
-Cc: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-6-linus.walleij@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/vexpress.c               | 6 +++++-
- default-configs/arm-softmmu.mak | 2 ++
-files changed, 7 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/vexpress.c
-+++ b/hw/arm/vexpress.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/arm/arm.h"
- #include "hw/arm/primecell.h"
- #include "hw/devices.h"
-+#include "hw/i2c/i2c.h"
- #include "net/net.h"
- #include "sysemu/sysemu.h"
- #include "hw/boards.h"
-@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
-     uint32_t sys_id;
-     DriveInfo *dinfo;
-     pflash_t *pflash0;
-+    I2CBus *i2c;
-     ram_addr_t vram_size, sram_size;
-     MemoryRegion *sysmem = get_system_memory();
-     MemoryRegion *vram = g_new(MemoryRegion, 1);
-@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
-     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
-     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
--    /* VE_SERIALDVI: not modelled */
-+    dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
-+    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
-+    i2c_create_slave(i2c, "sii9022", 0x39);
-     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
-diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
-index XXXXXXX..XXXXXXX 100644
---- a/default-configs/arm-softmmu.mak
-+++ b/default-configs/arm-softmmu.mak
-@@ -XXX,XX +XXX,XX @@ CONFIG_STELLARIS_INPUT=y
- CONFIG_STELLARIS_ENET=y
- CONFIG_SSD0303=y
- CONFIG_SSD0323=y
-+CONFIG_DDC=y
-+CONFIG_SII9022=y
- CONFIG_ADS7846=y
- CONFIG_MAX111X=y
- CONFIG_SSI=y
---
-.16.2

-[Qemu-devel] [PULL 09/42] include/exec/helper-head.h: support f16 in helper calls
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This allows us to explicitly pass float16 to helpers rather than
-assuming uint32_t and dealing with the result. Of course they will be
-passed in i32 sized registers by default.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-2-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/exec/helper-head.h | 3 +++
-file changed, 3 insertions(+)
-diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/helper-head.h
-+++ b/include/exec/helper-head.h
-@@ -XXX,XX +XXX,XX @@
- #define dh_alias_int i32
- #define dh_alias_i64 i64
- #define dh_alias_s64 i64
-+#define dh_alias_f16 i32
- #define dh_alias_f32 i32
- #define dh_alias_f64 i64
- #define dh_alias_ptr ptr
-@@ -XXX,XX +XXX,XX @@
- #define dh_ctype_int int
- #define dh_ctype_i64 uint64_t
- #define dh_ctype_s64 int64_t
-+#define dh_ctype_f16 float16
- #define dh_ctype_f32 float32
- #define dh_ctype_f64 float64
- #define dh_ctype_ptr void *
-@@ -XXX,XX +XXX,XX @@
- #define dh_is_signed_s32 1
- #define dh_is_signed_i64 0
- #define dh_is_signed_s64 1
-+#define dh_is_signed_f16 0
- #define dh_is_signed_f32 0
- #define dh_is_signed_f64 0
- #define dh_is_signed_tl  0
---
-.16.2

-[Qemu-devel] [PULL 10/42] target/arm/cpu64: introduce ARM_V8_FP16 feature bit
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-3-alex.bennee@linaro.org
-[PMM: postpone actually enabling feature until end of the
- patch series]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h | 1 +
-file changed, 1 insertion(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ enum arm_features {
-     ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
-     ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
-     ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
-+    ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
- };
- static inline int arm_feature(CPUARMState *env, int feature)
---
-.16.2

-[Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-4-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h | 1 +
-file changed, 1 insertion(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct {
-  *  Qn = regs[n].d[1]:regs[n].d[0]
-  *  Dn = regs[n].d[0]
-  *  Sn = regs[n].d[0] bits 31..0
-+ *  Hn = regs[n].d[0] bits 15..0
-  *
-  * This corresponds to the architecturally defined mapping between
-  * the two execution states, and means we do not need to explicitly
---
-.16.2

-[Qemu-devel] [PULL 12/42] target/arm/cpu.h: add additional float_status flags
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Half-precision flush to zero behaviour is controlled by a separate
-FZ16 bit in the FPCR. To handle this we pass a pointer to
-fp_status_fp16 when working on half-precision operations. The value of
-the presented FPCR is calculated from an amalgam of the two when read.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h           | 32 ++++++++++++++++++++++------
- target/arm/helper.c        | 26 ++++++++++++++++++-----
- target/arm/translate-a64.c | 53 +++++++++++++++++++++++++---------------------
-files changed, 75 insertions(+), 36 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
-         /* scratch space when Tn are not sufficient.  */
-         uint32_t scratch[8];
--        /* fp_status is the "normal" fp status. standard_fp_status retains
--         * values corresponding to the ARM "Standard FPSCR Value", ie
--         * default-NaN, flush-to-zero, round-to-nearest and is used by
--         * any operations (generally Neon) which the architecture defines
--         * as controlled by the standard FPSCR value rather than the FPSCR.
-+        /* There are a number of distinct float control structures:
-+         *
-+         *  fp_status: is the "normal" fp status.
-+         *  fp_status_fp16: used for half-precision calculations
-+         *  standard_fp_status : the ARM "Standard FPSCR Value"
-+         *
-+         * Half-precision operations are governed by a separate
-+         * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
-+         * status structure to control this.
-+         *
-+         * The "Standard FPSCR", ie default-NaN, flush-to-zero,
-+         * round-to-nearest and is used by any operations (generally
-+         * Neon) which the architecture defines as controlled by the
-+         * standard FPSCR value rather than the FPSCR.
-          *
-          * To avoid having to transfer exception bits around, we simply
-          * say that the FPSCR cumulative exception flags are the logical
--         * OR of the flags in the two fp statuses. This relies on the
-+         * OR of the flags in the three fp statuses. This relies on the
-          * only thing which needs to read the exception flags being
-          * an explicit FPSCR read.
-          */
-         float_status fp_status;
-+        float_status fp_status_f16;
-         float_status standard_fp_status;
-         /* ZCR_EL[1-3] */
-@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
- uint32_t vfp_get_fpscr(CPUARMState *env);
- void vfp_set_fpscr(CPUARMState *env, uint32_t val);
--/* For A64 the FPSCR is split into two logically distinct registers,
-+/* FPCR, Floating Point Control Register
-+ * FPSR, Floating Poiht Status Register
-+ *
-+ * For A64 the FPSCR is split into two logically distinct registers,
-  * FPCR and FPSR. However since they still use non-overlapping bits
-  * we store the underlying state in fpscr and just mask on read/write.
-  */
- #define FPSR_MASK 0xf800009f
- #define FPCR_MASK 0x07f79f00
-+
-+#define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
-+#define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
-+#define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
-+
- static inline uint32_t vfp_get_fpsr(CPUARMState *env)
- {
-     return vfp_get_fpscr(env) & FPSR_MASK;
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
-             | (env->vfp.vec_stride << 20);
-     i = get_float_exception_flags(&env->vfp.fp_status);
-     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
-+    i |= get_float_exception_flags(&env->vfp.fp_status_f16);
-     fpscr |= vfp_exceptbits_from_host(i);
-     return fpscr;
- }
-@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
-             break;
-         }
-         set_float_rounding_mode(i, &env->vfp.fp_status);
-+        set_float_rounding_mode(i, &env->vfp.fp_status_f16);
-     }
--    if (changed & (1 << 24)) {
--        set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
--        set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
-+    if (changed & FPCR_FZ16) {
-+        bool ftz_enabled = val & FPCR_FZ16;
-+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
-+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
-+    }
-+    if (changed & FPCR_FZ) {
-+        bool ftz_enabled = val & FPCR_FZ;
-+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
-+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
-+    }
-+    if (changed & FPCR_DN) {
-+        bool dnan_enabled = val & FPCR_DN;
-+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
-+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
-     }
--    if (changed & (1 << 25))
--        set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
-+    /* The exception flags are ORed together when we read fpscr so we
-+     * only need to preserve the current state in one of our
-+     * float_status values.
-+     */
-     i = vfp_exceptbits_to_host(val);
-     set_float_exception_flags(i, &env->vfp.fp_status);
-+    set_float_exception_flags(0, &env->vfp.fp_status_f16);
-     set_float_exception_flags(0, &env->vfp.standard_fp_status);
- }
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
-     tcg_temp_free_i64(tmp);
- }
--static TCGv_ptr get_fpstatus_ptr(void)
-+static TCGv_ptr get_fpstatus_ptr(bool is_f16)
- {
-     TCGv_ptr statusptr = tcg_temp_new_ptr();
-     int offset;
--    /* In A64 all instructions (both FP and Neon) use the FPCR;
--     * there is no equivalent of the A32 Neon "standard FPSCR value"
--     * and all operations use vfp.fp_status.
-+    /* In A64 all instructions (both FP and Neon) use the FPCR; there
-+     * is no equivalent of the A32 Neon "standard FPSCR value".
-+     * However half-precision operations operate under a different
-+     * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
-      */
--    offset = offsetof(CPUARMState, vfp.fp_status);
-+    if (is_f16) {
-+        offset = offsetof(CPUARMState, vfp.fp_status_f16);
-+    } else {
-+        offset = offsetof(CPUARMState, vfp.fp_status);
-+    }
-     tcg_gen_addi_ptr(statusptr, cpu_env, offset);
-     return statusptr;
- }
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
-                               bool cmp_with_zero, bool signal_all_nans)
- {
-     TCGv_i64 tcg_flags = tcg_temp_new_i64();
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     if (is_double) {
-         TCGv_i64 tcg_vn, tcg_vm;
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
-     TCGv_i32 tcg_op;
-     TCGv_i32 tcg_res;
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op = read_fp_sreg(s, rn);
-     tcg_res = tcg_temp_new_i32();
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
-         return;
-     }
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op = read_fp_dreg(s, rn);
-     tcg_res = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
-     TCGv_ptr fpst;
-     tcg_res = tcg_temp_new_i32();
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_sreg(s, rn);
-     tcg_op2 = read_fp_sreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
-     TCGv_ptr fpst;
-     tcg_res = tcg_temp_new_i64();
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_dreg(s, rn);
-     tcg_op2 = read_fp_dreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
- {
-     TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
-     TCGv_i32 tcg_res = tcg_temp_new_i32();
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_sreg(s, rn);
-     tcg_op2 = read_fp_sreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
- {
-     TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
-     TCGv_i64 tcg_res = tcg_temp_new_i64();
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_dreg(s, rn);
-     tcg_op2 = read_fp_dreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
-     TCGv_ptr tcg_fpstatus;
-     TCGv_i32 tcg_shift;
--    tcg_fpstatus = get_fpstatus_ptr();
-+    tcg_fpstatus = get_fpstatus_ptr(false);
-     tcg_shift = tcg_const_i32(64 - scale);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
-         TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
-         TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
-         TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
--        TCGv_ptr fpst = get_fpstatus_ptr();
-+        TCGv_ptr fpst = get_fpstatus_ptr(false);
-         assert(esize == 32);
-         assert(elements == 4);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
-         }
-         size = extract32(size, 0, 1) ? 3 : 2;
--        fpst = get_fpstatus_ptr();
-+        fpst = get_fpstatus_ptr(false);
-         break;
-     default:
-         unallocated_encoding(s);
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
-                                    int fracbits, int size)
- {
-     bool is_double = size == 3 ? true : false;
--    TCGv_ptr tcg_fpst = get_fpstatus_ptr();
-+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
-     TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
-     TCGv_i64 tcg_int = tcg_temp_new_i64();
-     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
--    tcg_fpstatus = get_fpstatus_ptr();
-+    tcg_fpstatus = get_fpstatus_ptr(false);
-     tcg_shift = tcg_const_i32(fracbits);
-     if (is_double) {
-@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
-                                int fpopcode, int rd, int rn, int rm)
- {
-     int pass;
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     for (pass = 0; pass < elements; pass++) {
-         if (size) {
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
-         return;
-     }
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     if (is_double) {
-         TCGv_i64 tcg_op = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
-                                     int size, int rn, int rd)
- {
-     bool is_double = (size == 3);
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     if (is_double) {
-         TCGv_i64 tcg_op = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
-     if (is_fcvt) {
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-         gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
--        tcg_fpstatus = get_fpstatus_ptr();
-+        tcg_fpstatus = get_fpstatus_ptr(false);
-     } else {
-         tcg_rmode = NULL;
-         tcg_fpstatus = NULL;
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
-     /* Floating point operations need fpst */
-     if (opcode >= 0x58) {
--        fpst = get_fpstatus_ptr();
-+        fpst = get_fpstatus_ptr(false);
-     } else {
-         fpst = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-     }
-     if (need_fpstatus) {
--        tcg_fpstatus = get_fpstatus_ptr();
-+        tcg_fpstatus = get_fpstatus_ptr(false);
-     } else {
-         tcg_fpstatus = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     }
-     if (is_fp) {
--        fpst = get_fpstatus_ptr();
-+        fpst = get_fpstatus_ptr(false);
-     } else {
-         fpst = NULL;
-     }
---
-.16.2

-[Qemu-devel] [PULL 20/42] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
+[PULL 09/24] target/arm: Make asimd_imm_const() public
-From: Alex Bennée <alex.bennee@linaro.org>
+The function asimd_imm_const() in translate-neon.c is an
 implementation of the pseudocode AdvSIMDExpandImm(), which we will
 also want for MVE.  Move the implementation to translate.c, with a
 prototype in translate.h.
-As some of the constants here will also be needed
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-elsewhere (specifically for the upcoming SVE support) we move them out
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-to softfloat.h.
+Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
 ---
  target/arm/translate.h      | 16 ++++++++++
  target/arm/translate-neon.c | 63 -------------------------------------
  target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 files changed, 73 insertions(+), 63 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/fpu/softfloat.h    | 18 +++++++++++++-----
  target/arm/helper-a64.h    |  2 ++
  target/arm/helper-a64.c    | 34 ++++++++++++++++++++++++++++++++++
  target/arm/translate-a64.c |  6 ++++++
 files changed, 55 insertions(+), 5 deletions(-)
 diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/fpu/softfloat.h
+--- a/target/arm/translate.h
-+++ b/include/fpu/softfloat.h
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline float16 float16_set_sign(float16 a, int sign)
+@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
      return opc | s->be_data;
  }
- #define float16_zero make_float16(0)
++/**
--#define float16_one make_float16(0x3c00)
++ * asimd_imm_const: Expand an encoded SIMD constant value
- #define float16_half make_float16(0x3800)
++ *
-+#define float16_one make_float16(0x3c00)
++ * Expand a SIMD constant value. This is essentially the pseudocode
-+#define float16_one_point_five make_float16(0x3e00)
++ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
-+#define float16_two make_float16(0x4000)
++ * VMVN and VBIC (when cmode < 14 && op == 1).
-+#define float16_three make_float16(0x4200)
++ *
- #define float16_infinity make_float16(0x7c00)
++ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
++ * callers must catch this.
- /*----------------------------------------------------------------------------
++ *
-@@ -XXX,XX +XXX,XX @@ static inline float32 float32_set_sign(float32 a, int sign)
++ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
 + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 + * we produce an immediate constant value of 0 in these cases.
 + */
 +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 +
  #endif /* TARGET_ARM_TRANSLATE_H */
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
  DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
  DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
 -{
 -    /*
 -     * Expand the encoded constant.
 -     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
 -     * We choose to not special-case this and will behave as if a
 -     * valid constant encoding of 0 had been given.
 -     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
 -     */
 -    switch (cmode) {
 -    case 0: case 1:
 -        /* no-op */
 -        break;
 -    case 2: case 3:
 -        imm <<= 8;
 -        break;
 -    case 4: case 5:
 -        imm <<= 16;
 -        break;
 -    case 6: case 7:
 -        imm <<= 24;
 -        break;
 -    case 8: case 9:
 -        imm |= imm << 16;
 -        break;
 -    case 10: case 11:
 -        imm = (imm << 8) | (imm << 24);
 -        break;
 -    case 12:
 -        imm = (imm << 8) | 0xff;
 -        break;
 -    case 13:
 -        imm = (imm << 16) | 0xffff;
 -        break;
 -    case 14:
 -        if (op) {
 -            /*
 -             * This is the only case where the top and bottom 32 bits
 -             * of the encoded constant differ.
 -             */
 -            uint64_t imm64 = 0;
 -            int n;
 -
 -            for (n = 0; n < 8; n++) {
 -                if (imm & (1 << n)) {
 -                    imm64 |= (0xffULL << (n * 8));
 -                }
 -            }
 -            return imm64;
 -        }
 -        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 -        break;
 -    case 15:
 -        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 -            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 -        break;
 -    }
 -    if (op) {
 -        imm = ~imm;
 -    }
 -    return dup_const(MO_32, imm);
 -}
 -
  static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                          GVecGen2iFn *fn)
  {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
      a64_translate_init();
  }
- #define float32_zero make_float32(0)
++uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
--#define float32_one make_float32(0x3f800000)
++{
- #define float32_half make_float32(0x3f000000)
++    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
-+#define float32_one make_float32(0x3f800000)
++    switch (cmode) {
-+#define float32_one_point_five make_float32(0x3fc00000)
++    case 0: case 1:
-+#define float32_two make_float32(0x40000000)
++        /* no-op */
-+#define float32_three make_float32(0x40400000)
++        break;
- #define float32_infinity make_float32(0x7f800000)
++    case 2: case 3:
++        imm <<= 8;
--
++        break;
- /*----------------------------------------------------------------------------
++    case 4: case 5:
- | The pattern for a default generated single-precision NaN.
++        imm <<= 16;
- *----------------------------------------------------------------------------*/
++        break;
-@@ -XXX,XX +XXX,XX @@ static inline float64 float64_set_sign(float64 a, int sign)
++    case 6: case 7:
- }
++        imm <<= 24;
++        break;
- #define float64_zero make_float64(0)
++    case 8: case 9:
--#define float64_one make_float64(0x3ff0000000000000LL)
++        imm |= imm << 16;
--#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
++        break;
- #define float64_half make_float64(0x3fe0000000000000LL)
++    case 10: case 11:
-+#define float64_one make_float64(0x3ff0000000000000LL)
++        imm = (imm << 8) | (imm << 24);
-+#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
++        break;
-+#define float64_two make_float64(0x4000000000000000ULL)
++    case 12:
-+#define float64_three make_float64(0x4008000000000000ULL)
++        imm = (imm << 8) | 0xff;
-+#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
++        break;
- #define float64_infinity make_float64(0x7ff0000000000000LL)
++    case 13:
++        imm = (imm << 16) | 0xffff;
- /*----------------------------------------------------------------------------
++        break;
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
++    case 14:
-index XXXXXXX..XXXXXXX 100644
++        if (op) {
---- a/target/arm/helper-a64.h
++            /*
-+++ b/target/arm/helper-a64.h
++             * This is the only case where the top and bottom 32 bits
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
++             * of the encoded constant differ.
- DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
++             */
- DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
++            uint64_t imm64 = 0;
- DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
++            int n;
 +DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
  DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
  DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
 +DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
  DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
  DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
  DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-a64.c
 +++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
   * versions, these do a fully fused multiply-add or
   * multiply-add-and-halve.
   */
 +#define float16_two make_float16(0x4000)
 +#define float16_three make_float16(0x4200)
 +#define float16_one_point_five make_float16(0x3e00)
 +
- #define float32_two make_float32(0x40000000)
++            for (n = 0; n < 8; n++) {
- #define float32_three make_float32(0x40400000)
++                if (imm & (1 << n)) {
- #define float32_one_point_five make_float32(0x3fc00000)
++                    imm64 |= (0xffULL << (n * 8));
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
++                }
- #define float64_three make_float64(0x4008000000000000ULL)
++            }
- #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
++            return imm64;
++        }
-+float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
++        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-+{
++        break;
-+    float_status *fpst = fpstp;
++    case 15:
-+
++        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-+    a = float16_squash_input_denormal(a, fpst);
++            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-+    b = float16_squash_input_denormal(b, fpst);
++        break;
 +
 +    a = float16_chs(a);
 +    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
 +        (float16_is_infinity(b) && float16_is_zero(a))) {
 +        return float16_two;
 +    }
-+    return float16_muladd(a, b, float16_two, 0, fpst);
++    if (op) {
 +        imm = ~imm;
 +    }
 +    return dup_const(MO_32, imm);
 +}
 +
- float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
+ /* Generate a label used for skipping this instruction */
  void arm_gen_condlabel(DisasContext *s)
  {
-     float_status *fpst = fpstp;
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
-     return float64_muladd(a, b, float64_two, 0, fpst);
- }
-+float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+
-+    a = float16_squash_input_denormal(a, fpst);
-+    b = float16_squash_input_denormal(b, fpst);
-+
-+    a = float16_chs(a);
-+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
-+        (float16_is_infinity(b) && float16_is_zero(a))) {
-+        return float16_one_point_five;
-+    }
-+    return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
-+}
-+
- float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
- {
-     float_status *fpst = fpstp;
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0x6: /* FMAX */
-             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x7: /* FRECPS */
-+            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x8: /* FMINNM */
-             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0xe: /* FMIN */
-             gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0xf: /* FRSQRTS */
-+            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x13: /* FMUL */
-             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
+[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
-From: Alex Bennée <alex.bennee@linaro.org>
+The A64 AdvSIMD modified-immediate grouping uses almost the same
 constant encoding that A32 Neon does; reuse asimd_imm_const() (to
 which we add the AArch64-specific case for cmode 15 op 1) instead of
 reimplementing it all.
-Neither of these operations alter the floating point status registers
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-so we can do a pure bitwise operation, either squashing any sign
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-bit (ABS) or inverting it (NEG).
+Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
 ---
  target/arm/translate.h     |  3 +-
  target/arm/translate-a64.c | 86 ++++----------------------------------
  target/arm/translate.c     | 17 +++++++-
 files changed, 24 insertions(+), 82 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+index XXXXXXX..XXXXXXX 100644
-Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
+--- a/target/arm/translate.h
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
++++ b/target/arm/translate.h
----
+@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
- target/arm/translate-a64.c | 16 +++++++++++++++-
+  * VMVN and VBIC (when cmode < 14 && op == 1).
-file changed, 15 insertions(+), 1 deletion(-)
+  *
+  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
 - * callers must catch this.
 + * callers must catch this; we return the 64-bit constant value defined
 + * for AArch64.
   *
   * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
   * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-     TCGv_i32 tcg_rmode = NULL;
+ {
-     TCGv_ptr tcg_fpstatus = NULL;
+     int rd = extract32(insn, 0, 5);
-     bool need_rmode = false;
+     int cmode = extract32(insn, 12, 4);
-+    bool need_fpst = true;
+-    int cmode_3_1 = extract32(cmode, 1, 3);
-     int rmode;
+-    int cmode_0 = extract32(cmode, 0, 1);
+     int o2 = extract32(insn, 11, 1);
-     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+     bool is_neg = extract32(insn, 29, 1);
-         need_rmode = true;
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
          rmode = FPROUNDING_ZERO;
          break;
 +    case 0x2f: /* FABS */
 +    case 0x6f: /* FNEG */
 +        need_fpst = false;
 +        break;
      default:
          fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
          return;
      }
--    if (need_rmode) {
+-    /* See AdvSIMDExpandImm() in ARM ARM */
-+    if (need_rmode || need_fpst) {
+-    switch (cmode_3_1) {
-         tcg_fpstatus = get_fpstatus_ptr(true);
+-    case 0: /* Replicate(Zeros(24):imm8, 2) */
 -    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
 -    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
 -    case 3: /* Replicate(imm8:Zeros(24), 2) */
 -    {
 -        int shift = cmode_3_1 * 8;
 -        imm = bitfield_replicate(abcdefgh << shift, 32);
 -        break;
 -    }
 -    case 4: /* Replicate(Zeros(8):imm8, 4) */
 -    case 5: /* Replicate(imm8:Zeros(8), 4) */
 -    {
 -        int shift = (cmode_3_1 & 0x1) * 8;
 -        imm = bitfield_replicate(abcdefgh << shift, 16);
 -        break;
 -    }
 -    case 6:
 -        if (cmode_0) {
 -            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
 -            imm = (abcdefgh << 16) | 0xffff;
 -        } else {
 -            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
 -            imm = (abcdefgh << 8) | 0xff;
 -        }
 -        imm = bitfield_replicate(imm, 32);
 -        break;
 -    case 7:
 -        if (!cmode_0 && !is_neg) {
 -            imm = bitfield_replicate(abcdefgh, 8);
 -        } else if (!cmode_0 && is_neg) {
 -            int i;
 -            imm = 0;
 -            for (i = 0; i < 8; i++) {
 -                if ((abcdefgh) & (1 << i)) {
 -                    imm |= 0xffULL << (i * 8);
 -                }
 -            }
 -        } else if (cmode_0) {
 -            if (is_neg) {
 -                imm = (abcdefgh & 0x3f) << 48;
 -                if (abcdefgh & 0x80) {
 -                    imm |= 0x8000000000000000ULL;
 -                }
 -                if (abcdefgh & 0x40) {
 -                    imm |= 0x3fc0000000000000ULL;
 -                } else {
 -                    imm |= 0x4000000000000000ULL;
 -                }
 -            } else {
 -                if (o2) {
 -                    /* FMOV (vector, immediate) - half-precision */
 -                    imm = vfp_expand_imm(MO_16, abcdefgh);
 -                    /* now duplicate across the lanes */
 -                    imm = bitfield_replicate(imm, 16);
 -                } else {
 -                    imm = (abcdefgh & 0x3f) << 19;
 -                    if (abcdefgh & 0x80) {
 -                        imm |= 0x80000000;
 -                    }
 -                    if (abcdefgh & 0x40) {
 -                        imm |= 0x3e000000;
 -                    } else {
 -                        imm |= 0x40000000;
 -                    }
 -                    imm |= (imm << 32);
 -                }
 -            }
 -        }
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -
 -    if (cmode_3_1 != 7 && is_neg) {
 -        imm = ~imm;
 +    if (cmode == 15 && o2 && !is_neg) {
 +        /* FMOV (vector, immediate) - half-precision */
 +        imm = vfp_expand_imm(MO_16, abcdefgh);
 +        /* now duplicate across the lanes */
 +        imm = bitfield_replicate(imm, 16);
 +    } else {
 +        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
      }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
-         case 0x7b: /* FCVTZU */
+diff --git a/target/arm/translate.c b/target/arm/translate.c
-             gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
+index XXXXXXX..XXXXXXX 100644
-             break;
+--- a/target/arm/translate.c
-+        case 0x6f: /* FNEG */
++++ b/target/arm/translate.c
-+            tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-+            break;
+     case 14:
-         default:
+         if (op) {
-             g_assert_not_reached();
+             /*
-         }
+-             * This is the only case where the top and bottom 32 bits
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+-             * of the encoded constant differ.
-             case 0x59: /* FRINTX */
++             * This and cmode == 15 op == 1 are the only cases where
-                 gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
++             * the top and bottom 32 bits of the encoded constant differ.
-                 break;
+              */
-+            case 0x2f: /* FABS */
+             uint64_t imm64 = 0;
-+                tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
+             int n;
-+                break;
+@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-+            case 0x6f: /* FNEG */
+         imm |= (imm << 8) | (imm << 16) | (imm << 24);
-+                tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+         break;
-+                break;
+     case 15:
-             default:
++        if (op) {
-                 g_assert_not_reached();
++            /* Reserved encoding for AArch32; valid for AArch64 */
-             }
++            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
 +            if (imm & 0x80) {
 +                imm64 |= 0x8000000000000000ULL;
 +            }
 +            if (imm & 0x40) {
 +                imm64 |= 0x3fc0000000000000ULL;
 +            } else {
 +                imm64 |= 0x4000000000000000ULL;
 +            }
 +            return imm64;
 +        }
          imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
              | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
          break;
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16
+[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
-From: Alex Bennée <alex.bennee@linaro.org>
+Use dup_const() instead of bitfield_replicate() in
 disas_simd_mod_imm().
-This covers the encoding group:
+(We can't replace the other use of bitfield_replicate() in this file,
 in logic_imm_decode_wmask(), because that location needs to handle 2
 and 4 bit elements, which dup_const() cannot.)
-  Advanced SIMD scalar three same FP16
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 As all the helpers are already there it is simply a case of calling the
 existing helpers in the scalar context.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-31-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
+ target/arm/translate-a64.c | 2 +-
-file changed, 99 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-     tcg_temp_free_i64(tcg_rd);
+         /* FMOV (vector, immediate) - half-precision */
- }
+         imm = vfp_expand_imm(MO_16, abcdefgh);
+         /* now duplicate across the lanes */
-+/* AdvSIMD scalar three same FP16
+-        imm = bitfield_replicate(imm, 16);
-+ *  31 30  29 28       24 23  22 21 20  16 15 14 13    11 10  9  5 4  0
++        imm = dup_const(MO_16, imm);
-+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
+     } else {
-+ * | 0 1 | U | 1 1 1 1 0 | a | 1 0 |  Rm  | 0 0 | opcode | 1 | Rn | Rd |
+         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
-+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
+     }
 + * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
 + * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
 + */
 +static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
 +                                                  uint32_t insn)
 +{
 +    int rd = extract32(insn, 0, 5);
 +    int rn = extract32(insn, 5, 5);
 +    int opcode = extract32(insn, 11, 3);
 +    int rm = extract32(insn, 16, 5);
 +    bool u = extract32(insn, 29, 1);
 +    bool a = extract32(insn, 23, 1);
 +    int fpopcode = opcode | (a << 3) |  (u << 4);
 +    TCGv_ptr fpst;
 +    TCGv_i32 tcg_op1;
 +    TCGv_i32 tcg_op2;
 +    TCGv_i32 tcg_res;
 +
 +    switch (fpopcode) {
 +    case 0x03: /* FMULX */
 +    case 0x04: /* FCMEQ (reg) */
 +    case 0x07: /* FRECPS */
 +    case 0x0f: /* FRSQRTS */
 +    case 0x14: /* FCMGE (reg) */
 +    case 0x15: /* FACGE */
 +    case 0x1a: /* FABD */
 +    case 0x1c: /* FCMGT (reg) */
 +    case 0x1d: /* FACGT */
 +        break;
 +    default:
 +        unallocated_encoding(s);
 +        return;
 +    }
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +        unallocated_encoding(s);
 +    }
 +
 +    if (!fp_access_check(s)) {
 +        return;
 +    }
 +
 +    fpst = get_fpstatus_ptr(true);
 +
 +    tcg_op1 = tcg_temp_new_i32();
 +    tcg_op2 = tcg_temp_new_i32();
 +    tcg_res = tcg_temp_new_i32();
 +
 +    read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
 +    read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
 +
 +    switch (fpopcode) {
 +    case 0x03: /* FMULX */
 +        gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x04: /* FCMEQ (reg) */
 +        gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x07: /* FRECPS */
 +        gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x0f: /* FRSQRTS */
 +        gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x14: /* FCMGE (reg) */
 +        gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x15: /* FACGE */
 +        gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x1a: /* FABD */
 +        gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
 +        break;
 +    case 0x1c: /* FCMGT (reg) */
 +        gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x1d: /* FACGT */
 +        gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    write_fp_sreg(s, rd, tcg_res);
 +
 +
 +    tcg_temp_free_i32(tcg_res);
 +    tcg_temp_free_i32(tcg_op1);
 +    tcg_temp_free_i32(tcg_op2);
 +    tcg_temp_free_ptr(fpst);
 +}
 +
  static void handle_2misc_64(DisasContext *s, int opcode, bool u,
                              TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
                              TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
      { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
      { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
      { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
 +    { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
      { 0x00000000, 0x00000000, NULL }
  };
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 16/42] arm/translate-a64: initial decode for simd_three_reg_same_fp16
+[PULL 12/24] target/arm: Implement MVE logical immediate insns
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE logical-immediate insns (VMOV, VMVN,
 VORR and VBIC). These have essentially the same encoding
 as their Neon equivalents, and we implement the decode
 in the same way.
-This is the initial decode skeleton for the Advanced SIMD three same
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-instruction group.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  4 +++
  target/arm/mve.decode      | 17 +++++++++++++
  target/arm/mve_helper.c    | 24 ++++++++++++++++++
  target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 files changed, 95 insertions(+)
-The fprintf is purely to aid debugging as the additional instructions
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 are added. It will be removed once the group is complete.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-9-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
 file changed, 73 insertions(+)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
-     }
+ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- }
+ DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
  DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 +
 +DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 +DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
  %size_28 28:1 !function=plus_1
 +# 1imm format immediate
 +%imm_28_16_0 28:1 16:3 0:4
 +
  &vldr_vstr rn qd imm p a w size l u
  &1op qd qm size
  &2op qd qm qn size
  &2scalar qd qn rm size
 +&1imm qd imm cmode op
  @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
  # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
  @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
  @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
       size=%size_28
 +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
  # The _rev suffix indicates that Vn and Vm are reversed. This is
  # the case for shifts. In the Arm ARM these insns are documented
@@ -XXX,XX +XXX,XX @@ VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
  # Predicate operations
  %mask_22_13      22:1 13:3
  VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 +
 +# Logical immediate operations (1 reg and modified-immediate)
 +
 +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
 +# not in a way we can conveniently represent in decodetree without
 +# a lot of repetition:
 +# VORR: op=0, (cmode & 1) && cmode < 12
 +# VBIC: op=1, (cmode & 1) && cmode < 12
 +# VMOV: everything else
 +# So we have a single decode line and check the cmode/op in the
 +# trans function.
 +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
  DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
  DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
 +/*
-+ * Advanced SIMD three same (ARMv8.2 FP16 variants)
++ * 1 operand immediates: Vda is destination and possibly also one source.
-+ *
++ * All these insns work at 64-bit widths.
 + *  31  30  29  28       24 23  22 21 20  16 15 14 13    11 10  9    5 4    0
 + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
 + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 |  Rm  | 0 0 | opcode | 1 |  Rn  |  Rd  |
 + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
 + *
 + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
 + * (register), FACGE, FABD, FCMGT (register) and FACGT.
 + *
 + */
-+static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
++#define DO_1OP_IMM(OP, FN)                                              \
-+{
++    void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm)    \
-+    int opcode, fpopcode;
++    {                                                                   \
-+    int is_q, u, a, rm, rn, rd;
++        uint64_t *da = vda;                                             \
-+    int datasize, elements;
++        uint16_t mask = mve_element_mask(env);                          \
-+    int pass;
++        unsigned e;                                                     \
-+    TCGv_ptr fpst;
++        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
-+
++            mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask);            \
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
++        }                                                               \
-+        unallocated_encoding(s);
++        mve_advance_vpt(env);                                           \
 +        return;
 +    }
 +
-+    if (!fp_access_check(s)) {
++#define DO_MOVI(N, I) (I)
-+        return;
++#define DO_ANDI(N, I) ((N) & (I))
 +#define DO_ORRI(N, I) ((N) | (I))
 +
 +DO_1OP_IMM(vmovi, DO_MOVI)
 +DO_1OP_IMM(vandi, DO_ANDI)
 +DO_1OP_IMM(vorri, DO_ORRI)
 +
  #define DO_2OP(OP, ESIZE, TYPE, FN)                                     \
      void HELPER(glue(mve_, OP))(CPUARMState *env,                       \
                                  void *vd, void *vn, void *vm)           \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
  /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
  static inline long mve_qreg_offset(unsigned reg)
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      mve_update_eci(s);
      return true;
  }
 +
 +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
 +{
 +    TCGv_ptr qd;
 +    uint64_t imm;
 +
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd) ||
 +        !fn) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    /* For these floating point ops, the U, a and opcode bits
++    imm = asimd_imm_const(a->imm, a->cmode, a->op);
 +     * together indicate the operation.
 +     */
 +    opcode = extract32(insn, 11, 3);
 +    u = extract32(insn, 29, 1);
 +    a = extract32(insn, 23, 1);
 +    is_q = extract32(insn, 30, 1);
 +    rm = extract32(insn, 16, 5);
 +    rn = extract32(insn, 5, 5);
 +    rd = extract32(insn, 0, 5);
 +
-+    fpopcode = opcode | (a << 3) |  (u << 4);
++    qd = mve_qreg_ptr(a->qd);
-+    datasize = is_q ? 128 : 64;
++    fn(cpu_env, qd, tcg_constant_i64(imm));
-+    elements = datasize / 16;
++    tcg_temp_free_ptr(qd);
-+
++    mve_update_eci(s);
-+    fpst = get_fpstatus_ptr(true);
++    return true;
 +
 +    for (pass = 0; pass < elements; pass++) {
 +        TCGv_i32 tcg_op1 = tcg_temp_new_i32();
 +        TCGv_i32 tcg_op2 = tcg_temp_new_i32();
 +        TCGv_i32 tcg_res = tcg_temp_new_i32();
 +
 +        read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
 +        read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
 +
 +        switch (fpopcode) {
 +        default:
 +            fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
 +                    __func__, insn, fpopcode, s->pc);
 +            g_assert_not_reached();
 +        }
 +
 +        write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
 +        tcg_temp_free_i32(tcg_res);
 +        tcg_temp_free_i32(tcg_op1);
 +        tcg_temp_free_i32(tcg_op2);
 +    }
 +
 +    tcg_temp_free_ptr(fpst);
 +
 +    clear_vec_high(s, is_q, rd);
 +}
 +
- static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
++static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
-                                   int size, int rn, int rd)
++{
- {
++    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
-@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
++    MVEGenOneOpImmFn *fn;
-     { 0xce000000, 0xff808000, disas_crypto_four_reg },
++
-     { 0xce800000, 0xffe00000, disas_crypto_xar },
++    if ((a->cmode & 1) && a->cmode < 12) {
-     { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
++        if (a->op) {
-+    { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
++            /*
-     { 0x00000000, 0x00000000, NULL }
++             * For op=1, the immediate will be inverted by asimd_imm_const(),
- };
++             * so the VBIC becomes a logical AND operation.
++             */
 +            fn = gen_helper_mve_vandi;
 +        } else {
 +            fn = gen_helper_mve_vorri;
 +        }
 +    } else {
 +        /* There is one unallocated cmode/op combination in this space */
 +        if (a->cmode == 15 && a->op == 1) {
 +            return false;
 +        }
 +        /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
 +        fn = gen_helper_mve_vmovi;
 +    }
 +    return do_1imm(s, a, fn);
 +}
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
+[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
+and VQSHLU.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 The size-and-immediate encoding here is the same as Neon, and we
 handle it the same way neon-dp.decode does.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.h    |  1 +
+ target/arm/helper-mve.h    | 16 +++++++++++
- target/arm/helper-a64.c    | 13 +++++++++++++
+ target/arm/mve.decode      | 23 +++++++++++++++
- target/arm/translate-a64.c |  5 +++++
+ target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
-files changed, 19 insertions(+)
+ target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
+files changed, 147 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
---- a/target/arm/helper-a64.h
+index XXXXXXX..XXXXXXX 100644
-+++ b/target/arm/helper-a64.h
+--- a/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
++++ b/target/arm/helper-mve.h
- DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
+ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
++
-index XXXXXXX..XXXXXXX 100644
++DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
---- a/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+++ b/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
++
 +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  &2op qd qm qn size
  &2scalar qd qn rm size
  &1imm qd imm cmode op
 +&2shift qd qm shift size
  @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
  # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
  @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
  @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 +@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
 +@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 +@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 +
  # Vector loads and stores
  # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
  # So we have a single decode line and check the cmode/op in the
  # trans function.
  Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
 +
 +# Shifts by immediate
 +
 +VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
 +VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
 +VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 +
 +VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
 +VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
 +VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
 +
 +VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
 +VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
 +VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
 +
 +VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
 +VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
 +VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
      WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
  #define DO_UQRSHL_OP(N, M, satp) \
      WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
 +#define DO_SUQSHL_OP(N, M, satp) \
 +    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
  DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
  DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
  DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +
 +/* Shifts by immediate */
 +#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        TYPE *d = vd, *m = vm;                                  \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
 +            mergemask(&d[H##ESIZE(e)],                          \
 +                      FN(m[H##ESIZE(e)], shift), mask);         \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        TYPE *d = vd, *m = vm;                                  \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        bool qc = false;                                        \
 +        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
 +            bool sat = false;                                   \
 +            mergemask(&d[H##ESIZE(e)],                          \
 +                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
 +            qc |= sat & mask & 1;                               \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +/* provide unsigned 2-op shift helpers for all sizes */
 +#define DO_2SHIFT_U(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
 +    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
 +    DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +
 +#define DO_2SHIFT_SAT_U(OP, FN)                 \
 +    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
 +    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
 +    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_SAT_S(OP, FN)                 \
 +    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
 +    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
 +    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
 +
 +DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
 +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
      }
-     return float16_to_uint16(a, fpst);
+     return do_1imm(s, a, fn);
  }
 +
-+/*
++static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
-+ * Square Root and Reciprocal square root
++                      bool negateshift)
 + */
 +
 +float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
 +{
-+    float_status *s = fpstp;
++    TCGv_ptr qd, qm;
-+
++    int shift = a->shift;
-+    return float16_sqrt(a, s);
++
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd | a->qm) ||
 +        !fn) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
 +     * When we handle a right shift insn using a left-shift helper
 +     * which permits a negative shift count to indicate a right-shift,
 +     * we must negate the shift count.
 +     */
 +    if (negateshift) {
 +        shift = -shift;
 +    }
 +
 +    qd = mve_qreg_ptr(a->qd);
 +    qm = mve_qreg_ptr(a->qm);
 +    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
 +    tcg_temp_free_ptr(qd);
 +    tcg_temp_free_ptr(qm);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
-+
++#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-index XXXXXXX..XXXXXXX 100644
++    {                                                           \
---- a/target/arm/translate-a64.c
++        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+++ b/target/arm/translate-a64.c
++            gen_helper_mve_##FN##b,                             \
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
++            gen_helper_mve_##FN##h,                             \
-     case 0x6f: /* FNEG */
++            gen_helper_mve_##FN##w,                             \
-         need_fpst = false;
++            NULL,                                               \
-         break;
++        };                                                      \
-+    case 0x7f: /* FSQRT (vector) */
++        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
-+        break;
++    }
-     default:
++
-         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
++DO_2SHIFT(VSHLI, vshli_u, false)
-         g_assert_not_reached();
++DO_2SHIFT(VQSHLI_S, vqshli_s, false)
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
++DO_2SHIFT(VQSHLI_U, vqshli_u, false)
-             case 0x6f: /* FNEG */
++DO_2SHIFT(VQSHLUI, vqshlui_s, false)
                  tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
                  break;
 +            case 0x7f: /* FSQRT */
 +                gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
 +                break;
              default:
                  g_assert_not_reached();
              }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 18/42] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
+[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE vector shift right by immediate insns VSHRI and
 VRSHRI.  As with Neon, we implement these by using helper functions
 which perform left shifts but allow negative shift counts to indicate
 right shifts.
-These use the generic float16_compare functionality which in turn uses
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-the common float_compare code from the softfloat re-factor.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h     | 12 ++++++++++++
  target/arm/translate.h      | 20 ++++++++++++++++++++
  target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
  target/arm/mve_helper.c     |  7 +++++++
  target/arm/translate-mve.c  |  5 +++++
  target/arm/translate-neon.c | 18 ------------------
 files changed, 72 insertions(+), 18 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper-a64.h    |  5 +++++
  target/arm/helper-a64.c    | 49 ++++++++++++++++++++++++++++++++++++++++++++++
  target/arm/translate-a64.c | 15 ++++++++++++++
 files changed, 69 insertions(+)
 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-a64.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
+ DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
+ DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
++DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
++DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
++DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
++
-+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+ DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/target/arm/translate.h
-+++ b/target/arm/helper-a64.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(min)
+@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
- ADVSIMD_HALFOP(max)
+     return x * 2 + 1;
- ADVSIMD_HALFOP(minnum)
+ }
- ADVSIMD_HALFOP(maxnum)
-+
++static inline int rsub_64(DisasContext *s, int x)
 +/*
 + * Floating point comparisons produce an integer result. Softfloat
 + * routines return float_relation types which we convert to the 0/-1
 + * Neon requires.
 + */
 +
 +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 +
 +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
 +{
-+    float_status *fpst = fpstp;
++    return 64 - x;
 +    int compare = float16_compare_quiet(a, b, fpst);
 +    return ADVSIMD_CMPRES(compare == float_relation_equal);
 +}
 +
-+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
++static inline int rsub_32(DisasContext *s, int x)
 +{
-+    float_status *fpst = fpstp;
++    return 32 - x;
 +    int compare = float16_compare(a, b, fpst);
 +    return ADVSIMD_CMPRES(compare == float_relation_greater ||
 +                          compare == float_relation_equal);
 +}
 +
-+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
++static inline int rsub_16(DisasContext *s, int x)
 +{
-+    float_status *fpst = fpstp;
++    return 16 - x;
 +    int compare = float16_compare(a, b, fpst);
 +    return ADVSIMD_CMPRES(compare == float_relation_greater);
 +}
 +
-+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
++static inline int rsub_8(DisasContext *s, int x)
 +{
-+    float_status *fpst = fpstp;
++    return 8 - x;
 +    float16 f0 = float16_abs(a);
 +    float16 f1 = float16_abs(b);
 +    int compare = float16_compare(f0, f1, fpst);
 +    return ADVSIMD_CMPRES(compare == float_relation_greater ||
 +                          compare == float_relation_equal);
 +}
 +
-+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+ static inline int arm_dc_feature(DisasContext *dc, int feature)
-+{
+ {
-+    float_status *fpst = fpstp;
+     return (dc->features & (1ULL << feature)) != 0;
-+    float16 f0 = float16_abs(a);
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 +    float16 f1 = float16_abs(b);
 +    int compare = float16_compare(f0, f1, fpst);
 +    return ADVSIMD_CMPRES(compare == float_relation_greater);
 +}
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/mve.decode
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@
-         case 0x2: /* FADD */
+ @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+ @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
-             break;
-+        case 0x4: /* FCMEQ */
++# Right shifts are encoded as N - shift, where N is the element size in bits.
-+            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
++%rshift_i5  16:5 !function=rsub_32
-+            break;
++%rshift_i4  16:4 !function=rsub_16
-         case 0x6: /* FMAX */
++%rshift_i3  16:3 !function=rsub_8
-             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
++
-             break;
++@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
++         size=0 shift=%rshift_i3
-         case 0x13: /* FMUL */
++@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
-             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
++         size=1 shift=%rshift_i4
-             break;
++@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
-+        case 0x14: /* FCMGE */
++         size=2 shift=%rshift_i5
-+            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
++
-+            break;
+ # Vector loads and stores
-+        case 0x15: /* FACGE */
-+            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+ # Widening loads and narrowing stores:
-+            break;
+@@ -XXX,XX +XXX,XX @@ VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-         case 0x17: /* FDIV */
+ VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
-             gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+ VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
-             break;
+ VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
++
-             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
++VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
-             tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
++VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
-             break;
++VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
-+        case 0x1c: /* FCMGT */
++
-+            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
++VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
-+            break;
++VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
-+        case 0x1d: /* FACGT */
++VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
-+            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
++
-+            break;
++VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
-         default:
++VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
-             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
++VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
-                     __func__, insn, fpopcode, s->pc);
++
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
      DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
      DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_S(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, int8_t, FN)             \
 +    DO_2SHIFT(OP##h, 2, int16_t, FN)            \
 +    DO_2SHIFT(OP##w, 4, int32_t, FN)
  #define DO_2SHIFT_SAT_U(OP, FN)                 \
      DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
  DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_S(vshli_s, DO_VSHLS)
  DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
  DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 +DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 +DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
  DO_2SHIFT(VQSHLI_S, vqshli_s, false)
  DO_2SHIFT(VQSHLI_U, vqshli_u, false)
  DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 +/* These right shifts use a left-shift helper with negated shift count */
 +DO_2SHIFT(VSHRI_S, vshli_s, true)
 +DO_2SHIFT(VSHRI_U, vshli_u, true)
 +DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 +DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
      return x + 1;
  }
 -static inline int rsub_64(DisasContext *s, int x)
 -{
 -    return 64 - x;
 -}
 -
 -static inline int rsub_32(DisasContext *s, int x)
 -{
 -    return 32 - x;
 -}
 -static inline int rsub_16(DisasContext *s, int x)
 -{
 -    return 16 - x;
 -}
 -static inline int rsub_8(DisasContext *s, int x)
 -{
 -    return 8 - x;
 -}
 -
  static inline int neon_3same_fp_size(DisasContext *s, int x)
  {
      /* Convert 0==fp32, 1==fp16 into a MO_* value */
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
+[PULL 15/24] target/arm: Implement MVE VSHLL
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE VHLL (vector shift left long) insn.  This has two
 encodings: the T1 encoding is the usual shift-by-immediate format,
 and the T2 encoding is a special case where the shift count is always
 equal to the element size.
-This adds the full range of half-precision floating point to integral
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-instructions.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  9 +++++++
  target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
  target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
  target/arm/translate-mve.c | 15 +++++++++++
 files changed, 105 insertions(+), 4 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper-a64.h    |   2 +
  target/arm/helper-a64.c    |  22 ++++++++
  target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++++--
 files changed, 142 insertions(+), 5 deletions(-)
 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-a64.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
++
-+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
++DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/target/arm/mve.decode
-+++ b/target/arm/helper-a64.c
++++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+@@ -XXX,XX +XXX,XX @@
-     int compare = float16_compare(f0, f1, fpst);
+ @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-     return ADVSIMD_CMPRES(compare == float_relation_greater);
+ @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
- }
 +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
 +@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 +# VSHLL encoding T2 where shift == esize
 +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
 +                qd=%qd qm=%qm size=0 shift=8
 +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
 +                qd=%qd qm=%qm size=1 shift=16
 +
-+/* round to integral */
+ # Right shifts are encoded as N - shift, where N is the element size in bits.
-+float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+ %rshift_i5  16:5 !function=rsub_32
  %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
  VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
  VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 -VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 -VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +# The VSHLL T2 encoding is not a @2op pattern, but is here because it
 +# overlaps what would be size=0b11 VMULH/VRMULH
 +{
-+    return float16_round_to_int(x, fp_status);
++  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
 +  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 -VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 -VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +}
 +
-+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 +{
-+    int old_flags = get_float_exception_flags(fp_status), new_flags;
++  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+    float16 ret;
++  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 +
-+    ret = float16_round_to_int(x, fp_status);
++  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +}
 +
-+    /* Suppress any inexact exceptions the conversion produced */
++{
-+    if (!(old_flags & float_flag_inexact)) {
++  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+        new_flags = get_float_exception_flags(fp_status);
++  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+        set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
++
 +  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +}
 +
 +{
 +  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
 +  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
 +
 +  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +}
  VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
  VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
 +VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +
 +/*
 + * Long shifts taking half-sized inputs from top or bottom of the input
 + * vector and producing a double-width result. ESIZE, TYPE are for
 + * the input, and LESIZE, LTYPE for the output.
 + * Unlike the normal shift helpers, we do not handle negative shift counts,
 + * because the long shift is strictly left-only.
 + */
 +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
 +                                void *vm, uint32_t shift)               \
 +    {                                                                   \
 +        LTYPE *d = vd;                                                  \
 +        TYPE *m = vm;                                                   \
 +        uint16_t mask = mve_element_mask(env);                          \
 +        unsigned le;                                                    \
 +        assert(shift <= 16);                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
 +            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
 +            mergemask(&d[H##LESIZE(le)], r, mask);                      \
 +        }                                                               \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
-+    return ret;
++#define DO_VSHLL_ALL(OP, TOP)                                \
-+}
++    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
 +    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
 +    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
 +
 +DO_VSHLL_ALL(vshllb, false)
 +DO_VSHLL_ALL(vshllt, true)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
-  */
+ DO_2SHIFT(VSHRI_U, vshli_u, true)
- static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+ DO_2SHIFT(VRSHRI_S, vrshli_s, true)
- {
+ DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 -    int fpop, opcode, a;
 +    int fpop, opcode, a, u;
 +    int rn, rd;
 +    bool is_q;
 +    bool is_scalar;
 +    bool only_in_vector = false;
 +
-+    int pass;
++#define DO_VSHLL(INSN, FN)                                      \
-+    TCGv_i32 tcg_rmode = NULL;
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+    TCGv_ptr tcg_fpstatus = NULL;
++    {                                                           \
-+    bool need_rmode = false;
++        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+    int rmode;
++            gen_helper_mve_##FN##b,                             \
++            gen_helper_mve_##FN##h,                             \
-     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
++        };                                                      \
-         unallocated_encoding(s);
++        return do_2shift(s, a, fns[a->size], false);            \
          return;
      }
 -    if (!fp_access_check(s)) {
 -        return;
 -    }
 +    rd = extract32(insn, 0, 5);
 +    rn = extract32(insn, 5, 5);
 -    opcode = extract32(insn, 12, 4);
      a = extract32(insn, 23, 1);
 +    u = extract32(insn, 29, 1);
 +    is_scalar = extract32(insn, 28, 1);
 +    is_q = extract32(insn, 30, 1);
 +
 +    opcode = extract32(insn, 12, 5);
      fpop = deposit32(opcode, 5, 1, a);
 +    fpop = deposit32(fpop, 6, 1, u);
      switch (fpop) {
 +    case 0x18: /* FRINTN */
 +        need_rmode = true;
 +        only_in_vector = true;
 +        rmode = FPROUNDING_TIEEVEN;
 +        break;
 +    case 0x19: /* FRINTM */
 +        need_rmode = true;
 +        only_in_vector = true;
 +        rmode = FPROUNDING_NEGINF;
 +        break;
 +    case 0x38: /* FRINTP */
 +        need_rmode = true;
 +        only_in_vector = true;
 +        rmode = FPROUNDING_POSINF;
 +        break;
 +    case 0x39: /* FRINTZ */
 +        need_rmode = true;
 +        only_in_vector = true;
 +        rmode = FPROUNDING_ZERO;
 +        break;
 +    case 0x58: /* FRINTA */
 +        need_rmode = true;
 +        only_in_vector = true;
 +        rmode = FPROUNDING_TIEAWAY;
 +        break;
 +    case 0x59: /* FRINTX */
 +    case 0x79: /* FRINTI */
 +        only_in_vector = true;
 +        /* current rounding mode */
 +        break;
      default:
          fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
          g_assert_not_reached();
      }
 +
 +    /* Check additional constraints for the scalar encoding */
 +    if (is_scalar) {
 +        if (!is_q) {
 +            unallocated_encoding(s);
 +            return;
 +        }
 +        /* FRINTxx is only in the vector form */
 +        if (only_in_vector) {
 +            unallocated_encoding(s);
 +            return;
 +        }
 +    }
 +
-+    if (!fp_access_check(s)) {
++DO_VSHLL(VSHLL_BS, vshllbs)
-+        return;
++DO_VSHLL(VSHLL_BU, vshllbu)
-+    }
++DO_VSHLL(VSHLL_TS, vshllts)
-+
++DO_VSHLL(VSHLL_TU, vshlltu)
 +    if (need_rmode) {
 +        tcg_fpstatus = get_fpstatus_ptr(true);
 +    }
 +
 +    if (need_rmode) {
 +        tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
 +        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
 +    }
 +
 +    if (is_scalar) {
 +        /* no operations yet */
 +    } else {
 +        for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
 +            TCGv_i32 tcg_op = tcg_temp_new_i32();
 +            TCGv_i32 tcg_res = tcg_temp_new_i32();
 +
 +            read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
 +
 +            switch (fpop) {
 +            case 0x18: /* FRINTN */
 +            case 0x19: /* FRINTM */
 +            case 0x38: /* FRINTP */
 +            case 0x39: /* FRINTZ */
 +            case 0x58: /* FRINTA */
 +            case 0x79: /* FRINTI */
 +                gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
 +                break;
 +            case 0x59: /* FRINTX */
 +                gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
 +                break;
 +            default:
 +                g_assert_not_reached();
 +            }
 +
 +            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
 +
 +            tcg_temp_free_i32(tcg_res);
 +            tcg_temp_free_i32(tcg_op);
 +        }
 +
 +        clear_vec_high(s, is_q, rd);
 +    }
 +
 +    if (tcg_rmode) {
 +        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
 +        tcg_temp_free_i32(tcg_rmode);
 +    }
 +
 +    if (tcg_fpstatus) {
 +        tcg_temp_free_ptr(tcg_fpstatus);
 +    }
  }
  /* AdvSIMD scalar x indexed element
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16
+[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE VSRI and VSLI insns, which perform a
 shift-and-insert operation.
-Much like recpe the ARM ARM has simplified the pseudo code for the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-calculation which is done on a fixed point 9 bit integer maths. So
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-while adding f16 we can also clean this up to be a little less heavy
+Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
-on the floating point and just return the fractional part and leave
+---
-the calle's to do the final packing of the result.
+ target/arm/helper-mve.h    |  8 ++++++++
  target/arm/mve.decode      |  9 ++++++++
  target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c |  3 +++
 files changed, 62 insertions(+)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-27-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.h |   1 +
  target/arm/helper.c | 221 ++++++++++++++++++++++++----------------------------
 files changed, 104 insertions(+), 118 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/helper.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
++
- DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
++DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
++DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_2(recpe_u32, i32, i32, ptr)
++DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
++
 +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/mve.decode
-+++ b/target/arm/helper.c
++++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
+@@ -XXX,XX +XXX,XX @@ VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
- /* The algorithm that must be used to calculate the estimate
-  * is specified by the ARM ARM.
+ VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
-  */
+ VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 -static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
 +
-+static int do_recip_sqrt_estimate(int a)
++# Shift-and-insert
- {
++VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
--    /* These calculations mustn't set any fp exception flags,
++VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
--     * so we use a local copy of the fp_status.
++VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
 -     */
 -    float_status dummy_status = *real_fp_status;
 -    float_status *s = &dummy_status;
 -    float64 q;
 -    int64_t q_int;
 +    int b, estimate;
 -    if (float64_lt(a, float64_half, s)) {
 -        /* range 0.25 <= a < 0.5 */
 -
 -        /* a in units of 1/512 rounded down */
 -        /* q0 = (int)(a * 512.0);  */
 -        q = float64_mul(float64_512, a, s);
 -        q_int = float64_to_int64_round_to_zero(q, s);
 -
 -        /* reciprocal root r */
 -        /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
 -        q = int64_to_float64(q_int, s);
 -        q = float64_add(q, float64_half, s);
 -        q = float64_div(q, float64_512, s);
 -        q = float64_sqrt(q, s);
 -        q = float64_div(float64_one, q, s);
 +    assert(128 <= a && a < 512);
 +    if (a < 256) {
 +        a = a * 2 + 1;
      } else {
 -        /* range 0.5 <= a < 1.0 */
 -
 -        /* a in units of 1/256 rounded down */
 -        /* q1 = (int)(a * 256.0); */
 -        q = float64_mul(float64_256, a, s);
 -        int64_t q_int = float64_to_int64_round_to_zero(q, s);
 -
 -        /* reciprocal root r */
 -        /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
 -        q = int64_to_float64(q_int, s);
 -        q = float64_add(q, float64_half, s);
 -        q = float64_div(q, float64_256, s);
 -        q = float64_sqrt(q, s);
 -        q = float64_div(float64_one, q, s);
 +        a = (a >> 1) << 1;
 +        a = (a + 1) * 2;
      }
 -    /* r in units of 1/256 rounded to nearest */
 -    /* s = (int)(256.0 * r + 0.5); */
 +    b = 512;
 +    while (a * (b + 1) * (b + 1) < (1 << 28)) {
 +        b += 1;
 +    }
 +    estimate = (b + 1) / 2;
 +    assert(256 <= estimate && estimate < 512);
 -    q = float64_mul(q, float64_256,s );
 -    q = float64_add(q, float64_half, s);
 -    q_int = float64_to_int64_round_to_zero(q, s);
 +    return estimate;
 +}
 -    /* return (double)s / 256.0;*/
 -    return float64_div(int64_to_float64(q_int, s), float64_256, s);
 +
-+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
++VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-+{
++VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
-+    int estimate;
++VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
-+    uint32_t scaled;
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-+
+index XXXXXXX..XXXXXXX 100644
-+    if (*exp == 0) {
+--- a/target/arm/mve_helper.c
-+        while (extract64(frac, 51, 1) == 0) {
++++ b/target/arm/mve_helper.c
-+            frac = frac << 1;
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
-+            *exp -= 1;
+ DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
-+        }
+ DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
-+        frac = extract64(frac, 0, 51) << 1;
 +/* Shift-and-insert; we always work with 64 bits at a time */
 +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN)                    \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
 +                                void *vm, uint32_t shift)               \
 +    {                                                                   \
 +        uint64_t *d = vd, *m = vm;                                      \
 +        uint16_t mask;                                                  \
 +        uint64_t shiftmask;                                             \
 +        unsigned e;                                                     \
 +        if (shift == 0 || shift == ESIZE * 8) {                         \
 +            /*                                                          \
 +             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
 +             * The generic logic would give the right answer for 0 but  \
 +             * fails for <dt>.                                          \
 +             */                                                         \
 +            goto done;                                                  \
 +        }                                                               \
 +        assert(shift < ESIZE * 8);                                      \
 +        mask = mve_element_mask(env);                                   \
 +        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \
 +        shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift));     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) |       \
 +                (d[H8(e)] & ~shiftmask);                                \
 +            mergemask(&d[H8(e)], r, mask);                              \
 +        }                                                               \
 +done:                                                                   \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
-+    if (*exp & 1) {
++#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
-+        /* scaled = UInt('01':fraction<51:45>) */
++#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
-+        scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
++#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
-+    } else {
++#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
 +        /* scaled = UInt('1':fraction<51:44>) */
 +        scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
 +    }
 +    estimate = do_recip_sqrt_estimate(scaled);
 +
-+    *exp = (exp_off - *exp) / 2;
++DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
-+    return extract64(estimate, 0, 8) << 44;
++DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
-+}
++DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
 +
-+float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+ /*
-+{
+  * Long shifts taking half-sized inputs from top or bottom of the input
-+    float_status *s = fpstp;
+  * vector and producing a double-width result. ESIZE, TYPE are for
-+    float16 f16 = float16_squash_input_denormal(input, s);
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-+    uint16_t val = float16_val(f16);
+index XXXXXXX..XXXXXXX 100644
-+    bool f16_sign = float16_is_neg(f16);
+--- a/target/arm/translate-mve.c
-+    int f16_exp = extract32(val, 10, 5);
++++ b/target/arm/translate-mve.c
-+    uint16_t f16_frac = extract32(val, 0, 10);
+@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
-+    uint64_t f64_frac;
+ DO_2SHIFT(VRSHRI_S, vrshli_s, true)
  DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 +DO_2SHIFT(VSRI, vsri, false)
 +DO_2SHIFT(VSLI, vsli, false)
 +
-+    if (float16_is_any_nan(f16)) {
+ #define DO_VSHLL(INSN, FN)                                      \
-+        float16 nan = f16;
+     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+        if (float16_is_signaling_nan(f16, s)) {
+     {                                                           \
 +            float_raise(float_flag_invalid, s);
 +            nan = float16_maybe_silence_nan(f16, s);
 +        }
 +        if (s->default_nan_mode) {
 +            nan =  float16_default_nan(s);
 +        }
 +        return nan;
 +    } else if (float16_is_zero(f16)) {
 +        float_raise(float_flag_divbyzero, s);
 +        return float16_set_sign(float16_infinity, f16_sign);
 +    } else if (f16_sign) {
 +        float_raise(float_flag_invalid, s);
 +        return float16_default_nan(s);
 +    } else if (float16_is_infinity(f16)) {
 +        return float16_zero;
 +    }
 +
 +    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
 +     * preserving the parity of the exponent.  */
 +
 +    f64_frac = ((uint64_t) f16_frac) << (52 - 10);
 +
 +    f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
 +
 +    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
 +    val = deposit32(0, 15, 1, f16_sign);
 +    val = deposit32(val, 10, 5, f16_exp);
 +    val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
 +    return make_float16(val);
  }
  float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
      float_status *s = fpstp;
      float32 f32 = float32_squash_input_denormal(input, s);
      uint32_t val = float32_val(f32);
 -    uint32_t f32_sbit = 0x80000000 & val;
 -    int32_t f32_exp = extract32(val, 23, 8);
 +    uint32_t f32_sign = float32_is_neg(f32);
 +    int f32_exp = extract32(val, 23, 8);
      uint32_t f32_frac = extract32(val, 0, 23);
      uint64_t f64_frac;
 -    uint64_t val64;
 -    int result_exp;
 -    float64 f64;
      if (float32_is_any_nan(f32)) {
          float32 nan = f32;
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
       * preserving the parity of the exponent.  */
      f64_frac = ((uint64_t) f32_frac) << 29;
 -    if (f32_exp == 0) {
 -        while (extract64(f64_frac, 51, 1) == 0) {
 -            f64_frac = f64_frac << 1;
 -            f32_exp = f32_exp-1;
 -        }
 -        f64_frac = extract64(f64_frac, 0, 51) << 1;
 -    }
 -    if (extract64(f32_exp, 0, 1) == 0) {
 -        f64 = make_float64(((uint64_t) f32_sbit) << 32
 -                           | (0x3feULL << 52)
 -                           | f64_frac);
 -    } else {
 -        f64 = make_float64(((uint64_t) f32_sbit) << 32
 -                           | (0x3fdULL << 52)
 -                           | f64_frac);
 -    }
 +    f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
 -    result_exp = (380 - f32_exp) / 2;
 -
 -    f64 = recip_sqrt_estimate(f64, s);
 -
 -    val64 = float64_val(f64);
 -
 -    val = ((result_exp & 0xff) << 23)
 -        | ((val64 >> 29)  & 0x7fffff);
 +    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
 +    val = deposit32(0, 31, 1, f32_sign);
 +    val = deposit32(val, 23, 8, f32_exp);
 +    val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
      return make_float32(val);
  }
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
      float_status *s = fpstp;
      float64 f64 = float64_squash_input_denormal(input, s);
      uint64_t val = float64_val(f64);
 -    uint64_t f64_sbit = 0x8000000000000000ULL & val;
 -    int64_t f64_exp = extract64(val, 52, 11);
 +    bool f64_sign = float64_is_neg(f64);
 +    int f64_exp = extract64(val, 52, 11);
      uint64_t f64_frac = extract64(val, 0, 52);
 -    int64_t result_exp;
 -    uint64_t result_frac;
      if (float64_is_any_nan(f64)) {
          float64 nan = f64;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
          return float64_zero;
      }
 -    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
 -     * preserving the parity of the exponent.  */
 +    f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
 -    if (f64_exp == 0) {
 -        while (extract64(f64_frac, 51, 1) == 0) {
 -            f64_frac = f64_frac << 1;
 -            f64_exp = f64_exp - 1;
 -        }
 -        f64_frac = extract64(f64_frac, 0, 51) << 1;
 -    }
 -
 -    if (extract64(f64_exp, 0, 1) == 0) {
 -        f64 = make_float64(f64_sbit
 -                           | (0x3feULL << 52)
 -                           | f64_frac);
 -    } else {
 -        f64 = make_float64(f64_sbit
 -                           | (0x3fdULL << 52)
 -                           | f64_frac);
 -    }
 -
 -    result_exp = (3068 - f64_exp) / 2;
 -
 -    f64 = recip_sqrt_estimate(f64, s);
 -
 -    result_frac = extract64(float64_val(f64), 0, 52);
 -
 -    return make_float64(f64_sbit |
 -                        ((result_exp & 0x7ff) << 52) |
 -                        result_frac);
 +    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
 +    val = deposit64(0, 61, 1, f64_sign);
 +    val = deposit64(val, 52, 11, f64_exp);
 +    val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
 +    return make_float64(val);
  }
  uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
  uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
  {
 -    float_status *fpst = fpstp;
 -    float64 f64;
 +    int estimate;
      if ((a & 0xc0000000) == 0) {
          return 0xffffffff;
      }
 -    if (a & 0x80000000) {
 -        f64 = make_float64((0x3feULL << 52)
 -                           | ((uint64_t)(a & 0x7fffffff) << 21));
 -    } else { /* bits 31-30 == '01' */
 -        f64 = make_float64((0x3fdULL << 52)
 -                           | ((uint64_t)(a & 0x3fffffff) << 22));
 -    }
 +    estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
 -    f64 = recip_sqrt_estimate(f64, fpst);
 -
 -    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
 +    return deposit32(0, 23, 9, estimate);
  }
  /* VFPv4 fused multiply-accumulate */
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
+[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
-This covers all the floating point convert operations.
+do_urshr() is borrowed from sve_helper.c.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.h    |  2 ++
+ target/arm/helper-mve.h    | 10 ++++++++++
- target/arm/helper-a64.c    | 32 +++++++++++++++++
+ target/arm/mve.decode      | 11 +++++++++++
- target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++-
+ target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
-files changed, 118 insertions(+), 1 deletion(-)
+ target/arm/translate-mve.c | 15 ++++++++++++++
 files changed, 76 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-a64.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
++
-+DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
++DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/target/arm/mve.decode
-+++ b/target/arm/helper-a64.c
++++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+@@ -XXX,XX +XXX,XX @@ VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
+ VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-     return ret;
+ VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
- }
+ VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 +
 +# Narrowing shifts (which only support b and h sizes)
 +VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 +VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 +VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 +VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 +
 +VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 +VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 +VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 +VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
  DO_VSHLL_ALL(vshllb, false)
  DO_VSHLL_ALL(vshllt, true)
 +
 +/*
-+ * Half-precision floating point conversion functions
++ * Narrowing right shifts, taking a double sized input, shifting it
-+ *
++ * and putting the result in either the top or bottom half of the output.
-+ * There are a multitude of conversion functions with various
++ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
 + * different rounding modes. This is dealt with by the calling code
 + * setting the mode appropriately before calling the helper.
 + */
++#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)       \
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
++                                void *vm, uint32_t shift)       \
++    {                                                           \
++        LTYPE *m = vm;                                          \
++        TYPE *d = vd;                                           \
++        uint16_t mask = mve_element_mask(env);                  \
++        unsigned le;                                            \
++        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
++            TYPE r = FN(m[H##LESIZE(le)], shift);               \
++            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
++        }                                                       \
++        mve_advance_vpt(env);                                   \
++    }
 +
-+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
++#define DO_VSHRN_ALL(OP, FN)                                    \
 +    DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN)        \
 +    DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN)       \
 +    DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN)         \
 +    DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
 +
 +static inline uint64_t do_urshr(uint64_t x, unsigned sh)
 +{
-+    float_status *fpst = fpstp;
++    if (likely(sh < 64)) {
-+
++        return (x >> sh) + ((x >> (sh - 1)) & 1);
-+    /* Invalid if we are passed a NaN */
++    } else if (sh == 64) {
-+    if (float16_is_any_nan(a)) {
++        return x >> 63;
-+        float_raise(float_flag_invalid, fpst);
++    } else {
 +        return 0;
 +    }
-+    return float16_to_int16(a, fpst);
 +}
 +
-+uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
++DO_VSHRN_ALL(vshrn, DO_SHR)
-+{
++DO_VSHRN_ALL(vrshrn, do_urshr)
-+    float_status *fpst = fpstp;
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
  DO_VSHLL(VSHLL_BU, vshllbu)
  DO_VSHLL(VSHLL_TS, vshllts)
  DO_VSHLL(VSHLL_TU, vshlltu)
 +
-+    /* Invalid if we are passed a NaN */
++#define DO_2SHIFT_N(INSN, FN)                                   \
-+    if (float16_is_any_nan(a)) {
++    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+        float_raise(float_flag_invalid, fpst);
++    {                                                           \
-+        return 0;
++        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], false);            \
 +    }
-+    return float16_to_uint16(a, fpst);
-+}
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         only_in_vector = true;
-         /* current rounding mode */
-         break;
-+    case 0x1a: /* FCVTNS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEEVEN;
-+        break;
-+    case 0x1b: /* FCVTMS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_NEGINF;
-+        break;
-+    case 0x1c: /* FCVTAS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEAWAY;
-+        break;
-+    case 0x3a: /* FCVTPS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_POSINF;
-+        break;
-+    case 0x3b: /* FCVTZS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_ZERO;
-+        break;
-+    case 0x5a: /* FCVTNU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEEVEN;
-+        break;
-+    case 0x5b: /* FCVTMU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_NEGINF;
-+        break;
-+    case 0x5c: /* FCVTAU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEAWAY;
-+        break;
-+    case 0x7a: /* FCVTPU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_POSINF;
-+        break;
-+    case 0x7b: /* FCVTZU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_ZERO;
-+        break;
-     default:
-         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
-         g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     }
-     if (is_scalar) {
--        /* no operations yet */
-+        TCGv_i32 tcg_op = tcg_temp_new_i32();
-+        TCGv_i32 tcg_res = tcg_temp_new_i32();
 +
-+        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
++DO_2SHIFT_N(VSHRNB, vshrnb)
-+
++DO_2SHIFT_N(VSHRNT, vshrnt)
-+        switch (fpop) {
++DO_2SHIFT_N(VRSHRNB, vrshrnb)
-+        case 0x1a: /* FCVTNS */
++DO_2SHIFT_N(VRSHRNT, vrshrnt)
 +        case 0x1b: /* FCVTMS */
 +        case 0x1c: /* FCVTAS */
 +        case 0x3a: /* FCVTPS */
 +        case 0x3b: /* FCVTZS */
 +            gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
 +            break;
 +        case 0x5a: /* FCVTNU */
 +        case 0x5b: /* FCVTMU */
 +        case 0x5c: /* FCVTAU */
 +        case 0x7a: /* FCVTPU */
 +        case 0x7b: /* FCVTZU */
 +            gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +
 +        /* limit any sign extension going on */
 +        tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
 +        write_fp_sreg(s, rd, tcg_res);
 +
 +        tcg_temp_free_i32(tcg_res);
 +        tcg_temp_free_i32(tcg_op);
      } else {
          for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
              TCGv_i32 tcg_op = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
              read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
              switch (fpop) {
 +            case 0x1a: /* FCVTNS */
 +            case 0x1b: /* FCVTMS */
 +            case 0x1c: /* FCVTAS */
 +            case 0x3a: /* FCVTPS */
 +            case 0x3b: /* FCVTZS */
 +                gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
 +                break;
 +            case 0x5a: /* FCVTNU */
 +            case 0x5b: /* FCVTMU */
 +            case 0x5c: /* FCVTAU */
 +            case 0x7a: /* FCVTPU */
 +            case 0x7b: /* FCVTZU */
 +                gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
 +                break;
              case 0x18: /* FRINTN */
              case 0x19: /* FRINTM */
              case 0x38: /* FRINTP */
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
+[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE saturating shift-right-and-narrow insns
+VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
-We go with the localised helper.
+do_srshr() is borrowed from sve_helper.c.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.h    |  1 +
+ target/arm/helper-mve.h    |  30 +++++++++++
- target/arm/helper-a64.c    | 29 +++++++++++++++++++++++++++++
+ target/arm/mve.decode      |  28 ++++++++++
- target/arm/translate-a64.c |  4 ++++
+ target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
-files changed, 34 insertions(+)
+ target/arm/translate-mve.c |  12 +++++
+files changed, 174 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
---- a/target/arm/helper-a64.h
+index XXXXXXX..XXXXXXX 100644
-+++ b/target/arm/helper-a64.h
+--- a/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
++++ b/target/arm/helper-mve.h
- DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
++
- DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-index XXXXXXX..XXXXXXX 100644
++DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
---- a/target/arm/helper-a64.c
++
-+++ b/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
++DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
  VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
  VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
  VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 +
 +VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
 +
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
      }
  }
- /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
++static inline int64_t do_srshr(int64_t x, unsigned sh)
 +float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
 +{
-+    float_status *fpst = fpstp;
++    if (likely(sh < 64)) {
-+    uint16_t val16, sbit;
++        return (x >> sh) + ((x >> (sh - 1)) & 1);
 +    int16_t exp;
 +
 +    if (float16_is_any_nan(a)) {
 +        float16 nan = a;
 +        if (float16_is_signaling_nan(a, fpst)) {
 +            float_raise(float_flag_invalid, fpst);
 +            nan = float16_maybe_silence_nan(a, fpst);
 +        }
 +        if (fpst->default_nan_mode) {
 +            nan = float16_default_nan(fpst);
 +        }
 +        return nan;
 +    }
 +
 +    val16 = float16_val(a);
 +    sbit = 0x8000 & val16;
 +    exp = extract32(val16, 10, 5);
 +
 +    if (exp == 0) {
 +        return make_float16(deposit32(sbit, 10, 5, 0x1e));
 +    } else {
-+        return make_float16(deposit32(sbit, 10, 5, ~exp));
++        /* Rounding the sign bit always produces 0. */
 +        return 0;
 +    }
 +}
 +
- float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
+ DO_VSHRN_ALL(vshrn, DO_SHR)
- {
+ DO_VSHRN_ALL(vrshrn, do_urshr)
-     float_status *fpst = fpstp;
++
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
-index XXXXXXX..XXXXXXX 100644
++                                 bool *satp)
---- a/target/arm/translate-a64.c
++{
-+++ b/target/arm/translate-a64.c
++    if (val > max) {
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
++        *satp = true;
-         handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
++        return max;
-         return;
++    } else if (val < min) {
-     case 0x3d: /* FRECPE */
++        *satp = true;
-+    case 0x3f: /* FRECPX */
++        return min;
-         break;
++    } else {
-     case 0x18: /* FRINTN */
++        return val;
-         need_rmode = true;
++    }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
++}
-         case 0x3d: /* FRECPE */
++
-             gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
++/* Saturating narrowing right shifts */
-             break;
++#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
-+        case 0x3f: /* FRECPX */
++    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+            gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
++                                void *vm, uint32_t shift)       \
-+            break;
++    {                                                           \
-         case 0x5a: /* FCVTNU */
++        LTYPE *m = vm;                                          \
-         case 0x5b: /* FCVTMU */
++        TYPE *d = vd;                                           \
-         case 0x5c: /* FCVTAU */
++        uint16_t mask = mve_element_mask(env);                  \
 +        bool qc = false;                                        \
 +        unsigned le;                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            bool sat = false;                                   \
 +            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
 +    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
 +
 +#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
 +    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
 +
 +#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
 +    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
 +
 +#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
 +    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
 +
 +#define DO_SHRN_SB(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
 +#define DO_SHRN_UB(N, M, SATP)                                  \
 +    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
 +#define DO_SHRUN_B(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
 +
 +#define DO_SHRN_SH(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_SHRN_UH(N, M, SATP)                                  \
 +    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
 +#define DO_SHRUN_H(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
 +
 +#define DO_RSHRN_SB(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
 +#define DO_RSHRN_UB(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
 +#define DO_RSHRUN_B(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
 +
 +#define DO_RSHRN_SH(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_RSHRN_UH(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
 +#define DO_RSHRUN_H(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
 +
 +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
 +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
 +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
 +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
 +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
 +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
 +
 +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
 +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
 +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
 +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
 +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
 +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
  DO_2SHIFT_N(VSHRNT, vshrnt)
  DO_2SHIFT_N(VRSHRNB, vrshrnb)
  DO_2SHIFT_N(VRSHRNT, vrshrnt)
 +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
 +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
 +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
 +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
 +DO_2SHIFT_N(VQSHRUNB, vqshrunb)
 +DO_2SHIFT_N(VQSHRUNT, vqshrunt)
 +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
 +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
 +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
 +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
 +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
 +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 41/42] linux-user: Report AArch64 FP16 support via hwcap bits
+[PULL 19/24] target/arm: Implement MVE VSHLC
-Set the appropriate Linux hwcap bits to tell the guest binary if we
+Implement the MVE VSHLC insn, which performs a shift left of the
-have implemented half-precision floating point support.
+entire vector with carry in bits provided from a general purpose
 register and carry out bits written back to that register.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
 ---
- linux-user/elfload.c | 2 ++
+ target/arm/helper-mve.h    |  2 ++
-file changed, 2 insertions(+)
+ target/arm/mve.decode      |  2 ++
  target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 files changed, 72 insertions(+)
-diff --git a/linux-user/elfload.c b/linux-user/elfload.c
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/elfload.c
+--- a/target/arm/helper-mve.h
-+++ b/linux-user/elfload.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
+ DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
+ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-     GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
+ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+    GET_FEATURE(ARM_FEATURE_V8_FP16,
++
-+                ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
++DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
- #undef GET_FEATURE
+diff --git a/target/arm/mve.decode b/target/arm/mve.decode
+index XXXXXXX..XXXXXXX 100644
-     return hwcaps;
+--- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
  VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
  VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
  VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
 +VSHLC             111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
  DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
  DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
  DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 +
 +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
 +                           uint32_t shift)
 +{
 +    uint32_t *d = vd;
 +    uint16_t mask = mve_element_mask(env);
 +    unsigned e;
 +    uint32_t r;
 +
 +    /*
 +     * For each 32-bit element, we shift it left, bringing in the
 +     * low 'shift' bits of rdm at the bottom. Bits shifted out at
 +     * the top become the new rdm, if the predicate mask permits.
 +     * The final rdm value is returned to update the register.
 +     * shift == 0 here means "shift by 32 bits".
 +     */
 +    if (shift == 0) {
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = rdm;
 +            if (mask & 1) {
 +                rdm = d[H4(e)];
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    } else {
 +        uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
 +
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = (d[H4(e)] << shift) | (rdm & shiftmask);
 +            if (mask & 1) {
 +                rdm = d[H4(e)] >> (32 - shift);
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    }
 +    mve_advance_vpt(env);
 +    return rdm;
 +}
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
  DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
  DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
  DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 +
 +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
 +{
 +    /*
 +     * Whole Vector Left Shift with Carry. The carry is taken
 +     * from a general purpose register and written back there.
 +     * An imm of 0 means "shift by 32".
 +     */
 +    TCGv_ptr qd;
 +    TCGv_i32 rdm;
 +
 +    if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
 +        return false;
 +    }
 +    if (a->rdm == 13 || a->rdm == 15) {
 +        /* CONSTRAINED UNPREDICTABLE: we UNDEF */
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    qd = mve_qreg_ptr(a->qd);
 +    rdm = load_reg(s, a->rdm);
 +    gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
 +    store_reg(s, a->rdm, rdm);
 +    tcg_temp_free_ptr(qd);
 +    mve_update_eci(s);
 +    return true;
 +}
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16
+[PULL 20/24] target/arm: Implement MVE VADDLV
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE VADDLV insn; this is similar to VADDV, except
 that it accumulates 32-bit elements into a 64-bit accumulator
 stored in a pair of general-purpose registers.
-This actually covers two different sections of the encoding table:
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
 ---
  target/arm/helper-mve.h    |  3 ++
  target/arm/mve.decode      |  6 +++-
  target/arm/mve_helper.c    | 19 ++++++++++++
  target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 files changed, 90 insertions(+), 1 deletion(-)
-   Advanced SIMD scalar two-register miscellaneous FP16
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
    Advanced SIMD two-register miscellaneous (FP16)
 The difference between the two is covered by a combination of Q (bit
 ) and S (bit 28). Notably the FRINTx instructions are only
 available in the vector form.
 This is just the decode skeleton which will be filled out by later
 patches.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++
 file changed, 40 insertions(+)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
-     }
+ DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
  DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
 +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
 +
  DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar   1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  VQRDMULH_scalar  1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  # Vector add across vector
 -VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +{
 +  VADDV          111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +  VADDLV         111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
 +                 rdahi=%rdahi rdalo=%rdalo
 +}
  # Predicate operations
  %mask_22_13      22:1 13:3
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +#define DO_VADDLV(OP, TYPE, LTYPE)                              \
 +    uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
 +                                    uint64_t ra)                \
 +    {                                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        TYPE *m = vm;                                           \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {              \
 +            if (mask & 1) {                                     \
 +                ra += (LTYPE)m[H4(e)];                          \
 +            }                                                   \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +        return ra;                                              \
 +    }                                                           \
 +
 +DO_VADDLV(vaddlv_s, int32_t, int64_t)
 +DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
 +
  /* Shifts by immediate */
  #define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
      void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      return true;
  }
-+/* AdvSIMD [scalar] two register miscellaneous (FP16)
++static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
 + *
 + *   31  30  29 28  27     24  23 22 21       17 16    12 11 10 9    5 4    0
 + * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
 + * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
 + * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
 + *   mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
 + *   val:  0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
 + *
 + * This actually covers two groups where scalar access is governed by
 + * bit 28. A bunch of the instructions (float to integral) only exist
 + * in the vector form and are un-allocated for the scalar decode. Also
 + * in the scalar decode Q is always 1.
 + */
 +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
 +{
-+    int fpop, opcode, a;
++    /*
 +     * Vector Add Long Across Vector: accumulate the 32-bit
 +     * elements of the vector into a 64-bit result stored in
 +     * a pair of general-purpose registers.
 +     * No need to check Qm's bank: it is only 3 bits in decode.
 +     */
 +    TCGv_ptr qm;
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
++    if (!dc_isar_feature(aa32_mve, s)) {
-+        unallocated_encoding(s);
++        return false;
-+        return;
++    }
 +    /*
 +     * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
 +     * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
 +     */
 +    if (a->rdahi == 13 || a->rdahi == 15) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    if (!fp_access_check(s)) {
++    /*
-+        return;
++     * This insn is subject to beat-wise execution. Partial execution
 +     * of an A=0 (no-accumulate) insn which does not execute the first
 +     * beat must start with the current value of RdaHi:RdaLo, not zero.
 +     */
 +    if (a->a || mve_skip_first_beat(s)) {
 +        /* Accumulate input from RdaHi:RdaLo */
 +        rda = tcg_temp_new_i64();
 +        rdalo = load_reg(s, a->rdalo);
 +        rdahi = load_reg(s, a->rdahi);
 +        tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +        tcg_temp_free_i32(rdalo);
 +        tcg_temp_free_i32(rdahi);
 +    } else {
 +        /* Accumulate starting at zero */
 +        rda = tcg_const_i64(0);
 +    }
 +
-+    opcode = extract32(insn, 12, 4);
++    qm = mve_qreg_ptr(a->qm);
-+    a = extract32(insn, 23, 1);
++    if (a->u) {
-+    fpop = deposit32(opcode, 5, 1, a);
++        gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
 +    } else {
 +        gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
 +    }
 +    tcg_temp_free_ptr(qm);
 +
-+    switch (fpop) {
++    rdalo = tcg_temp_new_i32();
-+    default:
++    rdahi = tcg_temp_new_i32();
-+        fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
++    tcg_gen_extrl_i64_i32(rdalo, rda);
-+        g_assert_not_reached();
++    tcg_gen_extrh_i64_i32(rdahi, rda);
-+    }
++    store_reg(s, a->rdalo, rdalo);
-+
++    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
- /* AdvSIMD scalar x indexed element
+ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
-  *  31 30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
+ {
-  * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
+     TCGv_ptr qd;
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
      { 0xce800000, 0xffe00000, disas_crypto_xar },
      { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
      { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
 +    { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
      { 0x00000000, 0x00000000, NULL }
  };
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
+[PULL 21/24] target/arm: Implement MVE long shifts by immediate
-From: Alex Bennée <alex.bennee@linaro.org>
+The MVE extension to v8.1M includes some new shift instructions which
+sit entirely within the non-coprocessor part of the encoding space
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+and which operate only on general-purpose registers.  They take up
 the space which was previously UNPREDICTABLE MOVS and ORRS encodings
 with Rm == 13 or 15.
 Implement the long shifts by immediate, which perform shifts on a
 pair of general-purpose registers treated as a 64-bit quantity, with
 an immediate shift count between 1 and 32.
 Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
 the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
 cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
 is too difficult, because the functions that generate the code are
 shared between a dozen different kinds of arithmetic or logical
 instruction for all A32, T16 and T32 encodings, and for some insns
 and some encodings Rm==13,15 are valid.)
 We make the helper functions we need for UQSHLL and SQSHLL take
 a 32-bit value which the helper casts to int8_t because we'll need
 these helpers also for the shift-by-register insns, where the shift
 count might be < 0 or > 32.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.h    |  2 ++
+ target/arm/helper-mve.h |  3 ++
- target/arm/helper-a64.c    | 24 ++++++++++++++++++++++++
+ target/arm/translate.h  |  1 +
- target/arm/translate-a64.c | 15 +++++++++++++++
+ target/arm/t32.decode   | 28 +++++++++++++
-files changed, 41 insertions(+)
+ target/arm/mve_helper.c | 10 +++++
+ target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
+files changed, 132 insertions(+)
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-+++ b/target/arm/helper-a64.h
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
+--- a/target/arm/helper-mve.h
- DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
++++ b/target/arm/helper-mve.h
- DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
-+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
++
-index XXXXXXX..XXXXXXX 100644
++DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
---- a/target/arm/helper-a64.c
++DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+++ b/target/arm/helper-a64.c
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
+index XXXXXXX..XXXXXXX 100644
- ADVSIMD_HALFOP(minnum)
+--- a/target/arm/translate.h
- ADVSIMD_HALFOP(maxnum)
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
-+/* Data processing - scalar floating-point and advanced SIMD */
+ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
-+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-+{
+ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-+    float_status *fpst = fpstp;
++typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
-+
-+    a = float16_squash_input_denormal(a, fpst);
+ /**
-+    b = float16_squash_input_denormal(b, fpst);
+  * arm_tbflags_from_tb:
-+
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-+    if ((float16_is_zero(a) && float16_is_infinity(b)) ||
+index XXXXXXX..XXXXXXX 100644
-+        (float16_is_infinity(a) && float16_is_zero(b))) {
+--- a/target/arm/t32.decode
-+        /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
++++ b/target/arm/t32.decode
-+        return make_float16((1U << 14) |
+@@ -XXX,XX +XXX,XX @@
-+                            ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
+ &mcr             !extern cp opc1 crn crm opc2 rt
-+    }
+ &mcrr            !extern cp opc1 crm rt rt2
-+    return float16_mul(a, b, fpst);
-+}
++&mve_shl_ri      rdalo rdahi shim
 +
-+/* fused multiply-accumulate */
++# rdahi: bits [3:1] from insn, bit 0 is 1
-+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
++# rdalo: bits [3:1] from insn, bit 0 is 0
-+{
++%rdahi_9 9:3 !function=times_2_plus_1
-+    float_status *fpst = fpstp;
++%rdalo_17 17:3 !function=times_2
-+    return float16_muladd(a, b, c, 0, fpst);
++
  # Data-processing (register)
  %imm5_12_6       12:3 6:2
@@ -XXX,XX +XXX,XX @@
  @S_xrr_shi       ....... .... .   rn:4 .... .... .. shty:2 rm:4 \
                   &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
 +@mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
 +                 &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
 +
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
    AND_rrri       1110101 0000 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
  {
 +  # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
 +  # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
 +  # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
 +  # they explicitly call unallocated_encoding() for cases that must UNDEF
 +  # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
 +  # the rest fall through (where ORR_rrri and MOV_rxri will end up
 +  # handling them as r13 and r15 accesses with the same semantics as A32).
 +  [
 +    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +
 +    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +  ]
 +
    MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
    ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
  }
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      mve_advance_vpt(env);
      return rdm;
  }
 +
 +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
      return true;
  }
 +/*
 + * v8.1M MVE wide-shifts
 + */
 +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
 +                          WideShiftImmFn *fn)
 +{
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13) {
 +        /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +
 +    rda = tcg_temp_new_i64();
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    fn(rda, rda, a->shim);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
 +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
 +}
 +
 +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
 +}
 +
 +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
 +}
 +
 +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_sqshll);
 +}
 +
 +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_uqshll);
 +}
 +
 +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_srshr64_i64);
 +}
 +
 +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_urshr64_i64);
 +}
 +
  /*
-  * Floating point comparisons produce an integer result. Softfloat
+  * Multiply and multiply accumulate
-  * routines return float_relation types which we convert to the 0/-1
+  */
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
          case 0x0: /* FMAXNM */
              gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
              break;
 +        case 0x1: /* FMLA */
 +            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
 +            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
 +                                       fpst);
 +            break;
          case 0x2: /* FADD */
              gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
              break;
 +        case 0x3: /* FMULX */
 +            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
 +            break;
          case 0x4: /* FCMEQ */
              gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
              break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
          case 0x8: /* FMINNM */
              gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
              break;
 +        case 0x9: /* FMLS */
 +             /* As usual for ARM, separate negation for fused multiply-add */
 +            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
 +            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
 +            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
 +                                       fpst);
 +            break;
          case 0xa: /* FSUB */
              gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
              break;
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 13/42] target/arm/helper: pass explicit fpst to set_rmode
+[PULL 22/24] target/arm: Implement MVE long shifts by register
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE long shifts by register, which perform shifts on a
+pair of general-purpose registers treated as a 64-bit quantity, with
-As the rounding mode is now split between FP16 and the rest of
+the shift count in another general-purpose register, which might be
-floating point we need to be explicit when tweaking it. Instead of
+either positive or negative.
-passing the CPU env we now pass the appropriate fpst pointer directly.
+Like the long-shifts-by-immediate, these encodings sit in the space
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
 Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
 also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
 we have to move the CSEL pattern into the same decodetree group.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-6-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.h        |  2 +-
+ target/arm/helper-mve.h |  6 +++
- target/arm/helper.c        |  4 ++--
+ target/arm/translate.h  |  1 +
- target/arm/translate-a64.c | 26 +++++++++++++-------------
+ target/arm/t32.decode   | 16 +++++--
- target/arm/translate.c     | 12 ++++++------
+ target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
-files changed, 22 insertions(+), 22 deletions(-)
+ target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
+files changed, 182 insertions(+), 3 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
---- a/target/arm/helper.h
+index XXXXXXX..XXXXXXX 100644
-+++ b/target/arm/helper.h
+--- a/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
++++ b/target/arm/helper-mve.h
- DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
+ DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
--DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env)
-+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
++DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
++DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env)
+ DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
++DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
-index XXXXXXX..XXXXXXX 100644
++DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
---- a/target/arm/helper.c
++DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+++ b/target/arm/helper.c
++DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
- /* Set the current fp rounding mode and return the old one.
+index XXXXXXX..XXXXXXX 100644
-  * The argument is a softfloat float_round_ value.
+--- a/target/arm/translate.h
-  */
++++ b/target/arm/translate.h
--uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
-+uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
+ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
- {
+ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
--    float_status *fp_status = &env->vfp.fp_status;
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
-+    float_status *fp_status = fpstp;
++typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
-     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
+ /**
-     set_float_rounding_mode(rmode, fp_status);
+  * arm_tbflags_from_tb:
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/t32.decode
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/t32.decode
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
+@@ -XXX,XX +XXX,XX @@
-     {
+ &mcrr            !extern cp opc1 crm rt rt2
-         TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+ &mve_shl_ri      rdalo rdahi shim
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++&mve_shl_rr      rdalo rdahi rm
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-         gen_helper_rints(tcg_res, tcg_op, fpst);
+ # rdahi: bits [3:1] from insn, bit 0 is 1
+ # rdalo: bits [3:1] from insn, bit 0 is 0
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+@@ -XXX,XX +XXX,XX @@
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-         tcg_temp_free_i32(tcg_rmode);
+ @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
-         break;
+                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-     }
++@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
++                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
-     {
-         TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+ {
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
-         gen_helper_rintd(tcg_res, tcg_op, fpst);
+     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
+     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
-         tcg_temp_free_i32(tcg_rmode);
++    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
-         break;
++    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
-     }
++    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
-@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
++    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
++    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+   ]
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
++
-         if (is_double) {
++  # v8.1M CSEL and friends
-             TCGv_i64 tcg_double = read_fp_dreg(s, rn);
++  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
+ }
-             tcg_temp_free_i32(tcg_single);
+ {
-         }
+   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
+@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ }
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
-         tcg_temp_free_i32(tcg_rmode);
+-# v8.1M CSEL and friends
-         if (!sf) {
+-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
+-
-     assert(!(is_scalar && is_q));
+ # Data-processing (register-shifted register)
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
+ MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-     tcg_fpstatus = get_fpstatus_ptr(false);
+index XXXXXXX..XXXXXXX 100644
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+--- a/target/arm/mve_helper.c
-     tcg_shift = tcg_const_i32(fracbits);
++++ b/target/arm/mve_helper.c
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-     if (is_double) {
+     return rdm;
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
+ }
-     tcg_temp_free_ptr(tcg_fpstatus);
++uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
-     tcg_temp_free_i32(tcg_shift);
++{
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
++}
-     tcg_temp_free_i32(tcg_rmode);
++
- }
++uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
++{
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
++    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
++}
-     if (is_fcvt) {
++
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+ uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ {
-         tcg_fpstatus = get_fpstatus_ptr(false);
+     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-     } else {
+ {
-         tcg_rmode = NULL;
+     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
-         tcg_fpstatus = NULL;
+ }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
++
-     }
++uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
++{
-     if (is_fcvt) {
++    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++}
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
++
-         tcg_temp_free_i32(tcg_rmode);
++uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-         tcg_temp_free_ptr(tcg_fpstatus);
++{
-     }
++    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
++}
-         return;
++
-     }
++/* Operate on 64-bit values, but saturate at 48 bits */
++static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
--    if (need_fpstatus) {
++                                    bool round, uint32_t *sat)
-+    if (need_fpstatus || need_rmode) {
++{
-         tcg_fpstatus = get_fpstatus_ptr(false);
++    if (shift <= -48) {
-     } else {
++        /* Rounding the sign bit always produces 0. */
-         tcg_fpstatus = NULL;
++        if (round) {
-     }
++            return 0;
-     if (need_rmode) {
++        }
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
++        return src >> 63;
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++    } else if (shift < 0) {
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
++        if (round) {
-     } else {
++            src >>= -shift - 1;
-         tcg_rmode = NULL;
++            return (src >> 1) + (src & 1);
-     }
++        }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
++        return src >> -shift;
-     clear_vec_high(s, is_q, rd);
++    } else if (shift < 48) {
++        int64_t val = src << shift;
-     if (need_rmode) {
++        int64_t extval = sextract64(val, 0, 48);
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++        if (!sat || val == extval) {
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
++            return extval;
-         tcg_temp_free_i32(tcg_rmode);
++        }
-     }
++    } else if (!sat || src == 0) {
-     if (need_fpstatus) {
++        return 0;
 +    }
 +
 +    *sat = 1;
 +    return (1ULL << 47) - (src >= 0);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
 +                                     bool round, uint32_t *sat)
 +{
 +    uint64_t val, extval;
 +
 +    if (shift <= -(48 + round)) {
 +        return 0;
 +    } else if (shift < 0) {
 +        if (round) {
 +            val = src >> (-shift - 1);
 +            val = (val >> 1) + (val & 1);
 +        } else {
 +            val = src >> -shift;
 +        }
 +        extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (shift < 48) {
 +        uint64_t val = src << shift;
 +        uint64_t extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
 +
 +    *sat = 1;
 +    return MAKE_64BIT_MASK(0, 48);
 +}
 +
 +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
+@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-     TCGv_i32 tcg_rmode;
+     return do_mve_shl_ri(s, a, gen_urshr64_i64);
+ }
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++{
++    TCGv_i64 rda;
-     if (dp) {
++    TCGv_i32 rdalo, rdahi;
-         TCGv_i64 tcg_op;
++
-@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-         tcg_temp_free_i32(tcg_res);
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-     }
++        return false;
++    }
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++    if (a->rdahi == 15) {
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
-     tcg_temp_free_i32(tcg_rmode);
++        return false;
++    }
-     tcg_temp_free_ptr(fpst);
++    if (!dc_isar_feature(aa32_mve, s) ||
-@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
-     tcg_shift = tcg_const_i32(0);
++        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
++        a->rm == a->rdahi || a->rm == a->rdalo) {
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
++        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++        unallocated_encoding(s);
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++        return true;
++    }
-     if (dp) {
++
-         TCGv_i64 tcg_double, tcg_res;
++    rda = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
++    rdalo = load_reg(s, a->rdalo);
-         tcg_temp_free_i32(tcg_single);
++    rdahi = load_reg(s, a->rdahi);
-     }
++    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
++
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++    fn(rda, cpu_env, rda, cpu_R[a->rm]);
-     tcg_temp_free_i32(tcg_rmode);
++
++    tcg_gen_extrl_i64_i32(rdalo, rda);
-     tcg_temp_free_i32(tcg_shift);
++    tcg_gen_extrh_i64_i32(rdahi, rda);
-@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
++    store_reg(s, a->rdalo, rdalo);
-                         TCGv_ptr fpst = get_fpstatus_ptr(0);
++    store_reg(s, a->rdahi, rdahi);
-                         TCGv_i32 tcg_rmode;
++    tcg_temp_free_i64(rda);
-                         tcg_rmode = tcg_const_i32(float_round_to_zero);
++
--                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++    return true;
-+                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++}
-                         if (dp) {
++
-                             gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
++static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
-                         } else {
++{
-                             gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
++    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
-                         }
++}
--                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
++
-+                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
-                         tcg_temp_free_i32(tcg_rmode);
++{
-                         tcg_temp_free_ptr(fpst);
++    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
-                         break;
++}
 +
 +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
 +}
 +
 +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
 +}
 +
 +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
 +}
 +
 +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 15/42] arm/translate-a64: handle_3same_64 comment fix
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-We do implement all the opcodes.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-8-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 3 +--
-file changed, 1 insertion(+), 2 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
-     /* Handle 64x64->64 opcodes which are shared between the scalar
-      * and vector 3-same groups. We cover every opcode where size == 3
-      * is valid in either the three-reg-same (integer, not pairwise)
--     * or scalar-three-reg-same groups. (Some opcodes are not yet
--     * implemented.)
-+     * or scalar-three-reg-same groups.
-      */
-     TCGCond cond;
---
-.16.2

-[Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++----------------
-file changed, 133 insertions(+), 75 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-     int datasize, elements;
-     int pass;
-     TCGv_ptr fpst;
-+    bool pairwise = false;
-     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-         unallocated_encoding(s);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-     datasize = is_q ? 128 : 64;
-     elements = datasize / 16;
-+    switch (fpopcode) {
-+    case 0x10: /* FMAXNMP */
-+    case 0x12: /* FADDP */
-+    case 0x16: /* FMAXP */
-+    case 0x18: /* FMINNMP */
-+    case 0x1e: /* FMINP */
-+        pairwise = true;
-+        break;
-+    }
-+
-     fpst = get_fpstatus_ptr(true);
--    for (pass = 0; pass < elements; pass++) {
-+    if (pairwise) {
-+        int maxpass = is_q ? 8 : 4;
-         TCGv_i32 tcg_op1 = tcg_temp_new_i32();
-         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
--        TCGv_i32 tcg_res = tcg_temp_new_i32();
-+        TCGv_i32 tcg_res[8];
--        read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
--        read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
-+        for (pass = 0; pass < maxpass; pass++) {
-+            int passreg = pass < (maxpass / 2) ? rn : rm;
-+            int passelt = (pass << 1) & (maxpass - 1);
--        switch (fpopcode) {
--        case 0x0: /* FMAXNM */
--            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x1: /* FMLA */
--            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
--            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
--                                       fpst);
--            break;
--        case 0x2: /* FADD */
--            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x3: /* FMULX */
--            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x4: /* FCMEQ */
--            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x6: /* FMAX */
--            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x7: /* FRECPS */
--            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x8: /* FMINNM */
--            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x9: /* FMLS */
--             /* As usual for ARM, separate negation for fused multiply-add */
--            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
--            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
--            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
--                                       fpst);
--            break;
--        case 0xa: /* FSUB */
--            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0xe: /* FMIN */
--            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0xf: /* FRSQRTS */
--            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x13: /* FMUL */
--            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x14: /* FCMGE */
--            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x15: /* FACGE */
--            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x17: /* FDIV */
--            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x1a: /* FABD */
--            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
--            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
--            break;
--        case 0x1c: /* FCMGT */
--            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x1d: /* FACGT */
--            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        default:
--            fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
--                    __func__, insn, fpopcode, s->pc);
--            g_assert_not_reached();
-+            read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
-+            read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
-+            tcg_res[pass] = tcg_temp_new_i32();
-+
-+            switch (fpopcode) {
-+            case 0x10: /* FMAXNMP */
-+                gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
-+                                           fpst);
-+                break;
-+            case 0x12: /* FADDP */
-+                gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x16: /* FMAXP */
-+                gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x18: /* FMINNMP */
-+                gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
-+                                           fpst);
-+                break;
-+            case 0x1e: /* FMINP */
-+                gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+        }
-+
-+        for (pass = 0; pass < maxpass; pass++) {
-+            write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
-+            tcg_temp_free_i32(tcg_res[pass]);
-         }
--        write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
--        tcg_temp_free_i32(tcg_res);
-         tcg_temp_free_i32(tcg_op1);
-         tcg_temp_free_i32(tcg_op2);
-+
-+    } else {
-+        for (pass = 0; pass < elements; pass++) {
-+            TCGv_i32 tcg_op1 = tcg_temp_new_i32();
-+            TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-+            TCGv_i32 tcg_res = tcg_temp_new_i32();
-+
-+            read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
-+            read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
-+
-+            switch (fpopcode) {
-+            case 0x0: /* FMAXNM */
-+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x1: /* FMLA */
-+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-+                                           fpst);
-+                break;
-+            case 0x2: /* FADD */
-+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x3: /* FMULX */
-+                gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x4: /* FCMEQ */
-+                gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x6: /* FMAX */
-+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x7: /* FRECPS */
-+                gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x8: /* FMINNM */
-+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x9: /* FMLS */
-+                /* As usual for ARM, separate negation for fused multiply-add */
-+                tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
-+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-+                                           fpst);
-+                break;
-+            case 0xa: /* FSUB */
-+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xe: /* FMIN */
-+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xf: /* FRSQRTS */
-+                gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x13: /* FMUL */
-+                gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x14: /* FCMGE */
-+                gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x15: /* FACGE */
-+                gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x17: /* FDIV */
-+                gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x1a: /* FABD */
-+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
-+                break;
-+            case 0x1c: /* FCMGT */
-+                gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x1d: /* FACGT */
-+                gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            default:
-+                fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
-+                        __func__, insn, fpopcode, s->pc);
-+                g_assert_not_reached();
-+            }
-+
-+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+            tcg_temp_free_i32(tcg_res);
-+            tcg_temp_free_i32(tcg_op1);
-+            tcg_temp_free_i32(tcg_op2);
-+        }
-     }
-     tcg_temp_free_ptr(fpst);
---
-.16.2

-[Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-The helpers use the new re-factored muladd support in SoftFloat for
-the float16 work.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180227143852.11175-15-alex.bennee@linaro.org
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++---------
-file changed, 66 insertions(+), 16 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     int rd = extract32(insn, 0, 5);
-     bool is_long = false;
-     bool is_fp = false;
-+    bool is_fp16 = false;
-     int index;
-     TCGv_ptr fpst;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-         }
-         /* fall through */
-     case 0x9: /* FMUL, FMULX */
--        if (!extract32(size, 1, 1)) {
-+        if (size == 1) {
-             unallocated_encoding(s);
-             return;
-         }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     }
-     if (is_fp) {
--        /* low bit of size indicates single/double */
--        size = extract32(size, 0, 1) ? 3 : 2;
--        if (size == 2) {
-+        /* convert insn encoded size to TCGMemOp size */
-+        switch (size) {
-+        case 2: /* single precision */
-+            size = MO_32;
-             index = h << 1 | l;
--        } else {
-+            rm |= (m << 4);
-+            break;
-+        case 3: /* double precision */
-+            size = MO_64;
-             if (l || !is_q) {
-                 unallocated_encoding(s);
-                 return;
-             }
-             index = h;
-+            rm |= (m << 4);
-+            break;
-+        case 0: /* half precision */
-+            size = MO_16;
-+            index = h << 2 | l << 1 | m;
-+            is_fp16 = true;
-+            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+                break;
-+            }
-+            /* fallthru */
-+        default: /* unallocated */
-+            unallocated_encoding(s);
-+            return;
-         }
--        rm |= (m << 4);
-     } else {
-         switch (size) {
-         case 1:
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     }
-     if (is_fp) {
--        fpst = get_fpstatus_ptr(false);
-+        fpst = get_fpstatus_ptr(is_fp16);
-     } else {
-         fpst = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-                 break;
-             }
-             case 0x5: /* FMLS */
--                /* As usual for ARM, separate negation for fused multiply-add */
--                gen_helper_vfp_negs(tcg_op, tcg_op);
--                /* fall through */
-             case 0x1: /* FMLA */
--                read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
--                gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
-+                read_vec_element_i32(s, tcg_res, rd, pass,
-+                                     is_scalar ? size : MO_32);
-+                switch (size) {
-+                case 1:
-+                    if (opcode == 0x5) {
-+                        /* As usual for ARM, separate negation for fused
-+                         * multiply-add */
-+                        tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
-+                    }
-+                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
-+                                               tcg_res, fpst);
-+                    break;
-+                case 2:
-+                    if (opcode == 0x5) {
-+                        /* As usual for ARM, separate negation for
-+                         * fused multiply-add */
-+                        tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
-+                    }
-+                    gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
-+                                           tcg_res, fpst);
-+                    break;
-+                default:
-+                    g_assert_not_reached();
-+                }
-                 break;
-             case 0x9: /* FMUL, FMULX */
--                if (u) {
--                    gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
--                } else {
--                    gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
-+                switch (size) {
-+                case 1:
-+                    if (u) {
-+                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
-+                                                 fpst);
-+                    } else {
-+                        g_assert_not_reached();
-+                    }
-+                    break;
-+                case 2:
-+                    if (u) {
-+                        gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
-+                    } else {
-+                        gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
-+                    }
-+                    break;
-+                default:
-+                    g_assert_not_reached();
-                 }
-                 break;
-             case 0xc: /* SQDMULH */
---
-.16.2

-[Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed
+[PULL 23/24] target/arm: Implement MVE shifts by immediate
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE shifts by immediate, which perform shifts
+on a single general-purpose register.
-A bunch of the vectorised bitwise operations just operate on larger
-chunks at a time. We can do the same for the new half-precision
+These patterns overlap with the long-shift-by-immediates,
-operations by introducing some TWOHALFOP helpers which work on each
+so we have to rearrange the grouping a little here.
-half of a pair of half-precision operations at once.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Hopefully all this hoop jumping will get simpler once we have
 generically vectorised helpers here.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
+Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.h    | 10 ++++++++++
+ target/arm/helper-mve.h |  3 ++
- target/arm/helper-a64.c    | 46 +++++++++++++++++++++++++++++++++++++++++++++-
+ target/arm/translate.h  |  1 +
- target/arm/translate-a64.c | 26 +++++++++++++++++++++-----
+ target/arm/t32.decode   | 31 ++++++++++++++-----
-files changed, 76 insertions(+), 6 deletions(-)
+ target/arm/mve_helper.c | 10 ++++++
+ target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
+files changed, 104 insertions(+), 9 deletions(-)
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-+++ b/target/arm/helper-a64.h
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
+--- a/target/arm/helper-mve.h
- DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
++++ b/target/arm/helper-mve.h
- DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
+ DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
+ DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
+ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
++
-+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
++DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
++DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
-+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
+index XXXXXXX..XXXXXXX 100644
-+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
+--- a/target/arm/translate.h
-+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
++++ b/target/arm/translate.h
-+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
+@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-index XXXXXXX..XXXXXXX 100644
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
---- a/target/arm/helper-a64.c
+ typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
-+++ b/target/arm/helper-a64.c
++typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
- ADVSIMD_HALFOP(minnum)
+ /**
- ADVSIMD_HALFOP(maxnum)
+  * arm_tbflags_from_tb:
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-+#define ADVSIMD_TWOHALFOP(name)                                         \
+index XXXXXXX..XXXXXXX 100644
-+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
+--- a/target/arm/t32.decode
-+{ \
++++ b/target/arm/t32.decode
-+    float16  a1, a2, b1, b2;                        \
+@@ -XXX,XX +XXX,XX @@
-+    uint32_t r1, r2;                                \
-+    float_status *fpst = fpstp;                     \
+ &mve_shl_ri      rdalo rdahi shim
-+    a1 = extract32(two_a, 0, 16);                   \
+ &mve_shl_rr      rdalo rdahi rm
-+    a2 = extract32(two_a, 16, 16);                  \
++&mve_sh_ri       rda shim
-+    b1 = extract32(two_b, 0, 16);                   \
-+    b2 = extract32(two_b, 16, 16);                  \
+ # rdahi: bits [3:1] from insn, bit 0 is 1
-+    r1 = float16_ ## name(a1, b1, fpst);            \
+ # rdalo: bits [3:1] from insn, bit 0 is 0
-+    r2 = float16_ ## name(a2, b2, fpst);            \
+@@ -XXX,XX +XXX,XX @@
-+    return deposit32(r1, 16, 16, r2);               \
+                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-+}
+ @mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
-+
+                  &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
-+ADVSIMD_TWOHALFOP(add)
++@mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
-+ADVSIMD_TWOHALFOP(sub)
++                 &mve_sh_ri shim=%imm5_12_6
-+ADVSIMD_TWOHALFOP(mul)
-+ADVSIMD_TWOHALFOP(div)
+ {
-+ADVSIMD_TWOHALFOP(min)
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
-+ADVSIMD_TWOHALFOP(max)
+@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
-+ADVSIMD_TWOHALFOP(minnum)
+   # the rest fall through (where ORR_rrri and MOV_rxri will end up
-+ADVSIMD_TWOHALFOP(maxnum)
+   # handling them as r13 and r15 accesses with the same semantics as A32).
-+
+   [
- /* Data processing - scalar floating-point and advanced SIMD */
+-    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
--float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+-    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
-+static float16 float16_mulx(float16 a, float16 b, void *fpstp)
+-    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
- {
++    {
-     float_status *fpst = fpstp;
++      UQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 00 1111  @mve_sh_ri
++      LSLL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
++      UQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
-     return float16_mul(a, b, fpst);
++    }
 -    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 -    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    {
 +      URSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 01 1111  @mve_sh_ri
 +      LSRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +      URSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SRSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 10 1111  @mve_sh_ri
 +      ASRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +      SRSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 11 1111  @mve_sh_ri
 +      SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    }
      LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
      ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
  }
++
-+ADVSIMD_HALFOP(mulx)
++uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-+ADVSIMD_TWOHALFOP(mulx)
++{
-+
++    return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
- /* fused multiply-accumulate */
++}
- float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
++
- {
++uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
++{
-     return float16_muladd(a, b, c, 0, fpst);
++    return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_movi_i32(d, 0);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_sari_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_URSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_extract_i32(d, a, sh - 1, 1);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_shri_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
      return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
  }
-+uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
++static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
-+                                  uint32_t two_c, void *fpstp)
++{
-+{
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-+    float_status *fpst = fpstp;
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-+    float16  a1, a2, b1, b2, c1, c2;
++        return false;
-+    uint32_t r1, r2;
++    }
-+    a1 = extract32(two_a, 0, 16);
++    if (!dc_isar_feature(aa32_mve, s) ||
-+    a2 = extract32(two_a, 16, 16);
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
-+    b1 = extract32(two_b, 0, 16);
++        a->rda == 13 || a->rda == 15) {
-+    b2 = extract32(two_b, 16, 16);
++        /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
-+    c1 = extract32(two_c, 0, 16);
++        unallocated_encoding(s);
-+    c2 = extract32(two_c, 16, 16);
++        return true;
-+    r1 = float16_muladd(a1, b1, c1, 0, fpst);
++    }
-+    r2 = float16_muladd(a2, b2, c2, 0, fpst);
++
-+    return deposit32(r1, 16, 16, r2);
++    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +    fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
 +
 +    return true;
 +}
 +
 +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_urshr32_i32);
 +}
 +
 +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_srshr32_i32);
 +}
 +
 +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_sqshl);
 +}
 +
 +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_uqshl);
 +}
 +
  /*
-  * Floating point comparisons produce an integer result. Softfloat
+  * Multiply and multiply accumulate
-  * routines return float_relation types which we convert to the 0/-1
+  */
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                           * multiply-add */
                          tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
                      }
 -                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
 -                                               tcg_res, fpst);
 +                    if (is_scalar) {
 +                        gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
 +                                                   tcg_res, fpst);
 +                    } else {
 +                        gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
 +                                                    tcg_res, fpst);
 +                    }
                      break;
                  case 2:
                      if (opcode == 0x5) {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                  switch (size) {
                  case 1:
                      if (u) {
 -                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
 -                                                 fpst);
 +                        if (is_scalar) {
 +                            gen_helper_advsimd_mulxh(tcg_res, tcg_op,
 +                                                     tcg_idx, fpst);
 +                        } else {
 +                            gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
 +                                                      tcg_idx, fpst);
 +                        }
                      } else {
 -                        g_assert_not_reached();
 +                        if (is_scalar) {
 +                            gen_helper_advsimd_mulh(tcg_res, tcg_op,
 +                                                    tcg_idx, fpst);
 +                        } else {
 +                            gen_helper_advsimd_mul2h(tcg_res, tcg_op,
 +                                                     tcg_idx, fpst);
 +                        }
                      }
                      break;
                  case 2:
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-I re-use the existing handle_2misc_fcmp_zero handler and tweak it
-slightly to deal with the half-precision case.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++-------------
-file changed, 57 insertions(+), 23 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
-                                    bool is_scalar, bool is_u, bool is_q,
-                                    int size, int rn, int rd)
- {
--    bool is_double = (size == 3);
-+    bool is_double = (size == MO_64);
-     TCGv_ptr fpst;
-     if (!fp_access_check(s)) {
-         return;
-     }
--    fpst = get_fpstatus_ptr(false);
-+    fpst = get_fpstatus_ptr(size == MO_16);
-     if (is_double) {
-         TCGv_i64 tcg_op = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
-         bool swap = false;
-         int pass, maxpasses;
--        switch (opcode) {
--        case 0x2e: /* FCMLT (zero) */
--            swap = true;
--            /* fall through */
--        case 0x2c: /* FCMGT (zero) */
--            genfn = gen_helper_neon_cgt_f32;
--            break;
--        case 0x2d: /* FCMEQ (zero) */
--            genfn = gen_helper_neon_ceq_f32;
--            break;
--        case 0x6d: /* FCMLE (zero) */
--            swap = true;
--            /* fall through */
--        case 0x6c: /* FCMGE (zero) */
--            genfn = gen_helper_neon_cge_f32;
--            break;
--        default:
--            g_assert_not_reached();
-+        if (size == MO_16) {
-+            switch (opcode) {
-+            case 0x2e: /* FCMLT (zero) */
-+                swap = true;
-+                /* fall through */
-+            case 0x2c: /* FCMGT (zero) */
-+                genfn = gen_helper_advsimd_cgt_f16;
-+                break;
-+            case 0x2d: /* FCMEQ (zero) */
-+                genfn = gen_helper_advsimd_ceq_f16;
-+                break;
-+            case 0x6d: /* FCMLE (zero) */
-+                swap = true;
-+                /* fall through */
-+            case 0x6c: /* FCMGE (zero) */
-+                genfn = gen_helper_advsimd_cge_f16;
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+        } else {
-+            switch (opcode) {
-+            case 0x2e: /* FCMLT (zero) */
-+                swap = true;
-+                /* fall through */
-+            case 0x2c: /* FCMGT (zero) */
-+                genfn = gen_helper_neon_cgt_f32;
-+                break;
-+            case 0x2d: /* FCMEQ (zero) */
-+                genfn = gen_helper_neon_ceq_f32;
-+                break;
-+            case 0x6d: /* FCMLE (zero) */
-+                swap = true;
-+                /* fall through */
-+            case 0x6c: /* FCMGE (zero) */
-+                genfn = gen_helper_neon_cge_f32;
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-         }
-         if (is_scalar) {
-             maxpasses = 1;
-         } else {
--            maxpasses = is_q ? 4 : 2;
-+            int vector_size = 8 << is_q;
-+            maxpasses = vector_size >> size;
-         }
-         for (pass = 0; pass < maxpasses; pass++) {
--            read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
-+            read_vec_element_i32(s, tcg_op, rn, pass, size);
-             if (swap) {
-                 genfn(tcg_res, tcg_zero, tcg_op, fpst);
-             } else {
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
-             if (is_scalar) {
-                 write_fp_sreg(s, rd, tcg_res);
-             } else {
--                write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
-+                write_vec_element_i32(s, tcg_res, rd, pass, size);
-             }
-         }
-         tcg_temp_free_i32(tcg_res);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     fpop = deposit32(opcode, 5, 1, a);
-     fpop = deposit32(fpop, 6, 1, u);
-+    rd = extract32(insn, 0, 5);
-+    rn = extract32(insn, 5, 5);
-+
-     switch (fpop) {
-+    break;
-+    case 0x2c: /* FCMGT (zero) */
-+    case 0x2d: /* FCMEQ (zero) */
-+    case 0x2e: /* FCMLT (zero) */
-+    case 0x6c: /* FCMGE (zero) */
-+    case 0x6d: /* FCMLE (zero) */
-+        handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
-+        return;
-     case 0x18: /* FRINTN */
-         need_rmode = true;
-         only_in_vector = true;
---
-.16.2

-[Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-I've re-factored the handle_simd_intfp_conv helper to properly handle
-half-precision as well as call plain conversion helpers when we are
-not doing fixed point conversion.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.h        |  10 ++++
- target/arm/helper.c        |   4 ++
- target/arm/translate-a64.c | 122 ++++++++++++++++++++++++++++++++++-----------
-files changed, 108 insertions(+), 28 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
- DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
- DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
-+DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
- DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
- DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
-+DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
- DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
- DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
-+DEF_HELPER_2(vfp_touih, i32, f16, ptr)
- DEF_HELPER_2(vfp_touis, i32, f32, ptr)
- DEF_HELPER_2(vfp_touid, i32, f64, ptr)
-+DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
- DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
- DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
-+DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
- DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
- DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
-+DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
- DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
- DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
- DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
- DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
- DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
-+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
-+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
- DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
- DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
- DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
-+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
-+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
- DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
- DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
- CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
- CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
-+FLOAT_CONVS(si, h, 16, )
- FLOAT_CONVS(si, s, 32, )
- FLOAT_CONVS(si, d, 64, )
-+FLOAT_CONVS(ui, h, 16, u)
- FLOAT_CONVS(ui, s, 32, u)
- FLOAT_CONVS(ui, d, 64, u)
-@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
- VFP_CONV_FIX(uh, s, 32, 32, uint16)
- VFP_CONV_FIX(ul, s, 32, 32, uint32)
- VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
-+VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
-+VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
- #undef VFP_CONV_FIX
- #undef VFP_CONV_FIX_FLOAT
- #undef VFP_CONV_FLOAT_FIX_ROUND
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
-                                    int elements, int is_signed,
-                                    int fracbits, int size)
- {
--    bool is_double = size == 3 ? true : false;
--    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
--    TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
--    TCGv_i64 tcg_int = tcg_temp_new_i64();
-+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
-+    TCGv_i32 tcg_shift = NULL;
-+
-     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
-     int pass;
--    for (pass = 0; pass < elements; pass++) {
--        read_vec_element(s, tcg_int, rn, pass, mop);
-+    if (fracbits || size == MO_64) {
-+        tcg_shift = tcg_const_i32(fracbits);
-+    }
-+
-+    if (size == MO_64) {
-+        TCGv_i64 tcg_int64 = tcg_temp_new_i64();
-+        TCGv_i64 tcg_double = tcg_temp_new_i64();
-+
-+        for (pass = 0; pass < elements; pass++) {
-+            read_vec_element(s, tcg_int64, rn, pass, mop);
--        if (is_double) {
--            TCGv_i64 tcg_double = tcg_temp_new_i64();
-             if (is_signed) {
--                gen_helper_vfp_sqtod(tcg_double, tcg_int,
-+                gen_helper_vfp_sqtod(tcg_double, tcg_int64,
-                                      tcg_shift, tcg_fpst);
-             } else {
--                gen_helper_vfp_uqtod(tcg_double, tcg_int,
-+                gen_helper_vfp_uqtod(tcg_double, tcg_int64,
-                                      tcg_shift, tcg_fpst);
-             }
-             if (elements == 1) {
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
-             } else {
-                 write_vec_element(s, tcg_double, rd, pass, MO_64);
-             }
--            tcg_temp_free_i64(tcg_double);
--        } else {
--            TCGv_i32 tcg_single = tcg_temp_new_i32();
--            if (is_signed) {
--                gen_helper_vfp_sqtos(tcg_single, tcg_int,
--                                     tcg_shift, tcg_fpst);
--            } else {
--                gen_helper_vfp_uqtos(tcg_single, tcg_int,
--                                     tcg_shift, tcg_fpst);
--            }
--            if (elements == 1) {
--                write_fp_sreg(s, rd, tcg_single);
--            } else {
--                write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
--            }
--            tcg_temp_free_i32(tcg_single);
-         }
-+
-+        tcg_temp_free_i64(tcg_int64);
-+        tcg_temp_free_i64(tcg_double);
-+
-+    } else {
-+        TCGv_i32 tcg_int32 = tcg_temp_new_i32();
-+        TCGv_i32 tcg_float = tcg_temp_new_i32();
-+
-+        for (pass = 0; pass < elements; pass++) {
-+            read_vec_element_i32(s, tcg_int32, rn, pass, mop);
-+
-+            switch (size) {
-+            case MO_32:
-+                if (fracbits) {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sltos(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_ultos(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    }
-+                } else {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
-+                    }
-+                }
-+                break;
-+            case MO_16:
-+                if (fracbits) {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sltoh(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_ultoh(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    }
-+                } else {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
-+                    }
-+                }
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+
-+            if (elements == 1) {
-+                write_fp_sreg(s, rd, tcg_float);
-+            } else {
-+                write_vec_element_i32(s, tcg_float, rd, pass, size);
-+            }
-+        }
-+
-+        tcg_temp_free_i32(tcg_int32);
-+        tcg_temp_free_i32(tcg_float);
-     }
--    tcg_temp_free_i64(tcg_int);
-     tcg_temp_free_ptr(tcg_fpst);
--    tcg_temp_free_i32(tcg_shift);
-+    if (tcg_shift) {
-+        tcg_temp_free_i32(tcg_shift);
-+    }
-     clear_vec_high(s, elements << size == 16, rd);
- }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     rn = extract32(insn, 5, 5);
-     switch (fpop) {
-+    case 0x1d: /* SCVTF */
-+    case 0x5d: /* UCVTF */
-+    {
-+        int elements;
-+
-+        if (is_scalar) {
-+            elements = 1;
-+        } else {
-+            elements = (is_q ? 8 : 4);
-+        }
-+
-+        if (!fp_access_check(s)) {
-+            return;
-+        }
-+        handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
-+        return;
-+    }
-     break;
-     case 0x2c: /* FCMGT (zero) */
-     case 0x2d: /* FCMEQ (zero) */
---
-.16.2

-[Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16
+[PULL 24/24] target/arm: Implement MVE shifts by register
-From: Alex Bennée <alex.bennee@linaro.org>
+Implement the MVE shifts by register, which perform
 shifts on a single general-purpose register.
-It looks like the ARM ARM has simplified the pseudo code for the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-calculation which is done on a fixed point 9 bit integer maths. So
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-while adding f16 we can also clean this up to be a little less heavy
+Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
-on the floating point and just return the fractional part and leave
+---
-the calle's to do the final packing of the result.
+ target/arm/helper-mve.h |  2 ++
  target/arm/translate.h  |  1 +
  target/arm/t32.decode   | 18 ++++++++++++++----
  target/arm/mve_helper.c | 10 ++++++++++
  target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 files changed, 57 insertions(+), 4 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.h |   1 +
  target/arm/helper.c | 226 +++++++++++++++++++++++++++++-----------------------
 files changed, 129 insertions(+), 98 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/helper-mve.h
-+++ b/target/arm/helper.h
++++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_3(recps_f32, f32, f32, f32, env)
+ DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
- DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
+ DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
-+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
++DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
- DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
++DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
- DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
  DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/translate.h
-+++ b/target/arm/helper.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-  * int->float conversions at run-time.  */
+ typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
- #define float64_256 make_float64(0x4070000000000000LL)
+ typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
- #define float64_512 make_float64(0x4080000000000000LL)
+ typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
-+#define float16_maxnorm make_float16(0x7bff)
++typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
- #define float32_maxnorm make_float32(0x7f7fffff)
- #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
+ /**
+  * arm_tbflags_from_tb:
- /* Reciprocal functions
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-  *
+index XXXXXXX..XXXXXXX 100644
-  * The algorithm that must be used to calculate the estimate
+--- a/target/arm/t32.decode
-- * is specified by the ARM ARM, see FPRecipEstimate()
++++ b/target/arm/t32.decode
-+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
+@@ -XXX,XX +XXX,XX @@
-  */
+ &mve_shl_ri      rdalo rdahi shim
+ &mve_shl_rr      rdalo rdahi rm
--static float64 recip_estimate(float64 a, float_status *real_fp_status)
+ &mve_sh_ri       rda shim
-+/* See RecipEstimate()
++&mve_sh_rr       rda rm
-+ *
-+ * input is a 9 bit fixed point number
+ # rdahi: bits [3:1] from insn, bit 0 is 1
-+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
+ # rdalo: bits [3:1] from insn, bit 0 is 0
-+ * result range 256 .. 511 for a number from 1.0 to 511/256.
+@@ -XXX,XX +XXX,XX @@
-+ */
+                  &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
-+
+ @mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
-+static int recip_estimate(int input)
+                  &mve_sh_ri shim=%imm5_12_6
 +@mve_sh_rr       ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
  {
--    /* These calculations mustn't set any fp exception flags,
+   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
--     * so we use a local copy of the fp_status.
+@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
--     */
+       SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 -    float_status dummy_status = *real_fp_status;
 -    float_status *s = &dummy_status;
 -    /* q = (int)(a * 512.0) */
 -    float64 q = float64_mul(float64_512, a, s);
 -    int64_t q_int = float64_to_int64_round_to_zero(q, s);
 -
 -    /* r = 1.0 / (((double)q + 0.5) / 512.0) */
 -    q = int64_to_float64(q_int, s);
 -    q = float64_add(q, float64_half, s);
 -    q = float64_div(q, float64_512, s);
 -    q = float64_div(float64_one, q, s);
 -
 -    /* s = (int)(256.0 * r + 0.5) */
 -    q = float64_mul(q, float64_256, s);
 -    q = float64_add(q, float64_half, s);
 -    q_int = float64_to_int64_round_to_zero(q, s);
 -
 -    /* return (double)s / 256.0 */
 -    return float64_div(int64_to_float64(q_int, s), float64_256, s);
 +    int a, b, r;
 +    assert(256 <= input && input < 512);
 +    a = (input * 2) + 1;
 +    b = (1 << 19) / a;
 +    r = (b + 1) >> 1;
 +    assert(256 <= r && r < 512);
 +    return r;
  }
 -/* Common wrapper to call recip_estimate */
 -static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
 -{
 -    uint64_t val64 = float64_val(num);
 -    uint64_t frac = extract64(val64, 0, 52);
 -    int64_t exp = extract64(val64, 52, 11);
 -    uint64_t sbit;
 -    float64 scaled, estimate;
 +/*
 + * Common wrapper to call recip_estimate
 + *
 + * The parameters are exponent and 64 bit fraction (without implicit
 + * bit) where the binary point is nominally at bit 52. Returns a
 + * float64 which can then be rounded to the appropriate size by the
 + * callee.
 + */
 -    /* Generate the scaled number for the estimate function */
 -    if (exp == 0) {
 +static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
 +{
 +    uint32_t scaled, estimate;
 +    uint64_t result_frac;
 +    int result_exp;
 +
 +    /* Handle sub-normals */
 +    if (*exp == 0) {
          if (extract64(frac, 51, 1) == 0) {
 -            exp = -1;
 -            frac = extract64(frac, 0, 50) << 2;
 +            *exp = -1;
 +            frac <<= 2;
          } else {
 -            frac = extract64(frac, 0, 51) << 1;
 +            frac <<= 1;
          }
      }
--    /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
+-    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
--    scaled = make_float64((0x3feULL << 52)
+-    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
--                          | extract64(frac, 44, 8) << 44);
+-    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
-+    /* scaled = UInt('1':fraction<51:44>) */
+-    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
-+    scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
++    {
-+    estimate = recip_estimate(scaled);
++      UQRSHL_rr    1110101 0010 1 ....  ....  1111 0000 1101  @mve_sh_rr
++      LSLL_rr      1110101 0010 1 ... 0 .... ... 1 0000 1101  @mve_shl_rr
--    estimate = recip_estimate(scaled, fpst);
++      UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101  @mve_shl_rr
 -
 -    /* Build new result */
 -    val64 = float64_val(estimate);
 -    sbit = 0x8000000000000000ULL & val64;
 -    exp = off - exp;
 -    frac = extract64(val64, 0, 52);
 -
 -    if (exp == 0) {
 -        frac = 1ULL << 51 | extract64(frac, 1, 51);
 -    } else if (exp == -1) {
 -        frac = 1ULL << 50 | extract64(frac, 2, 50);
 -        exp = 0;
 +    result_exp = exp_off - *exp;
 +    result_frac = deposit64(0, 44, 8, estimate);
 +    if (result_exp == 0) {
 +        result_frac = deposit64(result_frac >> 1, 51, 1, 1);
 +    } else if (result_exp == -1) {
 +        result_frac = deposit64(result_frac >> 2, 50, 2, 1);
 +        result_exp = 0;
      }
 -    return make_float64(sbit | (exp << 52) | frac);
 +    *exp = result_exp;
 +
 +    return result_frac;
  }
  static bool round_to_inf(float_status *fpst, bool sign_bit)
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
      g_assert_not_reached();
  }
 +float16 HELPER(recpe_f16)(float16 input, void *fpstp)
 +{
 +    float_status *fpst = fpstp;
 +    float16 f16 = float16_squash_input_denormal(input, fpst);
 +    uint32_t f16_val = float16_val(f16);
 +    uint32_t f16_sign = float16_is_neg(f16);
 +    int f16_exp = extract32(f16_val, 10, 5);
 +    uint32_t f16_frac = extract32(f16_val, 0, 10);
 +    uint64_t f64_frac;
 +
 +    if (float16_is_any_nan(f16)) {
 +        float16 nan = f16;
 +        if (float16_is_signaling_nan(f16, fpst)) {
 +            float_raise(float_flag_invalid, fpst);
 +            nan = float16_maybe_silence_nan(f16, fpst);
 +        }
 +        if (fpst->default_nan_mode) {
 +            nan =  float16_default_nan(fpst);
 +        }
 +        return nan;
 +    } else if (float16_is_infinity(f16)) {
 +        return float16_set_sign(float16_zero, float16_is_neg(f16));
 +    } else if (float16_is_zero(f16)) {
 +        float_raise(float_flag_divbyzero, fpst);
 +        return float16_set_sign(float16_infinity, float16_is_neg(f16));
 +    } else if (float16_abs(f16) < (1 << 8)) {
 +        /* Abs(value) < 2.0^-16 */
 +        float_raise(float_flag_overflow | float_flag_inexact, fpst);
 +        if (round_to_inf(fpst, f16_sign)) {
 +            return float16_set_sign(float16_infinity, f16_sign);
 +        } else {
 +            return float16_set_sign(float16_maxnorm, f16_sign);
 +        }
 +    } else if (f16_exp >= 29 && fpst->flush_to_zero) {
 +        float_raise(float_flag_underflow, fpst);
 +        return float16_set_sign(float16_zero, float16_is_neg(f16));
 +    }
 +
-+    f64_frac = call_recip_estimate(&f16_exp, 29,
++    {
-+                                   ((uint64_t) f16_frac) << (52 - 10));
++      SQRSHR_rr    1110101 0010 1 ....  ....  1111 0010 1101  @mve_sh_rr
 +      ASRL_rr      1110101 0010 1 ... 0 .... ... 1 0010 1101  @mve_shl_rr
 +      SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101  @mve_shl_rr
 +    }
 +
-+    /* result = sign : result_exp<4:0> : fraction<51:42> */
+     UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
-+    f16_val = deposit32(0, 15, 1, f16_sign);
+     SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
-+    f16_val = deposit32(f16_val, 10, 5, f16_exp);
+   ]
-+    f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
+diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-+    return make_float16(f16_val);
+index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
  {
      return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
  }
 +
 +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
 +}
 +
- float32 HELPER(recpe_f32)(float32 input, void *fpstp)
++uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
- {
++{
-     float_status *fpst = fpstp;
++    return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
-     float32 f32 = float32_squash_input_denormal(input, fpst);
++}
-     uint32_t f32_val = float32_val(f32);
+diff --git a/target/arm/translate.c b/target/arm/translate.c
--    uint32_t f32_sbit = 0x80000000ULL & f32_val;
+index XXXXXXX..XXXXXXX 100644
--    int32_t f32_exp = extract32(f32_val, 23, 8);
+--- a/target/arm/translate.c
-+    bool f32_sign = float32_is_neg(f32);
++++ b/target/arm/translate.c
-+    int f32_exp = extract32(f32_val, 23, 8);
+@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
-     uint32_t f32_frac = extract32(f32_val, 0, 23);
+     return do_mve_sh_ri(s, a, gen_mve_uqshl);
 -    float64 f64, r64;
 -    uint64_t r64_val;
 -    int64_t r64_exp;
 -    uint64_t r64_frac;
 +    uint64_t f64_frac;
      if (float32_is_any_nan(f32)) {
          float32 nan = f32;
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
      } else if (float32_is_zero(f32)) {
          float_raise(float_flag_divbyzero, fpst);
          return float32_set_sign(float32_infinity, float32_is_neg(f32));
 -    } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
 +    } else if (float32_abs(f32) < (1ULL << 21)) {
          /* Abs(value) < 2.0^-128 */
          float_raise(float_flag_overflow | float_flag_inexact, fpst);
 -        if (round_to_inf(fpst, f32_sbit)) {
 -            return float32_set_sign(float32_infinity, float32_is_neg(f32));
 +        if (round_to_inf(fpst, f32_sign)) {
 +            return float32_set_sign(float32_infinity, f32_sign);
          } else {
 -            return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
 +            return float32_set_sign(float32_maxnorm, f32_sign);
          }
      } else if (f32_exp >= 253 && fpst->flush_to_zero) {
          float_raise(float_flag_underflow, fpst);
          return float32_set_sign(float32_zero, float32_is_neg(f32));
      }
 +    f64_frac = call_recip_estimate(&f32_exp, 253,
 +                                   ((uint64_t) f32_frac) << (52 - 23));
 -    f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
 -    r64 = call_recip_estimate(f64, 253, fpst);
 -    r64_val = float64_val(r64);
 -    r64_exp = extract64(r64_val, 52, 11);
 -    r64_frac = extract64(r64_val, 0, 52);
 -
 -    /* result = sign : result_exp<7:0> : fraction<51:29>; */
 -    return make_float32(f32_sbit |
 -                        (r64_exp & 0xff) << 23 |
 -                        extract64(r64_frac, 29, 24));
 +    /* result = sign : result_exp<7:0> : fraction<51:29> */
 +    f32_val = deposit32(0, 31, 1, f32_sign);
 +    f32_val = deposit32(f32_val, 23, 8, f32_exp);
 +    f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
 +    return make_float32(f32_val);
  }
- float64 HELPER(recpe_f64)(float64 input, void *fpstp)
++static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
++{
-     float_status *fpst = fpstp;
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-     float64 f64 = float64_squash_input_denormal(input, fpst);
++        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-     uint64_t f64_val = float64_val(f64);
++        return false;
--    uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
++    }
--    int64_t f64_exp = extract64(f64_val, 52, 11);
++    if (!dc_isar_feature(aa32_mve, s) ||
--    float64 r64;
++        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
--    uint64_t r64_val;
++        a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
--    int64_t r64_exp;
++        a->rm == a->rda) {
--    uint64_t r64_frac;
++        /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
-+    bool f64_sign = float64_is_neg(f64);
++        unallocated_encoding(s);
-+    int f64_exp = extract64(f64_val, 52, 11);
++        return true;
-+    uint64_t f64_frac = extract64(f64_val, 0, 52);
++    }
++
-     /* Deal with any special cases */
++    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
-     if (float64_is_any_nan(f64)) {
++    fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
++    return true;
-     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
++}
-         /* Abs(value) < 2.0^-1024 */
++
-         float_raise(float_flag_overflow | float_flag_inexact, fpst);
++static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
--        if (round_to_inf(fpst, f64_sbit)) {
++{
--            return float64_set_sign(float64_infinity, float64_is_neg(f64));
++    return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
-+        if (round_to_inf(fpst, f64_sign)) {
++}
-+            return float64_set_sign(float64_infinity, f64_sign);
++
-         } else {
++static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
--            return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
++{
-+            return float64_set_sign(float64_maxnorm, f64_sign);
++    return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
-         }
++}
-     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
++
-         float_raise(float_flag_underflow, fpst);
+ /*
-         return float64_set_sign(float64_zero, float64_is_neg(f64));
+  * Multiply and multiply accumulate
-     }
+  */
 -    r64 = call_recip_estimate(f64, 2045, fpst);
 -    r64_val = float64_val(r64);
 -    r64_exp = extract64(r64_val, 52, 11);
 -    r64_frac = extract64(r64_val, 0, 52);
 +    f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
 -    /* result = sign : result_exp<10:0> : fraction<51:0> */
 -    return make_float64(f64_sbit |
 -                        ((r64_exp & 0x7ff) << 52) |
 -                        r64_frac);
 +    /* result = sign : result_exp<10:0> : fraction<51:0>; */
 +    f64_val = deposit64(0, 63, 1, f64_sign);
 +    f64_val = deposit64(f64_val, 52, 11, f64_exp);
 +    f64_val = deposit64(f64_val, 0, 52, f64_frac);
 +    return make_float64(f64_val);
  }
  /* The algorithm that must be used to calculate the estimate
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
  uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
  {
 -    float_status *s = fpstp;
 -    float64 f64;
 +    /* float_status *s = fpstp; */
 +    int input, estimate;
      if ((a & 0x80000000) == 0) {
          return 0xffffffff;
      }
 -    f64 = make_float64((0x3feULL << 52)
 -                       | ((int64_t)(a & 0x7fffffff) << 21));
 +    input = extract32(a, 23, 9);
 +    estimate = recip_estimate(input);
 -    f64 = recip_estimate(f64, s);
 -
 -    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
 +    return deposit32(0, (32 - 9), 9, estimate);
  }
  uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Now we have added f16 during the re-factoring we can simply call the
-helper.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 8 ++++++++
-file changed, 8 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     case 0x6d: /* FCMLE (zero) */
-         handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
-         return;
-+    case 0x3d: /* FRECPE */
-+        break;
-     case 0x18: /* FRINTN */
-         need_rmode = true;
-         only_in_vector = true;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         case 0x3b: /* FCVTZS */
-             gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
-             break;
-+        case 0x3d: /* FRECPE */
-+            gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-         case 0x5a: /* FCVTNU */
-         case 0x5b: /* FCVTMU */
-         case 0x5c: /* FCVTAU */
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             case 0x3b: /* FCVTZS */
-                 gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
-                 break;
-+            case 0x3d: /* FRECPE */
-+                gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-             case 0x5a: /* FCVTNU */
-             case 0x5b: /* FCVTMU */
-             case 0x5c: /* FCVTAU */
---
-.16.2

-[Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 7 +++++++
-file changed, 7 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     case 0x6f: /* FNEG */
-         need_fpst = false;
-         break;
-+    case 0x7d: /* FRSQRTE */
-     case 0x7f: /* FSQRT (vector) */
-         break;
-     default:
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         case 0x6f: /* FNEG */
-             tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-             break;
-+        case 0x7d: /* FRSQRTE */
-+            gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-         default:
-             g_assert_not_reached();
-         }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             case 0x6f: /* FNEG */
-                 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-                 break;
-+            case 0x7d: /* FRSQRTE */
-+                gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-             case 0x7f: /* FSQRT */
-                 gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
-                 break;
---
-.16.2

-[Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Only one half-precision instruction has been added to this group.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-29-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 35 +++++++++++++++++++++++++----------
-file changed, 25 insertions(+), 10 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
-  *   MVNI - move inverted (shifted) imm into register
-  *   ORR  - bitwise OR of (shifted) imm with register
-  *   BIC  - bitwise clear of (shifted) imm with register
-+ * With ARMv8.2 we also have:
-+ *   FMOV half-precision
-  */
- static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
- {
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-     uint64_t imm = 0;
-     if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
--        unallocated_encoding(s);
--        return;
-+        /* Check for FMOV (vector, immediate) - half-precision */
-+        if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
-+            unallocated_encoding(s);
-+            return;
-+        }
-     }
-     if (!fp_access_check(s)) {
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-                     imm |= 0x4000000000000000ULL;
-                 }
-             } else {
--                imm = (abcdefgh & 0x3f) << 19;
--                if (abcdefgh & 0x80) {
--                    imm |= 0x80000000;
--                }
--                if (abcdefgh & 0x40) {
--                    imm |= 0x3e000000;
-+                if (o2) {
-+                    /* FMOV (vector, immediate) - half-precision */
-+                    imm = vfp_expand_imm(MO_16, abcdefgh);
-+                    /* now duplicate across the lanes */
-+                    imm = bitfield_replicate(imm, 16);
-                 } else {
--                    imm |= 0x40000000;
-+                    imm = (abcdefgh & 0x3f) << 19;
-+                    if (abcdefgh & 0x80) {
-+                        imm |= 0x80000000;
-+                    }
-+                    if (abcdefgh & 0x40) {
-+                        imm |= 0x3e000000;
-+                    } else {
-+                        imm |= 0x40000000;
-+                    }
-+                    imm |= (imm << 32);
-                 }
--                imm |= (imm << 32);
-             }
-         }
-         break;
-+    default:
-+        fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
-+        g_assert_not_reached();
-     }
-     if (cmode_3_1 != 7 && is_neg) {
---
-.16.2

-[Qemu-devel] [PULL 37/42] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-I only needed to do a little light re-factoring to support the
-half-precision helpers.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++---------------
-file changed, 54 insertions(+), 26 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
-     case 0xf: /* FMAXP */
-     case 0x2c: /* FMINNMP */
-     case 0x2f: /* FMINP */
--        /* FP op, size[0] is 32 or 64 bit */
-+        /* FP op, size[0] is 32 or 64 bit*/
-         if (!u) {
--            unallocated_encoding(s);
--            return;
-+            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+                unallocated_encoding(s);
-+                return;
-+            } else {
-+                size = MO_16;
-+            }
-+        } else {
-+            size = extract32(size, 0, 1) ? MO_64 : MO_32;
-         }
-+
-         if (!fp_access_check(s)) {
-             return;
-         }
--        size = extract32(size, 0, 1) ? 3 : 2;
--        fpst = get_fpstatus_ptr(false);
-+        fpst = get_fpstatus_ptr(size == MO_16);
-         break;
-     default:
-         unallocated_encoding(s);
-         return;
-     }
--    if (size == 3) {
-+    if (size == MO_64) {
-         TCGv_i64 tcg_op1 = tcg_temp_new_i64();
-         TCGv_i64 tcg_op2 = tcg_temp_new_i64();
-         TCGv_i64 tcg_res = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
-         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-         TCGv_i32 tcg_res = tcg_temp_new_i32();
--        read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
--        read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
-+        read_vec_element_i32(s, tcg_op1, rn, 0, size);
-+        read_vec_element_i32(s, tcg_op2, rn, 1, size);
--        switch (opcode) {
--        case 0xc: /* FMAXNMP */
--            gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0xd: /* FADDP */
--            gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0xf: /* FMAXP */
--            gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x2c: /* FMINNMP */
--            gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x2f: /* FMINP */
--            gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        default:
--            g_assert_not_reached();
-+        if (size == MO_16) {
-+            switch (opcode) {
-+            case 0xc: /* FMAXNMP */
-+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xd: /* FADDP */
-+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xf: /* FMAXP */
-+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x2c: /* FMINNMP */
-+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x2f: /* FMINP */
-+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+        } else {
-+            switch (opcode) {
-+            case 0xc: /* FMAXNMP */
-+                gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xd: /* FADDP */
-+                gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xf: /* FMAXP */
-+                gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x2c: /* FMINNMP */
-+                gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x2f: /* FMINP */
-+                gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-         }
-         write_fp_sreg(s, rd, tcg_res);
---
-.16.2

Arm queue -- I have more stuff pending but I prefer to push
this first lot out and keep the pull below 50 patches.
Most of this is Alex's FP16 support work.

-- PMM

The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:

Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301

for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:

MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)

----------------------------------------------------------------
target-arm queue:
 * update MAINTAINERS for Alistair's new email address
 * add Arm v8.2 FP16 arithmetic extension for linux-user
 * implement display connector emulation for vexpress board
 * xilinx_spips: Enable only two slaves when reading/writing with stripe
 * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
 * hw: register: Run post_write hook on reset

----------------------------------------------------------------
Alex Bennée (31):
      include/exec/helper-head.h: support f16 in helper calls
      target/arm/cpu64: introduce ARM_V8_FP16 feature bit
      target/arm/cpu.h: update comment for half-precision values
      target/arm/cpu.h: add additional float_status flags
      target/arm/helper: pass explicit fpst to set_rmode
      arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
      arm/translate-a64: handle_3same_64 comment fix
      arm/translate-a64: initial decode for simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
      arm/translate-a64: add FP16 x2 ops for simd_indexed
      arm/translate-a64: initial decode for simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
      arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
      arm/helper.c: re-factor recpe and add recepe_f16
      arm/translate-a64: add FP16 FRECPE
      arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
      arm/helper.c: re-factor rsqrte and add rsqrte_f16
      arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FMOV to simd_mod_imm
      arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
      arm/translate-a64: implement simd_scalar_three_reg_same_fp16
      arm/translate-a64: add all single op FP16 to handle_fp_1src_half

Alistair Francis (2):
      hw: register: Run post_write hook on reset
      MAINTAINERS: Update my email address

Corey Minyard (2):
      i2c: Fix some brace style issues
      i2c: Move the bus class to i2c.h

Francisco Iglesias (2):
      xilinx_spips: Enable only two slaves when reading/writing with stripe
      xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands

Linus Walleij (3):
      hw/i2c-ddc: Do not fail writes
      hw/sii9022: Add support for Silicon Image SII9022
      arm/vexpress: Add proper display connector emulation

Peter Maydell (2):
      target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
      linux-user: Report AArch64 FP16 support via hwcap bits

From: Alistair Francis <alistair.francis@xilinx.com>

Ensure that the post write hook is called during reset. This allows us
to rely on the post write functions instead of having to call them from
the reset() function.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/register.h | 6 +++---
 hw/core/register.c    | 8 ++++++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/include/hw/register.h b/include/hw/register.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -XXX,XX +XXX,XX @@ typedef struct RegisterInfoArray RegisterInfoArray;
  * immediately before the actual write. The returned value is what is written,
  * giving the handler a chance to modify the written value.
  * @post_write: Post write callback. Passed the written value. Most write side
- * effects should be implemented here.
+ * effects should be implemented here. This is called during device reset.
  *
  * @post_read: Post read callback. Passes the value that is about to be returned
  * for a read. The return value from this function is what is ultimately read,
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
                        bool debug);
 
 /**
- * reset a register
- * @reg: register to reset
+ * Resets a register. This will also call the post_write hook if it exists.
+ * @reg: The register to reset.
  */
 
 void register_reset(RegisterInfo *reg);
diff --git a/hw/core/register.c b/hw/core/register.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
 
 void register_reset(RegisterInfo *reg)
 {
+    const RegisterAccessInfo *ac;
+
     g_assert(reg);
 
     if (!reg->data || !reg->access) {
         return;
     }
 
+    ac = reg->access;
+
     register_write_val(reg, reg->access->reset);
+
+    if (ac->post_write) {
+        ac->post_write(reg, reg->access->reset);
+    }
 }
 
 void register_init(RegisterInfo *reg)
-- 
2.16.2

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
chip selects are enabled (e.g reading/writing with stripe).

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
 {
     int i;
 
-    for (i = 0; i < s->num_cs; i++) {
+    for (i = 0; i < s->num_cs * s->num_busses; i++) {
         bool old_state = s->cs_lines_state[i];
         bool new_state = field & (1 << i);
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
         }
         qemu_set_irq(s->cs_lines[i], !new_state);
     }
-    if (!(field & ((1 << s->num_cs) - 1))) {
+    if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
         s->snoop_state = SNOOP_CHECKING;
         s->cmd_dummies = 0;
         s->link_state = 1;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
 {
     if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
         int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
-        xilinx_spips_update_cs(XILINX_SPIPS(s), field);
+        bool upper_cs_sel = field & (1 << 1);
+        bool lower_cs_sel = field & 1;
+        bool bus0_enabled;
+        bool bus1_enabled;
+        uint8_t buses;
+        int cs = 0;
+
+        buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
+        bus0_enabled = buses & 1;
+        bus1_enabled = buses & (1 << 1);
+
+        if (bus0_enabled && bus1_enabled) {
+            if (lower_cs_sel) {
+                cs |= 1;
+            }
+            if (upper_cs_sel) {
+                cs |= 1 << 3;
+            }
+        } else if (bus0_enabled) {
+            if (lower_cs_sel) {
+                cs |= 1;
+            }
+            if (upper_cs_sel) {
+                cs |= 1 << 1;
+            }
+        } else if (bus1_enabled) {
+            if (lower_cs_sel) {
+                cs |= 1 << 2;
+            }
+            if (upper_cs_sel) {
+                cs |= 1 << 3;
+            }
+        }
+        xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
     if (num_effective_busses(s) == 2) {
         /* Single bit chip-select for qspi */
         field &= 0x1;
-        field |= field << 1;
+        field |= field << 3;
     /* Dual stack U-Page */
     } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
                s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
-- 
2.16.2

From: Corey Minyard <cminyard@mvista.com>

Signed-off-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-2-linus.walleij@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/i2c.h | 6 ++----
 hw/i2c/core.c        | 3 +--
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlave I2CSlave;
 #define I2C_SLAVE_GET_CLASS(obj) \
      OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
 
-typedef struct I2CSlaveClass
-{
+typedef struct I2CSlaveClass {
     DeviceClass parent_class;
 
     /* Callbacks provided by the device.  */
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlaveClass
     int (*event)(I2CSlave *s, enum i2c_event event);
 } I2CSlaveClass;
 
-struct I2CSlave
-{
+struct I2CSlave {
     DeviceState qdev;
 
     /* Remaining fields for internal use by the I2C code.  */
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -XXX,XX +XXX,XX @@ struct I2CNode {
 
 #define I2C_BROADCAST 0x00
 
-struct I2CBus
-{
+struct I2CBus {
     BusState qbus;
     QLIST_HEAD(, I2CNode) current_devs;
     uint8_t saved_address;
-- 
2.16.2

From: Corey Minyard <cminyard@mvista.com>

Some devices need access to it.

Signed-off-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-3-linus.walleij@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/i2c.h | 17 +++++++++++++++++
 hw/i2c/core.c        | 17 -----------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -XXX,XX +XXX,XX @@ struct I2CSlave {
     uint8_t address;
 };
 
+#define TYPE_I2C_BUS "i2c-bus"
+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
+
+typedef struct I2CNode I2CNode;
+
+struct I2CNode {
+    I2CSlave *elt;
+    QLIST_ENTRY(I2CNode) next;
+};
+
+struct I2CBus {
+    BusState qbus;
+    QLIST_HEAD(, I2CNode) current_devs;
+    uint8_t saved_address;
+    bool broadcast;
+};
+
 I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
 void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
 int i2c_bus_busy(I2CBus *bus);
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/i2c/i2c.h"
 
-typedef struct I2CNode I2CNode;
-
-struct I2CNode {
-    I2CSlave *elt;
-    QLIST_ENTRY(I2CNode) next;
-};
-
 #define I2C_BROADCAST 0x00
 
-struct I2CBus {
-    BusState qbus;
-    QLIST_HEAD(, I2CNode) current_devs;
-    uint8_t saved_address;
-    bool broadcast;
-};
-
 static Property i2c_props[] = {
     DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-#define TYPE_I2C_BUS "i2c-bus"
-#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
-
 static const TypeInfo i2c_bus_info = {
     .name = TYPE_I2C_BUS,
     .parent = TYPE_BUS,
-- 
2.16.2

From: Linus Walleij <linus.walleij@linaro.org>

The tx function of the DDC I2C slave emulation was returning 1
on all writes resulting in NACK in the I2C bus. Changing it to
0 makes the DDC I2C work fine with bit-banged I2C such as the
versatile I2C.

I guess it was not affecting whatever I2C controller this was
used with until now, but with the Versatile I2C it surely
does not work.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-4-linus.walleij@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/i2c-ddc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/i2c-ddc.c
+++ b/hw/i2c/i2c-ddc.c
@@ -XXX,XX +XXX,XX @@ static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
         s->reg = data;
         s->firstbyte = false;
         DPRINTF("[EDID] Written new pointer: %u\n", data);
-        return 1;
+        return 0;
     }
 
     /* Ignore all writes */
     s->reg++;
-    return 1;
+    return 0;
 }
 
 static void i2c_ddc_init(Object *obj)
-- 
2.16.2

From: Linus Walleij <linus.walleij@linaro.org>

This adds support for emulating the Silicon Image SII9022 DVI/HDMI
bridge. It's not very clever right now, it just acknowledges
the switch into DDC I2C mode and back. Combining this with the
existing DDC I2C emulation gives the right behavior on the Versatile
Express emulation passing through the QEMU EDID to the emulated
platform.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/display/Makefile.objs |   1 +
 hw/display/sii9022.c     | 191 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/display/trace-events  |   5 ++
 3 files changed, 197 insertions(+)
 create mode 100644 hw/display/sii9022.c

diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
 common-obj-$(CONFIG_G364FB) += g364fb.o
 common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
 common-obj-$(CONFIG_PL110) += pl110.o
+common-obj-$(CONFIG_SII9022) += sii9022.o
 common-obj-$(CONFIG_SSD0303) += ssd0303.o
 common-obj-$(CONFIG_SSD0323) += ssd0323.o
 common-obj-$(CONFIG_XEN) += xenfb.o
diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/display/sii9022.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Silicon Image SiI9022
+ *
+ * This is a pretty hollow emulation: all we do is acknowledge that we
+ * exist (chip ID) and confirm that we get switched over into DDC mode
+ * so the emulated host can proceed to read out EDID data. All subsequent
+ * set-up of connectors etc will be acknowledged and ignored.
+ *
+ * Copyright (C) 2018 Linus Walleij
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/i2c-ddc.h"
+#include "trace.h"
+
+#define SII9022_SYS_CTRL_DATA 0x1a
+#define SII9022_SYS_CTRL_PWR_DWN 0x10
+#define SII9022_SYS_CTRL_AV_MUTE 0x08
+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
+#define SII9022_REG_CHIPID 0x1b
+#define SII9022_INT_ENABLE 0x3c
+#define SII9022_INT_STATUS 0x3d
+#define SII9022_INT_STATUS_HOTPLUG 0x01;
+#define SII9022_INT_STATUS_PLUGGED 0x04;
+
+#define TYPE_SII9022 "sii9022"
+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
+
+typedef struct sii9022_state {
+    I2CSlave parent_obj;
+    uint8_t ptr;
+    bool addr_byte;
+    bool ddc_req;
+    bool ddc_skip_finish;
+    bool ddc;
+} sii9022_state;
+
+static const VMStateDescription vmstate_sii9022 = {
+    .name = "sii9022",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
+        VMSTATE_UINT8(ptr, sii9022_state),
+        VMSTATE_BOOL(addr_byte, sii9022_state),
+        VMSTATE_BOOL(ddc_req, sii9022_state),
+        VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
+        VMSTATE_BOOL(ddc, sii9022_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
+{
+    sii9022_state *s = SII9022(i2c);
+
+    switch (event) {
+    case I2C_START_SEND:
+        s->addr_byte = true;
+        break;
+    case I2C_START_RECV:
+        break;
+    case I2C_FINISH:
+        break;
+    case I2C_NACK:
+        break;
+    }
+
+    return 0;
+}
+
+static int sii9022_rx(I2CSlave *i2c)
+{
+    sii9022_state *s = SII9022(i2c);
+    uint8_t res = 0x00;
+
+    switch (s->ptr) {
+    case SII9022_SYS_CTRL_DATA:
+        if (s->ddc_req) {
+            /* Acknowledge DDC bus request */
+            res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
+        }
+        break;
+    case SII9022_REG_CHIPID:
+        res = 0xb0;
+        break;
+    case SII9022_INT_STATUS:
+        /* Something is cold-plugged in, no interrupts */
+        res = SII9022_INT_STATUS_PLUGGED;
+        break;
+    default:
+        break;
+    }
+
+    trace_sii9022_read_reg(s->ptr, res);
+    s->ptr++;
+
+    return res;
+}
+
+static int sii9022_tx(I2CSlave *i2c, uint8_t data)
+{
+    sii9022_state *s = SII9022(i2c);
+
+    if (s->addr_byte) {
+        s->ptr = data;
+        s->addr_byte = false;
+        return 0;
+    }
+
+    switch (s->ptr) {
+    case SII9022_SYS_CTRL_DATA:
+        if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
+            s->ddc_req = true;
+            if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
+                s->ddc = true;
+                /* Skip this finish since we just switched to DDC */
+                s->ddc_skip_finish = true;
+                trace_sii9022_switch_mode("DDC");
+            }
+        } else {
+            s->ddc_req = false;
+            s->ddc = false;
+            trace_sii9022_switch_mode("normal");
+        }
+        break;
+    default:
+        break;
+    }
+
+    trace_sii9022_write_reg(s->ptr, data);
+    s->ptr++;
+
+    return 0;
+}
+
+static void sii9022_reset(DeviceState *dev)
+{
+    sii9022_state *s = SII9022(dev);
+
+    s->ptr = 0;
+    s->addr_byte = false;
+    s->ddc_req = false;
+    s->ddc_skip_finish = false;
+    s->ddc = false;
+}
+
+static void sii9022_realize(DeviceState *dev, Error **errp)
+{
+    I2CBus *bus;
+
+    bus = I2C_BUS(qdev_get_parent_bus(dev));
+    i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
+}
+
+static void sii9022_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+    k->event = sii9022_event;
+    k->recv = sii9022_rx;
+    k->send = sii9022_tx;
+    dc->reset = sii9022_reset;
+    dc->realize = sii9022_realize;
+    dc->vmsd = &vmstate_sii9022;
+}
+
+static const TypeInfo sii9022_info = {
+    .name          = TYPE_SII9022,
+    .parent        = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(sii9022_state),
+    .class_init    = sii9022_class_init,
+};
+
+static void sii9022_register_types(void)
+{
+    type_register_static(&sii9022_info);
+}
+
+type_init(sii9022_register_types)
diff --git a/hw/display/trace-events b/hw/display/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -XXX,XX +XXX,XX @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
 vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
+
+# hw/display/sii9022.c
+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+sii9022_switch_mode(const char *mode) "mode: %s"
-- 
2.16.2

From: Linus Walleij <linus.walleij@linaro.org>

This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
Versatile Express machine, and selects the two I2C devices necessary
in the arm-softmmu.mak configuration so everything will build
smoothly.

I am implementing proper handling of the graphics in the Linux
kernel and adding proper emulation of SiI9022 and EDID makes the
driver probe as nicely as before, retrieving the resolutions
supported by the "QEMU monitor" and overall just working nice.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-6-linus.walleij@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/vexpress.c               | 6 +++++-
 default-configs/arm-softmmu.mak | 2 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/arm.h"
 #include "hw/arm/primecell.h"
 #include "hw/devices.h"
+#include "hw/i2c/i2c.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     uint32_t sys_id;
     DriveInfo *dinfo;
     pflash_t *pflash0;
+    I2CBus *i2c;
     ram_addr_t vram_size, sram_size;
     MemoryRegion *sysmem = get_system_memory();
     MemoryRegion *vram = g_new(MemoryRegion, 1);
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 
-    /* VE_SERIALDVI: not modelled */
+    dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
+    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
+    i2c_create_slave(i2c, "sii9022", 0x39);
 
     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_STELLARIS_INPUT=y
 CONFIG_STELLARIS_ENET=y
 CONFIG_SSD0303=y
 CONFIG_SSD0323=y
+CONFIG_DDC=y
+CONFIG_SII9022=y
 CONFIG_ADS7846=y
 CONFIG_MAX111X=y
 CONFIG_SSI=y
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-2-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/helper-head.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_int i32
 #define dh_alias_i64 i64
 #define dh_alias_s64 i64
+#define dh_alias_f16 i32
 #define dh_alias_f32 i32
 #define dh_alias_f64 i64
 #define dh_alias_ptr ptr
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_int int
 #define dh_ctype_i64 uint64_t
 #define dh_ctype_s64 int64_t
+#define dh_ctype_f16 float16
 #define dh_ctype_f32 float32
 #define dh_ctype_f64 float64
 #define dh_ctype_ptr void *
@@ -XXX,XX +XXX,XX @@
 #define dh_is_signed_s32 1
 #define dh_is_signed_i64 0
 #define dh_is_signed_s64 1
+#define dh_is_signed_f16 0
 #define dh_is_signed_f32 0
 #define dh_is_signed_f64 0
 #define dh_is_signed_tl  0
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h           | 32 ++++++++++++++++++++++------
 target/arm/helper.c        | 26 ++++++++++++++++++-----
 target/arm/translate-a64.c | 53 +++++++++++++++++++++++++---------------------
 3 files changed, 75 insertions(+), 36 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
         /* scratch space when Tn are not sufficient.  */
         uint32_t scratch[8];
 
-        /* fp_status is the "normal" fp status. standard_fp_status retains
-         * values corresponding to the ARM "Standard FPSCR Value", ie
-         * default-NaN, flush-to-zero, round-to-nearest and is used by
-         * any operations (generally Neon) which the architecture defines
-         * as controlled by the standard FPSCR value rather than the FPSCR.
+        /* There are a number of distinct float control structures:
+         *
+         *  fp_status: is the "normal" fp status.
+         *  fp_status_fp16: used for half-precision calculations
+         *  standard_fp_status : the ARM "Standard FPSCR Value"
+         *
+         * Half-precision operations are governed by a separate
+         * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
+         * status structure to control this.
+         *
+         * The "Standard FPSCR", ie default-NaN, flush-to-zero,
+         * round-to-nearest and is used by any operations (generally
+         * Neon) which the architecture defines as controlled by the
+         * standard FPSCR value rather than the FPSCR.
          *
          * To avoid having to transfer exception bits around, we simply
          * say that the FPSCR cumulative exception flags are the logical
-         * OR of the flags in the two fp statuses. This relies on the
+         * OR of the flags in the three fp statuses. This relies on the
          * only thing which needs to read the exception flags being
          * an explicit FPSCR read.
          */
         float_status fp_status;
+        float_status fp_status_f16;
         float_status standard_fp_status;
 
         /* ZCR_EL[1-3] */
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 uint32_t vfp_get_fpscr(CPUARMState *env);
 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 
-/* For A64 the FPSCR is split into two logically distinct registers,
+/* FPCR, Floating Point Control Register
+ * FPSR, Floating Poiht Status Register
+ *
+ * For A64 the FPSCR is split into two logically distinct registers,
  * FPCR and FPSR. However since they still use non-overlapping bits
  * we store the underlying state in fpscr and just mask on read/write.
  */
 #define FPSR_MASK 0xf800009f
 #define FPCR_MASK 0x07f79f00
+
+#define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
+#define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
+#define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
+
 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
 {
     return vfp_get_fpscr(env) & FPSR_MASK;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
             | (env->vfp.vec_stride << 20);
     i = get_float_exception_flags(&env->vfp.fp_status);
     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
+    i |= get_float_exception_flags(&env->vfp.fp_status_f16);
     fpscr |= vfp_exceptbits_from_host(i);
     return fpscr;
 }
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
             break;
         }
         set_float_rounding_mode(i, &env->vfp.fp_status);
+        set_float_rounding_mode(i, &env->vfp.fp_status_f16);
     }
-    if (changed & (1 << 24)) {
-        set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
-        set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
+    if (changed & FPCR_FZ16) {
+        bool ftz_enabled = val & FPCR_FZ16;
+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+    }
+    if (changed & FPCR_FZ) {
+        bool ftz_enabled = val & FPCR_FZ;
+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
+    }
+    if (changed & FPCR_DN) {
+        bool dnan_enabled = val & FPCR_DN;
+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
     }
-    if (changed & (1 << 25))
-        set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
 
+    /* The exception flags are ORed together when we read fpscr so we
+     * only need to preserve the current state in one of our
+     * float_status values.
+     */
     i = vfp_exceptbits_to_host(val);
     set_float_exception_flags(i, &env->vfp.fp_status);
+    set_float_exception_flags(0, &env->vfp.fp_status_f16);
     set_float_exception_flags(0, &env->vfp.standard_fp_status);
 }
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
     tcg_temp_free_i64(tmp);
 }
 
-static TCGv_ptr get_fpstatus_ptr(void)
+static TCGv_ptr get_fpstatus_ptr(bool is_f16)
 {
     TCGv_ptr statusptr = tcg_temp_new_ptr();
     int offset;
 
-    /* In A64 all instructions (both FP and Neon) use the FPCR;
-     * there is no equivalent of the A32 Neon "standard FPSCR value"
-     * and all operations use vfp.fp_status.
+    /* In A64 all instructions (both FP and Neon) use the FPCR; there
+     * is no equivalent of the A32 Neon "standard FPSCR value".
+     * However half-precision operations operate under a different
+     * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
      */
-    offset = offsetof(CPUARMState, vfp.fp_status);
+    if (is_f16) {
+        offset = offsetof(CPUARMState, vfp.fp_status_f16);
+    } else {
+        offset = offsetof(CPUARMState, vfp.fp_status);
+    }
     tcg_gen_addi_ptr(statusptr, cpu_env, offset);
     return statusptr;
 }
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
                               bool cmp_with_zero, bool signal_all_nans)
 {
     TCGv_i64 tcg_flags = tcg_temp_new_i64();
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     if (is_double) {
         TCGv_i64 tcg_vn, tcg_vm;
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
     TCGv_i32 tcg_op;
     TCGv_i32 tcg_res;
 
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op = read_fp_sreg(s, rn);
     tcg_res = tcg_temp_new_i32();
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
         return;
     }
 
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op = read_fp_dreg(s, rn);
     tcg_res = tcg_temp_new_i64();
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
     TCGv_ptr fpst;
 
     tcg_res = tcg_temp_new_i32();
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op1 = read_fp_sreg(s, rn);
     tcg_op2 = read_fp_sreg(s, rm);
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
     TCGv_ptr fpst;
 
     tcg_res = tcg_temp_new_i64();
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op1 = read_fp_dreg(s, rn);
     tcg_op2 = read_fp_dreg(s, rm);
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
 {
     TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
     TCGv_i32 tcg_res = tcg_temp_new_i32();
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     tcg_op1 = read_fp_sreg(s, rn);
     tcg_op2 = read_fp_sreg(s, rm);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
 {
     TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
     TCGv_i64 tcg_res = tcg_temp_new_i64();
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     tcg_op1 = read_fp_dreg(s, rn);
     tcg_op2 = read_fp_dreg(s, rm);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
     TCGv_ptr tcg_fpstatus;
     TCGv_i32 tcg_shift;
 
-    tcg_fpstatus = get_fpstatus_ptr();
+    tcg_fpstatus = get_fpstatus_ptr(false);
 
     tcg_shift = tcg_const_i32(64 - scale);
 
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
         TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
         TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
         TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
-        TCGv_ptr fpst = get_fpstatus_ptr();
+        TCGv_ptr fpst = get_fpstatus_ptr(false);
 
         assert(esize == 32);
         assert(elements == 4);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
         }
 
         size = extract32(size, 0, 1) ? 3 : 2;
-        fpst = get_fpstatus_ptr();
+        fpst = get_fpstatus_ptr(false);
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
                                    int fracbits, int size)
 {
     bool is_double = size == 3 ? true : false;
-    TCGv_ptr tcg_fpst = get_fpstatus_ptr();
+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
     TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
     TCGv_i64 tcg_int = tcg_temp_new_i64();
     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
 
     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-    tcg_fpstatus = get_fpstatus_ptr();
+    tcg_fpstatus = get_fpstatus_ptr(false);
     tcg_shift = tcg_const_i32(fracbits);
 
     if (is_double) {
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
                                int fpopcode, int rd, int rn, int rm)
 {
     int pass;
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     for (pass = 0; pass < elements; pass++) {
         if (size) {
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
         return;
     }
 
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
 
     if (is_double) {
         TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
                                     int size, int rn, int rd)
 {
     bool is_double = (size == 3);
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     if (is_double) {
         TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
     if (is_fcvt) {
         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
         gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-        tcg_fpstatus = get_fpstatus_ptr();
+        tcg_fpstatus = get_fpstatus_ptr(false);
     } else {
         tcg_rmode = NULL;
         tcg_fpstatus = NULL;
@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
 
     /* Floating point operations need fpst */
     if (opcode >= 0x58) {
-        fpst = get_fpstatus_ptr();
+        fpst = get_fpstatus_ptr(false);
     } else {
         fpst = NULL;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
     }
 
     if (need_fpstatus) {
-        tcg_fpstatus = get_fpstatus_ptr();
+        tcg_fpstatus = get_fpstatus_ptr(false);
     } else {
         tcg_fpstatus = NULL;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
     }
 
     if (is_fp) {
-        fpst = get_fpstatus_ptr();
+        fpst = get_fpstatus_ptr(false);
     } else {
         fpst = NULL;
     }
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

As the rounding mode is now split between FP16 and the rest of
floating point we need to be explicit when tweaking it. Instead of
passing the CPU env we now pass the appropriate fpst pointer directly.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-6-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  2 +-
 target/arm/helper.c        |  4 ++--
 target/arm/translate-a64.c | 26 +++++++++++++-------------
 target/arm/translate.c     | 12 ++++++------
 4 files changed, 22 insertions(+), 22 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |   4 ++
 target/arm/helper-a64.c    |  18 ++++++
 target/arm/translate-a64.c | 140 ++++++++++++++++++++++++++++-----------------
 3 files changed, 109 insertions(+), 53 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
 DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
 DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
                    i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
 {
     return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
 }
+
+/*
+ * AdvSIMD half-precision
+ */
+
+#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
+
+#define ADVSIMD_HALFOP(name) \
+float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+{ \
+    float_status *fpst = fpstp; \
+    return float16_ ## name(a, b, fpst);    \
+}
+
+ADVSIMD_HALFOP(min)
+ADVSIMD_HALFOP(max)
+ADVSIMD_HALFOP(minnum)
+ADVSIMD_HALFOP(maxnum)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resh);
 }
 
-static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
-                        int opc, bool is_min, TCGv_ptr fpst)
+/*
+ * do_reduction_op helper
+ *
+ * This mirrors the Reduce() pseudocode in the ARM ARM. It is
+ * important for correct NaN propagation that we do these
+ * operations in exactly the order specified by the pseudocode.
+ *
+ * This is a recursive function, TCG temps should be freed by the
+ * calling function once it is done with the values.
+ */
+static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
+                                int esize, int size, int vmap, TCGv_ptr fpst)
 {
-    /* Helper function for disas_simd_across_lanes: do a single precision
-     * min/max operation on the specified two inputs,
-     * and return the result in tcg_elt1.
-     */
-    if (opc == 0xc) {
-        if (is_min) {
-            gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-        } else {
-            gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-        }
+    if (esize == size) {
+        int element;
+        TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
+        TCGv_i32 tcg_elem;
+
+        /* We should have one register left here */
+        assert(ctpop8(vmap) == 1);
+        element = ctz32(vmap);
+        assert(element < 8);
+
+        tcg_elem = tcg_temp_new_i32();
+        read_vec_element_i32(s, tcg_elem, rn, element, msize);
+        return tcg_elem;
     } else {
-        assert(opc == 0xf);
-        if (is_min) {
-            gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-        } else {
-            gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+        int bits = size / 2;
+        int shift = ctpop8(vmap) / 2;
+        int vmap_lo = (vmap >> shift) & vmap;
+        int vmap_hi = (vmap & ~vmap_lo);
+        TCGv_i32 tcg_hi, tcg_lo, tcg_res;
+
+        tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
+        tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
+        tcg_res = tcg_temp_new_i32();
+
+        switch (fpopcode) {
+        case 0x0c: /* fmaxnmv half-precision */
+            gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x0f: /* fmaxv half-precision */
+            gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x1c: /* fminnmv half-precision */
+            gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x1f: /* fminv half-precision */
+            gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x2c: /* fmaxnmv */
+            gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x2f: /* fmaxv */
+            gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x3c: /* fminnmv */
+            gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x3f: /* fminv */
+            gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        default:
+            g_assert_not_reached();
         }
+
+        tcg_temp_free_i32(tcg_hi);
+        tcg_temp_free_i32(tcg_lo);
+        return tcg_res;
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
         break;
     case 0xc: /* FMAXNMV, FMINNMV */
     case 0xf: /* FMAXV, FMINV */
-        if (!is_u || !is_q || extract32(size, 0, 1)) {
-            unallocated_encoding(s);
-            return;
-        }
-        /* Bit 1 of size field encodes min vs max, and actual size is always
-         * 32 bits: adjust the size variable so following code can rely on it
+        /* Bit 1 of size field encodes min vs max and the actual size
+         * depends on the encoding of the U bit. If not set (and FP16
+         * enabled) then we do half-precision float instead of single
+         * precision.
          */
         is_min = extract32(size, 1, 1);
         is_fp = true;
-        size = 2;
+        if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            size = 1;
+        } else if (!is_u || !is_q || extract32(size, 0, 1)) {
+            unallocated_encoding(s);
+            return;
+        } else {
+            size = 2;
+        }
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
 
         }
     } else {
-        /* Floating point ops which work on 32 bit (single) intermediates.
+        /* Floating point vector reduction ops which work across 32
+         * bit (single) or 16 bit (half-precision) intermediates.
          * Note that correct NaN propagation requires that we do these
          * operations in exactly the order specified by the pseudocode.
          */
-        TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
-        TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
-        TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
-        TCGv_ptr fpst = get_fpstatus_ptr(false);
-
-        assert(esize == 32);
-        assert(elements == 4);
-
-        read_vec_element(s, tcg_elt, rn, 0, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
-        read_vec_element(s, tcg_elt, rn, 1, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
-
-        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
-
-        read_vec_element(s, tcg_elt, rn, 2, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
-        read_vec_element(s, tcg_elt, rn, 3, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
-
-        do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
-
-        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
-
-        tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
-        tcg_temp_free_i32(tcg_elt1);
-        tcg_temp_free_i32(tcg_elt2);
-        tcg_temp_free_i32(tcg_elt3);
+        TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
+        int fpopcode = opcode | is_min << 4 | is_u << 5;
+        int vmap = (1 << elements) - 1;
+        TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
+                                             (is_q ? 128 : 64), vmap, fpst);
+        tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
+        tcg_temp_free_i32(tcg_res32);
         tcg_temp_free_ptr(fpst);
     }
 
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

We do implement all the opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-8-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
     /* Handle 64x64->64 opcodes which are shared between the scalar
      * and vector 3-same groups. We cover every opcode where size == 3
      * is valid in either the three-reg-same (integer, not pairwise)
-     * or scalar-three-reg-same groups. (Some opcodes are not yet
-     * implemented.)
+     * or scalar-three-reg-same groups.
      */
     TCGCond cond;
 
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This is the initial decode skeleton for the Advanced SIMD three same
instruction group.

The fprintf is purely to aid debugging as the additional instructions
are added. It will be removed once the group is complete.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-9-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  4 ++++
 target/arm/helper-a64.c    |  4 ++++
 target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
     return float16_ ## name(a, b, fpst);    \
 }
 
+ADVSIMD_HALFOP(add)
+ADVSIMD_HALFOP(sub)
+ADVSIMD_HALFOP(mul)
+ADVSIMD_HALFOP(div)
 ADVSIMD_HALFOP(min)
 ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
 
         switch (fpopcode) {
+        case 0x0: /* FMAXNM */
+            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x2: /* FADD */
+            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x6: /* FMAX */
+            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x8: /* FMINNM */
+            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xa: /* FSUB */
+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xe: /* FMIN */
+            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x13: /* FMUL */
+            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x17: /* FDIV */
+            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x1a: /* FABD */
+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
+            break;
         default:
             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
                     __func__, insn, fpopcode, s->pc);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  5 +++++
 target/arm/helper-a64.c    | 49 ++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 15 ++++++++++++++
 3 files changed, 69 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
 DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
 DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
 DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(min)
 ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
 ADVSIMD_HALFOP(maxnum)
+
+/*
+ * Floating point comparisons produce an integer result. Softfloat
+ * routines return float_relation types which we convert to the 0/-1
+ * Neon requires.
+ */
+
+#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
+
+uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    int compare = float16_compare_quiet(a, b, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_equal);
+}
+
+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    int compare = float16_compare(a, b, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater ||
+                          compare == float_relation_equal);
+}
+
+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    int compare = float16_compare(a, b, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater);
+}
+
+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16 f0 = float16_abs(a);
+    float16 f1 = float16_abs(b);
+    int compare = float16_compare(f0, f1, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater ||
+                          compare == float_relation_equal);
+}
+
+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16 f0 = float16_abs(a);
+    float16 f1 = float16_abs(b);
+    int compare = float16_compare(f0, f1, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x2: /* FADD */
             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x4: /* FCMEQ */
+            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x6: /* FMAX */
             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x13: /* FMUL */
             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x14: /* FCMGE */
+            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x15: /* FACGE */
+            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x17: /* FDIV */
             gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
             tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
             break;
+        case 0x1c: /* FCMGT */
+            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x1d: /* FACGT */
+            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         default:
             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
                     __func__, insn, fpopcode, s->pc);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  2 ++
 target/arm/helper-a64.c    | 24 ++++++++++++++++++++++++
 target/arm/translate-a64.c | 15 +++++++++++++++
 3 files changed, 41 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
 ADVSIMD_HALFOP(maxnum)
 
+/* Data processing - scalar floating-point and advanced SIMD */
+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    a = float16_squash_input_denormal(a, fpst);
+    b = float16_squash_input_denormal(b, fpst);
+
+    if ((float16_is_zero(a) && float16_is_infinity(b)) ||
+        (float16_is_infinity(a) && float16_is_zero(b))) {
+        /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
+        return make_float16((1U << 14) |
+                            ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
+    }
+    return float16_mul(a, b, fpst);
+}
+
+/* fused multiply-accumulate */
+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    return float16_muladd(a, b, c, 0, fpst);
+}
+
 /*
  * Floating point comparisons produce an integer result. Softfloat
  * routines return float_relation types which we convert to the 0/-1
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x0: /* FMAXNM */
             gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x1: /* FMLA */
+            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                       fpst);
+            break;
         case 0x2: /* FADD */
             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x3: /* FMULX */
+            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x4: /* FCMEQ */
             gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x8: /* FMINNM */
             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x9: /* FMLS */
+             /* As usual for ARM, separate negation for fused multiply-add */
+            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
+            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                       fpst);
+            break;
         case 0xa: /* FSUB */
             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/fpu/softfloat.h    | 18 +++++++++++++-----
 target/arm/helper-a64.h    |  2 ++
 target/arm/helper-a64.c    | 34 ++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c |  6 ++++++
 4 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index XXXXXXX..XXXXXXX 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -XXX,XX +XXX,XX @@ static inline float16 float16_set_sign(float16 a, int sign)
 }
 
 #define float16_zero make_float16(0)
-#define float16_one make_float16(0x3c00)
 #define float16_half make_float16(0x3800)
+#define float16_one make_float16(0x3c00)
+#define float16_one_point_five make_float16(0x3e00)
+#define float16_two make_float16(0x4000)
+#define float16_three make_float16(0x4200)
 #define float16_infinity make_float16(0x7c00)
 
 /*----------------------------------------------------------------------------
@@ -XXX,XX +XXX,XX @@ static inline float32 float32_set_sign(float32 a, int sign)
 }
 
 #define float32_zero make_float32(0)
-#define float32_one make_float32(0x3f800000)
 #define float32_half make_float32(0x3f000000)
+#define float32_one make_float32(0x3f800000)
+#define float32_one_point_five make_float32(0x3fc00000)
+#define float32_two make_float32(0x40000000)
+#define float32_three make_float32(0x40400000)
 #define float32_infinity make_float32(0x7f800000)
 
-
 /*----------------------------------------------------------------------------
 | The pattern for a default generated single-precision NaN.
 *----------------------------------------------------------------------------*/
@@ -XXX,XX +XXX,XX @@ static inline float64 float64_set_sign(float64 a, int sign)
 }
 
 #define float64_zero make_float64(0)
-#define float64_one make_float64(0x3ff0000000000000LL)
-#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
 #define float64_half make_float64(0x3fe0000000000000LL)
+#define float64_one make_float64(0x3ff0000000000000LL)
+#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
+#define float64_two make_float64(0x4000000000000000ULL)
+#define float64_three make_float64(0x4008000000000000ULL)
+#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
 #define float64_infinity make_float64(0x7ff0000000000000LL)
 
 /*----------------------------------------------------------------------------
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
 DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
 DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
 DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
 DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
 DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
 DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
  * versions, these do a fully fused multiply-add or
  * multiply-add-and-halve.
  */
+#define float16_two make_float16(0x4000)
+#define float16_three make_float16(0x4200)
+#define float16_one_point_five make_float16(0x3e00)
+
 #define float32_two make_float32(0x40000000)
 #define float32_three make_float32(0x40400000)
 #define float32_one_point_five make_float32(0x3fc00000)
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 #define float64_three make_float64(0x4008000000000000ULL)
 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
+float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    a = float16_squash_input_denormal(a, fpst);
+    b = float16_squash_input_denormal(b, fpst);
+
+    a = float16_chs(a);
+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
+        (float16_is_infinity(b) && float16_is_zero(a))) {
+        return float16_two;
+    }
+    return float16_muladd(a, b, float16_two, 0, fpst);
+}
+
 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 {
     float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
     return float64_muladd(a, b, float64_two, 0, fpst);
 }
 
+float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    a = float16_squash_input_denormal(a, fpst);
+    b = float16_squash_input_denormal(b, fpst);
+
+    a = float16_chs(a);
+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
+        (float16_is_infinity(b) && float16_is_zero(a))) {
+        return float16_one_point_five;
+    }
+    return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
+}
+
 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 {
     float_status *fpst = fpstp;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x6: /* FMAX */
             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x7: /* FRECPS */
+            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x8: /* FMINNM */
             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0xe: /* FMIN */
             gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0xf: /* FRSQRTS */
+            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x13: /* FMUL */
             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++----------------
 1 file changed, 133 insertions(+), 75 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
     int datasize, elements;
     int pass;
     TCGv_ptr fpst;
+    bool pairwise = false;
 
     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
     datasize = is_q ? 128 : 64;
     elements = datasize / 16;
 
+    switch (fpopcode) {
+    case 0x10: /* FMAXNMP */
+    case 0x12: /* FADDP */
+    case 0x16: /* FMAXP */
+    case 0x18: /* FMINNMP */
+    case 0x1e: /* FMINP */
+        pairwise = true;
+        break;
+    }
+
     fpst = get_fpstatus_ptr(true);
 
-    for (pass = 0; pass < elements; pass++) {
+    if (pairwise) {
+        int maxpass = is_q ? 8 : 4;
         TCGv_i32 tcg_op1 = tcg_temp_new_i32();
         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-        TCGv_i32 tcg_res = tcg_temp_new_i32();
+        TCGv_i32 tcg_res[8];
 
-        read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
-        read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+        for (pass = 0; pass < maxpass; pass++) {
+            int passreg = pass < (maxpass / 2) ? rn : rm;
+            int passelt = (pass << 1) & (maxpass - 1);
 
-        switch (fpopcode) {
-        case 0x0: /* FMAXNM */
-            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x1: /* FMLA */
-            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-                                       fpst);
-            break;
-        case 0x2: /* FADD */
-            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x3: /* FMULX */
-            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x4: /* FCMEQ */
-            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x6: /* FMAX */
-            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x7: /* FRECPS */
-            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x8: /* FMINNM */
-            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x9: /* FMLS */
-             /* As usual for ARM, separate negation for fused multiply-add */
-            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
-            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-                                       fpst);
-            break;
-        case 0xa: /* FSUB */
-            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xe: /* FMIN */
-            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xf: /* FRSQRTS */
-            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x13: /* FMUL */
-            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x14: /* FCMGE */
-            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x15: /* FACGE */
-            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x17: /* FDIV */
-            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x1a: /* FABD */
-            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
-            break;
-        case 0x1c: /* FCMGT */
-            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x1d: /* FACGT */
-            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        default:
-            fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
-                    __func__, insn, fpopcode, s->pc);
-            g_assert_not_reached();
+            read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
+            read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
+            tcg_res[pass] = tcg_temp_new_i32();
+
+            switch (fpopcode) {
+            case 0x10: /* FMAXNMP */
+                gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
+                                           fpst);
+                break;
+            case 0x12: /* FADDP */
+                gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x16: /* FMAXP */
+                gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x18: /* FMINNMP */
+                gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
+                                           fpst);
+                break;
+            case 0x1e: /* FMINP */
+                gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+        }
+
+        for (pass = 0; pass < maxpass; pass++) {
+            write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
+            tcg_temp_free_i32(tcg_res[pass]);
         }
 
-        write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-        tcg_temp_free_i32(tcg_res);
         tcg_temp_free_i32(tcg_op1);
         tcg_temp_free_i32(tcg_op2);
+
+    } else {
+        for (pass = 0; pass < elements; pass++) {
+            TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+            TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+            TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+            read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
+            read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+
+            switch (fpopcode) {
+            case 0x0: /* FMAXNM */
+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x1: /* FMLA */
+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                           fpst);
+                break;
+            case 0x2: /* FADD */
+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x3: /* FMULX */
+                gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x4: /* FCMEQ */
+                gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x6: /* FMAX */
+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x7: /* FRECPS */
+                gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x8: /* FMINNM */
+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x9: /* FMLS */
+                /* As usual for ARM, separate negation for fused multiply-add */
+                tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                           fpst);
+                break;
+            case 0xa: /* FSUB */
+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xe: /* FMIN */
+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xf: /* FRSQRTS */
+                gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x13: /* FMUL */
+                gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x14: /* FCMGE */
+                gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x15: /* FACGE */
+                gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x17: /* FDIV */
+                gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x1a: /* FABD */
+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+                tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
+                break;
+            case 0x1c: /* FCMGT */
+                gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x1d: /* FACGT */
+                gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
+                        __func__, insn, fpopcode, s->pc);
+                g_assert_not_reached();
+            }
+
+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+            tcg_temp_free_i32(tcg_res);
+            tcg_temp_free_i32(tcg_op1);
+            tcg_temp_free_i32(tcg_op2);
+        }
     }
 
     tcg_temp_free_ptr(fpst);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

The helpers use the new re-factored muladd support in SoftFloat for
the float16 work.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180227143852.11175-15-alex.bennee@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 66 insertions(+), 16 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.

Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    | 10 ++++++++++
 target/arm/helper-a64.c    | 46 +++++++++++++++++++++++++++++++++++++++++++++-
 target/arm/translate-a64.c | 26 +++++++++++++++++++++-----
 3 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
 DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
 ADVSIMD_HALFOP(maxnum)
 
+#define ADVSIMD_TWOHALFOP(name)                                         \
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
+{ \
+    float16  a1, a2, b1, b2;                        \
+    uint32_t r1, r2;                                \
+    float_status *fpst = fpstp;                     \
+    a1 = extract32(two_a, 0, 16);                   \
+    a2 = extract32(two_a, 16, 16);                  \
+    b1 = extract32(two_b, 0, 16);                   \
+    b2 = extract32(two_b, 16, 16);                  \
+    r1 = float16_ ## name(a1, b1, fpst);            \
+    r2 = float16_ ## name(a2, b2, fpst);            \
+    return deposit32(r1, 16, 16, r2);               \
+}
+
+ADVSIMD_TWOHALFOP(add)
+ADVSIMD_TWOHALFOP(sub)
+ADVSIMD_TWOHALFOP(mul)
+ADVSIMD_TWOHALFOP(div)
+ADVSIMD_TWOHALFOP(min)
+ADVSIMD_TWOHALFOP(max)
+ADVSIMD_TWOHALFOP(minnum)
+ADVSIMD_TWOHALFOP(maxnum)
+
 /* Data processing - scalar floating-point and advanced SIMD */
-float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+static float16 float16_mulx(float16 a, float16 b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
     return float16_mul(a, b, fpst);
 }
 
+ADVSIMD_HALFOP(mulx)
+ADVSIMD_TWOHALFOP(mulx)
+
 /* fused multiply-accumulate */
 float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
 {
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
     return float16_muladd(a, b, c, 0, fpst);
 }
 
+uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
+                                  uint32_t two_c, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16  a1, a2, b1, b2, c1, c2;
+    uint32_t r1, r2;
+    a1 = extract32(two_a, 0, 16);
+    a2 = extract32(two_a, 16, 16);
+    b1 = extract32(two_b, 0, 16);
+    b2 = extract32(two_b, 16, 16);
+    c1 = extract32(two_c, 0, 16);
+    c2 = extract32(two_c, 16, 16);
+    r1 = float16_muladd(a1, b1, c1, 0, fpst);
+    r2 = float16_muladd(a2, b2, c2, 0, fpst);
+    return deposit32(r1, 16, 16, r2);
+}
+
 /*
  * Floating point comparisons produce an integer result. Softfloat
  * routines return float_relation types which we convert to the 0/-1
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                          * multiply-add */
                         tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
                     }
-                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
-                                               tcg_res, fpst);
+                    if (is_scalar) {
+                        gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
+                                                   tcg_res, fpst);
+                    } else {
+                        gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
+                                                    tcg_res, fpst);
+                    }
                     break;
                 case 2:
                     if (opcode == 0x5) {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                 switch (size) {
                 case 1:
                     if (u) {
-                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
-                                                 fpst);
+                        if (is_scalar) {
+                            gen_helper_advsimd_mulxh(tcg_res, tcg_op,
+                                                     tcg_idx, fpst);
+                        } else {
+                            gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
+                                                      tcg_idx, fpst);
+                        }
                     } else {
-                        g_assert_not_reached();
+                        if (is_scalar) {
+                            gen_helper_advsimd_mulh(tcg_res, tcg_op,
+                                                    tcg_idx, fpst);
+                        } else {
+                            gen_helper_advsimd_mul2h(tcg_res, tcg_op,
+                                                     tcg_idx, fpst);
+                        }
                     }
                     break;
                 case 2:
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This actually covers two different sections of the encoding table:

Advanced SIMD scalar two-register miscellaneous FP16
   Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

This adds the full range of half-precision floating point to integral
instructions.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |   2 +
 target/arm/helper-a64.c    |  22 ++++++++
 target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++++--
 3 files changed, 142 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
 DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
 DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
 DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
     int compare = float16_compare(f0, f1, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_greater);
 }
+
+/* round to integral */
+float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+{
+    return float16_round_to_int(x, fp_status);
+}
+
+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+{
+    int old_flags = get_float_exception_flags(fp_status), new_flags;
+    float16 ret;
+
+    ret = float16_round_to_int(x, fp_status);
+
+    /* Suppress any inexact exceptions the conversion produced */
+    if (!(old_flags & float_flag_inexact)) {
+        new_flags = get_float_exception_flags(fp_status);
+        set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
+    }
+
+    return ret;
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
 {
-    int fpop, opcode, a;
+    int fpop, opcode, a, u;
+    int rn, rd;
+    bool is_q;
+    bool is_scalar;
+    bool only_in_vector = false;
+
+    int pass;
+    TCGv_i32 tcg_rmode = NULL;
+    TCGv_ptr tcg_fpstatus = NULL;
+    bool need_rmode = false;
+    int rmode;
 
     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
         unallocated_encoding(s);
         return;
     }
 
-    if (!fp_access_check(s)) {
-        return;
-    }
+    rd = extract32(insn, 0, 5);
+    rn = extract32(insn, 5, 5);
 
-    opcode = extract32(insn, 12, 4);
     a = extract32(insn, 23, 1);
+    u = extract32(insn, 29, 1);
+    is_scalar = extract32(insn, 28, 1);
+    is_q = extract32(insn, 30, 1);
+
+    opcode = extract32(insn, 12, 5);
     fpop = deposit32(opcode, 5, 1, a);
+    fpop = deposit32(fpop, 6, 1, u);
 
     switch (fpop) {
+    case 0x18: /* FRINTN */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_TIEEVEN;
+        break;
+    case 0x19: /* FRINTM */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_NEGINF;
+        break;
+    case 0x38: /* FRINTP */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_POSINF;
+        break;
+    case 0x39: /* FRINTZ */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_ZERO;
+        break;
+    case 0x58: /* FRINTA */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_TIEAWAY;
+        break;
+    case 0x59: /* FRINTX */
+    case 0x79: /* FRINTI */
+        only_in_vector = true;
+        /* current rounding mode */
+        break;
     default:
         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
         g_assert_not_reached();
     }
 
+
+    /* Check additional constraints for the scalar encoding */
+    if (is_scalar) {
+        if (!is_q) {
+            unallocated_encoding(s);
+            return;
+        }
+        /* FRINTxx is only in the vector form */
+        if (only_in_vector) {
+            unallocated_encoding(s);
+            return;
+        }
+    }
+
+    if (!fp_access_check(s)) {
+        return;
+    }
+
+    if (need_rmode) {
+        tcg_fpstatus = get_fpstatus_ptr(true);
+    }
+
+    if (need_rmode) {
+        tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+    }
+
+    if (is_scalar) {
+        /* no operations yet */
+    } else {
+        for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
+            TCGv_i32 tcg_op = tcg_temp_new_i32();
+            TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+            read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
+
+            switch (fpop) {
+            case 0x18: /* FRINTN */
+            case 0x19: /* FRINTM */
+            case 0x38: /* FRINTP */
+            case 0x39: /* FRINTZ */
+            case 0x58: /* FRINTA */
+            case 0x79: /* FRINTI */
+                gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
+                break;
+            case 0x59: /* FRINTX */
+                gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+
+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+
+            tcg_temp_free_i32(tcg_res);
+            tcg_temp_free_i32(tcg_op);
+        }
+
+        clear_vec_high(s, is_q, rd);
+    }
+
+    if (tcg_rmode) {
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+        tcg_temp_free_i32(tcg_rmode);
+    }
+
+    if (tcg_fpstatus) {
+        tcg_temp_free_ptr(tcg_fpstatus);
+    }
 }
 
 /* AdvSIMD scalar x indexed element
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This covers all the floating point convert operations.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  2 ++
 target/arm/helper-a64.c    | 32 +++++++++++++++++
 target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 118 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
 DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
 DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
 DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
+DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 
     return ret;
 }
+
+/*
+ * Half-precision floating point conversion functions
+ *
+ * There are a multitude of conversion functions with various
+ * different rounding modes. This is dealt with by the calling code
+ * setting the mode appropriately before calling the helper.
+ */
+
+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    /* Invalid if we are passed a NaN */
+    if (float16_is_any_nan(a)) {
+        float_raise(float_flag_invalid, fpst);
+        return 0;
+    }
+    return float16_to_int16(a, fpst);
+}
+
+uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    /* Invalid if we are passed a NaN */
+    if (float16_is_any_nan(a)) {
+        float_raise(float_flag_invalid, fpst);
+        return 0;
+    }
+    return float16_to_uint16(a, fpst);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
         only_in_vector = true;
         /* current rounding mode */
         break;
+    case 0x1a: /* FCVTNS */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEEVEN;
+        break;
+    case 0x1b: /* FCVTMS */
+        need_rmode = true;
+        rmode = FPROUNDING_NEGINF;
+        break;
+    case 0x1c: /* FCVTAS */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEAWAY;
+        break;
+    case 0x3a: /* FCVTPS */
+        need_rmode = true;
+        rmode = FPROUNDING_POSINF;
+        break;
+    case 0x3b: /* FCVTZS */
+        need_rmode = true;
+        rmode = FPROUNDING_ZERO;
+        break;
+    case 0x5a: /* FCVTNU */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEEVEN;
+        break;
+    case 0x5b: /* FCVTMU */
+        need_rmode = true;
+        rmode = FPROUNDING_NEGINF;
+        break;
+    case 0x5c: /* FCVTAU */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEAWAY;
+        break;
+    case 0x7a: /* FCVTPU */
+        need_rmode = true;
+        rmode = FPROUNDING_POSINF;
+        break;
+    case 0x7b: /* FCVTZU */
+        need_rmode = true;
+        rmode = FPROUNDING_ZERO;
+        break;
     default:
         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     }
 
     if (is_scalar) {
-        /* no operations yet */
+        TCGv_i32 tcg_op = tcg_temp_new_i32();
+        TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
+
+        switch (fpop) {
+        case 0x1a: /* FCVTNS */
+        case 0x1b: /* FCVTMS */
+        case 0x1c: /* FCVTAS */
+        case 0x3a: /* FCVTPS */
+        case 0x3b: /* FCVTZS */
+            gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
+            break;
+        case 0x5a: /* FCVTNU */
+        case 0x5b: /* FCVTMU */
+        case 0x5c: /* FCVTAU */
+        case 0x7a: /* FCVTPU */
+        case 0x7b: /* FCVTZU */
+            gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        /* limit any sign extension going on */
+        tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
+        write_fp_sreg(s, rd, tcg_res);
+
+        tcg_temp_free_i32(tcg_res);
+        tcg_temp_free_i32(tcg_op);
     } else {
         for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
             TCGv_i32 tcg_op = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
             read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
 
             switch (fpop) {
+            case 0x1a: /* FCVTNS */
+            case 0x1b: /* FCVTMS */
+            case 0x1c: /* FCVTAS */
+            case 0x3a: /* FCVTPS */
+            case 0x3b: /* FCVTZS */
+                gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
+                break;
+            case 0x5a: /* FCVTNU */
+            case 0x5b: /* FCVTMU */
+            case 0x5c: /* FCVTAU */
+            case 0x7a: /* FCVTPU */
+            case 0x7b: /* FCVTZU */
+                gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
+                break;
             case 0x18: /* FRINTN */
             case 0x19: /* FRINTM */
             case 0x38: /* FRINTP */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 57 insertions(+), 23 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
                                    bool is_scalar, bool is_u, bool is_q,
                                    int size, int rn, int rd)
 {
-    bool is_double = (size == 3);
+    bool is_double = (size == MO_64);
     TCGv_ptr fpst;
 
     if (!fp_access_check(s)) {
         return;
     }
 
-    fpst = get_fpstatus_ptr(false);
+    fpst = get_fpstatus_ptr(size == MO_16);
 
     if (is_double) {
         TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
         bool swap = false;
         int pass, maxpasses;
 
-        switch (opcode) {
-        case 0x2e: /* FCMLT (zero) */
-            swap = true;
-            /* fall through */
-        case 0x2c: /* FCMGT (zero) */
-            genfn = gen_helper_neon_cgt_f32;
-            break;
-        case 0x2d: /* FCMEQ (zero) */
-            genfn = gen_helper_neon_ceq_f32;
-            break;
-        case 0x6d: /* FCMLE (zero) */
-            swap = true;
-            /* fall through */
-        case 0x6c: /* FCMGE (zero) */
-            genfn = gen_helper_neon_cge_f32;
-            break;
-        default:
-            g_assert_not_reached();
+        if (size == MO_16) {
+            switch (opcode) {
+            case 0x2e: /* FCMLT (zero) */
+                swap = true;
+                /* fall through */
+            case 0x2c: /* FCMGT (zero) */
+                genfn = gen_helper_advsimd_cgt_f16;
+                break;
+            case 0x2d: /* FCMEQ (zero) */
+                genfn = gen_helper_advsimd_ceq_f16;
+                break;
+            case 0x6d: /* FCMLE (zero) */
+                swap = true;
+                /* fall through */
+            case 0x6c: /* FCMGE (zero) */
+                genfn = gen_helper_advsimd_cge_f16;
+                break;
+            default:
+                g_assert_not_reached();
+            }
+        } else {
+            switch (opcode) {
+            case 0x2e: /* FCMLT (zero) */
+                swap = true;
+                /* fall through */
+            case 0x2c: /* FCMGT (zero) */
+                genfn = gen_helper_neon_cgt_f32;
+                break;
+            case 0x2d: /* FCMEQ (zero) */
+                genfn = gen_helper_neon_ceq_f32;
+                break;
+            case 0x6d: /* FCMLE (zero) */
+                swap = true;
+                /* fall through */
+            case 0x6c: /* FCMGE (zero) */
+                genfn = gen_helper_neon_cge_f32;
+                break;
+            default:
+                g_assert_not_reached();
+            }
         }
 
         if (is_scalar) {
             maxpasses = 1;
         } else {
-            maxpasses = is_q ? 4 : 2;
+            int vector_size = 8 << is_q;
+            maxpasses = vector_size >> size;
         }
 
         for (pass = 0; pass < maxpasses; pass++) {
-            read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
+            read_vec_element_i32(s, tcg_op, rn, pass, size);
             if (swap) {
                 genfn(tcg_res, tcg_zero, tcg_op, fpst);
             } else {
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
             if (is_scalar) {
                 write_fp_sreg(s, rd, tcg_res);
             } else {
-                write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
+                write_vec_element_i32(s, tcg_res, rd, pass, size);
             }
         }
         tcg_temp_free_i32(tcg_res);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     fpop = deposit32(opcode, 5, 1, a);
     fpop = deposit32(fpop, 6, 1, u);
 
+    rd = extract32(insn, 0, 5);
+    rn = extract32(insn, 5, 5);
+
     switch (fpop) {
+    break;
+    case 0x2c: /* FCMGT (zero) */
+    case 0x2d: /* FCMEQ (zero) */
+    case 0x2e: /* FCMLT (zero) */
+    case 0x6c: /* FCMGE (zero) */
+    case 0x6d: /* FCMLE (zero) */
+        handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
+        return;
     case 0x18: /* FRINTN */
         need_rmode = true;
         only_in_vector = true;
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

I've re-factored the handle_simd_intfp_conv helper to properly handle
half-precision as well as call plain conversion helpers when we are
not doing fixed point conversion.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  10 ++++
 target/arm/helper.c        |   4 ++
 target/arm/translate-a64.c | 122 ++++++++++++++++++++++++++++++++++-----------
 3 files changed, 108 insertions(+), 28 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
 DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
 DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
 
+DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
 DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
 DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
+DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
 DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
 DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
 
+DEF_HELPER_2(vfp_touih, i32, f16, ptr)
 DEF_HELPER_2(vfp_touis, i32, f32, ptr)
 DEF_HELPER_2(vfp_touid, i32, f64, ptr)
+DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
 DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
 DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
+DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
 DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
 DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
+DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
 DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
 DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
 
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
 DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
 DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
 DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
 
 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
 DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
 
+FLOAT_CONVS(si, h, 16, )
 FLOAT_CONVS(si, s, 32, )
 FLOAT_CONVS(si, d, 64, )
+FLOAT_CONVS(ui, h, 16, u)
 FLOAT_CONVS(ui, s, 32, u)
 FLOAT_CONVS(ui, d, 64, u)
 
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
 VFP_CONV_FIX(uh, s, 32, 32, uint16)
 VFP_CONV_FIX(ul, s, 32, 32, uint32)
 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
+VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
+VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
 #undef VFP_CONV_FIX
 #undef VFP_CONV_FIX_FLOAT
 #undef VFP_CONV_FLOAT_FIX_ROUND
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
                                    int elements, int is_signed,
                                    int fracbits, int size)
 {
-    bool is_double = size == 3 ? true : false;
-    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
-    TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
-    TCGv_i64 tcg_int = tcg_temp_new_i64();
+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
+    TCGv_i32 tcg_shift = NULL;
+
     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
     int pass;
 
-    for (pass = 0; pass < elements; pass++) {
-        read_vec_element(s, tcg_int, rn, pass, mop);
+    if (fracbits || size == MO_64) {
+        tcg_shift = tcg_const_i32(fracbits);
+    }
+
+    if (size == MO_64) {
+        TCGv_i64 tcg_int64 = tcg_temp_new_i64();
+        TCGv_i64 tcg_double = tcg_temp_new_i64();
+
+        for (pass = 0; pass < elements; pass++) {
+            read_vec_element(s, tcg_int64, rn, pass, mop);
 
-        if (is_double) {
-            TCGv_i64 tcg_double = tcg_temp_new_i64();
             if (is_signed) {
-                gen_helper_vfp_sqtod(tcg_double, tcg_int,
+                gen_helper_vfp_sqtod(tcg_double, tcg_int64,
                                      tcg_shift, tcg_fpst);
             } else {
-                gen_helper_vfp_uqtod(tcg_double, tcg_int,
+                gen_helper_vfp_uqtod(tcg_double, tcg_int64,
                                      tcg_shift, tcg_fpst);
             }
             if (elements == 1) {
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
             } else {
                 write_vec_element(s, tcg_double, rd, pass, MO_64);
             }
-            tcg_temp_free_i64(tcg_double);
-        } else {
-            TCGv_i32 tcg_single = tcg_temp_new_i32();
-            if (is_signed) {
-                gen_helper_vfp_sqtos(tcg_single, tcg_int,
-                                     tcg_shift, tcg_fpst);
-            } else {
-                gen_helper_vfp_uqtos(tcg_single, tcg_int,
-                                     tcg_shift, tcg_fpst);
-            }
-            if (elements == 1) {
-                write_fp_sreg(s, rd, tcg_single);
-            } else {
-                write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
-            }
-            tcg_temp_free_i32(tcg_single);
         }
+
+        tcg_temp_free_i64(tcg_int64);
+        tcg_temp_free_i64(tcg_double);
+
+    } else {
+        TCGv_i32 tcg_int32 = tcg_temp_new_i32();
+        TCGv_i32 tcg_float = tcg_temp_new_i32();
+
+        for (pass = 0; pass < elements; pass++) {
+            read_vec_element_i32(s, tcg_int32, rn, pass, mop);
+
+            switch (size) {
+            case MO_32:
+                if (fracbits) {
+                    if (is_signed) {
+                        gen_helper_vfp_sltos(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_ultos(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    }
+                } else {
+                    if (is_signed) {
+                        gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
+                    }
+                }
+                break;
+            case MO_16:
+                if (fracbits) {
+                    if (is_signed) {
+                        gen_helper_vfp_sltoh(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_ultoh(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    }
+                } else {
+                    if (is_signed) {
+                        gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
+                    }
+                }
+                break;
+            default:
+                g_assert_not_reached();
+            }
+
+            if (elements == 1) {
+                write_fp_sreg(s, rd, tcg_float);
+            } else {
+                write_vec_element_i32(s, tcg_float, rd, pass, size);
+            }
+        }
+
+        tcg_temp_free_i32(tcg_int32);
+        tcg_temp_free_i32(tcg_float);
     }
 
-    tcg_temp_free_i64(tcg_int);
     tcg_temp_free_ptr(tcg_fpst);
-    tcg_temp_free_i32(tcg_shift);
+    if (tcg_shift) {
+        tcg_temp_free_i32(tcg_shift);
+    }
 
     clear_vec_high(s, elements << size == 16, rd);
 }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     rn = extract32(insn, 5, 5);
 
     switch (fpop) {
+    case 0x1d: /* SCVTF */
+    case 0x5d: /* UCVTF */
+    {
+        int elements;
+
+        if (is_scalar) {
+            elements = 1;
+        } else {
+            elements = (is_q ? 8 : 4);
+        }
+
+        if (!fp_access_check(s)) {
+            return;
+        }
+        handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
+        return;
+    }
     break;
     case 0x2c: /* FCMGT (zero) */
     case 0x2d: /* FCMEQ (zero) */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

From: Alex Bennée <alex.bennee@linaro.org>

It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h |   1 +
 target/arm/helper.c | 226 +++++++++++++++++++++++++++++-----------------------
 2 files changed, 129 insertions(+), 98 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
 
 DEF_HELPER_3(recps_f32, f32, f32, f32, env)
 DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
 DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
  * int->float conversions at run-time.  */
 #define float64_256 make_float64(0x4070000000000000LL)
 #define float64_512 make_float64(0x4080000000000000LL)
+#define float16_maxnorm make_float16(0x7bff)
 #define float32_maxnorm make_float32(0x7f7fffff)
 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
 
 /* Reciprocal functions
  *
  * The algorithm that must be used to calculate the estimate
- * is specified by the ARM ARM, see FPRecipEstimate()
+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
  */
 
-static float64 recip_estimate(float64 a, float_status *real_fp_status)
+/* See RecipEstimate()
+ *
+ * input is a 9 bit fixed point number
+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
+ * result range 256 .. 511 for a number from 1.0 to 511/256.
+ */
+
+static int recip_estimate(int input)
 {
-    /* These calculations mustn't set any fp exception flags,
-     * so we use a local copy of the fp_status.
-     */
-    float_status dummy_status = *real_fp_status;
-    float_status *s = &dummy_status;
-    /* q = (int)(a * 512.0) */
-    float64 q = float64_mul(float64_512, a, s);
-    int64_t q_int = float64_to_int64_round_to_zero(q, s);
-
-    /* r = 1.0 / (((double)q + 0.5) / 512.0) */
-    q = int64_to_float64(q_int, s);
-    q = float64_add(q, float64_half, s);
-    q = float64_div(q, float64_512, s);
-    q = float64_div(float64_one, q, s);
-
-    /* s = (int)(256.0 * r + 0.5) */
-    q = float64_mul(q, float64_256, s);
-    q = float64_add(q, float64_half, s);
-    q_int = float64_to_int64_round_to_zero(q, s);
-
-    /* return (double)s / 256.0 */
-    return float64_div(int64_to_float64(q_int, s), float64_256, s);
+    int a, b, r;
+    assert(256 <= input && input < 512);
+    a = (input * 2) + 1;
+    b = (1 << 19) / a;
+    r = (b + 1) >> 1;
+    assert(256 <= r && r < 512);
+    return r;
 }
 
-/* Common wrapper to call recip_estimate */
-static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
-{
-    uint64_t val64 = float64_val(num);
-    uint64_t frac = extract64(val64, 0, 52);
-    int64_t exp = extract64(val64, 52, 11);
-    uint64_t sbit;
-    float64 scaled, estimate;
+/*
+ * Common wrapper to call recip_estimate
+ *
+ * The parameters are exponent and 64 bit fraction (without implicit
+ * bit) where the binary point is nominally at bit 52. Returns a
+ * float64 which can then be rounded to the appropriate size by the
+ * callee.
+ */
 
-    /* Generate the scaled number for the estimate function */
-    if (exp == 0) {
+static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
+{
+    uint32_t scaled, estimate;
+    uint64_t result_frac;
+    int result_exp;
+
+    /* Handle sub-normals */
+    if (*exp == 0) {
         if (extract64(frac, 51, 1) == 0) {
-            exp = -1;
-            frac = extract64(frac, 0, 50) << 2;
+            *exp = -1;
+            frac <<= 2;
         } else {
-            frac = extract64(frac, 0, 51) << 1;
+            frac <<= 1;
         }
     }
 
-    /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
-    scaled = make_float64((0x3feULL << 52)
-                          | extract64(frac, 44, 8) << 44);
+    /* scaled = UInt('1':fraction<51:44>) */
+    scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
+    estimate = recip_estimate(scaled);
 
-    estimate = recip_estimate(scaled, fpst);
-
-    /* Build new result */
-    val64 = float64_val(estimate);
-    sbit = 0x8000000000000000ULL & val64;
-    exp = off - exp;
-    frac = extract64(val64, 0, 52);
-
-    if (exp == 0) {
-        frac = 1ULL << 51 | extract64(frac, 1, 51);
-    } else if (exp == -1) {
-        frac = 1ULL << 50 | extract64(frac, 2, 50);
-        exp = 0;
+    result_exp = exp_off - *exp;
+    result_frac = deposit64(0, 44, 8, estimate);
+    if (result_exp == 0) {
+        result_frac = deposit64(result_frac >> 1, 51, 1, 1);
+    } else if (result_exp == -1) {
+        result_frac = deposit64(result_frac >> 2, 50, 2, 1);
+        result_exp = 0;
     }
 
-    return make_float64(sbit | (exp << 52) | frac);
+    *exp = result_exp;
+
+    return result_frac;
 }
 
 static bool round_to_inf(float_status *fpst, bool sign_bit)
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
     g_assert_not_reached();
 }
 
+float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16 f16 = float16_squash_input_denormal(input, fpst);
+    uint32_t f16_val = float16_val(f16);
+    uint32_t f16_sign = float16_is_neg(f16);
+    int f16_exp = extract32(f16_val, 10, 5);
+    uint32_t f16_frac = extract32(f16_val, 0, 10);
+    uint64_t f64_frac;
+
+    if (float16_is_any_nan(f16)) {
+        float16 nan = f16;
+        if (float16_is_signaling_nan(f16, fpst)) {
+            float_raise(float_flag_invalid, fpst);
+            nan = float16_maybe_silence_nan(f16, fpst);
+        }
+        if (fpst->default_nan_mode) {
+            nan =  float16_default_nan(fpst);
+        }
+        return nan;
+    } else if (float16_is_infinity(f16)) {
+        return float16_set_sign(float16_zero, float16_is_neg(f16));
+    } else if (float16_is_zero(f16)) {
+        float_raise(float_flag_divbyzero, fpst);
+        return float16_set_sign(float16_infinity, float16_is_neg(f16));
+    } else if (float16_abs(f16) < (1 << 8)) {
+        /* Abs(value) < 2.0^-16 */
+        float_raise(float_flag_overflow | float_flag_inexact, fpst);
+        if (round_to_inf(fpst, f16_sign)) {
+            return float16_set_sign(float16_infinity, f16_sign);
+        } else {
+            return float16_set_sign(float16_maxnorm, f16_sign);
+        }
+    } else if (f16_exp >= 29 && fpst->flush_to_zero) {
+        float_raise(float_flag_underflow, fpst);
+        return float16_set_sign(float16_zero, float16_is_neg(f16));
+    }
+
+    f64_frac = call_recip_estimate(&f16_exp, 29,
+                                   ((uint64_t) f16_frac) << (52 - 10));
+
+    /* result = sign : result_exp<4:0> : fraction<51:42> */
+    f16_val = deposit32(0, 15, 1, f16_sign);
+    f16_val = deposit32(f16_val, 10, 5, f16_exp);
+    f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
+    return make_float16(f16_val);
+}
+
 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
 {
     float_status *fpst = fpstp;
     float32 f32 = float32_squash_input_denormal(input, fpst);
     uint32_t f32_val = float32_val(f32);
-    uint32_t f32_sbit = 0x80000000ULL & f32_val;
-    int32_t f32_exp = extract32(f32_val, 23, 8);
+    bool f32_sign = float32_is_neg(f32);
+    int f32_exp = extract32(f32_val, 23, 8);
     uint32_t f32_frac = extract32(f32_val, 0, 23);
-    float64 f64, r64;
-    uint64_t r64_val;
-    int64_t r64_exp;
-    uint64_t r64_frac;
+    uint64_t f64_frac;
 
     if (float32_is_any_nan(f32)) {
         float32 nan = f32;
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
     } else if (float32_is_zero(f32)) {
         float_raise(float_flag_divbyzero, fpst);
         return float32_set_sign(float32_infinity, float32_is_neg(f32));
-    } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
+    } else if (float32_abs(f32) < (1ULL << 21)) {
         /* Abs(value) < 2.0^-128 */
         float_raise(float_flag_overflow | float_flag_inexact, fpst);
-        if (round_to_inf(fpst, f32_sbit)) {
-            return float32_set_sign(float32_infinity, float32_is_neg(f32));
+        if (round_to_inf(fpst, f32_sign)) {
+            return float32_set_sign(float32_infinity, f32_sign);
         } else {
-            return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
+            return float32_set_sign(float32_maxnorm, f32_sign);
         }
     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
         float_raise(float_flag_underflow, fpst);
         return float32_set_sign(float32_zero, float32_is_neg(f32));
     }
 
+    f64_frac = call_recip_estimate(&f32_exp, 253,
+                                   ((uint64_t) f32_frac) << (52 - 23));
 
-    f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
-    r64 = call_recip_estimate(f64, 253, fpst);
-    r64_val = float64_val(r64);
-    r64_exp = extract64(r64_val, 52, 11);
-    r64_frac = extract64(r64_val, 0, 52);
-
-    /* result = sign : result_exp<7:0> : fraction<51:29>; */
-    return make_float32(f32_sbit |
-                        (r64_exp & 0xff) << 23 |
-                        extract64(r64_frac, 29, 24));
+    /* result = sign : result_exp<7:0> : fraction<51:29> */
+    f32_val = deposit32(0, 31, 1, f32_sign);
+    f32_val = deposit32(f32_val, 23, 8, f32_exp);
+    f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
+    return make_float32(f32_val);
 }
 
 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
     float_status *fpst = fpstp;
     float64 f64 = float64_squash_input_denormal(input, fpst);
     uint64_t f64_val = float64_val(f64);
-    uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
-    int64_t f64_exp = extract64(f64_val, 52, 11);
-    float64 r64;
-    uint64_t r64_val;
-    int64_t r64_exp;
-    uint64_t r64_frac;
+    bool f64_sign = float64_is_neg(f64);
+    int f64_exp = extract64(f64_val, 52, 11);
+    uint64_t f64_frac = extract64(f64_val, 0, 52);
 
     /* Deal with any special cases */
     if (float64_is_any_nan(f64)) {
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
         /* Abs(value) < 2.0^-1024 */
         float_raise(float_flag_overflow | float_flag_inexact, fpst);
-        if (round_to_inf(fpst, f64_sbit)) {
-            return float64_set_sign(float64_infinity, float64_is_neg(f64));
+        if (round_to_inf(fpst, f64_sign)) {
+            return float64_set_sign(float64_infinity, f64_sign);
         } else {
-            return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
+            return float64_set_sign(float64_maxnorm, f64_sign);
         }
     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
         float_raise(float_flag_underflow, fpst);
         return float64_set_sign(float64_zero, float64_is_neg(f64));
     }
 
-    r64 = call_recip_estimate(f64, 2045, fpst);
-    r64_val = float64_val(r64);
-    r64_exp = extract64(r64_val, 52, 11);
-    r64_frac = extract64(r64_val, 0, 52);
+    f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
 
-    /* result = sign : result_exp<10:0> : fraction<51:0> */
-    return make_float64(f64_sbit |
-                        ((r64_exp & 0x7ff) << 52) |
-                        r64_frac);
+    /* result = sign : result_exp<10:0> : fraction<51:0>; */
+    f64_val = deposit64(0, 63, 1, f64_sign);
+    f64_val = deposit64(f64_val, 52, 11, f64_exp);
+    f64_val = deposit64(f64_val, 0, 52, f64_frac);
+    return make_float64(f64_val);
 }
 
 /* The algorithm that must be used to calculate the estimate
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
 
 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
 {
-    float_status *s = fpstp;
-    float64 f64;
+    /* float_status *s = fpstp; */
+    int input, estimate;
 
     if ((a & 0x80000000) == 0) {
         return 0xffffffff;
     }
 
-    f64 = make_float64((0x3feULL << 52)
-                       | ((int64_t)(a & 0x7fffffff) << 21));
+    input = extract32(a, 23, 9);
+    estimate = recip_estimate(input);
 
-    f64 = recip_estimate(f64, s);
-
-    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
+    return deposit32(0, (32 - 9), 9, estimate);
 }
 
 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Now we have added f16 during the re-factoring we can simply call the
helper.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 8 ++++++++
 1 file changed, 8 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

We go with the localised helper.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  1 +
 target/arm/helper-a64.c    | 29 +++++++++++++++++++++++++++++
 target/arm/translate-a64.c |  4 ++++
 3 files changed, 34 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
 DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
 DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
 DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
 DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
 DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 }
 
 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
+float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    uint16_t val16, sbit;
+    int16_t exp;
+
+    if (float16_is_any_nan(a)) {
+        float16 nan = a;
+        if (float16_is_signaling_nan(a, fpst)) {
+            float_raise(float_flag_invalid, fpst);
+            nan = float16_maybe_silence_nan(a, fpst);
+        }
+        if (fpst->default_nan_mode) {
+            nan = float16_default_nan(fpst);
+        }
+        return nan;
+    }
+
+    val16 = float16_val(a);
+    sbit = 0x8000 & val16;
+    exp = extract32(val16, 10, 5);
+
+    if (exp == 0) {
+        return make_float16(deposit32(sbit, 10, 5, 0x1e));
+    } else {
+        return make_float16(deposit32(sbit, 10, 5, ~exp));
+    }
+}
+
 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
 {
     float_status *fpst = fpstp;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
         handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
         return;
     case 0x3d: /* FRECPE */
+    case 0x3f: /* FRECPX */
         break;
     case 0x18: /* FRINTN */
         need_rmode = true;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
         case 0x3d: /* FRECPE */
             gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
             break;
+        case 0x3f: /* FRECPX */
+            gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
+            break;
         case 0x5a: /* FCVTNU */
         case 0x5b: /* FCVTMU */
         case 0x5c: /* FCVTAU */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  1 +
 target/arm/helper-a64.c    | 13 +++++++++++++
 target/arm/translate-a64.c |  5 +++++
 3 files changed, 19 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
 DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
 DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
 DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
     }
     return float16_to_uint16(a, fpst);
 }
+
+/*
+ * Square Root and Reciprocal square root
+ */
+
+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+{
+    float_status *s = fpstp;
+
+    return float16_sqrt(a, s);
+}
+
+
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     case 0x6f: /* FNEG */
         need_fpst = false;
         break;
+    case 0x7f: /* FSQRT (vector) */
+        break;
     default:
         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
             case 0x6f: /* FNEG */
                 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
                 break;
+            case 0x7f: /* FSQRT */
+                gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
+                break;
             default:
                 g_assert_not_reached();
             }
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Much like recpe the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-27-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h |   1 +
 target/arm/helper.c | 221 ++++++++++++++++++++++++----------------------------
 2 files changed, 104 insertions(+), 118 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
 DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
 DEF_HELPER_2(recpe_u32, i32, i32, ptr)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
 /* The algorithm that must be used to calculate the estimate
  * is specified by the ARM ARM.
  */
-static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
+
+static int do_recip_sqrt_estimate(int a)
 {
-    /* These calculations mustn't set any fp exception flags,
-     * so we use a local copy of the fp_status.
-     */
-    float_status dummy_status = *real_fp_status;
-    float_status *s = &dummy_status;
-    float64 q;
-    int64_t q_int;
+    int b, estimate;
 
-    if (float64_lt(a, float64_half, s)) {
-        /* range 0.25 <= a < 0.5 */
-
-        /* a in units of 1/512 rounded down */
-        /* q0 = (int)(a * 512.0);  */
-        q = float64_mul(float64_512, a, s);
-        q_int = float64_to_int64_round_to_zero(q, s);
-
-        /* reciprocal root r */
-        /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
-        q = int64_to_float64(q_int, s);
-        q = float64_add(q, float64_half, s);
-        q = float64_div(q, float64_512, s);
-        q = float64_sqrt(q, s);
-        q = float64_div(float64_one, q, s);
+    assert(128 <= a && a < 512);
+    if (a < 256) {
+        a = a * 2 + 1;
     } else {
-        /* range 0.5 <= a < 1.0 */
-
-        /* a in units of 1/256 rounded down */
-        /* q1 = (int)(a * 256.0); */
-        q = float64_mul(float64_256, a, s);
-        int64_t q_int = float64_to_int64_round_to_zero(q, s);
-
-        /* reciprocal root r */
-        /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
-        q = int64_to_float64(q_int, s);
-        q = float64_add(q, float64_half, s);
-        q = float64_div(q, float64_256, s);
-        q = float64_sqrt(q, s);
-        q = float64_div(float64_one, q, s);
+        a = (a >> 1) << 1;
+        a = (a + 1) * 2;
     }
-    /* r in units of 1/256 rounded to nearest */
-    /* s = (int)(256.0 * r + 0.5); */
+    b = 512;
+    while (a * (b + 1) * (b + 1) < (1 << 28)) {
+        b += 1;
+    }
+    estimate = (b + 1) / 2;
+    assert(256 <= estimate && estimate < 512);
 
-    q = float64_mul(q, float64_256,s );
-    q = float64_add(q, float64_half, s);
-    q_int = float64_to_int64_round_to_zero(q, s);
+    return estimate;
+}
 
-    /* return (double)s / 256.0;*/
-    return float64_div(int64_to_float64(q_int, s), float64_256, s);
+
+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
+{
+    int estimate;
+    uint32_t scaled;
+
+    if (*exp == 0) {
+        while (extract64(frac, 51, 1) == 0) {
+            frac = frac << 1;
+            *exp -= 1;
+        }
+        frac = extract64(frac, 0, 51) << 1;
+    }
+
+    if (*exp & 1) {
+        /* scaled = UInt('01':fraction<51:45>) */
+        scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
+    } else {
+        /* scaled = UInt('1':fraction<51:44>) */
+        scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
+    }
+    estimate = do_recip_sqrt_estimate(scaled);
+
+    *exp = (exp_off - *exp) / 2;
+    return extract64(estimate, 0, 8) << 44;
+}
+
+float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+{
+    float_status *s = fpstp;
+    float16 f16 = float16_squash_input_denormal(input, s);
+    uint16_t val = float16_val(f16);
+    bool f16_sign = float16_is_neg(f16);
+    int f16_exp = extract32(val, 10, 5);
+    uint16_t f16_frac = extract32(val, 0, 10);
+    uint64_t f64_frac;
+
+    if (float16_is_any_nan(f16)) {
+        float16 nan = f16;
+        if (float16_is_signaling_nan(f16, s)) {
+            float_raise(float_flag_invalid, s);
+            nan = float16_maybe_silence_nan(f16, s);
+        }
+        if (s->default_nan_mode) {
+            nan =  float16_default_nan(s);
+        }
+        return nan;
+    } else if (float16_is_zero(f16)) {
+        float_raise(float_flag_divbyzero, s);
+        return float16_set_sign(float16_infinity, f16_sign);
+    } else if (f16_sign) {
+        float_raise(float_flag_invalid, s);
+        return float16_default_nan(s);
+    } else if (float16_is_infinity(f16)) {
+        return float16_zero;
+    }
+
+    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
+     * preserving the parity of the exponent.  */
+
+    f64_frac = ((uint64_t) f16_frac) << (52 - 10);
+
+    f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
+
+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
+    val = deposit32(0, 15, 1, f16_sign);
+    val = deposit32(val, 10, 5, f16_exp);
+    val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
+    return make_float16(val);
 }
 
 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
     float_status *s = fpstp;
     float32 f32 = float32_squash_input_denormal(input, s);
     uint32_t val = float32_val(f32);
-    uint32_t f32_sbit = 0x80000000 & val;
-    int32_t f32_exp = extract32(val, 23, 8);
+    uint32_t f32_sign = float32_is_neg(f32);
+    int f32_exp = extract32(val, 23, 8);
     uint32_t f32_frac = extract32(val, 0, 23);
     uint64_t f64_frac;
-    uint64_t val64;
-    int result_exp;
-    float64 f64;
 
     if (float32_is_any_nan(f32)) {
         float32 nan = f32;
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
      * preserving the parity of the exponent.  */
 
     f64_frac = ((uint64_t) f32_frac) << 29;
-    if (f32_exp == 0) {
-        while (extract64(f64_frac, 51, 1) == 0) {
-            f64_frac = f64_frac << 1;
-            f32_exp = f32_exp-1;
-        }
-        f64_frac = extract64(f64_frac, 0, 51) << 1;
-    }
 
-    if (extract64(f32_exp, 0, 1) == 0) {
-        f64 = make_float64(((uint64_t) f32_sbit) << 32
-                           | (0x3feULL << 52)
-                           | f64_frac);
-    } else {
-        f64 = make_float64(((uint64_t) f32_sbit) << 32
-                           | (0x3fdULL << 52)
-                           | f64_frac);
-    }
+    f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
 
-    result_exp = (380 - f32_exp) / 2;
-
-    f64 = recip_sqrt_estimate(f64, s);
-
-    val64 = float64_val(f64);
-
-    val = ((result_exp & 0xff) << 23)
-        | ((val64 >> 29)  & 0x7fffff);
+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
+    val = deposit32(0, 31, 1, f32_sign);
+    val = deposit32(val, 23, 8, f32_exp);
+    val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
     return make_float32(val);
 }
 
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
     float_status *s = fpstp;
     float64 f64 = float64_squash_input_denormal(input, s);
     uint64_t val = float64_val(f64);
-    uint64_t f64_sbit = 0x8000000000000000ULL & val;
-    int64_t f64_exp = extract64(val, 52, 11);
+    bool f64_sign = float64_is_neg(f64);
+    int f64_exp = extract64(val, 52, 11);
     uint64_t f64_frac = extract64(val, 0, 52);
-    int64_t result_exp;
-    uint64_t result_frac;
 
     if (float64_is_any_nan(f64)) {
         float64 nan = f64;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         return float64_zero;
     }
 
-    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
-     * preserving the parity of the exponent.  */
+    f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
 
-    if (f64_exp == 0) {
-        while (extract64(f64_frac, 51, 1) == 0) {
-            f64_frac = f64_frac << 1;
-            f64_exp = f64_exp - 1;
-        }
-        f64_frac = extract64(f64_frac, 0, 51) << 1;
-    }
-
-    if (extract64(f64_exp, 0, 1) == 0) {
-        f64 = make_float64(f64_sbit
-                           | (0x3feULL << 52)
-                           | f64_frac);
-    } else {
-        f64 = make_float64(f64_sbit
-                           | (0x3fdULL << 52)
-                           | f64_frac);
-    }
-
-    result_exp = (3068 - f64_exp) / 2;
-
-    f64 = recip_sqrt_estimate(f64, s);
-
-    result_frac = extract64(float64_val(f64), 0, 52);
-
-    return make_float64(f64_sbit |
-                        ((result_exp & 0x7ff) << 52) |
-                        result_frac);
+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
+    val = deposit64(0, 61, 1, f64_sign);
+    val = deposit64(val, 52, 11, f64_exp);
+    val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
+    return make_float64(val);
 }
 
 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
 
 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
 {
-    float_status *fpst = fpstp;
-    float64 f64;
+    int estimate;
 
     if ((a & 0xc0000000) == 0) {
         return 0xffffffff;
     }
 
-    if (a & 0x80000000) {
-        f64 = make_float64((0x3feULL << 52)
-                           | ((uint64_t)(a & 0x7fffffff) << 21));
-    } else { /* bits 31-30 == '01' */
-        f64 = make_float64((0x3fdULL << 52)
-                           | ((uint64_t)(a & 0x3fffffff) << 22));
-    }
+    estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
 
-    f64 = recip_sqrt_estimate(f64, fpst);
-
-    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
+    return deposit32(0, 23, 9, estimate);
 }
 
 /* VFPv4 fused multiply-accumulate */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 7 +++++++
 1 file changed, 7 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

Only one half-precision instruction has been added to this group.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-29-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 35 +++++++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
  *   MVNI - move inverted (shifted) imm into register
  *   ORR  - bitwise OR of (shifted) imm with register
  *   BIC  - bitwise clear of (shifted) imm with register
+ * With ARMv8.2 we also have:
+ *   FMOV half-precision
  */
 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
     uint64_t imm = 0;
 
     if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
-        unallocated_encoding(s);
-        return;
+        /* Check for FMOV (vector, immediate) - half-precision */
+        if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
+            unallocated_encoding(s);
+            return;
+        }
     }
 
     if (!fp_access_check(s)) {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
                     imm |= 0x4000000000000000ULL;
                 }
             } else {
-                imm = (abcdefgh & 0x3f) << 19;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x80000000;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3e000000;
+                if (o2) {
+                    /* FMOV (vector, immediate) - half-precision */
+                    imm = vfp_expand_imm(MO_16, abcdefgh);
+                    /* now duplicate across the lanes */
+                    imm = bitfield_replicate(imm, 16);
                 } else {
-                    imm |= 0x40000000;
+                    imm = (abcdefgh & 0x3f) << 19;
+                    if (abcdefgh & 0x80) {
+                        imm |= 0x80000000;
+                    }
+                    if (abcdefgh & 0x40) {
+                        imm |= 0x3e000000;
+                    } else {
+                        imm |= 0x40000000;
+                    }
+                    imm |= (imm << 32);
                 }
-                imm |= (imm << 32);
             }
         }
         break;
+    default:
+        fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
+        g_assert_not_reached();
     }
 
     if (cmode_3_1 != 7 && is_neg) {
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

I only needed to do a little light re-factoring to support the
half-precision helpers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 26 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
     case 0xf: /* FMAXP */
     case 0x2c: /* FMINNMP */
     case 0x2f: /* FMINP */
-        /* FP op, size[0] is 32 or 64 bit */
+        /* FP op, size[0] is 32 or 64 bit*/
         if (!u) {
-            unallocated_encoding(s);
-            return;
+            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+                unallocated_encoding(s);
+                return;
+            } else {
+                size = MO_16;
+            }
+        } else {
+            size = extract32(size, 0, 1) ? MO_64 : MO_32;
         }
+
         if (!fp_access_check(s)) {
             return;
         }
 
-        size = extract32(size, 0, 1) ? 3 : 2;
-        fpst = get_fpstatus_ptr(false);
+        fpst = get_fpstatus_ptr(size == MO_16);
         break;
     default:
         unallocated_encoding(s);
         return;
     }
 
-    if (size == 3) {
+    if (size == MO_64) {
         TCGv_i64 tcg_op1 = tcg_temp_new_i64();
         TCGv_i64 tcg_op2 = tcg_temp_new_i64();
         TCGv_i64 tcg_res = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
         TCGv_i32 tcg_res = tcg_temp_new_i32();
 
-        read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
-        read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
+        read_vec_element_i32(s, tcg_op1, rn, 0, size);
+        read_vec_element_i32(s, tcg_op2, rn, 1, size);
 
-        switch (opcode) {
-        case 0xc: /* FMAXNMP */
-            gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xd: /* FADDP */
-            gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xf: /* FMAXP */
-            gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x2c: /* FMINNMP */
-            gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x2f: /* FMINP */
-            gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        default:
-            g_assert_not_reached();
+        if (size == MO_16) {
+            switch (opcode) {
+            case 0xc: /* FMAXNMP */
+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xd: /* FADDP */
+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xf: /* FMAXP */
+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2c: /* FMINNMP */
+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2f: /* FMINP */
+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+        } else {
+            switch (opcode) {
+            case 0xc: /* FMAXNMP */
+                gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xd: /* FADDP */
+                gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xf: /* FMAXP */
+                gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2c: /* FMINNMP */
+                gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2f: /* FMINP */
+                gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                g_assert_not_reached();
+            }
         }
 
         write_fp_sreg(s, rd, tcg_res);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This covers the encoding group:

Advanced SIMD scalar three same FP16

As all the helpers are already there it is simply a case of calling the
existing helpers in the scalar context.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-31-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

This includes FMOV, FABS, FNEG, FSQRT and  FRINT[NPMZAXI]. We re-use
existing helpers to achieve this.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-32-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(t_true);
 }
 
+/* Floating-point data-processing (1 source) - half precision */
+static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
+{
+    TCGv_ptr fpst = NULL;
+    TCGv_i32 tcg_op = tcg_temp_new_i32();
+    TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+    read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
+
+    switch (opcode) {
+    case 0x0: /* FMOV */
+        tcg_gen_mov_i32(tcg_res, tcg_op);
+        break;
+    case 0x1: /* FABS */
+        tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
+        break;
+    case 0x2: /* FNEG */
+        tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+        break;
+    case 0x3: /* FSQRT */
+        gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
+        break;
+    case 0x8: /* FRINTN */
+    case 0x9: /* FRINTP */
+    case 0xa: /* FRINTM */
+    case 0xb: /* FRINTZ */
+    case 0xc: /* FRINTA */
+    {
+        TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+        fpst = get_fpstatus_ptr(true);
+
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
+
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+        tcg_temp_free_i32(tcg_rmode);
+        break;
+    }
+    case 0xe: /* FRINTX */
+        fpst = get_fpstatus_ptr(true);
+        gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
+        break;
+    case 0xf: /* FRINTI */
+        fpst = get_fpstatus_ptr(true);
+        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
+        break;
+    default:
+        abort();
+    }
+
+    write_fp_sreg(s, rd, tcg_res);
+
+    if (fpst) {
+        tcg_temp_free_ptr(fpst);
+    }
+    tcg_temp_free_i32(tcg_op);
+    tcg_temp_free_i32(tcg_res);
+}
+
 /* Floating-point data-processing (1 source) - single precision */
 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
 
             handle_fp_1src_double(s, opcode, rd, rn);
             break;
+        case 3:
+            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+                unallocated_encoding(s);
+                return;
+            }
+
+            if (!fp_access_check(s)) {
+                return;
+            }
+
+            handle_fp_1src_half(s, opcode, rd, rn);
+            break;
         default:
             unallocated_encoding(s);
         }
-- 
2.16.2

From: Alistair Francis <alistair.francis@xilinx.com>

I am leaving Xilinx, so to avoid having an email address that bounces
update my maintainer address to point to my personal email address.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/misc/arm_sysctl.c
 
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/xilinx_*
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/zynq*
 X: hw/ssi/xilinx_*
 
 Xilinx ZynqMP
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 L: qemu-arm@nongnu.org
 S: Maintained
@@ -XXX,XX +XXX,XX @@ T: git git://github.com/bonzini/qemu.git scsi-next
 
 SSI
 M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/ssi/*
 F: hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
 F: tests/m25p80-test.c
 
 Xilinx SPI
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
 S: Maintained
 F: hw/ssi/xilinx_*
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/net/eepro100.c
 
 Generic Loader
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/core/generic-loader.c
 F: include/hw/core/generic-loader.h
@@ -XXX,XX +XXX,XX @@ F: tests/qmp-test.c
 T: git git://repo.or.cz/qemu/armbru.git qapi-next
 
 Register API
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/core/register.c
 F: include/hw/register.h
-- 
2.16.2

The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

----------------------------------------------------------------
target-arm queue:
 * more MVE instructions
 * hw/gpio/gpio_pwr: use shutdown function for reboot
 * target/arm: Check NaN mode before silencing NaN
 * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 * hw/arm: Add basic power management to raspi.
 * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

----------------------------------------------------------------
Joe Komlodi (1):
      target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):
      hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):
      hw/arm: Add basic power management to raspi.

Patrick Venture (2):
      docs/system/arm: Add quanta-q7l1-bmc reference
      docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):
      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Make asimd_imm_const() public
      target/arm: Use asimd_imm_const for A64 decode
      target/arm: Use dup_const() instead of bitfield_replicate()
      target/arm: Implement MVE logical immediate insns
      target/arm: Implement MVE vector shift left by immediate insns
      target/arm: Implement MVE vector shift right by immediate insns
      target/arm: Implement MVE VSHLL
      target/arm: Implement MVE VSRI, VSLI
      target/arm: Implement MVE VSHRN, VRSHRN
      target/arm: Implement MVE saturating narrowing shifts
      target/arm: Implement MVE VSHLC
      target/arm: Implement MVE VADDLV
      target/arm: Implement MVE long shifts by immediate
      target/arm: Implement MVE long shifts by register
      target/arm: Implement MVE shifts by immediate
      target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):
      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst             |   1 +
 docs/system/arm/nuvoton.rst            |   5 +-
 include/hw/arm/bcm2835_peripherals.h   |   3 +-
 include/hw/misc/bcm2835_powermgt.h     |  29 ++
 target/arm/helper-mve.h                | 108 +++++++
 target/arm/translate.h                 |  41 +++
 target/arm/mve.decode                  | 177 ++++++++++-
 target/arm/t32.decode                  |  71 ++++-
 hw/arm/bcm2835_peripherals.c           |  13 +-
 hw/gpio/gpio_pwr.c                     |   2 +-
 hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
 target/arm/helper-a64.c                |  12 +-
 target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c             |  86 +-----
 target/arm/translate-mve.c             | 261 +++++++++++++++-
 target/arm/translate-neon.c            |  81 -----
 target/arm/translate.c                 | 327 +++++++++++++++++++-
 target/arm/vfp_helper.c                |  24 +-
 hw/misc/meson.build                    |   1 +
 tests/acceptance/boot_linux_console.py |  43 +++
 20 files changed, 1760 insertions(+), 209 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-=====================================================
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+================================================================
 
 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
 Hyperscale applications. The following machines are based on this chip :
 
+- ``quanta-gbs-bmc``    Quanta GBS server BMC
 - ``quanta-gsj``        Quanta GSJ server BMC
 
 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
-- 
2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
 moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   3 +-
 include/hw/misc/bcm2835_powermgt.h   |  29 +++++
 hw/arm/bcm2835_peripherals.c         |  13 ++-
 hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
 hw/misc/meson.build                  |   1 +
 5 files changed, 204 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_powermgt.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
 #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     BCM2835MphiState mphi;
     UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
-    UnimplementedDeviceState powermgt;
+    BCM2835PowerMgtState powermgt;
     BCM2835CprmanState cprman;
     PL011State uart0;
     BCM2835AuxState aux;
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_powermgt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_POWERMGT_H
+#define BCM2835_POWERMGT_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
+
+struct BCM2835PowerMgtState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+
+    uint32_t rstc;
+    uint32_t rsts;
+    uint32_t wdog;
+};
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
 
     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                    OBJECT(&s->gpu_bus_mr));
+
+    /* Power Management */
+    object_initialize_child(obj, "powermgt", &s->powermgt,
+                            TYPE_BCM2835_POWERMGT);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    /* Power Management */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+
     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/bcm2835_powermgt.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
+
+#define PASSWORD 0x5a000000
+#define PASSWORD_MASK 0xff000000
+
+#define R_RSTC 0x1c
+#define V_RSTC_RESET 0x20
+#define R_RSTS 0x20
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
+#define R_WDOG 0x24
+
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+    uint32_t res = 0;
+
+    switch (offset) {
+    case R_RSTC:
+        res = s->rstc;
+        break;
+    case R_RSTS:
+        res = s->rsts;
+        break;
+    case R_WDOG:
+        res = s->wdog;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        res = 0;
+        break;
+    }
+
+    return res;
+}
+
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+
+    if ((value & PASSWORD_MASK) != PASSWORD) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
+                      " at offset 0x%08"HWADDR_PRIx"\n",
+                      value, offset);
+        return;
+    }
+
+    value = value & ~PASSWORD_MASK;
+
+    switch (offset) {
+    case R_RSTC:
+        s->rstc = value;
+        if (value & V_RSTC_RESET) {
+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+            } else {
+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            }
+        }
+        break;
+    case R_RSTS:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: RSTS\n");
+        s->rsts = value;
+        break;
+    case R_WDOG:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: WDOG\n");
+        s->wdog = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps bcm2835_powermgt_ops = {
+    .read = bcm2835_powermgt_read,
+    .write = bcm2835_powermgt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_powermgt = {
+    .name = TYPE_BCM2835_POWERMGT,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void bcm2835_powermgt_init(Object *obj)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+
+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+                          TYPE_BCM2835_POWERMGT, 0x200);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_powermgt_reset(DeviceState *dev)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+
+    /* https://elinux.org/BCM2835_registers#PM */
+    s->rstc = 0x00000102;
+    s->rsts = 0x00001000;
+    s->wdog = 0x00000000;
+}
+
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = bcm2835_powermgt_reset;
+    dc->vmsd = &vmstate_bcm2835_powermgt;
+}
+
+static TypeInfo bcm2835_powermgt_info = {
+    .name          = TYPE_BCM2835_POWERMGT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835PowerMgtState),
+    .class_init    = bcm2835_powermgt_class_init,
+    .instance_init = bcm2835_powermgt_init,
+};
+
+static void bcm2835_powermgt_register_types(void)
+{
+    type_register_static(&bcm2835_powermgt_info);
+}
+
+type_init(bcm2835_powermgt_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
   'bcm2835_rng.c',
   'bcm2835_thermal.c',
   'bcm2835_cprman.c',
+  'bcm2835_powermgt.c',
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
  console: [    0.000000] Booting Linux on physical CPU 0xf00
  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
  console: [    0.000000] CPU: div instructions available: patching division code
  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
  ...
  console: Boot successful.
  console: cat /proc/cpuinfo
  console: / # cat /proc/cpuinfo
  ...
  console: processor      : 3
  console: model name     : ARMv7 Processor rev 5 (v7l)
  console: BogoMIPS       : 125.00
  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  console: CPU implementer        : 0x41
  console: CPU architecture: 7
  console: CPU variant    : 0x0
  console: CPU part       : 0xc07
  console: CPU revision   : 5
  console: Hardware       : BCM2835
  console: Revision       : 0000
  console: Serial         : 0000000000000000
  console: cat /proc/iomem
  console: / # cat /proc/iomem
  console: 00000000-3bffffff : System RAM
  console: 00008000-00afffff : Kernel code
  console: 00c00000-00d468ef : Kernel data
  console: 3f006000-3f006fff : dwc_otg
  console: 3f007000-3f007eff : /soc/dma@7e007000
  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
  console: 3f100000-3f100027 : /soc/watchdog@7e100000
  console: 3f101000-3f102fff : /soc/cprman@7e101000
  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
  PASS (24.59 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
  JOB TIME   : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@
 from avocado import skip
 from avocado import skipUnless
 from avocado_qemu import Test
+from avocado_qemu import exec_command
 from avocado_qemu import exec_command_and_wait_for_pattern
 from avocado_qemu import interrupt_interactive_console_until_pattern
 from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
         """
         self.do_test_arm_raspi2(0)
 
+    def test_arm_raspi2_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:raspi2
+        """
+        deb_url = ('http://archive.raspberrypi.org/debian/'
+                   'pool/main/r/raspberrypi-firmware/'
+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
+
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv7a.cpio.gz')
+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+                               'panic=-1 noreboot ' +
+                               'dwc_otg.fiq_fsm_enable=0')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'BCM2835')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                '/soc/cprman@7e101000')
+        exec_command(self, 'halt')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_arm_exynos4210_initrd(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.c | 12 +++++++++---
 target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
         float16 nan = a;
         if (float16_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         float32 nan = a;
         if (float32_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         float64 nan = a;
         if (float64_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float64_default_nan(fpst);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(f16, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(f32, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(f64, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float16_silence_nan(f16, s);
+            if (!s->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float32_silence_nan(f32, s);
+            if (!s->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float64_silence_nan(f64, s);
+            if (!s->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float64_default_nan(s);
-- 
2.20.1

From: Maxim Uvarov <maxim.uvarov@linaro.org>

qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/gpio_pwr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/gpio_pwr.c
+++ b/hw/gpio/gpio_pwr.c
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
 static void gpio_pwr_shutdown(void *opaque, int n, int level)
 {
     if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
     }
 }
 
-- 
2.20.1

In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector.  This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
     }
 }
 
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+                    unsigned msize)
 {
     TCGv_i32 addr;
     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
         return true;
     }
 
-    offset = a->imm << a->size;
+    offset = a->imm << msize;
     if (!a->a) {
         offset = -offset;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
         { NULL, NULL }
     };
-    return do_ldst(s, a, ldstfns[a->size][a->l]);
+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 }
 
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
     {                                                           \
         static MVEGenLdStFn * const ldstfns[2][2] = {           \
             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
             { NULL, gen_helper_mve_##ULD },                     \
         };                                                      \
-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
     }
 
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
 
 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 {
-- 
2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
 * the 32x32 multiply of elements was being done as 32x32->32,
   not 32x32->64
 * we were incorrectly maintaining the accumulator in its full
   72-bit form across all 4 beats of the insn; in the pseudocode
   it is squashed back into the 64 bits of the RdaHi:RdaLo
   registers after each beat

In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
---
 target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/int128.h"
 #include "cpu.h"
 #include "internals.h"
 #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
 
 /*
- * Rounding multiply add long dual accumulate high: we must keep
- * a 72-bit internal accumulator value and return the top 64 bits.
+ * Rounding multiply add long dual accumulate high. In the pseudocode
+ * this is implemented with a 72-bit internal accumulator value of which
+ * the top 64 bits are returned. We optimize this to avoid having to
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
+ * is squashed back into 64-bits after each beat.
  */
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                     void *vm, uint64_t a)               \
     {                                                                   \
         uint16_t mask = mve_element_mask(env);                          \
         unsigned e;                                                     \
         TYPE *n = vn, *m = vm;                                          \
-        Int128 acc = int128_lshift(TO128(a), 8);                        \
-        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
             if (mask & 1) {                                             \
+                LTYPE mul;                                              \
                 if (e & 1) {                                            \
-                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
-                                            m[H##ESIZE(e)]));           \
+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
+                    if (SUB) {                                          \
+                        mul = -mul;                                     \
+                    }                                                   \
                 } else {                                                \
-                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
-                                             m[H##ESIZE(e)]));          \
+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                 }                                                       \
-                acc = int128_add(acc, int128_make64(1 << 7));           \
+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
+                a += mul;                                               \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \
-        return int128_getlo(int128_rshift(acc, 8));                     \
+        return a;                                                       \
     }
 
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
 
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
 
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
 
 /* Vector add across vector */
 #define DO_VADDV(OP, ESIZE, TYPE)                               \
-- 
2.20.1

The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE.  Move the implementation to translate.c, with a
prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
---
 target/arm/translate.h      | 16 ++++++++++
 target/arm/translate-neon.c | 63 -------------------------------------
 target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
     return opc | s->be_data;
 }
 
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
 DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
 DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
-    /*
-     * Expand the encoded constant.
-     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-     * We choose to not special-case this and will behave as if a
-     * valid constant encoding of 0 had been given.
-     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
-     */
-    switch (cmode) {
-    case 0: case 1:
-        /* no-op */
-        break;
-    case 2: case 3:
-        imm <<= 8;
-        break;
-    case 4: case 5:
-        imm <<= 16;
-        break;
-    case 6: case 7:
-        imm <<= 24;
-        break;
-    case 8: case 9:
-        imm |= imm << 16;
-        break;
-    case 10: case 11:
-        imm = (imm << 8) | (imm << 24);
-        break;
-    case 12:
-        imm = (imm << 8) | 0xff;
-        break;
-    case 13:
-        imm = (imm << 16) | 0xffff;
-        break;
-    case 14:
-        if (op) {
-            /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
-             */
-            uint64_t imm64 = 0;
-            int n;
-
-            for (n = 0; n < 8; n++) {
-                if (imm & (1 << n)) {
-                    imm64 |= (0xffULL << (n * 8));
-                }
-            }
-            return imm64;
-        }
-        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-        break;
-    case 15:
-        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-        break;
-    }
-    if (op) {
-        imm = ~imm;
-    }
-    return dup_const(MO_32, imm);
-}
-
 static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                         GVecGen2iFn *fn)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
 /* Generate a label used for skipping this instruction */
 void arm_gen_condlabel(DisasContext *s)
 {
-- 
2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
 target/arm/translate.h     |  3 +-
 target/arm/translate-a64.c | 86 ++++----------------------------------
 target/arm/translate.c     | 17 +++++++-
 3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  * VMVN and VBIC (when cmode < 14 && op == 1).
  *
  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
  *
  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int cmode = extract32(insn, 12, 4);
-    int cmode_3_1 = extract32(cmode, 1, 3);
-    int cmode_0 = extract32(cmode, 0, 1);
     int o2 = extract32(insn, 11, 1);
     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
     bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* See AdvSIMDExpandImm() in ARM ARM */
-    switch (cmode_3_1) {
-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-    {
-        int shift = cmode_3_1 * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 32);
-        break;
-    }
-    case 4: /* Replicate(Zeros(8):imm8, 4) */
-    case 5: /* Replicate(imm8:Zeros(8), 4) */
-    {
-        int shift = (cmode_3_1 & 0x1) * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 16);
-        break;
-    }
-    case 6:
-        if (cmode_0) {
-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
-            imm = (abcdefgh << 16) | 0xffff;
-        } else {
-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-            imm = (abcdefgh << 8) | 0xff;
-        }
-        imm = bitfield_replicate(imm, 32);
-        break;
-    case 7:
-        if (!cmode_0 && !is_neg) {
-            imm = bitfield_replicate(abcdefgh, 8);
-        } else if (!cmode_0 && is_neg) {
-            int i;
-            imm = 0;
-            for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
-                    imm |= 0xffULL << (i * 8);
-                }
-            }
-        } else if (cmode_0) {
-            if (is_neg) {
-                imm = (abcdefgh & 0x3f) << 48;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x8000000000000000ULL;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3fc0000000000000ULL;
-                } else {
-                    imm |= 0x4000000000000000ULL;
-                }
-            } else {
-                if (o2) {
-                    /* FMOV (vector, immediate) - half-precision */
-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-                    /* now duplicate across the lanes */
-                    imm = bitfield_replicate(imm, 16);
-                } else {
-                    imm = (abcdefgh & 0x3f) << 19;
-                    if (abcdefgh & 0x80) {
-                        imm |= 0x80000000;
-                    }
-                    if (abcdefgh & 0x40) {
-                        imm |= 0x3e000000;
-                    } else {
-                        imm |= 0x40000000;
-                    }
-                    imm |= (imm << 32);
-                }
-            }
-        }
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (cmode_3_1 != 7 && is_neg) {
-        imm = ~imm;
+    if (cmode == 15 && o2 && !is_neg) {
+        /* FMOV (vector, immediate) - half-precision */
+        imm = vfp_expand_imm(MO_16, abcdefgh);
+        /* now duplicate across the lanes */
+        imm = bitfield_replicate(imm, 16);
+    } else {
+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
 
     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
     case 14:
         if (op) {
             /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
+             * This and cmode == 15 op == 1 are the only cases where
+             * the top and bottom 32 bits of the encoded constant differ.
              */
             uint64_t imm64 = 0;
             int n;
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
         imm |= (imm << 8) | (imm << 16) | (imm << 24);
         break;
     case 15:
+        if (op) {
+            /* Reserved encoding for AArch32; valid for AArch64 */
+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+            if (imm & 0x80) {
+                imm64 |= 0x8000000000000000ULL;
+            }
+            if (imm & 0x40) {
+                imm64 |= 0x3fc0000000000000ULL;
+            } else {
+                imm64 |= 0x4000000000000000ULL;
+            }
+            return imm64;
+        }
         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
         break;
-- 
2.20.1

Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         /* FMOV (vector, immediate) - half-precision */
         imm = vfp_expand_imm(MO_16, abcdefgh);
         /* now duplicate across the lanes */
-        imm = bitfield_replicate(imm, 16);
+        imm = dup_const(MO_16, imm);
     } else {
         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
-- 
2.20.1

Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  4 +++
 target/arm/mve.decode      | 17 +++++++++++++
 target/arm/mve_helper.c    | 24 ++++++++++++++++++
 target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.

The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 16 +++++++++++
 target/arm/mve.decode      | 23 +++++++++++++++
 target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 &2op qd qm qn size
 &2scalar qd qn rm size
 &1imm qd imm cmode op
+&2shift qd qm shift size
 
 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
 # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+
 # Vector loads and stores
 
 # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 # So we have a single decode line and check the cmode/op in the
 # trans function.
 Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+
+# Shifts by immediate
+
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
 #define DO_UQRSHL_OP(N, M, satp) \
     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
+#define DO_SUQSHL_OP(N, M, satp) \
+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
 
 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
 DO_VADDV(vaddvub, 1, uint8_t)
 DO_VADDV(vaddvuh, 2, uint16_t)
 DO_VADDV(vaddvuw, 4, uint32_t)
+
+/* Shifts by immediate */
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift), mask);         \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        bool qc = false;                                        \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            bool sat = false;                                   \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
+            qc |= sat & mask & 1;                               \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+/* provide unsigned 2-op shift helpers for all sizes */
+#define DO_2SHIFT_U(OP, FN)                     \
+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
+
+#define DO_2SHIFT_SAT_U(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
+#define DO_2SHIFT_SAT_S(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
+
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     }
     return do_1imm(s, a, fn);
 }
+
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    TCGv_ptr qd, qm;
+    int shift = a->shift;
+
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
+        !fn) {
+        return false;
+    }
+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * When we handle a right shift insn using a left-shift helper
+     * which permits a negative shift count to indicate a right-shift,
+     * we must negate the shift count.
+     */
+    if (negateshift) {
+        shift = -shift;
+    }
+
+    qd = mve_qreg_ptr(a->qd);
+    qm = mve_qreg_ptr(a->qm);
+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+    tcg_temp_free_ptr(qd);
+    tcg_temp_free_ptr(qm);
+    mve_update_eci(s);
+    return true;
+}
+
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+            gen_helper_mve_##FN##w,                             \
+            NULL,                                               \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+    }
+
+DO_2SHIFT(VSHLI, vshli_u, false)
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
-- 
2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI.  As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
---
 target/arm/helper-mve.h     | 12 ++++++++++++
 target/arm/translate.h      | 20 ++++++++++++++++++++
 target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
 target/arm/mve_helper.c     |  7 +++++++
 target/arm/translate-mve.c  |  5 +++++
 target/arm/translate-neon.c | 18 ------------------
 6 files changed, 72 insertions(+), 18 deletions(-)

Implement the MVE VHLL (vector shift left long) insn.  This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  9 +++++++
 target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
 target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
 target/arm/translate-mve.c | 15 +++++++++++
 4 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+# VSHLL encoding T2 where shift == esize
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=0 shift=8
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=1 shift=16
+
 # Right shifts are encoded as N - shift, where N is the element size in bits.
 %rshift_i5  16:5 !function=rsub_32
 %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 
-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+# overlaps what would be size=0b11 VMULH/VRMULH
+{
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 
-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
 
 VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+
+/*
+ * Long shifts taking half-sized inputs from top or bottom of the input
+ * vector and producing a double-width result. ESIZE, TYPE are for
+ * the input, and LESIZE, LTYPE for the output.
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+ * because the long shift is strictly left-only.
+ */
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+                                void *vm, uint32_t shift)               \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *m = vm;                                                   \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        assert(shift <= 16);                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
+#define DO_VSHLL_ALL(OP, TOP)                                \
+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+
+DO_VSHLL_ALL(vshllb, false)
+DO_VSHLL_ALL(vshllt, true)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
 DO_2SHIFT(VSHRI_U, vshli_u, true)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+
+#define DO_VSHLL(INSN, FN)                                      \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], false);            \
+    }
+
+DO_VSHLL(VSHLL_BS, vshllbs)
+DO_VSHLL(VSHLL_BU, vshllbu)
+DO_VSHLL(VSHLL_TS, vshllts)
+DO_VSHLL(VSHLL_TU, vshlltu)
-- 
2.20.1

Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  8 ++++++++
 target/arm/mve.decode      |  9 ++++++++
 target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  3 +++
 4 files changed, 62 insertions(+)

Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.

do_urshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 11 +++++++++++
 target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 15 ++++++++++++++
 4 files changed, 76 insertions(+)

Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.

do_srshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  30 +++++++++++
 target/arm/mve.decode      |  28 ++++++++++
 target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  12 +++++
 4 files changed, 174 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
     }
 }
 
+static inline int64_t do_srshr(int64_t x, unsigned sh)
+{
+    if (likely(sh < 64)) {
+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+    } else {
+        /* Rounding the sign bit always produces 0. */
+        return 0;
+    }
+}
+
 DO_VSHRN_ALL(vshrn, DO_SHR)
 DO_VSHRN_ALL(vrshrn, do_urshr)
+
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
+                                 bool *satp)
+{
+    if (val > max) {
+        *satp = true;
+        return max;
+    } else if (val < min) {
+        *satp = true;
+        return min;
+    } else {
+        return val;
+    }
+}
+
+/* Saturating narrowing right shifts */
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        LTYPE *m = vm;                                          \
+        TYPE *d = vd;                                           \
+        uint16_t mask = mve_element_mask(env);                  \
+        bool qc = false;                                        \
+        unsigned le;                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+            bool sat = false;                                   \
+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
+
+#define DO_SHRN_SB(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+#define DO_SHRN_UB(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+#define DO_SHRUN_B(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+
+#define DO_SHRN_SH(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+#define DO_SHRN_UH(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+#define DO_SHRUN_H(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+
+#define DO_RSHRN_SB(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+#define DO_RSHRN_UB(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
+#define DO_RSHRUN_B(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
+
+#define DO_RSHRN_SH(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
+#define DO_RSHRN_UH(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
+#define DO_RSHRUN_H(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
+
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
+
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
 DO_2SHIFT_N(VSHRNT, vshrnt)
 DO_2SHIFT_N(VRSHRNB, vrshrnb)
 DO_2SHIFT_N(VRSHRNT, vrshrnt)
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-- 
2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  2 ++
 target/arm/mve.decode      |  2 ++
 target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+)

Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  3 ++
 target/arm/mve.decode      |  6 +++-
 target/arm/mve_helper.c    | 19 ++++++++++++
 target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 1 deletion(-)

The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers.  They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 28 +++++++++++++
 target/arm/mve_helper.c | 10 +++++
 target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)

Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  6 +++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 16 +++++--
 target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 
 /**
  * arm_tbflags_from_tb:
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
 &mcrr            !extern cp opc1 crm rt rt2
 
 &mve_shl_ri      rdalo rdahi shim
+&mve_shl_rr      rdalo rdahi rm
 
 # rdahi: bits [3:1] from insn, bit 0 is 1
 # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
 
 @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 
 {
   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+
+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
   ]
 
   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+
+  # v8.1M CSEL and friends
+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 }
 {
   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
 }
 RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 
-# v8.1M CSEL and friends
-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-
 # Data-processing (register-shifted register)
 
 MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
     return rdm;
 }
 
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
+}
+
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
+}
+
 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 }
+
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
+                                    bool round, uint32_t *sat)
+{
+    if (shift <= -48) {
+        /* Rounding the sign bit always produces 0. */
+        if (round) {
+            return 0;
+        }
+        return src >> 63;
+    } else if (shift < 0) {
+        if (round) {
+            src >>= -shift - 1;
+            return (src >> 1) + (src & 1);
+        }
+        return src >> -shift;
+    } else if (shift < 48) {
+        int64_t val = src << shift;
+        int64_t extval = sextract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return (1ULL << 47) - (src >= 0);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
+                                     bool round, uint32_t *sat)
+{
+    uint64_t val, extval;
+
+    if (shift <= -(48 + round)) {
+        return 0;
+    } else if (shift < 0) {
+        if (round) {
+            val = src >> (-shift - 1);
+            val = (val >> 1) + (val & 1);
+        } else {
+            val = src >> -shift;
+        }
+        extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (shift < 48) {
+        uint64_t val = src << shift;
+        uint64_t extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return MAKE_64BIT_MASK(0, 48);
+}
+
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
     return do_mve_shl_ri(s, a, gen_urshr64_i64);
 }
 
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
+{
+    TCGv_i64 rda;
+    TCGv_i32 rdalo, rdahi;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+        return false;
+    }
+    if (a->rdahi == 15) {
+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
+        return false;
+    }
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
+        a->rm == a->rdahi || a->rm == a->rdalo) {
+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    rda = tcg_temp_new_i64();
+    rdalo = load_reg(s, a->rdalo);
+    rdahi = load_reg(s, a->rdahi);
+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+
+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
+
+    tcg_gen_extrl_i64_i32(rdalo, rda);
+    tcg_gen_extrh_i64_i32(rdahi, rda);
+    store_reg(s, a->rdalo, rdalo);
+    store_reg(s, a->rdahi, rdahi);
+    tcg_temp_free_i64(rda);
+
+    return true;
+}
+
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
+}
+
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+}
+
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
+}
+
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
+}
+
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
+}
+
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
+}
+
 /*
  * Multiply and multiply accumulate
  */
-- 
2.20.1

Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 31 ++++++++++++++-----
 target/arm/mve_helper.c | 10 ++++++
 target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 5 files changed, 104 insertions(+), 9 deletions(-)

Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  2 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 18 ++++++++++++++----
 target/arm/mve_helper.c | 10 ++++++++++
 target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 4 deletions(-)