[Qemu-devel] [PULL 00/42] target-arm queue
[PULL v2 00/11] target-arm queue
1
Arm queue -- I have more stuff pending but I prefer to push
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
this first lot out and keep the pull below 50 patches.
2
ethernet device failed 'make check' on big-endian hosts.
3
Most of this is Alex's FP16 support work.
4
3
5
-- PMM
4
-- PMM
6
5
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
7
7
8
The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
9
10
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
15
13
16
for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
17
15
18
MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* update MAINTAINERS for Alistair's new email address
20
* Correctly initialize MDCR_EL2.HPMN
23
* add Arm v8.2 FP16 arithmetic extension for linux-user
21
* versal: Use nr_apu_cpus in favor of hard coding 2
24
* implement display connector emulation for vexpress board
22
* accel/tcg: Add URL of clang bug to comment about our workaround
25
* xilinx_spips: Enable only two slaves when reading/writing with stripe
23
* Add support for FEAT_DIT, Data Independent Timing
26
* xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
24
* Remove GPIO from unimplemented NPCM7XX
27
* hw: register: Run post_write hook on reset
25
* Fix SCR RES1 handling
26
* Don't migrate CPUARMState.features
28
27
29
----------------------------------------------------------------
28
----------------------------------------------------------------
30
Alex Bennée (31):
29
Aaron Lindsay (1):
31
include/exec/helper-head.h: support f16 in helper calls
30
target/arm: Don't migrate CPUARMState.features
32
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
33
target/arm/cpu.h: update comment for half-precision values
34
target/arm/cpu.h: add additional float_status flags
35
target/arm/helper: pass explicit fpst to set_rmode
36
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
37
arm/translate-a64: handle_3same_64 comment fix
38
arm/translate-a64: initial decode for simd_three_reg_same_fp16
39
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
40
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
41
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
42
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
43
arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
44
arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
45
arm/translate-a64: add FP16 x2 ops for simd_indexed
46
arm/translate-a64: initial decode for simd_two_reg_misc_fp16
47
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
48
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
49
arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
50
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
51
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
52
arm/helper.c: re-factor recpe and add recepe_f16
53
arm/translate-a64: add FP16 FRECPE
54
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
55
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
56
arm/helper.c: re-factor rsqrte and add rsqrte_f16
57
arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
58
arm/translate-a64: add FP16 FMOV to simd_mod_imm
59
arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
60
arm/translate-a64: implement simd_scalar_three_reg_same_fp16
61
arm/translate-a64: add all single op FP16 to handle_fp_1src_half
62
31
63
Alistair Francis (2):
32
Daniel Müller (1):
64
hw: register: Run post_write hook on reset
33
target/arm: Correctly initialize MDCR_EL2.HPMN
65
MAINTAINERS: Update my email address
66
34
67
Corey Minyard (2):
35
Edgar E. Iglesias (1):
68
i2c: Fix some brace style issues
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
69
i2c: Move the bus class to i2c.h
70
37
71
Francisco Iglesias (2):
38
Hao Wu (1):
72
xilinx_spips: Enable only two slaves when reading/writing with stripe
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
73
xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
74
40
75
Linus Walleij (3):
41
Mike Nawrocki (1):
76
hw/i2c-ddc: Do not fail writes
42
target/arm: Fix SCR RES1 handling
77
hw/sii9022: Add support for Silicon Image SII9022
78
arm/vexpress: Add proper display connector emulation
79
43
80
Peter Maydell (2):
44
Peter Maydell (2):
81
target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
45
arm: Update infocenter.arm.com URLs
82
linux-user: Report AArch64 FP16 support via hwcap bits
46
accel/tcg: Add URL of clang bug to comment about our workaround
83
47
84
hw/display/Makefile.objs | 1 +
48
Rebecca Cran (4):
85
include/exec/helper-head.h | 3 +
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
86
include/fpu/softfloat.h | 18 +-
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
87
include/hw/i2c/i2c.h | 23 +-
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
88
include/hw/register.h | 6 +-
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
89
target/arm/cpu.h | 34 +-
90
target/arm/helper-a64.h | 33 +
91
target/arm/helper.h | 14 +-
92
hw/arm/vexpress.c | 6 +-
93
hw/core/register.c | 8 +
94
hw/display/sii9022.c | 191 ++++++
95
hw/i2c/core.c | 18 -
96
hw/i2c/i2c-ddc.c | 4 +-
97
hw/ssi/xilinx_spips.c | 43 +-
98
linux-user/elfload.c | 2 +
99
target/arm/cpu64.c | 1 +
100
target/arm/helper-a64.c | 269 +++++++++
101
target/arm/helper.c | 481 ++++++++-------
102
target/arm/translate-a64.c | 1266 +++++++++++++++++++++++++++++++++------
103
target/arm/translate.c | 12 +-
104
MAINTAINERS | 12 +-
105
default-configs/arm-softmmu.mak | 2 +
106
hw/display/trace-events | 5 +
107
23 files changed, 1981 insertions(+), 471 deletions(-)
108
create mode 100644 hw/display/sii9022.c
109
53
54
include/hw/dma/pl080.h | 7 ++--
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Ensure that the post write hook is called during reset. This allows us
4
to rely on the post write functions instead of having to call them from
5
the reset() function.
6
7
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/register.h | 6 +++---
13
hw/core/register.c | 8 ++++++++
14
2 files changed, 11 insertions(+), 3 deletions(-)
15
16
diff --git a/include/hw/register.h b/include/hw/register.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/register.h
19
+++ b/include/hw/register.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct RegisterInfoArray RegisterInfoArray;
21
* immediately before the actual write. The returned value is what is written,
22
* giving the handler a chance to modify the written value.
23
* @post_write: Post write callback. Passed the written value. Most write side
24
- * effects should be implemented here.
25
+ * effects should be implemented here. This is called during device reset.
26
*
27
* @post_read: Post read callback. Passes the value that is about to be returned
28
* for a read. The return value from this function is what is ultimately read,
29
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
30
bool debug);
31
32
/**
33
- * reset a register
34
- * @reg: register to reset
35
+ * Resets a register. This will also call the post_write hook if it exists.
36
+ * @reg: The register to reset.
37
*/
38
39
void register_reset(RegisterInfo *reg);
40
diff --git a/hw/core/register.c b/hw/core/register.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/core/register.c
43
+++ b/hw/core/register.c
44
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
45
46
void register_reset(RegisterInfo *reg)
47
{
48
+ const RegisterAccessInfo *ac;
49
+
50
g_assert(reg);
51
52
if (!reg->data || !reg->access) {
53
return;
54
}
55
56
+ ac = reg->access;
57
+
58
register_write_val(reg, reg->access->reset);
59
+
60
+ if (ac->post_write) {
61
+ ac->post_write(reg, reg->access->reset);
62
+ }
63
}
64
65
void register_init(RegisterInfo *reg)
66
--
67
2.16.2
68
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe
Deleted patch
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
2
1
3
Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
4
chip selects are enabled (e.g reading/writing with stripe).
5
6
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
9
Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++----
13
1 file changed, 37 insertions(+), 4 deletions(-)
14
15
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/ssi/xilinx_spips.c
18
+++ b/hw/ssi/xilinx_spips.c
19
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
20
{
21
int i;
22
23
- for (i = 0; i < s->num_cs; i++) {
24
+ for (i = 0; i < s->num_cs * s->num_busses; i++) {
25
bool old_state = s->cs_lines_state[i];
26
bool new_state = field & (1 << i);
27
28
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
29
}
30
qemu_set_irq(s->cs_lines[i], !new_state);
31
}
32
- if (!(field & ((1 << s->num_cs) - 1))) {
33
+ if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
34
s->snoop_state = SNOOP_CHECKING;
35
s->cmd_dummies = 0;
36
s->link_state = 1;
37
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
38
{
39
if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
40
int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
41
- xilinx_spips_update_cs(XILINX_SPIPS(s), field);
42
+ bool upper_cs_sel = field & (1 << 1);
43
+ bool lower_cs_sel = field & 1;
44
+ bool bus0_enabled;
45
+ bool bus1_enabled;
46
+ uint8_t buses;
47
+ int cs = 0;
48
+
49
+ buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
50
+ bus0_enabled = buses & 1;
51
+ bus1_enabled = buses & (1 << 1);
52
+
53
+ if (bus0_enabled && bus1_enabled) {
54
+ if (lower_cs_sel) {
55
+ cs |= 1;
56
+ }
57
+ if (upper_cs_sel) {
58
+ cs |= 1 << 3;
59
+ }
60
+ } else if (bus0_enabled) {
61
+ if (lower_cs_sel) {
62
+ cs |= 1;
63
+ }
64
+ if (upper_cs_sel) {
65
+ cs |= 1 << 1;
66
+ }
67
+ } else if (bus1_enabled) {
68
+ if (lower_cs_sel) {
69
+ cs |= 1 << 2;
70
+ }
71
+ if (upper_cs_sel) {
72
+ cs |= 1 << 3;
73
+ }
74
+ }
75
+ xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
76
}
77
}
78
79
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
80
if (num_effective_busses(s) == 2) {
81
/* Single bit chip-select for qspi */
82
field &= 0x1;
83
- field |= field << 1;
84
+ field |= field << 3;
85
/* Dual stack U-Page */
86
} else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
87
s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
88
--
89
2.16.2
90
91
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
Deleted patch
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
2
1
3
Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
4
for matching what is expected by Micron (Numonyx) flashes (the default target
5
flash type of the QSPI).
6
7
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Message-id: 20180223232233.31482-3-frasse.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/ssi/xilinx_spips.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/xilinx_spips.c
19
+++ b/hw/ssi/xilinx_spips.c
20
@@ -XXX,XX +XXX,XX @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
21
return 2;
22
case QIOR:
23
case QIOR_4:
24
- return 5;
25
+ return 4;
26
default:
27
return -1;
28
}
29
--
30
2.16.2
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/42] i2c: Fix some brace style issues
Deleted patch
1
From: Corey Minyard <cminyard@mvista.com>
2
1
3
Signed-off-by: Corey Minyard <cminyard@mvista.com>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6
Message-id: 20180227104903.21353-2-linus.walleij@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/i2c/i2c.h | 6 ++----
10
hw/i2c/core.c | 3 +--
11
2 files changed, 3 insertions(+), 6 deletions(-)
12
13
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/i2c/i2c.h
16
+++ b/include/hw/i2c/i2c.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlave I2CSlave;
18
#define I2C_SLAVE_GET_CLASS(obj) \
19
OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
20
21
-typedef struct I2CSlaveClass
22
-{
23
+typedef struct I2CSlaveClass {
24
DeviceClass parent_class;
25
26
/* Callbacks provided by the device. */
27
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlaveClass
28
int (*event)(I2CSlave *s, enum i2c_event event);
29
} I2CSlaveClass;
30
31
-struct I2CSlave
32
-{
33
+struct I2CSlave {
34
DeviceState qdev;
35
36
/* Remaining fields for internal use by the I2C code. */
37
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/i2c/core.c
40
+++ b/hw/i2c/core.c
41
@@ -XXX,XX +XXX,XX @@ struct I2CNode {
42
43
#define I2C_BROADCAST 0x00
44
45
-struct I2CBus
46
-{
47
+struct I2CBus {
48
BusState qbus;
49
QLIST_HEAD(, I2CNode) current_devs;
50
uint8_t saved_address;
51
--
52
2.16.2
53
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/42] i2c: Move the bus class to i2c.h
Deleted patch
1
From: Corey Minyard <cminyard@mvista.com>
2
1
3
Some devices need access to it.
4
5
Signed-off-by: Corey Minyard <cminyard@mvista.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
8
Message-id: 20180227104903.21353-3-linus.walleij@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/i2c/i2c.h | 17 +++++++++++++++++
12
hw/i2c/core.c | 17 -----------------
13
2 files changed, 17 insertions(+), 17 deletions(-)
14
15
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/i2c/i2c.h
18
+++ b/include/hw/i2c/i2c.h
19
@@ -XXX,XX +XXX,XX @@ struct I2CSlave {
20
uint8_t address;
21
};
22
23
+#define TYPE_I2C_BUS "i2c-bus"
24
+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
25
+
26
+typedef struct I2CNode I2CNode;
27
+
28
+struct I2CNode {
29
+ I2CSlave *elt;
30
+ QLIST_ENTRY(I2CNode) next;
31
+};
32
+
33
+struct I2CBus {
34
+ BusState qbus;
35
+ QLIST_HEAD(, I2CNode) current_devs;
36
+ uint8_t saved_address;
37
+ bool broadcast;
38
+};
39
+
40
I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
41
void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
42
int i2c_bus_busy(I2CBus *bus);
43
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/i2c/core.c
46
+++ b/hw/i2c/core.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "qemu/osdep.h"
49
#include "hw/i2c/i2c.h"
50
51
-typedef struct I2CNode I2CNode;
52
-
53
-struct I2CNode {
54
- I2CSlave *elt;
55
- QLIST_ENTRY(I2CNode) next;
56
-};
57
-
58
#define I2C_BROADCAST 0x00
59
60
-struct I2CBus {
61
- BusState qbus;
62
- QLIST_HEAD(, I2CNode) current_devs;
63
- uint8_t saved_address;
64
- bool broadcast;
65
-};
66
-
67
static Property i2c_props[] = {
68
DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
69
DEFINE_PROP_END_OF_LIST(),
70
};
71
72
-#define TYPE_I2C_BUS "i2c-bus"
73
-#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
74
-
75
static const TypeInfo i2c_bus_info = {
76
.name = TYPE_I2C_BUS,
77
.parent = TYPE_BUS,
78
--
79
2.16.2
80
81
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/42] hw/i2c-ddc: Do not fail writes
Deleted patch
1
From: Linus Walleij <linus.walleij@linaro.org>
2
1
3
The tx function of the DDC I2C slave emulation was returning 1
4
on all writes resulting in NACK in the I2C bus. Changing it to
5
0 makes the DDC I2C work fine with bit-banged I2C such as the
6
versatile I2C.
7
8
I guess it was not affecting whatever I2C controller this was
9
used with until now, but with the Versatile I2C it surely
10
does not work.
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
14
Message-id: 20180227104903.21353-4-linus.walleij@linaro.org
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/i2c/i2c-ddc.c | 4 ++--
19
1 file changed, 2 insertions(+), 2 deletions(-)
20
21
diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/i2c/i2c-ddc.c
24
+++ b/hw/i2c/i2c-ddc.c
25
@@ -XXX,XX +XXX,XX @@ static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
26
s->reg = data;
27
s->firstbyte = false;
28
DPRINTF("[EDID] Written new pointer: %u\n", data);
29
- return 1;
30
+ return 0;
31
}
32
33
/* Ignore all writes */
34
s->reg++;
35
- return 1;
36
+ return 0;
37
}
38
39
static void i2c_ddc_init(Object *obj)
40
--
41
2.16.2
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/42] hw/sii9022: Add support for Silicon Image SII9022
Deleted patch
1
From: Linus Walleij <linus.walleij@linaro.org>
2
1
3
This adds support for emulating the Silicon Image SII9022 DVI/HDMI
4
bridge. It's not very clever right now, it just acknowledges
5
the switch into DDC I2C mode and back. Combining this with the
6
existing DDC I2C emulation gives the right behavior on the Versatile
7
Express emulation passing through the QEMU EDID to the emulated
8
platform.
9
10
Cc: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
12
Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/display/Makefile.objs | 1 +
18
hw/display/sii9022.c | 191 +++++++++++++++++++++++++++++++++++++++++++++++
19
hw/display/trace-events | 5 ++
20
3 files changed, 197 insertions(+)
21
create mode 100644 hw/display/sii9022.c
22
23
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/display/Makefile.objs
26
+++ b/hw/display/Makefile.objs
27
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
28
common-obj-$(CONFIG_G364FB) += g364fb.o
29
common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
30
common-obj-$(CONFIG_PL110) += pl110.o
31
+common-obj-$(CONFIG_SII9022) += sii9022.o
32
common-obj-$(CONFIG_SSD0303) += ssd0303.o
33
common-obj-$(CONFIG_SSD0323) += ssd0323.o
34
common-obj-$(CONFIG_XEN) += xenfb.o
35
diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
36
new file mode 100644
37
index XXXXXXX..XXXXXXX
38
--- /dev/null
39
+++ b/hw/display/sii9022.c
40
@@ -XXX,XX +XXX,XX @@
41
+/*
42
+ * Silicon Image SiI9022
43
+ *
44
+ * This is a pretty hollow emulation: all we do is acknowledge that we
45
+ * exist (chip ID) and confirm that we get switched over into DDC mode
46
+ * so the emulated host can proceed to read out EDID data. All subsequent
47
+ * set-up of connectors etc will be acknowledged and ignored.
48
+ *
49
+ * Copyright (C) 2018 Linus Walleij
50
+ *
51
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
52
+ * See the COPYING file in the top-level directory.
53
+ * SPDX-License-Identifier: GPL-2.0-or-later
54
+ */
55
+
56
+#include "qemu/osdep.h"
57
+#include "qemu-common.h"
58
+#include "hw/i2c/i2c.h"
59
+#include "hw/i2c/i2c-ddc.h"
60
+#include "trace.h"
61
+
62
+#define SII9022_SYS_CTRL_DATA 0x1a
63
+#define SII9022_SYS_CTRL_PWR_DWN 0x10
64
+#define SII9022_SYS_CTRL_AV_MUTE 0x08
65
+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
66
+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
67
+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
68
+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
69
+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
70
+#define SII9022_REG_CHIPID 0x1b
71
+#define SII9022_INT_ENABLE 0x3c
72
+#define SII9022_INT_STATUS 0x3d
73
+#define SII9022_INT_STATUS_HOTPLUG 0x01;
74
+#define SII9022_INT_STATUS_PLUGGED 0x04;
75
+
76
+#define TYPE_SII9022 "sii9022"
77
+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
78
+
79
+typedef struct sii9022_state {
80
+ I2CSlave parent_obj;
81
+ uint8_t ptr;
82
+ bool addr_byte;
83
+ bool ddc_req;
84
+ bool ddc_skip_finish;
85
+ bool ddc;
86
+} sii9022_state;
87
+
88
+static const VMStateDescription vmstate_sii9022 = {
89
+ .name = "sii9022",
90
+ .version_id = 1,
91
+ .minimum_version_id = 1,
92
+ .fields = (VMStateField[]) {
93
+ VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
94
+ VMSTATE_UINT8(ptr, sii9022_state),
95
+ VMSTATE_BOOL(addr_byte, sii9022_state),
96
+ VMSTATE_BOOL(ddc_req, sii9022_state),
97
+ VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
98
+ VMSTATE_BOOL(ddc, sii9022_state),
99
+ VMSTATE_END_OF_LIST()
100
+ }
101
+};
102
+
103
+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
104
+{
105
+ sii9022_state *s = SII9022(i2c);
106
+
107
+ switch (event) {
108
+ case I2C_START_SEND:
109
+ s->addr_byte = true;
110
+ break;
111
+ case I2C_START_RECV:
112
+ break;
113
+ case I2C_FINISH:
114
+ break;
115
+ case I2C_NACK:
116
+ break;
117
+ }
118
+
119
+ return 0;
120
+}
121
+
122
+static int sii9022_rx(I2CSlave *i2c)
123
+{
124
+ sii9022_state *s = SII9022(i2c);
125
+ uint8_t res = 0x00;
126
+
127
+ switch (s->ptr) {
128
+ case SII9022_SYS_CTRL_DATA:
129
+ if (s->ddc_req) {
130
+ /* Acknowledge DDC bus request */
131
+ res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
132
+ }
133
+ break;
134
+ case SII9022_REG_CHIPID:
135
+ res = 0xb0;
136
+ break;
137
+ case SII9022_INT_STATUS:
138
+ /* Something is cold-plugged in, no interrupts */
139
+ res = SII9022_INT_STATUS_PLUGGED;
140
+ break;
141
+ default:
142
+ break;
143
+ }
144
+
145
+ trace_sii9022_read_reg(s->ptr, res);
146
+ s->ptr++;
147
+
148
+ return res;
149
+}
150
+
151
+static int sii9022_tx(I2CSlave *i2c, uint8_t data)
152
+{
153
+ sii9022_state *s = SII9022(i2c);
154
+
155
+ if (s->addr_byte) {
156
+ s->ptr = data;
157
+ s->addr_byte = false;
158
+ return 0;
159
+ }
160
+
161
+ switch (s->ptr) {
162
+ case SII9022_SYS_CTRL_DATA:
163
+ if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
164
+ s->ddc_req = true;
165
+ if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
166
+ s->ddc = true;
167
+ /* Skip this finish since we just switched to DDC */
168
+ s->ddc_skip_finish = true;
169
+ trace_sii9022_switch_mode("DDC");
170
+ }
171
+ } else {
172
+ s->ddc_req = false;
173
+ s->ddc = false;
174
+ trace_sii9022_switch_mode("normal");
175
+ }
176
+ break;
177
+ default:
178
+ break;
179
+ }
180
+
181
+ trace_sii9022_write_reg(s->ptr, data);
182
+ s->ptr++;
183
+
184
+ return 0;
185
+}
186
+
187
+static void sii9022_reset(DeviceState *dev)
188
+{
189
+ sii9022_state *s = SII9022(dev);
190
+
191
+ s->ptr = 0;
192
+ s->addr_byte = false;
193
+ s->ddc_req = false;
194
+ s->ddc_skip_finish = false;
195
+ s->ddc = false;
196
+}
197
+
198
+static void sii9022_realize(DeviceState *dev, Error **errp)
199
+{
200
+ I2CBus *bus;
201
+
202
+ bus = I2C_BUS(qdev_get_parent_bus(dev));
203
+ i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
204
+}
205
+
206
+static void sii9022_class_init(ObjectClass *klass, void *data)
207
+{
208
+ DeviceClass *dc = DEVICE_CLASS(klass);
209
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
210
+
211
+ k->event = sii9022_event;
212
+ k->recv = sii9022_rx;
213
+ k->send = sii9022_tx;
214
+ dc->reset = sii9022_reset;
215
+ dc->realize = sii9022_realize;
216
+ dc->vmsd = &vmstate_sii9022;
217
+}
218
+
219
+static const TypeInfo sii9022_info = {
220
+ .name = TYPE_SII9022,
221
+ .parent = TYPE_I2C_SLAVE,
222
+ .instance_size = sizeof(sii9022_state),
223
+ .class_init = sii9022_class_init,
224
+};
225
+
226
+static void sii9022_register_types(void)
227
+{
228
+ type_register_static(&sii9022_info);
229
+}
230
+
231
+type_init(sii9022_register_types)
232
diff --git a/hw/display/trace-events b/hw/display/trace-events
233
index XXXXXXX..XXXXXXX 100644
234
--- a/hw/display/trace-events
235
+++ b/hw/display/trace-events
236
@@ -XXX,XX +XXX,XX @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
237
vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
238
vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
239
vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
240
+
241
+# hw/display/sii9022.c
242
+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
243
+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
244
+sii9022_switch_mode(const char *mode) "mode: %s"
245
--
246
2.16.2
247
248
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/42] arm/vexpress: Add proper display connector emulation
Deleted patch
1
From: Linus Walleij <linus.walleij@linaro.org>
2
1
3
This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
4
Versatile Express machine, and selects the two I2C devices necessary
5
in the arm-softmmu.mak configuration so everything will build
6
smoothly.
7
8
I am implementing proper handling of the graphics in the Linux
9
kernel and adding proper emulation of SiI9022 and EDID makes the
10
driver probe as nicely as before, retrieving the resolutions
11
supported by the "QEMU monitor" and overall just working nice.
12
13
Cc: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
15
Message-id: 20180227104903.21353-6-linus.walleij@linaro.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/vexpress.c | 6 +++++-
21
default-configs/arm-softmmu.mak | 2 ++
22
2 files changed, 7 insertions(+), 1 deletion(-)
23
24
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/vexpress.c
27
+++ b/hw/arm/vexpress.c
28
@@ -XXX,XX +XXX,XX @@
29
#include "hw/arm/arm.h"
30
#include "hw/arm/primecell.h"
31
#include "hw/devices.h"
32
+#include "hw/i2c/i2c.h"
33
#include "net/net.h"
34
#include "sysemu/sysemu.h"
35
#include "hw/boards.h"
36
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
37
uint32_t sys_id;
38
DriveInfo *dinfo;
39
pflash_t *pflash0;
40
+ I2CBus *i2c;
41
ram_addr_t vram_size, sram_size;
42
MemoryRegion *sysmem = get_system_memory();
43
MemoryRegion *vram = g_new(MemoryRegion, 1);
44
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
45
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
46
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
47
48
- /* VE_SERIALDVI: not modelled */
49
+ dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
50
+ i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
51
+ i2c_create_slave(i2c, "sii9022", 0x39);
52
53
sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
54
55
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
56
index XXXXXXX..XXXXXXX 100644
57
--- a/default-configs/arm-softmmu.mak
58
+++ b/default-configs/arm-softmmu.mak
59
@@ -XXX,XX +XXX,XX @@ CONFIG_STELLARIS_INPUT=y
60
CONFIG_STELLARIS_ENET=y
61
CONFIG_SSD0303=y
62
CONFIG_SSD0323=y
63
+CONFIG_DDC=y
64
+CONFIG_SII9022=y
65
CONFIG_ADS7846=y
66
CONFIG_MAX111X=y
67
CONFIG_SSI=y
68
--
69
2.16.2
70
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/42] include/exec/helper-head.h: support f16 in helper calls
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This allows us to explicitly pass float16 to helpers rather than
4
assuming uint32_t and dealing with the result. Of course they will be
5
passed in i32 sized registers by default.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-2-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/exec/helper-head.h | 3 +++
13
1 file changed, 3 insertions(+)
14
15
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/helper-head.h
18
+++ b/include/exec/helper-head.h
19
@@ -XXX,XX +XXX,XX @@
20
#define dh_alias_int i32
21
#define dh_alias_i64 i64
22
#define dh_alias_s64 i64
23
+#define dh_alias_f16 i32
24
#define dh_alias_f32 i32
25
#define dh_alias_f64 i64
26
#define dh_alias_ptr ptr
27
@@ -XXX,XX +XXX,XX @@
28
#define dh_ctype_int int
29
#define dh_ctype_i64 uint64_t
30
#define dh_ctype_s64 int64_t
31
+#define dh_ctype_f16 float16
32
#define dh_ctype_f32 float32
33
#define dh_ctype_f64 float64
34
#define dh_ctype_ptr void *
35
@@ -XXX,XX +XXX,XX @@
36
#define dh_is_signed_s32 1
37
#define dh_is_signed_i64 0
38
#define dh_is_signed_s64 1
39
+#define dh_is_signed_f16 0
40
#define dh_is_signed_f32 0
41
#define dh_is_signed_f64 0
42
#define dh_is_signed_tl 0
43
--
44
2.16.2
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/42] target/arm/cpu64: introduce ARM_V8_FP16 feature bit
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-3-alex.bennee@linaro.org
6
[PMM: postpone actually enabling feature until end of the
7
patch series]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ enum arm_features {
18
ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
19
ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
20
ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
21
+ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
22
};
23
24
static inline int arm_feature(CPUARMState *env, int feature)
25
--
26
2.16.2
27
28
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-4-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/cpu.h | 1 +
9
1 file changed, 1 insertion(+)
10
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu.h
14
+++ b/target/arm/cpu.h
15
@@ -XXX,XX +XXX,XX @@ typedef struct {
16
* Qn = regs[n].d[1]:regs[n].d[0]
17
* Dn = regs[n].d[0]
18
* Sn = regs[n].d[0] bits 31..0
19
+ * Hn = regs[n].d[0] bits 15..0
20
*
21
* This corresponds to the architecturally defined mapping between
22
* the two execution states, and means we do not need to explicitly
23
--
24
2.16.2
25
26
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/42] target/arm/cpu.h: add additional float_status flags
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Half-precision flush to zero behaviour is controlled by a separate
4
FZ16 bit in the FPCR. To handle this we pass a pointer to
5
fp_status_fp16 when working on half-precision operations. The value of
6
the presented FPCR is calculated from an amalgam of the two when read.
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 32 ++++++++++++++++++++++------
14
target/arm/helper.c | 26 ++++++++++++++++++-----
15
target/arm/translate-a64.c | 53 +++++++++++++++++++++++++---------------------
16
3 files changed, 75 insertions(+), 36 deletions(-)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
23
/* scratch space when Tn are not sufficient. */
24
uint32_t scratch[8];
25
26
- /* fp_status is the "normal" fp status. standard_fp_status retains
27
- * values corresponding to the ARM "Standard FPSCR Value", ie
28
- * default-NaN, flush-to-zero, round-to-nearest and is used by
29
- * any operations (generally Neon) which the architecture defines
30
- * as controlled by the standard FPSCR value rather than the FPSCR.
31
+ /* There are a number of distinct float control structures:
32
+ *
33
+ * fp_status: is the "normal" fp status.
34
+ * fp_status_fp16: used for half-precision calculations
35
+ * standard_fp_status : the ARM "Standard FPSCR Value"
36
+ *
37
+ * Half-precision operations are governed by a separate
38
+ * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
39
+ * status structure to control this.
40
+ *
41
+ * The "Standard FPSCR", ie default-NaN, flush-to-zero,
42
+ * round-to-nearest and is used by any operations (generally
43
+ * Neon) which the architecture defines as controlled by the
44
+ * standard FPSCR value rather than the FPSCR.
45
*
46
* To avoid having to transfer exception bits around, we simply
47
* say that the FPSCR cumulative exception flags are the logical
48
- * OR of the flags in the two fp statuses. This relies on the
49
+ * OR of the flags in the three fp statuses. This relies on the
50
* only thing which needs to read the exception flags being
51
* an explicit FPSCR read.
52
*/
53
float_status fp_status;
54
+ float_status fp_status_f16;
55
float_status standard_fp_status;
56
57
/* ZCR_EL[1-3] */
58
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
59
uint32_t vfp_get_fpscr(CPUARMState *env);
60
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
61
62
-/* For A64 the FPSCR is split into two logically distinct registers,
63
+/* FPCR, Floating Point Control Register
64
+ * FPSR, Floating Poiht Status Register
65
+ *
66
+ * For A64 the FPSCR is split into two logically distinct registers,
67
* FPCR and FPSR. However since they still use non-overlapping bits
68
* we store the underlying state in fpscr and just mask on read/write.
69
*/
70
#define FPSR_MASK 0xf800009f
71
#define FPCR_MASK 0x07f79f00
72
+
73
+#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
74
+#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
75
+#define FPCR_DN (1 << 25) /* Default NaN enable bit */
76
+
77
static inline uint32_t vfp_get_fpsr(CPUARMState *env)
78
{
79
return vfp_get_fpscr(env) & FPSR_MASK;
80
diff --git a/target/arm/helper.c b/target/arm/helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/helper.c
83
+++ b/target/arm/helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
85
| (env->vfp.vec_stride << 20);
86
i = get_float_exception_flags(&env->vfp.fp_status);
87
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
88
+ i |= get_float_exception_flags(&env->vfp.fp_status_f16);
89
fpscr |= vfp_exceptbits_from_host(i);
90
return fpscr;
91
}
92
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
93
break;
94
}
95
set_float_rounding_mode(i, &env->vfp.fp_status);
96
+ set_float_rounding_mode(i, &env->vfp.fp_status_f16);
97
}
98
- if (changed & (1 << 24)) {
99
- set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
100
- set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
101
+ if (changed & FPCR_FZ16) {
102
+ bool ftz_enabled = val & FPCR_FZ16;
103
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
104
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
105
+ }
106
+ if (changed & FPCR_FZ) {
107
+ bool ftz_enabled = val & FPCR_FZ;
108
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
109
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
110
+ }
111
+ if (changed & FPCR_DN) {
112
+ bool dnan_enabled = val & FPCR_DN;
113
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
114
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
115
}
116
- if (changed & (1 << 25))
117
- set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
118
119
+ /* The exception flags are ORed together when we read fpscr so we
120
+ * only need to preserve the current state in one of our
121
+ * float_status values.
122
+ */
123
i = vfp_exceptbits_to_host(val);
124
set_float_exception_flags(i, &env->vfp.fp_status);
125
+ set_float_exception_flags(0, &env->vfp.fp_status_f16);
126
set_float_exception_flags(0, &env->vfp.standard_fp_status);
127
}
128
129
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/translate-a64.c
132
+++ b/target/arm/translate-a64.c
133
@@ -XXX,XX +XXX,XX @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
134
tcg_temp_free_i64(tmp);
135
}
136
137
-static TCGv_ptr get_fpstatus_ptr(void)
138
+static TCGv_ptr get_fpstatus_ptr(bool is_f16)
139
{
140
TCGv_ptr statusptr = tcg_temp_new_ptr();
141
int offset;
142
143
- /* In A64 all instructions (both FP and Neon) use the FPCR;
144
- * there is no equivalent of the A32 Neon "standard FPSCR value"
145
- * and all operations use vfp.fp_status.
146
+ /* In A64 all instructions (both FP and Neon) use the FPCR; there
147
+ * is no equivalent of the A32 Neon "standard FPSCR value".
148
+ * However half-precision operations operate under a different
149
+ * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
150
*/
151
- offset = offsetof(CPUARMState, vfp.fp_status);
152
+ if (is_f16) {
153
+ offset = offsetof(CPUARMState, vfp.fp_status_f16);
154
+ } else {
155
+ offset = offsetof(CPUARMState, vfp.fp_status);
156
+ }
157
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
158
return statusptr;
159
}
160
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
161
bool cmp_with_zero, bool signal_all_nans)
162
{
163
TCGv_i64 tcg_flags = tcg_temp_new_i64();
164
- TCGv_ptr fpst = get_fpstatus_ptr();
165
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
166
167
if (is_double) {
168
TCGv_i64 tcg_vn, tcg_vm;
169
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
170
TCGv_i32 tcg_op;
171
TCGv_i32 tcg_res;
172
173
- fpst = get_fpstatus_ptr();
174
+ fpst = get_fpstatus_ptr(false);
175
tcg_op = read_fp_sreg(s, rn);
176
tcg_res = tcg_temp_new_i32();
177
178
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
179
return;
180
}
181
182
- fpst = get_fpstatus_ptr();
183
+ fpst = get_fpstatus_ptr(false);
184
tcg_op = read_fp_dreg(s, rn);
185
tcg_res = tcg_temp_new_i64();
186
187
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
188
TCGv_ptr fpst;
189
190
tcg_res = tcg_temp_new_i32();
191
- fpst = get_fpstatus_ptr();
192
+ fpst = get_fpstatus_ptr(false);
193
tcg_op1 = read_fp_sreg(s, rn);
194
tcg_op2 = read_fp_sreg(s, rm);
195
196
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
197
TCGv_ptr fpst;
198
199
tcg_res = tcg_temp_new_i64();
200
- fpst = get_fpstatus_ptr();
201
+ fpst = get_fpstatus_ptr(false);
202
tcg_op1 = read_fp_dreg(s, rn);
203
tcg_op2 = read_fp_dreg(s, rm);
204
205
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
206
{
207
TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
208
TCGv_i32 tcg_res = tcg_temp_new_i32();
209
- TCGv_ptr fpst = get_fpstatus_ptr();
210
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
211
212
tcg_op1 = read_fp_sreg(s, rn);
213
tcg_op2 = read_fp_sreg(s, rm);
214
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
215
{
216
TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
217
TCGv_i64 tcg_res = tcg_temp_new_i64();
218
- TCGv_ptr fpst = get_fpstatus_ptr();
219
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
220
221
tcg_op1 = read_fp_dreg(s, rn);
222
tcg_op2 = read_fp_dreg(s, rm);
223
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
224
TCGv_ptr tcg_fpstatus;
225
TCGv_i32 tcg_shift;
226
227
- tcg_fpstatus = get_fpstatus_ptr();
228
+ tcg_fpstatus = get_fpstatus_ptr(false);
229
230
tcg_shift = tcg_const_i32(64 - scale);
231
232
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
233
TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
234
TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
235
TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
236
- TCGv_ptr fpst = get_fpstatus_ptr();
237
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
238
239
assert(esize == 32);
240
assert(elements == 4);
241
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
242
}
243
244
size = extract32(size, 0, 1) ? 3 : 2;
245
- fpst = get_fpstatus_ptr();
246
+ fpst = get_fpstatus_ptr(false);
247
break;
248
default:
249
unallocated_encoding(s);
250
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
251
int fracbits, int size)
252
{
253
bool is_double = size == 3 ? true : false;
254
- TCGv_ptr tcg_fpst = get_fpstatus_ptr();
255
+ TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
256
TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
257
TCGv_i64 tcg_int = tcg_temp_new_i64();
258
TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
259
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
260
261
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
262
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
263
- tcg_fpstatus = get_fpstatus_ptr();
264
+ tcg_fpstatus = get_fpstatus_ptr(false);
265
tcg_shift = tcg_const_i32(fracbits);
266
267
if (is_double) {
268
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
269
int fpopcode, int rd, int rn, int rm)
270
{
271
int pass;
272
- TCGv_ptr fpst = get_fpstatus_ptr();
273
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
274
275
for (pass = 0; pass < elements; pass++) {
276
if (size) {
277
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
278
return;
279
}
280
281
- fpst = get_fpstatus_ptr();
282
+ fpst = get_fpstatus_ptr(false);
283
284
if (is_double) {
285
TCGv_i64 tcg_op = tcg_temp_new_i64();
286
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
287
int size, int rn, int rd)
288
{
289
bool is_double = (size == 3);
290
- TCGv_ptr fpst = get_fpstatus_ptr();
291
+ TCGv_ptr fpst = get_fpstatus_ptr(false);
292
293
if (is_double) {
294
TCGv_i64 tcg_op = tcg_temp_new_i64();
295
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
296
if (is_fcvt) {
297
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
298
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
299
- tcg_fpstatus = get_fpstatus_ptr();
300
+ tcg_fpstatus = get_fpstatus_ptr(false);
301
} else {
302
tcg_rmode = NULL;
303
tcg_fpstatus = NULL;
304
@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
305
306
/* Floating point operations need fpst */
307
if (opcode >= 0x58) {
308
- fpst = get_fpstatus_ptr();
309
+ fpst = get_fpstatus_ptr(false);
310
} else {
311
fpst = NULL;
312
}
313
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
314
}
315
316
if (need_fpstatus) {
317
- tcg_fpstatus = get_fpstatus_ptr();
318
+ tcg_fpstatus = get_fpstatus_ptr(false);
319
} else {
320
tcg_fpstatus = NULL;
321
}
322
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
323
}
324
325
if (is_fp) {
326
- fpst = get_fpstatus_ptr();
327
+ fpst = get_fpstatus_ptr(false);
328
} else {
329
fpst = NULL;
330
}
331
--
332
2.16.2
333
334
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/42] target/arm/helper: pass explicit fpst to set_rmode
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
As the rounding mode is now split between FP16 and the rest of
4
floating point we need to be explicit when tweaking it. Instead of
5
passing the CPU env we now pass the appropriate fpst pointer directly.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-6-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.h | 2 +-
13
target/arm/helper.c | 4 ++--
14
target/arm/translate-a64.c | 26 +++++++++++++-------------
15
target/arm/translate.c | 12 ++++++------
16
4 files changed, 22 insertions(+), 22 deletions(-)
17
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
23
DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
24
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
25
26
-DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env)
27
+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
28
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
29
30
DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env)
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/helper.c
34
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
36
/* Set the current fp rounding mode and return the old one.
37
* The argument is a softfloat float_round_ value.
38
*/
39
-uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
40
+uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
41
{
42
- float_status *fp_status = &env->vfp.fp_status;
43
+ float_status *fp_status = fpstp;
44
45
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
46
set_float_rounding_mode(rmode, fp_status);
47
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/translate-a64.c
50
+++ b/target/arm/translate-a64.c
51
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
52
{
53
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
54
55
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
56
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
57
gen_helper_rints(tcg_res, tcg_op, fpst);
58
59
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
60
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
61
tcg_temp_free_i32(tcg_rmode);
62
break;
63
}
64
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
65
{
66
TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
67
68
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
69
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
70
gen_helper_rintd(tcg_res, tcg_op, fpst);
71
72
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
73
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
74
tcg_temp_free_i32(tcg_rmode);
75
break;
76
}
77
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
78
79
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
80
81
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
82
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
83
84
if (is_double) {
85
TCGv_i64 tcg_double = read_fp_dreg(s, rn);
86
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
87
tcg_temp_free_i32(tcg_single);
88
}
89
90
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
91
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
92
tcg_temp_free_i32(tcg_rmode);
93
94
if (!sf) {
95
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
96
assert(!(is_scalar && is_q));
97
98
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
99
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
100
tcg_fpstatus = get_fpstatus_ptr(false);
101
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
102
tcg_shift = tcg_const_i32(fracbits);
103
104
if (is_double) {
105
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
106
107
tcg_temp_free_ptr(tcg_fpstatus);
108
tcg_temp_free_i32(tcg_shift);
109
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
110
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
111
tcg_temp_free_i32(tcg_rmode);
112
}
113
114
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
115
116
if (is_fcvt) {
117
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
118
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
119
tcg_fpstatus = get_fpstatus_ptr(false);
120
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
121
} else {
122
tcg_rmode = NULL;
123
tcg_fpstatus = NULL;
124
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
125
}
126
127
if (is_fcvt) {
128
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
129
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
130
tcg_temp_free_i32(tcg_rmode);
131
tcg_temp_free_ptr(tcg_fpstatus);
132
}
133
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
134
return;
135
}
136
137
- if (need_fpstatus) {
138
+ if (need_fpstatus || need_rmode) {
139
tcg_fpstatus = get_fpstatus_ptr(false);
140
} else {
141
tcg_fpstatus = NULL;
142
}
143
if (need_rmode) {
144
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
145
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
146
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
147
} else {
148
tcg_rmode = NULL;
149
}
150
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
151
clear_vec_high(s, is_q, rd);
152
153
if (need_rmode) {
154
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
155
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
156
tcg_temp_free_i32(tcg_rmode);
157
}
158
if (need_fpstatus) {
159
diff --git a/target/arm/translate.c b/target/arm/translate.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/target/arm/translate.c
162
+++ b/target/arm/translate.c
163
@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
164
TCGv_i32 tcg_rmode;
165
166
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
167
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
168
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
169
170
if (dp) {
171
TCGv_i64 tcg_op;
172
@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
173
tcg_temp_free_i32(tcg_res);
174
}
175
176
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
177
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
178
tcg_temp_free_i32(tcg_rmode);
179
180
tcg_temp_free_ptr(fpst);
181
@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
182
tcg_shift = tcg_const_i32(0);
183
184
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
185
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
186
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
187
188
if (dp) {
189
TCGv_i64 tcg_double, tcg_res;
190
@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
191
tcg_temp_free_i32(tcg_single);
192
}
193
194
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
195
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
196
tcg_temp_free_i32(tcg_rmode);
197
198
tcg_temp_free_i32(tcg_shift);
199
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
200
TCGv_ptr fpst = get_fpstatus_ptr(0);
201
TCGv_i32 tcg_rmode;
202
tcg_rmode = tcg_const_i32(float_round_to_zero);
203
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
204
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
205
if (dp) {
206
gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
207
} else {
208
gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
209
}
210
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
211
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
212
tcg_temp_free_i32(tcg_rmode);
213
tcg_temp_free_ptr(fpst);
214
break;
215
--
216
2.16.2
217
218
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/42] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This implements the half-precision variants of the across vector
4
reduction operations. This involves a re-factor of the reduction code
5
which more closely matches the ARM ARM order (and handles 8 element
6
reductions).
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper-a64.h | 4 ++
14
target/arm/helper-a64.c | 18 ++++++
15
target/arm/translate-a64.c | 140 ++++++++++++++++++++++++++++-----------------
16
3 files changed, 109 insertions(+), 53 deletions(-)
17
18
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-a64.h
21
+++ b/target/arm/helper-a64.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
23
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
24
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
25
i64, env, i64, i64, i64)
26
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
27
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
28
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
29
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
30
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper-a64.c
33
+++ b/target/arm/helper-a64.c
34
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
35
{
36
return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
37
}
38
+
39
+/*
40
+ * AdvSIMD half-precision
41
+ */
42
+
43
+#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
44
+
45
+#define ADVSIMD_HALFOP(name) \
46
+float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
47
+{ \
48
+ float_status *fpst = fpstp; \
49
+ return float16_ ## name(a, b, fpst); \
50
+}
51
+
52
+ADVSIMD_HALFOP(min)
53
+ADVSIMD_HALFOP(max)
54
+ADVSIMD_HALFOP(minnum)
55
+ADVSIMD_HALFOP(maxnum)
56
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/translate-a64.c
59
+++ b/target/arm/translate-a64.c
60
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
61
tcg_temp_free_i64(tcg_resh);
62
}
63
64
-static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
65
- int opc, bool is_min, TCGv_ptr fpst)
66
+/*
67
+ * do_reduction_op helper
68
+ *
69
+ * This mirrors the Reduce() pseudocode in the ARM ARM. It is
70
+ * important for correct NaN propagation that we do these
71
+ * operations in exactly the order specified by the pseudocode.
72
+ *
73
+ * This is a recursive function, TCG temps should be freed by the
74
+ * calling function once it is done with the values.
75
+ */
76
+static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
77
+ int esize, int size, int vmap, TCGv_ptr fpst)
78
{
79
- /* Helper function for disas_simd_across_lanes: do a single precision
80
- * min/max operation on the specified two inputs,
81
- * and return the result in tcg_elt1.
82
- */
83
- if (opc == 0xc) {
84
- if (is_min) {
85
- gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
86
- } else {
87
- gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
88
- }
89
+ if (esize == size) {
90
+ int element;
91
+ TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
92
+ TCGv_i32 tcg_elem;
93
+
94
+ /* We should have one register left here */
95
+ assert(ctpop8(vmap) == 1);
96
+ element = ctz32(vmap);
97
+ assert(element < 8);
98
+
99
+ tcg_elem = tcg_temp_new_i32();
100
+ read_vec_element_i32(s, tcg_elem, rn, element, msize);
101
+ return tcg_elem;
102
} else {
103
- assert(opc == 0xf);
104
- if (is_min) {
105
- gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
106
- } else {
107
- gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
108
+ int bits = size / 2;
109
+ int shift = ctpop8(vmap) / 2;
110
+ int vmap_lo = (vmap >> shift) & vmap;
111
+ int vmap_hi = (vmap & ~vmap_lo);
112
+ TCGv_i32 tcg_hi, tcg_lo, tcg_res;
113
+
114
+ tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
115
+ tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
116
+ tcg_res = tcg_temp_new_i32();
117
+
118
+ switch (fpopcode) {
119
+ case 0x0c: /* fmaxnmv half-precision */
120
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
121
+ break;
122
+ case 0x0f: /* fmaxv half-precision */
123
+ gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
124
+ break;
125
+ case 0x1c: /* fminnmv half-precision */
126
+ gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
127
+ break;
128
+ case 0x1f: /* fminv half-precision */
129
+ gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
130
+ break;
131
+ case 0x2c: /* fmaxnmv */
132
+ gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
133
+ break;
134
+ case 0x2f: /* fmaxv */
135
+ gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
136
+ break;
137
+ case 0x3c: /* fminnmv */
138
+ gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
139
+ break;
140
+ case 0x3f: /* fminv */
141
+ gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
142
+ break;
143
+ default:
144
+ g_assert_not_reached();
145
}
146
+
147
+ tcg_temp_free_i32(tcg_hi);
148
+ tcg_temp_free_i32(tcg_lo);
149
+ return tcg_res;
150
}
151
}
152
153
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
154
break;
155
case 0xc: /* FMAXNMV, FMINNMV */
156
case 0xf: /* FMAXV, FMINV */
157
- if (!is_u || !is_q || extract32(size, 0, 1)) {
158
- unallocated_encoding(s);
159
- return;
160
- }
161
- /* Bit 1 of size field encodes min vs max, and actual size is always
162
- * 32 bits: adjust the size variable so following code can rely on it
163
+ /* Bit 1 of size field encodes min vs max and the actual size
164
+ * depends on the encoding of the U bit. If not set (and FP16
165
+ * enabled) then we do half-precision float instead of single
166
+ * precision.
167
*/
168
is_min = extract32(size, 1, 1);
169
is_fp = true;
170
- size = 2;
171
+ if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
172
+ size = 1;
173
+ } else if (!is_u || !is_q || extract32(size, 0, 1)) {
174
+ unallocated_encoding(s);
175
+ return;
176
+ } else {
177
+ size = 2;
178
+ }
179
break;
180
default:
181
unallocated_encoding(s);
182
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
183
184
}
185
} else {
186
- /* Floating point ops which work on 32 bit (single) intermediates.
187
+ /* Floating point vector reduction ops which work across 32
188
+ * bit (single) or 16 bit (half-precision) intermediates.
189
* Note that correct NaN propagation requires that we do these
190
* operations in exactly the order specified by the pseudocode.
191
*/
192
- TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
193
- TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
194
- TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
195
- TCGv_ptr fpst = get_fpstatus_ptr(false);
196
-
197
- assert(esize == 32);
198
- assert(elements == 4);
199
-
200
- read_vec_element(s, tcg_elt, rn, 0, MO_32);
201
- tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
202
- read_vec_element(s, tcg_elt, rn, 1, MO_32);
203
- tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
204
-
205
- do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
206
-
207
- read_vec_element(s, tcg_elt, rn, 2, MO_32);
208
- tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
209
- read_vec_element(s, tcg_elt, rn, 3, MO_32);
210
- tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
211
-
212
- do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
213
-
214
- do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
215
-
216
- tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
217
- tcg_temp_free_i32(tcg_elt1);
218
- tcg_temp_free_i32(tcg_elt2);
219
- tcg_temp_free_i32(tcg_elt3);
220
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
221
+ int fpopcode = opcode | is_min << 4 | is_u << 5;
222
+ int vmap = (1 << elements) - 1;
223
+ TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
224
+ (is_q ? 128 : 64), vmap, fpst);
225
+ tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
226
+ tcg_temp_free_i32(tcg_res32);
227
tcg_temp_free_ptr(fpst);
228
}
229
230
--
231
2.16.2
232
233
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/42] arm/translate-a64: handle_3same_64 comment fix
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
We do implement all the opcodes.
4
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180227143852.11175-8-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 3 +--
11
1 file changed, 1 insertion(+), 2 deletions(-)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
18
/* Handle 64x64->64 opcodes which are shared between the scalar
19
* and vector 3-same groups. We cover every opcode where size == 3
20
* is valid in either the three-reg-same (integer, not pairwise)
21
- * or scalar-three-reg-same groups. (Some opcodes are not yet
22
- * implemented.)
23
+ * or scalar-three-reg-same groups.
24
*/
25
TCGCond cond;
26
27
--
28
2.16.2
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/42] arm/translate-a64: initial decode for simd_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This is the initial decode skeleton for the Advanced SIMD three same
4
instruction group.
5
6
The fprintf is purely to aid debugging as the additional instructions
7
are added. It will be removed once the group is complete.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180227143852.11175-9-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
15
1 file changed, 73 insertions(+)
16
17
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-a64.c
20
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
22
}
23
}
24
25
+/*
26
+ * Advanced SIMD three same (ARMv8.2 FP16 variants)
27
+ *
28
+ * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
29
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
30
+ * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
31
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
32
+ *
33
+ * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
34
+ * (register), FACGE, FABD, FCMGT (register) and FACGT.
35
+ *
36
+ */
37
+static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
38
+{
39
+ int opcode, fpopcode;
40
+ int is_q, u, a, rm, rn, rd;
41
+ int datasize, elements;
42
+ int pass;
43
+ TCGv_ptr fpst;
44
+
45
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
46
+ unallocated_encoding(s);
47
+ return;
48
+ }
49
+
50
+ if (!fp_access_check(s)) {
51
+ return;
52
+ }
53
+
54
+ /* For these floating point ops, the U, a and opcode bits
55
+ * together indicate the operation.
56
+ */
57
+ opcode = extract32(insn, 11, 3);
58
+ u = extract32(insn, 29, 1);
59
+ a = extract32(insn, 23, 1);
60
+ is_q = extract32(insn, 30, 1);
61
+ rm = extract32(insn, 16, 5);
62
+ rn = extract32(insn, 5, 5);
63
+ rd = extract32(insn, 0, 5);
64
+
65
+ fpopcode = opcode | (a << 3) | (u << 4);
66
+ datasize = is_q ? 128 : 64;
67
+ elements = datasize / 16;
68
+
69
+ fpst = get_fpstatus_ptr(true);
70
+
71
+ for (pass = 0; pass < elements; pass++) {
72
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
73
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
74
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
75
+
76
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
77
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
78
+
79
+ switch (fpopcode) {
80
+ default:
81
+ fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
82
+ __func__, insn, fpopcode, s->pc);
83
+ g_assert_not_reached();
84
+ }
85
+
86
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
87
+ tcg_temp_free_i32(tcg_res);
88
+ tcg_temp_free_i32(tcg_op1);
89
+ tcg_temp_free_i32(tcg_op2);
90
+ }
91
+
92
+ tcg_temp_free_ptr(fpst);
93
+
94
+ clear_vec_high(s, is_q, rd);
95
+}
96
+
97
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
98
int size, int rn, int rd)
99
{
100
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
101
{ 0xce000000, 0xff808000, disas_crypto_four_reg },
102
{ 0xce800000, 0xffe00000, disas_crypto_xar },
103
{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
104
+ { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
105
{ 0x00000000, 0x00000000, NULL }
106
};
107
108
--
109
2.16.2
110
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/42] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
The fprintf is only there for debugging as the skeleton is added to,
4
it will be removed once the skeleton is complete.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper-a64.h | 4 ++++
12
target/arm/helper-a64.c | 4 ++++
13
target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++
14
3 files changed, 36 insertions(+)
15
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
19
+++ b/target/arm/helper-a64.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
21
DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
22
DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
23
DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
24
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
25
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
26
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
27
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
28
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper-a64.c
31
+++ b/target/arm/helper-a64.c
32
@@ -XXX,XX +XXX,XX @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
33
return float16_ ## name(a, b, fpst); \
34
}
35
36
+ADVSIMD_HALFOP(add)
37
+ADVSIMD_HALFOP(sub)
38
+ADVSIMD_HALFOP(mul)
39
+ADVSIMD_HALFOP(div)
40
ADVSIMD_HALFOP(min)
41
ADVSIMD_HALFOP(max)
42
ADVSIMD_HALFOP(minnum)
43
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/translate-a64.c
46
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
48
read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
49
50
switch (fpopcode) {
51
+ case 0x0: /* FMAXNM */
52
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
53
+ break;
54
+ case 0x2: /* FADD */
55
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
56
+ break;
57
+ case 0x6: /* FMAX */
58
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
59
+ break;
60
+ case 0x8: /* FMINNM */
61
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
62
+ break;
63
+ case 0xa: /* FSUB */
64
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
65
+ break;
66
+ case 0xe: /* FMIN */
67
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
68
+ break;
69
+ case 0x13: /* FMUL */
70
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
71
+ break;
72
+ case 0x17: /* FDIV */
73
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
74
+ break;
75
+ case 0x1a: /* FABD */
76
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
77
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
78
+ break;
79
default:
80
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
81
__func__, insn, fpopcode, s->pc);
82
--
83
2.16.2
84
85
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/42] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
These use the generic float16_compare functionality which in turn uses
4
the common float_compare code from the softfloat re-factor.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper-a64.h | 5 +++++
12
target/arm/helper-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++
13
target/arm/translate-a64.c | 15 ++++++++++++++
14
3 files changed, 69 insertions(+)
15
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
19
+++ b/target/arm/helper-a64.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
21
DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
22
DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
23
DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
24
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
25
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
26
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
27
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
28
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
29
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper-a64.c
32
+++ b/target/arm/helper-a64.c
33
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(min)
34
ADVSIMD_HALFOP(max)
35
ADVSIMD_HALFOP(minnum)
36
ADVSIMD_HALFOP(maxnum)
37
+
38
+/*
39
+ * Floating point comparisons produce an integer result. Softfloat
40
+ * routines return float_relation types which we convert to the 0/-1
41
+ * Neon requires.
42
+ */
43
+
44
+#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
45
+
46
+uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
47
+{
48
+ float_status *fpst = fpstp;
49
+ int compare = float16_compare_quiet(a, b, fpst);
50
+ return ADVSIMD_CMPRES(compare == float_relation_equal);
51
+}
52
+
53
+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
54
+{
55
+ float_status *fpst = fpstp;
56
+ int compare = float16_compare(a, b, fpst);
57
+ return ADVSIMD_CMPRES(compare == float_relation_greater ||
58
+ compare == float_relation_equal);
59
+}
60
+
61
+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
62
+{
63
+ float_status *fpst = fpstp;
64
+ int compare = float16_compare(a, b, fpst);
65
+ return ADVSIMD_CMPRES(compare == float_relation_greater);
66
+}
67
+
68
+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
69
+{
70
+ float_status *fpst = fpstp;
71
+ float16 f0 = float16_abs(a);
72
+ float16 f1 = float16_abs(b);
73
+ int compare = float16_compare(f0, f1, fpst);
74
+ return ADVSIMD_CMPRES(compare == float_relation_greater ||
75
+ compare == float_relation_equal);
76
+}
77
+
78
+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
79
+{
80
+ float_status *fpst = fpstp;
81
+ float16 f0 = float16_abs(a);
82
+ float16 f1 = float16_abs(b);
83
+ int compare = float16_compare(f0, f1, fpst);
84
+ return ADVSIMD_CMPRES(compare == float_relation_greater);
85
+}
86
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/translate-a64.c
89
+++ b/target/arm/translate-a64.c
90
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
91
case 0x2: /* FADD */
92
gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
93
break;
94
+ case 0x4: /* FCMEQ */
95
+ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
96
+ break;
97
case 0x6: /* FMAX */
98
gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
99
break;
100
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
101
case 0x13: /* FMUL */
102
gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
103
break;
104
+ case 0x14: /* FCMGE */
105
+ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
106
+ break;
107
+ case 0x15: /* FACGE */
108
+ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
109
+ break;
110
case 0x17: /* FDIV */
111
gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
112
break;
113
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
114
gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
115
tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
116
break;
117
+ case 0x1c: /* FCMGT */
118
+ gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
119
+ break;
120
+ case 0x1d: /* FACGT */
121
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
122
+ break;
123
default:
124
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
125
__func__, insn, fpopcode, s->pc);
126
--
127
2.16.2
128
129
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper-a64.h | 2 ++
9
target/arm/helper-a64.c | 24 ++++++++++++++++++++++++
10
target/arm/translate-a64.c | 15 +++++++++++++++
11
3 files changed, 41 insertions(+)
12
13
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper-a64.h
16
+++ b/target/arm/helper-a64.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
18
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
19
DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
20
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
21
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
22
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
23
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-a64.c
26
+++ b/target/arm/helper-a64.c
27
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
28
ADVSIMD_HALFOP(minnum)
29
ADVSIMD_HALFOP(maxnum)
30
31
+/* Data processing - scalar floating-point and advanced SIMD */
32
+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
33
+{
34
+ float_status *fpst = fpstp;
35
+
36
+ a = float16_squash_input_denormal(a, fpst);
37
+ b = float16_squash_input_denormal(b, fpst);
38
+
39
+ if ((float16_is_zero(a) && float16_is_infinity(b)) ||
40
+ (float16_is_infinity(a) && float16_is_zero(b))) {
41
+ /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
42
+ return make_float16((1U << 14) |
43
+ ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
44
+ }
45
+ return float16_mul(a, b, fpst);
46
+}
47
+
48
+/* fused multiply-accumulate */
49
+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
50
+{
51
+ float_status *fpst = fpstp;
52
+ return float16_muladd(a, b, c, 0, fpst);
53
+}
54
+
55
/*
56
* Floating point comparisons produce an integer result. Softfloat
57
* routines return float_relation types which we convert to the 0/-1
58
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-a64.c
61
+++ b/target/arm/translate-a64.c
62
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
63
case 0x0: /* FMAXNM */
64
gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
65
break;
66
+ case 0x1: /* FMLA */
67
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
68
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
69
+ fpst);
70
+ break;
71
case 0x2: /* FADD */
72
gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
73
break;
74
+ case 0x3: /* FMULX */
75
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
76
+ break;
77
case 0x4: /* FCMEQ */
78
gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
79
break;
80
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
81
case 0x8: /* FMINNM */
82
gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
83
break;
84
+ case 0x9: /* FMLS */
85
+ /* As usual for ARM, separate negation for fused multiply-add */
86
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
87
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
88
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
89
+ fpst);
90
+ break;
91
case 0xa: /* FSUB */
92
gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
93
break;
94
--
95
2.16.2
96
97
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/42] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
As some of the constants here will also be needed
4
elsewhere (specifically for the upcoming SVE support) we move them out
5
to softfloat.h.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/fpu/softfloat.h | 18 +++++++++++++-----
13
target/arm/helper-a64.h | 2 ++
14
target/arm/helper-a64.c | 34 ++++++++++++++++++++++++++++++++++
15
target/arm/translate-a64.c | 6 ++++++
16
4 files changed, 55 insertions(+), 5 deletions(-)
17
18
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/fpu/softfloat.h
21
+++ b/include/fpu/softfloat.h
22
@@ -XXX,XX +XXX,XX @@ static inline float16 float16_set_sign(float16 a, int sign)
23
}
24
25
#define float16_zero make_float16(0)
26
-#define float16_one make_float16(0x3c00)
27
#define float16_half make_float16(0x3800)
28
+#define float16_one make_float16(0x3c00)
29
+#define float16_one_point_five make_float16(0x3e00)
30
+#define float16_two make_float16(0x4000)
31
+#define float16_three make_float16(0x4200)
32
#define float16_infinity make_float16(0x7c00)
33
34
/*----------------------------------------------------------------------------
35
@@ -XXX,XX +XXX,XX @@ static inline float32 float32_set_sign(float32 a, int sign)
36
}
37
38
#define float32_zero make_float32(0)
39
-#define float32_one make_float32(0x3f800000)
40
#define float32_half make_float32(0x3f000000)
41
+#define float32_one make_float32(0x3f800000)
42
+#define float32_one_point_five make_float32(0x3fc00000)
43
+#define float32_two make_float32(0x40000000)
44
+#define float32_three make_float32(0x40400000)
45
#define float32_infinity make_float32(0x7f800000)
46
47
-
48
/*----------------------------------------------------------------------------
49
| The pattern for a default generated single-precision NaN.
50
*----------------------------------------------------------------------------*/
51
@@ -XXX,XX +XXX,XX @@ static inline float64 float64_set_sign(float64 a, int sign)
52
}
53
54
#define float64_zero make_float64(0)
55
-#define float64_one make_float64(0x3ff0000000000000LL)
56
-#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
57
#define float64_half make_float64(0x3fe0000000000000LL)
58
+#define float64_one make_float64(0x3ff0000000000000LL)
59
+#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
60
+#define float64_two make_float64(0x4000000000000000ULL)
61
+#define float64_three make_float64(0x4008000000000000ULL)
62
+#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
63
#define float64_infinity make_float64(0x7ff0000000000000LL)
64
65
/*----------------------------------------------------------------------------
66
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/helper-a64.h
69
+++ b/target/arm/helper-a64.h
70
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
71
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
72
DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
73
DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
74
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
75
DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
76
DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
77
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
78
DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
79
DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
80
DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
81
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/helper-a64.c
84
+++ b/target/arm/helper-a64.c
85
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
86
* versions, these do a fully fused multiply-add or
87
* multiply-add-and-halve.
88
*/
89
+#define float16_two make_float16(0x4000)
90
+#define float16_three make_float16(0x4200)
91
+#define float16_one_point_five make_float16(0x3e00)
92
+
93
#define float32_two make_float32(0x40000000)
94
#define float32_three make_float32(0x40400000)
95
#define float32_one_point_five make_float32(0x3fc00000)
96
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
97
#define float64_three make_float64(0x4008000000000000ULL)
98
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
99
100
+float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
101
+{
102
+ float_status *fpst = fpstp;
103
+
104
+ a = float16_squash_input_denormal(a, fpst);
105
+ b = float16_squash_input_denormal(b, fpst);
106
+
107
+ a = float16_chs(a);
108
+ if ((float16_is_infinity(a) && float16_is_zero(b)) ||
109
+ (float16_is_infinity(b) && float16_is_zero(a))) {
110
+ return float16_two;
111
+ }
112
+ return float16_muladd(a, b, float16_two, 0, fpst);
113
+}
114
+
115
float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
116
{
117
float_status *fpst = fpstp;
118
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
119
return float64_muladd(a, b, float64_two, 0, fpst);
120
}
121
122
+float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
123
+{
124
+ float_status *fpst = fpstp;
125
+
126
+ a = float16_squash_input_denormal(a, fpst);
127
+ b = float16_squash_input_denormal(b, fpst);
128
+
129
+ a = float16_chs(a);
130
+ if ((float16_is_infinity(a) && float16_is_zero(b)) ||
131
+ (float16_is_infinity(b) && float16_is_zero(a))) {
132
+ return float16_one_point_five;
133
+ }
134
+ return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
135
+}
136
+
137
float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
138
{
139
float_status *fpst = fpstp;
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/translate-a64.c
143
+++ b/target/arm/translate-a64.c
144
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
145
case 0x6: /* FMAX */
146
gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
147
break;
148
+ case 0x7: /* FRECPS */
149
+ gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
150
+ break;
151
case 0x8: /* FMINNM */
152
gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
153
break;
154
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
155
case 0xe: /* FMIN */
156
gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
157
break;
158
+ case 0xf: /* FRSQRTS */
159
+ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
160
+ break;
161
case 0x13: /* FMUL */
162
gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
163
break;
164
--
165
2.16.2
166
167
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.
4
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++----------------
11
1 file changed, 133 insertions(+), 75 deletions(-)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
18
int datasize, elements;
19
int pass;
20
TCGv_ptr fpst;
21
+ bool pairwise = false;
22
23
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
24
unallocated_encoding(s);
25
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
26
datasize = is_q ? 128 : 64;
27
elements = datasize / 16;
28
29
+ switch (fpopcode) {
30
+ case 0x10: /* FMAXNMP */
31
+ case 0x12: /* FADDP */
32
+ case 0x16: /* FMAXP */
33
+ case 0x18: /* FMINNMP */
34
+ case 0x1e: /* FMINP */
35
+ pairwise = true;
36
+ break;
37
+ }
38
+
39
fpst = get_fpstatus_ptr(true);
40
41
- for (pass = 0; pass < elements; pass++) {
42
+ if (pairwise) {
43
+ int maxpass = is_q ? 8 : 4;
44
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
45
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
46
- TCGv_i32 tcg_res = tcg_temp_new_i32();
47
+ TCGv_i32 tcg_res[8];
48
49
- read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
50
- read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
51
+ for (pass = 0; pass < maxpass; pass++) {
52
+ int passreg = pass < (maxpass / 2) ? rn : rm;
53
+ int passelt = (pass << 1) & (maxpass - 1);
54
55
- switch (fpopcode) {
56
- case 0x0: /* FMAXNM */
57
- gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
- break;
59
- case 0x1: /* FMLA */
60
- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
61
- gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
62
- fpst);
63
- break;
64
- case 0x2: /* FADD */
65
- gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
66
- break;
67
- case 0x3: /* FMULX */
68
- gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
69
- break;
70
- case 0x4: /* FCMEQ */
71
- gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
72
- break;
73
- case 0x6: /* FMAX */
74
- gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
75
- break;
76
- case 0x7: /* FRECPS */
77
- gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
78
- break;
79
- case 0x8: /* FMINNM */
80
- gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
81
- break;
82
- case 0x9: /* FMLS */
83
- /* As usual for ARM, separate negation for fused multiply-add */
84
- tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
85
- read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
86
- gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
87
- fpst);
88
- break;
89
- case 0xa: /* FSUB */
90
- gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
91
- break;
92
- case 0xe: /* FMIN */
93
- gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
94
- break;
95
- case 0xf: /* FRSQRTS */
96
- gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
97
- break;
98
- case 0x13: /* FMUL */
99
- gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
100
- break;
101
- case 0x14: /* FCMGE */
102
- gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
103
- break;
104
- case 0x15: /* FACGE */
105
- gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
106
- break;
107
- case 0x17: /* FDIV */
108
- gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
109
- break;
110
- case 0x1a: /* FABD */
111
- gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
112
- tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
113
- break;
114
- case 0x1c: /* FCMGT */
115
- gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
116
- break;
117
- case 0x1d: /* FACGT */
118
- gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
119
- break;
120
- default:
121
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
122
- __func__, insn, fpopcode, s->pc);
123
- g_assert_not_reached();
124
+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
125
+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
126
+ tcg_res[pass] = tcg_temp_new_i32();
127
+
128
+ switch (fpopcode) {
129
+ case 0x10: /* FMAXNMP */
130
+ gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
131
+ fpst);
132
+ break;
133
+ case 0x12: /* FADDP */
134
+ gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
135
+ break;
136
+ case 0x16: /* FMAXP */
137
+ gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
138
+ break;
139
+ case 0x18: /* FMINNMP */
140
+ gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
141
+ fpst);
142
+ break;
143
+ case 0x1e: /* FMINP */
144
+ gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
145
+ break;
146
+ default:
147
+ g_assert_not_reached();
148
+ }
149
+ }
150
+
151
+ for (pass = 0; pass < maxpass; pass++) {
152
+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
153
+ tcg_temp_free_i32(tcg_res[pass]);
154
}
155
156
- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
157
- tcg_temp_free_i32(tcg_res);
158
tcg_temp_free_i32(tcg_op1);
159
tcg_temp_free_i32(tcg_op2);
160
+
161
+ } else {
162
+ for (pass = 0; pass < elements; pass++) {
163
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
164
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
165
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
166
+
167
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
168
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
169
+
170
+ switch (fpopcode) {
171
+ case 0x0: /* FMAXNM */
172
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
173
+ break;
174
+ case 0x1: /* FMLA */
175
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
176
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
177
+ fpst);
178
+ break;
179
+ case 0x2: /* FADD */
180
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
181
+ break;
182
+ case 0x3: /* FMULX */
183
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
184
+ break;
185
+ case 0x4: /* FCMEQ */
186
+ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
187
+ break;
188
+ case 0x6: /* FMAX */
189
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
190
+ break;
191
+ case 0x7: /* FRECPS */
192
+ gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
193
+ break;
194
+ case 0x8: /* FMINNM */
195
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
196
+ break;
197
+ case 0x9: /* FMLS */
198
+ /* As usual for ARM, separate negation for fused multiply-add */
199
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
200
+ read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
201
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
202
+ fpst);
203
+ break;
204
+ case 0xa: /* FSUB */
205
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
206
+ break;
207
+ case 0xe: /* FMIN */
208
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
209
+ break;
210
+ case 0xf: /* FRSQRTS */
211
+ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
212
+ break;
213
+ case 0x13: /* FMUL */
214
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
215
+ break;
216
+ case 0x14: /* FCMGE */
217
+ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
218
+ break;
219
+ case 0x15: /* FACGE */
220
+ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
221
+ break;
222
+ case 0x17: /* FDIV */
223
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
224
+ break;
225
+ case 0x1a: /* FABD */
226
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
227
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
228
+ break;
229
+ case 0x1c: /* FCMGT */
230
+ gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
231
+ break;
232
+ case 0x1d: /* FACGT */
233
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
234
+ break;
235
+ default:
236
+ fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
237
+ __func__, insn, fpopcode, s->pc);
238
+ g_assert_not_reached();
239
+ }
240
+
241
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
242
+ tcg_temp_free_i32(tcg_res);
243
+ tcg_temp_free_i32(tcg_op1);
244
+ tcg_temp_free_i32(tcg_op2);
245
+ }
246
}
247
248
tcg_temp_free_ptr(fpst);
249
--
250
2.16.2
251
252
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
The helpers use the new re-factored muladd support in SoftFloat for
4
the float16 work.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180227143852.11175-15-alex.bennee@linaro.org
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++---------
12
1 file changed, 66 insertions(+), 16 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
19
int rd = extract32(insn, 0, 5);
20
bool is_long = false;
21
bool is_fp = false;
22
+ bool is_fp16 = false;
23
int index;
24
TCGv_ptr fpst;
25
26
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
27
}
28
/* fall through */
29
case 0x9: /* FMUL, FMULX */
30
- if (!extract32(size, 1, 1)) {
31
+ if (size == 1) {
32
unallocated_encoding(s);
33
return;
34
}
35
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
36
}
37
38
if (is_fp) {
39
- /* low bit of size indicates single/double */
40
- size = extract32(size, 0, 1) ? 3 : 2;
41
- if (size == 2) {
42
+ /* convert insn encoded size to TCGMemOp size */
43
+ switch (size) {
44
+ case 2: /* single precision */
45
+ size = MO_32;
46
index = h << 1 | l;
47
- } else {
48
+ rm |= (m << 4);
49
+ break;
50
+ case 3: /* double precision */
51
+ size = MO_64;
52
if (l || !is_q) {
53
unallocated_encoding(s);
54
return;
55
}
56
index = h;
57
+ rm |= (m << 4);
58
+ break;
59
+ case 0: /* half precision */
60
+ size = MO_16;
61
+ index = h << 2 | l << 1 | m;
62
+ is_fp16 = true;
63
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
64
+ break;
65
+ }
66
+ /* fallthru */
67
+ default: /* unallocated */
68
+ unallocated_encoding(s);
69
+ return;
70
}
71
- rm |= (m << 4);
72
} else {
73
switch (size) {
74
case 1:
75
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
76
}
77
78
if (is_fp) {
79
- fpst = get_fpstatus_ptr(false);
80
+ fpst = get_fpstatus_ptr(is_fp16);
81
} else {
82
fpst = NULL;
83
}
84
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
85
break;
86
}
87
case 0x5: /* FMLS */
88
- /* As usual for ARM, separate negation for fused multiply-add */
89
- gen_helper_vfp_negs(tcg_op, tcg_op);
90
- /* fall through */
91
case 0x1: /* FMLA */
92
- read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
93
- gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
94
+ read_vec_element_i32(s, tcg_res, rd, pass,
95
+ is_scalar ? size : MO_32);
96
+ switch (size) {
97
+ case 1:
98
+ if (opcode == 0x5) {
99
+ /* As usual for ARM, separate negation for fused
100
+ * multiply-add */
101
+ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
102
+ }
103
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
104
+ tcg_res, fpst);
105
+ break;
106
+ case 2:
107
+ if (opcode == 0x5) {
108
+ /* As usual for ARM, separate negation for
109
+ * fused multiply-add */
110
+ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
111
+ }
112
+ gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
113
+ tcg_res, fpst);
114
+ break;
115
+ default:
116
+ g_assert_not_reached();
117
+ }
118
break;
119
case 0x9: /* FMUL, FMULX */
120
- if (u) {
121
- gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
122
- } else {
123
- gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
124
+ switch (size) {
125
+ case 1:
126
+ if (u) {
127
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
128
+ fpst);
129
+ } else {
130
+ g_assert_not_reached();
131
+ }
132
+ break;
133
+ case 2:
134
+ if (u) {
135
+ gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
136
+ } else {
137
+ gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
138
+ }
139
+ break;
140
+ default:
141
+ g_assert_not_reached();
142
}
143
break;
144
case 0xc: /* SQDMULH */
145
--
146
2.16.2
147
148
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
A bunch of the vectorised bitwise operations just operate on larger
4
chunks at a time. We can do the same for the new half-precision
5
operations by introducing some TWOHALFOP helpers which work on each
6
half of a pair of half-precision operations at once.
7
8
Hopefully all this hoop jumping will get simpler once we have
9
generically vectorised helpers here.
10
11
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/helper-a64.h | 10 ++++++++++
17
target/arm/helper-a64.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
18
target/arm/translate-a64.c | 26 +++++++++++++++++++++-----
19
3 files changed, 76 insertions(+), 6 deletions(-)
20
21
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper-a64.h
24
+++ b/target/arm/helper-a64.h
25
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
26
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
27
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
28
DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
29
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
30
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
31
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
32
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
33
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
34
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
35
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
36
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
37
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
38
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
39
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper-a64.c
42
+++ b/target/arm/helper-a64.c
43
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
44
ADVSIMD_HALFOP(minnum)
45
ADVSIMD_HALFOP(maxnum)
46
47
+#define ADVSIMD_TWOHALFOP(name) \
48
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
49
+{ \
50
+ float16 a1, a2, b1, b2; \
51
+ uint32_t r1, r2; \
52
+ float_status *fpst = fpstp; \
53
+ a1 = extract32(two_a, 0, 16); \
54
+ a2 = extract32(two_a, 16, 16); \
55
+ b1 = extract32(two_b, 0, 16); \
56
+ b2 = extract32(two_b, 16, 16); \
57
+ r1 = float16_ ## name(a1, b1, fpst); \
58
+ r2 = float16_ ## name(a2, b2, fpst); \
59
+ return deposit32(r1, 16, 16, r2); \
60
+}
61
+
62
+ADVSIMD_TWOHALFOP(add)
63
+ADVSIMD_TWOHALFOP(sub)
64
+ADVSIMD_TWOHALFOP(mul)
65
+ADVSIMD_TWOHALFOP(div)
66
+ADVSIMD_TWOHALFOP(min)
67
+ADVSIMD_TWOHALFOP(max)
68
+ADVSIMD_TWOHALFOP(minnum)
69
+ADVSIMD_TWOHALFOP(maxnum)
70
+
71
/* Data processing - scalar floating-point and advanced SIMD */
72
-float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
73
+static float16 float16_mulx(float16 a, float16 b, void *fpstp)
74
{
75
float_status *fpst = fpstp;
76
77
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
78
return float16_mul(a, b, fpst);
79
}
80
81
+ADVSIMD_HALFOP(mulx)
82
+ADVSIMD_TWOHALFOP(mulx)
83
+
84
/* fused multiply-accumulate */
85
float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
86
{
87
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
88
return float16_muladd(a, b, c, 0, fpst);
89
}
90
91
+uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
92
+ uint32_t two_c, void *fpstp)
93
+{
94
+ float_status *fpst = fpstp;
95
+ float16 a1, a2, b1, b2, c1, c2;
96
+ uint32_t r1, r2;
97
+ a1 = extract32(two_a, 0, 16);
98
+ a2 = extract32(two_a, 16, 16);
99
+ b1 = extract32(two_b, 0, 16);
100
+ b2 = extract32(two_b, 16, 16);
101
+ c1 = extract32(two_c, 0, 16);
102
+ c2 = extract32(two_c, 16, 16);
103
+ r1 = float16_muladd(a1, b1, c1, 0, fpst);
104
+ r2 = float16_muladd(a2, b2, c2, 0, fpst);
105
+ return deposit32(r1, 16, 16, r2);
106
+}
107
+
108
/*
109
* Floating point comparisons produce an integer result. Softfloat
110
* routines return float_relation types which we convert to the 0/-1
111
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/translate-a64.c
114
+++ b/target/arm/translate-a64.c
115
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
116
* multiply-add */
117
tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
118
}
119
- gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
120
- tcg_res, fpst);
121
+ if (is_scalar) {
122
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
123
+ tcg_res, fpst);
124
+ } else {
125
+ gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
126
+ tcg_res, fpst);
127
+ }
128
break;
129
case 2:
130
if (opcode == 0x5) {
131
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
132
switch (size) {
133
case 1:
134
if (u) {
135
- gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
136
- fpst);
137
+ if (is_scalar) {
138
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op,
139
+ tcg_idx, fpst);
140
+ } else {
141
+ gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
142
+ tcg_idx, fpst);
143
+ }
144
} else {
145
- g_assert_not_reached();
146
+ if (is_scalar) {
147
+ gen_helper_advsimd_mulh(tcg_res, tcg_op,
148
+ tcg_idx, fpst);
149
+ } else {
150
+ gen_helper_advsimd_mul2h(tcg_res, tcg_op,
151
+ tcg_idx, fpst);
152
+ }
153
}
154
break;
155
case 2:
156
--
157
2.16.2
158
159
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This actually covers two different sections of the encoding table:
4
5
Advanced SIMD scalar two-register miscellaneous FP16
6
Advanced SIMD two-register miscellaneous (FP16)
7
8
The difference between the two is covered by a combination of Q (bit
9
30) and S (bit 28). Notably the FRINTx instructions are only
10
available in the vector form.
11
12
This is just the decode skeleton which will be filled out by later
13
patches.
14
15
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++
21
1 file changed, 40 insertions(+)
22
23
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/translate-a64.c
26
+++ b/target/arm/translate-a64.c
27
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
28
}
29
}
30
31
+/* AdvSIMD [scalar] two register miscellaneous (FP16)
32
+ *
33
+ * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
34
+ * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
35
+ * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
36
+ * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
37
+ * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
38
+ * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
39
+ *
40
+ * This actually covers two groups where scalar access is governed by
41
+ * bit 28. A bunch of the instructions (float to integral) only exist
42
+ * in the vector form and are un-allocated for the scalar decode. Also
43
+ * in the scalar decode Q is always 1.
44
+ */
45
+static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
46
+{
47
+ int fpop, opcode, a;
48
+
49
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
50
+ unallocated_encoding(s);
51
+ return;
52
+ }
53
+
54
+ if (!fp_access_check(s)) {
55
+ return;
56
+ }
57
+
58
+ opcode = extract32(insn, 12, 4);
59
+ a = extract32(insn, 23, 1);
60
+ fpop = deposit32(opcode, 5, 1, a);
61
+
62
+ switch (fpop) {
63
+ default:
64
+ fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
65
+ g_assert_not_reached();
66
+ }
67
+
68
+}
69
+
70
/* AdvSIMD scalar x indexed element
71
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
72
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
73
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
74
{ 0xce800000, 0xffe00000, disas_crypto_xar },
75
{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
76
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
77
+ { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
78
{ 0x00000000, 0x00000000, NULL }
79
};
80
81
--
82
2.16.2
83
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This adds the full range of half-precision floating point to integral
4
instructions.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper-a64.h | 2 +
12
target/arm/helper-a64.c | 22 ++++++++
13
target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++++--
14
3 files changed, 142 insertions(+), 5 deletions(-)
15
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
19
+++ b/target/arm/helper-a64.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
21
DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
22
DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
23
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
24
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
25
+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
26
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/helper-a64.c
29
+++ b/target/arm/helper-a64.c
30
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
31
int compare = float16_compare(f0, f1, fpst);
32
return ADVSIMD_CMPRES(compare == float_relation_greater);
33
}
34
+
35
+/* round to integral */
36
+float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
37
+{
38
+ return float16_round_to_int(x, fp_status);
39
+}
40
+
41
+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
42
+{
43
+ int old_flags = get_float_exception_flags(fp_status), new_flags;
44
+ float16 ret;
45
+
46
+ ret = float16_round_to_int(x, fp_status);
47
+
48
+ /* Suppress any inexact exceptions the conversion produced */
49
+ if (!(old_flags & float_flag_inexact)) {
50
+ new_flags = get_float_exception_flags(fp_status);
51
+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
52
+ }
53
+
54
+ return ret;
55
+}
56
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/translate-a64.c
59
+++ b/target/arm/translate-a64.c
60
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
61
*/
62
static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
63
{
64
- int fpop, opcode, a;
65
+ int fpop, opcode, a, u;
66
+ int rn, rd;
67
+ bool is_q;
68
+ bool is_scalar;
69
+ bool only_in_vector = false;
70
+
71
+ int pass;
72
+ TCGv_i32 tcg_rmode = NULL;
73
+ TCGv_ptr tcg_fpstatus = NULL;
74
+ bool need_rmode = false;
75
+ int rmode;
76
77
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
78
unallocated_encoding(s);
79
return;
80
}
81
82
- if (!fp_access_check(s)) {
83
- return;
84
- }
85
+ rd = extract32(insn, 0, 5);
86
+ rn = extract32(insn, 5, 5);
87
88
- opcode = extract32(insn, 12, 4);
89
a = extract32(insn, 23, 1);
90
+ u = extract32(insn, 29, 1);
91
+ is_scalar = extract32(insn, 28, 1);
92
+ is_q = extract32(insn, 30, 1);
93
+
94
+ opcode = extract32(insn, 12, 5);
95
fpop = deposit32(opcode, 5, 1, a);
96
+ fpop = deposit32(fpop, 6, 1, u);
97
98
switch (fpop) {
99
+ case 0x18: /* FRINTN */
100
+ need_rmode = true;
101
+ only_in_vector = true;
102
+ rmode = FPROUNDING_TIEEVEN;
103
+ break;
104
+ case 0x19: /* FRINTM */
105
+ need_rmode = true;
106
+ only_in_vector = true;
107
+ rmode = FPROUNDING_NEGINF;
108
+ break;
109
+ case 0x38: /* FRINTP */
110
+ need_rmode = true;
111
+ only_in_vector = true;
112
+ rmode = FPROUNDING_POSINF;
113
+ break;
114
+ case 0x39: /* FRINTZ */
115
+ need_rmode = true;
116
+ only_in_vector = true;
117
+ rmode = FPROUNDING_ZERO;
118
+ break;
119
+ case 0x58: /* FRINTA */
120
+ need_rmode = true;
121
+ only_in_vector = true;
122
+ rmode = FPROUNDING_TIEAWAY;
123
+ break;
124
+ case 0x59: /* FRINTX */
125
+ case 0x79: /* FRINTI */
126
+ only_in_vector = true;
127
+ /* current rounding mode */
128
+ break;
129
default:
130
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
131
g_assert_not_reached();
132
}
133
134
+
135
+ /* Check additional constraints for the scalar encoding */
136
+ if (is_scalar) {
137
+ if (!is_q) {
138
+ unallocated_encoding(s);
139
+ return;
140
+ }
141
+ /* FRINTxx is only in the vector form */
142
+ if (only_in_vector) {
143
+ unallocated_encoding(s);
144
+ return;
145
+ }
146
+ }
147
+
148
+ if (!fp_access_check(s)) {
149
+ return;
150
+ }
151
+
152
+ if (need_rmode) {
153
+ tcg_fpstatus = get_fpstatus_ptr(true);
154
+ }
155
+
156
+ if (need_rmode) {
157
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
158
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
159
+ }
160
+
161
+ if (is_scalar) {
162
+ /* no operations yet */
163
+ } else {
164
+ for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
165
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
166
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
167
+
168
+ read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
169
+
170
+ switch (fpop) {
171
+ case 0x18: /* FRINTN */
172
+ case 0x19: /* FRINTM */
173
+ case 0x38: /* FRINTP */
174
+ case 0x39: /* FRINTZ */
175
+ case 0x58: /* FRINTA */
176
+ case 0x79: /* FRINTI */
177
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
178
+ break;
179
+ case 0x59: /* FRINTX */
180
+ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
181
+ break;
182
+ default:
183
+ g_assert_not_reached();
184
+ }
185
+
186
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
187
+
188
+ tcg_temp_free_i32(tcg_res);
189
+ tcg_temp_free_i32(tcg_op);
190
+ }
191
+
192
+ clear_vec_high(s, is_q, rd);
193
+ }
194
+
195
+ if (tcg_rmode) {
196
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
197
+ tcg_temp_free_i32(tcg_rmode);
198
+ }
199
+
200
+ if (tcg_fpstatus) {
201
+ tcg_temp_free_ptr(tcg_fpstatus);
202
+ }
203
}
204
205
/* AdvSIMD scalar x indexed element
206
--
207
2.16.2
208
209
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This covers all the floating point convert operations.
4
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper-a64.h | 2 ++
11
target/arm/helper-a64.c | 32 +++++++++++++++++
12
target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++-
13
3 files changed, 118 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.h
18
+++ b/target/arm/helper-a64.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
20
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
21
DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
22
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
23
+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
24
+DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
25
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper-a64.c
28
+++ b/target/arm/helper-a64.c
29
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
30
31
return ret;
32
}
33
+
34
+/*
35
+ * Half-precision floating point conversion functions
36
+ *
37
+ * There are a multitude of conversion functions with various
38
+ * different rounding modes. This is dealt with by the calling code
39
+ * setting the mode appropriately before calling the helper.
40
+ */
41
+
42
+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
43
+{
44
+ float_status *fpst = fpstp;
45
+
46
+ /* Invalid if we are passed a NaN */
47
+ if (float16_is_any_nan(a)) {
48
+ float_raise(float_flag_invalid, fpst);
49
+ return 0;
50
+ }
51
+ return float16_to_int16(a, fpst);
52
+}
53
+
54
+uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
55
+{
56
+ float_status *fpst = fpstp;
57
+
58
+ /* Invalid if we are passed a NaN */
59
+ if (float16_is_any_nan(a)) {
60
+ float_raise(float_flag_invalid, fpst);
61
+ return 0;
62
+ }
63
+ return float16_to_uint16(a, fpst);
64
+}
65
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/translate-a64.c
68
+++ b/target/arm/translate-a64.c
69
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
70
only_in_vector = true;
71
/* current rounding mode */
72
break;
73
+ case 0x1a: /* FCVTNS */
74
+ need_rmode = true;
75
+ rmode = FPROUNDING_TIEEVEN;
76
+ break;
77
+ case 0x1b: /* FCVTMS */
78
+ need_rmode = true;
79
+ rmode = FPROUNDING_NEGINF;
80
+ break;
81
+ case 0x1c: /* FCVTAS */
82
+ need_rmode = true;
83
+ rmode = FPROUNDING_TIEAWAY;
84
+ break;
85
+ case 0x3a: /* FCVTPS */
86
+ need_rmode = true;
87
+ rmode = FPROUNDING_POSINF;
88
+ break;
89
+ case 0x3b: /* FCVTZS */
90
+ need_rmode = true;
91
+ rmode = FPROUNDING_ZERO;
92
+ break;
93
+ case 0x5a: /* FCVTNU */
94
+ need_rmode = true;
95
+ rmode = FPROUNDING_TIEEVEN;
96
+ break;
97
+ case 0x5b: /* FCVTMU */
98
+ need_rmode = true;
99
+ rmode = FPROUNDING_NEGINF;
100
+ break;
101
+ case 0x5c: /* FCVTAU */
102
+ need_rmode = true;
103
+ rmode = FPROUNDING_TIEAWAY;
104
+ break;
105
+ case 0x7a: /* FCVTPU */
106
+ need_rmode = true;
107
+ rmode = FPROUNDING_POSINF;
108
+ break;
109
+ case 0x7b: /* FCVTZU */
110
+ need_rmode = true;
111
+ rmode = FPROUNDING_ZERO;
112
+ break;
113
default:
114
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
115
g_assert_not_reached();
116
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
117
}
118
119
if (is_scalar) {
120
- /* no operations yet */
121
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
122
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
123
+
124
+ read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
125
+
126
+ switch (fpop) {
127
+ case 0x1a: /* FCVTNS */
128
+ case 0x1b: /* FCVTMS */
129
+ case 0x1c: /* FCVTAS */
130
+ case 0x3a: /* FCVTPS */
131
+ case 0x3b: /* FCVTZS */
132
+ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
133
+ break;
134
+ case 0x5a: /* FCVTNU */
135
+ case 0x5b: /* FCVTMU */
136
+ case 0x5c: /* FCVTAU */
137
+ case 0x7a: /* FCVTPU */
138
+ case 0x7b: /* FCVTZU */
139
+ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
140
+ break;
141
+ default:
142
+ g_assert_not_reached();
143
+ }
144
+
145
+ /* limit any sign extension going on */
146
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
147
+ write_fp_sreg(s, rd, tcg_res);
148
+
149
+ tcg_temp_free_i32(tcg_res);
150
+ tcg_temp_free_i32(tcg_op);
151
} else {
152
for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
153
TCGv_i32 tcg_op = tcg_temp_new_i32();
154
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
155
read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
156
157
switch (fpop) {
158
+ case 0x1a: /* FCVTNS */
159
+ case 0x1b: /* FCVTMS */
160
+ case 0x1c: /* FCVTAS */
161
+ case 0x3a: /* FCVTPS */
162
+ case 0x3b: /* FCVTZS */
163
+ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
164
+ break;
165
+ case 0x5a: /* FCVTNU */
166
+ case 0x5b: /* FCVTMU */
167
+ case 0x5c: /* FCVTAU */
168
+ case 0x7a: /* FCVTPU */
169
+ case 0x7b: /* FCVTZU */
170
+ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
171
+ break;
172
case 0x18: /* FRINTN */
173
case 0x19: /* FRINTM */
174
case 0x38: /* FRINTP */
175
--
176
2.16.2
177
178
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
4
slightly to deal with the half-precision case.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++-------------
12
1 file changed, 57 insertions(+), 23 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
19
bool is_scalar, bool is_u, bool is_q,
20
int size, int rn, int rd)
21
{
22
- bool is_double = (size == 3);
23
+ bool is_double = (size == MO_64);
24
TCGv_ptr fpst;
25
26
if (!fp_access_check(s)) {
27
return;
28
}
29
30
- fpst = get_fpstatus_ptr(false);
31
+ fpst = get_fpstatus_ptr(size == MO_16);
32
33
if (is_double) {
34
TCGv_i64 tcg_op = tcg_temp_new_i64();
35
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
36
bool swap = false;
37
int pass, maxpasses;
38
39
- switch (opcode) {
40
- case 0x2e: /* FCMLT (zero) */
41
- swap = true;
42
- /* fall through */
43
- case 0x2c: /* FCMGT (zero) */
44
- genfn = gen_helper_neon_cgt_f32;
45
- break;
46
- case 0x2d: /* FCMEQ (zero) */
47
- genfn = gen_helper_neon_ceq_f32;
48
- break;
49
- case 0x6d: /* FCMLE (zero) */
50
- swap = true;
51
- /* fall through */
52
- case 0x6c: /* FCMGE (zero) */
53
- genfn = gen_helper_neon_cge_f32;
54
- break;
55
- default:
56
- g_assert_not_reached();
57
+ if (size == MO_16) {
58
+ switch (opcode) {
59
+ case 0x2e: /* FCMLT (zero) */
60
+ swap = true;
61
+ /* fall through */
62
+ case 0x2c: /* FCMGT (zero) */
63
+ genfn = gen_helper_advsimd_cgt_f16;
64
+ break;
65
+ case 0x2d: /* FCMEQ (zero) */
66
+ genfn = gen_helper_advsimd_ceq_f16;
67
+ break;
68
+ case 0x6d: /* FCMLE (zero) */
69
+ swap = true;
70
+ /* fall through */
71
+ case 0x6c: /* FCMGE (zero) */
72
+ genfn = gen_helper_advsimd_cge_f16;
73
+ break;
74
+ default:
75
+ g_assert_not_reached();
76
+ }
77
+ } else {
78
+ switch (opcode) {
79
+ case 0x2e: /* FCMLT (zero) */
80
+ swap = true;
81
+ /* fall through */
82
+ case 0x2c: /* FCMGT (zero) */
83
+ genfn = gen_helper_neon_cgt_f32;
84
+ break;
85
+ case 0x2d: /* FCMEQ (zero) */
86
+ genfn = gen_helper_neon_ceq_f32;
87
+ break;
88
+ case 0x6d: /* FCMLE (zero) */
89
+ swap = true;
90
+ /* fall through */
91
+ case 0x6c: /* FCMGE (zero) */
92
+ genfn = gen_helper_neon_cge_f32;
93
+ break;
94
+ default:
95
+ g_assert_not_reached();
96
+ }
97
}
98
99
if (is_scalar) {
100
maxpasses = 1;
101
} else {
102
- maxpasses = is_q ? 4 : 2;
103
+ int vector_size = 8 << is_q;
104
+ maxpasses = vector_size >> size;
105
}
106
107
for (pass = 0; pass < maxpasses; pass++) {
108
- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
109
+ read_vec_element_i32(s, tcg_op, rn, pass, size);
110
if (swap) {
111
genfn(tcg_res, tcg_zero, tcg_op, fpst);
112
} else {
113
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
114
if (is_scalar) {
115
write_fp_sreg(s, rd, tcg_res);
116
} else {
117
- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
118
+ write_vec_element_i32(s, tcg_res, rd, pass, size);
119
}
120
}
121
tcg_temp_free_i32(tcg_res);
122
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
123
fpop = deposit32(opcode, 5, 1, a);
124
fpop = deposit32(fpop, 6, 1, u);
125
126
+ rd = extract32(insn, 0, 5);
127
+ rn = extract32(insn, 5, 5);
128
+
129
switch (fpop) {
130
+ break;
131
+ case 0x2c: /* FCMGT (zero) */
132
+ case 0x2d: /* FCMEQ (zero) */
133
+ case 0x2e: /* FCMLT (zero) */
134
+ case 0x6c: /* FCMGE (zero) */
135
+ case 0x6d: /* FCMLE (zero) */
136
+ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
137
+ return;
138
case 0x18: /* FRINTN */
139
need_rmode = true;
140
only_in_vector = true;
141
--
142
2.16.2
143
144
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
I've re-factored the handle_simd_intfp_conv helper to properly handle
4
half-precision as well as call plain conversion helpers when we are
5
not doing fixed point conversion.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.h | 10 ++++
13
target/arm/helper.c | 4 ++
14
target/arm/translate-a64.c | 122 ++++++++++++++++++++++++++++++++++-----------
15
3 files changed, 108 insertions(+), 28 deletions(-)
16
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.h
20
+++ b/target/arm/helper.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
22
DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
23
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
24
25
+DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
26
DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
27
DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
28
+DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
29
DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
30
DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
31
32
+DEF_HELPER_2(vfp_touih, i32, f16, ptr)
33
DEF_HELPER_2(vfp_touis, i32, f32, ptr)
34
DEF_HELPER_2(vfp_touid, i32, f64, ptr)
35
+DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
36
DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
37
DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
38
+DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
39
DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
40
DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
41
+DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
42
DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
43
DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
44
45
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
46
DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
47
DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
48
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
49
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
50
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
51
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
52
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
53
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
55
DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
56
DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
57
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
58
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
59
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
60
61
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
62
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
63
diff --git a/target/arm/helper.c b/target/arm/helper.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/helper.c
66
+++ b/target/arm/helper.c
67
@@ -XXX,XX +XXX,XX @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
68
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
69
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
70
71
+FLOAT_CONVS(si, h, 16, )
72
FLOAT_CONVS(si, s, 32, )
73
FLOAT_CONVS(si, d, 64, )
74
+FLOAT_CONVS(ui, h, 16, u)
75
FLOAT_CONVS(ui, s, 32, u)
76
FLOAT_CONVS(ui, d, 64, u)
77
78
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
79
VFP_CONV_FIX(uh, s, 32, 32, uint16)
80
VFP_CONV_FIX(ul, s, 32, 32, uint32)
81
VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
82
+VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
83
+VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
84
#undef VFP_CONV_FIX
85
#undef VFP_CONV_FIX_FLOAT
86
#undef VFP_CONV_FLOAT_FIX_ROUND
87
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/translate-a64.c
90
+++ b/target/arm/translate-a64.c
91
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
92
int elements, int is_signed,
93
int fracbits, int size)
94
{
95
- bool is_double = size == 3 ? true : false;
96
- TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
97
- TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
98
- TCGv_i64 tcg_int = tcg_temp_new_i64();
99
+ TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
100
+ TCGv_i32 tcg_shift = NULL;
101
+
102
TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
103
int pass;
104
105
- for (pass = 0; pass < elements; pass++) {
106
- read_vec_element(s, tcg_int, rn, pass, mop);
107
+ if (fracbits || size == MO_64) {
108
+ tcg_shift = tcg_const_i32(fracbits);
109
+ }
110
+
111
+ if (size == MO_64) {
112
+ TCGv_i64 tcg_int64 = tcg_temp_new_i64();
113
+ TCGv_i64 tcg_double = tcg_temp_new_i64();
114
+
115
+ for (pass = 0; pass < elements; pass++) {
116
+ read_vec_element(s, tcg_int64, rn, pass, mop);
117
118
- if (is_double) {
119
- TCGv_i64 tcg_double = tcg_temp_new_i64();
120
if (is_signed) {
121
- gen_helper_vfp_sqtod(tcg_double, tcg_int,
122
+ gen_helper_vfp_sqtod(tcg_double, tcg_int64,
123
tcg_shift, tcg_fpst);
124
} else {
125
- gen_helper_vfp_uqtod(tcg_double, tcg_int,
126
+ gen_helper_vfp_uqtod(tcg_double, tcg_int64,
127
tcg_shift, tcg_fpst);
128
}
129
if (elements == 1) {
130
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
131
} else {
132
write_vec_element(s, tcg_double, rd, pass, MO_64);
133
}
134
- tcg_temp_free_i64(tcg_double);
135
- } else {
136
- TCGv_i32 tcg_single = tcg_temp_new_i32();
137
- if (is_signed) {
138
- gen_helper_vfp_sqtos(tcg_single, tcg_int,
139
- tcg_shift, tcg_fpst);
140
- } else {
141
- gen_helper_vfp_uqtos(tcg_single, tcg_int,
142
- tcg_shift, tcg_fpst);
143
- }
144
- if (elements == 1) {
145
- write_fp_sreg(s, rd, tcg_single);
146
- } else {
147
- write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
148
- }
149
- tcg_temp_free_i32(tcg_single);
150
}
151
+
152
+ tcg_temp_free_i64(tcg_int64);
153
+ tcg_temp_free_i64(tcg_double);
154
+
155
+ } else {
156
+ TCGv_i32 tcg_int32 = tcg_temp_new_i32();
157
+ TCGv_i32 tcg_float = tcg_temp_new_i32();
158
+
159
+ for (pass = 0; pass < elements; pass++) {
160
+ read_vec_element_i32(s, tcg_int32, rn, pass, mop);
161
+
162
+ switch (size) {
163
+ case MO_32:
164
+ if (fracbits) {
165
+ if (is_signed) {
166
+ gen_helper_vfp_sltos(tcg_float, tcg_int32,
167
+ tcg_shift, tcg_fpst);
168
+ } else {
169
+ gen_helper_vfp_ultos(tcg_float, tcg_int32,
170
+ tcg_shift, tcg_fpst);
171
+ }
172
+ } else {
173
+ if (is_signed) {
174
+ gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
175
+ } else {
176
+ gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
177
+ }
178
+ }
179
+ break;
180
+ case MO_16:
181
+ if (fracbits) {
182
+ if (is_signed) {
183
+ gen_helper_vfp_sltoh(tcg_float, tcg_int32,
184
+ tcg_shift, tcg_fpst);
185
+ } else {
186
+ gen_helper_vfp_ultoh(tcg_float, tcg_int32,
187
+ tcg_shift, tcg_fpst);
188
+ }
189
+ } else {
190
+ if (is_signed) {
191
+ gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
192
+ } else {
193
+ gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
194
+ }
195
+ }
196
+ break;
197
+ default:
198
+ g_assert_not_reached();
199
+ }
200
+
201
+ if (elements == 1) {
202
+ write_fp_sreg(s, rd, tcg_float);
203
+ } else {
204
+ write_vec_element_i32(s, tcg_float, rd, pass, size);
205
+ }
206
+ }
207
+
208
+ tcg_temp_free_i32(tcg_int32);
209
+ tcg_temp_free_i32(tcg_float);
210
}
211
212
- tcg_temp_free_i64(tcg_int);
213
tcg_temp_free_ptr(tcg_fpst);
214
- tcg_temp_free_i32(tcg_shift);
215
+ if (tcg_shift) {
216
+ tcg_temp_free_i32(tcg_shift);
217
+ }
218
219
clear_vec_high(s, elements << size == 16, rd);
220
}
221
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
222
rn = extract32(insn, 5, 5);
223
224
switch (fpop) {
225
+ case 0x1d: /* SCVTF */
226
+ case 0x5d: /* UCVTF */
227
+ {
228
+ int elements;
229
+
230
+ if (is_scalar) {
231
+ elements = 1;
232
+ } else {
233
+ elements = (is_q ? 8 : 4);
234
+ }
235
+
236
+ if (!fp_access_check(s)) {
237
+ return;
238
+ }
239
+ handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
240
+ return;
241
+ }
242
break;
243
case 0x2c: /* FCMGT (zero) */
244
case 0x2d: /* FCMEQ (zero) */
245
--
246
2.16.2
247
248
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Neither of these operations alter the floating point status registers
4
so we can do a pure bitwise operation, either squashing any sign
5
bit (ABS) or inverting it (NEG).
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 16 +++++++++++++++-
13
1 file changed, 15 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
20
TCGv_i32 tcg_rmode = NULL;
21
TCGv_ptr tcg_fpstatus = NULL;
22
bool need_rmode = false;
23
+ bool need_fpst = true;
24
int rmode;
25
26
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
27
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
28
need_rmode = true;
29
rmode = FPROUNDING_ZERO;
30
break;
31
+ case 0x2f: /* FABS */
32
+ case 0x6f: /* FNEG */
33
+ need_fpst = false;
34
+ break;
35
default:
36
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
37
g_assert_not_reached();
38
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
39
return;
40
}
41
42
- if (need_rmode) {
43
+ if (need_rmode || need_fpst) {
44
tcg_fpstatus = get_fpstatus_ptr(true);
45
}
46
47
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
48
case 0x7b: /* FCVTZU */
49
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
50
break;
51
+ case 0x6f: /* FNEG */
52
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
53
+ break;
54
default:
55
g_assert_not_reached();
56
}
57
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
58
case 0x59: /* FRINTX */
59
gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
60
break;
61
+ case 0x2f: /* FABS */
62
+ tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
63
+ break;
64
+ case 0x6f: /* FNEG */
65
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
66
+ break;
67
default:
68
g_assert_not_reached();
69
}
70
--
71
2.16.2
72
73
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
It looks like the ARM ARM has simplified the pseudo code for the
4
calculation which is done on a fixed point 9 bit integer maths. So
5
while adding f16 we can also clean this up to be a little less heavy
6
on the floating point and just return the fractional part and leave
7
the calle's to do the final packing of the result.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/helper.h | 1 +
15
target/arm/helper.c | 226 +++++++++++++++++++++++++++++-----------------------
16
2 files changed, 129 insertions(+), 98 deletions(-)
17
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
23
24
DEF_HELPER_3(recps_f32, f32, f32, f32, env)
25
DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
26
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
27
DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
28
DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
35
* int->float conversions at run-time. */
36
#define float64_256 make_float64(0x4070000000000000LL)
37
#define float64_512 make_float64(0x4080000000000000LL)
38
+#define float16_maxnorm make_float16(0x7bff)
39
#define float32_maxnorm make_float32(0x7f7fffff)
40
#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
41
42
/* Reciprocal functions
43
*
44
* The algorithm that must be used to calculate the estimate
45
- * is specified by the ARM ARM, see FPRecipEstimate()
46
+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
47
*/
48
49
-static float64 recip_estimate(float64 a, float_status *real_fp_status)
50
+/* See RecipEstimate()
51
+ *
52
+ * input is a 9 bit fixed point number
53
+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
54
+ * result range 256 .. 511 for a number from 1.0 to 511/256.
55
+ */
56
+
57
+static int recip_estimate(int input)
58
{
59
- /* These calculations mustn't set any fp exception flags,
60
- * so we use a local copy of the fp_status.
61
- */
62
- float_status dummy_status = *real_fp_status;
63
- float_status *s = &dummy_status;
64
- /* q = (int)(a * 512.0) */
65
- float64 q = float64_mul(float64_512, a, s);
66
- int64_t q_int = float64_to_int64_round_to_zero(q, s);
67
-
68
- /* r = 1.0 / (((double)q + 0.5) / 512.0) */
69
- q = int64_to_float64(q_int, s);
70
- q = float64_add(q, float64_half, s);
71
- q = float64_div(q, float64_512, s);
72
- q = float64_div(float64_one, q, s);
73
-
74
- /* s = (int)(256.0 * r + 0.5) */
75
- q = float64_mul(q, float64_256, s);
76
- q = float64_add(q, float64_half, s);
77
- q_int = float64_to_int64_round_to_zero(q, s);
78
-
79
- /* return (double)s / 256.0 */
80
- return float64_div(int64_to_float64(q_int, s), float64_256, s);
81
+ int a, b, r;
82
+ assert(256 <= input && input < 512);
83
+ a = (input * 2) + 1;
84
+ b = (1 << 19) / a;
85
+ r = (b + 1) >> 1;
86
+ assert(256 <= r && r < 512);
87
+ return r;
88
}
89
90
-/* Common wrapper to call recip_estimate */
91
-static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
92
-{
93
- uint64_t val64 = float64_val(num);
94
- uint64_t frac = extract64(val64, 0, 52);
95
- int64_t exp = extract64(val64, 52, 11);
96
- uint64_t sbit;
97
- float64 scaled, estimate;
98
+/*
99
+ * Common wrapper to call recip_estimate
100
+ *
101
+ * The parameters are exponent and 64 bit fraction (without implicit
102
+ * bit) where the binary point is nominally at bit 52. Returns a
103
+ * float64 which can then be rounded to the appropriate size by the
104
+ * callee.
105
+ */
106
107
- /* Generate the scaled number for the estimate function */
108
- if (exp == 0) {
109
+static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
110
+{
111
+ uint32_t scaled, estimate;
112
+ uint64_t result_frac;
113
+ int result_exp;
114
+
115
+ /* Handle sub-normals */
116
+ if (*exp == 0) {
117
if (extract64(frac, 51, 1) == 0) {
118
- exp = -1;
119
- frac = extract64(frac, 0, 50) << 2;
120
+ *exp = -1;
121
+ frac <<= 2;
122
} else {
123
- frac = extract64(frac, 0, 51) << 1;
124
+ frac <<= 1;
125
}
126
}
127
128
- /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
129
- scaled = make_float64((0x3feULL << 52)
130
- | extract64(frac, 44, 8) << 44);
131
+ /* scaled = UInt('1':fraction<51:44>) */
132
+ scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
133
+ estimate = recip_estimate(scaled);
134
135
- estimate = recip_estimate(scaled, fpst);
136
-
137
- /* Build new result */
138
- val64 = float64_val(estimate);
139
- sbit = 0x8000000000000000ULL & val64;
140
- exp = off - exp;
141
- frac = extract64(val64, 0, 52);
142
-
143
- if (exp == 0) {
144
- frac = 1ULL << 51 | extract64(frac, 1, 51);
145
- } else if (exp == -1) {
146
- frac = 1ULL << 50 | extract64(frac, 2, 50);
147
- exp = 0;
148
+ result_exp = exp_off - *exp;
149
+ result_frac = deposit64(0, 44, 8, estimate);
150
+ if (result_exp == 0) {
151
+ result_frac = deposit64(result_frac >> 1, 51, 1, 1);
152
+ } else if (result_exp == -1) {
153
+ result_frac = deposit64(result_frac >> 2, 50, 2, 1);
154
+ result_exp = 0;
155
}
156
157
- return make_float64(sbit | (exp << 52) | frac);
158
+ *exp = result_exp;
159
+
160
+ return result_frac;
161
}
162
163
static bool round_to_inf(float_status *fpst, bool sign_bit)
164
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
165
g_assert_not_reached();
166
}
167
168
+float16 HELPER(recpe_f16)(float16 input, void *fpstp)
169
+{
170
+ float_status *fpst = fpstp;
171
+ float16 f16 = float16_squash_input_denormal(input, fpst);
172
+ uint32_t f16_val = float16_val(f16);
173
+ uint32_t f16_sign = float16_is_neg(f16);
174
+ int f16_exp = extract32(f16_val, 10, 5);
175
+ uint32_t f16_frac = extract32(f16_val, 0, 10);
176
+ uint64_t f64_frac;
177
+
178
+ if (float16_is_any_nan(f16)) {
179
+ float16 nan = f16;
180
+ if (float16_is_signaling_nan(f16, fpst)) {
181
+ float_raise(float_flag_invalid, fpst);
182
+ nan = float16_maybe_silence_nan(f16, fpst);
183
+ }
184
+ if (fpst->default_nan_mode) {
185
+ nan = float16_default_nan(fpst);
186
+ }
187
+ return nan;
188
+ } else if (float16_is_infinity(f16)) {
189
+ return float16_set_sign(float16_zero, float16_is_neg(f16));
190
+ } else if (float16_is_zero(f16)) {
191
+ float_raise(float_flag_divbyzero, fpst);
192
+ return float16_set_sign(float16_infinity, float16_is_neg(f16));
193
+ } else if (float16_abs(f16) < (1 << 8)) {
194
+ /* Abs(value) < 2.0^-16 */
195
+ float_raise(float_flag_overflow | float_flag_inexact, fpst);
196
+ if (round_to_inf(fpst, f16_sign)) {
197
+ return float16_set_sign(float16_infinity, f16_sign);
198
+ } else {
199
+ return float16_set_sign(float16_maxnorm, f16_sign);
200
+ }
201
+ } else if (f16_exp >= 29 && fpst->flush_to_zero) {
202
+ float_raise(float_flag_underflow, fpst);
203
+ return float16_set_sign(float16_zero, float16_is_neg(f16));
204
+ }
205
+
206
+ f64_frac = call_recip_estimate(&f16_exp, 29,
207
+ ((uint64_t) f16_frac) << (52 - 10));
208
+
209
+ /* result = sign : result_exp<4:0> : fraction<51:42> */
210
+ f16_val = deposit32(0, 15, 1, f16_sign);
211
+ f16_val = deposit32(f16_val, 10, 5, f16_exp);
212
+ f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
213
+ return make_float16(f16_val);
214
+}
215
+
216
float32 HELPER(recpe_f32)(float32 input, void *fpstp)
217
{
218
float_status *fpst = fpstp;
219
float32 f32 = float32_squash_input_denormal(input, fpst);
220
uint32_t f32_val = float32_val(f32);
221
- uint32_t f32_sbit = 0x80000000ULL & f32_val;
222
- int32_t f32_exp = extract32(f32_val, 23, 8);
223
+ bool f32_sign = float32_is_neg(f32);
224
+ int f32_exp = extract32(f32_val, 23, 8);
225
uint32_t f32_frac = extract32(f32_val, 0, 23);
226
- float64 f64, r64;
227
- uint64_t r64_val;
228
- int64_t r64_exp;
229
- uint64_t r64_frac;
230
+ uint64_t f64_frac;
231
232
if (float32_is_any_nan(f32)) {
233
float32 nan = f32;
234
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
235
} else if (float32_is_zero(f32)) {
236
float_raise(float_flag_divbyzero, fpst);
237
return float32_set_sign(float32_infinity, float32_is_neg(f32));
238
- } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
239
+ } else if (float32_abs(f32) < (1ULL << 21)) {
240
/* Abs(value) < 2.0^-128 */
241
float_raise(float_flag_overflow | float_flag_inexact, fpst);
242
- if (round_to_inf(fpst, f32_sbit)) {
243
- return float32_set_sign(float32_infinity, float32_is_neg(f32));
244
+ if (round_to_inf(fpst, f32_sign)) {
245
+ return float32_set_sign(float32_infinity, f32_sign);
246
} else {
247
- return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
248
+ return float32_set_sign(float32_maxnorm, f32_sign);
249
}
250
} else if (f32_exp >= 253 && fpst->flush_to_zero) {
251
float_raise(float_flag_underflow, fpst);
252
return float32_set_sign(float32_zero, float32_is_neg(f32));
253
}
254
255
+ f64_frac = call_recip_estimate(&f32_exp, 253,
256
+ ((uint64_t) f32_frac) << (52 - 23));
257
258
- f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
259
- r64 = call_recip_estimate(f64, 253, fpst);
260
- r64_val = float64_val(r64);
261
- r64_exp = extract64(r64_val, 52, 11);
262
- r64_frac = extract64(r64_val, 0, 52);
263
-
264
- /* result = sign : result_exp<7:0> : fraction<51:29>; */
265
- return make_float32(f32_sbit |
266
- (r64_exp & 0xff) << 23 |
267
- extract64(r64_frac, 29, 24));
268
+ /* result = sign : result_exp<7:0> : fraction<51:29> */
269
+ f32_val = deposit32(0, 31, 1, f32_sign);
270
+ f32_val = deposit32(f32_val, 23, 8, f32_exp);
271
+ f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
272
+ return make_float32(f32_val);
273
}
274
275
float64 HELPER(recpe_f64)(float64 input, void *fpstp)
276
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
277
float_status *fpst = fpstp;
278
float64 f64 = float64_squash_input_denormal(input, fpst);
279
uint64_t f64_val = float64_val(f64);
280
- uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
281
- int64_t f64_exp = extract64(f64_val, 52, 11);
282
- float64 r64;
283
- uint64_t r64_val;
284
- int64_t r64_exp;
285
- uint64_t r64_frac;
286
+ bool f64_sign = float64_is_neg(f64);
287
+ int f64_exp = extract64(f64_val, 52, 11);
288
+ uint64_t f64_frac = extract64(f64_val, 0, 52);
289
290
/* Deal with any special cases */
291
if (float64_is_any_nan(f64)) {
292
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
293
} else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
294
/* Abs(value) < 2.0^-1024 */
295
float_raise(float_flag_overflow | float_flag_inexact, fpst);
296
- if (round_to_inf(fpst, f64_sbit)) {
297
- return float64_set_sign(float64_infinity, float64_is_neg(f64));
298
+ if (round_to_inf(fpst, f64_sign)) {
299
+ return float64_set_sign(float64_infinity, f64_sign);
300
} else {
301
- return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
302
+ return float64_set_sign(float64_maxnorm, f64_sign);
303
}
304
} else if (f64_exp >= 2045 && fpst->flush_to_zero) {
305
float_raise(float_flag_underflow, fpst);
306
return float64_set_sign(float64_zero, float64_is_neg(f64));
307
}
308
309
- r64 = call_recip_estimate(f64, 2045, fpst);
310
- r64_val = float64_val(r64);
311
- r64_exp = extract64(r64_val, 52, 11);
312
- r64_frac = extract64(r64_val, 0, 52);
313
+ f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
314
315
- /* result = sign : result_exp<10:0> : fraction<51:0> */
316
- return make_float64(f64_sbit |
317
- ((r64_exp & 0x7ff) << 52) |
318
- r64_frac);
319
+ /* result = sign : result_exp<10:0> : fraction<51:0>; */
320
+ f64_val = deposit64(0, 63, 1, f64_sign);
321
+ f64_val = deposit64(f64_val, 52, 11, f64_exp);
322
+ f64_val = deposit64(f64_val, 0, 52, f64_frac);
323
+ return make_float64(f64_val);
324
}
325
326
/* The algorithm that must be used to calculate the estimate
327
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
328
329
uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
330
{
331
- float_status *s = fpstp;
332
- float64 f64;
333
+ /* float_status *s = fpstp; */
334
+ int input, estimate;
335
336
if ((a & 0x80000000) == 0) {
337
return 0xffffffff;
338
}
339
340
- f64 = make_float64((0x3feULL << 52)
341
- | ((int64_t)(a & 0x7fffffff) << 21));
342
+ input = extract32(a, 23, 9);
343
+ estimate = recip_estimate(input);
344
345
- f64 = recip_estimate(f64, s);
346
-
347
- return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
348
+ return deposit32(0, (32 - 9), 9, estimate);
349
}
350
351
uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
352
--
353
2.16.2
354
355
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Now we have added f16 during the re-factoring we can simply call the
4
helper.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 8 ++++++++
12
1 file changed, 8 insertions(+)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
19
case 0x6d: /* FCMLE (zero) */
20
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
21
return;
22
+ case 0x3d: /* FRECPE */
23
+ break;
24
case 0x18: /* FRINTN */
25
need_rmode = true;
26
only_in_vector = true;
27
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
28
case 0x3b: /* FCVTZS */
29
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
30
break;
31
+ case 0x3d: /* FRECPE */
32
+ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
33
+ break;
34
case 0x5a: /* FCVTNU */
35
case 0x5b: /* FCVTMU */
36
case 0x5c: /* FCVTAU */
37
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
38
case 0x3b: /* FCVTZS */
39
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
40
break;
41
+ case 0x3d: /* FRECPE */
42
+ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
43
+ break;
44
case 0x5a: /* FCVTNU */
45
case 0x5b: /* FCVTMU */
46
case 0x5c: /* FCVTAU */
47
--
48
2.16.2
49
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
We go with the localised helper.
4
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper-a64.h | 1 +
11
target/arm/helper-a64.c | 29 +++++++++++++++++++++++++++++
12
target/arm/translate-a64.c | 4 ++++
13
3 files changed, 34 insertions(+)
14
15
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.h
18
+++ b/target/arm/helper-a64.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
20
DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
21
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
22
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
23
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
24
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
25
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
26
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
27
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper-a64.c
30
+++ b/target/arm/helper-a64.c
31
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
32
}
33
34
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
35
+float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
36
+{
37
+ float_status *fpst = fpstp;
38
+ uint16_t val16, sbit;
39
+ int16_t exp;
40
+
41
+ if (float16_is_any_nan(a)) {
42
+ float16 nan = a;
43
+ if (float16_is_signaling_nan(a, fpst)) {
44
+ float_raise(float_flag_invalid, fpst);
45
+ nan = float16_maybe_silence_nan(a, fpst);
46
+ }
47
+ if (fpst->default_nan_mode) {
48
+ nan = float16_default_nan(fpst);
49
+ }
50
+ return nan;
51
+ }
52
+
53
+ val16 = float16_val(a);
54
+ sbit = 0x8000 & val16;
55
+ exp = extract32(val16, 10, 5);
56
+
57
+ if (exp == 0) {
58
+ return make_float16(deposit32(sbit, 10, 5, 0x1e));
59
+ } else {
60
+ return make_float16(deposit32(sbit, 10, 5, ~exp));
61
+ }
62
+}
63
+
64
float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
65
{
66
float_status *fpst = fpstp;
67
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/translate-a64.c
70
+++ b/target/arm/translate-a64.c
71
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
72
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
73
return;
74
case 0x3d: /* FRECPE */
75
+ case 0x3f: /* FRECPX */
76
break;
77
case 0x18: /* FRINTN */
78
need_rmode = true;
79
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
80
case 0x3d: /* FRECPE */
81
gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
82
break;
83
+ case 0x3f: /* FRECPX */
84
+ gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
85
+ break;
86
case 0x5a: /* FCVTNU */
87
case 0x5b: /* FCVTMU */
88
case 0x5c: /* FCVTAU */
89
--
90
2.16.2
91
92
diff view generated by jsdifflib
[Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper-a64.h | 1 +
9
target/arm/helper-a64.c | 13 +++++++++++++
10
target/arm/translate-a64.c | 5 +++++
11
3 files changed, 19 insertions(+)
12
13
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper-a64.h
16
+++ b/target/arm/helper-a64.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
18
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
19
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
20
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
21
+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
22
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper-a64.c
25
+++ b/target/arm/helper-a64.c
26
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
27
}
28
return float16_to_uint16(a, fpst);
29
}
30
+
31
+/*
32
+ * Square Root and Reciprocal square root
33
+ */
34
+
35
+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
36
+{
37
+ float_status *s = fpstp;
38
+
39
+ return float16_sqrt(a, s);
40
+}
41
+
42
+
43
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/translate-a64.c
46
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
48
case 0x6f: /* FNEG */
49
need_fpst = false;
50
break;
51
+ case 0x7f: /* FSQRT (vector) */
52
+ break;
53
default:
54
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
55
g_assert_not_reached();
56
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
57
case 0x6f: /* FNEG */
58
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
59
break;
60
+ case 0x7f: /* FSQRT */
61
+ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
62
+ break;
63
default:
64
g_assert_not_reached();
65
}
66
--
67
2.16.2
68
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Much like recpe the ARM ARM has simplified the pseudo code for the
4
calculation which is done on a fixed point 9 bit integer maths. So
5
while adding f16 we can also clean this up to be a little less heavy
6
on the floating point and just return the fractional part and leave
7
the calle's to do the final packing of the result.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180227143852.11175-27-alex.bennee@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/helper.h | 1 +
15
target/arm/helper.c | 221 ++++++++++++++++++++++++----------------------------
16
2 files changed, 104 insertions(+), 118 deletions(-)
17
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
23
DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
24
DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
25
DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
26
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
27
DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_2(recpe_u32, i32, i32, ptr)
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
35
/* The algorithm that must be used to calculate the estimate
36
* is specified by the ARM ARM.
37
*/
38
-static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
39
+
40
+static int do_recip_sqrt_estimate(int a)
41
{
42
- /* These calculations mustn't set any fp exception flags,
43
- * so we use a local copy of the fp_status.
44
- */
45
- float_status dummy_status = *real_fp_status;
46
- float_status *s = &dummy_status;
47
- float64 q;
48
- int64_t q_int;
49
+ int b, estimate;
50
51
- if (float64_lt(a, float64_half, s)) {
52
- /* range 0.25 <= a < 0.5 */
53
-
54
- /* a in units of 1/512 rounded down */
55
- /* q0 = (int)(a * 512.0); */
56
- q = float64_mul(float64_512, a, s);
57
- q_int = float64_to_int64_round_to_zero(q, s);
58
-
59
- /* reciprocal root r */
60
- /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
61
- q = int64_to_float64(q_int, s);
62
- q = float64_add(q, float64_half, s);
63
- q = float64_div(q, float64_512, s);
64
- q = float64_sqrt(q, s);
65
- q = float64_div(float64_one, q, s);
66
+ assert(128 <= a && a < 512);
67
+ if (a < 256) {
68
+ a = a * 2 + 1;
69
} else {
70
- /* range 0.5 <= a < 1.0 */
71
-
72
- /* a in units of 1/256 rounded down */
73
- /* q1 = (int)(a * 256.0); */
74
- q = float64_mul(float64_256, a, s);
75
- int64_t q_int = float64_to_int64_round_to_zero(q, s);
76
-
77
- /* reciprocal root r */
78
- /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
79
- q = int64_to_float64(q_int, s);
80
- q = float64_add(q, float64_half, s);
81
- q = float64_div(q, float64_256, s);
82
- q = float64_sqrt(q, s);
83
- q = float64_div(float64_one, q, s);
84
+ a = (a >> 1) << 1;
85
+ a = (a + 1) * 2;
86
}
87
- /* r in units of 1/256 rounded to nearest */
88
- /* s = (int)(256.0 * r + 0.5); */
89
+ b = 512;
90
+ while (a * (b + 1) * (b + 1) < (1 << 28)) {
91
+ b += 1;
92
+ }
93
+ estimate = (b + 1) / 2;
94
+ assert(256 <= estimate && estimate < 512);
95
96
- q = float64_mul(q, float64_256,s );
97
- q = float64_add(q, float64_half, s);
98
- q_int = float64_to_int64_round_to_zero(q, s);
99
+ return estimate;
100
+}
101
102
- /* return (double)s / 256.0;*/
103
- return float64_div(int64_to_float64(q_int, s), float64_256, s);
104
+
105
+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
106
+{
107
+ int estimate;
108
+ uint32_t scaled;
109
+
110
+ if (*exp == 0) {
111
+ while (extract64(frac, 51, 1) == 0) {
112
+ frac = frac << 1;
113
+ *exp -= 1;
114
+ }
115
+ frac = extract64(frac, 0, 51) << 1;
116
+ }
117
+
118
+ if (*exp & 1) {
119
+ /* scaled = UInt('01':fraction<51:45>) */
120
+ scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
121
+ } else {
122
+ /* scaled = UInt('1':fraction<51:44>) */
123
+ scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
124
+ }
125
+ estimate = do_recip_sqrt_estimate(scaled);
126
+
127
+ *exp = (exp_off - *exp) / 2;
128
+ return extract64(estimate, 0, 8) << 44;
129
+}
130
+
131
+float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
132
+{
133
+ float_status *s = fpstp;
134
+ float16 f16 = float16_squash_input_denormal(input, s);
135
+ uint16_t val = float16_val(f16);
136
+ bool f16_sign = float16_is_neg(f16);
137
+ int f16_exp = extract32(val, 10, 5);
138
+ uint16_t f16_frac = extract32(val, 0, 10);
139
+ uint64_t f64_frac;
140
+
141
+ if (float16_is_any_nan(f16)) {
142
+ float16 nan = f16;
143
+ if (float16_is_signaling_nan(f16, s)) {
144
+ float_raise(float_flag_invalid, s);
145
+ nan = float16_maybe_silence_nan(f16, s);
146
+ }
147
+ if (s->default_nan_mode) {
148
+ nan = float16_default_nan(s);
149
+ }
150
+ return nan;
151
+ } else if (float16_is_zero(f16)) {
152
+ float_raise(float_flag_divbyzero, s);
153
+ return float16_set_sign(float16_infinity, f16_sign);
154
+ } else if (f16_sign) {
155
+ float_raise(float_flag_invalid, s);
156
+ return float16_default_nan(s);
157
+ } else if (float16_is_infinity(f16)) {
158
+ return float16_zero;
159
+ }
160
+
161
+ /* Scale and normalize to a double-precision value between 0.25 and 1.0,
162
+ * preserving the parity of the exponent. */
163
+
164
+ f64_frac = ((uint64_t) f16_frac) << (52 - 10);
165
+
166
+ f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
167
+
168
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
169
+ val = deposit32(0, 15, 1, f16_sign);
170
+ val = deposit32(val, 10, 5, f16_exp);
171
+ val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
172
+ return make_float16(val);
173
}
174
175
float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
176
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
177
float_status *s = fpstp;
178
float32 f32 = float32_squash_input_denormal(input, s);
179
uint32_t val = float32_val(f32);
180
- uint32_t f32_sbit = 0x80000000 & val;
181
- int32_t f32_exp = extract32(val, 23, 8);
182
+ uint32_t f32_sign = float32_is_neg(f32);
183
+ int f32_exp = extract32(val, 23, 8);
184
uint32_t f32_frac = extract32(val, 0, 23);
185
uint64_t f64_frac;
186
- uint64_t val64;
187
- int result_exp;
188
- float64 f64;
189
190
if (float32_is_any_nan(f32)) {
191
float32 nan = f32;
192
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
193
* preserving the parity of the exponent. */
194
195
f64_frac = ((uint64_t) f32_frac) << 29;
196
- if (f32_exp == 0) {
197
- while (extract64(f64_frac, 51, 1) == 0) {
198
- f64_frac = f64_frac << 1;
199
- f32_exp = f32_exp-1;
200
- }
201
- f64_frac = extract64(f64_frac, 0, 51) << 1;
202
- }
203
204
- if (extract64(f32_exp, 0, 1) == 0) {
205
- f64 = make_float64(((uint64_t) f32_sbit) << 32
206
- | (0x3feULL << 52)
207
- | f64_frac);
208
- } else {
209
- f64 = make_float64(((uint64_t) f32_sbit) << 32
210
- | (0x3fdULL << 52)
211
- | f64_frac);
212
- }
213
+ f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
214
215
- result_exp = (380 - f32_exp) / 2;
216
-
217
- f64 = recip_sqrt_estimate(f64, s);
218
-
219
- val64 = float64_val(f64);
220
-
221
- val = ((result_exp & 0xff) << 23)
222
- | ((val64 >> 29) & 0x7fffff);
223
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
224
+ val = deposit32(0, 31, 1, f32_sign);
225
+ val = deposit32(val, 23, 8, f32_exp);
226
+ val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
227
return make_float32(val);
228
}
229
230
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
231
float_status *s = fpstp;
232
float64 f64 = float64_squash_input_denormal(input, s);
233
uint64_t val = float64_val(f64);
234
- uint64_t f64_sbit = 0x8000000000000000ULL & val;
235
- int64_t f64_exp = extract64(val, 52, 11);
236
+ bool f64_sign = float64_is_neg(f64);
237
+ int f64_exp = extract64(val, 52, 11);
238
uint64_t f64_frac = extract64(val, 0, 52);
239
- int64_t result_exp;
240
- uint64_t result_frac;
241
242
if (float64_is_any_nan(f64)) {
243
float64 nan = f64;
244
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
245
return float64_zero;
246
}
247
248
- /* Scale and normalize to a double-precision value between 0.25 and 1.0,
249
- * preserving the parity of the exponent. */
250
+ f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
251
252
- if (f64_exp == 0) {
253
- while (extract64(f64_frac, 51, 1) == 0) {
254
- f64_frac = f64_frac << 1;
255
- f64_exp = f64_exp - 1;
256
- }
257
- f64_frac = extract64(f64_frac, 0, 51) << 1;
258
- }
259
-
260
- if (extract64(f64_exp, 0, 1) == 0) {
261
- f64 = make_float64(f64_sbit
262
- | (0x3feULL << 52)
263
- | f64_frac);
264
- } else {
265
- f64 = make_float64(f64_sbit
266
- | (0x3fdULL << 52)
267
- | f64_frac);
268
- }
269
-
270
- result_exp = (3068 - f64_exp) / 2;
271
-
272
- f64 = recip_sqrt_estimate(f64, s);
273
-
274
- result_frac = extract64(float64_val(f64), 0, 52);
275
-
276
- return make_float64(f64_sbit |
277
- ((result_exp & 0x7ff) << 52) |
278
- result_frac);
279
+ /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
280
+ val = deposit64(0, 61, 1, f64_sign);
281
+ val = deposit64(val, 52, 11, f64_exp);
282
+ val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
283
+ return make_float64(val);
284
}
285
286
uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
287
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
288
289
uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
290
{
291
- float_status *fpst = fpstp;
292
- float64 f64;
293
+ int estimate;
294
295
if ((a & 0xc0000000) == 0) {
296
return 0xffffffff;
297
}
298
299
- if (a & 0x80000000) {
300
- f64 = make_float64((0x3feULL << 52)
301
- | ((uint64_t)(a & 0x7fffffff) << 21));
302
- } else { /* bits 31-30 == '01' */
303
- f64 = make_float64((0x3fdULL << 52)
304
- | ((uint64_t)(a & 0x3fffffff) << 22));
305
- }
306
+ estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
307
308
- f64 = recip_sqrt_estimate(f64, fpst);
309
-
310
- return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
311
+ return deposit32(0, 23, 9, estimate);
312
}
313
314
/* VFPv4 fused multiply-accumulate */
315
--
316
2.16.2
317
318
diff view generated by jsdifflib
[Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 7 +++++++
9
1 file changed, 7 insertions(+)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
16
case 0x6f: /* FNEG */
17
need_fpst = false;
18
break;
19
+ case 0x7d: /* FRSQRTE */
20
case 0x7f: /* FSQRT (vector) */
21
break;
22
default:
23
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
24
case 0x6f: /* FNEG */
25
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
26
break;
27
+ case 0x7d: /* FRSQRTE */
28
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
29
+ break;
30
default:
31
g_assert_not_reached();
32
}
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
34
case 0x6f: /* FNEG */
35
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
36
break;
37
+ case 0x7d: /* FRSQRTE */
38
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
39
+ break;
40
case 0x7f: /* FSQRT */
41
gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
42
break;
43
--
44
2.16.2
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
Only one half-precision instruction has been added to this group.
4
5
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180227143852.11175-29-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 35 +++++++++++++++++++++++++----------
11
1 file changed, 25 insertions(+), 10 deletions(-)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
18
* MVNI - move inverted (shifted) imm into register
19
* ORR - bitwise OR of (shifted) imm with register
20
* BIC - bitwise clear of (shifted) imm with register
21
+ * With ARMv8.2 we also have:
22
+ * FMOV half-precision
23
*/
24
static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
25
{
26
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
27
uint64_t imm = 0;
28
29
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
30
- unallocated_encoding(s);
31
- return;
32
+ /* Check for FMOV (vector, immediate) - half-precision */
33
+ if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
34
+ unallocated_encoding(s);
35
+ return;
36
+ }
37
}
38
39
if (!fp_access_check(s)) {
40
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
41
imm |= 0x4000000000000000ULL;
42
}
43
} else {
44
- imm = (abcdefgh & 0x3f) << 19;
45
- if (abcdefgh & 0x80) {
46
- imm |= 0x80000000;
47
- }
48
- if (abcdefgh & 0x40) {
49
- imm |= 0x3e000000;
50
+ if (o2) {
51
+ /* FMOV (vector, immediate) - half-precision */
52
+ imm = vfp_expand_imm(MO_16, abcdefgh);
53
+ /* now duplicate across the lanes */
54
+ imm = bitfield_replicate(imm, 16);
55
} else {
56
- imm |= 0x40000000;
57
+ imm = (abcdefgh & 0x3f) << 19;
58
+ if (abcdefgh & 0x80) {
59
+ imm |= 0x80000000;
60
+ }
61
+ if (abcdefgh & 0x40) {
62
+ imm |= 0x3e000000;
63
+ } else {
64
+ imm |= 0x40000000;
65
+ }
66
+ imm |= (imm << 32);
67
}
68
- imm |= (imm << 32);
69
}
70
}
71
break;
72
+ default:
73
+ fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
74
+ g_assert_not_reached();
75
}
76
77
if (cmode_3_1 != 7 && is_neg) {
78
--
79
2.16.2
80
81
diff view generated by jsdifflib
[Qemu-devel] [PULL 37/42] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
I only needed to do a little light re-factoring to support the
4
half-precision helpers.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++---------------
12
1 file changed, 54 insertions(+), 26 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
19
case 0xf: /* FMAXP */
20
case 0x2c: /* FMINNMP */
21
case 0x2f: /* FMINP */
22
- /* FP op, size[0] is 32 or 64 bit */
23
+ /* FP op, size[0] is 32 or 64 bit*/
24
if (!u) {
25
- unallocated_encoding(s);
26
- return;
27
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
28
+ unallocated_encoding(s);
29
+ return;
30
+ } else {
31
+ size = MO_16;
32
+ }
33
+ } else {
34
+ size = extract32(size, 0, 1) ? MO_64 : MO_32;
35
}
36
+
37
if (!fp_access_check(s)) {
38
return;
39
}
40
41
- size = extract32(size, 0, 1) ? 3 : 2;
42
- fpst = get_fpstatus_ptr(false);
43
+ fpst = get_fpstatus_ptr(size == MO_16);
44
break;
45
default:
46
unallocated_encoding(s);
47
return;
48
}
49
50
- if (size == 3) {
51
+ if (size == MO_64) {
52
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
53
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
54
TCGv_i64 tcg_res = tcg_temp_new_i64();
55
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
56
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
57
TCGv_i32 tcg_res = tcg_temp_new_i32();
58
59
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
60
- read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
61
+ read_vec_element_i32(s, tcg_op1, rn, 0, size);
62
+ read_vec_element_i32(s, tcg_op2, rn, 1, size);
63
64
- switch (opcode) {
65
- case 0xc: /* FMAXNMP */
66
- gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
67
- break;
68
- case 0xd: /* FADDP */
69
- gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
70
- break;
71
- case 0xf: /* FMAXP */
72
- gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
73
- break;
74
- case 0x2c: /* FMINNMP */
75
- gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
76
- break;
77
- case 0x2f: /* FMINP */
78
- gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
79
- break;
80
- default:
81
- g_assert_not_reached();
82
+ if (size == MO_16) {
83
+ switch (opcode) {
84
+ case 0xc: /* FMAXNMP */
85
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
86
+ break;
87
+ case 0xd: /* FADDP */
88
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
89
+ break;
90
+ case 0xf: /* FMAXP */
91
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
92
+ break;
93
+ case 0x2c: /* FMINNMP */
94
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
95
+ break;
96
+ case 0x2f: /* FMINP */
97
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
98
+ break;
99
+ default:
100
+ g_assert_not_reached();
101
+ }
102
+ } else {
103
+ switch (opcode) {
104
+ case 0xc: /* FMAXNMP */
105
+ gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
106
+ break;
107
+ case 0xd: /* FADDP */
108
+ gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
109
+ break;
110
+ case 0xf: /* FMAXP */
111
+ gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
112
+ break;
113
+ case 0x2c: /* FMINNMP */
114
+ gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
115
+ break;
116
+ case 0x2f: /* FMINP */
117
+ gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
118
+ break;
119
+ default:
120
+ g_assert_not_reached();
121
+ }
122
}
123
124
write_fp_sreg(s, rd, tcg_res);
125
--
126
2.16.2
127
128
diff view generated by jsdifflib
[Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This covers the encoding group:
4
5
Advanced SIMD scalar three same FP16
6
7
As all the helpers are already there it is simply a case of calling the
8
existing helpers in the scalar context.
9
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20180227143852.11175-31-alex.bennee@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
16
1 file changed, 99 insertions(+)
17
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
21
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
23
tcg_temp_free_i64(tcg_rd);
24
}
25
26
+/* AdvSIMD scalar three same FP16
27
+ * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
28
+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
29
+ * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
30
+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
31
+ * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
32
+ * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
33
+ */
34
+static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
35
+ uint32_t insn)
36
+{
37
+ int rd = extract32(insn, 0, 5);
38
+ int rn = extract32(insn, 5, 5);
39
+ int opcode = extract32(insn, 11, 3);
40
+ int rm = extract32(insn, 16, 5);
41
+ bool u = extract32(insn, 29, 1);
42
+ bool a = extract32(insn, 23, 1);
43
+ int fpopcode = opcode | (a << 3) | (u << 4);
44
+ TCGv_ptr fpst;
45
+ TCGv_i32 tcg_op1;
46
+ TCGv_i32 tcg_op2;
47
+ TCGv_i32 tcg_res;
48
+
49
+ switch (fpopcode) {
50
+ case 0x03: /* FMULX */
51
+ case 0x04: /* FCMEQ (reg) */
52
+ case 0x07: /* FRECPS */
53
+ case 0x0f: /* FRSQRTS */
54
+ case 0x14: /* FCMGE (reg) */
55
+ case 0x15: /* FACGE */
56
+ case 0x1a: /* FABD */
57
+ case 0x1c: /* FCMGT (reg) */
58
+ case 0x1d: /* FACGT */
59
+ break;
60
+ default:
61
+ unallocated_encoding(s);
62
+ return;
63
+ }
64
+
65
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
66
+ unallocated_encoding(s);
67
+ }
68
+
69
+ if (!fp_access_check(s)) {
70
+ return;
71
+ }
72
+
73
+ fpst = get_fpstatus_ptr(true);
74
+
75
+ tcg_op1 = tcg_temp_new_i32();
76
+ tcg_op2 = tcg_temp_new_i32();
77
+ tcg_res = tcg_temp_new_i32();
78
+
79
+ read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
80
+ read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
81
+
82
+ switch (fpopcode) {
83
+ case 0x03: /* FMULX */
84
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
85
+ break;
86
+ case 0x04: /* FCMEQ (reg) */
87
+ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
88
+ break;
89
+ case 0x07: /* FRECPS */
90
+ gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
91
+ break;
92
+ case 0x0f: /* FRSQRTS */
93
+ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
94
+ break;
95
+ case 0x14: /* FCMGE (reg) */
96
+ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
97
+ break;
98
+ case 0x15: /* FACGE */
99
+ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
100
+ break;
101
+ case 0x1a: /* FABD */
102
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
103
+ tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
104
+ break;
105
+ case 0x1c: /* FCMGT (reg) */
106
+ gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
107
+ break;
108
+ case 0x1d: /* FACGT */
109
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
110
+ break;
111
+ default:
112
+ g_assert_not_reached();
113
+ }
114
+
115
+ write_fp_sreg(s, rd, tcg_res);
116
+
117
+
118
+ tcg_temp_free_i32(tcg_res);
119
+ tcg_temp_free_i32(tcg_op1);
120
+ tcg_temp_free_i32(tcg_op2);
121
+ tcg_temp_free_ptr(fpst);
122
+}
123
+
124
static void handle_2misc_64(DisasContext *s, int opcode, bool u,
125
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
126
TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
127
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
128
{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
129
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
130
{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
131
+ { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
132
{ 0x00000000, 0x00000000, NULL }
133
};
134
135
--
136
2.16.2
137
138
diff view generated by jsdifflib
[Qemu-devel] [PULL 39/42] arm/translate-a64: add all single op FP16 to handle_fp_1src_half
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use
4
existing helpers to achieve this.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180227143852.11175-32-alex.bennee@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
12
1 file changed, 71 insertions(+)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
19
tcg_temp_free_i64(t_true);
20
}
21
22
+/* Floating-point data-processing (1 source) - half precision */
23
+static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
24
+{
25
+ TCGv_ptr fpst = NULL;
26
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
27
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
28
+
29
+ read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
30
+
31
+ switch (opcode) {
32
+ case 0x0: /* FMOV */
33
+ tcg_gen_mov_i32(tcg_res, tcg_op);
34
+ break;
35
+ case 0x1: /* FABS */
36
+ tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
37
+ break;
38
+ case 0x2: /* FNEG */
39
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
40
+ break;
41
+ case 0x3: /* FSQRT */
42
+ gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
43
+ break;
44
+ case 0x8: /* FRINTN */
45
+ case 0x9: /* FRINTP */
46
+ case 0xa: /* FRINTM */
47
+ case 0xb: /* FRINTZ */
48
+ case 0xc: /* FRINTA */
49
+ {
50
+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
51
+ fpst = get_fpstatus_ptr(true);
52
+
53
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
54
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
55
+
56
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
57
+ tcg_temp_free_i32(tcg_rmode);
58
+ break;
59
+ }
60
+ case 0xe: /* FRINTX */
61
+ fpst = get_fpstatus_ptr(true);
62
+ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
63
+ break;
64
+ case 0xf: /* FRINTI */
65
+ fpst = get_fpstatus_ptr(true);
66
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
67
+ break;
68
+ default:
69
+ abort();
70
+ }
71
+
72
+ write_fp_sreg(s, rd, tcg_res);
73
+
74
+ if (fpst) {
75
+ tcg_temp_free_ptr(fpst);
76
+ }
77
+ tcg_temp_free_i32(tcg_op);
78
+ tcg_temp_free_i32(tcg_res);
79
+}
80
+
81
/* Floating-point data-processing (1 source) - single precision */
82
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
83
{
84
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
85
86
handle_fp_1src_double(s, opcode, rd, rn);
87
break;
88
+ case 3:
89
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
90
+ unallocated_encoding(s);
91
+ return;
92
+ }
93
+
94
+ if (!fp_access_check(s)) {
95
+ return;
96
+ }
97
+
98
+ handle_fp_1src_half(s, opcode, rd, rn);
99
+ break;
100
default:
101
unallocated_encoding(s);
102
}
103
--
104
2.16.2
105
106
diff view generated by jsdifflib
[Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
Deleted patch
1
Now we have implemented FP16 we can enable it for the "any" CPU.
2
1
3
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
[PMM: split out from an earlier patch in the series]
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/cpu64.c | 1 +
9
1 file changed, 1 insertion(+)
10
11
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu64.c
14
+++ b/target/arm/cpu64.c
15
@@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj)
16
set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
17
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
18
set_feature(&cpu->env, ARM_FEATURE_CRC);
19
+ set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
20
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
21
cpu->dcz_blocksize = 7; /* 512 bytes */
22
}
23
--
24
2.16.2
25
26
diff view generated by jsdifflib
[Qemu-devel] [PULL 41/42] linux-user: Report AArch64 FP16 support via hwcap bits
Deleted patch
1
Set the appropriate Linux hwcap bits to tell the guest binary if we
2
have implemented half-precision floating point support.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
linux-user/elfload.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/linux-user/elfload.c
13
+++ b/linux-user/elfload.c
14
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
15
GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
16
GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
17
GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
18
+ GET_FEATURE(ARM_FEATURE_V8_FP16,
19
+ ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
20
#undef GET_FEATURE
21
22
return hwcaps;
23
--
24
2.16.2
25
26
diff view generated by jsdifflib
[Qemu-devel] [PULL 42/42] MAINTAINERS: Update my email address
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
I am leaving Xilinx, so to avoid having an email address that bounces
4
update my maintainer address to point to my personal email address.
5
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
7
Signed-off-by: Alistair Francis <alistair@alistair23.me>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
MAINTAINERS | 12 ++++++------
13
1 file changed, 6 insertions(+), 6 deletions(-)
14
15
diff --git a/MAINTAINERS b/MAINTAINERS
16
index XXXXXXX..XXXXXXX 100644
17
--- a/MAINTAINERS
18
+++ b/MAINTAINERS
19
@@ -XXX,XX +XXX,XX @@ F: hw/misc/arm_sysctl.c
20
21
Xilinx Zynq
22
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
23
-M: Alistair Francis <alistair.francis@xilinx.com>
24
+M: Alistair Francis <alistair@alistair23.me>
25
L: qemu-arm@nongnu.org
26
S: Maintained
27
F: hw/*/xilinx_*
28
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/zynq*
29
X: hw/ssi/xilinx_*
30
31
Xilinx ZynqMP
32
-M: Alistair Francis <alistair.francis@xilinx.com>
33
+M: Alistair Francis <alistair@alistair23.me>
34
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
35
L: qemu-arm@nongnu.org
36
S: Maintained
37
@@ -XXX,XX +XXX,XX @@ T: git git://github.com/bonzini/qemu.git scsi-next
38
39
SSI
40
M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
41
-M: Alistair Francis <alistair.francis@xilinx.com>
42
+M: Alistair Francis <alistair@alistair23.me>
43
S: Maintained
44
F: hw/ssi/*
45
F: hw/block/m25p80.c
46
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
47
F: tests/m25p80-test.c
48
49
Xilinx SPI
50
-M: Alistair Francis <alistair.francis@xilinx.com>
51
+M: Alistair Francis <alistair@alistair23.me>
52
M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
53
S: Maintained
54
F: hw/ssi/xilinx_*
55
@@ -XXX,XX +XXX,XX @@ S: Maintained
56
F: hw/net/eepro100.c
57
58
Generic Loader
59
-M: Alistair Francis <alistair.francis@xilinx.com>
60
+M: Alistair Francis <alistair@alistair23.me>
61
S: Maintained
62
F: hw/core/generic-loader.c
63
F: include/hw/core/generic-loader.h
64
@@ -XXX,XX +XXX,XX @@ F: tests/qmp-test.c
65
T: git git://repo.or.cz/qemu/armbru.git qapi-next
66
67
Register API
68
-M: Alistair Francis <alistair.francis@xilinx.com>
69
+M: Alistair Francis <alistair@alistair23.me>
70
S: Maintained
71
F: hw/core/register.c
72
F: include/hw/register.h
73
--
74
2.16.2
75
76
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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