Series comparison

-[Qemu-devel] [PULL 00/42] target-arm queue
+[Qemu-devel] [PULL 00/12] target-arm queue
-Arm queue -- I have more stuff pending but I prefer to push
+Not very much here, but several people have fallen over
-this first lot out and keep the pull below 50 patches.
+the vector operation segfault bug, so let's get the fix
-Most of this is Alex's FP16 support work.
+into master.
+thanks
 -- PMM
+The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
-The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:
+  Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
   Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
-for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:
+for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
-  MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)
+  hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * update MAINTAINERS for Alistair's new email address
+ * exynos4210: QOM'ify the Exynos4210 SoC
- * add Arm v8.2 FP16 arithmetic extension for linux-user
+ * exynos4210: Add DMA support for the Exynos4210
- * implement display connector emulation for vexpress board
+ * arm_gicv3: Fix writes to ICC_CTLR_EL3
- * xilinx_spips: Enable only two slaves when reading/writing with stripe
+ * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
- * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
+ * target/arm: Fix vector operation segfault
- * hw: register: Run post_write hook on reset
+ * target/arm: Minor improvements to BFXIL, EXTR
 ----------------------------------------------------------------
-Alex Bennée (31):
+Alistair Francis (1):
-      include/exec/helper-head.h: support f16 in helper calls
+      target/arm: Fix vector operation segfault
       target/arm/cpu64: introduce ARM_V8_FP16 feature bit
       target/arm/cpu.h: update comment for half-precision values
       target/arm/cpu.h: add additional float_status flags
       target/arm/helper: pass explicit fpst to set_rmode
       arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
       arm/translate-a64: handle_3same_64 comment fix
       arm/translate-a64: initial decode for simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
       arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
       arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
       arm/translate-a64: add FP16 x2 ops for simd_indexed
       arm/translate-a64: initial decode for simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
       arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
       arm/helper.c: re-factor recpe and add recepe_f16
       arm/translate-a64: add FP16 FRECPE
       arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
       arm/helper.c: re-factor rsqrte and add rsqrte_f16
       arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
       arm/translate-a64: add FP16 FMOV to simd_mod_imm
       arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
       arm/translate-a64: implement simd_scalar_three_reg_same_fp16
       arm/translate-a64: add all single op FP16 to handle_fp_1src_half
-Alistair Francis (2):
+Guenter Roeck (1):
-      hw: register: Run post_write hook on reset
+      hw/arm/exynos4210: Add DMA support for the Exynos4210
       MAINTAINERS: Update my email address
-Corey Minyard (2):
+Peter Maydell (5):
-      i2c: Fix some brace style issues
+      arm: Move system_clock_scale to armv7m_systick.h
-      i2c: Move the bus class to i2c.h
+      arm: Remove unnecessary includes of hw/arm/arm.h
       arm: Rename hw/arm/arm.h to hw/arm/boot.h
       hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
       hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
-Francisco Iglesias (2):
+Philippe Mathieu-Daudé (3):
-      xilinx_spips: Enable only two slaves when reading/writing with stripe
+      hw/arm/exynos4: Remove unuseful debug code
-      xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
+      hw/arm/exynos4: Use the IEC binary prefix definitions
       hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
-Linus Walleij (3):
+Richard Henderson (2):
-      hw/i2c-ddc: Do not fail writes
+      target/arm: Use extract2 for EXTR
-      hw/sii9022: Add support for Silicon Image SII9022
+      target/arm: Simplify BFXIL expansion
       arm/vexpress: Add proper display connector emulation
-Peter Maydell (2):
+ include/hw/arm/allwinner-a10.h    |  2 +-
-      target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
+ include/hw/arm/aspeed_soc.h       |  1 -
-      linux-user: Report AArch64 FP16 support via hwcap bits
+ include/hw/arm/bcm2836.h          |  1 -
  include/hw/arm/{arm.h => boot.h}  | 12 +++------
  include/hw/arm/exynos4210.h       |  9 +++++--
  include/hw/arm/fsl-imx25.h        |  2 +-
  include/hw/arm/fsl-imx31.h        |  2 +-
  include/hw/arm/fsl-imx6.h         |  2 +-
  include/hw/arm/fsl-imx6ul.h       |  2 +-
  include/hw/arm/fsl-imx7.h         |  2 +-
  include/hw/arm/virt.h             |  2 +-
  include/hw/arm/xlnx-versal.h      |  2 +-
  include/hw/arm/xlnx-zynqmp.h      |  2 +-
  include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
  hw/arm/armsse.c                   |  2 +-
  hw/arm/armv7m.c                   |  2 +-
  hw/arm/aspeed.c                   |  2 +-
  hw/arm/boot.c                     |  2 +-
  hw/arm/collie.c                   |  2 +-
  hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
  hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
  hw/arm/highbank.c                 |  2 +-
  hw/arm/integratorcp.c             |  2 +-
  hw/arm/mainstone.c                |  2 +-
  hw/arm/microbit.c                 |  2 +-
  hw/arm/mps2-tz.c                  |  2 +-
  hw/arm/mps2.c                     |  2 +-
  hw/arm/msf2-soc.c                 |  1 -
  hw/arm/msf2-som.c                 |  2 +-
  hw/arm/musca.c                    |  2 +-
  hw/arm/musicpal.c                 |  2 +-
  hw/arm/netduino2.c                |  2 +-
  hw/arm/nrf51_soc.c                |  2 +-
  hw/arm/nseries.c                  |  2 +-
  hw/arm/omap1.c                    |  2 +-
  hw/arm/omap2.c                    |  2 +-
  hw/arm/omap_sx1.c                 |  2 +-
  hw/arm/palm.c                     |  2 +-
  hw/arm/raspi.c                    |  2 +-
  hw/arm/realview.c                 |  2 +-
  hw/arm/spitz.c                    |  2 +-
  hw/arm/stellaris.c                |  2 +-
  hw/arm/stm32f205_soc.c            |  2 +-
  hw/arm/strongarm.c                |  2 +-
  hw/arm/tosa.c                     |  2 +-
  hw/arm/versatilepb.c              |  2 +-
  hw/arm/vexpress.c                 |  2 +-
  hw/arm/virt.c                     |  2 +-
  hw/arm/xilinx_zynq.c              |  2 +-
  hw/arm/xlnx-versal.c              |  2 +-
  hw/arm/z2.c                       |  2 +-
  hw/intc/arm_gicv3_cpuif.c         |  6 ++---
  hw/intc/armv7m_nvic.c             |  1 -
  target/arm/arm-semi.c             |  1 -
  target/arm/cpu.c                  |  1 -
  target/arm/cpu64.c                |  1 -
  target/arm/kvm.c                  |  1 -
  target/arm/kvm32.c                |  1 -
  target/arm/kvm64.c                |  1 -
  target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
  target/arm/translate.c            |  4 +--
 files changed, 164 insertions(+), 123 deletions(-)
  rename include/hw/arm/{arm.h => boot.h} (96%)
- hw/display/Makefile.objs        |    1 +
- include/exec/helper-head.h      |    3 +
- include/fpu/softfloat.h         |   18 +-
- include/hw/i2c/i2c.h            |   23 +-
- include/hw/register.h           |    6 +-
- target/arm/cpu.h                |   34 +-
- target/arm/helper-a64.h         |   33 +
- target/arm/helper.h             |   14 +-
- hw/arm/vexpress.c               |    6 +-
- hw/core/register.c              |    8 +
- hw/display/sii9022.c            |  191 ++++++
- hw/i2c/core.c                   |   18 -
- hw/i2c/i2c-ddc.c                |    4 +-
- hw/ssi/xilinx_spips.c           |   43 +-
- linux-user/elfload.c            |    2 +
- target/arm/cpu64.c              |    1 +
- target/arm/helper-a64.c         |  269 +++++++++
- target/arm/helper.c             |  481 ++++++++-------
- target/arm/translate-a64.c      | 1266 +++++++++++++++++++++++++++++++++------
- target/arm/translate.c          |   12 +-
- MAINTAINERS                     |   12 +-
- default-configs/arm-softmmu.mak |    2 +
- hw/display/trace-events         |    5 +
-files changed, 1981 insertions(+), 471 deletions(-)
- create mode 100644 hw/display/sii9022.c

-[Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-Ensure that the post write hook is called during reset. This allows us
-to rely on the post write functions instead of having to call them from
-the reset() function.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/register.h | 6 +++---
- hw/core/register.c    | 8 ++++++++
-files changed, 11 insertions(+), 3 deletions(-)
-diff --git a/include/hw/register.h b/include/hw/register.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/register.h
-+++ b/include/hw/register.h
-@@ -XXX,XX +XXX,XX @@ typedef struct RegisterInfoArray RegisterInfoArray;
-  * immediately before the actual write. The returned value is what is written,
-  * giving the handler a chance to modify the written value.
-  * @post_write: Post write callback. Passed the written value. Most write side
-- * effects should be implemented here.
-+ * effects should be implemented here. This is called during device reset.
-  *
-  * @post_read: Post read callback. Passes the value that is about to be returned
-  * for a read. The return value from this function is what is ultimately read,
-@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
-                        bool debug);
- /**
-- * reset a register
-- * @reg: register to reset
-+ * Resets a register. This will also call the post_write hook if it exists.
-+ * @reg: The register to reset.
-  */
- void register_reset(RegisterInfo *reg);
-diff --git a/hw/core/register.c b/hw/core/register.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/core/register.c
-+++ b/hw/core/register.c
-@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
- void register_reset(RegisterInfo *reg)
- {
-+    const RegisterAccessInfo *ac;
-+
-     g_assert(reg);
-     if (!reg->data || !reg->access) {
-         return;
-     }
-+    ac = reg->access;
-+
-     register_write_val(reg, reg->access->reset);
-+
-+    if (ac->post_write) {
-+        ac->post_write(reg, reg->access->reset);
-+    }
- }
- void register_init(RegisterInfo *reg)
---
-.16.2

-[Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe
+Deleted patch
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
-Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
-chip selects are enabled (e.g reading/writing with stripe).
-Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Tested-by: Alistair Francis <alistair.francis@xilinx.com>
-Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++----
-file changed, 37 insertions(+), 4 deletions(-)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
-+++ b/hw/ssi/xilinx_spips.c
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
- {
-     int i;
--    for (i = 0; i < s->num_cs; i++) {
-+    for (i = 0; i < s->num_cs * s->num_busses; i++) {
-         bool old_state = s->cs_lines_state[i];
-         bool new_state = field & (1 << i);
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
-         }
-         qemu_set_irq(s->cs_lines[i], !new_state);
-     }
--    if (!(field & ((1 << s->num_cs) - 1))) {
-+    if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
-         s->snoop_state = SNOOP_CHECKING;
-         s->cmd_dummies = 0;
-         s->link_state = 1;
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
- {
-     if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
-         int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
--        xilinx_spips_update_cs(XILINX_SPIPS(s), field);
-+        bool upper_cs_sel = field & (1 << 1);
-+        bool lower_cs_sel = field & 1;
-+        bool bus0_enabled;
-+        bool bus1_enabled;
-+        uint8_t buses;
-+        int cs = 0;
-+
-+        buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
-+        bus0_enabled = buses & 1;
-+        bus1_enabled = buses & (1 << 1);
-+
-+        if (bus0_enabled && bus1_enabled) {
-+            if (lower_cs_sel) {
-+                cs |= 1;
-+            }
-+            if (upper_cs_sel) {
-+                cs |= 1 << 3;
-+            }
-+        } else if (bus0_enabled) {
-+            if (lower_cs_sel) {
-+                cs |= 1;
-+            }
-+            if (upper_cs_sel) {
-+                cs |= 1 << 1;
-+            }
-+        } else if (bus1_enabled) {
-+            if (lower_cs_sel) {
-+                cs |= 1 << 2;
-+            }
-+            if (upper_cs_sel) {
-+                cs |= 1 << 3;
-+            }
-+        }
-+        xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
-     if (num_effective_busses(s) == 2) {
-         /* Single bit chip-select for qspi */
-         field &= 0x1;
--        field |= field << 1;
-+        field |= field << 3;
-     /* Dual stack U-Page */
-     } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
-                s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
---
-.16.2

-[Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
+[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-I re-use the existing handle_2misc_fcmp_zero handler and tweak it
+This is, after all, how we implement extract2 in tcg/aarch64.
 slightly to deal with the half-precision case.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
+Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++-------------
+ target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
-file changed, 57 insertions(+), 23 deletions(-)
+file changed, 20 insertions(+), 18 deletions(-)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
+@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
-                                    bool is_scalar, bool is_u, bool is_q,
+             } else {
-                                    int size, int rn, int rd)
+                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
- {
+             }
--    bool is_double = (size == 3);
+-        } else if (rm == rn) { /* ROR */
-+    bool is_double = (size == MO_64);
+-            tcg_rm = cpu_reg(s, rm);
-     TCGv_ptr fpst;
+-            if (sf) {
+-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
-     if (!fp_access_check(s)) {
+-            } else {
-         return;
+-                TCGv_i32 tmp = tcg_temp_new_i32();
-     }
+-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
+-                tcg_gen_rotri_i32(tmp, tmp, imm);
--    fpst = get_fpstatus_ptr(false);
+-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
-+    fpst = get_fpstatus_ptr(size == MO_16);
+-                tcg_temp_free_i32(tmp);
+-            }
      if (is_double) {
          TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
          bool swap = false;
          int pass, maxpasses;
 -        switch (opcode) {
 -        case 0x2e: /* FCMLT (zero) */
 -            swap = true;
 -            /* fall through */
 -        case 0x2c: /* FCMGT (zero) */
 -            genfn = gen_helper_neon_cgt_f32;
 -            break;
 -        case 0x2d: /* FCMEQ (zero) */
 -            genfn = gen_helper_neon_ceq_f32;
 -            break;
 -        case 0x6d: /* FCMLE (zero) */
 -            swap = true;
 -            /* fall through */
 -        case 0x6c: /* FCMGE (zero) */
 -            genfn = gen_helper_neon_cge_f32;
 -            break;
 -        default:
 -            g_assert_not_reached();
 +        if (size == MO_16) {
 +            switch (opcode) {
 +            case 0x2e: /* FCMLT (zero) */
 +                swap = true;
 +                /* fall through */
 +            case 0x2c: /* FCMGT (zero) */
 +                genfn = gen_helper_advsimd_cgt_f16;
 +                break;
 +            case 0x2d: /* FCMEQ (zero) */
 +                genfn = gen_helper_advsimd_ceq_f16;
 +                break;
 +            case 0x6d: /* FCMLE (zero) */
 +                swap = true;
 +                /* fall through */
 +            case 0x6c: /* FCMGE (zero) */
 +                genfn = gen_helper_advsimd_cge_f16;
 +                break;
 +            default:
 +                g_assert_not_reached();
 +            }
 +        } else {
 +            switch (opcode) {
 +            case 0x2e: /* FCMLT (zero) */
 +                swap = true;
 +                /* fall through */
 +            case 0x2c: /* FCMGT (zero) */
 +                genfn = gen_helper_neon_cgt_f32;
 +                break;
 +            case 0x2d: /* FCMEQ (zero) */
 +                genfn = gen_helper_neon_ceq_f32;
 +                break;
 +            case 0x6d: /* FCMLE (zero) */
 +                swap = true;
 +                /* fall through */
 +            case 0x6c: /* FCMGE (zero) */
 +                genfn = gen_helper_neon_cge_f32;
 +                break;
 +            default:
 +                g_assert_not_reached();
 +            }
          }
          if (is_scalar) {
              maxpasses = 1;
          } else {
--            maxpasses = is_q ? 4 : 2;
+-            tcg_rm = read_cpu_reg(s, rm, sf);
-+            int vector_size = 8 << is_q;
+-            tcg_rn = read_cpu_reg(s, rn, sf);
-+            maxpasses = vector_size >> size;
+-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
-         }
+-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
+-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-         for (pass = 0; pass < maxpasses; pass++) {
+-            if (!sf) {
--            read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
+-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
-+            read_vec_element_i32(s, tcg_op, rn, pass, size);
++            tcg_rm = cpu_reg(s, rm);
-             if (swap) {
++            tcg_rn = cpu_reg(s, rn);
-                 genfn(tcg_res, tcg_zero, tcg_op, fpst);
++
-             } else {
++            if (sf) {
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
++                /* Specialization to ROR happens in EXTRACT2.  */
-             if (is_scalar) {
++                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
-                 write_fp_sreg(s, rd, tcg_res);
++            } else {
-             } else {
++                TCGv_i32 t0 = tcg_temp_new_i32();
--                write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
++
-+                write_vec_element_i32(s, tcg_res, rd, pass, size);
++                tcg_gen_extrl_i64_i32(t0, tcg_rm);
 +                if (rm == rn) {
 +                    tcg_gen_rotri_i32(t0, t0, imm);
 +                } else {
 +                    TCGv_i32 t1 = tcg_temp_new_i32();
 +                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
 +                    tcg_gen_extract2_i32(t0, t0, t1, imm);
 +                    tcg_temp_free_i32(t1);
 +                }
 +                tcg_gen_extu_i32_i64(tcg_rd, t0);
 +                tcg_temp_free_i32(t0);
              }
          }
-         tcg_temp_free_i32(tcg_res);
+     }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
      fpop = deposit32(opcode, 5, 1, a);
      fpop = deposit32(fpop, 6, 1, u);
 +    rd = extract32(insn, 0, 5);
 +    rn = extract32(insn, 5, 5);
 +
      switch (fpop) {
 +    break;
 +    case 0x2c: /* FCMGT (zero) */
 +    case 0x2d: /* FCMEQ (zero) */
 +    case 0x2e: /* FCMLT (zero) */
 +    case 0x6c: /* FCMGE (zero) */
 +    case 0x6d: /* FCMLE (zero) */
 +        handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
 +        return;
      case 0x18: /* FRINTN */
          need_rmode = true;
          only_in_vector = true;
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 37/42] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
+[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-I only needed to do a little light re-factoring to support the
+The mask implied by the extract is redundant with the one
-half-precision helpers.
+implied by the deposit.  Also, fix spelling of BFXIL.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
+Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++---------------
+ target/arm/translate-a64.c | 6 +++---
-file changed, 54 insertions(+), 26 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
-     case 0xf: /* FMAXP */
+             tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
      case 0x2c: /* FMINNMP */
      case 0x2f: /* FMINP */
 -        /* FP op, size[0] is 32 or 64 bit */
 +        /* FP op, size[0] is 32 or 64 bit*/
          if (!u) {
 -            unallocated_encoding(s);
 -            return;
 +            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +                unallocated_encoding(s);
 +                return;
 +            } else {
 +                size = MO_16;
 +            }
 +        } else {
 +            size = extract32(size, 0, 1) ? MO_64 : MO_32;
          }
 +
          if (!fp_access_check(s)) {
              return;
          }
+-        /* opc == 1, BXFIL fall through to deposit */
--        size = extract32(size, 0, 1) ? 3 : 2;
+-        tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
--        fpst = get_fpstatus_ptr(false);
++        /* opc == 1, BFXIL fall through to deposit */
-+        fpst = get_fpstatus_ptr(size == MO_16);
++        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
-         break;
+         pos = 0;
-     default:
+     } else {
-         unallocated_encoding(s);
+         /* Handle the ri > si case with a deposit
-         return;
+@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
          len = ri;
      }
--    if (size == 3) {
+-    if (opc == 1) { /* BFM, BXFIL */
-+    if (size == MO_64) {
++    if (opc == 1) { /* BFM, BFXIL */
-         TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+         tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
-         TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+     } else {
-         TCGv_i64 tcg_res = tcg_temp_new_i64();
+         /* SBFM or UBFM: We start with zero, and we haven't modified
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
          TCGv_i32 tcg_op2 = tcg_temp_new_i32();
          TCGv_i32 tcg_res = tcg_temp_new_i32();
 -        read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
 -        read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
 +        read_vec_element_i32(s, tcg_op1, rn, 0, size);
 +        read_vec_element_i32(s, tcg_op2, rn, 1, size);
 -        switch (opcode) {
 -        case 0xc: /* FMAXNMP */
 -            gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
 -            break;
 -        case 0xd: /* FADDP */
 -            gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
 -            break;
 -        case 0xf: /* FMAXP */
 -            gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
 -            break;
 -        case 0x2c: /* FMINNMP */
 -            gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
 -            break;
 -        case 0x2f: /* FMINP */
 -            gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
 -            break;
 -        default:
 -            g_assert_not_reached();
 +        if (size == MO_16) {
 +            switch (opcode) {
 +            case 0xc: /* FMAXNMP */
 +                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0xd: /* FADDP */
 +                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0xf: /* FMAXP */
 +                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0x2c: /* FMINNMP */
 +                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0x2f: /* FMINP */
 +                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            default:
 +                g_assert_not_reached();
 +            }
 +        } else {
 +            switch (opcode) {
 +            case 0xc: /* FMAXNMP */
 +                gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0xd: /* FADDP */
 +                gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0xf: /* FMAXP */
 +                gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0x2c: /* FMINNMP */
 +                gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            case 0x2f: /* FMINP */
 +                gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
 +                break;
 +            default:
 +                g_assert_not_reached();
 +            }
          }
          write_fp_sreg(s, rd, tcg_res);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 13/42] target/arm/helper: pass explicit fpst to set_rmode
+[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Alistair Francis <alistair.francis@wdc.com>
-As the rounding mode is now split between FP16 and the rest of
+Commit 89e68b575 "target/arm: Use vector operations for saturation"
-floating point we need to be explicit when tweaking it. Instead of
+causes this abort() when booting QEMU ARM with a Cortex-A15:
 passing the CPU env we now pass the appropriate fpst pointer directly.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
 This patch ensures that we don't hit the abort() in the second switch
 case in disas_neon_data_insn() as we will return from the first case.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-6-alex.bennee@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.h        |  2 +-
+ target/arm/translate.c | 4 ++--
- target/arm/helper.c        |  4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
  target/arm/translate-a64.c | 26 +++++++++++++-------------
  target/arm/translate.c     | 12 ++++++------
 files changed, 22 insertions(+), 22 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
--DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env)
-+DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
- DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
- DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
- /* Set the current fp rounding mode and return the old one.
-  * The argument is a softfloat float_round_ value.
-  */
--uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
-+uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
- {
--    float_status *fp_status = &env->vfp.fp_status;
-+    float_status *fp_status = fpstp;
-     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
-     set_float_rounding_mode(rmode, fp_status);
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
-     {
-         TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-         gen_helper_rints(tcg_res, tcg_op, fpst);
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-         tcg_temp_free_i32(tcg_rmode);
-         break;
-     }
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
-     {
-         TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-         gen_helper_rintd(tcg_res, tcg_op, fpst);
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-         tcg_temp_free_i32(tcg_rmode);
-         break;
-     }
-@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-         if (is_double) {
-             TCGv_i64 tcg_double = read_fp_dreg(s, rn);
-@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
-             tcg_temp_free_i32(tcg_single);
-         }
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-         tcg_temp_free_i32(tcg_rmode);
-         if (!sf) {
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
-     assert(!(is_scalar && is_q));
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-     tcg_fpstatus = get_fpstatus_ptr(false);
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-     tcg_shift = tcg_const_i32(fracbits);
-     if (is_double) {
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
-     tcg_temp_free_ptr(tcg_fpstatus);
-     tcg_temp_free_i32(tcg_shift);
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-     tcg_temp_free_i32(tcg_rmode);
- }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
-     if (is_fcvt) {
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-         tcg_fpstatus = get_fpstatus_ptr(false);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-     } else {
-         tcg_rmode = NULL;
-         tcg_fpstatus = NULL;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
-     }
-     if (is_fcvt) {
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-         tcg_temp_free_i32(tcg_rmode);
-         tcg_temp_free_ptr(tcg_fpstatus);
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-         return;
-     }
--    if (need_fpstatus) {
-+    if (need_fpstatus || need_rmode) {
-         tcg_fpstatus = get_fpstatus_ptr(false);
-     } else {
-         tcg_fpstatus = NULL;
-     }
-     if (need_rmode) {
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-     } else {
-         tcg_rmode = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-     clear_vec_high(s, is_q, rd);
-     if (need_rmode) {
--        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-         tcg_temp_free_i32(tcg_rmode);
-     }
-     if (need_fpstatus) {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     TCGv_i32 tcg_rmode;
+             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
+                            rn_ofs, rm_ofs, vec_size, vec_size,
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
+                            (u ? uqadd_op : sqadd_op) + size);
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+-            break;
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
++            return 0;
-     if (dp) {
+         case NEON_3R_VQSUB:
-         TCGv_i64 tcg_op;
+             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-@@ -XXX,XX +XXX,XX @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
+                            rn_ofs, rm_ofs, vec_size, vec_size,
-         tcg_temp_free_i32(tcg_res);
+                            (u ? uqsub_op : sqsub_op) + size);
-     }
+-            break;
++            return 0;
--    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+         case NEON_3R_VMUL: /* VMUL */
-     tcg_temp_free_i32(tcg_rmode);
+             if (u) {
      tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
      tcg_shift = tcg_const_i32(0);
      tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
 -    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
 +    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
      if (dp) {
          TCGv_i64 tcg_double, tcg_res;
@@ -XXX,XX +XXX,XX @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
          tcg_temp_free_i32(tcg_single);
      }
 -    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
 +    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
      tcg_temp_free_i32(tcg_rmode);
      tcg_temp_free_i32(tcg_shift);
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                          TCGv_ptr fpst = get_fpstatus_ptr(0);
                          TCGv_i32 tcg_rmode;
                          tcg_rmode = tcg_const_i32(float_round_to_zero);
 -                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
 +                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
                          if (dp) {
                              gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
                          } else {
                              gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
                          }
 -                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
 +                        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
                          tcg_temp_free_i32(tcg_rmode);
                          tcg_temp_free_ptr(fpst);
                          break;
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 41/42] linux-user: Report AArch64 FP16 support via hwcap bits
+[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
-Set the appropriate Linux hwcap bits to tell the guest binary if we
+The system_clock_scale global is used only by the armv7m systick
-have implemented half-precision floating point support.
+device; move the extern declaration to the armv7m_systick.h header,
 and expand the comment to explain what it is and that it should
 ideally be replaced with a different approach.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
 ---
- linux-user/elfload.c | 2 ++
+ include/hw/arm/arm.h              |  4 ----
-file changed, 2 insertions(+)
+ include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
 files changed, 22 insertions(+), 4 deletions(-)
-diff --git a/linux-user/elfload.c b/linux-user/elfload.c
+diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/elfload.c
+--- a/include/hw/arm/arm.h
-+++ b/linux-user/elfload.c
++++ b/include/hw/arm/arm.h
-@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
+@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
-     GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
+                                             const struct arm_boot_info *info,
-     GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
+                                             hwaddr mvbar_addr);
-     GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
-+    GET_FEATURE(ARM_FEATURE_V8_FP16,
+-/* Multiplication factor to convert from system clock ticks to qemu timer
-+                ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
+-   ticks.  */
- #undef GET_FEATURE
+-extern int system_clock_scale;
+-
-     return hwcaps;
+ #endif /* HW_ARM_H */
 diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/timer/armv7m_systick.h
 +++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
      qemu_irq irq;
  } SysTickState;
 +/*
 + * Multiplication factor to convert from system clock ticks to qemu timer
 + * ticks. This should be set (by board code, usually) to a value
 + * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
 + * in Hz of the CPU.
 + *
 + * This value is used by the systick device when it is running in
 + * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
 + * set how fast the timer should tick.
 + *
 + * TODO: we should refactor this so that rather than using a global
 + * we use a device property or something similar. This is complicated
 + * because (a) the property would need to be plumbed through from the
 + * board code down through various layers to the systick device
 + * and (b) the property needs to be modifiable after realize, because
 + * the stellaris board uses this to implement the behaviour where the
 + * guest can reprogram the PLL registers to downclock the CPU, and the
 + * systick device needs to react accordingly. Possibly this should
 + * be deferred until we have a good API for modelling clock trees.
 + */
 +extern int system_clock_scale;
 +
  #endif
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
+[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
-Now we have implemented FP16 we can enable it for the "any" CPU.
+The hw/arm/arm.h header now only includes declarations relating
 to boot.c code, so it is only needed by Arm board or SoC code.
 Remove some unnecessary inclusions of it from target/arm files
 and from hw/intc/armv7m_nvic.c.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-[PMM: split out from an earlier patch in the series]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
 ---
- target/arm/cpu64.c | 1 +
+ hw/intc/armv7m_nvic.c | 1 -
-file changed, 1 insertion(+)
+ target/arm/arm-semi.c | 1 -
  target/arm/cpu.c      | 1 -
  target/arm/cpu64.c    | 1 -
  target/arm/kvm.c      | 1 -
  target/arm/kvm32.c    | 1 -
  target/arm/kvm64.c    | 1 -
 files changed, 7 deletions(-)
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/armv7m_nvic.c
++++ b/hw/intc/armv7m_nvic.c
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+ #include "qemu/timer.h"
+-#include "hw/arm/arm.h"
+ #include "hw/intc/armv7m_nvic.h"
+ #include "target/arm/cpu.h"
+ #include "exec/exec-all.h"
+diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/arm-semi.c
++++ b/target/arm/arm-semi.c
+@@ -XXX,XX +XXX,XX @@
+ #else
+ #include "qemu-common.h"
+ #include "exec/gdbstub.h"
+-#include "hw/arm/arm.h"
+ #include "qemu/cutils.h"
+ #endif
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@
+ #if !defined(CONFIG_USER_ONLY)
+ #include "hw/loader.h"
+ #endif
+-#include "hw/arm/arm.h"
+ #include "sysemu/sysemu.h"
+ #include "sysemu/hw_accel.h"
+ #include "kvm_arm.h"
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_any_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@
-     set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
+ #if !defined(CONFIG_USER_ONLY)
-     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ #include "hw/loader.h"
-     set_feature(&cpu->env, ARM_FEATURE_CRC);
+ #endif
-+    set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
+-#include "hw/arm/arm.h"
-     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
+ #include "sysemu/sysemu.h"
-     cpu->dcz_blocksize = 7; /*  512 bytes */
+ #include "sysemu/kvm.h"
- }
+ #include "kvm_arm.h"
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "cpu.h"
  #include "trace.h"
  #include "internals.h"
 -#include "hw/arm/arm.h"
  #include "hw/pci/pci.h"
  #include "exec/memattrs.h"
  #include "exec/address-spaces.h"
 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/kvm.h"
  #include "kvm_arm.h"
  #include "internals.h"
 -#include "hw/arm/arm.h"
  #include "qemu/log.h"
  static inline void set_feature(uint64_t *features, int feature)
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/kvm.h"
  #include "kvm_arm.h"
  #include "internals.h"
 -#include "hw/arm/arm.h"
  static bool have_guest_debug;
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 08/42] arm/vexpress: Add proper display connector emulation
+[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
-From: Linus Walleij <linus.walleij@linaro.org>
+The header file hw/arm/arm.h now includes only declarations
 relating to hw/arm/boot.c functionality. Rename it accordingly,
 and adjust its header comment.
-This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
+The bulk of this commit was created via
-Versatile Express machine, and selects the two I2C devices necessary
+ perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
 in the arm-softmmu.mak configuration so everything will build
 smoothly.
-I am implementing proper handling of the graphics in the Linux
+In a few cases we can just delete the #include:
-kernel and adding proper emulation of SiI9022 and EDID makes the
+hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
-driver probe as nicely as before, retrieving the resolutions
+include/hw/arm/bcm2836.h did not require it.
 supported by the "QEMU monitor" and overall just working nice.
-Cc: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-6-linus.walleij@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
 ---
- hw/arm/vexpress.c               | 6 +++++-
+ include/hw/arm/allwinner-a10.h   | 2 +-
- default-configs/arm-softmmu.mak | 2 ++
+ include/hw/arm/aspeed_soc.h      | 1 -
-files changed, 7 insertions(+), 1 deletion(-)
+ include/hw/arm/bcm2836.h         | 1 -
  include/hw/arm/{arm.h => boot.h} | 8 ++++----
  include/hw/arm/fsl-imx25.h       | 2 +-
  include/hw/arm/fsl-imx31.h       | 2 +-
  include/hw/arm/fsl-imx6.h        | 2 +-
  include/hw/arm/fsl-imx6ul.h      | 2 +-
  include/hw/arm/fsl-imx7.h        | 2 +-
  include/hw/arm/virt.h            | 2 +-
  include/hw/arm/xlnx-versal.h     | 2 +-
  include/hw/arm/xlnx-zynqmp.h     | 2 +-
  hw/arm/armsse.c                  | 2 +-
  hw/arm/armv7m.c                  | 2 +-
  hw/arm/aspeed.c                  | 2 +-
  hw/arm/boot.c                    | 2 +-
  hw/arm/collie.c                  | 2 +-
  hw/arm/exynos4210.c              | 2 +-
  hw/arm/exynos4_boards.c          | 2 +-
  hw/arm/highbank.c                | 2 +-
  hw/arm/integratorcp.c            | 2 +-
  hw/arm/mainstone.c               | 2 +-
  hw/arm/microbit.c                | 2 +-
  hw/arm/mps2-tz.c                 | 2 +-
  hw/arm/mps2.c                    | 2 +-
  hw/arm/msf2-soc.c                | 1 -
  hw/arm/msf2-som.c                | 2 +-
  hw/arm/musca.c                   | 2 +-
  hw/arm/musicpal.c                | 2 +-
  hw/arm/netduino2.c               | 2 +-
  hw/arm/nrf51_soc.c               | 2 +-
  hw/arm/nseries.c                 | 2 +-
  hw/arm/omap1.c                   | 2 +-
  hw/arm/omap2.c                   | 2 +-
  hw/arm/omap_sx1.c                | 2 +-
  hw/arm/palm.c                    | 2 +-
  hw/arm/raspi.c                   | 2 +-
  hw/arm/realview.c                | 2 +-
  hw/arm/spitz.c                   | 2 +-
  hw/arm/stellaris.c               | 2 +-
  hw/arm/stm32f205_soc.c           | 2 +-
  hw/arm/strongarm.c               | 2 +-
  hw/arm/tosa.c                    | 2 +-
  hw/arm/versatilepb.c             | 2 +-
  hw/arm/vexpress.c                | 2 +-
  hw/arm/virt.c                    | 2 +-
  hw/arm/xilinx_zynq.c             | 2 +-
  hw/arm/xlnx-versal.c             | 2 +-
  hw/arm/z2.c                      | 2 +-
 files changed, 49 insertions(+), 52 deletions(-)
  rename include/hw/arm/{arm.h => boot.h} (98%)
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/allwinner-a10.h
++++ b/include/hw/arm/allwinner-a10.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "qemu/error-report.h"
+ #include "hw/char/serial.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/timer/allwinner-a10-pit.h"
+ #include "hw/intc/allwinner-a10-pic.h"
+ #include "hw/net/allwinner_emac.h"
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/aspeed_soc.h
++++ b/include/hw/arm/aspeed_soc.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef ASPEED_SOC_H
+ #define ASPEED_SOC_H
+-#include "hw/arm/arm.h"
+ #include "hw/intc/aspeed_vic.h"
+ #include "hw/misc/aspeed_scu.h"
+ #include "hw/misc/aspeed_sdmc.h"
+diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/bcm2836.h
++++ b/include/hw/arm/bcm2836.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef BCM2836_H
+ #define BCM2836_H
+-#include "hw/arm/arm.h"
+ #include "hw/arm/bcm2835_peripherals.h"
+ #include "hw/intc/bcm2836_control.h"
+diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
+similarity index 98%
+rename from include/hw/arm/arm.h
+rename to include/hw/arm/boot.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/arm.h
++++ b/include/hw/arm/boot.h
+@@ -XXX,XX +XXX,XX @@
+ /*
+- * Misc ARM declarations
++ * ARM kernel loader.
+  *
+  * Copyright (c) 2006 CodeSourcery.
+  * Written by Paul Brook
+@@ -XXX,XX +XXX,XX @@
+  *
+  */
+-#ifndef HW_ARM_H
+-#define HW_ARM_H
++#ifndef HW_ARM_BOOT_H
++#define HW_ARM_BOOT_H
+ #include "exec/memory.h"
+ #include "target/arm/cpu-qom.h"
+@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
+                                             const struct arm_boot_info *info,
+                                             hwaddr mvbar_addr);
+-#endif /* HW_ARM_H */
++#endif /* HW_ARM_BOOT_H */
+diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx25.h
++++ b/include/hw/arm/fsl-imx25.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX25_H
+ #define FSL_IMX25_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/imx_avic.h"
+ #include "hw/misc/imx25_ccm.h"
+ #include "hw/char/imx_serial.h"
+diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx31.h
++++ b/include/hw/arm/fsl-imx31.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX31_H
+ #define FSL_IMX31_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/imx_avic.h"
+ #include "hw/misc/imx31_ccm.h"
+ #include "hw/char/imx_serial.h"
+diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6.h
++++ b/include/hw/arm/fsl-imx6.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX6_H
+ #define FSL_IMX6_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/cpu/a9mpcore.h"
+ #include "hw/misc/imx6_ccm.h"
+ #include "hw/misc/imx6_src.h"
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX6UL_H
+ #define FSL_IMX6UL_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/cpu/a15mpcore.h"
+ #include "hw/misc/imx6ul_ccm.h"
+ #include "hw/misc/imx6_src.h"
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx7.h
++++ b/include/hw/arm/fsl-imx7.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX7_H
+ #define FSL_IMX7_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/cpu/a15mpcore.h"
+ #include "hw/intc/imx_gpcv2.h"
+ #include "hw/misc/imx7_ccm.h"
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/virt.h
++++ b/include/hw/arm/virt.h
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/hwaddr.h"
+ #include "qemu/notify.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/block/flash.h"
+ #include "sysemu/kvm.h"
+ #include "hw/intc/arm_gicv3_common.h"
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-versal.h
++++ b/include/hw/arm/xlnx-versal.h
+@@ -XXX,XX +XXX,XX @@
+ #define XLNX_VERSAL_H
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/arm_gicv3.h"
+ #define TYPE_XLNX_VERSAL "xlnx-versal"
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef XLNX_ZYNQMP_H
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/arm_gic.h"
+ #include "hw/net/cadence_gem.h"
+ #include "hw/char/cadence_uart.h"
+diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/armsse.c
++++ b/hw/arm/armsse.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/registerfields.h"
+ #include "hw/arm/armsse.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ /* Format of the System Information block SYS_CONFIG register */
+ typedef enum SysConfigFormat {
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/armv7m.c
++++ b/hw/arm/armv7m.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/loader.h"
+ #include "elf.h"
+ #include "sysemu/qtest.h"
+diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed.c
++++ b/hw/arm/aspeed.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "exec/address-spaces.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/aspeed.h"
+ #include "hw/arm/aspeed_soc.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/boot.c
++++ b/hw/arm/boot.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include <libfdt.h>
+ #include "hw/hw.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/linux-boot-if.h"
+ #include "sysemu/kvm.h"
+ #include "sysemu/sysemu.h"
+diff --git a/hw/arm/collie.c b/hw/arm/collie.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/collie.c
++++ b/hw/arm/collie.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/boards.h"
+ #include "strongarm.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/block/flash.h"
+ #include "exec/address-spaces.h"
+ #include "cpu.h"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/boards.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/loader.h"
+ #include "hw/arm/exynos4210.h"
+ #include "hw/sd/sdhci.h"
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4_boards.c
++++ b/hw/arm/exynos4_boards.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/sysemu.h"
+ #include "hw/sysbus.h"
+ #include "net/net.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "exec/address-spaces.h"
+ #include "hw/arm/exynos4210.h"
+ #include "hw/net/lan9118.h"
+diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/highbank.c
++++ b/hw/arm/highbank.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/loader.h"
+ #include "net/net.h"
+ #include "sysemu/kvm.h"
+diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/integratorcp.c
++++ b/hw/arm/integratorcp.c
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/misc/arm_integrator_debug.h"
+ #include "hw/net/smc91c111.h"
+ #include "net/net.h"
+diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mainstone.c
++++ b/hw/arm/mainstone.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "hw/hw.h"
+ #include "hw/arm/pxa.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "net/net.h"
+ #include "hw/net/smc91c111.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/microbit.c
++++ b/hw/arm/microbit.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "sysemu/sysemu.h"
+ #include "exec/address-spaces.h"
+diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mps2-tz.c
++++ b/hw/arm/mps2-tz.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu/error-report.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/armv7m.h"
+ #include "hw/or-irq.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mps2.c
++++ b/hw/arm/mps2.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu/error-report.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/armv7m.h"
+ #include "hw/or-irq.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/msf2-soc.c
++++ b/hw/arm/msf2-soc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/units.h"
+ #include "qapi/error.h"
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
+ #include "exec/address-spaces.h"
+ #include "hw/char/serial.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/msf2-som.c
++++ b/hw/arm/msf2-som.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "qemu/error-report.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "exec/address-spaces.h"
+ #include "hw/arm/msf2-soc.h"
+ #include "cpu.h"
+diff --git a/hw/arm/musca.c b/hw/arm/musca.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/musca.c
++++ b/hw/arm/musca.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "exec/address-spaces.h"
+ #include "sysemu/sysemu.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/armsse.h"
+ #include "hw/boards.h"
+ #include "hw/char/pl011.h"
+diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/musicpal.c
++++ b/hw/arm/musicpal.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "net/net.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/netduino2.c
++++ b/hw/arm/netduino2.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/boards.h"
+ #include "qemu/error-report.h"
+ #include "hw/arm/stm32f205_soc.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ static void netduino2_init(MachineState *machine)
+ {
+diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/nrf51_soc.c
++++ b/hw/arm/nrf51_soc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/sysbus.h"
+ #include "hw/boards.h"
+ #include "hw/misc/unimp.h"
+diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/nseries.c
++++ b/hw/arm/nseries.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/bswap.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/arm/omap.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/irq.h"
+ #include "ui/console.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap1.c
++++ b/hw/arm/omap1.c
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
+ #include "hw/boards.h"
+ #include "hw/hw.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/omap.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/arm/soc_dma.h"
+diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap2.c
++++ b/hw/arm/omap2.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/qtest.h"
+ #include "hw/boards.h"
+ #include "hw/hw.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/omap.h"
+ #include "sysemu/sysemu.h"
+ #include "qemu/timer.h"
+diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap_sx1.c
++++ b/hw/arm/omap_sx1.c
+@@ -XXX,XX +XXX,XX @@
+ #include "ui/console.h"
+ #include "hw/arm/omap.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/block/flash.h"
+ #include "sysemu/qtest.h"
+ #include "exec/address-spaces.h"
+diff --git a/hw/arm/palm.c b/hw/arm/palm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/palm.c
++++ b/hw/arm/palm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "ui/console.h"
+ #include "hw/arm/omap.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/input/tsc2xxx.h"
+ #include "hw/loader.h"
+ #include "exec/address-spaces.h"
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/raspi.c
++++ b/hw/arm/raspi.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/error-report.h"
+ #include "hw/boards.h"
+ #include "hw/loader.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "sysemu/sysemu.h"
+ #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
+diff --git a/hw/arm/realview.c b/hw/arm/realview.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/realview.c
++++ b/hw/arm/realview.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/primecell.h"
+ #include "hw/net/lan9118.h"
+ #include "hw/net/smc91c111.h"
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "hw/hw.h"
+ #include "hw/arm/pxa.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/pcmcia.h"
+ #include "hw/i2c/i2c.h"
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/stellaris.c
++++ b/hw/arm/stellaris.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "hw/sysbus.h"
+ #include "hw/ssi/ssi.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "qemu/timer.h"
+ #include "hw/i2c/i2c.h"
+ #include "net/net.h"
+diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/stm32f205_soc.c
++++ b/hw/arm/stm32f205_soc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "exec/address-spaces.h"
+ #include "hw/arm/stm32f205_soc.h"
+diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/strongarm.c
++++ b/hw/arm/strongarm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "strongarm.h"
+ #include "qemu/error-report.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "chardev/char-fe.h"
+ #include "chardev/char-serial.h"
+ #include "sysemu/sysemu.h"
+diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/tosa.c
++++ b/hw/arm/tosa.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "hw/hw.h"
+ #include "hw/arm/pxa.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/sharpsl.h"
+ #include "hw/pcmcia.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/versatilepb.c
++++ b/hw/arm/versatilepb.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/net/smc91c111.h"
+ #include "net/net.h"
+ #include "sysemu/sysemu.h"
 diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/vexpress.c
 +++ b/hw/arm/vexpress.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/arm/arm.h"
+ #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/primecell.h"
- #include "hw/devices.h"
+ #include "hw/net/lan9118.h"
-+#include "hw/i2c/i2c.h"
+ #include "hw/i2c/i2c.h"
- #include "net/net.h"
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
- #include "sysemu/sysemu.h"
+index XXXXXXX..XXXXXXX 100644
- #include "hw/boards.h"
+--- a/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
++++ b/hw/arm/virt.c
-     uint32_t sys_id;
+@@ -XXX,XX +XXX,XX @@
-     DriveInfo *dinfo;
+ #include "qemu/option.h"
-     pflash_t *pflash0;
+ #include "qapi/error.h"
-+    I2CBus *i2c;
+ #include "hw/sysbus.h"
-     ram_addr_t vram_size, sram_size;
+-#include "hw/arm/arm.h"
-     MemoryRegion *sysmem = get_system_memory();
++#include "hw/arm/boot.h"
-     MemoryRegion *vram = g_new(MemoryRegion, 1);
+ #include "hw/arm/primecell.h"
-@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
+ #include "hw/arm/virt.h"
-     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
+ #include "hw/block/flash.h"
-     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
+diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
+index XXXXXXX..XXXXXXX 100644
--    /* VE_SERIALDVI: not modelled */
+--- a/hw/arm/xilinx_zynq.c
-+    dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
++++ b/hw/arm/xilinx_zynq.c
-+    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
+@@ -XXX,XX +XXX,XX @@
-+    i2c_create_slave(i2c, "sii9022", 0x39);
+ #include "qemu-common.h"
+ #include "cpu.h"
-     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
-diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
++#include "hw/arm/boot.h"
-index XXXXXXX..XXXXXXX 100644
+ #include "net/net.h"
---- a/default-configs/arm-softmmu.mak
+ #include "exec/address-spaces.h"
-+++ b/default-configs/arm-softmmu.mak
+ #include "sysemu/sysemu.h"
-@@ -XXX,XX +XXX,XX @@ CONFIG_STELLARIS_INPUT=y
+diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
- CONFIG_STELLARIS_ENET=y
+index XXXXXXX..XXXXXXX 100644
- CONFIG_SSD0303=y
+--- a/hw/arm/xlnx-versal.c
- CONFIG_SSD0323=y
++++ b/hw/arm/xlnx-versal.c
-+CONFIG_DDC=y
+@@ -XXX,XX +XXX,XX @@
-+CONFIG_SII9022=y
+ #include "net/net.h"
- CONFIG_ADS7846=y
+ #include "sysemu/sysemu.h"
- CONFIG_MAX111X=y
+ #include "sysemu/kvm.h"
- CONFIG_SSI=y
+-#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "kvm_arm.h"
  #include "hw/misc/unimp.h"
  #include "hw/intc/arm_gicv3_common.h"
 diff --git a/hw/arm/z2.c b/hw/arm/z2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/z2.c
 +++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/i2c/i2c.h"
  #include "hw/ssi/ssi.h"
  #include "hw/boards.h"
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
+[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
+In ich_vmcr_write() we enforce "writes of BPR fields to less than
 their minimum sets them to the minimum" by doing a "read vbpr and
 write it back" operation.  A typo here meant that we weren't handling
 writes to these fields correctly, because we were reading from VBPR0
 but writing to VBPR1.
-Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
-for matching what is expected by Micron (Numonyx) flashes (the default target
-flash type of the QSPI).
-Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Tested-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Message-id: 20180223232233.31482-3-frasse.iglesias@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
 ---
- hw/ssi/xilinx_spips.c | 2 +-
+ hw/intc/arm_gicv3_cpuif.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/ssi/xilinx_spips.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
+@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         return 2;
+     /* Enforce "writing BPRs to less than minimum sets them to the minimum"
-     case QIOR:
+      * by reading and writing back the fields.
-     case QIOR_4:
+      */
--        return 5;
+-    write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
-+        return 4;
++    write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
-     default:
+     write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
-         return -1;
-     }
+     gicv3_cpuif_virt_update(cs);
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 04/42] i2c: Fix some brace style issues
+Deleted patch
-From: Corey Minyard <cminyard@mvista.com>
-Signed-off-by: Corey Minyard <cminyard@mvista.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-2-linus.walleij@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/i2c/i2c.h | 6 ++----
- hw/i2c/core.c        | 3 +--
-files changed, 3 insertions(+), 6 deletions(-)
-diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/i2c/i2c.h
-+++ b/include/hw/i2c/i2c.h
-@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlave I2CSlave;
- #define I2C_SLAVE_GET_CLASS(obj) \
-      OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
--typedef struct I2CSlaveClass
--{
-+typedef struct I2CSlaveClass {
-     DeviceClass parent_class;
-     /* Callbacks provided by the device.  */
-@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlaveClass
-     int (*event)(I2CSlave *s, enum i2c_event event);
- } I2CSlaveClass;
--struct I2CSlave
--{
-+struct I2CSlave {
-     DeviceState qdev;
-     /* Remaining fields for internal use by the I2C code.  */
-diff --git a/hw/i2c/core.c b/hw/i2c/core.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/core.c
-+++ b/hw/i2c/core.c
-@@ -XXX,XX +XXX,XX @@ struct I2CNode {
- #define I2C_BROADCAST 0x00
--struct I2CBus
--{
-+struct I2CBus {
-     BusState qbus;
-     QLIST_HEAD(, I2CNode) current_devs;
-     uint8_t saved_address;
---
-.16.2

-[Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm
+[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
-From: Alex Bennée <alex.bennee@linaro.org>
+The ICC_CTLR_EL3 register includes some bits which are aliases
 of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
 to keep those bits in the cs->icc_ctlr_el1[] struct fields.
 Unfortunately a missing '~' in the code to update the bits
 in those fields meant that writing to ICC_CTLR_EL3 would corrupt
 the ICC_CLTR_EL1 register values.
-Only one half-precision instruction has been added to this group.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
 ---
  hw/intc/arm_gicv3_cpuif.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-29-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/translate-a64.c | 35 +++++++++++++++++++++++++----------
 file changed, 25 insertions(+), 10 deletions(-)
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/target/arm/translate-a64.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-  *   MVNI - move inverted (shifted) imm into register
+     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
-  *   ORR  - bitwise OR of (shifted) imm with register
-  *   BIC  - bitwise clear of (shifted) imm with register
+     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-+ * With ARMv8.2 we also have:
+-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
-+ *   FMOV half-precision
++    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
-  */
+     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
- static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
+         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
  {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
      uint64_t imm = 0;
      if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
 -        unallocated_encoding(s);
 -        return;
 +        /* Check for FMOV (vector, immediate) - half-precision */
 +        if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
 +            unallocated_encoding(s);
 +            return;
 +        }
      }
+@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     if (!fp_access_check(s)) {
+         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
                      imm |= 0x4000000000000000ULL;
                  }
              } else {
 -                imm = (abcdefgh & 0x3f) << 19;
 -                if (abcdefgh & 0x80) {
 -                    imm |= 0x80000000;
 -                }
 -                if (abcdefgh & 0x40) {
 -                    imm |= 0x3e000000;
 +                if (o2) {
 +                    /* FMOV (vector, immediate) - half-precision */
 +                    imm = vfp_expand_imm(MO_16, abcdefgh);
 +                    /* now duplicate across the lanes */
 +                    imm = bitfield_replicate(imm, 16);
                  } else {
 -                    imm |= 0x40000000;
 +                    imm = (abcdefgh & 0x3f) << 19;
 +                    if (abcdefgh & 0x80) {
 +                        imm |= 0x80000000;
 +                    }
 +                    if (abcdefgh & 0x40) {
 +                        imm |= 0x3e000000;
 +                    } else {
 +                        imm |= 0x40000000;
 +                    }
 +                    imm |= (imm << 32);
                  }
 -                imm |= (imm << 32);
              }
          }
          break;
 +    default:
 +        fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
 +        g_assert_not_reached();
      }
-     if (cmode_3_1 != 7 && is_neg) {
+-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
 +    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
      if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
          cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
      }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16
+[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-This covers the encoding group:
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-  Advanced SIMD scalar three same FP16
+Message-id: 20190520214342.13709-2-philmd@redhat.com
 As all the helpers are already there it is simply a case of calling the
 existing helpers in the scalar context.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-31-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
+ hw/arm/exynos4_boards.c | 24 ------------------------
-file changed, 99 insertions(+)
+file changed, 24 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/hw/arm/exynos4_boards.c
-+++ b/target/arm/translate-a64.c
++++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@
-     tcg_temp_free_i64(tcg_rd);
+ #include "hw/net/lan9118.h"
- }
+ #include "hw/boards.h"
-+/* AdvSIMD scalar three same FP16
+-#undef DEBUG
-+ *  31 30  29 28       24 23  22 21 20  16 15 14 13    11 10  9  5 4  0
+-
-+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
+-//#define DEBUG
-+ * | 0 1 | U | 1 1 1 1 0 | a | 1 0 |  Rm  | 0 0 | opcode | 1 | Rn | Rd |
+-
-+ * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
+-#ifdef DEBUG
-+ * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
+-    #undef PRINT_DEBUG
-+ * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
+-    #define  PRINT_DEBUG(fmt, args...) \
-+ */
+-        do { \
-+static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
+-            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
-+                                                  uint32_t insn)
+-        } while (0)
-+{
+-#else
-+    int rd = extract32(insn, 0, 5);
+-    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
-+    int rn = extract32(insn, 5, 5);
+-#endif
-+    int opcode = extract32(insn, 11, 3);
+-
-+    int rm = extract32(insn, 16, 5);
+ #define SMDK_LAN9118_BASE_ADDR      0x05000000
-+    bool u = extract32(insn, 29, 1);
-+    bool a = extract32(insn, 23, 1);
+ typedef enum Exynos4BoardType {
-+    int fpopcode = opcode | (a << 3) |  (u << 4);
+@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
-+    TCGv_ptr fpst;
+     exynos4_board_binfo.gic_cpu_if_addr =
-+    TCGv_i32 tcg_op1;
+             EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
-+    TCGv_i32 tcg_op2;
-+    TCGv_i32 tcg_res;
+-    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
-+
+-            " kernel_filename: %s\n"
-+    switch (fpopcode) {
+-            " kernel_cmdline: %s\n"
-+    case 0x03: /* FMULX */
+-            " initrd_filename: %s\n",
-+    case 0x04: /* FCMEQ (reg) */
+-            exynos4_board_ram_size[board_type] / 1048576,
-+    case 0x07: /* FRECPS */
+-            exynos4_board_ram_size[board_type],
-+    case 0x0f: /* FRSQRTS */
+-            machine->kernel_filename,
-+    case 0x14: /* FCMGE (reg) */
+-            machine->kernel_cmdline,
-+    case 0x15: /* FACGE */
+-            machine->initrd_filename);
-+    case 0x1a: /* FABD */
+-
-+    case 0x1c: /* FCMGT (reg) */
+     exynos4_boards_init_ram(s, get_system_memory(),
-+    case 0x1d: /* FACGT */
+                             exynos4_board_ram_size[board_type]);
 +        break;
 +    default:
 +        unallocated_encoding(s);
 +        return;
 +    }
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +        unallocated_encoding(s);
 +    }
 +
 +    if (!fp_access_check(s)) {
 +        return;
 +    }
 +
 +    fpst = get_fpstatus_ptr(true);
 +
 +    tcg_op1 = tcg_temp_new_i32();
 +    tcg_op2 = tcg_temp_new_i32();
 +    tcg_res = tcg_temp_new_i32();
 +
 +    read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
 +    read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
 +
 +    switch (fpopcode) {
 +    case 0x03: /* FMULX */
 +        gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x04: /* FCMEQ (reg) */
 +        gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x07: /* FRECPS */
 +        gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x0f: /* FRSQRTS */
 +        gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x14: /* FCMGE (reg) */
 +        gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x15: /* FACGE */
 +        gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x1a: /* FABD */
 +        gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
 +        break;
 +    case 0x1c: /* FCMGT (reg) */
 +        gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x1d: /* FACGT */
 +        gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    write_fp_sreg(s, rd, tcg_res);
 +
 +
 +    tcg_temp_free_i32(tcg_res);
 +    tcg_temp_free_i32(tcg_op1);
 +    tcg_temp_free_i32(tcg_op2);
 +    tcg_temp_free_ptr(fpst);
 +}
 +
  static void handle_2misc_64(DisasContext *s, int opcode, bool u,
                              TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
                              TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
      { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
      { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
      { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
 +    { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
      { 0x00000000, 0x00000000, NULL }
  };
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 05/42] i2c: Move the bus class to i2c.h
+[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
-From: Corey Minyard <cminyard@mvista.com>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-Some devices need access to it.
+It eases code review, unit is explicit.
-Signed-off-by: Corey Minyard <cminyard@mvista.com>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Message-id: 20190520214342.13709-3-philmd@redhat.com
 Message-id: 20180227104903.21353-3-linus.walleij@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/i2c/i2c.h | 17 +++++++++++++++++
+ hw/arm/exynos4_boards.c | 5 +++--
- hw/i2c/core.c        | 17 -----------------
+file changed, 3 insertions(+), 2 deletions(-)
 files changed, 17 insertions(+), 17 deletions(-)
-diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/i2c/i2c.h
+--- a/hw/arm/exynos4_boards.c
-+++ b/include/hw/i2c/i2c.h
++++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@ struct I2CSlave {
+@@ -XXX,XX +XXX,XX @@
-     uint8_t address;
+  */
  #include "qemu/osdep.h"
 +#include "qemu/units.h"
  #include "qapi/error.h"
  #include "qemu/error-report.h"
  #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
  };
-+#define TYPE_I2C_BUS "i2c-bus"
+ static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
+-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-+
+-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
-+typedef struct I2CNode I2CNode;
++    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
-+
++    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
 +struct I2CNode {
 +    I2CSlave *elt;
 +    QLIST_ENTRY(I2CNode) next;
 +};
 +
 +struct I2CBus {
 +    BusState qbus;
 +    QLIST_HEAD(, I2CNode) current_devs;
 +    uint8_t saved_address;
 +    bool broadcast;
 +};
 +
  I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
  void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
  int i2c_bus_busy(I2CBus *bus);
 diff --git a/hw/i2c/core.c b/hw/i2c/core.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/i2c/core.c
 +++ b/hw/i2c/core.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/i2c/i2c.h"
 -typedef struct I2CNode I2CNode;
 -
 -struct I2CNode {
 -    I2CSlave *elt;
 -    QLIST_ENTRY(I2CNode) next;
 -};
 -
  #define I2C_BROADCAST 0x00
 -struct I2CBus {
 -    BusState qbus;
 -    QLIST_HEAD(, I2CNode) current_devs;
 -    uint8_t saved_address;
 -    bool broadcast;
 -};
 -
  static Property i2c_props[] = {
      DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
--#define TYPE_I2C_BUS "i2c-bus"
+ static struct arm_boot_info exynos4_board_binfo = {
 -#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
 -
  static const TypeInfo i2c_bus_info = {
      .name = TYPE_I2C_BUS,
      .parent = TYPE_BUS,
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 06/42] hw/i2c-ddc: Do not fail writes
+Deleted patch
-From: Linus Walleij <linus.walleij@linaro.org>
-The tx function of the DDC I2C slave emulation was returning 1
-on all writes resulting in NACK in the I2C bus. Changing it to
-makes the DDC I2C work fine with bit-banged I2C such as the
-versatile I2C.
-I guess it was not affecting whatever I2C controller this was
-used with until now, but with the Versatile I2C it surely
-does not work.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-4-linus.walleij@linaro.org
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/i2c/i2c-ddc.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/i2c-ddc.c
-+++ b/hw/i2c/i2c-ddc.c
-@@ -XXX,XX +XXX,XX @@ static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
-         s->reg = data;
-         s->firstbyte = false;
-         DPRINTF("[EDID] Written new pointer: %u\n", data);
--        return 1;
-+        return 0;
-     }
-     /* Ignore all writes */
-     s->reg++;
--    return 1;
-+    return 0;
- }
- static void i2c_ddc_init(Object *obj)
---
-.16.2

-[Qemu-devel] [PULL 07/42] hw/sii9022: Add support for Silicon Image SII9022
+Deleted patch
-From: Linus Walleij <linus.walleij@linaro.org>
-This adds support for emulating the Silicon Image SII9022 DVI/HDMI
-bridge. It's not very clever right now, it just acknowledges
-the switch into DDC I2C mode and back. Combining this with the
-existing DDC I2C emulation gives the right behavior on the Versatile
-Express emulation passing through the QEMU EDID to the emulated
-platform.
-Cc: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/display/Makefile.objs |   1 +
- hw/display/sii9022.c     | 191 +++++++++++++++++++++++++++++++++++++++++++++++
- hw/display/trace-events  |   5 ++
-files changed, 197 insertions(+)
- create mode 100644 hw/display/sii9022.c
-diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
-index XXXXXXX..XXXXXXX 100644
---- a/hw/display/Makefile.objs
-+++ b/hw/display/Makefile.objs
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
- common-obj-$(CONFIG_G364FB) += g364fb.o
- common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
- common-obj-$(CONFIG_PL110) += pl110.o
-+common-obj-$(CONFIG_SII9022) += sii9022.o
- common-obj-$(CONFIG_SSD0303) += ssd0303.o
- common-obj-$(CONFIG_SSD0323) += ssd0323.o
- common-obj-$(CONFIG_XEN) += xenfb.o
-diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/hw/display/sii9022.c
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * Silicon Image SiI9022
-+ *
-+ * This is a pretty hollow emulation: all we do is acknowledge that we
-+ * exist (chip ID) and confirm that we get switched over into DDC mode
-+ * so the emulated host can proceed to read out EDID data. All subsequent
-+ * set-up of connectors etc will be acknowledged and ignored.
-+ *
-+ * Copyright (C) 2018 Linus Walleij
-+ *
-+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+ * See the COPYING file in the top-level directory.
-+ * SPDX-License-Identifier: GPL-2.0-or-later
-+ */
-+
-+#include "qemu/osdep.h"
-+#include "qemu-common.h"
-+#include "hw/i2c/i2c.h"
-+#include "hw/i2c/i2c-ddc.h"
-+#include "trace.h"
-+
-+#define SII9022_SYS_CTRL_DATA 0x1a
-+#define SII9022_SYS_CTRL_PWR_DWN 0x10
-+#define SII9022_SYS_CTRL_AV_MUTE 0x08
-+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
-+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
-+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
-+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
-+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
-+#define SII9022_REG_CHIPID 0x1b
-+#define SII9022_INT_ENABLE 0x3c
-+#define SII9022_INT_STATUS 0x3d
-+#define SII9022_INT_STATUS_HOTPLUG 0x01;
-+#define SII9022_INT_STATUS_PLUGGED 0x04;
-+
-+#define TYPE_SII9022 "sii9022"
-+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
-+
-+typedef struct sii9022_state {
-+    I2CSlave parent_obj;
-+    uint8_t ptr;
-+    bool addr_byte;
-+    bool ddc_req;
-+    bool ddc_skip_finish;
-+    bool ddc;
-+} sii9022_state;
-+
-+static const VMStateDescription vmstate_sii9022 = {
-+    .name = "sii9022",
-+    .version_id = 1,
-+    .minimum_version_id = 1,
-+    .fields = (VMStateField[]) {
-+        VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
-+        VMSTATE_UINT8(ptr, sii9022_state),
-+        VMSTATE_BOOL(addr_byte, sii9022_state),
-+        VMSTATE_BOOL(ddc_req, sii9022_state),
-+        VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
-+        VMSTATE_BOOL(ddc, sii9022_state),
-+        VMSTATE_END_OF_LIST()
-+    }
-+};
-+
-+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
-+{
-+    sii9022_state *s = SII9022(i2c);
-+
-+    switch (event) {
-+    case I2C_START_SEND:
-+        s->addr_byte = true;
-+        break;
-+    case I2C_START_RECV:
-+        break;
-+    case I2C_FINISH:
-+        break;
-+    case I2C_NACK:
-+        break;
-+    }
-+
-+    return 0;
-+}
-+
-+static int sii9022_rx(I2CSlave *i2c)
-+{
-+    sii9022_state *s = SII9022(i2c);
-+    uint8_t res = 0x00;
-+
-+    switch (s->ptr) {
-+    case SII9022_SYS_CTRL_DATA:
-+        if (s->ddc_req) {
-+            /* Acknowledge DDC bus request */
-+            res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
-+        }
-+        break;
-+    case SII9022_REG_CHIPID:
-+        res = 0xb0;
-+        break;
-+    case SII9022_INT_STATUS:
-+        /* Something is cold-plugged in, no interrupts */
-+        res = SII9022_INT_STATUS_PLUGGED;
-+        break;
-+    default:
-+        break;
-+    }
-+
-+    trace_sii9022_read_reg(s->ptr, res);
-+    s->ptr++;
-+
-+    return res;
-+}
-+
-+static int sii9022_tx(I2CSlave *i2c, uint8_t data)
-+{
-+    sii9022_state *s = SII9022(i2c);
-+
-+    if (s->addr_byte) {
-+        s->ptr = data;
-+        s->addr_byte = false;
-+        return 0;
-+    }
-+
-+    switch (s->ptr) {
-+    case SII9022_SYS_CTRL_DATA:
-+        if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
-+            s->ddc_req = true;
-+            if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
-+                s->ddc = true;
-+                /* Skip this finish since we just switched to DDC */
-+                s->ddc_skip_finish = true;
-+                trace_sii9022_switch_mode("DDC");
-+            }
-+        } else {
-+            s->ddc_req = false;
-+            s->ddc = false;
-+            trace_sii9022_switch_mode("normal");
-+        }
-+        break;
-+    default:
-+        break;
-+    }
-+
-+    trace_sii9022_write_reg(s->ptr, data);
-+    s->ptr++;
-+
-+    return 0;
-+}
-+
-+static void sii9022_reset(DeviceState *dev)
-+{
-+    sii9022_state *s = SII9022(dev);
-+
-+    s->ptr = 0;
-+    s->addr_byte = false;
-+    s->ddc_req = false;
-+    s->ddc_skip_finish = false;
-+    s->ddc = false;
-+}
-+
-+static void sii9022_realize(DeviceState *dev, Error **errp)
-+{
-+    I2CBus *bus;
-+
-+    bus = I2C_BUS(qdev_get_parent_bus(dev));
-+    i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
-+}
-+
-+static void sii9022_class_init(ObjectClass *klass, void *data)
-+{
-+    DeviceClass *dc = DEVICE_CLASS(klass);
-+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
-+
-+    k->event = sii9022_event;
-+    k->recv = sii9022_rx;
-+    k->send = sii9022_tx;
-+    dc->reset = sii9022_reset;
-+    dc->realize = sii9022_realize;
-+    dc->vmsd = &vmstate_sii9022;
-+}
-+
-+static const TypeInfo sii9022_info = {
-+    .name          = TYPE_SII9022,
-+    .parent        = TYPE_I2C_SLAVE,
-+    .instance_size = sizeof(sii9022_state),
-+    .class_init    = sii9022_class_init,
-+};
-+
-+static void sii9022_register_types(void)
-+{
-+    type_register_static(&sii9022_info);
-+}
-+
-+type_init(sii9022_register_types)
-diff --git a/hw/display/trace-events b/hw/display/trace-events
-index XXXXXXX..XXXXXXX 100644
---- a/hw/display/trace-events
-+++ b/hw/display/trace-events
-@@ -XXX,XX +XXX,XX @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
- vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
- vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
- vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
-+
-+# hw/display/sii9022.c
-+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
-+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
-+sii9022_switch_mode(const char *mode) "mode: %s"
---
-.16.2

-[Qemu-devel] [PULL 09/42] include/exec/helper-head.h: support f16 in helper calls
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This allows us to explicitly pass float16 to helpers rather than
-assuming uint32_t and dealing with the result. Of course they will be
-passed in i32 sized registers by default.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-2-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/exec/helper-head.h | 3 +++
-file changed, 3 insertions(+)
-diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/helper-head.h
-+++ b/include/exec/helper-head.h
-@@ -XXX,XX +XXX,XX @@
- #define dh_alias_int i32
- #define dh_alias_i64 i64
- #define dh_alias_s64 i64
-+#define dh_alias_f16 i32
- #define dh_alias_f32 i32
- #define dh_alias_f64 i64
- #define dh_alias_ptr ptr
-@@ -XXX,XX +XXX,XX @@
- #define dh_ctype_int int
- #define dh_ctype_i64 uint64_t
- #define dh_ctype_s64 int64_t
-+#define dh_ctype_f16 float16
- #define dh_ctype_f32 float32
- #define dh_ctype_f64 float64
- #define dh_ctype_ptr void *
-@@ -XXX,XX +XXX,XX @@
- #define dh_is_signed_s32 1
- #define dh_is_signed_i64 0
- #define dh_is_signed_s64 1
-+#define dh_is_signed_f16 0
- #define dh_is_signed_f32 0
- #define dh_is_signed_f64 0
- #define dh_is_signed_tl  0
---
-.16.2

-[Qemu-devel] [PULL 10/42] target/arm/cpu64: introduce ARM_V8_FP16 feature bit
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-3-alex.bennee@linaro.org
-[PMM: postpone actually enabling feature until end of the
- patch series]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h | 1 +
-file changed, 1 insertion(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ enum arm_features {
-     ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
-     ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
-     ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
-+    ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
- };
- static inline int arm_feature(CPUARMState *env, int feature)
---
-.16.2

-[Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-4-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h | 1 +
-file changed, 1 insertion(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct {
-  *  Qn = regs[n].d[1]:regs[n].d[0]
-  *  Dn = regs[n].d[0]
-  *  Sn = regs[n].d[0] bits 31..0
-+ *  Hn = regs[n].d[0] bits 15..0
-  *
-  * This corresponds to the architecturally defined mapping between
-  * the two execution states, and means we do not need to explicitly
---
-.16.2

-[Qemu-devel] [PULL 12/42] target/arm/cpu.h: add additional float_status flags
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Half-precision flush to zero behaviour is controlled by a separate
-FZ16 bit in the FPCR. To handle this we pass a pointer to
-fp_status_fp16 when working on half-precision operations. The value of
-the presented FPCR is calculated from an amalgam of the two when read.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h           | 32 ++++++++++++++++++++++------
- target/arm/helper.c        | 26 ++++++++++++++++++-----
- target/arm/translate-a64.c | 53 +++++++++++++++++++++++++---------------------
-files changed, 75 insertions(+), 36 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
-         /* scratch space when Tn are not sufficient.  */
-         uint32_t scratch[8];
--        /* fp_status is the "normal" fp status. standard_fp_status retains
--         * values corresponding to the ARM "Standard FPSCR Value", ie
--         * default-NaN, flush-to-zero, round-to-nearest and is used by
--         * any operations (generally Neon) which the architecture defines
--         * as controlled by the standard FPSCR value rather than the FPSCR.
-+        /* There are a number of distinct float control structures:
-+         *
-+         *  fp_status: is the "normal" fp status.
-+         *  fp_status_fp16: used for half-precision calculations
-+         *  standard_fp_status : the ARM "Standard FPSCR Value"
-+         *
-+         * Half-precision operations are governed by a separate
-+         * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
-+         * status structure to control this.
-+         *
-+         * The "Standard FPSCR", ie default-NaN, flush-to-zero,
-+         * round-to-nearest and is used by any operations (generally
-+         * Neon) which the architecture defines as controlled by the
-+         * standard FPSCR value rather than the FPSCR.
-          *
-          * To avoid having to transfer exception bits around, we simply
-          * say that the FPSCR cumulative exception flags are the logical
--         * OR of the flags in the two fp statuses. This relies on the
-+         * OR of the flags in the three fp statuses. This relies on the
-          * only thing which needs to read the exception flags being
-          * an explicit FPSCR read.
-          */
-         float_status fp_status;
-+        float_status fp_status_f16;
-         float_status standard_fp_status;
-         /* ZCR_EL[1-3] */
-@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
- uint32_t vfp_get_fpscr(CPUARMState *env);
- void vfp_set_fpscr(CPUARMState *env, uint32_t val);
--/* For A64 the FPSCR is split into two logically distinct registers,
-+/* FPCR, Floating Point Control Register
-+ * FPSR, Floating Poiht Status Register
-+ *
-+ * For A64 the FPSCR is split into two logically distinct registers,
-  * FPCR and FPSR. However since they still use non-overlapping bits
-  * we store the underlying state in fpscr and just mask on read/write.
-  */
- #define FPSR_MASK 0xf800009f
- #define FPCR_MASK 0x07f79f00
-+
-+#define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
-+#define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
-+#define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
-+
- static inline uint32_t vfp_get_fpsr(CPUARMState *env)
- {
-     return vfp_get_fpscr(env) & FPSR_MASK;
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
-             | (env->vfp.vec_stride << 20);
-     i = get_float_exception_flags(&env->vfp.fp_status);
-     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
-+    i |= get_float_exception_flags(&env->vfp.fp_status_f16);
-     fpscr |= vfp_exceptbits_from_host(i);
-     return fpscr;
- }
-@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
-             break;
-         }
-         set_float_rounding_mode(i, &env->vfp.fp_status);
-+        set_float_rounding_mode(i, &env->vfp.fp_status_f16);
-     }
--    if (changed & (1 << 24)) {
--        set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
--        set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
-+    if (changed & FPCR_FZ16) {
-+        bool ftz_enabled = val & FPCR_FZ16;
-+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
-+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
-+    }
-+    if (changed & FPCR_FZ) {
-+        bool ftz_enabled = val & FPCR_FZ;
-+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
-+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
-+    }
-+    if (changed & FPCR_DN) {
-+        bool dnan_enabled = val & FPCR_DN;
-+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
-+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
-     }
--    if (changed & (1 << 25))
--        set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
-+    /* The exception flags are ORed together when we read fpscr so we
-+     * only need to preserve the current state in one of our
-+     * float_status values.
-+     */
-     i = vfp_exceptbits_to_host(val);
-     set_float_exception_flags(i, &env->vfp.fp_status);
-+    set_float_exception_flags(0, &env->vfp.fp_status_f16);
-     set_float_exception_flags(0, &env->vfp.standard_fp_status);
- }
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
-     tcg_temp_free_i64(tmp);
- }
--static TCGv_ptr get_fpstatus_ptr(void)
-+static TCGv_ptr get_fpstatus_ptr(bool is_f16)
- {
-     TCGv_ptr statusptr = tcg_temp_new_ptr();
-     int offset;
--    /* In A64 all instructions (both FP and Neon) use the FPCR;
--     * there is no equivalent of the A32 Neon "standard FPSCR value"
--     * and all operations use vfp.fp_status.
-+    /* In A64 all instructions (both FP and Neon) use the FPCR; there
-+     * is no equivalent of the A32 Neon "standard FPSCR value".
-+     * However half-precision operations operate under a different
-+     * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
-      */
--    offset = offsetof(CPUARMState, vfp.fp_status);
-+    if (is_f16) {
-+        offset = offsetof(CPUARMState, vfp.fp_status_f16);
-+    } else {
-+        offset = offsetof(CPUARMState, vfp.fp_status);
-+    }
-     tcg_gen_addi_ptr(statusptr, cpu_env, offset);
-     return statusptr;
- }
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
-                               bool cmp_with_zero, bool signal_all_nans)
- {
-     TCGv_i64 tcg_flags = tcg_temp_new_i64();
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     if (is_double) {
-         TCGv_i64 tcg_vn, tcg_vm;
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
-     TCGv_i32 tcg_op;
-     TCGv_i32 tcg_res;
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op = read_fp_sreg(s, rn);
-     tcg_res = tcg_temp_new_i32();
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
-         return;
-     }
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op = read_fp_dreg(s, rn);
-     tcg_res = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
-     TCGv_ptr fpst;
-     tcg_res = tcg_temp_new_i32();
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_sreg(s, rn);
-     tcg_op2 = read_fp_sreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
-     TCGv_ptr fpst;
-     tcg_res = tcg_temp_new_i64();
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_dreg(s, rn);
-     tcg_op2 = read_fp_dreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
- {
-     TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
-     TCGv_i32 tcg_res = tcg_temp_new_i32();
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_sreg(s, rn);
-     tcg_op2 = read_fp_sreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
- {
-     TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
-     TCGv_i64 tcg_res = tcg_temp_new_i64();
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     tcg_op1 = read_fp_dreg(s, rn);
-     tcg_op2 = read_fp_dreg(s, rm);
-@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
-     TCGv_ptr tcg_fpstatus;
-     TCGv_i32 tcg_shift;
--    tcg_fpstatus = get_fpstatus_ptr();
-+    tcg_fpstatus = get_fpstatus_ptr(false);
-     tcg_shift = tcg_const_i32(64 - scale);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
-         TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
-         TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
-         TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
--        TCGv_ptr fpst = get_fpstatus_ptr();
-+        TCGv_ptr fpst = get_fpstatus_ptr(false);
-         assert(esize == 32);
-         assert(elements == 4);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
-         }
-         size = extract32(size, 0, 1) ? 3 : 2;
--        fpst = get_fpstatus_ptr();
-+        fpst = get_fpstatus_ptr(false);
-         break;
-     default:
-         unallocated_encoding(s);
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
-                                    int fracbits, int size)
- {
-     bool is_double = size == 3 ? true : false;
--    TCGv_ptr tcg_fpst = get_fpstatus_ptr();
-+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
-     TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
-     TCGv_i64 tcg_int = tcg_temp_new_i64();
-     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
-     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
--    tcg_fpstatus = get_fpstatus_ptr();
-+    tcg_fpstatus = get_fpstatus_ptr(false);
-     tcg_shift = tcg_const_i32(fracbits);
-     if (is_double) {
-@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
-                                int fpopcode, int rd, int rn, int rm)
- {
-     int pass;
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     for (pass = 0; pass < elements; pass++) {
-         if (size) {
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
-         return;
-     }
--    fpst = get_fpstatus_ptr();
-+    fpst = get_fpstatus_ptr(false);
-     if (is_double) {
-         TCGv_i64 tcg_op = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
-                                     int size, int rn, int rd)
- {
-     bool is_double = (size == 3);
--    TCGv_ptr fpst = get_fpstatus_ptr();
-+    TCGv_ptr fpst = get_fpstatus_ptr(false);
-     if (is_double) {
-         TCGv_i64 tcg_op = tcg_temp_new_i64();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
-     if (is_fcvt) {
-         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-         gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
--        tcg_fpstatus = get_fpstatus_ptr();
-+        tcg_fpstatus = get_fpstatus_ptr(false);
-     } else {
-         tcg_rmode = NULL;
-         tcg_fpstatus = NULL;
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
-     /* Floating point operations need fpst */
-     if (opcode >= 0x58) {
--        fpst = get_fpstatus_ptr();
-+        fpst = get_fpstatus_ptr(false);
-     } else {
-         fpst = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-     }
-     if (need_fpstatus) {
--        tcg_fpstatus = get_fpstatus_ptr();
-+        tcg_fpstatus = get_fpstatus_ptr(false);
-     } else {
-         tcg_fpstatus = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     }
-     if (is_fp) {
--        fpst = get_fpstatus_ptr();
-+        fpst = get_fpstatus_ptr(false);
-     } else {
-         fpst = NULL;
-     }
---
-.16.2

-[Qemu-devel] [PULL 14/42] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This implements the half-precision variants of the across vector
-reduction operations. This involves a re-factor of the reduction code
-which more closely matches the ARM ARM order (and handles 8 element
-reductions).
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |   4 ++
- target/arm/helper-a64.c    |  18 ++++++
- target/arm/translate-a64.c | 140 ++++++++++++++++++++++++++++-----------------
-files changed, 109 insertions(+), 53 deletions(-)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
- DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
- DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
-                    i64, env, i64, i64, i64)
-+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
-+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
-+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
-+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
- {
-     return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
- }
-+
-+/*
-+ * AdvSIMD half-precision
-+ */
-+
-+#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
-+
-+#define ADVSIMD_HALFOP(name) \
-+float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
-+{ \
-+    float_status *fpst = fpstp; \
-+    return float16_ ## name(a, b, fpst);    \
-+}
-+
-+ADVSIMD_HALFOP(min)
-+ADVSIMD_HALFOP(max)
-+ADVSIMD_HALFOP(minnum)
-+ADVSIMD_HALFOP(maxnum)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
-     tcg_temp_free_i64(tcg_resh);
- }
--static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
--                        int opc, bool is_min, TCGv_ptr fpst)
-+/*
-+ * do_reduction_op helper
-+ *
-+ * This mirrors the Reduce() pseudocode in the ARM ARM. It is
-+ * important for correct NaN propagation that we do these
-+ * operations in exactly the order specified by the pseudocode.
-+ *
-+ * This is a recursive function, TCG temps should be freed by the
-+ * calling function once it is done with the values.
-+ */
-+static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
-+                                int esize, int size, int vmap, TCGv_ptr fpst)
- {
--    /* Helper function for disas_simd_across_lanes: do a single precision
--     * min/max operation on the specified two inputs,
--     * and return the result in tcg_elt1.
--     */
--    if (opc == 0xc) {
--        if (is_min) {
--            gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
--        } else {
--            gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
--        }
-+    if (esize == size) {
-+        int element;
-+        TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
-+        TCGv_i32 tcg_elem;
-+
-+        /* We should have one register left here */
-+        assert(ctpop8(vmap) == 1);
-+        element = ctz32(vmap);
-+        assert(element < 8);
-+
-+        tcg_elem = tcg_temp_new_i32();
-+        read_vec_element_i32(s, tcg_elem, rn, element, msize);
-+        return tcg_elem;
-     } else {
--        assert(opc == 0xf);
--        if (is_min) {
--            gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
--        } else {
--            gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-+        int bits = size / 2;
-+        int shift = ctpop8(vmap) / 2;
-+        int vmap_lo = (vmap >> shift) & vmap;
-+        int vmap_hi = (vmap & ~vmap_lo);
-+        TCGv_i32 tcg_hi, tcg_lo, tcg_res;
-+
-+        tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
-+        tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
-+        tcg_res = tcg_temp_new_i32();
-+
-+        switch (fpopcode) {
-+        case 0x0c: /* fmaxnmv half-precision */
-+            gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x0f: /* fmaxv half-precision */
-+            gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x1c: /* fminnmv half-precision */
-+            gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x1f: /* fminv half-precision */
-+            gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x2c: /* fmaxnmv */
-+            gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x2f: /* fmaxv */
-+            gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x3c: /* fminnmv */
-+            gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        case 0x3f: /* fminv */
-+            gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
-+            break;
-+        default:
-+            g_assert_not_reached();
-         }
-+
-+        tcg_temp_free_i32(tcg_hi);
-+        tcg_temp_free_i32(tcg_lo);
-+        return tcg_res;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
-         break;
-     case 0xc: /* FMAXNMV, FMINNMV */
-     case 0xf: /* FMAXV, FMINV */
--        if (!is_u || !is_q || extract32(size, 0, 1)) {
--            unallocated_encoding(s);
--            return;
--        }
--        /* Bit 1 of size field encodes min vs max, and actual size is always
--         * 32 bits: adjust the size variable so following code can rely on it
-+        /* Bit 1 of size field encodes min vs max and the actual size
-+         * depends on the encoding of the U bit. If not set (and FP16
-+         * enabled) then we do half-precision float instead of single
-+         * precision.
-          */
-         is_min = extract32(size, 1, 1);
-         is_fp = true;
--        size = 2;
-+        if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+            size = 1;
-+        } else if (!is_u || !is_q || extract32(size, 0, 1)) {
-+            unallocated_encoding(s);
-+            return;
-+        } else {
-+            size = 2;
-+        }
-         break;
-     default:
-         unallocated_encoding(s);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
-         }
-     } else {
--        /* Floating point ops which work on 32 bit (single) intermediates.
-+        /* Floating point vector reduction ops which work across 32
-+         * bit (single) or 16 bit (half-precision) intermediates.
-          * Note that correct NaN propagation requires that we do these
-          * operations in exactly the order specified by the pseudocode.
-          */
--        TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
--        TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
--        TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
--        TCGv_ptr fpst = get_fpstatus_ptr(false);
--
--        assert(esize == 32);
--        assert(elements == 4);
--
--        read_vec_element(s, tcg_elt, rn, 0, MO_32);
--        tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
--        read_vec_element(s, tcg_elt, rn, 1, MO_32);
--        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
--
--        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
--
--        read_vec_element(s, tcg_elt, rn, 2, MO_32);
--        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
--        read_vec_element(s, tcg_elt, rn, 3, MO_32);
--        tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
--
--        do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
--
--        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
--
--        tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
--        tcg_temp_free_i32(tcg_elt1);
--        tcg_temp_free_i32(tcg_elt2);
--        tcg_temp_free_i32(tcg_elt3);
-+        TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
-+        int fpopcode = opcode | is_min << 4 | is_u << 5;
-+        int vmap = (1 << elements) - 1;
-+        TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
-+                                             (is_q ? 128 : 64), vmap, fpst);
-+        tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
-+        tcg_temp_free_i32(tcg_res32);
-         tcg_temp_free_ptr(fpst);
-     }
---
-.16.2

-[Qemu-devel] [PULL 15/42] arm/translate-a64: handle_3same_64 comment fix
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-We do implement all the opcodes.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-8-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 3 +--
-file changed, 1 insertion(+), 2 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
-     /* Handle 64x64->64 opcodes which are shared between the scalar
-      * and vector 3-same groups. We cover every opcode where size == 3
-      * is valid in either the three-reg-same (integer, not pairwise)
--     * or scalar-three-reg-same groups. (Some opcodes are not yet
--     * implemented.)
-+     * or scalar-three-reg-same groups.
-      */
-     TCGCond cond;
---
-.16.2

-[Qemu-devel] [PULL 39/42] arm/translate-a64: add all single op FP16 to handle_fp_1src_half
+[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
-This includes FMOV, FABS, FNEG, FSQRT and  FRINT[NPMZAXI]. We re-use
+QEMU already supports pl330. Instantiate it for Exynos4210.
 existing helpers to achieve this.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-32-alex.bennee@linaro.org
+/ {
     soc: soc {
         amba {
             pdma0: pdma@12680000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12680000 0x1000>;
                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA0>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             pdma1: pdma@12690000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12690000 0x1000>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA1>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             mdma1: mdma@12850000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12850000 0x1000>;
                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_MDMA>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <1>;
             };
         };
     };
 };
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190520214342.13709-4-philmd@redhat.com
 [PMD: Do not set default qdev properties, create the controllers in the SoC
       rather than the board (Peter Maydell), add dtsi in commit message]
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
+ hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
-file changed, 71 insertions(+)
+file changed, 26 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/hw/arm/exynos4210.c
-+++ b/target/arm/translate-a64.c
++++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@
-     tcg_temp_free_i64(t_true);
+ /* EHCI */
  #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 +/* DMA */
 +#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
 +#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
 +#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
 +
  static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
 x09, 0x00, 0x00, 0x00 };
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
      return (0x9 << ARM_AFF1_SHIFT) | cpu;
  }
-+/* Floating-point data-processing (1 source) - half precision */
++static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
 +static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
 +{
-+    TCGv_ptr fpst = NULL;
++    SysBusDevice *busdev;
-+    TCGv_i32 tcg_op = tcg_temp_new_i32();
++    DeviceState *dev;
 +    TCGv_i32 tcg_res = tcg_temp_new_i32();
 +
-+    read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
++    dev = qdev_create(NULL, "pl330");
-+
++    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
-+    switch (opcode) {
++    qdev_init_nofail(dev);
-+    case 0x0: /* FMOV */
++    busdev = SYS_BUS_DEVICE(dev);
-+        tcg_gen_mov_i32(tcg_res, tcg_op);
++    sysbus_mmio_map(busdev, 0, base);
-+        break;
++    sysbus_connect_irq(busdev, 0, irq);
 +    case 0x1: /* FABS */
 +        tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
 +        break;
 +    case 0x2: /* FNEG */
 +        tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
 +        break;
 +    case 0x3: /* FSQRT */
 +        gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
 +        break;
 +    case 0x8: /* FRINTN */
 +    case 0x9: /* FRINTP */
 +    case 0xa: /* FRINTM */
 +    case 0xb: /* FRINTZ */
 +    case 0xc: /* FRINTA */
 +    {
 +        TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
 +        fpst = get_fpstatus_ptr(true);
 +
 +        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 +        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
 +
 +        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 +        tcg_temp_free_i32(tcg_rmode);
 +        break;
 +    }
 +    case 0xe: /* FRINTX */
 +        fpst = get_fpstatus_ptr(true);
 +        gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
 +        break;
 +    case 0xf: /* FRINTI */
 +        fpst = get_fpstatus_ptr(true);
 +        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
 +        break;
 +    default:
 +        abort();
 +    }
 +
 +    write_fp_sreg(s, rd, tcg_res);
 +
 +    if (fpst) {
 +        tcg_temp_free_ptr(fpst);
 +    }
 +    tcg_temp_free_i32(tcg_op);
 +    tcg_temp_free_i32(tcg_res);
 +}
 +
- /* Floating-point data-processing (1 source) - single precision */
+ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
  static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
  {
-@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
+     Exynos4210State *s = g_new0(Exynos4210State, 1);
+@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
-             handle_fp_1src_double(s, opcode, rd, rn);
+     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
-             break;
+             s->irq_table[exynos4210_get_irq(28, 3)]);
-+        case 3:
-+            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
++    /*** DMA controllers ***/
-+                unallocated_encoding(s);
++    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
-+                return;
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
-+            }
++    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
 +                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
 +    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
 +                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 +
-+            if (!fp_access_check(s)) {
+     return s;
-+                return;
+ }
 +            }
 +
 +            handle_fp_1src_half(s, opcode, rd, rn);
 +            break;
          default:
              unallocated_encoding(s);
          }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 16/42] arm/translate-a64: initial decode for simd_three_reg_same_fp16
+[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-This is the initial decode skeleton for the Advanced SIMD three same
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-instruction group.
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20190520214342.13709-5-philmd@redhat.com
 The fprintf is purely to aid debugging as the additional instructions
 are added. It will be removed once the group is complete.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180227143852.11175-9-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
+ include/hw/arm/exynos4210.h |  9 +++++++--
-file changed, 73 insertions(+)
+ hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
  hw/arm/exynos4_boards.c     |  9 ++++++---
 files changed, 37 insertions(+), 9 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/include/hw/arm/exynos4210.h
-+++ b/target/arm/translate-a64.c
++++ b/include/hw/arm/exynos4210.h
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
-     }
+ } Exynos4210Irq;
  typedef struct Exynos4210State {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +    /*< public >*/
      ARMCPU *cpu[EXYNOS4210_NCPUS];
      Exynos4210Irq irqs;
      qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
      I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
  } Exynos4210State;
 +#define TYPE_EXYNOS4210_SOC "exynos4210"
 +#define EXYNOS4210_SOC(obj) \
 +    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
 +
  void exynos4210_write_secondary(ARMCPU *cpu,
          const struct arm_boot_info *info);
 -Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
 -
  /* Initialize exynos4210 IRQ subsystem stub */
  qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
      sysbus_connect_irq(busdev, 0, irq);
  }
-+/*
+-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
-+ * Advanced SIMD three same (ARMv8.2 FP16 variants)
++static void exynos4210_realize(DeviceState *socdev, Error **errp)
-+ *
+ {
-+ *  31  30  29  28       24 23  22 21 20  16 15 14 13    11 10  9    5 4    0
+-    Exynos4210State *s = g_new0(Exynos4210State, 1);
-+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
++    Exynos4210State *s = EXYNOS4210_SOC(socdev);
-+ * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 |  Rm  | 0 0 | opcode | 1 |  Rn  |  Rd  |
++    MemoryRegion *system_mem = get_system_memory();
-+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
+     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
-+ *
+     SysBusDevice *busdev;
-+ * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
+     DeviceState *dev;
-+ * (register), FACGE, FABD, FCMGT (register) and FACGT.
+@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
-+ *
+                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
-+ */
+     pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
-+static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
+                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 -
 -    return s;
  }
 +
 +static void exynos4210_class_init(ObjectClass *klass, void *data)
 +{
-+    int opcode, fpopcode;
++    DeviceClass *dc = DEVICE_CLASS(klass);
 +    int is_q, u, a, rm, rn, rd;
 +    int datasize, elements;
 +    int pass;
 +    TCGv_ptr fpst;
 +
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
++    dc->realize = exynos4210_realize;
 +        unallocated_encoding(s);
 +        return;
 +    }
 +
 +    if (!fp_access_check(s)) {
 +        return;
 +    }
 +
 +    /* For these floating point ops, the U, a and opcode bits
 +     * together indicate the operation.
 +     */
 +    opcode = extract32(insn, 11, 3);
 +    u = extract32(insn, 29, 1);
 +    a = extract32(insn, 23, 1);
 +    is_q = extract32(insn, 30, 1);
 +    rm = extract32(insn, 16, 5);
 +    rn = extract32(insn, 5, 5);
 +    rd = extract32(insn, 0, 5);
 +
 +    fpopcode = opcode | (a << 3) |  (u << 4);
 +    datasize = is_q ? 128 : 64;
 +    elements = datasize / 16;
 +
 +    fpst = get_fpstatus_ptr(true);
 +
 +    for (pass = 0; pass < elements; pass++) {
 +        TCGv_i32 tcg_op1 = tcg_temp_new_i32();
 +        TCGv_i32 tcg_op2 = tcg_temp_new_i32();
 +        TCGv_i32 tcg_res = tcg_temp_new_i32();
 +
 +        read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
 +        read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
 +
 +        switch (fpopcode) {
 +        default:
 +            fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
 +                    __func__, insn, fpopcode, s->pc);
 +            g_assert_not_reached();
 +        }
 +
 +        write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
 +        tcg_temp_free_i32(tcg_res);
 +        tcg_temp_free_i32(tcg_op1);
 +        tcg_temp_free_i32(tcg_op2);
 +    }
 +
 +    tcg_temp_free_ptr(fpst);
 +
 +    clear_vec_high(s, is_q, rd);
 +}
 +
- static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
++static const TypeInfo exynos4210_info = {
-                                   int size, int rn, int rd)
++    .name = TYPE_EXYNOS4210_SOC,
- {
++    .parent = TYPE_SYS_BUS_DEVICE,
-@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
++    .instance_size = sizeof(Exynos4210State),
-     { 0xce000000, 0xff808000, disas_crypto_four_reg },
++    .class_init = exynos4210_class_init,
-     { 0xce800000, 0xffe00000, disas_crypto_xar },
++};
-     { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
++
-+    { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
++static void exynos4210_register_types(void)
-     { 0x00000000, 0x00000000, NULL }
++{
- };
++    type_register_static(&exynos4210_info);
 +}
 +
 +type_init(exynos4210_register_types)
 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4_boards.c
 +++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
  } Exynos4BoardType;
  typedef struct Exynos4BoardState {
 -    Exynos4210State *soc;
 +    Exynos4210State soc;
      MemoryRegion dram0_mem;
      MemoryRegion dram1_mem;
  } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
      exynos4_boards_init_ram(s, get_system_memory(),
                              exynos4_board_ram_size[board_type]);
 -    s->soc = exynos4210_init(get_system_memory());
 +    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
 +    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
 +    object_property_set_bool(OBJECT(&s->soc), true, "realized",
 +                             &error_fatal);
      return s;
  }
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
                                                        EXYNOS4_BOARD_SMDKC210);
      lan9215_init(SMDK_LAN9118_BASE_ADDR,
 -            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
 +            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
      arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
  }
 --
-.16.2
+.20.1

-[Qemu-devel] [PULL 17/42] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-The fprintf is only there for debugging as the skeleton is added to,
-it will be removed once the skeleton is complete.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |  4 ++++
- target/arm/helper-a64.c    |  4 ++++
- target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++
-files changed, 36 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
-     return float16_ ## name(a, b, fpst);    \
- }
-+ADVSIMD_HALFOP(add)
-+ADVSIMD_HALFOP(sub)
-+ADVSIMD_HALFOP(mul)
-+ADVSIMD_HALFOP(div)
- ADVSIMD_HALFOP(min)
- ADVSIMD_HALFOP(max)
- ADVSIMD_HALFOP(minnum)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
-         switch (fpopcode) {
-+        case 0x0: /* FMAXNM */
-+            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x2: /* FADD */
-+            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x6: /* FMAX */
-+            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x8: /* FMINNM */
-+            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0xa: /* FSUB */
-+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0xe: /* FMIN */
-+            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x13: /* FMUL */
-+            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x17: /* FDIV */
-+            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x1a: /* FABD */
-+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
-+            break;
-         default:
-             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
-                     __func__, insn, fpopcode, s->pc);
---
-.16.2

-[Qemu-devel] [PULL 18/42] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-These use the generic float16_compare functionality which in turn uses
-the common float_compare code from the softfloat re-factor.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |  5 +++++
- target/arm/helper-a64.c    | 49 ++++++++++++++++++++++++++++++++++++++++++++++
- target/arm/translate-a64.c | 15 ++++++++++++++
-files changed, 69 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
- DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
- DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
- DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(min)
- ADVSIMD_HALFOP(max)
- ADVSIMD_HALFOP(minnum)
- ADVSIMD_HALFOP(maxnum)
-+
-+/*
-+ * Floating point comparisons produce an integer result. Softfloat
-+ * routines return float_relation types which we convert to the 0/-1
-+ * Neon requires.
-+ */
-+
-+#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
-+
-+uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    int compare = float16_compare_quiet(a, b, fpst);
-+    return ADVSIMD_CMPRES(compare == float_relation_equal);
-+}
-+
-+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    int compare = float16_compare(a, b, fpst);
-+    return ADVSIMD_CMPRES(compare == float_relation_greater ||
-+                          compare == float_relation_equal);
-+}
-+
-+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    int compare = float16_compare(a, b, fpst);
-+    return ADVSIMD_CMPRES(compare == float_relation_greater);
-+}
-+
-+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    float16 f0 = float16_abs(a);
-+    float16 f1 = float16_abs(b);
-+    int compare = float16_compare(f0, f1, fpst);
-+    return ADVSIMD_CMPRES(compare == float_relation_greater ||
-+                          compare == float_relation_equal);
-+}
-+
-+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    float16 f0 = float16_abs(a);
-+    float16 f1 = float16_abs(b);
-+    int compare = float16_compare(f0, f1, fpst);
-+    return ADVSIMD_CMPRES(compare == float_relation_greater);
-+}
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0x2: /* FADD */
-             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x4: /* FCMEQ */
-+            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x6: /* FMAX */
-             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0x13: /* FMUL */
-             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x14: /* FCMGE */
-+            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x15: /* FACGE */
-+            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x17: /* FDIV */
-             gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-             tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
-             break;
-+        case 0x1c: /* FCMGT */
-+            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-+        case 0x1d: /* FACGT */
-+            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         default:
-             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
-                     __func__, insn, fpopcode, s->pc);
---
-.16.2

-[Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |  2 ++
- target/arm/helper-a64.c    | 24 ++++++++++++++++++++++++
- target/arm/translate-a64.c | 15 +++++++++++++++
-files changed, 41 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
- DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
- DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
- DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
-+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
- ADVSIMD_HALFOP(minnum)
- ADVSIMD_HALFOP(maxnum)
-+/* Data processing - scalar floating-point and advanced SIMD */
-+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+
-+    a = float16_squash_input_denormal(a, fpst);
-+    b = float16_squash_input_denormal(b, fpst);
-+
-+    if ((float16_is_zero(a) && float16_is_infinity(b)) ||
-+        (float16_is_infinity(a) && float16_is_zero(b))) {
-+        /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
-+        return make_float16((1U << 14) |
-+                            ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
-+    }
-+    return float16_mul(a, b, fpst);
-+}
-+
-+/* fused multiply-accumulate */
-+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    return float16_muladd(a, b, c, 0, fpst);
-+}
-+
- /*
-  * Floating point comparisons produce an integer result. Softfloat
-  * routines return float_relation types which we convert to the 0/-1
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0x0: /* FMAXNM */
-             gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x1: /* FMLA */
-+            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-+                                       fpst);
-+            break;
-         case 0x2: /* FADD */
-             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x3: /* FMULX */
-+            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x4: /* FCMEQ */
-             gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0x8: /* FMINNM */
-             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x9: /* FMLS */
-+             /* As usual for ARM, separate negation for fused multiply-add */
-+            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
-+            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-+                                       fpst);
-+            break;
-         case 0xa: /* FSUB */
-             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
---
-.16.2

-[Qemu-devel] [PULL 20/42] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-As some of the constants here will also be needed
-elsewhere (specifically for the upcoming SVE support) we move them out
-to softfloat.h.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/fpu/softfloat.h    | 18 +++++++++++++-----
- target/arm/helper-a64.h    |  2 ++
- target/arm/helper-a64.c    | 34 ++++++++++++++++++++++++++++++++++
- target/arm/translate-a64.c |  6 ++++++
-files changed, 55 insertions(+), 5 deletions(-)
-diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/fpu/softfloat.h
-+++ b/include/fpu/softfloat.h
-@@ -XXX,XX +XXX,XX @@ static inline float16 float16_set_sign(float16 a, int sign)
- }
- #define float16_zero make_float16(0)
--#define float16_one make_float16(0x3c00)
- #define float16_half make_float16(0x3800)
-+#define float16_one make_float16(0x3c00)
-+#define float16_one_point_five make_float16(0x3e00)
-+#define float16_two make_float16(0x4000)
-+#define float16_three make_float16(0x4200)
- #define float16_infinity make_float16(0x7c00)
- /*----------------------------------------------------------------------------
-@@ -XXX,XX +XXX,XX @@ static inline float32 float32_set_sign(float32 a, int sign)
- }
- #define float32_zero make_float32(0)
--#define float32_one make_float32(0x3f800000)
- #define float32_half make_float32(0x3f000000)
-+#define float32_one make_float32(0x3f800000)
-+#define float32_one_point_five make_float32(0x3fc00000)
-+#define float32_two make_float32(0x40000000)
-+#define float32_three make_float32(0x40400000)
- #define float32_infinity make_float32(0x7f800000)
--
- /*----------------------------------------------------------------------------
- | The pattern for a default generated single-precision NaN.
- *----------------------------------------------------------------------------*/
-@@ -XXX,XX +XXX,XX @@ static inline float64 float64_set_sign(float64 a, int sign)
- }
- #define float64_zero make_float64(0)
--#define float64_one make_float64(0x3ff0000000000000LL)
--#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
- #define float64_half make_float64(0x3fe0000000000000LL)
-+#define float64_one make_float64(0x3ff0000000000000LL)
-+#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
-+#define float64_two make_float64(0x4000000000000000ULL)
-+#define float64_three make_float64(0x4008000000000000ULL)
-+#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
- #define float64_infinity make_float64(0x7ff0000000000000LL)
- /*----------------------------------------------------------------------------
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
- DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
- DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
- DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
-+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
- DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
-+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
- DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
- DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
- DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
-  * versions, these do a fully fused multiply-add or
-  * multiply-add-and-halve.
-  */
-+#define float16_two make_float16(0x4000)
-+#define float16_three make_float16(0x4200)
-+#define float16_one_point_five make_float16(0x3e00)
-+
- #define float32_two make_float32(0x40000000)
- #define float32_three make_float32(0x40400000)
- #define float32_one_point_five make_float32(0x3fc00000)
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
- #define float64_three make_float64(0x4008000000000000ULL)
- #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
-+float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+
-+    a = float16_squash_input_denormal(a, fpst);
-+    b = float16_squash_input_denormal(b, fpst);
-+
-+    a = float16_chs(a);
-+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
-+        (float16_is_infinity(b) && float16_is_zero(a))) {
-+        return float16_two;
-+    }
-+    return float16_muladd(a, b, float16_two, 0, fpst);
-+}
-+
- float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
- {
-     float_status *fpst = fpstp;
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
-     return float64_muladd(a, b, float64_two, 0, fpst);
- }
-+float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+
-+    a = float16_squash_input_denormal(a, fpst);
-+    b = float16_squash_input_denormal(b, fpst);
-+
-+    a = float16_chs(a);
-+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
-+        (float16_is_infinity(b) && float16_is_zero(a))) {
-+        return float16_one_point_five;
-+    }
-+    return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
-+}
-+
- float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
- {
-     float_status *fpst = fpstp;
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0x6: /* FMAX */
-             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0x7: /* FRECPS */
-+            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x8: /* FMINNM */
-             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-         case 0xe: /* FMIN */
-             gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
-+        case 0xf: /* FRSQRTS */
-+            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+            break;
-         case 0x13: /* FMUL */
-             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-             break;
---
-.16.2

-[Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++----------------
-file changed, 133 insertions(+), 75 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-     int datasize, elements;
-     int pass;
-     TCGv_ptr fpst;
-+    bool pairwise = false;
-     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-         unallocated_encoding(s);
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
-     datasize = is_q ? 128 : 64;
-     elements = datasize / 16;
-+    switch (fpopcode) {
-+    case 0x10: /* FMAXNMP */
-+    case 0x12: /* FADDP */
-+    case 0x16: /* FMAXP */
-+    case 0x18: /* FMINNMP */
-+    case 0x1e: /* FMINP */
-+        pairwise = true;
-+        break;
-+    }
-+
-     fpst = get_fpstatus_ptr(true);
--    for (pass = 0; pass < elements; pass++) {
-+    if (pairwise) {
-+        int maxpass = is_q ? 8 : 4;
-         TCGv_i32 tcg_op1 = tcg_temp_new_i32();
-         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
--        TCGv_i32 tcg_res = tcg_temp_new_i32();
-+        TCGv_i32 tcg_res[8];
--        read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
--        read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
-+        for (pass = 0; pass < maxpass; pass++) {
-+            int passreg = pass < (maxpass / 2) ? rn : rm;
-+            int passelt = (pass << 1) & (maxpass - 1);
--        switch (fpopcode) {
--        case 0x0: /* FMAXNM */
--            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x1: /* FMLA */
--            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
--            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
--                                       fpst);
--            break;
--        case 0x2: /* FADD */
--            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x3: /* FMULX */
--            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x4: /* FCMEQ */
--            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x6: /* FMAX */
--            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x7: /* FRECPS */
--            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x8: /* FMINNM */
--            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x9: /* FMLS */
--             /* As usual for ARM, separate negation for fused multiply-add */
--            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
--            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
--            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
--                                       fpst);
--            break;
--        case 0xa: /* FSUB */
--            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0xe: /* FMIN */
--            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0xf: /* FRSQRTS */
--            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x13: /* FMUL */
--            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x14: /* FCMGE */
--            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x15: /* FACGE */
--            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x17: /* FDIV */
--            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x1a: /* FABD */
--            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
--            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
--            break;
--        case 0x1c: /* FCMGT */
--            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        case 0x1d: /* FACGT */
--            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
--            break;
--        default:
--            fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
--                    __func__, insn, fpopcode, s->pc);
--            g_assert_not_reached();
-+            read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
-+            read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
-+            tcg_res[pass] = tcg_temp_new_i32();
-+
-+            switch (fpopcode) {
-+            case 0x10: /* FMAXNMP */
-+                gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
-+                                           fpst);
-+                break;
-+            case 0x12: /* FADDP */
-+                gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x16: /* FMAXP */
-+                gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x18: /* FMINNMP */
-+                gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
-+                                           fpst);
-+                break;
-+            case 0x1e: /* FMINP */
-+                gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+        }
-+
-+        for (pass = 0; pass < maxpass; pass++) {
-+            write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
-+            tcg_temp_free_i32(tcg_res[pass]);
-         }
--        write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
--        tcg_temp_free_i32(tcg_res);
-         tcg_temp_free_i32(tcg_op1);
-         tcg_temp_free_i32(tcg_op2);
-+
-+    } else {
-+        for (pass = 0; pass < elements; pass++) {
-+            TCGv_i32 tcg_op1 = tcg_temp_new_i32();
-+            TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-+            TCGv_i32 tcg_res = tcg_temp_new_i32();
-+
-+            read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
-+            read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
-+
-+            switch (fpopcode) {
-+            case 0x0: /* FMAXNM */
-+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x1: /* FMLA */
-+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-+                                           fpst);
-+                break;
-+            case 0x2: /* FADD */
-+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x3: /* FMULX */
-+                gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x4: /* FCMEQ */
-+                gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x6: /* FMAX */
-+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x7: /* FRECPS */
-+                gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x8: /* FMINNM */
-+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x9: /* FMLS */
-+                /* As usual for ARM, separate negation for fused multiply-add */
-+                tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
-+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-+                                           fpst);
-+                break;
-+            case 0xa: /* FSUB */
-+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xe: /* FMIN */
-+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0xf: /* FRSQRTS */
-+                gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x13: /* FMUL */
-+                gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x14: /* FCMGE */
-+                gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x15: /* FACGE */
-+                gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x17: /* FDIV */
-+                gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x1a: /* FABD */
-+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+                tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
-+                break;
-+            case 0x1c: /* FCMGT */
-+                gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            case 0x1d: /* FACGT */
-+                gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-+                break;
-+            default:
-+                fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
-+                        __func__, insn, fpopcode, s->pc);
-+                g_assert_not_reached();
-+            }
-+
-+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+            tcg_temp_free_i32(tcg_res);
-+            tcg_temp_free_i32(tcg_op1);
-+            tcg_temp_free_i32(tcg_op2);
-+        }
-     }
-     tcg_temp_free_ptr(fpst);
---
-.16.2

-[Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-The helpers use the new re-factored muladd support in SoftFloat for
-the float16 work.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180227143852.11175-15-alex.bennee@linaro.org
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++---------
-file changed, 66 insertions(+), 16 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     int rd = extract32(insn, 0, 5);
-     bool is_long = false;
-     bool is_fp = false;
-+    bool is_fp16 = false;
-     int index;
-     TCGv_ptr fpst;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-         }
-         /* fall through */
-     case 0x9: /* FMUL, FMULX */
--        if (!extract32(size, 1, 1)) {
-+        if (size == 1) {
-             unallocated_encoding(s);
-             return;
-         }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     }
-     if (is_fp) {
--        /* low bit of size indicates single/double */
--        size = extract32(size, 0, 1) ? 3 : 2;
--        if (size == 2) {
-+        /* convert insn encoded size to TCGMemOp size */
-+        switch (size) {
-+        case 2: /* single precision */
-+            size = MO_32;
-             index = h << 1 | l;
--        } else {
-+            rm |= (m << 4);
-+            break;
-+        case 3: /* double precision */
-+            size = MO_64;
-             if (l || !is_q) {
-                 unallocated_encoding(s);
-                 return;
-             }
-             index = h;
-+            rm |= (m << 4);
-+            break;
-+        case 0: /* half precision */
-+            size = MO_16;
-+            index = h << 2 | l << 1 | m;
-+            is_fp16 = true;
-+            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+                break;
-+            }
-+            /* fallthru */
-+        default: /* unallocated */
-+            unallocated_encoding(s);
-+            return;
-         }
--        rm |= (m << 4);
-     } else {
-         switch (size) {
-         case 1:
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-     }
-     if (is_fp) {
--        fpst = get_fpstatus_ptr(false);
-+        fpst = get_fpstatus_ptr(is_fp16);
-     } else {
-         fpst = NULL;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-                 break;
-             }
-             case 0x5: /* FMLS */
--                /* As usual for ARM, separate negation for fused multiply-add */
--                gen_helper_vfp_negs(tcg_op, tcg_op);
--                /* fall through */
-             case 0x1: /* FMLA */
--                read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
--                gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
-+                read_vec_element_i32(s, tcg_res, rd, pass,
-+                                     is_scalar ? size : MO_32);
-+                switch (size) {
-+                case 1:
-+                    if (opcode == 0x5) {
-+                        /* As usual for ARM, separate negation for fused
-+                         * multiply-add */
-+                        tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
-+                    }
-+                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
-+                                               tcg_res, fpst);
-+                    break;
-+                case 2:
-+                    if (opcode == 0x5) {
-+                        /* As usual for ARM, separate negation for
-+                         * fused multiply-add */
-+                        tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
-+                    }
-+                    gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
-+                                           tcg_res, fpst);
-+                    break;
-+                default:
-+                    g_assert_not_reached();
-+                }
-                 break;
-             case 0x9: /* FMUL, FMULX */
--                if (u) {
--                    gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
--                } else {
--                    gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
-+                switch (size) {
-+                case 1:
-+                    if (u) {
-+                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
-+                                                 fpst);
-+                    } else {
-+                        g_assert_not_reached();
-+                    }
-+                    break;
-+                case 2:
-+                    if (u) {
-+                        gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
-+                    } else {
-+                        gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
-+                    }
-+                    break;
-+                default:
-+                    g_assert_not_reached();
-                 }
-                 break;
-             case 0xc: /* SQDMULH */
---
-.16.2

-[Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-A bunch of the vectorised bitwise operations just operate on larger
-chunks at a time. We can do the same for the new half-precision
-operations by introducing some TWOHALFOP helpers which work on each
-half of a pair of half-precision operations at once.
-Hopefully all this hoop jumping will get simpler once we have
-generically vectorised helpers here.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    | 10 ++++++++++
- target/arm/helper-a64.c    | 46 +++++++++++++++++++++++++++++++++++++++++++++-
- target/arm/translate-a64.c | 26 +++++++++++++++++++++-----
-files changed, 76 insertions(+), 6 deletions(-)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
- DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
- DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
- DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
-+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
-+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
-+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
- ADVSIMD_HALFOP(minnum)
- ADVSIMD_HALFOP(maxnum)
-+#define ADVSIMD_TWOHALFOP(name)                                         \
-+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
-+{ \
-+    float16  a1, a2, b1, b2;                        \
-+    uint32_t r1, r2;                                \
-+    float_status *fpst = fpstp;                     \
-+    a1 = extract32(two_a, 0, 16);                   \
-+    a2 = extract32(two_a, 16, 16);                  \
-+    b1 = extract32(two_b, 0, 16);                   \
-+    b2 = extract32(two_b, 16, 16);                  \
-+    r1 = float16_ ## name(a1, b1, fpst);            \
-+    r2 = float16_ ## name(a2, b2, fpst);            \
-+    return deposit32(r1, 16, 16, r2);               \
-+}
-+
-+ADVSIMD_TWOHALFOP(add)
-+ADVSIMD_TWOHALFOP(sub)
-+ADVSIMD_TWOHALFOP(mul)
-+ADVSIMD_TWOHALFOP(div)
-+ADVSIMD_TWOHALFOP(min)
-+ADVSIMD_TWOHALFOP(max)
-+ADVSIMD_TWOHALFOP(minnum)
-+ADVSIMD_TWOHALFOP(maxnum)
-+
- /* Data processing - scalar floating-point and advanced SIMD */
--float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
-+static float16 float16_mulx(float16 a, float16 b, void *fpstp)
- {
-     float_status *fpst = fpstp;
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
-     return float16_mul(a, b, fpst);
- }
-+ADVSIMD_HALFOP(mulx)
-+ADVSIMD_TWOHALFOP(mulx)
-+
- /* fused multiply-accumulate */
- float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
- {
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
-     return float16_muladd(a, b, c, 0, fpst);
- }
-+uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
-+                                  uint32_t two_c, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    float16  a1, a2, b1, b2, c1, c2;
-+    uint32_t r1, r2;
-+    a1 = extract32(two_a, 0, 16);
-+    a2 = extract32(two_a, 16, 16);
-+    b1 = extract32(two_b, 0, 16);
-+    b2 = extract32(two_b, 16, 16);
-+    c1 = extract32(two_c, 0, 16);
-+    c2 = extract32(two_c, 16, 16);
-+    r1 = float16_muladd(a1, b1, c1, 0, fpst);
-+    r2 = float16_muladd(a2, b2, c2, 0, fpst);
-+    return deposit32(r1, 16, 16, r2);
-+}
-+
- /*
-  * Floating point comparisons produce an integer result. Softfloat
-  * routines return float_relation types which we convert to the 0/-1
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-                          * multiply-add */
-                         tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
-                     }
--                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
--                                               tcg_res, fpst);
-+                    if (is_scalar) {
-+                        gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
-+                                                   tcg_res, fpst);
-+                    } else {
-+                        gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
-+                                                    tcg_res, fpst);
-+                    }
-                     break;
-                 case 2:
-                     if (opcode == 0x5) {
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-                 switch (size) {
-                 case 1:
-                     if (u) {
--                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
--                                                 fpst);
-+                        if (is_scalar) {
-+                            gen_helper_advsimd_mulxh(tcg_res, tcg_op,
-+                                                     tcg_idx, fpst);
-+                        } else {
-+                            gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
-+                                                      tcg_idx, fpst);
-+                        }
-                     } else {
--                        g_assert_not_reached();
-+                        if (is_scalar) {
-+                            gen_helper_advsimd_mulh(tcg_res, tcg_op,
-+                                                    tcg_idx, fpst);
-+                        } else {
-+                            gen_helper_advsimd_mul2h(tcg_res, tcg_op,
-+                                                     tcg_idx, fpst);
-+                        }
-                     }
-                     break;
-                 case 2:
---
-.16.2

-[Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This actually covers two different sections of the encoding table:
-   Advanced SIMD scalar two-register miscellaneous FP16
-   Advanced SIMD two-register miscellaneous (FP16)
-The difference between the two is covered by a combination of Q (bit
-) and S (bit 28). Notably the FRINTx instructions are only
-available in the vector form.
-This is just the decode skeleton which will be filled out by later
-patches.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++
-file changed, 40 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-     }
- }
-+/* AdvSIMD [scalar] two register miscellaneous (FP16)
-+ *
-+ *   31  30  29 28  27     24  23 22 21       17 16    12 11 10 9    5 4    0
-+ * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
-+ * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
-+ * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
-+ *   mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
-+ *   val:  0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
-+ *
-+ * This actually covers two groups where scalar access is governed by
-+ * bit 28. A bunch of the instructions (float to integral) only exist
-+ * in the vector form and are un-allocated for the scalar decode. Also
-+ * in the scalar decode Q is always 1.
-+ */
-+static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-+{
-+    int fpop, opcode, a;
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+        unallocated_encoding(s);
-+        return;
-+    }
-+
-+    if (!fp_access_check(s)) {
-+        return;
-+    }
-+
-+    opcode = extract32(insn, 12, 4);
-+    a = extract32(insn, 23, 1);
-+    fpop = deposit32(opcode, 5, 1, a);
-+
-+    switch (fpop) {
-+    default:
-+        fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
-+        g_assert_not_reached();
-+    }
-+
-+}
-+
- /* AdvSIMD scalar x indexed element
-  *  31 30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
-  * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
-@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
-     { 0xce800000, 0xffe00000, disas_crypto_xar },
-     { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
-     { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
-+    { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
-     { 0x00000000, 0x00000000, NULL }
- };
---
-.16.2

-[Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This adds the full range of half-precision floating point to integral
-instructions.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |   2 +
- target/arm/helper-a64.c    |  22 ++++++++
- target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++++--
-files changed, 142 insertions(+), 5 deletions(-)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
- DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
- DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
- DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
-+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
-+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
-     int compare = float16_compare(f0, f1, fpst);
-     return ADVSIMD_CMPRES(compare == float_relation_greater);
- }
-+
-+/* round to integral */
-+float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
-+{
-+    return float16_round_to_int(x, fp_status);
-+}
-+
-+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
-+{
-+    int old_flags = get_float_exception_flags(fp_status), new_flags;
-+    float16 ret;
-+
-+    ret = float16_round_to_int(x, fp_status);
-+
-+    /* Suppress any inexact exceptions the conversion produced */
-+    if (!(old_flags & float_flag_inexact)) {
-+        new_flags = get_float_exception_flags(fp_status);
-+        set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
-+    }
-+
-+    return ret;
-+}
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-  */
- static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
- {
--    int fpop, opcode, a;
-+    int fpop, opcode, a, u;
-+    int rn, rd;
-+    bool is_q;
-+    bool is_scalar;
-+    bool only_in_vector = false;
-+
-+    int pass;
-+    TCGv_i32 tcg_rmode = NULL;
-+    TCGv_ptr tcg_fpstatus = NULL;
-+    bool need_rmode = false;
-+    int rmode;
-     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-         unallocated_encoding(s);
-         return;
-     }
--    if (!fp_access_check(s)) {
--        return;
--    }
-+    rd = extract32(insn, 0, 5);
-+    rn = extract32(insn, 5, 5);
--    opcode = extract32(insn, 12, 4);
-     a = extract32(insn, 23, 1);
-+    u = extract32(insn, 29, 1);
-+    is_scalar = extract32(insn, 28, 1);
-+    is_q = extract32(insn, 30, 1);
-+
-+    opcode = extract32(insn, 12, 5);
-     fpop = deposit32(opcode, 5, 1, a);
-+    fpop = deposit32(fpop, 6, 1, u);
-     switch (fpop) {
-+    case 0x18: /* FRINTN */
-+        need_rmode = true;
-+        only_in_vector = true;
-+        rmode = FPROUNDING_TIEEVEN;
-+        break;
-+    case 0x19: /* FRINTM */
-+        need_rmode = true;
-+        only_in_vector = true;
-+        rmode = FPROUNDING_NEGINF;
-+        break;
-+    case 0x38: /* FRINTP */
-+        need_rmode = true;
-+        only_in_vector = true;
-+        rmode = FPROUNDING_POSINF;
-+        break;
-+    case 0x39: /* FRINTZ */
-+        need_rmode = true;
-+        only_in_vector = true;
-+        rmode = FPROUNDING_ZERO;
-+        break;
-+    case 0x58: /* FRINTA */
-+        need_rmode = true;
-+        only_in_vector = true;
-+        rmode = FPROUNDING_TIEAWAY;
-+        break;
-+    case 0x59: /* FRINTX */
-+    case 0x79: /* FRINTI */
-+        only_in_vector = true;
-+        /* current rounding mode */
-+        break;
-     default:
-         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
-         g_assert_not_reached();
-     }
-+
-+    /* Check additional constraints for the scalar encoding */
-+    if (is_scalar) {
-+        if (!is_q) {
-+            unallocated_encoding(s);
-+            return;
-+        }
-+        /* FRINTxx is only in the vector form */
-+        if (only_in_vector) {
-+            unallocated_encoding(s);
-+            return;
-+        }
-+    }
-+
-+    if (!fp_access_check(s)) {
-+        return;
-+    }
-+
-+    if (need_rmode) {
-+        tcg_fpstatus = get_fpstatus_ptr(true);
-+    }
-+
-+    if (need_rmode) {
-+        tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-+    }
-+
-+    if (is_scalar) {
-+        /* no operations yet */
-+    } else {
-+        for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
-+            TCGv_i32 tcg_op = tcg_temp_new_i32();
-+            TCGv_i32 tcg_res = tcg_temp_new_i32();
-+
-+            read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
-+
-+            switch (fpop) {
-+            case 0x18: /* FRINTN */
-+            case 0x19: /* FRINTM */
-+            case 0x38: /* FRINTP */
-+            case 0x39: /* FRINTZ */
-+            case 0x58: /* FRINTA */
-+            case 0x79: /* FRINTI */
-+                gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-+            case 0x59: /* FRINTX */
-+                gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+
-+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-+
-+            tcg_temp_free_i32(tcg_res);
-+            tcg_temp_free_i32(tcg_op);
-+        }
-+
-+        clear_vec_high(s, is_q, rd);
-+    }
-+
-+    if (tcg_rmode) {
-+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-+        tcg_temp_free_i32(tcg_rmode);
-+    }
-+
-+    if (tcg_fpstatus) {
-+        tcg_temp_free_ptr(tcg_fpstatus);
-+    }
- }
- /* AdvSIMD scalar x indexed element
---
-.16.2

-[Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-This covers all the floating point convert operations.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |  2 ++
- target/arm/helper-a64.c    | 32 +++++++++++++++++
- target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++-
-files changed, 118 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
- DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
- DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
- DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
-+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
-+DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
-     return ret;
- }
-+
-+/*
-+ * Half-precision floating point conversion functions
-+ *
-+ * There are a multitude of conversion functions with various
-+ * different rounding modes. This is dealt with by the calling code
-+ * setting the mode appropriately before calling the helper.
-+ */
-+
-+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+
-+    /* Invalid if we are passed a NaN */
-+    if (float16_is_any_nan(a)) {
-+        float_raise(float_flag_invalid, fpst);
-+        return 0;
-+    }
-+    return float16_to_int16(a, fpst);
-+}
-+
-+uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+
-+    /* Invalid if we are passed a NaN */
-+    if (float16_is_any_nan(a)) {
-+        float_raise(float_flag_invalid, fpst);
-+        return 0;
-+    }
-+    return float16_to_uint16(a, fpst);
-+}
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         only_in_vector = true;
-         /* current rounding mode */
-         break;
-+    case 0x1a: /* FCVTNS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEEVEN;
-+        break;
-+    case 0x1b: /* FCVTMS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_NEGINF;
-+        break;
-+    case 0x1c: /* FCVTAS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEAWAY;
-+        break;
-+    case 0x3a: /* FCVTPS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_POSINF;
-+        break;
-+    case 0x3b: /* FCVTZS */
-+        need_rmode = true;
-+        rmode = FPROUNDING_ZERO;
-+        break;
-+    case 0x5a: /* FCVTNU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEEVEN;
-+        break;
-+    case 0x5b: /* FCVTMU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_NEGINF;
-+        break;
-+    case 0x5c: /* FCVTAU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_TIEAWAY;
-+        break;
-+    case 0x7a: /* FCVTPU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_POSINF;
-+        break;
-+    case 0x7b: /* FCVTZU */
-+        need_rmode = true;
-+        rmode = FPROUNDING_ZERO;
-+        break;
-     default:
-         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
-         g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     }
-     if (is_scalar) {
--        /* no operations yet */
-+        TCGv_i32 tcg_op = tcg_temp_new_i32();
-+        TCGv_i32 tcg_res = tcg_temp_new_i32();
-+
-+        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-+
-+        switch (fpop) {
-+        case 0x1a: /* FCVTNS */
-+        case 0x1b: /* FCVTMS */
-+        case 0x1c: /* FCVTAS */
-+        case 0x3a: /* FCVTPS */
-+        case 0x3b: /* FCVTZS */
-+            gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-+        case 0x5a: /* FCVTNU */
-+        case 0x5b: /* FCVTMU */
-+        case 0x5c: /* FCVTAU */
-+        case 0x7a: /* FCVTPU */
-+        case 0x7b: /* FCVTZU */
-+            gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-+        default:
-+            g_assert_not_reached();
-+        }
-+
-+        /* limit any sign extension going on */
-+        tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
-+        write_fp_sreg(s, rd, tcg_res);
-+
-+        tcg_temp_free_i32(tcg_res);
-+        tcg_temp_free_i32(tcg_op);
-     } else {
-         for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
-             TCGv_i32 tcg_op = tcg_temp_new_i32();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
-             switch (fpop) {
-+            case 0x1a: /* FCVTNS */
-+            case 0x1b: /* FCVTMS */
-+            case 0x1c: /* FCVTAS */
-+            case 0x3a: /* FCVTPS */
-+            case 0x3b: /* FCVTZS */
-+                gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-+            case 0x5a: /* FCVTNU */
-+            case 0x5b: /* FCVTMU */
-+            case 0x5c: /* FCVTAU */
-+            case 0x7a: /* FCVTPU */
-+            case 0x7b: /* FCVTZU */
-+                gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-             case 0x18: /* FRINTN */
-             case 0x19: /* FRINTM */
-             case 0x38: /* FRINTP */
---
-.16.2

-[Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-I've re-factored the handle_simd_intfp_conv helper to properly handle
-half-precision as well as call plain conversion helpers when we are
-not doing fixed point conversion.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.h        |  10 ++++
- target/arm/helper.c        |   4 ++
- target/arm/translate-a64.c | 122 ++++++++++++++++++++++++++++++++++-----------
-files changed, 108 insertions(+), 28 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
- DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
- DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
-+DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
- DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
- DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
-+DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
- DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
- DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
-+DEF_HELPER_2(vfp_touih, i32, f16, ptr)
- DEF_HELPER_2(vfp_touis, i32, f32, ptr)
- DEF_HELPER_2(vfp_touid, i32, f64, ptr)
-+DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
- DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
- DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
-+DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
- DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
- DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
-+DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
- DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
- DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
- DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
- DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
- DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
-+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
-+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
- DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
- DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
- DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
- DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
-+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
-+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
- DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
- DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
- CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
- CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
-+FLOAT_CONVS(si, h, 16, )
- FLOAT_CONVS(si, s, 32, )
- FLOAT_CONVS(si, d, 64, )
-+FLOAT_CONVS(ui, h, 16, u)
- FLOAT_CONVS(ui, s, 32, u)
- FLOAT_CONVS(ui, d, 64, u)
-@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
- VFP_CONV_FIX(uh, s, 32, 32, uint16)
- VFP_CONV_FIX(ul, s, 32, 32, uint32)
- VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
-+VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
-+VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
- #undef VFP_CONV_FIX
- #undef VFP_CONV_FIX_FLOAT
- #undef VFP_CONV_FLOAT_FIX_ROUND
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
-                                    int elements, int is_signed,
-                                    int fracbits, int size)
- {
--    bool is_double = size == 3 ? true : false;
--    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
--    TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
--    TCGv_i64 tcg_int = tcg_temp_new_i64();
-+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
-+    TCGv_i32 tcg_shift = NULL;
-+
-     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
-     int pass;
--    for (pass = 0; pass < elements; pass++) {
--        read_vec_element(s, tcg_int, rn, pass, mop);
-+    if (fracbits || size == MO_64) {
-+        tcg_shift = tcg_const_i32(fracbits);
-+    }
-+
-+    if (size == MO_64) {
-+        TCGv_i64 tcg_int64 = tcg_temp_new_i64();
-+        TCGv_i64 tcg_double = tcg_temp_new_i64();
-+
-+        for (pass = 0; pass < elements; pass++) {
-+            read_vec_element(s, tcg_int64, rn, pass, mop);
--        if (is_double) {
--            TCGv_i64 tcg_double = tcg_temp_new_i64();
-             if (is_signed) {
--                gen_helper_vfp_sqtod(tcg_double, tcg_int,
-+                gen_helper_vfp_sqtod(tcg_double, tcg_int64,
-                                      tcg_shift, tcg_fpst);
-             } else {
--                gen_helper_vfp_uqtod(tcg_double, tcg_int,
-+                gen_helper_vfp_uqtod(tcg_double, tcg_int64,
-                                      tcg_shift, tcg_fpst);
-             }
-             if (elements == 1) {
-@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
-             } else {
-                 write_vec_element(s, tcg_double, rd, pass, MO_64);
-             }
--            tcg_temp_free_i64(tcg_double);
--        } else {
--            TCGv_i32 tcg_single = tcg_temp_new_i32();
--            if (is_signed) {
--                gen_helper_vfp_sqtos(tcg_single, tcg_int,
--                                     tcg_shift, tcg_fpst);
--            } else {
--                gen_helper_vfp_uqtos(tcg_single, tcg_int,
--                                     tcg_shift, tcg_fpst);
--            }
--            if (elements == 1) {
--                write_fp_sreg(s, rd, tcg_single);
--            } else {
--                write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
--            }
--            tcg_temp_free_i32(tcg_single);
-         }
-+
-+        tcg_temp_free_i64(tcg_int64);
-+        tcg_temp_free_i64(tcg_double);
-+
-+    } else {
-+        TCGv_i32 tcg_int32 = tcg_temp_new_i32();
-+        TCGv_i32 tcg_float = tcg_temp_new_i32();
-+
-+        for (pass = 0; pass < elements; pass++) {
-+            read_vec_element_i32(s, tcg_int32, rn, pass, mop);
-+
-+            switch (size) {
-+            case MO_32:
-+                if (fracbits) {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sltos(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_ultos(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    }
-+                } else {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
-+                    }
-+                }
-+                break;
-+            case MO_16:
-+                if (fracbits) {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sltoh(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_ultoh(tcg_float, tcg_int32,
-+                                             tcg_shift, tcg_fpst);
-+                    }
-+                } else {
-+                    if (is_signed) {
-+                        gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
-+                    } else {
-+                        gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
-+                    }
-+                }
-+                break;
-+            default:
-+                g_assert_not_reached();
-+            }
-+
-+            if (elements == 1) {
-+                write_fp_sreg(s, rd, tcg_float);
-+            } else {
-+                write_vec_element_i32(s, tcg_float, rd, pass, size);
-+            }
-+        }
-+
-+        tcg_temp_free_i32(tcg_int32);
-+        tcg_temp_free_i32(tcg_float);
-     }
--    tcg_temp_free_i64(tcg_int);
-     tcg_temp_free_ptr(tcg_fpst);
--    tcg_temp_free_i32(tcg_shift);
-+    if (tcg_shift) {
-+        tcg_temp_free_i32(tcg_shift);
-+    }
-     clear_vec_high(s, elements << size == 16, rd);
- }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     rn = extract32(insn, 5, 5);
-     switch (fpop) {
-+    case 0x1d: /* SCVTF */
-+    case 0x5d: /* UCVTF */
-+    {
-+        int elements;
-+
-+        if (is_scalar) {
-+            elements = 1;
-+        } else {
-+            elements = (is_q ? 8 : 4);
-+        }
-+
-+        if (!fp_access_check(s)) {
-+            return;
-+        }
-+        handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
-+        return;
-+    }
-     break;
-     case 0x2c: /* FCMGT (zero) */
-     case 0x2d: /* FCMEQ (zero) */
---
-.16.2

-[Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Neither of these operations alter the floating point status registers
-so we can do a pure bitwise operation, either squashing any sign
-bit (ABS) or inverting it (NEG).
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 16 +++++++++++++++-
-file changed, 15 insertions(+), 1 deletion(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     TCGv_i32 tcg_rmode = NULL;
-     TCGv_ptr tcg_fpstatus = NULL;
-     bool need_rmode = false;
-+    bool need_fpst = true;
-     int rmode;
-     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         need_rmode = true;
-         rmode = FPROUNDING_ZERO;
-         break;
-+    case 0x2f: /* FABS */
-+    case 0x6f: /* FNEG */
-+        need_fpst = false;
-+        break;
-     default:
-         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
-         g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         return;
-     }
--    if (need_rmode) {
-+    if (need_rmode || need_fpst) {
-         tcg_fpstatus = get_fpstatus_ptr(true);
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         case 0x7b: /* FCVTZU */
-             gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
-             break;
-+        case 0x6f: /* FNEG */
-+            tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-+            break;
-         default:
-             g_assert_not_reached();
-         }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             case 0x59: /* FRINTX */
-                 gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
-                 break;
-+            case 0x2f: /* FABS */
-+                tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
-+                break;
-+            case 0x6f: /* FNEG */
-+                tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-+                break;
-             default:
-                 g_assert_not_reached();
-             }
---
-.16.2

-[Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-It looks like the ARM ARM has simplified the pseudo code for the
-calculation which is done on a fixed point 9 bit integer maths. So
-while adding f16 we can also clean this up to be a little less heavy
-on the floating point and just return the fractional part and leave
-the calle's to do the final packing of the result.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.h |   1 +
- target/arm/helper.c | 226 +++++++++++++++++++++++++++++-----------------------
-files changed, 129 insertions(+), 98 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
- DEF_HELPER_3(recps_f32, f32, f32, f32, env)
- DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
-+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
- DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
- DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
- DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
-  * int->float conversions at run-time.  */
- #define float64_256 make_float64(0x4070000000000000LL)
- #define float64_512 make_float64(0x4080000000000000LL)
-+#define float16_maxnorm make_float16(0x7bff)
- #define float32_maxnorm make_float32(0x7f7fffff)
- #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
- /* Reciprocal functions
-  *
-  * The algorithm that must be used to calculate the estimate
-- * is specified by the ARM ARM, see FPRecipEstimate()
-+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
-  */
--static float64 recip_estimate(float64 a, float_status *real_fp_status)
-+/* See RecipEstimate()
-+ *
-+ * input is a 9 bit fixed point number
-+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
-+ * result range 256 .. 511 for a number from 1.0 to 511/256.
-+ */
-+
-+static int recip_estimate(int input)
- {
--    /* These calculations mustn't set any fp exception flags,
--     * so we use a local copy of the fp_status.
--     */
--    float_status dummy_status = *real_fp_status;
--    float_status *s = &dummy_status;
--    /* q = (int)(a * 512.0) */
--    float64 q = float64_mul(float64_512, a, s);
--    int64_t q_int = float64_to_int64_round_to_zero(q, s);
--
--    /* r = 1.0 / (((double)q + 0.5) / 512.0) */
--    q = int64_to_float64(q_int, s);
--    q = float64_add(q, float64_half, s);
--    q = float64_div(q, float64_512, s);
--    q = float64_div(float64_one, q, s);
--
--    /* s = (int)(256.0 * r + 0.5) */
--    q = float64_mul(q, float64_256, s);
--    q = float64_add(q, float64_half, s);
--    q_int = float64_to_int64_round_to_zero(q, s);
--
--    /* return (double)s / 256.0 */
--    return float64_div(int64_to_float64(q_int, s), float64_256, s);
-+    int a, b, r;
-+    assert(256 <= input && input < 512);
-+    a = (input * 2) + 1;
-+    b = (1 << 19) / a;
-+    r = (b + 1) >> 1;
-+    assert(256 <= r && r < 512);
-+    return r;
- }
--/* Common wrapper to call recip_estimate */
--static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
--{
--    uint64_t val64 = float64_val(num);
--    uint64_t frac = extract64(val64, 0, 52);
--    int64_t exp = extract64(val64, 52, 11);
--    uint64_t sbit;
--    float64 scaled, estimate;
-+/*
-+ * Common wrapper to call recip_estimate
-+ *
-+ * The parameters are exponent and 64 bit fraction (without implicit
-+ * bit) where the binary point is nominally at bit 52. Returns a
-+ * float64 which can then be rounded to the appropriate size by the
-+ * callee.
-+ */
--    /* Generate the scaled number for the estimate function */
--    if (exp == 0) {
-+static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
-+{
-+    uint32_t scaled, estimate;
-+    uint64_t result_frac;
-+    int result_exp;
-+
-+    /* Handle sub-normals */
-+    if (*exp == 0) {
-         if (extract64(frac, 51, 1) == 0) {
--            exp = -1;
--            frac = extract64(frac, 0, 50) << 2;
-+            *exp = -1;
-+            frac <<= 2;
-         } else {
--            frac = extract64(frac, 0, 51) << 1;
-+            frac <<= 1;
-         }
-     }
--    /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
--    scaled = make_float64((0x3feULL << 52)
--                          | extract64(frac, 44, 8) << 44);
-+    /* scaled = UInt('1':fraction<51:44>) */
-+    scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
-+    estimate = recip_estimate(scaled);
--    estimate = recip_estimate(scaled, fpst);
--
--    /* Build new result */
--    val64 = float64_val(estimate);
--    sbit = 0x8000000000000000ULL & val64;
--    exp = off - exp;
--    frac = extract64(val64, 0, 52);
--
--    if (exp == 0) {
--        frac = 1ULL << 51 | extract64(frac, 1, 51);
--    } else if (exp == -1) {
--        frac = 1ULL << 50 | extract64(frac, 2, 50);
--        exp = 0;
-+    result_exp = exp_off - *exp;
-+    result_frac = deposit64(0, 44, 8, estimate);
-+    if (result_exp == 0) {
-+        result_frac = deposit64(result_frac >> 1, 51, 1, 1);
-+    } else if (result_exp == -1) {
-+        result_frac = deposit64(result_frac >> 2, 50, 2, 1);
-+        result_exp = 0;
-     }
--    return make_float64(sbit | (exp << 52) | frac);
-+    *exp = result_exp;
-+
-+    return result_frac;
- }
- static bool round_to_inf(float_status *fpst, bool sign_bit)
-@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
-     g_assert_not_reached();
- }
-+float16 HELPER(recpe_f16)(float16 input, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    float16 f16 = float16_squash_input_denormal(input, fpst);
-+    uint32_t f16_val = float16_val(f16);
-+    uint32_t f16_sign = float16_is_neg(f16);
-+    int f16_exp = extract32(f16_val, 10, 5);
-+    uint32_t f16_frac = extract32(f16_val, 0, 10);
-+    uint64_t f64_frac;
-+
-+    if (float16_is_any_nan(f16)) {
-+        float16 nan = f16;
-+        if (float16_is_signaling_nan(f16, fpst)) {
-+            float_raise(float_flag_invalid, fpst);
-+            nan = float16_maybe_silence_nan(f16, fpst);
-+        }
-+        if (fpst->default_nan_mode) {
-+            nan =  float16_default_nan(fpst);
-+        }
-+        return nan;
-+    } else if (float16_is_infinity(f16)) {
-+        return float16_set_sign(float16_zero, float16_is_neg(f16));
-+    } else if (float16_is_zero(f16)) {
-+        float_raise(float_flag_divbyzero, fpst);
-+        return float16_set_sign(float16_infinity, float16_is_neg(f16));
-+    } else if (float16_abs(f16) < (1 << 8)) {
-+        /* Abs(value) < 2.0^-16 */
-+        float_raise(float_flag_overflow | float_flag_inexact, fpst);
-+        if (round_to_inf(fpst, f16_sign)) {
-+            return float16_set_sign(float16_infinity, f16_sign);
-+        } else {
-+            return float16_set_sign(float16_maxnorm, f16_sign);
-+        }
-+    } else if (f16_exp >= 29 && fpst->flush_to_zero) {
-+        float_raise(float_flag_underflow, fpst);
-+        return float16_set_sign(float16_zero, float16_is_neg(f16));
-+    }
-+
-+    f64_frac = call_recip_estimate(&f16_exp, 29,
-+                                   ((uint64_t) f16_frac) << (52 - 10));
-+
-+    /* result = sign : result_exp<4:0> : fraction<51:42> */
-+    f16_val = deposit32(0, 15, 1, f16_sign);
-+    f16_val = deposit32(f16_val, 10, 5, f16_exp);
-+    f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
-+    return make_float16(f16_val);
-+}
-+
- float32 HELPER(recpe_f32)(float32 input, void *fpstp)
- {
-     float_status *fpst = fpstp;
-     float32 f32 = float32_squash_input_denormal(input, fpst);
-     uint32_t f32_val = float32_val(f32);
--    uint32_t f32_sbit = 0x80000000ULL & f32_val;
--    int32_t f32_exp = extract32(f32_val, 23, 8);
-+    bool f32_sign = float32_is_neg(f32);
-+    int f32_exp = extract32(f32_val, 23, 8);
-     uint32_t f32_frac = extract32(f32_val, 0, 23);
--    float64 f64, r64;
--    uint64_t r64_val;
--    int64_t r64_exp;
--    uint64_t r64_frac;
-+    uint64_t f64_frac;
-     if (float32_is_any_nan(f32)) {
-         float32 nan = f32;
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
-     } else if (float32_is_zero(f32)) {
-         float_raise(float_flag_divbyzero, fpst);
-         return float32_set_sign(float32_infinity, float32_is_neg(f32));
--    } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
-+    } else if (float32_abs(f32) < (1ULL << 21)) {
-         /* Abs(value) < 2.0^-128 */
-         float_raise(float_flag_overflow | float_flag_inexact, fpst);
--        if (round_to_inf(fpst, f32_sbit)) {
--            return float32_set_sign(float32_infinity, float32_is_neg(f32));
-+        if (round_to_inf(fpst, f32_sign)) {
-+            return float32_set_sign(float32_infinity, f32_sign);
-         } else {
--            return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
-+            return float32_set_sign(float32_maxnorm, f32_sign);
-         }
-     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
-         float_raise(float_flag_underflow, fpst);
-         return float32_set_sign(float32_zero, float32_is_neg(f32));
-     }
-+    f64_frac = call_recip_estimate(&f32_exp, 253,
-+                                   ((uint64_t) f32_frac) << (52 - 23));
--    f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
--    r64 = call_recip_estimate(f64, 253, fpst);
--    r64_val = float64_val(r64);
--    r64_exp = extract64(r64_val, 52, 11);
--    r64_frac = extract64(r64_val, 0, 52);
--
--    /* result = sign : result_exp<7:0> : fraction<51:29>; */
--    return make_float32(f32_sbit |
--                        (r64_exp & 0xff) << 23 |
--                        extract64(r64_frac, 29, 24));
-+    /* result = sign : result_exp<7:0> : fraction<51:29> */
-+    f32_val = deposit32(0, 31, 1, f32_sign);
-+    f32_val = deposit32(f32_val, 23, 8, f32_exp);
-+    f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
-+    return make_float32(f32_val);
- }
- float64 HELPER(recpe_f64)(float64 input, void *fpstp)
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
-     float_status *fpst = fpstp;
-     float64 f64 = float64_squash_input_denormal(input, fpst);
-     uint64_t f64_val = float64_val(f64);
--    uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
--    int64_t f64_exp = extract64(f64_val, 52, 11);
--    float64 r64;
--    uint64_t r64_val;
--    int64_t r64_exp;
--    uint64_t r64_frac;
-+    bool f64_sign = float64_is_neg(f64);
-+    int f64_exp = extract64(f64_val, 52, 11);
-+    uint64_t f64_frac = extract64(f64_val, 0, 52);
-     /* Deal with any special cases */
-     if (float64_is_any_nan(f64)) {
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
-     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
-         /* Abs(value) < 2.0^-1024 */
-         float_raise(float_flag_overflow | float_flag_inexact, fpst);
--        if (round_to_inf(fpst, f64_sbit)) {
--            return float64_set_sign(float64_infinity, float64_is_neg(f64));
-+        if (round_to_inf(fpst, f64_sign)) {
-+            return float64_set_sign(float64_infinity, f64_sign);
-         } else {
--            return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
-+            return float64_set_sign(float64_maxnorm, f64_sign);
-         }
-     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
-         float_raise(float_flag_underflow, fpst);
-         return float64_set_sign(float64_zero, float64_is_neg(f64));
-     }
--    r64 = call_recip_estimate(f64, 2045, fpst);
--    r64_val = float64_val(r64);
--    r64_exp = extract64(r64_val, 52, 11);
--    r64_frac = extract64(r64_val, 0, 52);
-+    f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
--    /* result = sign : result_exp<10:0> : fraction<51:0> */
--    return make_float64(f64_sbit |
--                        ((r64_exp & 0x7ff) << 52) |
--                        r64_frac);
-+    /* result = sign : result_exp<10:0> : fraction<51:0>; */
-+    f64_val = deposit64(0, 63, 1, f64_sign);
-+    f64_val = deposit64(f64_val, 52, 11, f64_exp);
-+    f64_val = deposit64(f64_val, 0, 52, f64_frac);
-+    return make_float64(f64_val);
- }
- /* The algorithm that must be used to calculate the estimate
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
- uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
- {
--    float_status *s = fpstp;
--    float64 f64;
-+    /* float_status *s = fpstp; */
-+    int input, estimate;
-     if ((a & 0x80000000) == 0) {
-         return 0xffffffff;
-     }
--    f64 = make_float64((0x3feULL << 52)
--                       | ((int64_t)(a & 0x7fffffff) << 21));
-+    input = extract32(a, 23, 9);
-+    estimate = recip_estimate(input);
--    f64 = recip_estimate(f64, s);
--
--    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
-+    return deposit32(0, (32 - 9), 9, estimate);
- }
- uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
---
-.16.2

-[Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Now we have added f16 during the re-factoring we can simply call the
-helper.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 8 ++++++++
-file changed, 8 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     case 0x6d: /* FCMLE (zero) */
-         handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
-         return;
-+    case 0x3d: /* FRECPE */
-+        break;
-     case 0x18: /* FRINTN */
-         need_rmode = true;
-         only_in_vector = true;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         case 0x3b: /* FCVTZS */
-             gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
-             break;
-+        case 0x3d: /* FRECPE */
-+            gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-         case 0x5a: /* FCVTNU */
-         case 0x5b: /* FCVTMU */
-         case 0x5c: /* FCVTAU */
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             case 0x3b: /* FCVTZS */
-                 gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
-                 break;
-+            case 0x3d: /* FRECPE */
-+                gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-             case 0x5a: /* FCVTNU */
-             case 0x5b: /* FCVTMU */
-             case 0x5c: /* FCVTAU */
---
-.16.2

-[Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-We go with the localised helper.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |  1 +
- target/arm/helper-a64.c    | 29 +++++++++++++++++++++++++++++
- target/arm/translate-a64.c |  4 ++++
-files changed, 34 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
- DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
- DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
- DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
-+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
- DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
- DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
- DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
- }
- /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
-+float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
-+{
-+    float_status *fpst = fpstp;
-+    uint16_t val16, sbit;
-+    int16_t exp;
-+
-+    if (float16_is_any_nan(a)) {
-+        float16 nan = a;
-+        if (float16_is_signaling_nan(a, fpst)) {
-+            float_raise(float_flag_invalid, fpst);
-+            nan = float16_maybe_silence_nan(a, fpst);
-+        }
-+        if (fpst->default_nan_mode) {
-+            nan = float16_default_nan(fpst);
-+        }
-+        return nan;
-+    }
-+
-+    val16 = float16_val(a);
-+    sbit = 0x8000 & val16;
-+    exp = extract32(val16, 10, 5);
-+
-+    if (exp == 0) {
-+        return make_float16(deposit32(sbit, 10, 5, 0x1e));
-+    } else {
-+        return make_float16(deposit32(sbit, 10, 5, ~exp));
-+    }
-+}
-+
- float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
- {
-     float_status *fpst = fpstp;
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
-         return;
-     case 0x3d: /* FRECPE */
-+    case 0x3f: /* FRECPX */
-         break;
-     case 0x18: /* FRINTN */
-         need_rmode = true;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         case 0x3d: /* FRECPE */
-             gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
-             break;
-+        case 0x3f: /* FRECPX */
-+            gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-         case 0x5a: /* FCVTNU */
-         case 0x5b: /* FCVTMU */
-         case 0x5c: /* FCVTAU */
---
-.16.2

-[Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-a64.h    |  1 +
- target/arm/helper-a64.c    | 13 +++++++++++++
- target/arm/translate-a64.c |  5 +++++
-files changed, 19 insertions(+)
-diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.h
-+++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
- DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
- DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
- DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
-+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
-     }
-     return float16_to_uint16(a, fpst);
- }
-+
-+/*
-+ * Square Root and Reciprocal square root
-+ */
-+
-+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
-+{
-+    float_status *s = fpstp;
-+
-+    return float16_sqrt(a, s);
-+}
-+
-+
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     case 0x6f: /* FNEG */
-         need_fpst = false;
-         break;
-+    case 0x7f: /* FSQRT (vector) */
-+        break;
-     default:
-         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
-         g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             case 0x6f: /* FNEG */
-                 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-                 break;
-+            case 0x7f: /* FSQRT */
-+                gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-             default:
-                 g_assert_not_reached();
-             }
---
-.16.2

-[Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Much like recpe the ARM ARM has simplified the pseudo code for the
-calculation which is done on a fixed point 9 bit integer maths. So
-while adding f16 we can also clean this up to be a little less heavy
-on the floating point and just return the fractional part and leave
-the calle's to do the final packing of the result.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-27-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.h |   1 +
- target/arm/helper.c | 221 ++++++++++++++++++++++++----------------------------
-files changed, 104 insertions(+), 118 deletions(-)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
- DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
- DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
- DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
-+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
- DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
- DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
- DEF_HELPER_2(recpe_u32, i32, i32, ptr)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
- /* The algorithm that must be used to calculate the estimate
-  * is specified by the ARM ARM.
-  */
--static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
-+
-+static int do_recip_sqrt_estimate(int a)
- {
--    /* These calculations mustn't set any fp exception flags,
--     * so we use a local copy of the fp_status.
--     */
--    float_status dummy_status = *real_fp_status;
--    float_status *s = &dummy_status;
--    float64 q;
--    int64_t q_int;
-+    int b, estimate;
--    if (float64_lt(a, float64_half, s)) {
--        /* range 0.25 <= a < 0.5 */
--
--        /* a in units of 1/512 rounded down */
--        /* q0 = (int)(a * 512.0);  */
--        q = float64_mul(float64_512, a, s);
--        q_int = float64_to_int64_round_to_zero(q, s);
--
--        /* reciprocal root r */
--        /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
--        q = int64_to_float64(q_int, s);
--        q = float64_add(q, float64_half, s);
--        q = float64_div(q, float64_512, s);
--        q = float64_sqrt(q, s);
--        q = float64_div(float64_one, q, s);
-+    assert(128 <= a && a < 512);
-+    if (a < 256) {
-+        a = a * 2 + 1;
-     } else {
--        /* range 0.5 <= a < 1.0 */
--
--        /* a in units of 1/256 rounded down */
--        /* q1 = (int)(a * 256.0); */
--        q = float64_mul(float64_256, a, s);
--        int64_t q_int = float64_to_int64_round_to_zero(q, s);
--
--        /* reciprocal root r */
--        /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
--        q = int64_to_float64(q_int, s);
--        q = float64_add(q, float64_half, s);
--        q = float64_div(q, float64_256, s);
--        q = float64_sqrt(q, s);
--        q = float64_div(float64_one, q, s);
-+        a = (a >> 1) << 1;
-+        a = (a + 1) * 2;
-     }
--    /* r in units of 1/256 rounded to nearest */
--    /* s = (int)(256.0 * r + 0.5); */
-+    b = 512;
-+    while (a * (b + 1) * (b + 1) < (1 << 28)) {
-+        b += 1;
-+    }
-+    estimate = (b + 1) / 2;
-+    assert(256 <= estimate && estimate < 512);
--    q = float64_mul(q, float64_256,s );
--    q = float64_add(q, float64_half, s);
--    q_int = float64_to_int64_round_to_zero(q, s);
-+    return estimate;
-+}
--    /* return (double)s / 256.0;*/
--    return float64_div(int64_to_float64(q_int, s), float64_256, s);
-+
-+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
-+{
-+    int estimate;
-+    uint32_t scaled;
-+
-+    if (*exp == 0) {
-+        while (extract64(frac, 51, 1) == 0) {
-+            frac = frac << 1;
-+            *exp -= 1;
-+        }
-+        frac = extract64(frac, 0, 51) << 1;
-+    }
-+
-+    if (*exp & 1) {
-+        /* scaled = UInt('01':fraction<51:45>) */
-+        scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
-+    } else {
-+        /* scaled = UInt('1':fraction<51:44>) */
-+        scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
-+    }
-+    estimate = do_recip_sqrt_estimate(scaled);
-+
-+    *exp = (exp_off - *exp) / 2;
-+    return extract64(estimate, 0, 8) << 44;
-+}
-+
-+float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
-+{
-+    float_status *s = fpstp;
-+    float16 f16 = float16_squash_input_denormal(input, s);
-+    uint16_t val = float16_val(f16);
-+    bool f16_sign = float16_is_neg(f16);
-+    int f16_exp = extract32(val, 10, 5);
-+    uint16_t f16_frac = extract32(val, 0, 10);
-+    uint64_t f64_frac;
-+
-+    if (float16_is_any_nan(f16)) {
-+        float16 nan = f16;
-+        if (float16_is_signaling_nan(f16, s)) {
-+            float_raise(float_flag_invalid, s);
-+            nan = float16_maybe_silence_nan(f16, s);
-+        }
-+        if (s->default_nan_mode) {
-+            nan =  float16_default_nan(s);
-+        }
-+        return nan;
-+    } else if (float16_is_zero(f16)) {
-+        float_raise(float_flag_divbyzero, s);
-+        return float16_set_sign(float16_infinity, f16_sign);
-+    } else if (f16_sign) {
-+        float_raise(float_flag_invalid, s);
-+        return float16_default_nan(s);
-+    } else if (float16_is_infinity(f16)) {
-+        return float16_zero;
-+    }
-+
-+    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
-+     * preserving the parity of the exponent.  */
-+
-+    f64_frac = ((uint64_t) f16_frac) << (52 - 10);
-+
-+    f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
-+
-+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
-+    val = deposit32(0, 15, 1, f16_sign);
-+    val = deposit32(val, 10, 5, f16_exp);
-+    val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
-+    return make_float16(val);
- }
- float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
-     float_status *s = fpstp;
-     float32 f32 = float32_squash_input_denormal(input, s);
-     uint32_t val = float32_val(f32);
--    uint32_t f32_sbit = 0x80000000 & val;
--    int32_t f32_exp = extract32(val, 23, 8);
-+    uint32_t f32_sign = float32_is_neg(f32);
-+    int f32_exp = extract32(val, 23, 8);
-     uint32_t f32_frac = extract32(val, 0, 23);
-     uint64_t f64_frac;
--    uint64_t val64;
--    int result_exp;
--    float64 f64;
-     if (float32_is_any_nan(f32)) {
-         float32 nan = f32;
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
-      * preserving the parity of the exponent.  */
-     f64_frac = ((uint64_t) f32_frac) << 29;
--    if (f32_exp == 0) {
--        while (extract64(f64_frac, 51, 1) == 0) {
--            f64_frac = f64_frac << 1;
--            f32_exp = f32_exp-1;
--        }
--        f64_frac = extract64(f64_frac, 0, 51) << 1;
--    }
--    if (extract64(f32_exp, 0, 1) == 0) {
--        f64 = make_float64(((uint64_t) f32_sbit) << 32
--                           | (0x3feULL << 52)
--                           | f64_frac);
--    } else {
--        f64 = make_float64(((uint64_t) f32_sbit) << 32
--                           | (0x3fdULL << 52)
--                           | f64_frac);
--    }
-+    f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
--    result_exp = (380 - f32_exp) / 2;
--
--    f64 = recip_sqrt_estimate(f64, s);
--
--    val64 = float64_val(f64);
--
--    val = ((result_exp & 0xff) << 23)
--        | ((val64 >> 29)  & 0x7fffff);
-+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
-+    val = deposit32(0, 31, 1, f32_sign);
-+    val = deposit32(val, 23, 8, f32_exp);
-+    val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
-     return make_float32(val);
- }
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
-     float_status *s = fpstp;
-     float64 f64 = float64_squash_input_denormal(input, s);
-     uint64_t val = float64_val(f64);
--    uint64_t f64_sbit = 0x8000000000000000ULL & val;
--    int64_t f64_exp = extract64(val, 52, 11);
-+    bool f64_sign = float64_is_neg(f64);
-+    int f64_exp = extract64(val, 52, 11);
-     uint64_t f64_frac = extract64(val, 0, 52);
--    int64_t result_exp;
--    uint64_t result_frac;
-     if (float64_is_any_nan(f64)) {
-         float64 nan = f64;
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
-         return float64_zero;
-     }
--    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
--     * preserving the parity of the exponent.  */
-+    f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
--    if (f64_exp == 0) {
--        while (extract64(f64_frac, 51, 1) == 0) {
--            f64_frac = f64_frac << 1;
--            f64_exp = f64_exp - 1;
--        }
--        f64_frac = extract64(f64_frac, 0, 51) << 1;
--    }
--
--    if (extract64(f64_exp, 0, 1) == 0) {
--        f64 = make_float64(f64_sbit
--                           | (0x3feULL << 52)
--                           | f64_frac);
--    } else {
--        f64 = make_float64(f64_sbit
--                           | (0x3fdULL << 52)
--                           | f64_frac);
--    }
--
--    result_exp = (3068 - f64_exp) / 2;
--
--    f64 = recip_sqrt_estimate(f64, s);
--
--    result_frac = extract64(float64_val(f64), 0, 52);
--
--    return make_float64(f64_sbit |
--                        ((result_exp & 0x7ff) << 52) |
--                        result_frac);
-+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
-+    val = deposit64(0, 61, 1, f64_sign);
-+    val = deposit64(val, 52, 11, f64_exp);
-+    val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
-+    return make_float64(val);
- }
- uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
- uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
- {
--    float_status *fpst = fpstp;
--    float64 f64;
-+    int estimate;
-     if ((a & 0xc0000000) == 0) {
-         return 0xffffffff;
-     }
--    if (a & 0x80000000) {
--        f64 = make_float64((0x3feULL << 52)
--                           | ((uint64_t)(a & 0x7fffffff) << 21));
--    } else { /* bits 31-30 == '01' */
--        f64 = make_float64((0x3fdULL << 52)
--                           | ((uint64_t)(a & 0x3fffffff) << 22));
--    }
-+    estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
--    f64 = recip_sqrt_estimate(f64, fpst);
--
--    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
-+    return deposit32(0, 23, 9, estimate);
- }
- /* VFPv4 fused multiply-accumulate */
---
-.16.2

-[Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
+Deleted patch
-From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 7 +++++++
-file changed, 7 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-     case 0x6f: /* FNEG */
-         need_fpst = false;
-         break;
-+    case 0x7d: /* FRSQRTE */
-     case 0x7f: /* FSQRT (vector) */
-         break;
-     default:
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-         case 0x6f: /* FNEG */
-             tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-             break;
-+        case 0x7d: /* FRSQRTE */
-+            gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
-+            break;
-         default:
-             g_assert_not_reached();
-         }
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-             case 0x6f: /* FNEG */
-                 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
-                 break;
-+            case 0x7d: /* FRSQRTE */
-+                gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
-+                break;
-             case 0x7f: /* FSQRT */
-                 gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
-                 break;
---
-.16.2

-[Qemu-devel] [PULL 42/42] MAINTAINERS: Update my email address
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-I am leaving Xilinx, so to avoid having an email address that bounces
-update my maintainer address to point to my personal email address.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Signed-off-by: Alistair Francis <alistair@alistair23.me>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- MAINTAINERS | 12 ++++++------
-file changed, 6 insertions(+), 6 deletions(-)
-diff --git a/MAINTAINERS b/MAINTAINERS
-index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: hw/misc/arm_sysctl.c
- Xilinx Zynq
- M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
--M: Alistair Francis <alistair.francis@xilinx.com>
-+M: Alistair Francis <alistair@alistair23.me>
- L: qemu-arm@nongnu.org
- S: Maintained
- F: hw/*/xilinx_*
-@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/zynq*
- X: hw/ssi/xilinx_*
- Xilinx ZynqMP
--M: Alistair Francis <alistair.francis@xilinx.com>
-+M: Alistair Francis <alistair@alistair23.me>
- M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
- L: qemu-arm@nongnu.org
- S: Maintained
-@@ -XXX,XX +XXX,XX @@ T: git git://github.com/bonzini/qemu.git scsi-next
- SSI
- M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
--M: Alistair Francis <alistair.francis@xilinx.com>
-+M: Alistair Francis <alistair@alistair23.me>
- S: Maintained
- F: hw/ssi/*
- F: hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
- F: tests/m25p80-test.c
- Xilinx SPI
--M: Alistair Francis <alistair.francis@xilinx.com>
-+M: Alistair Francis <alistair@alistair23.me>
- M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
- S: Maintained
- F: hw/ssi/xilinx_*
-@@ -XXX,XX +XXX,XX @@ S: Maintained
- F: hw/net/eepro100.c
- Generic Loader
--M: Alistair Francis <alistair.francis@xilinx.com>
-+M: Alistair Francis <alistair@alistair23.me>
- S: Maintained
- F: hw/core/generic-loader.c
- F: include/hw/core/generic-loader.h
-@@ -XXX,XX +XXX,XX @@ F: tests/qmp-test.c
- T: git git://repo.or.cz/qemu/armbru.git qapi-next
- Register API
--M: Alistair Francis <alistair.francis@xilinx.com>
-+M: Alistair Francis <alistair@alistair23.me>
- S: Maintained
- F: hw/core/register.c
- F: include/hw/register.h
---
-.16.2

Arm queue -- I have more stuff pending but I prefer to push
this first lot out and keep the pull below 50 patches.
Most of this is Alex's FP16 support work.

-- PMM

The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:

Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301

for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:

MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000)

----------------------------------------------------------------
target-arm queue:
 * update MAINTAINERS for Alistair's new email address
 * add Arm v8.2 FP16 arithmetic extension for linux-user
 * implement display connector emulation for vexpress board
 * xilinx_spips: Enable only two slaves when reading/writing with stripe
 * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
 * hw: register: Run post_write hook on reset

----------------------------------------------------------------
Alex Bennée (31):
      include/exec/helper-head.h: support f16 in helper calls
      target/arm/cpu64: introduce ARM_V8_FP16 feature bit
      target/arm/cpu.h: update comment for half-precision values
      target/arm/cpu.h: add additional float_status flags
      target/arm/helper: pass explicit fpst to set_rmode
      arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
      arm/translate-a64: handle_3same_64 comment fix
      arm/translate-a64: initial decode for simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
      arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
      arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
      arm/translate-a64: add FP16 x2 ops for simd_indexed
      arm/translate-a64: initial decode for simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
      arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
      arm/helper.c: re-factor recpe and add recepe_f16
      arm/translate-a64: add FP16 FRECPE
      arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
      arm/helper.c: re-factor rsqrte and add rsqrte_f16
      arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FMOV to simd_mod_imm
      arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
      arm/translate-a64: implement simd_scalar_three_reg_same_fp16
      arm/translate-a64: add all single op FP16 to handle_fp_1src_half

Alistair Francis (2):
      hw: register: Run post_write hook on reset
      MAINTAINERS: Update my email address

Corey Minyard (2):
      i2c: Fix some brace style issues
      i2c: Move the bus class to i2c.h

Francisco Iglesias (2):
      xilinx_spips: Enable only two slaves when reading/writing with stripe
      xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands

Linus Walleij (3):
      hw/i2c-ddc: Do not fail writes
      hw/sii9022: Add support for Silicon Image SII9022
      arm/vexpress: Add proper display connector emulation

Peter Maydell (2):
      target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
      linux-user: Report AArch64 FP16 support via hwcap bits

From: Alistair Francis <alistair.francis@xilinx.com>

Ensure that the post write hook is called during reset. This allows us
to rely on the post write functions instead of having to call them from
the reset() function.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: d131e24b911653a945e46ca2d8f90f572469e1dd.1517856214.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/register.h | 6 +++---
 hw/core/register.c    | 8 ++++++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/include/hw/register.h b/include/hw/register.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -XXX,XX +XXX,XX @@ typedef struct RegisterInfoArray RegisterInfoArray;
  * immediately before the actual write. The returned value is what is written,
  * giving the handler a chance to modify the written value.
  * @post_write: Post write callback. Passed the written value. Most write side
- * effects should be implemented here.
+ * effects should be implemented here. This is called during device reset.
  *
  * @post_read: Post read callback. Passes the value that is about to be returned
  * for a read. The return value from this function is what is ultimately read,
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
                        bool debug);
 
 /**
- * reset a register
- * @reg: register to reset
+ * Resets a register. This will also call the post_write hook if it exists.
+ * @reg: The register to reset.
  */
 
 void register_reset(RegisterInfo *reg);
diff --git a/hw/core/register.c b/hw/core/register.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
 
 void register_reset(RegisterInfo *reg)
 {
+    const RegisterAccessInfo *ac;
+
     g_assert(reg);
 
     if (!reg->data || !reg->access) {
         return;
     }
 
+    ac = reg->access;
+
     register_write_val(reg, reg->access->reset);
+
+    if (ac->post_write) {
+        ac->post_write(reg, reg->access->reset);
+    }
 }
 
 void register_init(RegisterInfo *reg)
-- 
2.16.2

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
chip selects are enabled (e.g reading/writing with stripe).

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
 {
     int i;
 
-    for (i = 0; i < s->num_cs; i++) {
+    for (i = 0; i < s->num_cs * s->num_busses; i++) {
         bool old_state = s->cs_lines_state[i];
         bool new_state = field & (1 << i);
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
         }
         qemu_set_irq(s->cs_lines[i], !new_state);
     }
-    if (!(field & ((1 << s->num_cs) - 1))) {
+    if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
         s->snoop_state = SNOOP_CHECKING;
         s->cmd_dummies = 0;
         s->link_state = 1;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
 {
     if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
         int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
-        xilinx_spips_update_cs(XILINX_SPIPS(s), field);
+        bool upper_cs_sel = field & (1 << 1);
+        bool lower_cs_sel = field & 1;
+        bool bus0_enabled;
+        bool bus1_enabled;
+        uint8_t buses;
+        int cs = 0;
+
+        buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
+        bus0_enabled = buses & 1;
+        bus1_enabled = buses & (1 << 1);
+
+        if (bus0_enabled && bus1_enabled) {
+            if (lower_cs_sel) {
+                cs |= 1;
+            }
+            if (upper_cs_sel) {
+                cs |= 1 << 3;
+            }
+        } else if (bus0_enabled) {
+            if (lower_cs_sel) {
+                cs |= 1;
+            }
+            if (upper_cs_sel) {
+                cs |= 1 << 1;
+            }
+        } else if (bus1_enabled) {
+            if (lower_cs_sel) {
+                cs |= 1 << 2;
+            }
+            if (upper_cs_sel) {
+                cs |= 1 << 3;
+            }
+        }
+        xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
     if (num_effective_busses(s) == 2) {
         /* Single bit chip-select for qspi */
         field &= 0x1;
-        field |= field << 1;
+        field |= field << 3;
     /* Dual stack U-Page */
     } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
                s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
-- 
2.16.2

From: Corey Minyard <cminyard@mvista.com>

Signed-off-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-2-linus.walleij@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/i2c.h | 6 ++----
 hw/i2c/core.c        | 3 +--
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlave I2CSlave;
 #define I2C_SLAVE_GET_CLASS(obj) \
      OBJECT_GET_CLASS(I2CSlaveClass, (obj), TYPE_I2C_SLAVE)
 
-typedef struct I2CSlaveClass
-{
+typedef struct I2CSlaveClass {
     DeviceClass parent_class;
 
     /* Callbacks provided by the device.  */
@@ -XXX,XX +XXX,XX @@ typedef struct I2CSlaveClass
     int (*event)(I2CSlave *s, enum i2c_event event);
 } I2CSlaveClass;
 
-struct I2CSlave
-{
+struct I2CSlave {
     DeviceState qdev;
 
     /* Remaining fields for internal use by the I2C code.  */
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -XXX,XX +XXX,XX @@ struct I2CNode {
 
 #define I2C_BROADCAST 0x00
 
-struct I2CBus
-{
+struct I2CBus {
     BusState qbus;
     QLIST_HEAD(, I2CNode) current_devs;
     uint8_t saved_address;
-- 
2.16.2

From: Corey Minyard <cminyard@mvista.com>

Some devices need access to it.

Signed-off-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-3-linus.walleij@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/i2c.h | 17 +++++++++++++++++
 hw/i2c/core.c        | 17 -----------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -XXX,XX +XXX,XX @@ struct I2CSlave {
     uint8_t address;
 };
 
+#define TYPE_I2C_BUS "i2c-bus"
+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
+
+typedef struct I2CNode I2CNode;
+
+struct I2CNode {
+    I2CSlave *elt;
+    QLIST_ENTRY(I2CNode) next;
+};
+
+struct I2CBus {
+    BusState qbus;
+    QLIST_HEAD(, I2CNode) current_devs;
+    uint8_t saved_address;
+    bool broadcast;
+};
+
 I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
 void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
 int i2c_bus_busy(I2CBus *bus);
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/i2c/i2c.h"
 
-typedef struct I2CNode I2CNode;
-
-struct I2CNode {
-    I2CSlave *elt;
-    QLIST_ENTRY(I2CNode) next;
-};
-
 #define I2C_BROADCAST 0x00
 
-struct I2CBus {
-    BusState qbus;
-    QLIST_HEAD(, I2CNode) current_devs;
-    uint8_t saved_address;
-    bool broadcast;
-};
-
 static Property i2c_props[] = {
     DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-#define TYPE_I2C_BUS "i2c-bus"
-#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
-
 static const TypeInfo i2c_bus_info = {
     .name = TYPE_I2C_BUS,
     .parent = TYPE_BUS,
-- 
2.16.2

From: Linus Walleij <linus.walleij@linaro.org>

The tx function of the DDC I2C slave emulation was returning 1
on all writes resulting in NACK in the I2C bus. Changing it to
0 makes the DDC I2C work fine with bit-banged I2C such as the
versatile I2C.

I guess it was not affecting whatever I2C controller this was
used with until now, but with the Versatile I2C it surely
does not work.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-4-linus.walleij@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/i2c-ddc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/i2c-ddc.c
+++ b/hw/i2c/i2c-ddc.c
@@ -XXX,XX +XXX,XX @@ static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
         s->reg = data;
         s->firstbyte = false;
         DPRINTF("[EDID] Written new pointer: %u\n", data);
-        return 1;
+        return 0;
     }
 
     /* Ignore all writes */
     s->reg++;
-    return 1;
+    return 0;
 }
 
 static void i2c_ddc_init(Object *obj)
-- 
2.16.2

From: Linus Walleij <linus.walleij@linaro.org>

This adds support for emulating the Silicon Image SII9022 DVI/HDMI
bridge. It's not very clever right now, it just acknowledges
the switch into DDC I2C mode and back. Combining this with the
existing DDC I2C emulation gives the right behavior on the Versatile
Express emulation passing through the QEMU EDID to the emulated
platform.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/display/Makefile.objs |   1 +
 hw/display/sii9022.c     | 191 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/display/trace-events  |   5 ++
 3 files changed, 197 insertions(+)
 create mode 100644 hw/display/sii9022.c

diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
 common-obj-$(CONFIG_G364FB) += g364fb.o
 common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
 common-obj-$(CONFIG_PL110) += pl110.o
+common-obj-$(CONFIG_SII9022) += sii9022.o
 common-obj-$(CONFIG_SSD0303) += ssd0303.o
 common-obj-$(CONFIG_SSD0323) += ssd0323.o
 common-obj-$(CONFIG_XEN) += xenfb.o
diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/display/sii9022.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Silicon Image SiI9022
+ *
+ * This is a pretty hollow emulation: all we do is acknowledge that we
+ * exist (chip ID) and confirm that we get switched over into DDC mode
+ * so the emulated host can proceed to read out EDID data. All subsequent
+ * set-up of connectors etc will be acknowledged and ignored.
+ *
+ * Copyright (C) 2018 Linus Walleij
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/i2c-ddc.h"
+#include "trace.h"
+
+#define SII9022_SYS_CTRL_DATA 0x1a
+#define SII9022_SYS_CTRL_PWR_DWN 0x10
+#define SII9022_SYS_CTRL_AV_MUTE 0x08
+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
+#define SII9022_REG_CHIPID 0x1b
+#define SII9022_INT_ENABLE 0x3c
+#define SII9022_INT_STATUS 0x3d
+#define SII9022_INT_STATUS_HOTPLUG 0x01;
+#define SII9022_INT_STATUS_PLUGGED 0x04;
+
+#define TYPE_SII9022 "sii9022"
+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
+
+typedef struct sii9022_state {
+    I2CSlave parent_obj;
+    uint8_t ptr;
+    bool addr_byte;
+    bool ddc_req;
+    bool ddc_skip_finish;
+    bool ddc;
+} sii9022_state;
+
+static const VMStateDescription vmstate_sii9022 = {
+    .name = "sii9022",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
+        VMSTATE_UINT8(ptr, sii9022_state),
+        VMSTATE_BOOL(addr_byte, sii9022_state),
+        VMSTATE_BOOL(ddc_req, sii9022_state),
+        VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
+        VMSTATE_BOOL(ddc, sii9022_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
+{
+    sii9022_state *s = SII9022(i2c);
+
+    switch (event) {
+    case I2C_START_SEND:
+        s->addr_byte = true;
+        break;
+    case I2C_START_RECV:
+        break;
+    case I2C_FINISH:
+        break;
+    case I2C_NACK:
+        break;
+    }
+
+    return 0;
+}
+
+static int sii9022_rx(I2CSlave *i2c)
+{
+    sii9022_state *s = SII9022(i2c);
+    uint8_t res = 0x00;
+
+    switch (s->ptr) {
+    case SII9022_SYS_CTRL_DATA:
+        if (s->ddc_req) {
+            /* Acknowledge DDC bus request */
+            res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
+        }
+        break;
+    case SII9022_REG_CHIPID:
+        res = 0xb0;
+        break;
+    case SII9022_INT_STATUS:
+        /* Something is cold-plugged in, no interrupts */
+        res = SII9022_INT_STATUS_PLUGGED;
+        break;
+    default:
+        break;
+    }
+
+    trace_sii9022_read_reg(s->ptr, res);
+    s->ptr++;
+
+    return res;
+}
+
+static int sii9022_tx(I2CSlave *i2c, uint8_t data)
+{
+    sii9022_state *s = SII9022(i2c);
+
+    if (s->addr_byte) {
+        s->ptr = data;
+        s->addr_byte = false;
+        return 0;
+    }
+
+    switch (s->ptr) {
+    case SII9022_SYS_CTRL_DATA:
+        if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
+            s->ddc_req = true;
+            if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
+                s->ddc = true;
+                /* Skip this finish since we just switched to DDC */
+                s->ddc_skip_finish = true;
+                trace_sii9022_switch_mode("DDC");
+            }
+        } else {
+            s->ddc_req = false;
+            s->ddc = false;
+            trace_sii9022_switch_mode("normal");
+        }
+        break;
+    default:
+        break;
+    }
+
+    trace_sii9022_write_reg(s->ptr, data);
+    s->ptr++;
+
+    return 0;
+}
+
+static void sii9022_reset(DeviceState *dev)
+{
+    sii9022_state *s = SII9022(dev);
+
+    s->ptr = 0;
+    s->addr_byte = false;
+    s->ddc_req = false;
+    s->ddc_skip_finish = false;
+    s->ddc = false;
+}
+
+static void sii9022_realize(DeviceState *dev, Error **errp)
+{
+    I2CBus *bus;
+
+    bus = I2C_BUS(qdev_get_parent_bus(dev));
+    i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
+}
+
+static void sii9022_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+    k->event = sii9022_event;
+    k->recv = sii9022_rx;
+    k->send = sii9022_tx;
+    dc->reset = sii9022_reset;
+    dc->realize = sii9022_realize;
+    dc->vmsd = &vmstate_sii9022;
+}
+
+static const TypeInfo sii9022_info = {
+    .name          = TYPE_SII9022,
+    .parent        = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(sii9022_state),
+    .class_init    = sii9022_class_init,
+};
+
+static void sii9022_register_types(void)
+{
+    type_register_static(&sii9022_info);
+}
+
+type_init(sii9022_register_types)
diff --git a/hw/display/trace-events b/hw/display/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -XXX,XX +XXX,XX @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
 vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
+
+# hw/display/sii9022.c
+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+sii9022_switch_mode(const char *mode) "mode: %s"
-- 
2.16.2

From: Linus Walleij <linus.walleij@linaro.org>

This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
Versatile Express machine, and selects the two I2C devices necessary
in the arm-softmmu.mak configuration so everything will build
smoothly.

I am implementing proper handling of the graphics in the Linux
kernel and adding proper emulation of SiI9022 and EDID makes the
driver probe as nicely as before, retrieving the resolutions
supported by the "QEMU monitor" and overall just working nice.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-6-linus.walleij@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/vexpress.c               | 6 +++++-
 default-configs/arm-softmmu.mak | 2 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/arm.h"
 #include "hw/arm/primecell.h"
 #include "hw/devices.h"
+#include "hw/i2c/i2c.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     uint32_t sys_id;
     DriveInfo *dinfo;
     pflash_t *pflash0;
+    I2CBus *i2c;
     ram_addr_t vram_size, sram_size;
     MemoryRegion *sysmem = get_system_memory();
     MemoryRegion *vram = g_new(MemoryRegion, 1);
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 
-    /* VE_SERIALDVI: not modelled */
+    dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
+    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
+    i2c_create_slave(i2c, "sii9022", 0x39);
 
     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_STELLARIS_INPUT=y
 CONFIG_STELLARIS_ENET=y
 CONFIG_SSD0303=y
 CONFIG_SSD0323=y
+CONFIG_DDC=y
+CONFIG_SII9022=y
 CONFIG_ADS7846=y
 CONFIG_MAX111X=y
 CONFIG_SSI=y
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-2-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/helper-head.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_int i32
 #define dh_alias_i64 i64
 #define dh_alias_s64 i64
+#define dh_alias_f16 i32
 #define dh_alias_f32 i32
 #define dh_alias_f64 i64
 #define dh_alias_ptr ptr
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_int int
 #define dh_ctype_i64 uint64_t
 #define dh_ctype_s64 int64_t
+#define dh_ctype_f16 float16
 #define dh_ctype_f32 float32
 #define dh_ctype_f64 float64
 #define dh_ctype_ptr void *
@@ -XXX,XX +XXX,XX @@
 #define dh_is_signed_s32 1
 #define dh_is_signed_i64 0
 #define dh_is_signed_s64 1
+#define dh_is_signed_f16 0
 #define dh_is_signed_f32 0
 #define dh_is_signed_f64 0
 #define dh_is_signed_tl  0
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h           | 32 ++++++++++++++++++++++------
 target/arm/helper.c        | 26 ++++++++++++++++++-----
 target/arm/translate-a64.c | 53 +++++++++++++++++++++++++---------------------
 3 files changed, 75 insertions(+), 36 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
         /* scratch space when Tn are not sufficient.  */
         uint32_t scratch[8];
 
-        /* fp_status is the "normal" fp status. standard_fp_status retains
-         * values corresponding to the ARM "Standard FPSCR Value", ie
-         * default-NaN, flush-to-zero, round-to-nearest and is used by
-         * any operations (generally Neon) which the architecture defines
-         * as controlled by the standard FPSCR value rather than the FPSCR.
+        /* There are a number of distinct float control structures:
+         *
+         *  fp_status: is the "normal" fp status.
+         *  fp_status_fp16: used for half-precision calculations
+         *  standard_fp_status : the ARM "Standard FPSCR Value"
+         *
+         * Half-precision operations are governed by a separate
+         * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
+         * status structure to control this.
+         *
+         * The "Standard FPSCR", ie default-NaN, flush-to-zero,
+         * round-to-nearest and is used by any operations (generally
+         * Neon) which the architecture defines as controlled by the
+         * standard FPSCR value rather than the FPSCR.
          *
          * To avoid having to transfer exception bits around, we simply
          * say that the FPSCR cumulative exception flags are the logical
-         * OR of the flags in the two fp statuses. This relies on the
+         * OR of the flags in the three fp statuses. This relies on the
          * only thing which needs to read the exception flags being
          * an explicit FPSCR read.
          */
         float_status fp_status;
+        float_status fp_status_f16;
         float_status standard_fp_status;
 
         /* ZCR_EL[1-3] */
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 uint32_t vfp_get_fpscr(CPUARMState *env);
 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 
-/* For A64 the FPSCR is split into two logically distinct registers,
+/* FPCR, Floating Point Control Register
+ * FPSR, Floating Poiht Status Register
+ *
+ * For A64 the FPSCR is split into two logically distinct registers,
  * FPCR and FPSR. However since they still use non-overlapping bits
  * we store the underlying state in fpscr and just mask on read/write.
  */
 #define FPSR_MASK 0xf800009f
 #define FPCR_MASK 0x07f79f00
+
+#define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
+#define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
+#define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
+
 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
 {
     return vfp_get_fpscr(env) & FPSR_MASK;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
             | (env->vfp.vec_stride << 20);
     i = get_float_exception_flags(&env->vfp.fp_status);
     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
+    i |= get_float_exception_flags(&env->vfp.fp_status_f16);
     fpscr |= vfp_exceptbits_from_host(i);
     return fpscr;
 }
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
             break;
         }
         set_float_rounding_mode(i, &env->vfp.fp_status);
+        set_float_rounding_mode(i, &env->vfp.fp_status_f16);
     }
-    if (changed & (1 << 24)) {
-        set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
-        set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
+    if (changed & FPCR_FZ16) {
+        bool ftz_enabled = val & FPCR_FZ16;
+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+    }
+    if (changed & FPCR_FZ) {
+        bool ftz_enabled = val & FPCR_FZ;
+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
+        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
+    }
+    if (changed & FPCR_DN) {
+        bool dnan_enabled = val & FPCR_DN;
+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
     }
-    if (changed & (1 << 25))
-        set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
 
+    /* The exception flags are ORed together when we read fpscr so we
+     * only need to preserve the current state in one of our
+     * float_status values.
+     */
     i = vfp_exceptbits_to_host(val);
     set_float_exception_flags(i, &env->vfp.fp_status);
+    set_float_exception_flags(0, &env->vfp.fp_status_f16);
     set_float_exception_flags(0, &env->vfp.standard_fp_status);
 }
 
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
     tcg_temp_free_i64(tmp);
 }
 
-static TCGv_ptr get_fpstatus_ptr(void)
+static TCGv_ptr get_fpstatus_ptr(bool is_f16)
 {
     TCGv_ptr statusptr = tcg_temp_new_ptr();
     int offset;
 
-    /* In A64 all instructions (both FP and Neon) use the FPCR;
-     * there is no equivalent of the A32 Neon "standard FPSCR value"
-     * and all operations use vfp.fp_status.
+    /* In A64 all instructions (both FP and Neon) use the FPCR; there
+     * is no equivalent of the A32 Neon "standard FPSCR value".
+     * However half-precision operations operate under a different
+     * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
      */
-    offset = offsetof(CPUARMState, vfp.fp_status);
+    if (is_f16) {
+        offset = offsetof(CPUARMState, vfp.fp_status_f16);
+    } else {
+        offset = offsetof(CPUARMState, vfp.fp_status);
+    }
     tcg_gen_addi_ptr(statusptr, cpu_env, offset);
     return statusptr;
 }
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
                               bool cmp_with_zero, bool signal_all_nans)
 {
     TCGv_i64 tcg_flags = tcg_temp_new_i64();
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     if (is_double) {
         TCGv_i64 tcg_vn, tcg_vm;
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
     TCGv_i32 tcg_op;
     TCGv_i32 tcg_res;
 
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op = read_fp_sreg(s, rn);
     tcg_res = tcg_temp_new_i32();
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
         return;
     }
 
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op = read_fp_dreg(s, rn);
     tcg_res = tcg_temp_new_i64();
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
     TCGv_ptr fpst;
 
     tcg_res = tcg_temp_new_i32();
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op1 = read_fp_sreg(s, rn);
     tcg_op2 = read_fp_sreg(s, rm);
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
     TCGv_ptr fpst;
 
     tcg_res = tcg_temp_new_i64();
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
     tcg_op1 = read_fp_dreg(s, rn);
     tcg_op2 = read_fp_dreg(s, rm);
 
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
 {
     TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
     TCGv_i32 tcg_res = tcg_temp_new_i32();
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     tcg_op1 = read_fp_sreg(s, rn);
     tcg_op2 = read_fp_sreg(s, rm);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
 {
     TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
     TCGv_i64 tcg_res = tcg_temp_new_i64();
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     tcg_op1 = read_fp_dreg(s, rn);
     tcg_op2 = read_fp_dreg(s, rm);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
     TCGv_ptr tcg_fpstatus;
     TCGv_i32 tcg_shift;
 
-    tcg_fpstatus = get_fpstatus_ptr();
+    tcg_fpstatus = get_fpstatus_ptr(false);
 
     tcg_shift = tcg_const_i32(64 - scale);
 
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
         TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
         TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
         TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
-        TCGv_ptr fpst = get_fpstatus_ptr();
+        TCGv_ptr fpst = get_fpstatus_ptr(false);
 
         assert(esize == 32);
         assert(elements == 4);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
         }
 
         size = extract32(size, 0, 1) ? 3 : 2;
-        fpst = get_fpstatus_ptr();
+        fpst = get_fpstatus_ptr(false);
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
                                    int fracbits, int size)
 {
     bool is_double = size == 3 ? true : false;
-    TCGv_ptr tcg_fpst = get_fpstatus_ptr();
+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
     TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
     TCGv_i64 tcg_int = tcg_temp_new_i64();
     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
 
     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-    tcg_fpstatus = get_fpstatus_ptr();
+    tcg_fpstatus = get_fpstatus_ptr(false);
     tcg_shift = tcg_const_i32(fracbits);
 
     if (is_double) {
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
                                int fpopcode, int rd, int rn, int rm)
 {
     int pass;
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     for (pass = 0; pass < elements; pass++) {
         if (size) {
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
         return;
     }
 
-    fpst = get_fpstatus_ptr();
+    fpst = get_fpstatus_ptr(false);
 
     if (is_double) {
         TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
                                     int size, int rn, int rd)
 {
     bool is_double = (size == 3);
-    TCGv_ptr fpst = get_fpstatus_ptr();
+    TCGv_ptr fpst = get_fpstatus_ptr(false);
 
     if (is_double) {
         TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
     if (is_fcvt) {
         tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
         gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
-        tcg_fpstatus = get_fpstatus_ptr();
+        tcg_fpstatus = get_fpstatus_ptr(false);
     } else {
         tcg_rmode = NULL;
         tcg_fpstatus = NULL;
@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
 
     /* Floating point operations need fpst */
     if (opcode >= 0x58) {
-        fpst = get_fpstatus_ptr();
+        fpst = get_fpstatus_ptr(false);
     } else {
         fpst = NULL;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
     }
 
     if (need_fpstatus) {
-        tcg_fpstatus = get_fpstatus_ptr();
+        tcg_fpstatus = get_fpstatus_ptr(false);
     } else {
         tcg_fpstatus = NULL;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
     }
 
     if (is_fp) {
-        fpst = get_fpstatus_ptr();
+        fpst = get_fpstatus_ptr(false);
     } else {
         fpst = NULL;
     }
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

As the rounding mode is now split between FP16 and the rest of
floating point we need to be explicit when tweaking it. Instead of
passing the CPU env we now pass the appropriate fpst pointer directly.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-6-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  2 +-
 target/arm/helper.c        |  4 ++--
 target/arm/translate-a64.c | 26 +++++++++++++-------------
 target/arm/translate.c     | 12 ++++++------
 4 files changed, 22 insertions(+), 22 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |   4 ++
 target/arm/helper-a64.c    |  18 ++++++
 target/arm/translate-a64.c | 140 ++++++++++++++++++++++++++++-----------------
 3 files changed, 109 insertions(+), 53 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG,
 DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
 DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG,
                    i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
 {
     return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
 }
+
+/*
+ * AdvSIMD half-precision
+ */
+
+#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
+
+#define ADVSIMD_HALFOP(name) \
+float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+{ \
+    float_status *fpst = fpstp; \
+    return float16_ ## name(a, b, fpst);    \
+}
+
+ADVSIMD_HALFOP(min)
+ADVSIMD_HALFOP(max)
+ADVSIMD_HALFOP(minnum)
+ADVSIMD_HALFOP(maxnum)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resh);
 }
 
-static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
-                        int opc, bool is_min, TCGv_ptr fpst)
+/*
+ * do_reduction_op helper
+ *
+ * This mirrors the Reduce() pseudocode in the ARM ARM. It is
+ * important for correct NaN propagation that we do these
+ * operations in exactly the order specified by the pseudocode.
+ *
+ * This is a recursive function, TCG temps should be freed by the
+ * calling function once it is done with the values.
+ */
+static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
+                                int esize, int size, int vmap, TCGv_ptr fpst)
 {
-    /* Helper function for disas_simd_across_lanes: do a single precision
-     * min/max operation on the specified two inputs,
-     * and return the result in tcg_elt1.
-     */
-    if (opc == 0xc) {
-        if (is_min) {
-            gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-        } else {
-            gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-        }
+    if (esize == size) {
+        int element;
+        TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
+        TCGv_i32 tcg_elem;
+
+        /* We should have one register left here */
+        assert(ctpop8(vmap) == 1);
+        element = ctz32(vmap);
+        assert(element < 8);
+
+        tcg_elem = tcg_temp_new_i32();
+        read_vec_element_i32(s, tcg_elem, rn, element, msize);
+        return tcg_elem;
     } else {
-        assert(opc == 0xf);
-        if (is_min) {
-            gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
-        } else {
-            gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+        int bits = size / 2;
+        int shift = ctpop8(vmap) / 2;
+        int vmap_lo = (vmap >> shift) & vmap;
+        int vmap_hi = (vmap & ~vmap_lo);
+        TCGv_i32 tcg_hi, tcg_lo, tcg_res;
+
+        tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
+        tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
+        tcg_res = tcg_temp_new_i32();
+
+        switch (fpopcode) {
+        case 0x0c: /* fmaxnmv half-precision */
+            gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x0f: /* fmaxv half-precision */
+            gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x1c: /* fminnmv half-precision */
+            gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x1f: /* fminv half-precision */
+            gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x2c: /* fmaxnmv */
+            gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x2f: /* fmaxv */
+            gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x3c: /* fminnmv */
+            gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        case 0x3f: /* fminv */
+            gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
+            break;
+        default:
+            g_assert_not_reached();
         }
+
+        tcg_temp_free_i32(tcg_hi);
+        tcg_temp_free_i32(tcg_lo);
+        return tcg_res;
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
         break;
     case 0xc: /* FMAXNMV, FMINNMV */
     case 0xf: /* FMAXV, FMINV */
-        if (!is_u || !is_q || extract32(size, 0, 1)) {
-            unallocated_encoding(s);
-            return;
-        }
-        /* Bit 1 of size field encodes min vs max, and actual size is always
-         * 32 bits: adjust the size variable so following code can rely on it
+        /* Bit 1 of size field encodes min vs max and the actual size
+         * depends on the encoding of the U bit. If not set (and FP16
+         * enabled) then we do half-precision float instead of single
+         * precision.
          */
         is_min = extract32(size, 1, 1);
         is_fp = true;
-        size = 2;
+        if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            size = 1;
+        } else if (!is_u || !is_q || extract32(size, 0, 1)) {
+            unallocated_encoding(s);
+            return;
+        } else {
+            size = 2;
+        }
         break;
     default:
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
 
         }
     } else {
-        /* Floating point ops which work on 32 bit (single) intermediates.
+        /* Floating point vector reduction ops which work across 32
+         * bit (single) or 16 bit (half-precision) intermediates.
          * Note that correct NaN propagation requires that we do these
          * operations in exactly the order specified by the pseudocode.
          */
-        TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
-        TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
-        TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
-        TCGv_ptr fpst = get_fpstatus_ptr(false);
-
-        assert(esize == 32);
-        assert(elements == 4);
-
-        read_vec_element(s, tcg_elt, rn, 0, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
-        read_vec_element(s, tcg_elt, rn, 1, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
-
-        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
-
-        read_vec_element(s, tcg_elt, rn, 2, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
-        read_vec_element(s, tcg_elt, rn, 3, MO_32);
-        tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
-
-        do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
-
-        do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
-
-        tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
-        tcg_temp_free_i32(tcg_elt1);
-        tcg_temp_free_i32(tcg_elt2);
-        tcg_temp_free_i32(tcg_elt3);
+        TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
+        int fpopcode = opcode | is_min << 4 | is_u << 5;
+        int vmap = (1 << elements) - 1;
+        TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
+                                             (is_q ? 128 : 64), vmap, fpst);
+        tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
+        tcg_temp_free_i32(tcg_res32);
         tcg_temp_free_ptr(fpst);
     }
 
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

We do implement all the opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-8-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
     /* Handle 64x64->64 opcodes which are shared between the scalar
      * and vector 3-same groups. We cover every opcode where size == 3
      * is valid in either the three-reg-same (integer, not pairwise)
-     * or scalar-three-reg-same groups. (Some opcodes are not yet
-     * implemented.)
+     * or scalar-three-reg-same groups.
      */
     TCGCond cond;
 
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This is the initial decode skeleton for the Advanced SIMD three same
instruction group.

The fprintf is purely to aid debugging as the additional instructions
are added. It will be removed once the group is complete.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-9-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-10-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  4 ++++
 target/arm/helper-a64.c    |  4 ++++
 target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
     return float16_ ## name(a, b, fpst);    \
 }
 
+ADVSIMD_HALFOP(add)
+ADVSIMD_HALFOP(sub)
+ADVSIMD_HALFOP(mul)
+ADVSIMD_HALFOP(div)
 ADVSIMD_HALFOP(min)
 ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
 
         switch (fpopcode) {
+        case 0x0: /* FMAXNM */
+            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x2: /* FADD */
+            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x6: /* FMAX */
+            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x8: /* FMINNM */
+            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xa: /* FSUB */
+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xe: /* FMIN */
+            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x13: /* FMUL */
+            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x17: /* FDIV */
+            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x1a: /* FABD */
+            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
+            break;
         default:
             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
                     __func__, insn, fpopcode, s->pc);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-11-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  5 +++++
 target/arm/helper-a64.c    | 49 ++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 15 ++++++++++++++
 3 files changed, 69 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
 DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
 DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
 DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(min)
 ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
 ADVSIMD_HALFOP(maxnum)
+
+/*
+ * Floating point comparisons produce an integer result. Softfloat
+ * routines return float_relation types which we convert to the 0/-1
+ * Neon requires.
+ */
+
+#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
+
+uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    int compare = float16_compare_quiet(a, b, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_equal);
+}
+
+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    int compare = float16_compare(a, b, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater ||
+                          compare == float_relation_equal);
+}
+
+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    int compare = float16_compare(a, b, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater);
+}
+
+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16 f0 = float16_abs(a);
+    float16 f1 = float16_abs(b);
+    int compare = float16_compare(f0, f1, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater ||
+                          compare == float_relation_equal);
+}
+
+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16 f0 = float16_abs(a);
+    float16 f1 = float16_abs(b);
+    int compare = float16_compare(f0, f1, fpst);
+    return ADVSIMD_CMPRES(compare == float_relation_greater);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x2: /* FADD */
             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x4: /* FCMEQ */
+            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x6: /* FMAX */
             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x13: /* FMUL */
             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x14: /* FCMGE */
+            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x15: /* FACGE */
+            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x17: /* FDIV */
             gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
             tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
             break;
+        case 0x1c: /* FCMGT */
+            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x1d: /* FACGT */
+            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         default:
             fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
                     __func__, insn, fpopcode, s->pc);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-12-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  2 ++
 target/arm/helper-a64.c    | 24 ++++++++++++++++++++++++
 target/arm/translate-a64.c | 15 +++++++++++++++
 3 files changed, 41 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
 ADVSIMD_HALFOP(maxnum)
 
+/* Data processing - scalar floating-point and advanced SIMD */
+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    a = float16_squash_input_denormal(a, fpst);
+    b = float16_squash_input_denormal(b, fpst);
+
+    if ((float16_is_zero(a) && float16_is_infinity(b)) ||
+        (float16_is_infinity(a) && float16_is_zero(b))) {
+        /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
+        return make_float16((1U << 14) |
+                            ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
+    }
+    return float16_mul(a, b, fpst);
+}
+
+/* fused multiply-accumulate */
+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    return float16_muladd(a, b, c, 0, fpst);
+}
+
 /*
  * Floating point comparisons produce an integer result. Softfloat
  * routines return float_relation types which we convert to the 0/-1
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x0: /* FMAXNM */
             gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x1: /* FMLA */
+            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                       fpst);
+            break;
         case 0x2: /* FADD */
             gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x3: /* FMULX */
+            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x4: /* FCMEQ */
             gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x8: /* FMINNM */
             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x9: /* FMLS */
+             /* As usual for ARM, separate negation for fused multiply-add */
+            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
+            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                       fpst);
+            break;
         case 0xa: /* FSUB */
             gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-13-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/fpu/softfloat.h    | 18 +++++++++++++-----
 target/arm/helper-a64.h    |  2 ++
 target/arm/helper-a64.c    | 34 ++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c |  6 ++++++
 4 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index XXXXXXX..XXXXXXX 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -XXX,XX +XXX,XX @@ static inline float16 float16_set_sign(float16 a, int sign)
 }
 
 #define float16_zero make_float16(0)
-#define float16_one make_float16(0x3c00)
 #define float16_half make_float16(0x3800)
+#define float16_one make_float16(0x3c00)
+#define float16_one_point_five make_float16(0x3e00)
+#define float16_two make_float16(0x4000)
+#define float16_three make_float16(0x4200)
 #define float16_infinity make_float16(0x7c00)
 
 /*----------------------------------------------------------------------------
@@ -XXX,XX +XXX,XX @@ static inline float32 float32_set_sign(float32 a, int sign)
 }
 
 #define float32_zero make_float32(0)
-#define float32_one make_float32(0x3f800000)
 #define float32_half make_float32(0x3f000000)
+#define float32_one make_float32(0x3f800000)
+#define float32_one_point_five make_float32(0x3fc00000)
+#define float32_two make_float32(0x40000000)
+#define float32_three make_float32(0x40400000)
 #define float32_infinity make_float32(0x7f800000)
 
-
 /*----------------------------------------------------------------------------
 | The pattern for a default generated single-precision NaN.
 *----------------------------------------------------------------------------*/
@@ -XXX,XX +XXX,XX @@ static inline float64 float64_set_sign(float64 a, int sign)
 }
 
 #define float64_zero make_float64(0)
-#define float64_one make_float64(0x3ff0000000000000LL)
-#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
 #define float64_half make_float64(0x3fe0000000000000LL)
+#define float64_one make_float64(0x3ff0000000000000LL)
+#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
+#define float64_two make_float64(0x4000000000000000ULL)
+#define float64_three make_float64(0x4008000000000000ULL)
+#define float64_ln2 make_float64(0x3fe62e42fefa39efLL)
 #define float64_infinity make_float64(0x7ff0000000000000LL)
 
 /*----------------------------------------------------------------------------
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
 DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
 DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
 DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
+DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
 DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
+DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
 DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
 DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
 DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
  * versions, these do a fully fused multiply-add or
  * multiply-add-and-halve.
  */
+#define float16_two make_float16(0x4000)
+#define float16_three make_float16(0x4200)
+#define float16_one_point_five make_float16(0x3e00)
+
 #define float32_two make_float32(0x40000000)
 #define float32_three make_float32(0x40400000)
 #define float32_one_point_five make_float32(0x3fc00000)
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 #define float64_three make_float64(0x4008000000000000ULL)
 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
+float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    a = float16_squash_input_denormal(a, fpst);
+    b = float16_squash_input_denormal(b, fpst);
+
+    a = float16_chs(a);
+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
+        (float16_is_infinity(b) && float16_is_zero(a))) {
+        return float16_two;
+    }
+    return float16_muladd(a, b, float16_two, 0, fpst);
+}
+
 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 {
     float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
     return float64_muladd(a, b, float64_two, 0, fpst);
 }
 
+float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    a = float16_squash_input_denormal(a, fpst);
+    b = float16_squash_input_denormal(b, fpst);
+
+    a = float16_chs(a);
+    if ((float16_is_infinity(a) && float16_is_zero(b)) ||
+        (float16_is_infinity(b) && float16_is_zero(a))) {
+        return float16_one_point_five;
+    }
+    return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
+}
+
 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 {
     float_status *fpst = fpstp;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0x6: /* FMAX */
             gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0x7: /* FRECPS */
+            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x8: /* FMINNM */
             gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
         case 0xe: /* FMIN */
             gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
+        case 0xf: /* FRSQRTS */
+            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
         case 0x13: /* FMUL */
             gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
             break;
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++----------------
 1 file changed, 133 insertions(+), 75 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
     int datasize, elements;
     int pass;
     TCGv_ptr fpst;
+    bool pairwise = false;
 
     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
         unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
     datasize = is_q ? 128 : 64;
     elements = datasize / 16;
 
+    switch (fpopcode) {
+    case 0x10: /* FMAXNMP */
+    case 0x12: /* FADDP */
+    case 0x16: /* FMAXP */
+    case 0x18: /* FMINNMP */
+    case 0x1e: /* FMINP */
+        pairwise = true;
+        break;
+    }
+
     fpst = get_fpstatus_ptr(true);
 
-    for (pass = 0; pass < elements; pass++) {
+    if (pairwise) {
+        int maxpass = is_q ? 8 : 4;
         TCGv_i32 tcg_op1 = tcg_temp_new_i32();
         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-        TCGv_i32 tcg_res = tcg_temp_new_i32();
+        TCGv_i32 tcg_res[8];
 
-        read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
-        read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+        for (pass = 0; pass < maxpass; pass++) {
+            int passreg = pass < (maxpass / 2) ? rn : rm;
+            int passelt = (pass << 1) & (maxpass - 1);
 
-        switch (fpopcode) {
-        case 0x0: /* FMAXNM */
-            gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x1: /* FMLA */
-            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-                                       fpst);
-            break;
-        case 0x2: /* FADD */
-            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x3: /* FMULX */
-            gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x4: /* FCMEQ */
-            gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x6: /* FMAX */
-            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x7: /* FRECPS */
-            gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x8: /* FMINNM */
-            gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x9: /* FMLS */
-             /* As usual for ARM, separate negation for fused multiply-add */
-            tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
-            read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-            gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
-                                       fpst);
-            break;
-        case 0xa: /* FSUB */
-            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xe: /* FMIN */
-            gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xf: /* FRSQRTS */
-            gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x13: /* FMUL */
-            gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x14: /* FCMGE */
-            gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x15: /* FACGE */
-            gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x17: /* FDIV */
-            gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x1a: /* FABD */
-            gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-            tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
-            break;
-        case 0x1c: /* FCMGT */
-            gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x1d: /* FACGT */
-            gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        default:
-            fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
-                    __func__, insn, fpopcode, s->pc);
-            g_assert_not_reached();
+            read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
+            read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
+            tcg_res[pass] = tcg_temp_new_i32();
+
+            switch (fpopcode) {
+            case 0x10: /* FMAXNMP */
+                gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
+                                           fpst);
+                break;
+            case 0x12: /* FADDP */
+                gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x16: /* FMAXP */
+                gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x18: /* FMINNMP */
+                gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
+                                           fpst);
+                break;
+            case 0x1e: /* FMINP */
+                gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+        }
+
+        for (pass = 0; pass < maxpass; pass++) {
+            write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
+            tcg_temp_free_i32(tcg_res[pass]);
         }
 
-        write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
-        tcg_temp_free_i32(tcg_res);
         tcg_temp_free_i32(tcg_op1);
         tcg_temp_free_i32(tcg_op2);
+
+    } else {
+        for (pass = 0; pass < elements; pass++) {
+            TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+            TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+            TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+            read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
+            read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+
+            switch (fpopcode) {
+            case 0x0: /* FMAXNM */
+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x1: /* FMLA */
+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                           fpst);
+                break;
+            case 0x2: /* FADD */
+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x3: /* FMULX */
+                gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x4: /* FCMEQ */
+                gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x6: /* FMAX */
+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x7: /* FRECPS */
+                gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x8: /* FMINNM */
+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x9: /* FMLS */
+                /* As usual for ARM, separate negation for fused multiply-add */
+                tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
+                read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+                gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
+                                           fpst);
+                break;
+            case 0xa: /* FSUB */
+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xe: /* FMIN */
+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xf: /* FRSQRTS */
+                gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x13: /* FMUL */
+                gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x14: /* FCMGE */
+                gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x15: /* FACGE */
+                gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x17: /* FDIV */
+                gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x1a: /* FABD */
+                gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+                tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
+                break;
+            case 0x1c: /* FCMGT */
+                gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x1d: /* FACGT */
+                gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
+                        __func__, insn, fpopcode, s->pc);
+                g_assert_not_reached();
+            }
+
+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+            tcg_temp_free_i32(tcg_res);
+            tcg_temp_free_i32(tcg_op1);
+            tcg_temp_free_i32(tcg_op2);
+        }
     }
 
     tcg_temp_free_ptr(fpst);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

The helpers use the new re-factored muladd support in SoftFloat for
the float16 work.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180227143852.11175-15-alex.bennee@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 66 insertions(+), 16 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.

Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-16-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    | 10 ++++++++++
 target/arm/helper-a64.c    | 46 +++++++++++++++++++++++++++++++++++++++++++++-
 target/arm/translate-a64.c | 26 +++++++++++++++++++++-----
 3 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
 DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
 DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
+DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
+DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(max)
 ADVSIMD_HALFOP(minnum)
 ADVSIMD_HALFOP(maxnum)
 
+#define ADVSIMD_TWOHALFOP(name)                                         \
+uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
+{ \
+    float16  a1, a2, b1, b2;                        \
+    uint32_t r1, r2;                                \
+    float_status *fpst = fpstp;                     \
+    a1 = extract32(two_a, 0, 16);                   \
+    a2 = extract32(two_a, 16, 16);                  \
+    b1 = extract32(two_b, 0, 16);                   \
+    b2 = extract32(two_b, 16, 16);                  \
+    r1 = float16_ ## name(a1, b1, fpst);            \
+    r2 = float16_ ## name(a2, b2, fpst);            \
+    return deposit32(r1, 16, 16, r2);               \
+}
+
+ADVSIMD_TWOHALFOP(add)
+ADVSIMD_TWOHALFOP(sub)
+ADVSIMD_TWOHALFOP(mul)
+ADVSIMD_TWOHALFOP(div)
+ADVSIMD_TWOHALFOP(min)
+ADVSIMD_TWOHALFOP(max)
+ADVSIMD_TWOHALFOP(minnum)
+ADVSIMD_TWOHALFOP(maxnum)
+
 /* Data processing - scalar floating-point and advanced SIMD */
-float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+static float16 float16_mulx(float16 a, float16 b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
     return float16_mul(a, b, fpst);
 }
 
+ADVSIMD_HALFOP(mulx)
+ADVSIMD_TWOHALFOP(mulx)
+
 /* fused multiply-accumulate */
 float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
 {
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
     return float16_muladd(a, b, c, 0, fpst);
 }
 
+uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
+                                  uint32_t two_c, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16  a1, a2, b1, b2, c1, c2;
+    uint32_t r1, r2;
+    a1 = extract32(two_a, 0, 16);
+    a2 = extract32(two_a, 16, 16);
+    b1 = extract32(two_b, 0, 16);
+    b2 = extract32(two_b, 16, 16);
+    c1 = extract32(two_c, 0, 16);
+    c2 = extract32(two_c, 16, 16);
+    r1 = float16_muladd(a1, b1, c1, 0, fpst);
+    r2 = float16_muladd(a2, b2, c2, 0, fpst);
+    return deposit32(r1, 16, 16, r2);
+}
+
 /*
  * Floating point comparisons produce an integer result. Softfloat
  * routines return float_relation types which we convert to the 0/-1
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                          * multiply-add */
                         tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
                     }
-                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
-                                               tcg_res, fpst);
+                    if (is_scalar) {
+                        gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
+                                                   tcg_res, fpst);
+                    } else {
+                        gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
+                                                    tcg_res, fpst);
+                    }
                     break;
                 case 2:
                     if (opcode == 0x5) {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                 switch (size) {
                 case 1:
                     if (u) {
-                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
-                                                 fpst);
+                        if (is_scalar) {
+                            gen_helper_advsimd_mulxh(tcg_res, tcg_op,
+                                                     tcg_idx, fpst);
+                        } else {
+                            gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
+                                                      tcg_idx, fpst);
+                        }
                     } else {
-                        g_assert_not_reached();
+                        if (is_scalar) {
+                            gen_helper_advsimd_mulh(tcg_res, tcg_op,
+                                                    tcg_idx, fpst);
+                        } else {
+                            gen_helper_advsimd_mul2h(tcg_res, tcg_op,
+                                                     tcg_idx, fpst);
+                        }
                     }
                     break;
                 case 2:
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This actually covers two different sections of the encoding table:

Advanced SIMD scalar two-register miscellaneous FP16
   Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

This adds the full range of half-precision floating point to integral
instructions.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-18-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |   2 +
 target/arm/helper-a64.c    |  22 ++++++++
 target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++++--
 3 files changed, 142 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr)
 DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr)
 DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
 DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
+DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
     int compare = float16_compare(f0, f1, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_greater);
 }
+
+/* round to integral */
+float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+{
+    return float16_round_to_int(x, fp_status);
+}
+
+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+{
+    int old_flags = get_float_exception_flags(fp_status), new_flags;
+    float16 ret;
+
+    ret = float16_round_to_int(x, fp_status);
+
+    /* Suppress any inexact exceptions the conversion produced */
+    if (!(old_flags & float_flag_inexact)) {
+        new_flags = get_float_exception_flags(fp_status);
+        set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
+    }
+
+    return ret;
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
 {
-    int fpop, opcode, a;
+    int fpop, opcode, a, u;
+    int rn, rd;
+    bool is_q;
+    bool is_scalar;
+    bool only_in_vector = false;
+
+    int pass;
+    TCGv_i32 tcg_rmode = NULL;
+    TCGv_ptr tcg_fpstatus = NULL;
+    bool need_rmode = false;
+    int rmode;
 
     if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
         unallocated_encoding(s);
         return;
     }
 
-    if (!fp_access_check(s)) {
-        return;
-    }
+    rd = extract32(insn, 0, 5);
+    rn = extract32(insn, 5, 5);
 
-    opcode = extract32(insn, 12, 4);
     a = extract32(insn, 23, 1);
+    u = extract32(insn, 29, 1);
+    is_scalar = extract32(insn, 28, 1);
+    is_q = extract32(insn, 30, 1);
+
+    opcode = extract32(insn, 12, 5);
     fpop = deposit32(opcode, 5, 1, a);
+    fpop = deposit32(fpop, 6, 1, u);
 
     switch (fpop) {
+    case 0x18: /* FRINTN */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_TIEEVEN;
+        break;
+    case 0x19: /* FRINTM */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_NEGINF;
+        break;
+    case 0x38: /* FRINTP */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_POSINF;
+        break;
+    case 0x39: /* FRINTZ */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_ZERO;
+        break;
+    case 0x58: /* FRINTA */
+        need_rmode = true;
+        only_in_vector = true;
+        rmode = FPROUNDING_TIEAWAY;
+        break;
+    case 0x59: /* FRINTX */
+    case 0x79: /* FRINTI */
+        only_in_vector = true;
+        /* current rounding mode */
+        break;
     default:
         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
         g_assert_not_reached();
     }
 
+
+    /* Check additional constraints for the scalar encoding */
+    if (is_scalar) {
+        if (!is_q) {
+            unallocated_encoding(s);
+            return;
+        }
+        /* FRINTxx is only in the vector form */
+        if (only_in_vector) {
+            unallocated_encoding(s);
+            return;
+        }
+    }
+
+    if (!fp_access_check(s)) {
+        return;
+    }
+
+    if (need_rmode) {
+        tcg_fpstatus = get_fpstatus_ptr(true);
+    }
+
+    if (need_rmode) {
+        tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+    }
+
+    if (is_scalar) {
+        /* no operations yet */
+    } else {
+        for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
+            TCGv_i32 tcg_op = tcg_temp_new_i32();
+            TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+            read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
+
+            switch (fpop) {
+            case 0x18: /* FRINTN */
+            case 0x19: /* FRINTM */
+            case 0x38: /* FRINTP */
+            case 0x39: /* FRINTZ */
+            case 0x58: /* FRINTA */
+            case 0x79: /* FRINTI */
+                gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
+                break;
+            case 0x59: /* FRINTX */
+                gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+
+            write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+
+            tcg_temp_free_i32(tcg_res);
+            tcg_temp_free_i32(tcg_op);
+        }
+
+        clear_vec_high(s, is_q, rd);
+    }
+
+    if (tcg_rmode) {
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+        tcg_temp_free_i32(tcg_rmode);
+    }
+
+    if (tcg_fpstatus) {
+        tcg_temp_free_ptr(tcg_fpstatus);
+    }
 }
 
 /* AdvSIMD scalar x indexed element
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This covers all the floating point convert operations.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  2 ++
 target/arm/helper-a64.c    | 32 +++++++++++++++++
 target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 118 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
 DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
 DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
 DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
+DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 
     return ret;
 }
+
+/*
+ * Half-precision floating point conversion functions
+ *
+ * There are a multitude of conversion functions with various
+ * different rounding modes. This is dealt with by the calling code
+ * setting the mode appropriately before calling the helper.
+ */
+
+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    /* Invalid if we are passed a NaN */
+    if (float16_is_any_nan(a)) {
+        float_raise(float_flag_invalid, fpst);
+        return 0;
+    }
+    return float16_to_int16(a, fpst);
+}
+
+uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+{
+    float_status *fpst = fpstp;
+
+    /* Invalid if we are passed a NaN */
+    if (float16_is_any_nan(a)) {
+        float_raise(float_flag_invalid, fpst);
+        return 0;
+    }
+    return float16_to_uint16(a, fpst);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
         only_in_vector = true;
         /* current rounding mode */
         break;
+    case 0x1a: /* FCVTNS */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEEVEN;
+        break;
+    case 0x1b: /* FCVTMS */
+        need_rmode = true;
+        rmode = FPROUNDING_NEGINF;
+        break;
+    case 0x1c: /* FCVTAS */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEAWAY;
+        break;
+    case 0x3a: /* FCVTPS */
+        need_rmode = true;
+        rmode = FPROUNDING_POSINF;
+        break;
+    case 0x3b: /* FCVTZS */
+        need_rmode = true;
+        rmode = FPROUNDING_ZERO;
+        break;
+    case 0x5a: /* FCVTNU */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEEVEN;
+        break;
+    case 0x5b: /* FCVTMU */
+        need_rmode = true;
+        rmode = FPROUNDING_NEGINF;
+        break;
+    case 0x5c: /* FCVTAU */
+        need_rmode = true;
+        rmode = FPROUNDING_TIEAWAY;
+        break;
+    case 0x7a: /* FCVTPU */
+        need_rmode = true;
+        rmode = FPROUNDING_POSINF;
+        break;
+    case 0x7b: /* FCVTZU */
+        need_rmode = true;
+        rmode = FPROUNDING_ZERO;
+        break;
     default:
         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     }
 
     if (is_scalar) {
-        /* no operations yet */
+        TCGv_i32 tcg_op = tcg_temp_new_i32();
+        TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
+
+        switch (fpop) {
+        case 0x1a: /* FCVTNS */
+        case 0x1b: /* FCVTMS */
+        case 0x1c: /* FCVTAS */
+        case 0x3a: /* FCVTPS */
+        case 0x3b: /* FCVTZS */
+            gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
+            break;
+        case 0x5a: /* FCVTNU */
+        case 0x5b: /* FCVTMU */
+        case 0x5c: /* FCVTAU */
+        case 0x7a: /* FCVTPU */
+        case 0x7b: /* FCVTZU */
+            gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        /* limit any sign extension going on */
+        tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
+        write_fp_sreg(s, rd, tcg_res);
+
+        tcg_temp_free_i32(tcg_res);
+        tcg_temp_free_i32(tcg_op);
     } else {
         for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
             TCGv_i32 tcg_op = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
             read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
 
             switch (fpop) {
+            case 0x1a: /* FCVTNS */
+            case 0x1b: /* FCVTMS */
+            case 0x1c: /* FCVTAS */
+            case 0x3a: /* FCVTPS */
+            case 0x3b: /* FCVTZS */
+                gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
+                break;
+            case 0x5a: /* FCVTNU */
+            case 0x5b: /* FCVTMU */
+            case 0x5c: /* FCVTAU */
+            case 0x7a: /* FCVTPU */
+            case 0x7b: /* FCVTZU */
+                gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
+                break;
             case 0x18: /* FRINTN */
             case 0x19: /* FRINTM */
             case 0x38: /* FRINTP */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 57 insertions(+), 23 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
                                    bool is_scalar, bool is_u, bool is_q,
                                    int size, int rn, int rd)
 {
-    bool is_double = (size == 3);
+    bool is_double = (size == MO_64);
     TCGv_ptr fpst;
 
     if (!fp_access_check(s)) {
         return;
     }
 
-    fpst = get_fpstatus_ptr(false);
+    fpst = get_fpstatus_ptr(size == MO_16);
 
     if (is_double) {
         TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
         bool swap = false;
         int pass, maxpasses;
 
-        switch (opcode) {
-        case 0x2e: /* FCMLT (zero) */
-            swap = true;
-            /* fall through */
-        case 0x2c: /* FCMGT (zero) */
-            genfn = gen_helper_neon_cgt_f32;
-            break;
-        case 0x2d: /* FCMEQ (zero) */
-            genfn = gen_helper_neon_ceq_f32;
-            break;
-        case 0x6d: /* FCMLE (zero) */
-            swap = true;
-            /* fall through */
-        case 0x6c: /* FCMGE (zero) */
-            genfn = gen_helper_neon_cge_f32;
-            break;
-        default:
-            g_assert_not_reached();
+        if (size == MO_16) {
+            switch (opcode) {
+            case 0x2e: /* FCMLT (zero) */
+                swap = true;
+                /* fall through */
+            case 0x2c: /* FCMGT (zero) */
+                genfn = gen_helper_advsimd_cgt_f16;
+                break;
+            case 0x2d: /* FCMEQ (zero) */
+                genfn = gen_helper_advsimd_ceq_f16;
+                break;
+            case 0x6d: /* FCMLE (zero) */
+                swap = true;
+                /* fall through */
+            case 0x6c: /* FCMGE (zero) */
+                genfn = gen_helper_advsimd_cge_f16;
+                break;
+            default:
+                g_assert_not_reached();
+            }
+        } else {
+            switch (opcode) {
+            case 0x2e: /* FCMLT (zero) */
+                swap = true;
+                /* fall through */
+            case 0x2c: /* FCMGT (zero) */
+                genfn = gen_helper_neon_cgt_f32;
+                break;
+            case 0x2d: /* FCMEQ (zero) */
+                genfn = gen_helper_neon_ceq_f32;
+                break;
+            case 0x6d: /* FCMLE (zero) */
+                swap = true;
+                /* fall through */
+            case 0x6c: /* FCMGE (zero) */
+                genfn = gen_helper_neon_cge_f32;
+                break;
+            default:
+                g_assert_not_reached();
+            }
         }
 
         if (is_scalar) {
             maxpasses = 1;
         } else {
-            maxpasses = is_q ? 4 : 2;
+            int vector_size = 8 << is_q;
+            maxpasses = vector_size >> size;
         }
 
         for (pass = 0; pass < maxpasses; pass++) {
-            read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
+            read_vec_element_i32(s, tcg_op, rn, pass, size);
             if (swap) {
                 genfn(tcg_res, tcg_zero, tcg_op, fpst);
             } else {
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
             if (is_scalar) {
                 write_fp_sreg(s, rd, tcg_res);
             } else {
-                write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
+                write_vec_element_i32(s, tcg_res, rd, pass, size);
             }
         }
         tcg_temp_free_i32(tcg_res);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     fpop = deposit32(opcode, 5, 1, a);
     fpop = deposit32(fpop, 6, 1, u);
 
+    rd = extract32(insn, 0, 5);
+    rn = extract32(insn, 5, 5);
+
     switch (fpop) {
+    break;
+    case 0x2c: /* FCMGT (zero) */
+    case 0x2d: /* FCMEQ (zero) */
+    case 0x2e: /* FCMLT (zero) */
+    case 0x6c: /* FCMGE (zero) */
+    case 0x6d: /* FCMLE (zero) */
+        handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
+        return;
     case 0x18: /* FRINTN */
         need_rmode = true;
         only_in_vector = true;
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

I've re-factored the handle_simd_intfp_conv helper to properly handle
half-precision as well as call plain conversion helpers when we are
not doing fixed point conversion.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  10 ++++
 target/arm/helper.c        |   4 ++
 target/arm/translate-a64.c | 122 ++++++++++++++++++++++++++++++++++-----------
 3 files changed, 108 insertions(+), 28 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
 DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
 DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
 
+DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
 DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
 DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
+DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
 DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
 DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
 
+DEF_HELPER_2(vfp_touih, i32, f16, ptr)
 DEF_HELPER_2(vfp_touis, i32, f32, ptr)
 DEF_HELPER_2(vfp_touid, i32, f64, ptr)
+DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
 DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
 DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
+DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
 DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
 DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
+DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
 DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
 DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
 
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
 DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
 DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
 DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
+DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
+DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
 
 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
 DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
 
+FLOAT_CONVS(si, h, 16, )
 FLOAT_CONVS(si, s, 32, )
 FLOAT_CONVS(si, d, 64, )
+FLOAT_CONVS(ui, h, 16, u)
 FLOAT_CONVS(ui, s, 32, u)
 FLOAT_CONVS(ui, d, 64, u)
 
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
 VFP_CONV_FIX(uh, s, 32, 32, uint16)
 VFP_CONV_FIX(ul, s, 32, 32, uint32)
 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
+VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
+VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
 #undef VFP_CONV_FIX
 #undef VFP_CONV_FIX_FLOAT
 #undef VFP_CONV_FLOAT_FIX_ROUND
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
                                    int elements, int is_signed,
                                    int fracbits, int size)
 {
-    bool is_double = size == 3 ? true : false;
-    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
-    TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
-    TCGv_i64 tcg_int = tcg_temp_new_i64();
+    TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
+    TCGv_i32 tcg_shift = NULL;
+
     TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
     int pass;
 
-    for (pass = 0; pass < elements; pass++) {
-        read_vec_element(s, tcg_int, rn, pass, mop);
+    if (fracbits || size == MO_64) {
+        tcg_shift = tcg_const_i32(fracbits);
+    }
+
+    if (size == MO_64) {
+        TCGv_i64 tcg_int64 = tcg_temp_new_i64();
+        TCGv_i64 tcg_double = tcg_temp_new_i64();
+
+        for (pass = 0; pass < elements; pass++) {
+            read_vec_element(s, tcg_int64, rn, pass, mop);
 
-        if (is_double) {
-            TCGv_i64 tcg_double = tcg_temp_new_i64();
             if (is_signed) {
-                gen_helper_vfp_sqtod(tcg_double, tcg_int,
+                gen_helper_vfp_sqtod(tcg_double, tcg_int64,
                                      tcg_shift, tcg_fpst);
             } else {
-                gen_helper_vfp_uqtod(tcg_double, tcg_int,
+                gen_helper_vfp_uqtod(tcg_double, tcg_int64,
                                      tcg_shift, tcg_fpst);
             }
             if (elements == 1) {
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
             } else {
                 write_vec_element(s, tcg_double, rd, pass, MO_64);
             }
-            tcg_temp_free_i64(tcg_double);
-        } else {
-            TCGv_i32 tcg_single = tcg_temp_new_i32();
-            if (is_signed) {
-                gen_helper_vfp_sqtos(tcg_single, tcg_int,
-                                     tcg_shift, tcg_fpst);
-            } else {
-                gen_helper_vfp_uqtos(tcg_single, tcg_int,
-                                     tcg_shift, tcg_fpst);
-            }
-            if (elements == 1) {
-                write_fp_sreg(s, rd, tcg_single);
-            } else {
-                write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
-            }
-            tcg_temp_free_i32(tcg_single);
         }
+
+        tcg_temp_free_i64(tcg_int64);
+        tcg_temp_free_i64(tcg_double);
+
+    } else {
+        TCGv_i32 tcg_int32 = tcg_temp_new_i32();
+        TCGv_i32 tcg_float = tcg_temp_new_i32();
+
+        for (pass = 0; pass < elements; pass++) {
+            read_vec_element_i32(s, tcg_int32, rn, pass, mop);
+
+            switch (size) {
+            case MO_32:
+                if (fracbits) {
+                    if (is_signed) {
+                        gen_helper_vfp_sltos(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_ultos(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    }
+                } else {
+                    if (is_signed) {
+                        gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
+                    }
+                }
+                break;
+            case MO_16:
+                if (fracbits) {
+                    if (is_signed) {
+                        gen_helper_vfp_sltoh(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_ultoh(tcg_float, tcg_int32,
+                                             tcg_shift, tcg_fpst);
+                    }
+                } else {
+                    if (is_signed) {
+                        gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
+                    } else {
+                        gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
+                    }
+                }
+                break;
+            default:
+                g_assert_not_reached();
+            }
+
+            if (elements == 1) {
+                write_fp_sreg(s, rd, tcg_float);
+            } else {
+                write_vec_element_i32(s, tcg_float, rd, pass, size);
+            }
+        }
+
+        tcg_temp_free_i32(tcg_int32);
+        tcg_temp_free_i32(tcg_float);
     }
 
-    tcg_temp_free_i64(tcg_int);
     tcg_temp_free_ptr(tcg_fpst);
-    tcg_temp_free_i32(tcg_shift);
+    if (tcg_shift) {
+        tcg_temp_free_i32(tcg_shift);
+    }
 
     clear_vec_high(s, elements << size == 16, rd);
 }
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     rn = extract32(insn, 5, 5);
 
     switch (fpop) {
+    case 0x1d: /* SCVTF */
+    case 0x5d: /* UCVTF */
+    {
+        int elements;
+
+        if (is_scalar) {
+            elements = 1;
+        } else {
+            elements = (is_q ? 8 : 4);
+        }
+
+        if (!fp_access_check(s)) {
+            return;
+        }
+        handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
+        return;
+    }
     break;
     case 0x2c: /* FCMGT (zero) */
     case 0x2d: /* FCMEQ (zero) */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

From: Alex Bennée <alex.bennee@linaro.org>

It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-23-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h |   1 +
 target/arm/helper.c | 226 +++++++++++++++++++++++++++++-----------------------
 2 files changed, 129 insertions(+), 98 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
 
 DEF_HELPER_3(recps_f32, f32, f32, f32, env)
 DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
+DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
 DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
  * int->float conversions at run-time.  */
 #define float64_256 make_float64(0x4070000000000000LL)
 #define float64_512 make_float64(0x4080000000000000LL)
+#define float16_maxnorm make_float16(0x7bff)
 #define float32_maxnorm make_float32(0x7f7fffff)
 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
 
 /* Reciprocal functions
  *
  * The algorithm that must be used to calculate the estimate
- * is specified by the ARM ARM, see FPRecipEstimate()
+ * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
  */
 
-static float64 recip_estimate(float64 a, float_status *real_fp_status)
+/* See RecipEstimate()
+ *
+ * input is a 9 bit fixed point number
+ * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
+ * result range 256 .. 511 for a number from 1.0 to 511/256.
+ */
+
+static int recip_estimate(int input)
 {
-    /* These calculations mustn't set any fp exception flags,
-     * so we use a local copy of the fp_status.
-     */
-    float_status dummy_status = *real_fp_status;
-    float_status *s = &dummy_status;
-    /* q = (int)(a * 512.0) */
-    float64 q = float64_mul(float64_512, a, s);
-    int64_t q_int = float64_to_int64_round_to_zero(q, s);
-
-    /* r = 1.0 / (((double)q + 0.5) / 512.0) */
-    q = int64_to_float64(q_int, s);
-    q = float64_add(q, float64_half, s);
-    q = float64_div(q, float64_512, s);
-    q = float64_div(float64_one, q, s);
-
-    /* s = (int)(256.0 * r + 0.5) */
-    q = float64_mul(q, float64_256, s);
-    q = float64_add(q, float64_half, s);
-    q_int = float64_to_int64_round_to_zero(q, s);
-
-    /* return (double)s / 256.0 */
-    return float64_div(int64_to_float64(q_int, s), float64_256, s);
+    int a, b, r;
+    assert(256 <= input && input < 512);
+    a = (input * 2) + 1;
+    b = (1 << 19) / a;
+    r = (b + 1) >> 1;
+    assert(256 <= r && r < 512);
+    return r;
 }
 
-/* Common wrapper to call recip_estimate */
-static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
-{
-    uint64_t val64 = float64_val(num);
-    uint64_t frac = extract64(val64, 0, 52);
-    int64_t exp = extract64(val64, 52, 11);
-    uint64_t sbit;
-    float64 scaled, estimate;
+/*
+ * Common wrapper to call recip_estimate
+ *
+ * The parameters are exponent and 64 bit fraction (without implicit
+ * bit) where the binary point is nominally at bit 52. Returns a
+ * float64 which can then be rounded to the appropriate size by the
+ * callee.
+ */
 
-    /* Generate the scaled number for the estimate function */
-    if (exp == 0) {
+static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
+{
+    uint32_t scaled, estimate;
+    uint64_t result_frac;
+    int result_exp;
+
+    /* Handle sub-normals */
+    if (*exp == 0) {
         if (extract64(frac, 51, 1) == 0) {
-            exp = -1;
-            frac = extract64(frac, 0, 50) << 2;
+            *exp = -1;
+            frac <<= 2;
         } else {
-            frac = extract64(frac, 0, 51) << 1;
+            frac <<= 1;
         }
     }
 
-    /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
-    scaled = make_float64((0x3feULL << 52)
-                          | extract64(frac, 44, 8) << 44);
+    /* scaled = UInt('1':fraction<51:44>) */
+    scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
+    estimate = recip_estimate(scaled);
 
-    estimate = recip_estimate(scaled, fpst);
-
-    /* Build new result */
-    val64 = float64_val(estimate);
-    sbit = 0x8000000000000000ULL & val64;
-    exp = off - exp;
-    frac = extract64(val64, 0, 52);
-
-    if (exp == 0) {
-        frac = 1ULL << 51 | extract64(frac, 1, 51);
-    } else if (exp == -1) {
-        frac = 1ULL << 50 | extract64(frac, 2, 50);
-        exp = 0;
+    result_exp = exp_off - *exp;
+    result_frac = deposit64(0, 44, 8, estimate);
+    if (result_exp == 0) {
+        result_frac = deposit64(result_frac >> 1, 51, 1, 1);
+    } else if (result_exp == -1) {
+        result_frac = deposit64(result_frac >> 2, 50, 2, 1);
+        result_exp = 0;
     }
 
-    return make_float64(sbit | (exp << 52) | frac);
+    *exp = result_exp;
+
+    return result_frac;
 }
 
 static bool round_to_inf(float_status *fpst, bool sign_bit)
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
     g_assert_not_reached();
 }
 
+float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    float16 f16 = float16_squash_input_denormal(input, fpst);
+    uint32_t f16_val = float16_val(f16);
+    uint32_t f16_sign = float16_is_neg(f16);
+    int f16_exp = extract32(f16_val, 10, 5);
+    uint32_t f16_frac = extract32(f16_val, 0, 10);
+    uint64_t f64_frac;
+
+    if (float16_is_any_nan(f16)) {
+        float16 nan = f16;
+        if (float16_is_signaling_nan(f16, fpst)) {
+            float_raise(float_flag_invalid, fpst);
+            nan = float16_maybe_silence_nan(f16, fpst);
+        }
+        if (fpst->default_nan_mode) {
+            nan =  float16_default_nan(fpst);
+        }
+        return nan;
+    } else if (float16_is_infinity(f16)) {
+        return float16_set_sign(float16_zero, float16_is_neg(f16));
+    } else if (float16_is_zero(f16)) {
+        float_raise(float_flag_divbyzero, fpst);
+        return float16_set_sign(float16_infinity, float16_is_neg(f16));
+    } else if (float16_abs(f16) < (1 << 8)) {
+        /* Abs(value) < 2.0^-16 */
+        float_raise(float_flag_overflow | float_flag_inexact, fpst);
+        if (round_to_inf(fpst, f16_sign)) {
+            return float16_set_sign(float16_infinity, f16_sign);
+        } else {
+            return float16_set_sign(float16_maxnorm, f16_sign);
+        }
+    } else if (f16_exp >= 29 && fpst->flush_to_zero) {
+        float_raise(float_flag_underflow, fpst);
+        return float16_set_sign(float16_zero, float16_is_neg(f16));
+    }
+
+    f64_frac = call_recip_estimate(&f16_exp, 29,
+                                   ((uint64_t) f16_frac) << (52 - 10));
+
+    /* result = sign : result_exp<4:0> : fraction<51:42> */
+    f16_val = deposit32(0, 15, 1, f16_sign);
+    f16_val = deposit32(f16_val, 10, 5, f16_exp);
+    f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
+    return make_float16(f16_val);
+}
+
 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
 {
     float_status *fpst = fpstp;
     float32 f32 = float32_squash_input_denormal(input, fpst);
     uint32_t f32_val = float32_val(f32);
-    uint32_t f32_sbit = 0x80000000ULL & f32_val;
-    int32_t f32_exp = extract32(f32_val, 23, 8);
+    bool f32_sign = float32_is_neg(f32);
+    int f32_exp = extract32(f32_val, 23, 8);
     uint32_t f32_frac = extract32(f32_val, 0, 23);
-    float64 f64, r64;
-    uint64_t r64_val;
-    int64_t r64_exp;
-    uint64_t r64_frac;
+    uint64_t f64_frac;
 
     if (float32_is_any_nan(f32)) {
         float32 nan = f32;
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
     } else if (float32_is_zero(f32)) {
         float_raise(float_flag_divbyzero, fpst);
         return float32_set_sign(float32_infinity, float32_is_neg(f32));
-    } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
+    } else if (float32_abs(f32) < (1ULL << 21)) {
         /* Abs(value) < 2.0^-128 */
         float_raise(float_flag_overflow | float_flag_inexact, fpst);
-        if (round_to_inf(fpst, f32_sbit)) {
-            return float32_set_sign(float32_infinity, float32_is_neg(f32));
+        if (round_to_inf(fpst, f32_sign)) {
+            return float32_set_sign(float32_infinity, f32_sign);
         } else {
-            return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
+            return float32_set_sign(float32_maxnorm, f32_sign);
         }
     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
         float_raise(float_flag_underflow, fpst);
         return float32_set_sign(float32_zero, float32_is_neg(f32));
     }
 
+    f64_frac = call_recip_estimate(&f32_exp, 253,
+                                   ((uint64_t) f32_frac) << (52 - 23));
 
-    f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
-    r64 = call_recip_estimate(f64, 253, fpst);
-    r64_val = float64_val(r64);
-    r64_exp = extract64(r64_val, 52, 11);
-    r64_frac = extract64(r64_val, 0, 52);
-
-    /* result = sign : result_exp<7:0> : fraction<51:29>; */
-    return make_float32(f32_sbit |
-                        (r64_exp & 0xff) << 23 |
-                        extract64(r64_frac, 29, 24));
+    /* result = sign : result_exp<7:0> : fraction<51:29> */
+    f32_val = deposit32(0, 31, 1, f32_sign);
+    f32_val = deposit32(f32_val, 23, 8, f32_exp);
+    f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
+    return make_float32(f32_val);
 }
 
 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
     float_status *fpst = fpstp;
     float64 f64 = float64_squash_input_denormal(input, fpst);
     uint64_t f64_val = float64_val(f64);
-    uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
-    int64_t f64_exp = extract64(f64_val, 52, 11);
-    float64 r64;
-    uint64_t r64_val;
-    int64_t r64_exp;
-    uint64_t r64_frac;
+    bool f64_sign = float64_is_neg(f64);
+    int f64_exp = extract64(f64_val, 52, 11);
+    uint64_t f64_frac = extract64(f64_val, 0, 52);
 
     /* Deal with any special cases */
     if (float64_is_any_nan(f64)) {
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
         /* Abs(value) < 2.0^-1024 */
         float_raise(float_flag_overflow | float_flag_inexact, fpst);
-        if (round_to_inf(fpst, f64_sbit)) {
-            return float64_set_sign(float64_infinity, float64_is_neg(f64));
+        if (round_to_inf(fpst, f64_sign)) {
+            return float64_set_sign(float64_infinity, f64_sign);
         } else {
-            return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
+            return float64_set_sign(float64_maxnorm, f64_sign);
         }
     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
         float_raise(float_flag_underflow, fpst);
         return float64_set_sign(float64_zero, float64_is_neg(f64));
     }
 
-    r64 = call_recip_estimate(f64, 2045, fpst);
-    r64_val = float64_val(r64);
-    r64_exp = extract64(r64_val, 52, 11);
-    r64_frac = extract64(r64_val, 0, 52);
+    f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
 
-    /* result = sign : result_exp<10:0> : fraction<51:0> */
-    return make_float64(f64_sbit |
-                        ((r64_exp & 0x7ff) << 52) |
-                        r64_frac);
+    /* result = sign : result_exp<10:0> : fraction<51:0>; */
+    f64_val = deposit64(0, 63, 1, f64_sign);
+    f64_val = deposit64(f64_val, 52, 11, f64_exp);
+    f64_val = deposit64(f64_val, 0, 52, f64_frac);
+    return make_float64(f64_val);
 }
 
 /* The algorithm that must be used to calculate the estimate
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
 
 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
 {
-    float_status *s = fpstp;
-    float64 f64;
+    /* float_status *s = fpstp; */
+    int input, estimate;
 
     if ((a & 0x80000000) == 0) {
         return 0xffffffff;
     }
 
-    f64 = make_float64((0x3feULL << 52)
-                       | ((int64_t)(a & 0x7fffffff) << 21));
+    input = extract32(a, 23, 9);
+    estimate = recip_estimate(input);
 
-    f64 = recip_estimate(f64, s);
-
-    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
+    return deposit32(0, (32 - 9), 9, estimate);
 }
 
 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Now we have added f16 during the re-factoring we can simply call the
helper.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 8 ++++++++
 1 file changed, 8 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

We go with the localised helper.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-25-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  1 +
 target/arm/helper-a64.c    | 29 +++++++++++++++++++++++++++++
 target/arm/translate-a64.c |  4 ++++
 3 files changed, 34 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
 DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
 DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
 DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
+DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
 DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
 DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 }
 
 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
+float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+{
+    float_status *fpst = fpstp;
+    uint16_t val16, sbit;
+    int16_t exp;
+
+    if (float16_is_any_nan(a)) {
+        float16 nan = a;
+        if (float16_is_signaling_nan(a, fpst)) {
+            float_raise(float_flag_invalid, fpst);
+            nan = float16_maybe_silence_nan(a, fpst);
+        }
+        if (fpst->default_nan_mode) {
+            nan = float16_default_nan(fpst);
+        }
+        return nan;
+    }
+
+    val16 = float16_val(a);
+    sbit = 0x8000 & val16;
+    exp = extract32(val16, 10, 5);
+
+    if (exp == 0) {
+        return make_float16(deposit32(sbit, 10, 5, 0x1e));
+    } else {
+        return make_float16(deposit32(sbit, 10, 5, ~exp));
+    }
+}
+
 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
 {
     float_status *fpst = fpstp;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
         handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
         return;
     case 0x3d: /* FRECPE */
+    case 0x3f: /* FRECPX */
         break;
     case 0x18: /* FRINTN */
         need_rmode = true;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
         case 0x3d: /* FRECPE */
             gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
             break;
+        case 0x3f: /* FRECPX */
+            gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
+            break;
         case 0x5a: /* FCVTNU */
         case 0x5b: /* FCVTMU */
         case 0x5c: /* FCVTAU */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  1 +
 target/arm/helper-a64.c    | 13 +++++++++++++
 target/arm/translate-a64.c |  5 +++++
 3 files changed, 19 insertions(+)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
 DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
 DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
 DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
+DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
     }
     return float16_to_uint16(a, fpst);
 }
+
+/*
+ * Square Root and Reciprocal square root
+ */
+
+float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+{
+    float_status *s = fpstp;
+
+    return float16_sqrt(a, s);
+}
+
+
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     case 0x6f: /* FNEG */
         need_fpst = false;
         break;
+    case 0x7f: /* FSQRT (vector) */
+        break;
     default:
         fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
             case 0x6f: /* FNEG */
                 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
                 break;
+            case 0x7f: /* FSQRT */
+                gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
+                break;
             default:
                 g_assert_not_reached();
             }
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Much like recpe the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-27-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h |   1 +
 target/arm/helper.c | 221 ++++++++++++++++++++++++----------------------------
 2 files changed, 104 insertions(+), 118 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
 DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
+DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
 DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
 DEF_HELPER_2(recpe_u32, i32, i32, ptr)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
 /* The algorithm that must be used to calculate the estimate
  * is specified by the ARM ARM.
  */
-static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
+
+static int do_recip_sqrt_estimate(int a)
 {
-    /* These calculations mustn't set any fp exception flags,
-     * so we use a local copy of the fp_status.
-     */
-    float_status dummy_status = *real_fp_status;
-    float_status *s = &dummy_status;
-    float64 q;
-    int64_t q_int;
+    int b, estimate;
 
-    if (float64_lt(a, float64_half, s)) {
-        /* range 0.25 <= a < 0.5 */
-
-        /* a in units of 1/512 rounded down */
-        /* q0 = (int)(a * 512.0);  */
-        q = float64_mul(float64_512, a, s);
-        q_int = float64_to_int64_round_to_zero(q, s);
-
-        /* reciprocal root r */
-        /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
-        q = int64_to_float64(q_int, s);
-        q = float64_add(q, float64_half, s);
-        q = float64_div(q, float64_512, s);
-        q = float64_sqrt(q, s);
-        q = float64_div(float64_one, q, s);
+    assert(128 <= a && a < 512);
+    if (a < 256) {
+        a = a * 2 + 1;
     } else {
-        /* range 0.5 <= a < 1.0 */
-
-        /* a in units of 1/256 rounded down */
-        /* q1 = (int)(a * 256.0); */
-        q = float64_mul(float64_256, a, s);
-        int64_t q_int = float64_to_int64_round_to_zero(q, s);
-
-        /* reciprocal root r */
-        /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
-        q = int64_to_float64(q_int, s);
-        q = float64_add(q, float64_half, s);
-        q = float64_div(q, float64_256, s);
-        q = float64_sqrt(q, s);
-        q = float64_div(float64_one, q, s);
+        a = (a >> 1) << 1;
+        a = (a + 1) * 2;
     }
-    /* r in units of 1/256 rounded to nearest */
-    /* s = (int)(256.0 * r + 0.5); */
+    b = 512;
+    while (a * (b + 1) * (b + 1) < (1 << 28)) {
+        b += 1;
+    }
+    estimate = (b + 1) / 2;
+    assert(256 <= estimate && estimate < 512);
 
-    q = float64_mul(q, float64_256,s );
-    q = float64_add(q, float64_half, s);
-    q_int = float64_to_int64_round_to_zero(q, s);
+    return estimate;
+}
 
-    /* return (double)s / 256.0;*/
-    return float64_div(int64_to_float64(q_int, s), float64_256, s);
+
+static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
+{
+    int estimate;
+    uint32_t scaled;
+
+    if (*exp == 0) {
+        while (extract64(frac, 51, 1) == 0) {
+            frac = frac << 1;
+            *exp -= 1;
+        }
+        frac = extract64(frac, 0, 51) << 1;
+    }
+
+    if (*exp & 1) {
+        /* scaled = UInt('01':fraction<51:45>) */
+        scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
+    } else {
+        /* scaled = UInt('1':fraction<51:44>) */
+        scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
+    }
+    estimate = do_recip_sqrt_estimate(scaled);
+
+    *exp = (exp_off - *exp) / 2;
+    return extract64(estimate, 0, 8) << 44;
+}
+
+float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+{
+    float_status *s = fpstp;
+    float16 f16 = float16_squash_input_denormal(input, s);
+    uint16_t val = float16_val(f16);
+    bool f16_sign = float16_is_neg(f16);
+    int f16_exp = extract32(val, 10, 5);
+    uint16_t f16_frac = extract32(val, 0, 10);
+    uint64_t f64_frac;
+
+    if (float16_is_any_nan(f16)) {
+        float16 nan = f16;
+        if (float16_is_signaling_nan(f16, s)) {
+            float_raise(float_flag_invalid, s);
+            nan = float16_maybe_silence_nan(f16, s);
+        }
+        if (s->default_nan_mode) {
+            nan =  float16_default_nan(s);
+        }
+        return nan;
+    } else if (float16_is_zero(f16)) {
+        float_raise(float_flag_divbyzero, s);
+        return float16_set_sign(float16_infinity, f16_sign);
+    } else if (f16_sign) {
+        float_raise(float_flag_invalid, s);
+        return float16_default_nan(s);
+    } else if (float16_is_infinity(f16)) {
+        return float16_zero;
+    }
+
+    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
+     * preserving the parity of the exponent.  */
+
+    f64_frac = ((uint64_t) f16_frac) << (52 - 10);
+
+    f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
+
+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
+    val = deposit32(0, 15, 1, f16_sign);
+    val = deposit32(val, 10, 5, f16_exp);
+    val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
+    return make_float16(val);
 }
 
 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
     float_status *s = fpstp;
     float32 f32 = float32_squash_input_denormal(input, s);
     uint32_t val = float32_val(f32);
-    uint32_t f32_sbit = 0x80000000 & val;
-    int32_t f32_exp = extract32(val, 23, 8);
+    uint32_t f32_sign = float32_is_neg(f32);
+    int f32_exp = extract32(val, 23, 8);
     uint32_t f32_frac = extract32(val, 0, 23);
     uint64_t f64_frac;
-    uint64_t val64;
-    int result_exp;
-    float64 f64;
 
     if (float32_is_any_nan(f32)) {
         float32 nan = f32;
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
      * preserving the parity of the exponent.  */
 
     f64_frac = ((uint64_t) f32_frac) << 29;
-    if (f32_exp == 0) {
-        while (extract64(f64_frac, 51, 1) == 0) {
-            f64_frac = f64_frac << 1;
-            f32_exp = f32_exp-1;
-        }
-        f64_frac = extract64(f64_frac, 0, 51) << 1;
-    }
 
-    if (extract64(f32_exp, 0, 1) == 0) {
-        f64 = make_float64(((uint64_t) f32_sbit) << 32
-                           | (0x3feULL << 52)
-                           | f64_frac);
-    } else {
-        f64 = make_float64(((uint64_t) f32_sbit) << 32
-                           | (0x3fdULL << 52)
-                           | f64_frac);
-    }
+    f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
 
-    result_exp = (380 - f32_exp) / 2;
-
-    f64 = recip_sqrt_estimate(f64, s);
-
-    val64 = float64_val(f64);
-
-    val = ((result_exp & 0xff) << 23)
-        | ((val64 >> 29)  & 0x7fffff);
+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
+    val = deposit32(0, 31, 1, f32_sign);
+    val = deposit32(val, 23, 8, f32_exp);
+    val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
     return make_float32(val);
 }
 
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
     float_status *s = fpstp;
     float64 f64 = float64_squash_input_denormal(input, s);
     uint64_t val = float64_val(f64);
-    uint64_t f64_sbit = 0x8000000000000000ULL & val;
-    int64_t f64_exp = extract64(val, 52, 11);
+    bool f64_sign = float64_is_neg(f64);
+    int f64_exp = extract64(val, 52, 11);
     uint64_t f64_frac = extract64(val, 0, 52);
-    int64_t result_exp;
-    uint64_t result_frac;
 
     if (float64_is_any_nan(f64)) {
         float64 nan = f64;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         return float64_zero;
     }
 
-    /* Scale and normalize to a double-precision value between 0.25 and 1.0,
-     * preserving the parity of the exponent.  */
+    f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
 
-    if (f64_exp == 0) {
-        while (extract64(f64_frac, 51, 1) == 0) {
-            f64_frac = f64_frac << 1;
-            f64_exp = f64_exp - 1;
-        }
-        f64_frac = extract64(f64_frac, 0, 51) << 1;
-    }
-
-    if (extract64(f64_exp, 0, 1) == 0) {
-        f64 = make_float64(f64_sbit
-                           | (0x3feULL << 52)
-                           | f64_frac);
-    } else {
-        f64 = make_float64(f64_sbit
-                           | (0x3fdULL << 52)
-                           | f64_frac);
-    }
-
-    result_exp = (3068 - f64_exp) / 2;
-
-    f64 = recip_sqrt_estimate(f64, s);
-
-    result_frac = extract64(float64_val(f64), 0, 52);
-
-    return make_float64(f64_sbit |
-                        ((result_exp & 0x7ff) << 52) |
-                        result_frac);
+    /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
+    val = deposit64(0, 61, 1, f64_sign);
+    val = deposit64(val, 52, 11, f64_exp);
+    val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
+    return make_float64(val);
 }
 
 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
 
 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
 {
-    float_status *fpst = fpstp;
-    float64 f64;
+    int estimate;
 
     if ((a & 0xc0000000) == 0) {
         return 0xffffffff;
     }
 
-    if (a & 0x80000000) {
-        f64 = make_float64((0x3feULL << 52)
-                           | ((uint64_t)(a & 0x7fffffff) << 21));
-    } else { /* bits 31-30 == '01' */
-        f64 = make_float64((0x3fdULL << 52)
-                           | ((uint64_t)(a & 0x3fffffff) << 22));
-    }
+    estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
 
-    f64 = recip_sqrt_estimate(f64, fpst);
-
-    return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
+    return deposit32(0, 23, 9, estimate);
 }
 
 /* VFPv4 fused multiply-accumulate */
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 7 +++++++
 1 file changed, 7 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

Only one half-precision instruction has been added to this group.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-29-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 35 +++++++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
  *   MVNI - move inverted (shifted) imm into register
  *   ORR  - bitwise OR of (shifted) imm with register
  *   BIC  - bitwise clear of (shifted) imm with register
+ * With ARMv8.2 we also have:
+ *   FMOV half-precision
  */
 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
     uint64_t imm = 0;
 
     if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
-        unallocated_encoding(s);
-        return;
+        /* Check for FMOV (vector, immediate) - half-precision */
+        if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
+            unallocated_encoding(s);
+            return;
+        }
     }
 
     if (!fp_access_check(s)) {
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
                     imm |= 0x4000000000000000ULL;
                 }
             } else {
-                imm = (abcdefgh & 0x3f) << 19;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x80000000;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3e000000;
+                if (o2) {
+                    /* FMOV (vector, immediate) - half-precision */
+                    imm = vfp_expand_imm(MO_16, abcdefgh);
+                    /* now duplicate across the lanes */
+                    imm = bitfield_replicate(imm, 16);
                 } else {
-                    imm |= 0x40000000;
+                    imm = (abcdefgh & 0x3f) << 19;
+                    if (abcdefgh & 0x80) {
+                        imm |= 0x80000000;
+                    }
+                    if (abcdefgh & 0x40) {
+                        imm |= 0x3e000000;
+                    } else {
+                        imm |= 0x40000000;
+                    }
+                    imm |= (imm << 32);
                 }
-                imm |= (imm << 32);
             }
         }
         break;
+    default:
+        fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
+        g_assert_not_reached();
     }
 
     if (cmode_3_1 != 7 && is_neg) {
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

I only needed to do a little light re-factoring to support the
half-precision helpers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-30-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 26 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
     case 0xf: /* FMAXP */
     case 0x2c: /* FMINNMP */
     case 0x2f: /* FMINP */
-        /* FP op, size[0] is 32 or 64 bit */
+        /* FP op, size[0] is 32 or 64 bit*/
         if (!u) {
-            unallocated_encoding(s);
-            return;
+            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+                unallocated_encoding(s);
+                return;
+            } else {
+                size = MO_16;
+            }
+        } else {
+            size = extract32(size, 0, 1) ? MO_64 : MO_32;
         }
+
         if (!fp_access_check(s)) {
             return;
         }
 
-        size = extract32(size, 0, 1) ? 3 : 2;
-        fpst = get_fpstatus_ptr(false);
+        fpst = get_fpstatus_ptr(size == MO_16);
         break;
     default:
         unallocated_encoding(s);
         return;
     }
 
-    if (size == 3) {
+    if (size == MO_64) {
         TCGv_i64 tcg_op1 = tcg_temp_new_i64();
         TCGv_i64 tcg_op2 = tcg_temp_new_i64();
         TCGv_i64 tcg_res = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
         TCGv_i32 tcg_op2 = tcg_temp_new_i32();
         TCGv_i32 tcg_res = tcg_temp_new_i32();
 
-        read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
-        read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
+        read_vec_element_i32(s, tcg_op1, rn, 0, size);
+        read_vec_element_i32(s, tcg_op2, rn, 1, size);
 
-        switch (opcode) {
-        case 0xc: /* FMAXNMP */
-            gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xd: /* FADDP */
-            gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0xf: /* FMAXP */
-            gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x2c: /* FMINNMP */
-            gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        case 0x2f: /* FMINP */
-            gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
-            break;
-        default:
-            g_assert_not_reached();
+        if (size == MO_16) {
+            switch (opcode) {
+            case 0xc: /* FMAXNMP */
+                gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xd: /* FADDP */
+                gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xf: /* FMAXP */
+                gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2c: /* FMINNMP */
+                gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2f: /* FMINP */
+                gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+        } else {
+            switch (opcode) {
+            case 0xc: /* FMAXNMP */
+                gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xd: /* FADDP */
+                gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0xf: /* FMAXP */
+                gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2c: /* FMINNMP */
+                gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            case 0x2f: /* FMINP */
+                gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
+                break;
+            default:
+                g_assert_not_reached();
+            }
         }
 
         write_fp_sreg(s, rd, tcg_res);
-- 
2.16.2

From: Alex Bennée <alex.bennee@linaro.org>

This covers the encoding group:

Advanced SIMD scalar three same FP16

As all the helpers are already there it is simply a case of calling the
existing helpers in the scalar context.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-31-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

From: Alex Bennée <alex.bennee@linaro.org>

This includes FMOV, FABS, FNEG, FSQRT and  FRINT[NPMZAXI]. We re-use
existing helpers to achieve this.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-32-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(t_true);
 }
 
+/* Floating-point data-processing (1 source) - half precision */
+static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
+{
+    TCGv_ptr fpst = NULL;
+    TCGv_i32 tcg_op = tcg_temp_new_i32();
+    TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+    read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
+
+    switch (opcode) {
+    case 0x0: /* FMOV */
+        tcg_gen_mov_i32(tcg_res, tcg_op);
+        break;
+    case 0x1: /* FABS */
+        tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
+        break;
+    case 0x2: /* FNEG */
+        tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+        break;
+    case 0x3: /* FSQRT */
+        gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
+        break;
+    case 0x8: /* FRINTN */
+    case 0x9: /* FRINTP */
+    case 0xa: /* FRINTM */
+    case 0xb: /* FRINTZ */
+    case 0xc: /* FRINTA */
+    {
+        TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+        fpst = get_fpstatus_ptr(true);
+
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
+
+        gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+        tcg_temp_free_i32(tcg_rmode);
+        break;
+    }
+    case 0xe: /* FRINTX */
+        fpst = get_fpstatus_ptr(true);
+        gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
+        break;
+    case 0xf: /* FRINTI */
+        fpst = get_fpstatus_ptr(true);
+        gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
+        break;
+    default:
+        abort();
+    }
+
+    write_fp_sreg(s, rd, tcg_res);
+
+    if (fpst) {
+        tcg_temp_free_ptr(fpst);
+    }
+    tcg_temp_free_i32(tcg_op);
+    tcg_temp_free_i32(tcg_res);
+}
+
 /* Floating-point data-processing (1 source) - single precision */
 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
 
             handle_fp_1src_double(s, opcode, rd, rn);
             break;
+        case 3:
+            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+                unallocated_encoding(s);
+                return;
+            }
+
+            if (!fp_access_check(s)) {
+                return;
+            }
+
+            handle_fp_1src_half(s, opcode, rd, rn);
+            break;
         default:
             unallocated_encoding(s);
         }
-- 
2.16.2

From: Alistair Francis <alistair.francis@xilinx.com>

I am leaving Xilinx, so to avoid having an email address that bounces
update my maintainer address to point to my personal email address.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/misc/arm_sysctl.c
 
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/xilinx_*
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/zynq*
 X: hw/ssi/xilinx_*
 
 Xilinx ZynqMP
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 L: qemu-arm@nongnu.org
 S: Maintained
@@ -XXX,XX +XXX,XX @@ T: git git://github.com/bonzini/qemu.git scsi-next
 
 SSI
 M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/ssi/*
 F: hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
 F: tests/m25p80-test.c
 
 Xilinx SPI
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 M: Peter Crosthwaite <crosthwaite.peter@gmail.com>
 S: Maintained
 F: hw/ssi/xilinx_*
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/net/eepro100.c
 
 Generic Loader
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/core/generic-loader.c
 F: include/hw/core/generic-loader.h
@@ -XXX,XX +XXX,XX @@ F: tests/qmp-test.c
 T: git git://repo.or.cz/qemu/armbru.git qapi-next
 
 Register API
-M: Alistair Francis <alistair.francis@xilinx.com>
+M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/core/register.c
 F: include/hw/register.h
-- 
2.16.2

Not very much here, but several people have fallen over
the vector operation segfault bug, so let's get the fix
into master.

thanks
-- PMM

The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:

Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523

for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:

hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)

----------------------------------------------------------------
target-arm queue:
 * exynos4210: QOM'ify the Exynos4210 SoC
 * exynos4210: Add DMA support for the Exynos4210
 * arm_gicv3: Fix writes to ICC_CTLR_EL3
 * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
 * target/arm: Fix vector operation segfault
 * target/arm: Minor improvements to BFXIL, EXTR

----------------------------------------------------------------
Alistair Francis (1):
      target/arm: Fix vector operation segfault

Guenter Roeck (1):
      hw/arm/exynos4210: Add DMA support for the Exynos4210

Peter Maydell (5):
      arm: Move system_clock_scale to armv7m_systick.h
      arm: Remove unnecessary includes of hw/arm/arm.h
      arm: Rename hw/arm/arm.h to hw/arm/boot.h
      hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
      hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3

Philippe Mathieu-Daudé (3):
      hw/arm/exynos4: Remove unuseful debug code
      hw/arm/exynos4: Use the IEC binary prefix definitions
      hw/arm/exynos4210: QOM'ify the Exynos4210 SoC

Richard Henderson (2):
      target/arm: Use extract2 for EXTR
      target/arm: Simplify BFXIL expansion

include/hw/arm/allwinner-a10.h    |  2 +-
 include/hw/arm/aspeed_soc.h       |  1 -
 include/hw/arm/bcm2836.h          |  1 -
 include/hw/arm/{arm.h => boot.h}  | 12 +++------
 include/hw/arm/exynos4210.h       |  9 +++++--
 include/hw/arm/fsl-imx25.h        |  2 +-
 include/hw/arm/fsl-imx31.h        |  2 +-
 include/hw/arm/fsl-imx6.h         |  2 +-
 include/hw/arm/fsl-imx6ul.h       |  2 +-
 include/hw/arm/fsl-imx7.h         |  2 +-
 include/hw/arm/virt.h             |  2 +-
 include/hw/arm/xlnx-versal.h      |  2 +-
 include/hw/arm/xlnx-zynqmp.h      |  2 +-
 include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
 hw/arm/armsse.c                   |  2 +-
 hw/arm/armv7m.c                   |  2 +-
 hw/arm/aspeed.c                   |  2 +-
 hw/arm/boot.c                     |  2 +-
 hw/arm/collie.c                   |  2 +-
 hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
 hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
 hw/arm/highbank.c                 |  2 +-
 hw/arm/integratorcp.c             |  2 +-
 hw/arm/mainstone.c                |  2 +-
 hw/arm/microbit.c                 |  2 +-
 hw/arm/mps2-tz.c                  |  2 +-
 hw/arm/mps2.c                     |  2 +-
 hw/arm/msf2-soc.c                 |  1 -
 hw/arm/msf2-som.c                 |  2 +-
 hw/arm/musca.c                    |  2 +-
 hw/arm/musicpal.c                 |  2 +-
 hw/arm/netduino2.c                |  2 +-
 hw/arm/nrf51_soc.c                |  2 +-
 hw/arm/nseries.c                  |  2 +-
 hw/arm/omap1.c                    |  2 +-
 hw/arm/omap2.c                    |  2 +-
 hw/arm/omap_sx1.c                 |  2 +-
 hw/arm/palm.c                     |  2 +-
 hw/arm/raspi.c                    |  2 +-
 hw/arm/realview.c                 |  2 +-
 hw/arm/spitz.c                    |  2 +-
 hw/arm/stellaris.c                |  2 +-
 hw/arm/stm32f205_soc.c            |  2 +-
 hw/arm/strongarm.c                |  2 +-
 hw/arm/tosa.c                     |  2 +-
 hw/arm/versatilepb.c              |  2 +-
 hw/arm/vexpress.c                 |  2 +-
 hw/arm/virt.c                     |  2 +-
 hw/arm/xilinx_zynq.c              |  2 +-
 hw/arm/xlnx-versal.c              |  2 +-
 hw/arm/z2.c                       |  2 +-
 hw/intc/arm_gicv3_cpuif.c         |  6 ++---
 hw/intc/armv7m_nvic.c             |  1 -
 target/arm/arm-semi.c             |  1 -
 target/arm/cpu.c                  |  1 -
 target/arm/cpu64.c                |  1 -
 target/arm/kvm.c                  |  1 -
 target/arm/kvm32.c                |  1 -
 target/arm/kvm64.c                |  1 -
 target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
 target/arm/translate.c            |  4 +--
 61 files changed, 164 insertions(+), 123 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (96%)

From: Richard Henderson <richard.henderson@linaro.org>

This is, after all, how we implement extract2 in tcg/aarch64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
             } else {
                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
             }
-        } else if (rm == rn) { /* ROR */
-            tcg_rm = cpu_reg(s, rm);
-            if (sf) {
-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
-            } else {
-                TCGv_i32 tmp = tcg_temp_new_i32();
-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
-                tcg_gen_rotri_i32(tmp, tmp, imm);
-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
-                tcg_temp_free_i32(tmp);
-            }
         } else {
-            tcg_rm = read_cpu_reg(s, rm, sf);
-            tcg_rn = read_cpu_reg(s, rn, sf);
-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-            if (!sf) {
-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+            tcg_rm = cpu_reg(s, rm);
+            tcg_rn = cpu_reg(s, rn);
+
+            if (sf) {
+                /* Specialization to ROR happens in EXTRACT2.  */
+                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
+            } else {
+                TCGv_i32 t0 = tcg_temp_new_i32();
+
+                tcg_gen_extrl_i64_i32(t0, tcg_rm);
+                if (rm == rn) {
+                    tcg_gen_rotri_i32(t0, t0, imm);
+                } else {
+                    TCGv_i32 t1 = tcg_temp_new_i32();
+                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
+                    tcg_gen_extract2_i32(t0, t0, t1, imm);
+                    tcg_temp_free_i32(t1);
+                }
+                tcg_gen_extu_i32_i64(tcg_rd, t0);
+                tcg_temp_free_i32(t0);
             }
         }
     }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The mask implied by the extract is redundant with the one
implied by the deposit.  Also, fix spelling of BFXIL.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
             tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
             return;
         }
-        /* opc == 1, BXFIL fall through to deposit */
-        tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
+        /* opc == 1, BFXIL fall through to deposit */
+        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
         pos = 0;
     } else {
         /* Handle the ri > si case with a deposit
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
         len = ri;
     }
 
-    if (opc == 1) { /* BFM, BXFIL */
+    if (opc == 1) { /* BFM, BFXIL */
         tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
     } else {
         /* SBFM or UBFM: We start with zero, and we haven't modified
-- 
2.20.1

From: Alistair Francis <alistair.francis@wdc.com>

Commit 89e68b575 "target/arm: Use vector operations for saturation"
causes this abort() when booting QEMU ARM with a Cortex-A15:

0  0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
1  0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
2  0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
3  0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
4  0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
5  0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
6  0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
7  0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
8  0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
9  0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.

This patch ensures that we don't hit the abort() in the second switch
case in disas_neon_data_insn() as we will return from the first case.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqadd_op : sqadd_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VQSUB:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqsub_op : sqsub_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VMUL: /* VMUL */
             if (u) {
-- 
2.20.1

The system_clock_scale global is used only by the armv7m systick
device; move the extern declaration to the armv7m_systick.h header,
and expand the comment to explain what it is and that it should
ideally be replaced with a different approach.

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-/* Multiplication factor to convert from system clock ticks to qemu timer
-   ticks.  */
-extern int system_clock_scale;
-
 #endif /* HW_ARM_H */
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
     qemu_irq irq;
 } SysTickState;
 
+/*
+ * Multiplication factor to convert from system clock ticks to qemu timer
+ * ticks. This should be set (by board code, usually) to a value
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
+ * in Hz of the CPU.
+ *
+ * This value is used by the systick device when it is running in
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
+ * set how fast the timer should tick.
+ *
+ * TODO: we should refactor this so that rather than using a global
+ * we use a device property or something similar. This is complicated
+ * because (a) the property would need to be plumbed through from the
+ * board code down through various layers to the systick device
+ * and (b) the property needs to be modifiable after realize, because
+ * the stellaris board uses this to implement the behaviour where the
+ * guest can reprogram the PLL registers to downclock the CPU, and the
+ * systick device needs to react accordingly. Possibly this should
+ * be deferred until we have a good API for modelling clock trees.
+ */
+extern int system_clock_scale;
+
 #endif
-- 
2.20.1

The hw/arm/arm.h header now only includes declarations relating
to boot.c code, so it is only needed by Arm board or SoC code.
Remove some unnecessary inclusions of it from target/arm files
and from hw/intc/armv7m_nvic.c.

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
-#include "hw/arm/arm.h"
 #include "hw/intc/armv7m_nvic.h"
 #include "target/arm/cpu.h"
 #include "exec/exec-all.h"
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@
 #else
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
-#include "hw/arm/arm.h"
 #include "qemu/cutils.h"
 #endif
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/hw_accel.h"
 #include "kvm_arm.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "trace.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "hw/pci/pci.h"
 #include "exec/memattrs.h"
 #include "exec/address-spaces.h"
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "qemu/log.h"
 
 static inline void set_feature(uint64_t *features, int feature)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 
 static bool have_guest_debug;
 
-- 
2.20.1

The header file hw/arm/arm.h now includes only declarations
relating to hw/arm/boot.c functionality. Rename it accordingly,
and adjust its header comment.

The bulk of this commit was created via
 perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h

In a few cases we can just delete the #include:
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
include/hw/arm/bcm2836.h did not require it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
---
 include/hw/arm/allwinner-a10.h   | 2 +-
 include/hw/arm/aspeed_soc.h      | 1 -
 include/hw/arm/bcm2836.h         | 1 -
 include/hw/arm/{arm.h => boot.h} | 8 ++++----
 include/hw/arm/fsl-imx25.h       | 2 +-
 include/hw/arm/fsl-imx31.h       | 2 +-
 include/hw/arm/fsl-imx6.h        | 2 +-
 include/hw/arm/fsl-imx6ul.h      | 2 +-
 include/hw/arm/fsl-imx7.h        | 2 +-
 include/hw/arm/virt.h            | 2 +-
 include/hw/arm/xlnx-versal.h     | 2 +-
 include/hw/arm/xlnx-zynqmp.h     | 2 +-
 hw/arm/armsse.c                  | 2 +-
 hw/arm/armv7m.c                  | 2 +-
 hw/arm/aspeed.c                  | 2 +-
 hw/arm/boot.c                    | 2 +-
 hw/arm/collie.c                  | 2 +-
 hw/arm/exynos4210.c              | 2 +-
 hw/arm/exynos4_boards.c          | 2 +-
 hw/arm/highbank.c                | 2 +-
 hw/arm/integratorcp.c            | 2 +-
 hw/arm/mainstone.c               | 2 +-
 hw/arm/microbit.c                | 2 +-
 hw/arm/mps2-tz.c                 | 2 +-
 hw/arm/mps2.c                    | 2 +-
 hw/arm/msf2-soc.c                | 1 -
 hw/arm/msf2-som.c                | 2 +-
 hw/arm/musca.c                   | 2 +-
 hw/arm/musicpal.c                | 2 +-
 hw/arm/netduino2.c               | 2 +-
 hw/arm/nrf51_soc.c               | 2 +-
 hw/arm/nseries.c                 | 2 +-
 hw/arm/omap1.c                   | 2 +-
 hw/arm/omap2.c                   | 2 +-
 hw/arm/omap_sx1.c                | 2 +-
 hw/arm/palm.c                    | 2 +-
 hw/arm/raspi.c                   | 2 +-
 hw/arm/realview.c                | 2 +-
 hw/arm/spitz.c                   | 2 +-
 hw/arm/stellaris.c               | 2 +-
 hw/arm/stm32f205_soc.c           | 2 +-
 hw/arm/strongarm.c               | 2 +-
 hw/arm/tosa.c                    | 2 +-
 hw/arm/versatilepb.c             | 2 +-
 hw/arm/vexpress.c                | 2 +-
 hw/arm/virt.c                    | 2 +-
 hw/arm/xilinx_zynq.c             | 2 +-
 hw/arm/xlnx-versal.c             | 2 +-
 hw/arm/z2.c                      | 2 +-
 49 files changed, 49 insertions(+), 52 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (98%)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "qemu/error-report.h"
 #include "hw/char/serial.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/timer/allwinner-a10-pit.h"
 #include "hw/intc/allwinner-a10-pic.h"
 #include "hw/net/allwinner_emac.h"
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef ASPEED_SOC_H
 #define ASPEED_SOC_H
 
-#include "hw/arm/arm.h"
 #include "hw/intc/aspeed_vic.h"
 #include "hw/misc/aspeed_scu.h"
 #include "hw/misc/aspeed_sdmc.h"
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #ifndef BCM2836_H
 #define BCM2836_H
 
-#include "hw/arm/arm.h"
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
similarity index 98%
rename from include/hw/arm/arm.h
rename to include/hw/arm/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/boot.h
@@ -XXX,XX +XXX,XX @@
 /*
- * Misc ARM declarations
+ * ARM kernel loader.
  *
  * Copyright (c) 2006 CodeSourcery.
  * Written by Paul Brook
@@ -XXX,XX +XXX,XX @@
  *
  */
 
-#ifndef HW_ARM_H
-#define HW_ARM_H
+#ifndef HW_ARM_BOOT_H
+#define HW_ARM_BOOT_H
 
 #include "exec/memory.h"
 #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-#endif /* HW_ARM_H */
+#endif /* HW_ARM_BOOT_H */
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX25_H
 #define FSL_IMX25_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx25_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX31_H
 #define FSL_IMX31_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx31_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6_H
 #define FSL_IMX6_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/misc/imx6_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6UL_H
 #define FSL_IMX6UL_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX7_H
 #define FSL_IMX7_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/misc/imx7_ccm.h"
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/kvm.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #define XLNX_VERSAL_H
 
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gicv3.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #ifndef XLNX_ZYNQMP_H
 
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/registerfields.h"
 #include "hw/arm/armsse.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 /* Format of the System Information block SYS_CONFIG register */
 typedef enum SysConfigFormat {
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "elf.h"
 #include "sysemu/qtest.h"
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "exec/address-spaces.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/boards.h"
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include <libfdt.h>
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/linux-boot-if.h"
 #include "sysemu/kvm.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "strongarm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/sd/sdhci.h"
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
 #include "net/net.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/net/lan9118.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "net/net.h"
 #include "sysemu/kvm.h"
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/misc/arm_integrator_debug.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "hw/net/smc91c111.h"
 #include "hw/boards.h"
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
 #include "exec/address-spaces.h"
 #include "hw/char/serial.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/msf2-soc.h"
 #include "cpu.h"
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armsse.h"
 #include "hw/boards.h"
 #include "hw/char/pl011.h"
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "qemu/error-report.h"
 #include "hw/arm/stm32f205_soc.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 static void netduino2_init(MachineState *machine)
 {
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "hw/misc/unimp.h"
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bswap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/omap.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/irq.h"
 #include "ui/console.h"
 #include "hw/boards.h"
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/soc_dma.h"
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "qemu/timer.h"
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/qtest.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/input/tsc2xxx.h"
 #include "hw/loader.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "hw/boards.h"
 #include "hw/loader.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 
 #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/net/smc91c111.h"
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "hw/pcmcia.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/sysbus.h"
 #include "hw/ssi/ssi.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "qemu/timer.h"
 #include "hw/i2c/i2c.h"
 #include "net/net.h"
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/stm32f205_soc.h"
 
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "strongarm.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "chardev/char-fe.h"
 #include "chardev/char-serial.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/sharpsl.h"
 #include "hw/pcmcia.h"
 #include "hw/boards.h"
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/option.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/arm/virt.h"
 #include "hw/block/flash.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "kvm_arm.h"
 #include "hw/misc/unimp.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/i2c/i2c.h"
 #include "hw/ssi/ssi.h"
 #include "hw/boards.h"
-- 
2.20.1

In ich_vmcr_write() we enforce "writes of BPR fields to less than
their minimum sets them to the minimum" by doing a "read vbpr and
write it back" operation.  A typo here meant that we weren't handling
writes to these fields correctly, because we were reading from VBPR0
but writing to VBPR1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
 
     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
     }
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
     }
 
-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
         cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
     }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/lan9118.h"
 #include "hw/boards.h"
 
-#undef DEBUG
-
-//#define DEBUG
-
-#ifdef DEBUG
-    #undef PRINT_DEBUG
-    #define  PRINT_DEBUG(fmt, args...) \
-        do { \
-            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
-        } while (0)
-#else
-    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
-#endif
-
 #define SMDK_LAN9118_BASE_ADDR      0x05000000
 
 typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_board_binfo.gic_cpu_if_addr =
             EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 
-    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
-            " kernel_filename: %s\n"
-            " kernel_cmdline: %s\n"
-            " initrd_filename: %s\n",
-            exynos4_board_ram_size[board_type] / 1048576,
-            exynos4_board_ram_size[board_type],
-            machine->kernel_filename,
-            machine->kernel_cmdline,
-            machine->initrd_filename);
-
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

It eases code review, unit is explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
 };
 
 static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
+    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
+    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
 };
 
 static struct arm_boot_info exynos4_board_binfo = {
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

QEMU already supports pl330. Instantiate it for Exynos4210.

Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:

/ {
    soc: soc {
        amba {
            pdma0: pdma@12680000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12680000 0x1000>;
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA0>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            pdma1: pdma@12690000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12690000 0x1000>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA1>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            mdma1: mdma@12850000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12850000 0x1000>;
                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_MDMA>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <1>;
            };
        };
    };
};

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
      rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 /* EHCI */
 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 
+/* DMA */
+#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
+#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
+#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
     return (0x9 << ARM_AFF1_SHIFT) | cpu;
 }
 
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
+{
+    SysBusDevice *busdev;
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, "pl330");
+    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
+    qdev_init_nofail(dev);
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, base);
+    sysbus_connect_irq(busdev, 0, irq);
+}
+
 Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
 {
     Exynos4210State *s = g_new0(Exynos4210State, 1);
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
             s->irq_table[exynos4210_get_irq(28, 3)]);
 
+    /*** DMA controllers ***/
+    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
+
     return s;
 }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-5-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/exynos4210.h |  9 +++++++--
 hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
 hw/arm/exynos4_boards.c     |  9 ++++++---
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
 } Exynos4210Irq;
 
 typedef struct Exynos4210State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
     qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
 } Exynos4210State;
 
+#define TYPE_EXYNOS4210_SOC "exynos4210"
+#define EXYNOS4210_SOC(obj) \
+    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
+
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
-
 /* Initialize exynos4210 IRQ subsystem stub */
 qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
     sysbus_connect_irq(busdev, 0, irq);
 }
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
 {
-    Exynos4210State *s = g_new0(Exynos4210State, 1);
+    Exynos4210State *s = EXYNOS4210_SOC(socdev);
+    MemoryRegion *system_mem = get_system_memory();
     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     SysBusDevice *busdev;
     DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
     pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
-
-    return s;
 }
+
+static void exynos4210_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = exynos4210_realize;
+}
+
+static const TypeInfo exynos4210_info = {
+    .name = TYPE_EXYNOS4210_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Exynos4210State),
+    .class_init = exynos4210_class_init,
+};
+
+static void exynos4210_register_types(void)
+{
+    type_register_static(&exynos4210_info);
+}
+
+type_init(exynos4210_register_types)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
 } Exynos4BoardType;
 
 typedef struct Exynos4BoardState {
-    Exynos4210State *soc;
+    Exynos4210State soc;
     MemoryRegion dram0_mem;
     MemoryRegion dram1_mem;
 } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-    s->soc = exynos4210_init(get_system_memory());
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
+    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
+    object_property_set_bool(OBJECT(&s->soc), true, "realized",
+                             &error_fatal);
 
     return s;
 }
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
                                                       EXYNOS4_BOARD_SMDKC210);
 
     lan9215_init(SMDK_LAN9118_BASE_ADDR,
-            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
+            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
     arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
 }
 
-- 
2.20.1