[Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values

Alex Bennée posted 31 patches 7 years, 8 months ago
There is a newer version of this series
[Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values
Posted by Alex Bennée 7 years, 8 months ago
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 267a9d7e2f..c2bce23fa5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -168,6 +168,7 @@ typedef struct {
  *  Qn = regs[n].d[1]:regs[n].d[0]
  *  Dn = regs[n].d[0]
  *  Sn = regs[n].d[0] bits 31..0
+ *  Hn = regs[n].d[0] bits 15..0 for even n, and bits 31..16 for odd n
  *
  * This corresponds to the architecturally defined mapping between
  * the two execution states, and means we do not need to explicitly
-- 
2.15.1


Re: [Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values
Posted by Richard Henderson 7 years, 8 months ago
On 02/23/2018 07:36 AM, Alex Bennée wrote:
> @@ -168,6 +168,7 @@ typedef struct {
>   *  Qn = regs[n].d[1]:regs[n].d[0]
>   *  Dn = regs[n].d[0]
>   *  Sn = regs[n].d[0] bits 31..0
> + *  Hn = regs[n].d[0] bits 15..0 for even n, and bits 31..16 for odd n

Everything past here --------------^ is wrong.


r~