[Qemu-devel] [PULL 00/32] target-arm queue
[Qemu-devel] [PULL 00/29] target-arm queue
1
Latest run of arm patches -- most of these are Philippe's SD card
1
First arm pullreq of 4.2...
2
cleanups. I have more in my queue to review, but 32 is enough
3
patches to warrant sending out.
4
2
5
thanks
3
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit ff8689611a1d954897d857b28f7ef404e11cfa2c:
6
The following changes since commit 27608c7c66bd923eb5e5faab80e795408cbe2b51:
9
7
10
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-signed' into staging (2018-02-22 11:37:05 +0000)
8
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20190814a' into staging (2019-08-16 12:00:18 +0100)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180222
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190816
15
13
16
for you to fetch changes up to 4e5cc6756586e967993187657dfcdde4e00288d9:
14
for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b:
17
15
18
sdcard: simplify SD_SEND_OP_COND (ACMD41) (2018-02-22 15:12:54 +0000)
16
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16 14:02:53 +0100)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
* New "raspi3" machine emulating RaspberryPi 3
19
target-arm queue:
22
* Fix bad register definitions for VMIDR and VMPIDR (which caused
20
* target/arm: generate a custom MIDR for -cpu max
23
assertions for 64-bit guest CPUs with EL2 on big-endian hosts)
21
* hw/misc/zynq_slcr: refactor to use standard register definition
24
* hw/char/stm32f2xx_usart: fix TXE/TC bit handling
22
* Set ENET_BD_BDU in I.MX FEC controller
25
* Fix ast2500 protection register emulation
23
* target/arm: Fix routing of singlestep exceptions
26
* Lots of SD card emulation cleanups and bugfixes
24
* refactor a32/t32 decoder handling of PC
25
* minor optimisations/cleanups of some a32/t32 codegen
26
* target/arm/cpu64: Ensure kvm really supports aarch64=off
27
* target/arm/cpu: Ensure we can use the pmu with kvm
28
* target/arm: Minor cleanups preparatory to KVM SVE support
27
29
28
----------------------------------------------------------------
30
----------------------------------------------------------------
29
Hugo Landau (1):
31
Aaron Hill (1):
30
Fix ast2500 protection register emulation
32
Set ENET_BD_BDU in I.MX FEC controller
31
33
32
Pekka Enberg (1):
34
Alex Bennée (1):
33
raspi: Add "raspi3" machine type
35
target/arm: generate a custom MIDR for -cpu max
34
36
35
Peter Maydell (1):
37
Andrew Jones (6):
36
target/arm: Fix register definitions for VMIDR and VMPIDR
38
target/arm/cpu64: Ensure kvm really supports aarch64=off
39
target/arm/cpu: Ensure we can use the pmu with kvm
40
target/arm/helper: zcr: Add build bug next to value range assumption
41
target/arm/cpu: Use div-round-up to determine predicate register array size
42
target/arm/kvm64: Fix error returns
43
target/arm/kvm64: Move the get/put of fpsimd registers out
37
44
38
Philippe Mathieu-Daudé (28):
45
Damien Hedde (1):
39
hw/sd/milkymist-memcard: use qemu_log_mask()
46
hw/misc/zynq_slcr: use standard register definition
40
hw/sd/milkymist-memcard: split realize() out of SysBusDevice init()
41
hw/sd/milkymist-memcard: expose a SDBus and connect the SDCard to it
42
hw/sd/ssi-sd: use the SDBus API, connect the SDCard to the bus
43
sdcard: reorder SDState struct members
44
sdcard: replace DPRINTF() by trace events
45
sdcard: add a trace event for command responses
46
sdcard: replace fprintf() by qemu_hexdump()
47
sdcard: add more trace events
48
sdcard: define SDMMC_CMD_MAX instead of using the magic '64'
49
sdcard: use G_BYTE from cutils
50
sdcard: use the registerfields API to access the OCR register
51
sdcard: Don't always set the high capacity bit
52
sdcard: update the CSD CRC register regardless the CSD structure version
53
sdcard: fix the 'maximum data transfer rate' to 25MHz
54
sdcard: clean the SCR register and add few comments
55
sdcard: remove commands from unsupported old MMC specification
56
sdcard: simplify using the ldst API
57
sdcard: use the correct masked OCR in the R3 reply
58
sdcard: use the registerfields API for the CARD_STATUS register masks
59
sdcard: handle CMD54 (SDIO)
60
sdcard: handle the Security Specification commands
61
sdcard: use a more descriptive label 'unimplemented_spi_cmd'
62
sdcard: handles more commands in SPI mode
63
sdcard: check the card is in correct state for APP CMD (CMD55)
64
sdcard: warn if host uses an incorrect address for APP CMD (CMD55)
65
sdcard: simplify SEND_IF_COND (CMD8)
66
sdcard: simplify SD_SEND_OP_COND (ACMD41)
67
47
68
Richard Braun (1):
48
Peter Maydell (2):
69
hw/char/stm32f2xx_usart: fix TXE/TC bit handling
49
target/arm: Factor out 'generate singlestep exception' function
50
target/arm: Fix routing of singlestep exceptions
70
51
71
hw/sd/sdmmc-internal.h | 15 ++
52
Richard Henderson (18):
72
include/hw/char/stm32f2xx_usart.h | 7 +-
53
target/arm: Pass in pc to thumb_insn_is_16bit
73
include/hw/sd/sd.h | 1 -
54
target/arm: Introduce pc_curr
74
hw/arm/raspi.c | 23 ++
55
target/arm: Introduce read_pc
75
hw/char/stm32f2xx_usart.c | 12 +-
56
target/arm: Introduce add_reg_for_lit
76
hw/misc/aspeed_scu.c | 6 +-
57
target/arm: Remove redundant s->pc & ~1
77
hw/misc/aspeed_sdmc.c | 8 +-
58
target/arm: Replace s->pc with s->base.pc_next
78
hw/sd/milkymist-memcard.c | 87 +++----
59
target/arm: Replace offset with pc in gen_exception_insn
79
hw/sd/sd.c | 467 +++++++++++++++++++++++---------------
60
target/arm: Replace offset with pc in gen_exception_internal_insn
80
hw/sd/ssi-sd.c | 32 +--
61
target/arm: Remove offset argument to gen_exception_bkpt_insn
81
target/arm/helper.c | 8 +-
62
target/arm: Use unallocated_encoding for aarch32
82
hw/sd/trace-events | 20 ++
63
target/arm: Remove helper_double_saturate
83
12 files changed, 446 insertions(+), 240 deletions(-)
64
target/arm: Use tcg_gen_extract_i32 for shifter_out_im
84
create mode 100644 hw/sd/sdmmc-internal.h
65
target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
66
target/arm: Remove redundant shift tests
67
target/arm: Use ror32 instead of open-coding the operation
68
target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
69
target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
70
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
85
71
72
target/arm/cpu.h | 13 +-
73
target/arm/helper.h | 1 -
74
target/arm/kvm_arm.h | 28 ++
75
target/arm/translate-a64.h | 4 +-
76
target/arm/translate.h | 39 ++-
77
hw/misc/zynq_slcr.c | 450 ++++++++++++++++----------------
78
hw/net/imx_fec.c | 4 +
79
target/arm/cpu.c | 30 ++-
80
target/arm/cpu64.c | 31 ++-
81
target/arm/helper.c | 7 +
82
target/arm/kvm.c | 7 +
83
target/arm/kvm64.c | 161 +++++++-----
84
target/arm/op_helper.c | 15 --
85
target/arm/translate-a64.c | 130 ++++------
86
target/arm/translate-vfp.inc.c | 45 +---
87
target/arm/translate.c | 572 +++++++++++++++++------------------------
88
16 files changed, 771 insertions(+), 766 deletions(-)
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/32] sdcard: simplify SD_SEND_OP_COND (ACMD41)
[Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
replace switch(single case) -> if()
3
While most features are now detected by probing the ID_* registers
4
kernels can (and do) use MIDR_EL1 for working out of they have to
5
apply errata. This can trip up warnings in the kernel as it tries to
6
work out if it should apply workarounds to features that don't
7
actually exist in the reported CPU type.
4
8
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Avoid this problem by synthesising our own MIDR value.
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
7
Message-id: 20180215221325.7611-17-f4bug@amsat.org
11
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20190726113950.7499-1-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
16
---
10
hw/sd/sd.c | 56 ++++++++++++++++++++++++++------------------------------
17
target/arm/cpu.h | 6 ++++++
11
1 file changed, 26 insertions(+), 30 deletions(-)
18
target/arm/cpu64.c | 19 +++++++++++++++++++
19
2 files changed, 25 insertions(+)
12
20
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
23
--- a/target/arm/cpu.h
16
+++ b/hw/sd/sd.c
24
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_app_command(SDState *sd,
25
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
18
sd->state = sd_transfer_state;
26
/*
19
return sd_r1;
27
* System register ID fields.
20
}
28
*/
21
- switch (sd->state) {
29
+FIELD(MIDR_EL1, REVISION, 0, 4)
22
- case sd_idle_state:
30
+FIELD(MIDR_EL1, PARTNUM, 4, 12)
23
- /* If it's the first ACMD41 since reset, we need to decide
31
+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
24
- * whether to power up. If this is not an enquiry ACMD41,
32
+FIELD(MIDR_EL1, VARIANT, 20, 4)
25
- * we immediately report power on and proceed below to the
33
+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
26
- * ready state, but if it is, we set a timer to model a
27
- * delay for power up. This works around a bug in EDK2
28
- * UEFI, which sends an initial enquiry ACMD41, but
29
- * assumes that the card is in ready state as soon as it
30
- * sees the power up bit set. */
31
- if (!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP)) {
32
- if ((req.arg & ACMD41_ENQUIRY_MASK) != 0) {
33
- timer_del(sd->ocr_power_timer);
34
- sd_ocr_powerup(sd);
35
- } else {
36
- trace_sdcard_inquiry_cmd41();
37
- if (!timer_pending(sd->ocr_power_timer)) {
38
- timer_mod_ns(sd->ocr_power_timer,
39
- (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
40
- + OCR_POWER_DELAY_NS));
41
- }
42
+ if (sd->state != sd_idle_state) {
43
+ break;
44
+ }
45
+ /* If it's the first ACMD41 since reset, we need to decide
46
+ * whether to power up. If this is not an enquiry ACMD41,
47
+ * we immediately report power on and proceed below to the
48
+ * ready state, but if it is, we set a timer to model a
49
+ * delay for power up. This works around a bug in EDK2
50
+ * UEFI, which sends an initial enquiry ACMD41, but
51
+ * assumes that the card is in ready state as soon as it
52
+ * sees the power up bit set. */
53
+ if (!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP)) {
54
+ if ((req.arg & ACMD41_ENQUIRY_MASK) != 0) {
55
+ timer_del(sd->ocr_power_timer);
56
+ sd_ocr_powerup(sd);
57
+ } else {
58
+ trace_sdcard_inquiry_cmd41();
59
+ if (!timer_pending(sd->ocr_power_timer)) {
60
+ timer_mod_ns(sd->ocr_power_timer,
61
+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
62
+ + OCR_POWER_DELAY_NS));
63
}
64
}
65
+ }
66
67
+ if (FIELD_EX32(sd->ocr & req.arg, OCR, VDD_VOLTAGE_WINDOW)) {
68
/* We accept any voltage. 10000 V is nothing.
69
*
70
* Once we're powered up, we advance straight to ready state
71
* unless it's an enquiry ACMD41 (bits 23:0 == 0).
72
*/
73
- if (req.arg & ACMD41_ENQUIRY_MASK) {
74
- sd->state = sd_ready_state;
75
- }
76
-
77
- return sd_r3;
78
-
79
- default:
80
- break;
81
+ sd->state = sd_ready_state;
82
}
83
- break;
84
+
34
+
85
+ return sd_r3;
35
FIELD(ID_ISAR0, SWAP, 0, 4)
86
36
FIELD(ID_ISAR0, BITCOUNT, 4, 4)
87
case 42:    /* ACMD42: SET_CLR_CARD_DETECT */
37
FIELD(ID_ISAR0, BITFIELD, 8, 4)
88
switch (sd->state) {
38
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu64.c
41
+++ b/target/arm/cpu64.c
42
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
43
uint32_t u;
44
aarch64_a57_initfn(obj);
45
46
+ /*
47
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
48
+ * one and try to apply errata workarounds or use impdef features we
49
+ * don't provide.
50
+ * An IMPLEMENTER field of 0 means "reserved for software use";
51
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
52
+ * to see which features are present";
53
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
54
+ * defined and we choose to define PARTNUM just in case guest
55
+ * code needs to distinguish this QEMU CPU from other software
56
+ * implementations, though this shouldn't be needed.
57
+ */
58
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
59
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
60
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
61
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
62
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
63
+ cpu->midr = t;
64
+
65
t = cpu->isar.id_aa64isar0;
66
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
67
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
89
--
68
--
90
2.16.1
69
2.20.1
91
70
92
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/32] sdcard: handle the Security Specification commands
[Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
2
3
returning sd_illegal, since they are not implemented.
3
Replace the zynq_slcr registers enum and macros using the
4
hw/registerfields.h macros.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20180215221325.7611-11-f4bug@amsat.org
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
[PMM: tweak multiline comment format]
9
Message-id: 20190729145654.14644-30-damien.hedde@greensocs.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/sd/sd.c | 12 ++++++++++++
12
hw/misc/zynq_slcr.c | 450 ++++++++++++++++++++++----------------------
12
1 file changed, 12 insertions(+)
13
1 file changed, 225 insertions(+), 225 deletions(-)
13
14
14
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
15
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/sd/sd.c
17
--- a/hw/misc/zynq_slcr.c
17
+++ b/hw/sd/sd.c
18
+++ b/hw/misc/zynq_slcr.c
18
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_app_command(SDState *sd,
19
@@ -XXX,XX +XXX,XX @@
20
#include "sysemu/sysemu.h"
21
#include "qemu/log.h"
22
#include "qemu/module.h"
23
+#include "hw/registerfields.h"
24
25
#ifndef ZYNQ_SLCR_ERR_DEBUG
26
#define ZYNQ_SLCR_ERR_DEBUG 0
27
@@ -XXX,XX +XXX,XX @@
28
#define XILINX_LOCK_KEY 0x767b
29
#define XILINX_UNLOCK_KEY 0xdf0d
30
31
-#define R_PSS_RST_CTRL_SOFT_RST 0x1
32
+REG32(SCL, 0x000)
33
+REG32(LOCK, 0x004)
34
+REG32(UNLOCK, 0x008)
35
+REG32(LOCKSTA, 0x00c)
36
37
-enum {
38
- SCL = 0x000 / 4,
39
- LOCK,
40
- UNLOCK,
41
- LOCKSTA,
42
+REG32(ARM_PLL_CTRL, 0x100)
43
+REG32(DDR_PLL_CTRL, 0x104)
44
+REG32(IO_PLL_CTRL, 0x108)
45
+REG32(PLL_STATUS, 0x10c)
46
+REG32(ARM_PLL_CFG, 0x110)
47
+REG32(DDR_PLL_CFG, 0x114)
48
+REG32(IO_PLL_CFG, 0x118)
49
50
- ARM_PLL_CTRL = 0x100 / 4,
51
- DDR_PLL_CTRL,
52
- IO_PLL_CTRL,
53
- PLL_STATUS,
54
- ARM_PLL_CFG,
55
- DDR_PLL_CFG,
56
- IO_PLL_CFG,
57
-
58
- ARM_CLK_CTRL = 0x120 / 4,
59
- DDR_CLK_CTRL,
60
- DCI_CLK_CTRL,
61
- APER_CLK_CTRL,
62
- USB0_CLK_CTRL,
63
- USB1_CLK_CTRL,
64
- GEM0_RCLK_CTRL,
65
- GEM1_RCLK_CTRL,
66
- GEM0_CLK_CTRL,
67
- GEM1_CLK_CTRL,
68
- SMC_CLK_CTRL,
69
- LQSPI_CLK_CTRL,
70
- SDIO_CLK_CTRL,
71
- UART_CLK_CTRL,
72
- SPI_CLK_CTRL,
73
- CAN_CLK_CTRL,
74
- CAN_MIOCLK_CTRL,
75
- DBG_CLK_CTRL,
76
- PCAP_CLK_CTRL,
77
- TOPSW_CLK_CTRL,
78
+REG32(ARM_CLK_CTRL, 0x120)
79
+REG32(DDR_CLK_CTRL, 0x124)
80
+REG32(DCI_CLK_CTRL, 0x128)
81
+REG32(APER_CLK_CTRL, 0x12c)
82
+REG32(USB0_CLK_CTRL, 0x130)
83
+REG32(USB1_CLK_CTRL, 0x134)
84
+REG32(GEM0_RCLK_CTRL, 0x138)
85
+REG32(GEM1_RCLK_CTRL, 0x13c)
86
+REG32(GEM0_CLK_CTRL, 0x140)
87
+REG32(GEM1_CLK_CTRL, 0x144)
88
+REG32(SMC_CLK_CTRL, 0x148)
89
+REG32(LQSPI_CLK_CTRL, 0x14c)
90
+REG32(SDIO_CLK_CTRL, 0x150)
91
+REG32(UART_CLK_CTRL, 0x154)
92
+REG32(SPI_CLK_CTRL, 0x158)
93
+REG32(CAN_CLK_CTRL, 0x15c)
94
+REG32(CAN_MIOCLK_CTRL, 0x160)
95
+REG32(DBG_CLK_CTRL, 0x164)
96
+REG32(PCAP_CLK_CTRL, 0x168)
97
+REG32(TOPSW_CLK_CTRL, 0x16c)
98
99
#define FPGA_CTRL_REGS(n, start) \
100
- FPGA ## n ## _CLK_CTRL = (start) / 4, \
101
- FPGA ## n ## _THR_CTRL, \
102
- FPGA ## n ## _THR_CNT, \
103
- FPGA ## n ## _THR_STA,
104
- FPGA_CTRL_REGS(0, 0x170)
105
- FPGA_CTRL_REGS(1, 0x180)
106
- FPGA_CTRL_REGS(2, 0x190)
107
- FPGA_CTRL_REGS(3, 0x1a0)
108
+ REG32(FPGA ## n ## _CLK_CTRL, (start)) \
109
+ REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
110
+ REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\
111
+ REG32(FPGA ## n ## _THR_STA, (start) + 0xc)
112
+FPGA_CTRL_REGS(0, 0x170)
113
+FPGA_CTRL_REGS(1, 0x180)
114
+FPGA_CTRL_REGS(2, 0x190)
115
+FPGA_CTRL_REGS(3, 0x1a0)
116
117
- BANDGAP_TRIP = 0x1b8 / 4,
118
- PLL_PREDIVISOR = 0x1c0 / 4,
119
- CLK_621_TRUE,
120
+REG32(BANDGAP_TRIP, 0x1b8)
121
+REG32(PLL_PREDIVISOR, 0x1c0)
122
+REG32(CLK_621_TRUE, 0x1c4)
123
124
- PSS_RST_CTRL = 0x200 / 4,
125
- DDR_RST_CTRL,
126
- TOPSW_RESET_CTRL,
127
- DMAC_RST_CTRL,
128
- USB_RST_CTRL,
129
- GEM_RST_CTRL,
130
- SDIO_RST_CTRL,
131
- SPI_RST_CTRL,
132
- CAN_RST_CTRL,
133
- I2C_RST_CTRL,
134
- UART_RST_CTRL,
135
- GPIO_RST_CTRL,
136
- LQSPI_RST_CTRL,
137
- SMC_RST_CTRL,
138
- OCM_RST_CTRL,
139
- FPGA_RST_CTRL = 0x240 / 4,
140
- A9_CPU_RST_CTRL,
141
+REG32(PSS_RST_CTRL, 0x200)
142
+ FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
143
+REG32(DDR_RST_CTRL, 0x204)
144
+REG32(TOPSW_RESET_CTRL, 0x208)
145
+REG32(DMAC_RST_CTRL, 0x20c)
146
+REG32(USB_RST_CTRL, 0x210)
147
+REG32(GEM_RST_CTRL, 0x214)
148
+REG32(SDIO_RST_CTRL, 0x218)
149
+REG32(SPI_RST_CTRL, 0x21c)
150
+REG32(CAN_RST_CTRL, 0x220)
151
+REG32(I2C_RST_CTRL, 0x224)
152
+REG32(UART_RST_CTRL, 0x228)
153
+REG32(GPIO_RST_CTRL, 0x22c)
154
+REG32(LQSPI_RST_CTRL, 0x230)
155
+REG32(SMC_RST_CTRL, 0x234)
156
+REG32(OCM_RST_CTRL, 0x238)
157
+REG32(FPGA_RST_CTRL, 0x240)
158
+REG32(A9_CPU_RST_CTRL, 0x244)
159
160
- RS_AWDT_CTRL = 0x24c / 4,
161
- RST_REASON,
162
+REG32(RS_AWDT_CTRL, 0x24c)
163
+REG32(RST_REASON, 0x250)
164
165
- REBOOT_STATUS = 0x258 / 4,
166
- BOOT_MODE,
167
+REG32(REBOOT_STATUS, 0x258)
168
+REG32(BOOT_MODE, 0x25c)
169
170
- APU_CTRL = 0x300 / 4,
171
- WDT_CLK_SEL,
172
+REG32(APU_CTRL, 0x300)
173
+REG32(WDT_CLK_SEL, 0x304)
174
175
- TZ_DMA_NS = 0x440 / 4,
176
- TZ_DMA_IRQ_NS,
177
- TZ_DMA_PERIPH_NS,
178
+REG32(TZ_DMA_NS, 0x440)
179
+REG32(TZ_DMA_IRQ_NS, 0x444)
180
+REG32(TZ_DMA_PERIPH_NS, 0x448)
181
182
- PSS_IDCODE = 0x530 / 4,
183
+REG32(PSS_IDCODE, 0x530)
184
185
- DDR_URGENT = 0x600 / 4,
186
- DDR_CAL_START = 0x60c / 4,
187
- DDR_REF_START = 0x614 / 4,
188
- DDR_CMD_STA,
189
- DDR_URGENT_SEL,
190
- DDR_DFI_STATUS,
191
+REG32(DDR_URGENT, 0x600)
192
+REG32(DDR_CAL_START, 0x60c)
193
+REG32(DDR_REF_START, 0x614)
194
+REG32(DDR_CMD_STA, 0x618)
195
+REG32(DDR_URGENT_SEL, 0x61c)
196
+REG32(DDR_DFI_STATUS, 0x620)
197
198
- MIO = 0x700 / 4,
199
+REG32(MIO, 0x700)
200
#define MIO_LENGTH 54
201
202
- MIO_LOOPBACK = 0x804 / 4,
203
- MIO_MST_TRI0,
204
- MIO_MST_TRI1,
205
+REG32(MIO_LOOPBACK, 0x804)
206
+REG32(MIO_MST_TRI0, 0x808)
207
+REG32(MIO_MST_TRI1, 0x80c)
208
209
- SD0_WP_CD_SEL = 0x830 / 4,
210
- SD1_WP_CD_SEL,
211
+REG32(SD0_WP_CD_SEL, 0x830)
212
+REG32(SD1_WP_CD_SEL, 0x834)
213
214
- LVL_SHFTR_EN = 0x900 / 4,
215
- OCM_CFG = 0x910 / 4,
216
+REG32(LVL_SHFTR_EN, 0x900)
217
+REG32(OCM_CFG, 0x910)
218
219
- CPU_RAM = 0xa00 / 4,
220
+REG32(CPU_RAM, 0xa00)
221
222
- IOU = 0xa30 / 4,
223
+REG32(IOU, 0xa30)
224
225
- DMAC_RAM = 0xa50 / 4,
226
+REG32(DMAC_RAM, 0xa50)
227
228
- AFI0 = 0xa60 / 4,
229
- AFI1 = AFI0 + 3,
230
- AFI2 = AFI1 + 3,
231
- AFI3 = AFI2 + 3,
232
+REG32(AFI0, 0xa60)
233
+REG32(AFI1, 0xa6c)
234
+REG32(AFI2, 0xa78)
235
+REG32(AFI3, 0xa84)
236
#define AFI_LENGTH 3
237
238
- OCM = 0xa90 / 4,
239
+REG32(OCM, 0xa90)
240
241
- DEVCI_RAM = 0xaa0 / 4,
242
+REG32(DEVCI_RAM, 0xaa0)
243
244
- CSG_RAM = 0xab0 / 4,
245
+REG32(CSG_RAM, 0xab0)
246
247
- GPIOB_CTRL = 0xb00 / 4,
248
- GPIOB_CFG_CMOS18,
249
- GPIOB_CFG_CMOS25,
250
- GPIOB_CFG_CMOS33,
251
- GPIOB_CFG_HSTL = 0xb14 / 4,
252
- GPIOB_DRVR_BIAS_CTRL,
253
+REG32(GPIOB_CTRL, 0xb00)
254
+REG32(GPIOB_CFG_CMOS18, 0xb04)
255
+REG32(GPIOB_CFG_CMOS25, 0xb08)
256
+REG32(GPIOB_CFG_CMOS33, 0xb0c)
257
+REG32(GPIOB_CFG_HSTL, 0xb14)
258
+REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)
259
260
- DDRIOB = 0xb40 / 4,
261
+REG32(DDRIOB, 0xb40)
262
#define DDRIOB_LENGTH 14
263
-};
264
265
#define ZYNQ_SLCR_MMIO_SIZE 0x1000
266
#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
267
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d)
268
269
DB_PRINT("RESET\n");
270
271
- s->regs[LOCKSTA] = 1;
272
+ s->regs[R_LOCKSTA] = 1;
273
/* 0x100 - 0x11C */
274
- s->regs[ARM_PLL_CTRL] = 0x0001A008;
275
- s->regs[DDR_PLL_CTRL] = 0x0001A008;
276
- s->regs[IO_PLL_CTRL] = 0x0001A008;
277
- s->regs[PLL_STATUS] = 0x0000003F;
278
- s->regs[ARM_PLL_CFG] = 0x00014000;
279
- s->regs[DDR_PLL_CFG] = 0x00014000;
280
- s->regs[IO_PLL_CFG] = 0x00014000;
281
+ s->regs[R_ARM_PLL_CTRL] = 0x0001A008;
282
+ s->regs[R_DDR_PLL_CTRL] = 0x0001A008;
283
+ s->regs[R_IO_PLL_CTRL] = 0x0001A008;
284
+ s->regs[R_PLL_STATUS] = 0x0000003F;
285
+ s->regs[R_ARM_PLL_CFG] = 0x00014000;
286
+ s->regs[R_DDR_PLL_CFG] = 0x00014000;
287
+ s->regs[R_IO_PLL_CFG] = 0x00014000;
288
289
/* 0x120 - 0x16C */
290
- s->regs[ARM_CLK_CTRL] = 0x1F000400;
291
- s->regs[DDR_CLK_CTRL] = 0x18400003;
292
- s->regs[DCI_CLK_CTRL] = 0x01E03201;
293
- s->regs[APER_CLK_CTRL] = 0x01FFCCCD;
294
- s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;
295
- s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;
296
- s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;
297
- s->regs[SMC_CLK_CTRL] = 0x00003C01;
298
- s->regs[LQSPI_CLK_CTRL] = 0x00002821;
299
- s->regs[SDIO_CLK_CTRL] = 0x00001E03;
300
- s->regs[UART_CLK_CTRL] = 0x00003F03;
301
- s->regs[SPI_CLK_CTRL] = 0x00003F03;
302
- s->regs[CAN_CLK_CTRL] = 0x00501903;
303
- s->regs[DBG_CLK_CTRL] = 0x00000F03;
304
- s->regs[PCAP_CLK_CTRL] = 0x00000F01;
305
+ s->regs[R_ARM_CLK_CTRL] = 0x1F000400;
306
+ s->regs[R_DDR_CLK_CTRL] = 0x18400003;
307
+ s->regs[R_DCI_CLK_CTRL] = 0x01E03201;
308
+ s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD;
309
+ s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941;
310
+ s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;
311
+ s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01;
312
+ s->regs[R_SMC_CLK_CTRL] = 0x00003C01;
313
+ s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;
314
+ s->regs[R_SDIO_CLK_CTRL] = 0x00001E03;
315
+ s->regs[R_UART_CLK_CTRL] = 0x00003F03;
316
+ s->regs[R_SPI_CLK_CTRL] = 0x00003F03;
317
+ s->regs[R_CAN_CLK_CTRL] = 0x00501903;
318
+ s->regs[R_DBG_CLK_CTRL] = 0x00000F03;
319
+ s->regs[R_PCAP_CLK_CTRL] = 0x00000F01;
320
321
/* 0x170 - 0x1AC */
322
- s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
323
- = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
324
- s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
325
- = s->regs[FPGA3_THR_STA] = 0x00010000;
326
+ s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL]
327
+ = s->regs[R_FPGA2_CLK_CTRL]
328
+ = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;
329
+ s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA]
330
+ = s->regs[R_FPGA2_THR_STA]
331
+ = s->regs[R_FPGA3_THR_STA] = 0x00010000;
332
333
/* 0x1B0 - 0x1D8 */
334
- s->regs[BANDGAP_TRIP] = 0x0000001F;
335
- s->regs[PLL_PREDIVISOR] = 0x00000001;
336
- s->regs[CLK_621_TRUE] = 0x00000001;
337
+ s->regs[R_BANDGAP_TRIP] = 0x0000001F;
338
+ s->regs[R_PLL_PREDIVISOR] = 0x00000001;
339
+ s->regs[R_CLK_621_TRUE] = 0x00000001;
340
341
/* 0x200 - 0x25C */
342
- s->regs[FPGA_RST_CTRL] = 0x01F33F0F;
343
- s->regs[RST_REASON] = 0x00000040;
344
+ s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F;
345
+ s->regs[R_RST_REASON] = 0x00000040;
346
347
- s->regs[BOOT_MODE] = 0x00000001;
348
+ s->regs[R_BOOT_MODE] = 0x00000001;
349
350
/* 0x700 - 0x7D4 */
351
for (i = 0; i < 54; i++) {
352
- s->regs[MIO + i] = 0x00001601;
353
+ s->regs[R_MIO + i] = 0x00001601;
354
}
355
for (i = 2; i <= 8; i++) {
356
- s->regs[MIO + i] = 0x00000601;
357
+ s->regs[R_MIO + i] = 0x00000601;
358
}
359
360
- s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
361
+ s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;
362
363
- s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
364
- = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
365
- = 0x00010101;
366
- s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
367
- s->regs[CPU_RAM + 6] = 0x00000001;
368
+ s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]
369
+ = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7]
370
+ = 0x00010101;
371
+ s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;
372
+ s->regs[R_CPU_RAM + 6] = 0x00000001;
373
374
- s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
375
- = 0x09090909;
376
- s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
377
- s->regs[IOU + 6] = 0x00000909;
378
+ s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]
379
+ = s->regs[R_IOU + 3] = 0x09090909;
380
+ s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;
381
+ s->regs[R_IOU + 6] = 0x00000909;
382
383
- s->regs[DMAC_RAM] = 0x00000009;
384
+ s->regs[R_DMAC_RAM] = 0x00000009;
385
386
- s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
387
- s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
388
- s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
389
- s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
390
- s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
391
- = s->regs[AFI3 + 2] = 0x00000909;
392
+ s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;
393
+ s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;
394
+ s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;
395
+ s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;
396
+ s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2]
397
+ = s->regs[R_AFI3 + 2] = 0x00000909;
398
399
- s->regs[OCM + 0] = 0x01010101;
400
- s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;
401
+ s->regs[R_OCM + 0] = 0x01010101;
402
+ s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;
403
404
- s->regs[DEVCI_RAM] = 0x00000909;
405
- s->regs[CSG_RAM] = 0x00000001;
406
+ s->regs[R_DEVCI_RAM] = 0x00000909;
407
+ s->regs[R_CSG_RAM] = 0x00000001;
408
409
- s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
410
- = s->regs[DDRIOB + 3] = 0x00000e00;
411
- s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
412
- = 0x00000e00;
413
- s->regs[DDRIOB + 12] = 0x00000021;
414
+ s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]
415
+ = s->regs[R_DDRIOB + 3] = 0x00000e00;
416
+ s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6]
417
+ = 0x00000e00;
418
+ s->regs[R_DDRIOB + 12] = 0x00000021;
419
}
420
421
422
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
423
{
424
switch (offset) {
425
- case LOCK:
426
- case UNLOCK:
427
- case DDR_CAL_START:
428
- case DDR_REF_START:
429
+ case R_LOCK:
430
+ case R_UNLOCK:
431
+ case R_DDR_CAL_START:
432
+ case R_DDR_REF_START:
433
return !rnw; /* Write only */
434
- case LOCKSTA:
435
- case FPGA0_THR_STA:
436
- case FPGA1_THR_STA:
437
- case FPGA2_THR_STA:
438
- case FPGA3_THR_STA:
439
- case BOOT_MODE:
440
- case PSS_IDCODE:
441
- case DDR_CMD_STA:
442
- case DDR_DFI_STATUS:
443
- case PLL_STATUS:
444
+ case R_LOCKSTA:
445
+ case R_FPGA0_THR_STA:
446
+ case R_FPGA1_THR_STA:
447
+ case R_FPGA2_THR_STA:
448
+ case R_FPGA3_THR_STA:
449
+ case R_BOOT_MODE:
450
+ case R_PSS_IDCODE:
451
+ case R_DDR_CMD_STA:
452
+ case R_DDR_DFI_STATUS:
453
+ case R_PLL_STATUS:
454
return rnw;/* read only */
455
- case SCL:
456
- case ARM_PLL_CTRL ... IO_PLL_CTRL:
457
- case ARM_PLL_CFG ... IO_PLL_CFG:
458
- case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
459
- case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
460
- case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
461
- case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
462
- case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
463
- case BANDGAP_TRIP:
464
- case PLL_PREDIVISOR:
465
- case CLK_621_TRUE:
466
- case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
467
- case RS_AWDT_CTRL:
468
- case RST_REASON:
469
- case REBOOT_STATUS:
470
- case APU_CTRL:
471
- case WDT_CLK_SEL:
472
- case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
473
- case DDR_URGENT:
474
- case DDR_URGENT_SEL:
475
- case MIO ... MIO + MIO_LENGTH - 1:
476
- case MIO_LOOPBACK ... MIO_MST_TRI1:
477
- case SD0_WP_CD_SEL:
478
- case SD1_WP_CD_SEL:
479
- case LVL_SHFTR_EN:
480
- case OCM_CFG:
481
- case CPU_RAM:
482
- case IOU:
483
- case DMAC_RAM:
484
- case AFI0 ... AFI3 + AFI_LENGTH - 1:
485
- case OCM:
486
- case DEVCI_RAM:
487
- case CSG_RAM:
488
- case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
489
- case GPIOB_CFG_HSTL:
490
- case GPIOB_DRVR_BIAS_CTRL:
491
- case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
492
+ case R_SCL:
493
+ case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL:
494
+ case R_ARM_PLL_CFG ... R_IO_PLL_CFG:
495
+ case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL:
496
+ case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT:
497
+ case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT:
498
+ case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT:
499
+ case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT:
500
+ case R_BANDGAP_TRIP:
501
+ case R_PLL_PREDIVISOR:
502
+ case R_CLK_621_TRUE:
503
+ case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL:
504
+ case R_RS_AWDT_CTRL:
505
+ case R_RST_REASON:
506
+ case R_REBOOT_STATUS:
507
+ case R_APU_CTRL:
508
+ case R_WDT_CLK_SEL:
509
+ case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS:
510
+ case R_DDR_URGENT:
511
+ case R_DDR_URGENT_SEL:
512
+ case R_MIO ... R_MIO + MIO_LENGTH - 1:
513
+ case R_MIO_LOOPBACK ... R_MIO_MST_TRI1:
514
+ case R_SD0_WP_CD_SEL:
515
+ case R_SD1_WP_CD_SEL:
516
+ case R_LVL_SHFTR_EN:
517
+ case R_OCM_CFG:
518
+ case R_CPU_RAM:
519
+ case R_IOU:
520
+ case R_DMAC_RAM:
521
+ case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1:
522
+ case R_OCM:
523
+ case R_DEVCI_RAM:
524
+ case R_CSG_RAM:
525
+ case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33:
526
+ case R_GPIOB_CFG_HSTL:
527
+ case R_GPIOB_DRVR_BIAS_CTRL:
528
+ case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1:
529
return true;
530
default:
531
return false;
532
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
533
}
534
535
switch (offset) {
536
- case SCL:
537
- s->regs[SCL] = val & 0x1;
538
+ case R_SCL:
539
+ s->regs[R_SCL] = val & 0x1;
540
return;
541
- case LOCK:
542
+ case R_LOCK:
543
if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
544
DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
545
(unsigned)val & 0xFFFF);
546
- s->regs[LOCKSTA] = 1;
547
+ s->regs[R_LOCKSTA] = 1;
548
} else {
549
DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
550
(int)offset, (unsigned)val & 0xFFFF);
551
}
552
return;
553
- case UNLOCK:
554
+ case R_UNLOCK:
555
if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
556
DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
557
(unsigned)val & 0xFFFF);
558
- s->regs[LOCKSTA] = 0;
559
+ s->regs[R_LOCKSTA] = 0;
560
} else {
561
DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
562
(int)offset, (unsigned)val & 0xFFFF);
563
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
564
return;
565
}
566
567
- if (s->regs[LOCKSTA]) {
568
+ if (s->regs[R_LOCKSTA]) {
569
qemu_log_mask(LOG_GUEST_ERROR,
570
"SCLR registers are locked. Unlock them first\n");
571
return;
572
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
573
s->regs[offset] = val;
574
575
switch (offset) {
576
- case PSS_RST_CTRL:
577
- if (val & R_PSS_RST_CTRL_SOFT_RST) {
578
+ case R_PSS_RST_CTRL:
579
+ if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
580
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
19
}
581
}
20
break;
582
break;
21
22
+ case 18: /* Reserved for SD security applications */
23
+ case 25:
24
+ case 26:
25
+ case 38:
26
+ case 43 ... 49:
27
+ /* Refer to the "SD Specifications Part3 Security Specification" for
28
+ * information about the SD Security Features.
29
+ */
30
+ qemu_log_mask(LOG_UNIMP, "SD: CMD%i Security not implemented\n",
31
+ req.cmd);
32
+ return sd_illegal;
33
+
34
default:
35
/* Fall back to standard commands. */
36
return sd_normal_command(sd, req);
37
--
583
--
38
2.16.1
584
2.20.1
39
585
40
586
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/32] sdcard: simplify SEND_IF_COND (CMD8)
[Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Aaron Hill <aa1ronham@gmail.com>
2
2
3
replace switch(single case) -> if()
3
This commit properly sets the ENET_BD_BDU flag once the emulated FEC controller
4
has finished processing the last descriptor. This is done for both transmit
5
and receive descriptors.
4
6
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
This allows the QNX 7.0.0 BSP for the Sabrelite board (which can be
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
found at http://blackberry.qnx.com/en/developers/bsp) to properly
7
Message-id: 20180215221325.7611-16-f4bug@amsat.org
9
control the FEC. Without this patch, the BSP ethernet driver will never
10
re-use FEC descriptors, as the unset ENET_BD_BDU flag will cause
11
it to believe that the descriptors are still in use by the NIC.
12
13
Note that Linux does not appear to use this field at all, and is
14
unaffected by this patch.
15
16
Without this patch, QNX will think that the NIC is still processing its
17
transaction descriptors, and won't send any more data over the network.
18
19
For reference:
20
21
On page 1192 of the I.MX 6DQ reference manual revision (Rev. 5, 06/2018),
22
which can be found at https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q?&tab=Documentation_Tab&linkline=Application-Note
23
24
the 'BDU' field is described as follows for the 'Enhanced transmit
25
buffer descriptor':
26
27
'Last buffer descriptor update done. Indicates that the last BD data has been updated by
28
uDMA. This field is written by the user (=0) and uDMA (=1).'
29
30
The same description is used for the receive buffer descriptor.
31
32
Signed-off-by: Aaron Hill <aa1ronham@gmail.com>
33
Message-id: 20190805142417.10433-1-aaron.hill@alertinnovation.com
34
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
36
---
10
hw/sd/sd.c | 26 +++++++++++---------------
37
hw/net/imx_fec.c | 4 ++++
11
1 file changed, 11 insertions(+), 15 deletions(-)
38
1 file changed, 4 insertions(+)
12
39
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
40
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
14
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
42
--- a/hw/net/imx_fec.c
16
+++ b/hw/sd/sd.c
43
+++ b/hw/net/imx_fec.c
17
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
44
@@ -XXX,XX +XXX,XX @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
18
45
if (bd.option & ENET_BD_TX_INT) {
19
case 8:    /* CMD8: SEND_IF_COND */
46
s->regs[ENET_EIR] |= int_txf;
20
/* Physical Layer Specification Version 2.00 command */
47
}
21
- switch (sd->state) {
48
+ /* Indicate that we've updated the last buffer descriptor. */
22
- case sd_idle_state:
49
+ bd.last_buffer = ENET_BD_BDU;
23
- sd->vhs = 0;
24
-
25
- /* No response if not exactly one VHS bit is set. */
26
- if (!(req.arg >> 8) || (req.arg >> (ctz32(req.arg & ~0xff) + 1))) {
27
- return sd->spi ? sd_r7 : sd_r0;
28
- }
29
-
30
- /* Accept. */
31
- sd->vhs = req.arg;
32
- return sd_r7;
33
-
34
- default:
35
+ if (sd->state != sd_idle_state) {
36
break;
37
}
50
}
38
- break;
51
if (bd.option & ENET_BD_TX_INT) {
39
+ sd->vhs = 0;
52
s->regs[ENET_EIR] |= int_txb;
40
+
53
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
41
+ /* No response if not exactly one VHS bit is set. */
54
/* Last buffer in frame. */
42
+ if (!(req.arg >> 8) || (req.arg >> (ctz32(req.arg & ~0xff) + 1))) {
55
bd.flags |= flags | ENET_BD_L;
43
+ return sd->spi ? sd_r7 : sd_r0;
56
FEC_PRINTF("rx frame flags %04x\n", bd.flags);
44
+ }
57
+ /* Indicate that we've updated the last buffer descriptor. */
45
+
58
+ bd.last_buffer = ENET_BD_BDU;
46
+ /* Accept. */
59
if (bd.option & ENET_BD_RX_INT) {
47
+ sd->vhs = req.arg;
60
s->regs[ENET_EIR] |= ENET_INT_RXF;
48
+ return sd_r7;
61
}
49
50
case 9:    /* CMD9: SEND_CSD */
51
switch (sd->state) {
52
--
62
--
53
2.16.1
63
2.20.1
54
64
55
65
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/32] sdcard: use the correct masked OCR in the R3 reply
[Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Factor out code to 'generate a singlestep exception', which is
2
currently repeated in four places.
2
3
3
use the registerfields API to access the OCR register
4
To do this we need to also pull the identical copies of the
5
gen-exception() function out of translate-a64.c and translate.c
6
into translate.h.
4
7
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
(There is a bug in the code: we're taking the exception to the wrong
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
target EL. This will be simpler to fix if there's only one place to
7
Message-id: 20180215221325.7611-8-f4bug@amsat.org
10
do it.)
11
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20190805130952.4415-2-peter.maydell@linaro.org
9
---
16
---
10
hw/sd/sd.c | 21 ++++++++++++++++-----
17
target/arm/translate.h | 23 +++++++++++++++++++++++
11
1 file changed, 16 insertions(+), 5 deletions(-)
18
target/arm/translate-a64.c | 19 ++-----------------
19
target/arm/translate.c | 20 ++------------------
20
3 files changed, 27 insertions(+), 35 deletions(-)
12
21
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
22
diff --git a/target/arm/translate.h b/target/arm/translate.h
14
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
24
--- a/target/arm/translate.h
16
+++ b/hw/sd/sd.c
25
+++ b/target/arm/translate.h
17
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@
18
27
#define TARGET_ARM_TRANSLATE_H
19
//#define DEBUG_SD 1
28
20
29
#include "exec/translator.h"
21
-#define ACMD41_ENQUIRY_MASK 0x00ffffff
30
+#include "internals.h"
31
32
33
/* internal defines */
34
@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
35
}
36
}
37
38
+static inline void gen_exception(int excp, uint32_t syndrome,
39
+ uint32_t target_el)
40
+{
41
+ TCGv_i32 tcg_excp = tcg_const_i32(excp);
42
+ TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
43
+ TCGv_i32 tcg_el = tcg_const_i32(target_el);
44
+
45
+ gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
46
+ tcg_syn, tcg_el);
47
+
48
+ tcg_temp_free_i32(tcg_el);
49
+ tcg_temp_free_i32(tcg_syn);
50
+ tcg_temp_free_i32(tcg_excp);
51
+}
52
+
53
+/* Generate an architectural singlestep exception */
54
+static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
55
+{
56
+ gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
57
+ default_exception_el(s));
58
+}
59
+
60
/*
61
* Given a VFP floating point constant encoded into an 8 bit immediate in an
62
* instruction, expand it to the actual constant value of the specified
63
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/translate-a64.c
66
+++ b/target/arm/translate-a64.c
67
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
68
tcg_temp_free_i32(tcg_excp);
69
}
70
71
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
72
-{
73
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
74
- TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
75
- TCGv_i32 tcg_el = tcg_const_i32(target_el);
22
-
76
-
23
typedef enum {
77
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
24
sd_r0 = 0, /* no response */
78
- tcg_syn, tcg_el);
25
sd_r1, /* normal response command */
79
- tcg_temp_free_i32(tcg_el);
26
@@ -XXX,XX +XXX,XX @@ static uint16_t sd_crc16(void *message, size_t width)
80
- tcg_temp_free_i32(tcg_syn);
27
81
- tcg_temp_free_i32(tcg_excp);
28
#define OCR_POWER_DELAY_NS 500000 /* 0.5ms */
82
-}
29
83
-
30
+FIELD(OCR, VDD_VOLTAGE_WINDOW, 0, 24)
84
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
31
+FIELD(OCR, VDD_VOLTAGE_WIN_LO, 0, 8)
32
+FIELD(OCR, DUAL_VOLTAGE_CARD, 7, 1)
33
+FIELD(OCR, VDD_VOLTAGE_WIN_HI, 8, 16)
34
+FIELD(OCR, ACCEPT_SWITCH_1V8, 24, 1) /* Only UHS-I */
35
+FIELD(OCR, UHS_II_CARD, 29, 1) /* Only UHS-II */
36
FIELD(OCR, CARD_CAPACITY, 30, 1) /* 0:SDSC, 1:SDHC/SDXC */
37
FIELD(OCR, CARD_POWER_UP, 31, 1)
38
39
+#define ACMD41_ENQUIRY_MASK 0x00ffffff
40
+#define ACMD41_R3_MASK (R_OCR_VDD_VOLTAGE_WIN_HI_MASK \
41
+ | R_OCR_ACCEPT_SWITCH_1V8_MASK \
42
+ | R_OCR_UHS_II_CARD_MASK \
43
+ | R_OCR_CARD_CAPACITY_MASK \
44
+ | R_OCR_CARD_POWER_UP_MASK)
45
+
46
static void sd_set_ocr(SDState *sd)
47
{
85
{
48
- /* All voltages OK, Standard Capacity SD Memory Card, not yet powered up */
86
gen_a64_set_pc_im(s->pc - offset);
49
- sd->ocr = 0x00ffff00;
87
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
50
+ /* All voltages OK */
88
* of the exception, and our syndrome information is always correct.
51
+ sd->ocr = R_OCR_VDD_VOLTAGE_WIN_HI_MASK;
89
*/
90
gen_ss_advance(s);
91
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
92
- default_exception_el(s));
93
+ gen_swstep_exception(s, 1, s->is_ldex);
94
s->base.is_jmp = DISAS_NORETURN;
52
}
95
}
53
96
54
static void sd_ocr_powerup(void *opaque)
97
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
55
@@ -XXX,XX +XXX,XX @@ static void sd_response_r1_make(SDState *sd, uint8_t *response)
98
* bits should be zero.
56
99
*/
57
static void sd_response_r3_make(SDState *sd, uint8_t *response)
100
assert(dc->base.num_insns == 1);
101
- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
102
- default_exception_el(dc));
103
+ gen_swstep_exception(dc, 0, 0);
104
dc->base.is_jmp = DISAS_NORETURN;
105
} else {
106
disas_a64_insn(env, dc);
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
112
tcg_temp_free_i32(tcg_excp);
113
}
114
115
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
116
-{
117
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
118
- TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
119
- TCGv_i32 tcg_el = tcg_const_i32(target_el);
120
-
121
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
122
- tcg_syn, tcg_el);
123
-
124
- tcg_temp_free_i32(tcg_el);
125
- tcg_temp_free_i32(tcg_syn);
126
- tcg_temp_free_i32(tcg_excp);
127
-}
128
-
129
static void gen_step_complete_exception(DisasContext *s)
58
{
130
{
59
- stl_be_p(response, sd->ocr);
131
/* We just completed step of an insn. Move from Active-not-pending
60
+ stl_be_p(response, sd->ocr & ACMD41_R3_MASK);
132
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
133
* of the exception, and our syndrome information is always correct.
134
*/
135
gen_ss_advance(s);
136
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
137
- default_exception_el(s));
138
+ gen_swstep_exception(s, 1, s->is_ldex);
139
s->base.is_jmp = DISAS_NORETURN;
61
}
140
}
62
141
63
static void sd_response_r6_make(SDState *sd, uint8_t *response)
142
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
143
* bits should be zero.
144
*/
145
assert(dc->base.num_insns == 1);
146
- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
147
- default_exception_el(dc));
148
+ gen_swstep_exception(dc, 0, 0);
149
dc->base.is_jmp = DISAS_NORETURN;
150
return true;
151
}
64
--
152
--
65
2.16.1
153
2.20.1
66
154
67
155
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/32] sdcard: replace fprintf() by qemu_hexdump()
[Qemu-devel] [PULL 05/29] target/arm: Fix routing of singlestep exceptions
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
When generating an architectural single-step exception we were
2
routing it to the "default exception level", which is to say
3
the same exception level we execute at except that EL0 exceptions
4
go to EL1. This is incorrect because the debug exception level
5
can be configured by the guest for situations such as single
6
stepping of EL0 and EL1 code by EL2.
2
7
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
We have to track the target debug exception level in the TB
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
flags, because it is dependent on CPU state like HCR_EL2.TGE
5
Message-id: 20180215220540.6556-5-f4bug@amsat.org
10
and MDCR_EL2.TDE. (That we were previously calling the
11
arm_debug_target_el() function to determine dc->ss_same_el
12
is itself a bug, though one that would only have manifested
13
as incorrect syndrome information.) Since we are out of TB
14
flag bits unless we want to expand into the cs_base field,
15
we share some bits with the M-profile only HANDLER and
16
STACKCHECK bits, since only A-profile has this singlestep.
17
18
Fixes: https://bugs.launchpad.net/qemu/+bug/1838913
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
21
Tested-by: Alex Bennée <alex.bennee@linaro.org>
22
Message-id: 20190805130952.4415-3-peter.maydell@linaro.org
7
---
23
---
8
hw/sd/sd.c | 16 +---------------
24
target/arm/cpu.h | 5 +++++
9
1 file changed, 1 insertion(+), 15 deletions(-)
25
target/arm/translate.h | 15 +++++++++++----
26
target/arm/helper.c | 6 ++++++
27
target/arm/translate-a64.c | 2 +-
28
target/arm/translate.c | 4 +++-
29
5 files changed, 26 insertions(+), 6 deletions(-)
10
30
11
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sd.c
33
--- a/target/arm/cpu.h
14
+++ b/hw/sd/sd.c
34
+++ b/target/arm/cpu.h
15
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
16
36
/* Target EL if we take a floating-point-disabled exception */
17
//#define DEBUG_SD 1
37
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
18
38
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
19
-#ifdef DEBUG_SD
39
+/*
20
-#define DPRINTF(fmt, ...) \
40
+ * For A-profile only, target EL for debug exceptions.
21
-do { fprintf(stderr, "SD: " fmt , ## __VA_ARGS__); } while (0)
41
+ * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.
22
-#else
42
+ */
23
-#define DPRINTF(fmt, ...) do {} while(0)
43
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
24
-#endif
44
25
-
45
/* Bit usage when in AArch32 state: */
26
#define ACMD41_ENQUIRY_MASK 0x00ffffff
46
FIELD(TBFLAG_A32, THUMB, 0, 1)
27
#define OCR_POWER_UP 0x80000000
47
diff --git a/target/arm/translate.h b/target/arm/translate.h
28
#define OCR_POWER_DELAY_NS 500000 /* 0.5ms */
48
index XXXXXXX..XXXXXXX 100644
29
@@ -XXX,XX +XXX,XX @@ send_response:
49
--- a/target/arm/translate.h
50
+++ b/target/arm/translate.h
51
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
52
uint32_t svc_imm;
53
int aarch64;
54
int current_el;
55
+ /* Debug target exception level for single-step exceptions */
56
+ int debug_target_el;
57
GHashTable *cp_regs;
58
uint64_t features; /* CPU features bits */
59
/* Because unallocated encodings generate different exception syndrome
60
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
61
* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
62
*/
63
bool is_ldex;
64
- /* True if a single-step exception will be taken to the current EL */
65
- bool ss_same_el;
66
/* True if v8.3-PAuth is active. */
67
bool pauth_active;
68
/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
69
@@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome,
70
/* Generate an architectural singlestep exception */
71
static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
72
{
73
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
74
- default_exception_el(s));
75
+ bool same_el = (s->debug_target_el == s->current_el);
76
+
77
+ /*
78
+ * If singlestep is targeting a lower EL than the current one,
79
+ * then s->ss_active must be false and we can never get here.
80
+ */
81
+ assert(s->debug_target_el >= s->current_el);
82
+
83
+ gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
84
}
85
86
/*
87
diff --git a/target/arm/helper.c b/target/arm/helper.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/helper.c
90
+++ b/target/arm/helper.c
91
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
92
}
30
}
93
}
31
94
32
#ifdef DEBUG_SD
95
+ if (!arm_feature(env, ARM_FEATURE_M)) {
33
- if (rsplen) {
96
+ int target_el = arm_debug_target_el(env);
34
- int i;
97
+
35
- DPRINTF("Response:");
98
+ flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el);
36
- for (i = 0; i < rsplen; i++) {
99
+ }
37
- DPRINTF(" %02x", response[i]);
100
+
38
- }
101
*pflags = flags;
39
- DPRINTF(" state %d\n", sd->state);
102
*cs_base = 0;
40
- }
103
}
41
+ qemu_hexdump((const char *)response, stderr, "Response", rsplen);
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
42
#endif
105
index XXXXXXX..XXXXXXX 100644
43
106
--- a/target/arm/translate-a64.c
44
return rsplen;
107
+++ b/target/arm/translate-a64.c
108
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
109
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
110
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
111
dc->is_ldex = false;
112
- dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
113
+ dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
114
115
/* Bound the number of insns to execute to those left on the page. */
116
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/translate.c
120
+++ b/target/arm/translate.c
121
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
122
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
123
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
124
dc->is_ldex = false;
125
- dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
126
+ if (!arm_feature(env, ARM_FEATURE_M)) {
127
+ dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
128
+ }
129
130
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
131
45
--
132
--
46
2.16.1
133
2.20.1
47
134
48
135
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/32] hw/sd/ssi-sd: use the SDBus API, connect the SDCard to the bus
[Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
On reset the bus will reset the card,
3
This function is used in two different contexts, and it will be
4
we can now drop the device_reset() call.
4
clearer if the function is given the address to which it applies.
5
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20180216022933.10945-5-f4bug@amsat.org
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-2-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/sd/ssi-sd.c | 32 +++++++++++++++++++-------------
12
target/arm/translate.c | 14 +++++++-------
12
1 file changed, 19 insertions(+), 13 deletions(-)
13
1 file changed, 7 insertions(+), 7 deletions(-)
13
14
14
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/sd/ssi-sd.c
17
--- a/target/arm/translate.c
17
+++ b/hw/sd/ssi-sd.c
18
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
19
int32_t arglen;
20
int32_t response_pos;
21
int32_t stopping;
22
- SDState *sd;
23
+ SDBus sdbus;
24
} ssi_sd_state;
25
26
#define TYPE_SSI_SD "ssi-sd"
27
@@ -XXX,XX +XXX,XX @@ static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
28
request.arg = (s->cmdarg[0] << 24) | (s->cmdarg[1] << 16)
29
| (s->cmdarg[2] << 8) | s->cmdarg[3];
30
DPRINTF("CMD%d arg 0x%08x\n", s->cmd, request.arg);
31
- s->arglen = sd_do_command(s->sd, &request, longresp);
32
+ s->arglen = sdbus_do_command(&s->sdbus, &request, longresp);
33
if (s->arglen <= 0) {
34
s->arglen = 1;
35
s->response[0] = 4;
36
@@ -XXX,XX +XXX,XX @@ static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
37
DPRINTF("Response 0x%02x\n", s->response[s->response_pos]);
38
return s->response[s->response_pos++];
39
}
40
- if (sd_data_ready(s->sd)) {
41
+ if (sdbus_data_ready(&s->sdbus)) {
42
DPRINTF("Data read\n");
43
s->mode = SSI_SD_DATA_START;
44
} else {
45
@@ -XXX,XX +XXX,XX @@ static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
46
s->mode = SSI_SD_DATA_READ;
47
return 0xfe;
48
case SSI_SD_DATA_READ:
49
- val = sd_read_data(s->sd);
50
- if (!sd_data_ready(s->sd)) {
51
+ val = sdbus_read_data(&s->sdbus);
52
+ if (!sdbus_data_ready(&s->sdbus)) {
53
DPRINTF("Data read end\n");
54
s->mode = SSI_SD_CMD;
55
}
56
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
57
static void ssi_sd_realize(SSISlave *d, Error **errp)
58
{
59
ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
60
+ DeviceState *carddev;
61
DriveInfo *dinfo;
62
+ Error *err = NULL;
63
64
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
65
+ DEVICE(d), "sd-bus");
66
+
67
+ /* Create and plug in the sd card */
68
/* FIXME use a qdev drive property instead of drive_get_next() */
69
dinfo = drive_get_next(IF_SD);
70
- s->sd = sd_init(dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, true);
71
- if (s->sd == NULL) {
72
- error_setg(errp, "Device initialization failed.");
73
+ carddev = qdev_create(&s->sdbus.qbus, TYPE_SD_CARD);
74
+ if (dinfo) {
75
+ qdev_prop_set_drive(carddev, "drive", blk_by_legacy_dinfo(dinfo), &err);
76
+ }
77
+ object_property_set_bool(OBJECT(carddev), true, "spi", &err);
78
+ object_property_set_bool(OBJECT(carddev), true, "realized", &err);
79
+ if (err) {
80
+ error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
81
return;
82
}
20
}
83
}
21
}
84
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_reset(DeviceState *dev)
22
85
s->arglen = 0;
23
-static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
86
s->response_pos = 0;
24
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
87
s->stopping = 0;
25
{
88
-
26
- /* Return true if this is a 16 bit instruction. We must be precise
89
- /* Since we're still using the legacy SD API the card is not plugged
27
- * about this (matching the decode). We assume that s->pc still
90
- * into any bus, and we must reset it manually.
28
- * points to the first 16 bits of the insn.
91
- */
29
+ /*
92
- device_reset(DEVICE(s->sd));
30
+ * Return true if this is a 16 bit instruction. We must be precise
31
+ * about this (matching the decode).
32
*/
33
if ((insn >> 11) < 0x1d) {
34
/* Definitely a 16-bit instruction */
35
@@ -XXX,XX +XXX,XX @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
36
return false;
37
}
38
39
- if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {
40
+ if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {
41
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
42
* is not on the next page; we merge this into a 32-bit
43
* insn.
44
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
45
*/
46
uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
47
48
- return !thumb_insn_is_16bit(s, insn);
49
+ return !thumb_insn_is_16bit(s, s->pc, insn);
93
}
50
}
94
51
95
static void ssi_sd_class_init(ObjectClass *klass, void *data)
52
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
53
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
54
}
55
56
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
57
- is_16bit = thumb_insn_is_16bit(dc, insn);
58
+ is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
59
dc->pc += 2;
60
if (!is_16bit) {
61
uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
96
--
62
--
97
2.16.1
63
2.20.1
98
64
99
65
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/32] Fix ast2500 protection register emulation
[Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr
1
From: Hugo Landau <hlandau@devever.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Some register blocks of the ast2500 are protected by protection key
3
Add a new field to retain the address of the instruction currently
4
registers which require the right magic value to be written to those
4
being translated. The 32-bit uses are all within subroutines used
5
registers to allow those registers to be mutated.
5
by a32 and t32. This will become less obvious when t16 support is
6
6
merged with a32+t32, and having a clear definition will help.
7
Register manuals indicate that writing the correct magic value to these
7
8
registers should cause subsequent reads from those values to return 1,
8
Convert aarch64 as well for consistency. Note that there is one
9
and writing any other value should cause subsequent reads to return 0.
9
instance of a pre-assert fprintf that used the wrong value for the
10
10
address of the current instruction.
11
Previously, qemu implemented these registers incorrectly: the registers
11
12
were handled as simple memory, meaning that writing some value x to a
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
protection key register would result in subsequent reads from that
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
register returning the same value x. The protection was implemented by
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
ensuring that the current value of that register equaled the magic
15
Message-id: 20190807045335.1361-3-richard.henderson@linaro.org
16
value.
17
18
This modifies qemu to have the correct behaviour: attempts to write to a
19
ast2500 protection register results in a transition to 1 or 0 depending
20
on whether the written value is the correct magic. The protection logic
21
is updated to ensure that the value of the register is nonzero.
22
23
This bug caused deadlocks with u-boot HEAD: when u-boot is done with a
24
protectable register block, it attempts to lock it by writing the
25
bitwise inverse of the correct magic value, and then spinning forever
26
until the register reads as zero. Since qemu implemented writes to these
27
registers as ordinary memory writes, writing the inverse of the magic
28
value resulted in subsequent reads returning that value, leading to
29
u-boot spinning forever.
30
31
Signed-off-by: Hugo Landau <hlandau@devever.net>
32
Reviewed-by: Cédric Le Goater <clg@kaod.org>
33
Acked-by: Andrew Jeffery <andrew@aj.id.au>
34
Message-id: 20180220132627.4163-1-hlandau@devever.net
35
[PMM: fixed incorrect code indentation]
36
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
---
17
---
38
hw/misc/aspeed_scu.c | 6 +++++-
18
target/arm/translate-a64.h | 2 +-
39
hw/misc/aspeed_sdmc.c | 8 +++++++-
19
target/arm/translate.h | 2 ++
40
2 files changed, 12 insertions(+), 2 deletions(-)
20
target/arm/translate-a64.c | 21 +++++++++++----------
41
21
target/arm/translate.c | 14 ++++++++------
42
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
22
4 files changed, 22 insertions(+), 17 deletions(-)
43
index XXXXXXX..XXXXXXX 100644
23
44
--- a/hw/misc/aspeed_scu.c
24
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
45
+++ b/hw/misc/aspeed_scu.c
25
index XXXXXXX..XXXXXXX 100644
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
26
--- a/target/arm/translate-a64.h
47
}
27
+++ b/target/arm/translate-a64.h
48
28
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
49
if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
29
qemu_log_mask(LOG_UNIMP, \
50
- s->regs[PROT_KEY] != ASPEED_SCU_PROT_KEY) {
30
"%s:%d: unsupported instruction encoding 0x%08x " \
51
+ !s->regs[PROT_KEY]) {
31
"at pc=%016" PRIx64 "\n", \
52
qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
32
- __FILE__, __LINE__, insn, s->pc - 4); \
33
+ __FILE__, __LINE__, insn, s->pc_curr); \
34
unallocated_encoding(s); \
35
} while (0)
36
37
diff --git a/target/arm/translate.h b/target/arm/translate.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.h
40
+++ b/target/arm/translate.h
41
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
42
const ARMISARegisters *isar;
43
44
target_ulong pc;
45
+ /* The address of the current instruction being translated. */
46
+ target_ulong pc_curr;
47
target_ulong page_start;
48
uint32_t insn;
49
/* Nonzero if this instruction has been conditionally skipped. */
50
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate-a64.c
53
+++ b/target/arm/translate-a64.c
54
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
55
*/
56
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
57
{
58
- uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
59
+ uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
60
61
if (insn & (1U << 31)) {
62
/* BL Branch with link */
63
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
64
sf = extract32(insn, 31, 1);
65
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
66
rt = extract32(insn, 0, 5);
67
- addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
68
+ addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
69
70
tcg_cmp = read_cpu_reg(s, rt, sf);
71
label_match = gen_new_label();
72
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
73
74
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
75
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
76
- addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
77
+ addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
78
rt = extract32(insn, 0, 5);
79
80
tcg_cmp = tcg_temp_new_i64();
81
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
82
unallocated_encoding(s);
53
return;
83
return;
54
}
84
}
55
@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
85
- addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
56
trace_aspeed_scu_write(offset, size, data);
86
+ addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
57
87
cond = extract32(insn, 0, 4);
58
switch (reg) {
88
59
+ case PROT_KEY:
89
reset_btype(s);
60
+ s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
90
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
61
+ return;
91
TCGv_i32 tcg_syn, tcg_isread;
62
+
92
uint32_t syndrome;
63
case FREQ_CNTR_EVAL:
93
64
case VGA_SCRATCH1 ... VGA_SCRATCH8:
94
- gen_a64_set_pc_im(s->pc - 4);
65
case RNG_DATA:
95
+ gen_a64_set_pc_im(s->pc_curr);
66
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
96
tmpptr = tcg_const_ptr(ri);
67
index XXXXXXX..XXXXXXX 100644
97
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
68
--- a/hw/misc/aspeed_sdmc.c
98
tcg_syn = tcg_const_i32(syndrome);
69
+++ b/hw/misc/aspeed_sdmc.c
99
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
70
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
100
/* The pre HVC helper handles cases when HVC gets trapped
101
* as an undefined insn by runtime configuration.
102
*/
103
- gen_a64_set_pc_im(s->pc - 4);
104
+ gen_a64_set_pc_im(s->pc_curr);
105
gen_helper_pre_hvc(cpu_env);
106
gen_ss_advance(s);
107
gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
108
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
109
unallocated_encoding(s);
110
break;
111
}
112
- gen_a64_set_pc_im(s->pc - 4);
113
+ gen_a64_set_pc_im(s->pc_curr);
114
tmp = tcg_const_i32(syn_aa64_smc(imm16));
115
gen_helper_pre_smc(cpu_env, tmp);
116
tcg_temp_free_i32(tmp);
117
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
118
119
tcg_rt = cpu_reg(s, rt);
120
121
- clean_addr = tcg_const_i64((s->pc - 4) + imm);
122
+ clean_addr = tcg_const_i64(s->pc_curr + imm);
123
if (is_vector) {
124
do_fp_ld(s, rt, clean_addr, size);
125
} else {
126
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
127
offset = sextract64(insn, 5, 19);
128
offset = offset << 2 | extract32(insn, 29, 2);
129
rd = extract32(insn, 0, 5);
130
- base = s->pc - 4;
131
+ base = s->pc_curr;
132
133
if (page) {
134
/* ADRP (page based) */
135
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
136
break;
137
default:
138
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
139
- __func__, insn, fpopcode, s->pc);
140
+ __func__, insn, fpopcode, s->pc_curr);
141
g_assert_not_reached();
142
}
143
144
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
145
{
146
uint32_t insn;
147
148
+ s->pc_curr = s->pc;
149
insn = arm_ldl_code(env, s->pc, s->sctlr_b);
150
s->insn = insn;
151
s->pc += 4;
152
diff --git a/target/arm/translate.c b/target/arm/translate.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate.c
155
+++ b/target/arm/translate.c
156
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
157
* as an undefined insn by runtime configuration (ie before
158
* the insn really executes).
159
*/
160
- gen_set_pc_im(s, s->pc - 4);
161
+ gen_set_pc_im(s, s->pc_curr);
162
gen_helper_pre_hvc(cpu_env);
163
/* Otherwise we will treat this as a real exception which
164
* happens after execution of the insn. (The distinction matters
165
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
166
*/
167
TCGv_i32 tmp;
168
169
- gen_set_pc_im(s, s->pc - 4);
170
+ gen_set_pc_im(s, s->pc_curr);
171
tmp = tcg_const_i32(syn_aa32_smc());
172
gen_helper_pre_smc(cpu_env, tmp);
173
tcg_temp_free_i32(tmp);
174
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
175
176
/* Sync state because msr_banked() can raise exceptions */
177
gen_set_condexec(s);
178
- gen_set_pc_im(s, s->pc - 4);
179
+ gen_set_pc_im(s, s->pc_curr);
180
tcg_reg = load_reg(s, rn);
181
tcg_tgtmode = tcg_const_i32(tgtmode);
182
tcg_regno = tcg_const_i32(regno);
183
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
184
185
/* Sync state because mrs_banked() can raise exceptions */
186
gen_set_condexec(s);
187
- gen_set_pc_im(s, s->pc - 4);
188
+ gen_set_pc_im(s, s->pc_curr);
189
tcg_reg = tcg_temp_new_i32();
190
tcg_tgtmode = tcg_const_i32(tgtmode);
191
tcg_regno = tcg_const_i32(regno);
192
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
193
}
194
195
gen_set_condexec(s);
196
- gen_set_pc_im(s, s->pc - 4);
197
+ gen_set_pc_im(s, s->pc_curr);
198
tmpptr = tcg_const_ptr(ri);
199
tcg_syn = tcg_const_i32(syndrome);
200
tcg_isread = tcg_const_i32(isread);
201
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
202
tmp = tcg_const_i32(mode);
203
/* get_r13_banked() will raise an exception if called from System mode */
204
gen_set_condexec(s);
205
- gen_set_pc_im(s, s->pc - 4);
206
+ gen_set_pc_im(s, s->pc_curr);
207
gen_helper_get_r13_banked(addr, cpu_env, tmp);
208
tcg_temp_free_i32(tmp);
209
switch (amode) {
210
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
71
return;
211
return;
72
}
212
}
73
213
74
- if (addr != R_PROT && s->regs[R_PROT] != PROT_KEY_UNLOCK) {
214
+ dc->pc_curr = dc->pc;
75
+ if (addr == R_PROT) {
215
insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
76
+ s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
216
dc->insn = insn;
77
+ return;
217
dc->pc += 4;
78
+ }
218
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
79
+
80
+ if (!s->regs[R_PROT]) {
81
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
82
return;
219
return;
83
}
220
}
84
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
221
85
data &= ~ASPEED_SDMC_READONLY_MASK;
222
+ dc->pc_curr = dc->pc;
86
break;
223
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
87
case AST2500_A0_SILICON_REV:
224
is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
88
+ case AST2500_A1_SILICON_REV:
225
dc->pc += 2;
89
data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
90
break;
91
default:
92
--
226
--
93
2.16.1
227
2.20.1
94
228
95
229
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/32] sdcard: warn if host uses an incorrect address for APP CMD (CMD55)
[Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
We currently have 3 different ways of computing the architectural
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
value of "PC" as seen in the ARM ARM.
5
Message-id: 20180215221325.7611-15-f4bug@amsat.org
5
6
The value of s->pc has been incremented past the current insn,
7
but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
8
for t16, PC = s->pc + 2. These differing computations make it
9
impossible at present to unify the various code paths.
10
11
With the newly introduced s->pc_curr, we can compute the correct
12
value for all cases, using the formula given in the ARM ARM.
13
14
This changes the behaviour for load_reg() and load_reg_var()
15
when called with reg==15 from a 32-bit Thumb instruction:
16
previously they would have returned the incorrect value
17
of pc_curr + 6, and now they will return the architecturally
18
correct value of PC, which is pc_curr + 4. This will not
19
affect well-behaved guest software, because all of the places
20
we call these functions from T32 code are instructions where
21
using r15 is UNPREDICTABLE. Using the architectural PC value
22
here is more consistent with the T16 and A32 behaviour.
23
24
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
27
Message-id: 20190807045335.1361-4-richard.henderson@linaro.org
28
[PMM: added commit message note about UNPREDICTABLE T32 cases]
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
30
---
8
hw/sd/sd.c | 5 +++++
31
target/arm/translate.c | 59 ++++++++++++++++--------------------------
9
1 file changed, 5 insertions(+)
32
1 file changed, 23 insertions(+), 36 deletions(-)
10
33
11
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
34
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sd.c
36
--- a/target/arm/translate.c
14
+++ b/hw/sd/sd.c
37
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
38
@@ -XXX,XX +XXX,XX @@ static inline void store_cpu_offset(TCGv_i32 var, int offset)
16
case sd_identification_state:
39
#define store_cpu_field(var, name) \
17
case sd_inactive_state:
40
store_cpu_offset(var, offsetof(CPUARMState, name))
18
return sd_illegal;
41
19
+ case sd_idle_state:
42
+/* The architectural value of PC. */
20
+ if (rca) {
43
+static uint32_t read_pc(DisasContext *s)
21
+ qemu_log_mask(LOG_GUEST_ERROR,
44
+{
22
+ "SD: illegal RCA 0x%04x for APP_CMD\n", req.cmd);
45
+ return s->pc_curr + (s->thumb ? 4 : 8);
23
+ }
46
+}
24
default:
47
+
48
/* Set a variable to the value of a CPU register. */
49
static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
50
{
51
if (reg == 15) {
52
- uint32_t addr;
53
- /* normally, since we updated PC, we need only to add one insn */
54
- if (s->thumb)
55
- addr = (long)s->pc + 2;
56
- else
57
- addr = (long)s->pc + 4;
58
- tcg_gen_movi_i32(var, addr);
59
+ tcg_gen_movi_i32(var, read_pc(s));
60
} else {
61
tcg_gen_mov_i32(var, cpu_R[reg]);
62
}
63
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
64
/* branch link and change to thumb (blx <offset>) */
65
int32_t offset;
66
67
- val = (uint32_t)s->pc;
68
tmp = tcg_temp_new_i32();
69
- tcg_gen_movi_i32(tmp, val);
70
+ tcg_gen_movi_i32(tmp, s->pc);
71
store_reg(s, 14, tmp);
72
/* Sign-extend the 24-bit offset */
73
offset = (((int32_t)insn) << 8) >> 8;
74
+ val = read_pc(s);
75
/* offset * 4 + bit24 * 2 + (thumb bit) */
76
val += (offset << 2) | ((insn >> 23) & 2) | 1;
77
- /* pipeline offset */
78
- val += 4;
79
/* protected by ARCH(5); above, near the start of uncond block */
80
gen_bx_im(s, val);
81
return;
82
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
83
} else {
84
/* store */
85
if (i == 15) {
86
- /* special case: r15 = PC + 8 */
87
- val = (long)s->pc + 4;
88
tmp = tcg_temp_new_i32();
89
- tcg_gen_movi_i32(tmp, val);
90
+ tcg_gen_movi_i32(tmp, read_pc(s));
91
} else if (user) {
92
tmp = tcg_temp_new_i32();
93
tmp2 = tcg_const_i32(i);
94
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
95
int32_t offset;
96
97
/* branch (and link) */
98
- val = (int32_t)s->pc;
99
if (insn & (1 << 24)) {
100
tmp = tcg_temp_new_i32();
101
- tcg_gen_movi_i32(tmp, val);
102
+ tcg_gen_movi_i32(tmp, s->pc);
103
store_reg(s, 14, tmp);
104
}
105
offset = sextract32(insn << 2, 0, 26);
106
- val += offset + 4;
107
- gen_jmp(s, val);
108
+ gen_jmp(s, read_pc(s) + offset);
109
}
110
break;
111
case 0xc:
112
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
113
tcg_temp_free_i32(addr);
114
} else if ((insn & (7 << 5)) == 0) {
115
/* Table Branch. */
116
- if (rn == 15) {
117
- addr = tcg_temp_new_i32();
118
- tcg_gen_movi_i32(addr, s->pc);
119
- } else {
120
- addr = load_reg(s, rn);
121
- }
122
+ addr = load_reg(s, rn);
123
tmp = load_reg(s, rm);
124
tcg_gen_add_i32(addr, addr, tmp);
125
if (insn & (1 << 4)) {
126
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
127
}
128
tcg_temp_free_i32(addr);
129
tcg_gen_shli_i32(tmp, tmp, 1);
130
- tcg_gen_addi_i32(tmp, tmp, s->pc);
131
+ tcg_gen_addi_i32(tmp, tmp, read_pc(s));
132
store_reg(s, 15, tmp);
133
} else {
134
bool is_lasr = false;
135
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
136
tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
137
}
138
139
- offset += s->pc;
140
+ offset += read_pc(s);
141
if (insn & (1 << 12)) {
142
/* b/bl */
143
gen_jmp(s, offset);
144
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
145
offset |= (insn & (1 << 11)) << 8;
146
147
/* jump to the offset */
148
- gen_jmp(s, s->pc + offset);
149
+ gen_jmp(s, read_pc(s) + offset);
150
}
151
} else {
152
/*
153
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
154
if (insn & (1 << 11)) {
155
rd = (insn >> 8) & 7;
156
/* load pc-relative. Bit 1 of PC is ignored. */
157
- val = s->pc + 2 + ((insn & 0xff) * 4);
158
+ val = read_pc(s) + ((insn & 0xff) * 4);
159
val &= ~(uint32_t)2;
160
addr = tcg_temp_new_i32();
161
tcg_gen_movi_i32(addr, val);
162
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
163
} else {
164
/* PC. bit 1 is ignored. */
165
tmp = tcg_temp_new_i32();
166
- tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
167
+ tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
168
}
169
val = (insn & 0xff) * 4;
170
tcg_gen_addi_i32(tmp, tmp, val);
171
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
172
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
173
tcg_temp_free_i32(tmp);
174
offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
175
- val = (uint32_t)s->pc + 2;
176
- val += offset;
177
- gen_jmp(s, val);
178
+ gen_jmp(s, read_pc(s) + offset);
179
break;
180
181
case 15: /* IT, nop-hint. */
182
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
183
arm_skip_unless(s, cond);
184
185
/* jump to the offset */
186
- val = (uint32_t)s->pc + 2;
187
+ val = read_pc(s);
188
offset = ((int32_t)insn << 24) >> 24;
189
val += offset << 1;
190
gen_jmp(s, val);
191
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
25
break;
192
break;
26
}
193
}
194
/* unconditional branch */
195
- val = (uint32_t)s->pc;
196
+ val = read_pc(s);
197
offset = ((int32_t)insn << 21) >> 21;
198
- val += (offset << 1) + 2;
199
+ val += offset << 1;
200
gen_jmp(s, val);
201
break;
202
203
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
204
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
205
uint32_t uoffset = ((int32_t)insn << 21) >> 9;
206
207
- tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
208
+ tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset);
209
}
210
break;
211
}
27
--
212
--
28
2.16.1
213
2.20.1
29
214
30
215
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/32] hw/sd/milkymist-memcard: use qemu_log_mask()
[Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Provide a common routine for the places that require ALIGN(PC, 4)
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
as the base address as opposed to plain PC. The two are always
5
Acked-by: Michael Walle <michael@walle.cc>
5
the same for A32, but the difference is meaningful for thumb mode.
6
Message-id: 20180216022933.10945-2-f4bug@amsat.org
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190807045335.1361-5-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
hw/sd/milkymist-memcard.c | 17 ++++++++++-------
13
target/arm/translate-vfp.inc.c | 38 ++------
10
1 file changed, 10 insertions(+), 7 deletions(-)
14
target/arm/translate.c | 166 +++++++++++++++------------------
11
15
2 files changed, 82 insertions(+), 122 deletions(-)
12
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
16
17
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
13
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/milkymist-memcard.c
19
--- a/target/arm/translate-vfp.inc.c
15
+++ b/hw/sd/milkymist-memcard.c
20
+++ b/target/arm/translate-vfp.inc.c
16
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
17
*/
22
offset = -offset;
18
23
}
19
#include "qemu/osdep.h"
24
20
+#include "qemu/log.h"
25
- if (s->thumb && a->rn == 15) {
21
#include "hw/hw.h"
26
- /* This is actually UNPREDICTABLE */
22
#include "hw/sysbus.h"
27
- addr = tcg_temp_new_i32();
23
#include "sysemu/sysemu.h"
28
- tcg_gen_movi_i32(addr, s->pc & ~2);
24
#include "trace.h"
29
- } else {
25
-#include "qemu/error-report.h"
30
- addr = load_reg(s, a->rn);
26
+#include "include/qapi/error.h"
31
- }
27
#include "sysemu/block-backend.h"
32
- tcg_gen_addi_i32(addr, addr, offset);
28
#include "sysemu/blockdev.h"
33
+ /* For thumb, use of PC is UNPREDICTABLE. */
29
#include "hw/sd/sd.h"
34
+ addr = add_reg_for_lit(s, a->rn, offset);
30
@@ -XXX,XX +XXX,XX @@ static uint64_t memcard_read(void *opaque, hwaddr addr,
35
tmp = tcg_temp_new_i32();
31
} else {
36
if (a->l) {
32
r = s->response[s->response_read_ptr++];
37
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
33
if (s->response_read_ptr > s->response_len) {
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
34
- error_report("milkymist_memcard: "
39
offset = -offset;
35
- "read more cmd bytes than available. Clipping.");
40
}
36
+ qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
41
37
+ "read more cmd bytes than available. Clipping.");
42
- if (s->thumb && a->rn == 15) {
38
s->response_read_ptr = 0;
43
- /* This is actually UNPREDICTABLE */
44
- addr = tcg_temp_new_i32();
45
- tcg_gen_movi_i32(addr, s->pc & ~2);
46
- } else {
47
- addr = load_reg(s, a->rn);
48
- }
49
- tcg_gen_addi_i32(addr, addr, offset);
50
+ /* For thumb, use of PC is UNPREDICTABLE. */
51
+ addr = add_reg_for_lit(s, a->rn, offset);
52
tmp = tcg_temp_new_i64();
53
if (a->l) {
54
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
55
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
56
return true;
57
}
58
59
- if (s->thumb && a->rn == 15) {
60
- /* This is actually UNPREDICTABLE */
61
- addr = tcg_temp_new_i32();
62
- tcg_gen_movi_i32(addr, s->pc & ~2);
63
- } else {
64
- addr = load_reg(s, a->rn);
65
- }
66
+ /* For thumb, use of PC is UNPREDICTABLE. */
67
+ addr = add_reg_for_lit(s, a->rn, 0);
68
if (a->p) {
69
/* pre-decrement */
70
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
71
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
72
return true;
73
}
74
75
- if (s->thumb && a->rn == 15) {
76
- /* This is actually UNPREDICTABLE */
77
- addr = tcg_temp_new_i32();
78
- tcg_gen_movi_i32(addr, s->pc & ~2);
79
- } else {
80
- addr = load_reg(s, a->rn);
81
- }
82
+ /* For thumb, use of PC is UNPREDICTABLE. */
83
+ addr = add_reg_for_lit(s, a->rn, 0);
84
if (a->p) {
85
/* pre-decrement */
86
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
87
diff --git a/target/arm/translate.c b/target/arm/translate.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/translate.c
90
+++ b/target/arm/translate.c
91
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
92
return tmp;
93
}
94
95
+/*
96
+ * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
97
+ * This is used for load/store for which use of PC implies (literal),
98
+ * or ADD that implies ADR.
99
+ */
100
+static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
101
+{
102
+ TCGv_i32 tmp = tcg_temp_new_i32();
103
+
104
+ if (reg == 15) {
105
+ tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs);
106
+ } else {
107
+ tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
108
+ }
109
+ return tmp;
110
+}
111
+
112
/* Set a CPU register. The source must be a temporary and will be
113
marked as dead. */
114
static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
115
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
116
*/
117
bool wback = extract32(insn, 21, 1);
118
119
- if (rn == 15) {
120
- if (insn & (1 << 21)) {
121
- /* UNPREDICTABLE */
122
- goto illegal_op;
123
- }
124
- addr = tcg_temp_new_i32();
125
- tcg_gen_movi_i32(addr, s->pc & ~3);
126
- } else {
127
- addr = load_reg(s, rn);
128
+ if (rn == 15 && (insn & (1 << 21))) {
129
+ /* UNPREDICTABLE */
130
+ goto illegal_op;
131
}
132
+
133
+ addr = add_reg_for_lit(s, rn, 0);
134
offset = (insn & 0xff) * 4;
135
if ((insn & (1 << 23)) == 0) {
136
offset = -offset;
137
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
138
store_reg(s, rd, tmp);
139
} else {
140
/* Add/sub 12-bit immediate. */
141
- if (rn == 15) {
142
- offset = s->pc & ~(uint32_t)3;
143
- if (insn & (1 << 23))
144
- offset -= imm;
145
- else
146
- offset += imm;
147
- tmp = tcg_temp_new_i32();
148
- tcg_gen_movi_i32(tmp, offset);
149
- store_reg(s, rd, tmp);
150
+ if (insn & (1 << 23)) {
151
+ imm = -imm;
152
+ }
153
+ tmp = add_reg_for_lit(s, rn, imm);
154
+ if (rn == 13 && rd == 13) {
155
+ /* ADD SP, SP, imm or SUB SP, SP, imm */
156
+ store_sp_checked(s, tmp);
157
} else {
158
- tmp = load_reg(s, rn);
159
- if (insn & (1 << 23))
160
- tcg_gen_subi_i32(tmp, tmp, imm);
161
- else
162
- tcg_gen_addi_i32(tmp, tmp, imm);
163
- if (rn == 13 && rd == 13) {
164
- /* ADD SP, SP, imm or SUB SP, SP, imm */
165
- store_sp_checked(s, tmp);
166
- } else {
167
- store_reg(s, rd, tmp);
168
- }
169
+ store_reg(s, rd, tmp);
170
}
171
}
172
}
173
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
39
}
174
}
40
}
175
}
41
@@ -XXX,XX +XXX,XX @@ static uint64_t memcard_read(void *opaque, hwaddr addr,
176
memidx = get_mem_index(s);
177
- if (rn == 15) {
178
- addr = tcg_temp_new_i32();
179
- /* PC relative. */
180
- /* s->pc has already been incremented by 4. */
181
- imm = s->pc & 0xfffffffc;
182
- if (insn & (1 << 23))
183
- imm += insn & 0xfff;
184
- else
185
- imm -= insn & 0xfff;
186
- tcg_gen_movi_i32(addr, imm);
187
+ imm = insn & 0xfff;
188
+ if (insn & (1 << 23)) {
189
+ /* PC relative or Positive offset. */
190
+ addr = add_reg_for_lit(s, rn, imm);
191
+ } else if (rn == 15) {
192
+ /* PC relative with negative offset. */
193
+ addr = add_reg_for_lit(s, rn, -imm);
194
} else {
195
addr = load_reg(s, rn);
196
- if (insn & (1 << 23)) {
197
- /* Positive offset. */
198
- imm = insn & 0xfff;
199
- tcg_gen_addi_i32(addr, addr, imm);
200
- } else {
201
- imm = insn & 0xff;
202
- switch ((insn >> 8) & 0xf) {
203
- case 0x0: /* Shifted Register. */
204
- shift = (insn >> 4) & 0xf;
205
- if (shift > 3) {
206
- tcg_temp_free_i32(addr);
207
- goto illegal_op;
208
- }
209
- tmp = load_reg(s, rm);
210
- if (shift)
211
- tcg_gen_shli_i32(tmp, tmp, shift);
212
- tcg_gen_add_i32(addr, addr, tmp);
213
- tcg_temp_free_i32(tmp);
214
- break;
215
- case 0xc: /* Negative offset. */
216
- tcg_gen_addi_i32(addr, addr, -imm);
217
- break;
218
- case 0xe: /* User privilege. */
219
- tcg_gen_addi_i32(addr, addr, imm);
220
- memidx = get_a32_user_mem_index(s);
221
- break;
222
- case 0x9: /* Post-decrement. */
223
- imm = -imm;
224
- /* Fall through. */
225
- case 0xb: /* Post-increment. */
226
- postinc = 1;
227
- writeback = 1;
228
- break;
229
- case 0xd: /* Pre-decrement. */
230
- imm = -imm;
231
- /* Fall through. */
232
- case 0xf: /* Pre-increment. */
233
- writeback = 1;
234
- break;
235
- default:
236
+ imm = insn & 0xff;
237
+ switch ((insn >> 8) & 0xf) {
238
+ case 0x0: /* Shifted Register. */
239
+ shift = (insn >> 4) & 0xf;
240
+ if (shift > 3) {
241
tcg_temp_free_i32(addr);
242
goto illegal_op;
243
}
244
+ tmp = load_reg(s, rm);
245
+ if (shift) {
246
+ tcg_gen_shli_i32(tmp, tmp, shift);
247
+ }
248
+ tcg_gen_add_i32(addr, addr, tmp);
249
+ tcg_temp_free_i32(tmp);
250
+ break;
251
+ case 0xc: /* Negative offset. */
252
+ tcg_gen_addi_i32(addr, addr, -imm);
253
+ break;
254
+ case 0xe: /* User privilege. */
255
+ tcg_gen_addi_i32(addr, addr, imm);
256
+ memidx = get_a32_user_mem_index(s);
257
+ break;
258
+ case 0x9: /* Post-decrement. */
259
+ imm = -imm;
260
+ /* Fall through. */
261
+ case 0xb: /* Post-increment. */
262
+ postinc = 1;
263
+ writeback = 1;
264
+ break;
265
+ case 0xd: /* Pre-decrement. */
266
+ imm = -imm;
267
+ /* Fall through. */
268
+ case 0xf: /* Pre-increment. */
269
+ writeback = 1;
270
+ break;
271
+ default:
272
+ tcg_temp_free_i32(addr);
273
+ goto illegal_op;
274
}
275
}
276
277
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
278
if (insn & (1 << 11)) {
279
rd = (insn >> 8) & 7;
280
/* load pc-relative. Bit 1 of PC is ignored. */
281
- val = read_pc(s) + ((insn & 0xff) * 4);
282
- val &= ~(uint32_t)2;
283
- addr = tcg_temp_new_i32();
284
- tcg_gen_movi_i32(addr, val);
285
+ addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
286
tmp = tcg_temp_new_i32();
287
gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
288
rd | ISSIs16Bit);
289
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
290
* - Add PC/SP (immediate)
291
*/
292
rd = (insn >> 8) & 7;
293
- if (insn & (1 << 11)) {
294
- /* SP */
295
- tmp = load_reg(s, 13);
296
- } else {
297
- /* PC. bit 1 is ignored. */
298
- tmp = tcg_temp_new_i32();
299
- tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
300
- }
301
val = (insn & 0xff) * 4;
302
- tcg_gen_addi_i32(tmp, tmp, val);
303
+ tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
304
store_reg(s, rd, tmp);
42
break;
305
break;
43
306
44
default:
45
- error_report("milkymist_memcard: read access to unknown register 0x"
46
- TARGET_FMT_plx, addr << 2);
47
+ qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
48
+ "read access to unknown register 0x%" HWADDR_PRIx "\n",
49
+ addr << 2);
50
break;
51
}
52
53
@@ -XXX,XX +XXX,XX @@ static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
54
break;
55
56
default:
57
- error_report("milkymist_memcard: write access to unknown register 0x"
58
- TARGET_FMT_plx, addr << 2);
59
+ qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
60
+ "write access to unknown register 0x%" HWADDR_PRIx " "
61
+ "(value 0x%" PRIx64 ")\n", addr << 2, value);
62
break;
63
}
64
}
65
--
307
--
66
2.16.1
308
2.20.1
67
309
68
310
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/32] sdcard: check the card is in correct state for APP CMD (CMD55)
[Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The thumb bit has already been removed from s->pc, and is always even.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180215221325.7611-14-f4bug@amsat.org
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20190807045335.1361-6-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/sd/sd.c | 8 ++++++++
11
target/arm/translate.c | 10 +++++-----
9
1 file changed, 8 insertions(+)
12
1 file changed, 5 insertions(+), 5 deletions(-)
10
13
11
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sd.c
16
--- a/target/arm/translate.c
14
+++ b/hw/sd/sd.c
17
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
18
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
16
19
/* Force a TB lookup after an instruction that changes the CPU state. */
17
/* Application specific commands (Class 8) */
20
static inline void gen_lookup_tb(DisasContext *s)
18
case 55:    /* CMD55: APP_CMD */
21
{
19
+ switch (sd->state) {
22
- tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
20
+ case sd_ready_state:
23
+ tcg_gen_movi_i32(cpu_R[15], s->pc);
21
+ case sd_identification_state:
24
s->base.is_jmp = DISAS_EXIT;
22
+ case sd_inactive_state:
25
}
23
+ return sd_illegal;
26
24
+ default:
27
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
25
+ break;
28
* self-modifying code correctly and also to take
26
+ }
29
* any pending interrupts immediately.
27
if (!sd->spi) {
30
*/
28
if (sd->rca != rca) {
31
- gen_goto_tb(s, 0, s->pc & ~1);
29
return sd_r0;
32
+ gen_goto_tb(s, 0, s->pc);
33
return;
34
case 7: /* sb */
35
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
36
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
37
* for TCG; MB and end the TB instead.
38
*/
39
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
40
- gen_goto_tb(s, 0, s->pc & ~1);
41
+ gen_goto_tb(s, 0, s->pc);
42
return;
43
default:
44
goto illegal_op;
45
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
46
* and also to take any pending interrupts
47
* immediately.
48
*/
49
- gen_goto_tb(s, 0, s->pc & ~1);
50
+ gen_goto_tb(s, 0, s->pc);
51
break;
52
case 7: /* sb */
53
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
54
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
55
* for TCG; MB and end the TB instead.
56
*/
57
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
58
- gen_goto_tb(s, 0, s->pc & ~1);
59
+ gen_goto_tb(s, 0, s->pc);
60
break;
61
default:
62
goto illegal_op;
30
--
63
--
31
2.16.1
64
2.20.1
32
65
33
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/32] sdcard: use a more descriptive label 'unimplemented_spi_cmd'
[Qemu-devel] [PULL 11/29] target/arm: Replace s->pc with s->base.pc_next
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Suggested-by: Alistair Francis <alistair.francis@xilinx.com>
3
We must update s->base.pc_next when we return from the translate_insn
4
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
hook to the main translator loop. By incrementing s->base.pc_next
5
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
5
immediately after reading the insn word, "pc_next" contains the address
6
Message-id: 20180215221325.7611-12-f4bug@amsat.org
6
of the next instruction throughout translation.
7
8
All remaining uses of s->pc are referencing the address of the next insn,
9
so this is now a simple global replacement. Remove the "s->pc" field.
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20190807045335.1361-7-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
16
---
9
hw/sd/sd.c | 22 +++++++++++++---------
17
target/arm/translate.h | 1 -
10
1 file changed, 13 insertions(+), 9 deletions(-)
18
target/arm/translate-a64.c | 51 +++++++++---------
19
target/arm/translate.c | 103 ++++++++++++++++++-------------------
20
3 files changed, 72 insertions(+), 83 deletions(-)
11
21
12
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
22
diff --git a/target/arm/translate.h b/target/arm/translate.h
13
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sd.c
24
--- a/target/arm/translate.h
15
+++ b/hw/sd/sd.c
25
+++ b/target/arm/translate.h
16
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
17
27
DisasContextBase base;
18
/* Block write commands (Class 4) */
28
const ARMISARegisters *isar;
19
case 24:    /* CMD24: WRITE_SINGLE_BLOCK */
29
20
- if (sd->spi)
30
- target_ulong pc;
21
- goto unimplemented_cmd;
31
/* The address of the current instruction being translated. */
22
+ if (sd->spi) {
32
target_ulong pc_curr;
23
+ goto unimplemented_spi_cmd;
33
target_ulong page_start;
24
+ }
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
switch (sd->state) {
35
index XXXXXXX..XXXXXXX 100644
26
case sd_transfer_state:
36
--- a/target/arm/translate-a64.c
27
/* Writing in SPI mode not implemented. */
37
+++ b/target/arm/translate-a64.c
28
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
38
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
39
40
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
41
{
42
- gen_a64_set_pc_im(s->pc - offset);
43
+ gen_a64_set_pc_im(s->base.pc_next - offset);
44
gen_exception_internal(excp);
45
s->base.is_jmp = DISAS_NORETURN;
46
}
47
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
48
static void gen_exception_insn(DisasContext *s, int offset, int excp,
49
uint32_t syndrome, uint32_t target_el)
50
{
51
- gen_a64_set_pc_im(s->pc - offset);
52
+ gen_a64_set_pc_im(s->base.pc_next - offset);
53
gen_exception(excp, syndrome, target_el);
54
s->base.is_jmp = DISAS_NORETURN;
55
}
56
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset,
57
{
58
TCGv_i32 tcg_syn;
59
60
- gen_a64_set_pc_im(s->pc - offset);
61
+ gen_a64_set_pc_im(s->base.pc_next - offset);
62
tcg_syn = tcg_const_i32(syndrome);
63
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
64
tcg_temp_free_i32(tcg_syn);
65
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
66
67
if (insn & (1U << 31)) {
68
/* BL Branch with link */
69
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
70
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
71
}
72
73
/* B Branch / BL Branch with link */
74
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
75
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
76
tcg_cmp, 0, label_match);
77
78
- gen_goto_tb(s, 0, s->pc);
79
+ gen_goto_tb(s, 0, s->base.pc_next);
80
gen_set_label(label_match);
81
gen_goto_tb(s, 1, addr);
82
}
83
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
84
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
85
tcg_cmp, 0, label_match);
86
tcg_temp_free_i64(tcg_cmp);
87
- gen_goto_tb(s, 0, s->pc);
88
+ gen_goto_tb(s, 0, s->base.pc_next);
89
gen_set_label(label_match);
90
gen_goto_tb(s, 1, addr);
91
}
92
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
93
/* genuinely conditional branches */
94
TCGLabel *label_match = gen_new_label();
95
arm_gen_test_cc(cond, label_match);
96
- gen_goto_tb(s, 0, s->pc);
97
+ gen_goto_tb(s, 0, s->base.pc_next);
98
gen_set_label(label_match);
99
gen_goto_tb(s, 1, addr);
100
} else {
101
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
102
* any pending interrupts immediately.
103
*/
104
reset_btype(s);
105
- gen_goto_tb(s, 0, s->pc);
106
+ gen_goto_tb(s, 0, s->base.pc_next);
107
return;
108
109
case 7: /* SB */
110
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
111
* MB and end the TB instead.
112
*/
113
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
114
- gen_goto_tb(s, 0, s->pc);
115
+ gen_goto_tb(s, 0, s->base.pc_next);
116
return;
117
118
default:
119
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
120
gen_a64_set_pc(s, dst);
121
/* BLR also needs to load return address */
122
if (opc == 1) {
123
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
124
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
125
}
29
break;
126
break;
30
127
31
case 25:    /* CMD25: WRITE_MULTIPLE_BLOCK */
128
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
32
- if (sd->spi)
129
gen_a64_set_pc(s, dst);
33
- goto unimplemented_cmd;
130
/* BLRAA also needs to load return address */
34
+ if (sd->spi) {
131
if (opc == 9) {
35
+ goto unimplemented_spi_cmd;
132
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
36
+ }
133
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
37
switch (sd->state) {
134
}
38
case sd_transfer_state:
39
/* Writing in SPI mode not implemented. */
40
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
41
break;
135
break;
42
136
43
case 27:    /* CMD27: PROGRAM_CSD */
137
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
44
- if (sd->spi)
138
{
45
- goto unimplemented_cmd;
139
uint32_t insn;
46
+ if (sd->spi) {
140
47
+ goto unimplemented_spi_cmd;
141
- s->pc_curr = s->pc;
48
+ }
142
- insn = arm_ldl_code(env, s->pc, s->sctlr_b);
49
switch (sd->state) {
143
+ s->pc_curr = s->base.pc_next;
50
case sd_transfer_state:
144
+ insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
51
sd->state = sd_receivingdata_state;
145
s->insn = insn;
52
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
146
- s->pc += 4;
53
147
+ s->base.pc_next += 4;
54
/* Lock card commands (Class 7) */
148
55
case 42:    /* CMD42: LOCK_UNLOCK */
149
s->fp_access_checked = false;
56
- if (sd->spi)
150
57
- goto unimplemented_cmd;
151
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
58
+ if (sd->spi) {
152
int bound, core_mmu_idx;
59
+ goto unimplemented_spi_cmd;
153
60
+ }
154
dc->isar = &arm_cpu->isar;
61
switch (sd->state) {
155
- dc->pc = dc->base.pc_first;
62
case sd_transfer_state:
156
dc->condjmp = 0;
63
sd->state = sd_receivingdata_state;
157
64
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
158
dc->aarch64 = 1;
65
qemu_log_mask(LOG_GUEST_ERROR, "SD: Unknown CMD%i\n", req.cmd);
159
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
66
return sd_illegal;
160
{
67
161
DisasContext *dc = container_of(dcbase, DisasContext, base);
68
- unimplemented_cmd:
162
69
+ unimplemented_spi_cmd:
163
- tcg_gen_insn_start(dc->pc, 0, 0);
70
/* Commands that are recognised but not yet implemented in SPI mode. */
164
+ tcg_gen_insn_start(dc->base.pc_next, 0, 0);
71
qemu_log_mask(LOG_UNIMP, "SD: CMD%i not implemented in SPI mode\n",
165
dc->insn_start = tcg_last_op();
72
req.cmd);
166
}
167
168
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
169
DisasContext *dc = container_of(dcbase, DisasContext, base);
170
171
if (bp->flags & BP_CPU) {
172
- gen_a64_set_pc_im(dc->pc);
173
+ gen_a64_set_pc_im(dc->base.pc_next);
174
gen_helper_check_breakpoints(cpu_env);
175
/* End the TB early; it likely won't be executed */
176
dc->base.is_jmp = DISAS_TOO_MANY;
177
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
178
to for it to be properly cleared -- thus we
179
increment the PC here so that the logic setting
180
tb->size below does the right thing. */
181
- dc->pc += 4;
182
+ dc->base.pc_next += 4;
183
dc->base.is_jmp = DISAS_NORETURN;
184
}
185
186
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
187
disas_a64_insn(env, dc);
188
}
189
190
- dc->base.pc_next = dc->pc;
191
translator_loop_temp_check(&dc->base);
192
}
193
194
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
195
*/
196
switch (dc->base.is_jmp) {
197
default:
198
- gen_a64_set_pc_im(dc->pc);
199
+ gen_a64_set_pc_im(dc->base.pc_next);
200
/* fall through */
201
case DISAS_EXIT:
202
case DISAS_JUMP:
203
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
204
switch (dc->base.is_jmp) {
205
case DISAS_NEXT:
206
case DISAS_TOO_MANY:
207
- gen_goto_tb(dc, 1, dc->pc);
208
+ gen_goto_tb(dc, 1, dc->base.pc_next);
209
break;
210
default:
211
case DISAS_UPDATE:
212
- gen_a64_set_pc_im(dc->pc);
213
+ gen_a64_set_pc_im(dc->base.pc_next);
214
/* fall through */
215
case DISAS_EXIT:
216
tcg_gen_exit_tb(NULL, 0);
217
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
218
case DISAS_SWI:
219
break;
220
case DISAS_WFE:
221
- gen_a64_set_pc_im(dc->pc);
222
+ gen_a64_set_pc_im(dc->base.pc_next);
223
gen_helper_wfe(cpu_env);
224
break;
225
case DISAS_YIELD:
226
- gen_a64_set_pc_im(dc->pc);
227
+ gen_a64_set_pc_im(dc->base.pc_next);
228
gen_helper_yield(cpu_env);
229
break;
230
case DISAS_WFI:
231
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
232
*/
233
TCGv_i32 tmp = tcg_const_i32(4);
234
235
- gen_a64_set_pc_im(dc->pc);
236
+ gen_a64_set_pc_im(dc->base.pc_next);
237
gen_helper_wfi(cpu_env, tmp);
238
tcg_temp_free_i32(tmp);
239
/* The helper doesn't necessarily throw an exception, but we
240
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
241
}
242
}
243
}
244
-
245
- /* Functions above can change dc->pc, so re-align db->pc_next */
246
- dc->base.pc_next = dc->pc;
247
}
248
249
static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
250
diff --git a/target/arm/translate.c b/target/arm/translate.c
251
index XXXXXXX..XXXXXXX 100644
252
--- a/target/arm/translate.c
253
+++ b/target/arm/translate.c
254
@@ -XXX,XX +XXX,XX @@ static inline void gen_blxns(DisasContext *s, int rm)
255
* We do however need to set the PC, because the blxns helper reads it.
256
* The blxns helper may throw an exception.
257
*/
258
- gen_set_pc_im(s, s->pc);
259
+ gen_set_pc_im(s, s->base.pc_next);
260
gen_helper_v7m_blxns(cpu_env, var);
261
tcg_temp_free_i32(var);
262
s->base.is_jmp = DISAS_EXIT;
263
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
264
* for single stepping.)
265
*/
266
s->svc_imm = imm16;
267
- gen_set_pc_im(s, s->pc);
268
+ gen_set_pc_im(s, s->base.pc_next);
269
s->base.is_jmp = DISAS_HVC;
270
}
271
272
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
273
tmp = tcg_const_i32(syn_aa32_smc());
274
gen_helper_pre_smc(cpu_env, tmp);
275
tcg_temp_free_i32(tmp);
276
- gen_set_pc_im(s, s->pc);
277
+ gen_set_pc_im(s, s->base.pc_next);
278
s->base.is_jmp = DISAS_SMC;
279
}
280
281
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
282
{
283
gen_set_condexec(s);
284
- gen_set_pc_im(s, s->pc - offset);
285
+ gen_set_pc_im(s, s->base.pc_next - offset);
286
gen_exception_internal(excp);
287
s->base.is_jmp = DISAS_NORETURN;
288
}
289
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,
290
int syn, uint32_t target_el)
291
{
292
gen_set_condexec(s);
293
- gen_set_pc_im(s, s->pc - offset);
294
+ gen_set_pc_im(s, s->base.pc_next - offset);
295
gen_exception(excp, syn, target_el);
296
s->base.is_jmp = DISAS_NORETURN;
297
}
298
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
299
TCGv_i32 tcg_syn;
300
301
gen_set_condexec(s);
302
- gen_set_pc_im(s, s->pc - offset);
303
+ gen_set_pc_im(s, s->base.pc_next - offset);
304
tcg_syn = tcg_const_i32(syn);
305
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
306
tcg_temp_free_i32(tcg_syn);
307
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
308
/* Force a TB lookup after an instruction that changes the CPU state. */
309
static inline void gen_lookup_tb(DisasContext *s)
310
{
311
- tcg_gen_movi_i32(cpu_R[15], s->pc);
312
+ tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
313
s->base.is_jmp = DISAS_EXIT;
314
}
315
316
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
317
{
318
#ifndef CONFIG_USER_ONLY
319
return (s->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
320
- ((s->pc - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
321
+ ((s->base.pc_next - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
322
#else
323
return true;
324
#endif
325
@@ -XXX,XX +XXX,XX @@ static void gen_nop_hint(DisasContext *s, int val)
326
*/
327
case 1: /* yield */
328
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
329
- gen_set_pc_im(s, s->pc);
330
+ gen_set_pc_im(s, s->base.pc_next);
331
s->base.is_jmp = DISAS_YIELD;
332
}
333
break;
334
case 3: /* wfi */
335
- gen_set_pc_im(s, s->pc);
336
+ gen_set_pc_im(s, s->base.pc_next);
337
s->base.is_jmp = DISAS_WFI;
338
break;
339
case 2: /* wfe */
340
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
341
- gen_set_pc_im(s, s->pc);
342
+ gen_set_pc_im(s, s->base.pc_next);
343
s->base.is_jmp = DISAS_WFE;
344
}
345
break;
346
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
347
if (isread) {
348
return 1;
349
}
350
- gen_set_pc_im(s, s->pc);
351
+ gen_set_pc_im(s, s->base.pc_next);
352
s->base.is_jmp = DISAS_WFI;
353
return 0;
354
default:
355
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
356
* self-modifying code correctly and also to take
357
* any pending interrupts immediately.
358
*/
359
- gen_goto_tb(s, 0, s->pc);
360
+ gen_goto_tb(s, 0, s->base.pc_next);
361
return;
362
case 7: /* sb */
363
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
364
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
365
* for TCG; MB and end the TB instead.
366
*/
367
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
368
- gen_goto_tb(s, 0, s->pc);
369
+ gen_goto_tb(s, 0, s->base.pc_next);
370
return;
371
default:
372
goto illegal_op;
373
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
374
int32_t offset;
375
376
tmp = tcg_temp_new_i32();
377
- tcg_gen_movi_i32(tmp, s->pc);
378
+ tcg_gen_movi_i32(tmp, s->base.pc_next);
379
store_reg(s, 14, tmp);
380
/* Sign-extend the 24-bit offset */
381
offset = (((int32_t)insn) << 8) >> 8;
382
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
383
/* branch link/exchange thumb (blx) */
384
tmp = load_reg(s, rm);
385
tmp2 = tcg_temp_new_i32();
386
- tcg_gen_movi_i32(tmp2, s->pc);
387
+ tcg_gen_movi_i32(tmp2, s->base.pc_next);
388
store_reg(s, 14, tmp2);
389
gen_bx(s, tmp);
390
break;
391
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
392
/* branch (and link) */
393
if (insn & (1 << 24)) {
394
tmp = tcg_temp_new_i32();
395
- tcg_gen_movi_i32(tmp, s->pc);
396
+ tcg_gen_movi_i32(tmp, s->base.pc_next);
397
store_reg(s, 14, tmp);
398
}
399
offset = sextract32(insn << 2, 0, 26);
400
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
401
break;
402
case 0xf:
403
/* swi */
404
- gen_set_pc_im(s, s->pc);
405
+ gen_set_pc_im(s, s->base.pc_next);
406
s->svc_imm = extract32(insn, 0, 24);
407
s->base.is_jmp = DISAS_SWI;
408
break;
409
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
410
411
if (insn & (1 << 14)) {
412
/* Branch and link. */
413
- tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
414
+ tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
415
}
416
417
offset += read_pc(s);
418
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
419
* and also to take any pending interrupts
420
* immediately.
421
*/
422
- gen_goto_tb(s, 0, s->pc);
423
+ gen_goto_tb(s, 0, s->base.pc_next);
424
break;
425
case 7: /* sb */
426
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
427
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
428
* for TCG; MB and end the TB instead.
429
*/
430
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
431
- gen_goto_tb(s, 0, s->pc);
432
+ gen_goto_tb(s, 0, s->base.pc_next);
433
break;
434
default:
435
goto illegal_op;
436
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
437
/* BLX/BX */
438
tmp = load_reg(s, rm);
439
if (link) {
440
- val = (uint32_t)s->pc | 1;
441
+ val = (uint32_t)s->base.pc_next | 1;
442
tmp2 = tcg_temp_new_i32();
443
tcg_gen_movi_i32(tmp2, val);
444
store_reg(s, 14, tmp2);
445
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
446
447
if (cond == 0xf) {
448
/* swi */
449
- gen_set_pc_im(s, s->pc);
450
+ gen_set_pc_im(s, s->base.pc_next);
451
s->svc_imm = extract32(insn, 0, 8);
452
s->base.is_jmp = DISAS_SWI;
453
break;
454
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
455
tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
456
457
tmp2 = tcg_temp_new_i32();
458
- tcg_gen_movi_i32(tmp2, s->pc | 1);
459
+ tcg_gen_movi_i32(tmp2, s->base.pc_next | 1);
460
store_reg(s, 14, tmp2);
461
gen_bx(s, tmp);
462
break;
463
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
464
tcg_gen_addi_i32(tmp, tmp, offset);
465
466
tmp2 = tcg_temp_new_i32();
467
- tcg_gen_movi_i32(tmp2, s->pc | 1);
468
+ tcg_gen_movi_i32(tmp2, s->base.pc_next | 1);
469
store_reg(s, 14, tmp2);
470
gen_bx(s, tmp);
471
} else {
472
@@ -XXX,XX +XXX,XX @@ undef:
473
474
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
475
{
476
- /* Return true if the insn at dc->pc might cross a page boundary.
477
+ /* Return true if the insn at dc->base.pc_next might cross a page boundary.
478
* (False positives are OK, false negatives are not.)
479
* We know this is a Thumb insn, and our caller ensures we are
480
- * only called if dc->pc is less than 4 bytes from the page
481
+ * only called if dc->base.pc_next is less than 4 bytes from the page
482
* boundary, so we cross the page if the first 16 bits indicate
483
* that this is a 32 bit insn.
484
*/
485
- uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
486
+ uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
487
488
- return !thumb_insn_is_16bit(s, s->pc, insn);
489
+ return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
490
}
491
492
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
493
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
494
uint32_t condexec, core_mmu_idx;
495
496
dc->isar = &cpu->isar;
497
- dc->pc = dc->base.pc_first;
498
dc->condjmp = 0;
499
500
dc->aarch64 = 0;
501
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
502
{
503
DisasContext *dc = container_of(dcbase, DisasContext, base);
504
505
- tcg_gen_insn_start(dc->pc,
506
+ tcg_gen_insn_start(dc->base.pc_next,
507
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
508
0);
509
dc->insn_start = tcg_last_op();
510
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
511
512
if (bp->flags & BP_CPU) {
513
gen_set_condexec(dc);
514
- gen_set_pc_im(dc, dc->pc);
515
+ gen_set_pc_im(dc, dc->base.pc_next);
516
gen_helper_check_breakpoints(cpu_env);
517
/* End the TB early; it's likely not going to be executed */
518
dc->base.is_jmp = DISAS_TOO_MANY;
519
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
520
tb->size below does the right thing. */
521
/* TODO: Advance PC by correct instruction length to
522
* avoid disassembler error messages */
523
- dc->pc += 2;
524
+ dc->base.pc_next += 2;
525
dc->base.is_jmp = DISAS_NORETURN;
526
}
527
528
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
529
{
530
#ifdef CONFIG_USER_ONLY
531
/* Intercept jump to the magic kernel page. */
532
- if (dc->pc >= 0xffff0000) {
533
+ if (dc->base.pc_next >= 0xffff0000) {
534
/* We always get here via a jump, so know we are not in a
535
conditional execution block. */
536
gen_exception_internal(EXCP_KERNEL_TRAP);
537
@@ -XXX,XX +XXX,XX @@ static void arm_post_translate_insn(DisasContext *dc)
538
gen_set_label(dc->condlabel);
539
dc->condjmp = 0;
540
}
541
- dc->base.pc_next = dc->pc;
542
translator_loop_temp_check(&dc->base);
543
}
544
545
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
546
return;
547
}
548
549
- dc->pc_curr = dc->pc;
550
- insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
551
+ dc->pc_curr = dc->base.pc_next;
552
+ insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
553
dc->insn = insn;
554
- dc->pc += 4;
555
+ dc->base.pc_next += 4;
556
disas_arm_insn(dc, insn);
557
558
arm_post_translate_insn(dc);
559
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
560
return;
561
}
562
563
- dc->pc_curr = dc->pc;
564
- insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
565
- is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
566
- dc->pc += 2;
567
+ dc->pc_curr = dc->base.pc_next;
568
+ insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
569
+ is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
570
+ dc->base.pc_next += 2;
571
if (!is_16bit) {
572
- uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
573
+ uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
574
575
insn = insn << 16 | insn2;
576
- dc->pc += 2;
577
+ dc->base.pc_next += 2;
578
}
579
dc->insn = insn;
580
581
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
582
* but isn't very efficient).
583
*/
584
if (dc->base.is_jmp == DISAS_NEXT
585
- && (dc->pc - dc->page_start >= TARGET_PAGE_SIZE
586
- || (dc->pc - dc->page_start >= TARGET_PAGE_SIZE - 3
587
+ && (dc->base.pc_next - dc->page_start >= TARGET_PAGE_SIZE
588
+ || (dc->base.pc_next - dc->page_start >= TARGET_PAGE_SIZE - 3
589
&& insn_crosses_page(env, dc)))) {
590
dc->base.is_jmp = DISAS_TOO_MANY;
591
}
592
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
593
case DISAS_NEXT:
594
case DISAS_TOO_MANY:
595
case DISAS_UPDATE:
596
- gen_set_pc_im(dc, dc->pc);
597
+ gen_set_pc_im(dc, dc->base.pc_next);
598
/* fall through */
599
default:
600
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
601
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
602
switch(dc->base.is_jmp) {
603
case DISAS_NEXT:
604
case DISAS_TOO_MANY:
605
- gen_goto_tb(dc, 1, dc->pc);
606
+ gen_goto_tb(dc, 1, dc->base.pc_next);
607
break;
608
case DISAS_JUMP:
609
gen_goto_ptr();
610
break;
611
case DISAS_UPDATE:
612
- gen_set_pc_im(dc, dc->pc);
613
+ gen_set_pc_im(dc, dc->base.pc_next);
614
/* fall through */
615
default:
616
/* indicate that the hash table must be used to find the next TB */
617
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
618
gen_set_label(dc->condlabel);
619
gen_set_condexec(dc);
620
if (unlikely(is_singlestepping(dc))) {
621
- gen_set_pc_im(dc, dc->pc);
622
+ gen_set_pc_im(dc, dc->base.pc_next);
623
gen_singlestep_exception(dc);
624
} else {
625
- gen_goto_tb(dc, 1, dc->pc);
626
+ gen_goto_tb(dc, 1, dc->base.pc_next);
627
}
628
}
629
-
630
- /* Functions above can change dc->pc, so re-align db->pc_next */
631
- dc->base.pc_next = dc->pc;
632
}
633
634
static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
73
--
635
--
74
2.16.1
636
2.20.1
75
637
76
638
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/32] sdcard: Don't always set the high capacity bit
[Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Don't set the high capacity bit by default as it will be set if required
3
The offset is variable depending on the instruction set, whereas
4
in the sd_set_csd() function.
4
we have stored values for the current pc and the next pc. Passing
5
5
in the actual value is clearer in intent.
6
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
6
7
and Peter Ogden <ogden@xilinx.com> from qemu/xilinx tag xilinx-v2015.4]
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20180215221325.7611-2-f4bug@amsat.org
10
Message-id: 20190807045335.1361-8-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
hw/sd/sd.c | 5 ++++-
13
target/arm/translate-a64.c | 25 ++++++++++++++-----------
14
1 file changed, 4 insertions(+), 1 deletion(-)
14
target/arm/translate-vfp.inc.c | 6 +++---
15
15
target/arm/translate.c | 31 ++++++++++++++++---------------
16
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
16
3 files changed, 33 insertions(+), 29 deletions(-)
17
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/sd/sd.c
20
--- a/target/arm/translate-a64.c
19
+++ b/hw/sd/sd.c
21
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
22
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
21
23
s->base.is_jmp = DISAS_NORETURN;
22
/* card power-up OK */
24
}
23
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
25
24
+
26
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
25
+ if (sd->size > 1 * G_BYTE) {
27
+static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
26
+ sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
28
uint32_t syndrome, uint32_t target_el)
27
+ }
29
{
28
}
30
- gen_a64_set_pc_im(s->base.pc_next - offset);
29
31
+ gen_a64_set_pc_im(pc);
30
static void sd_set_scr(SDState *sd)
32
gen_exception(excp, syndrome, target_el);
31
@@ -XXX,XX +XXX,XX @@ static void sd_set_csd(SDState *sd, uint64_t size)
33
s->base.is_jmp = DISAS_NORETURN;
32
sd->csd[13] = 0x40;
34
}
33
sd->csd[14] = 0x00;
35
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
34
sd->csd[15] = 0x00;
36
void unallocated_encoding(DisasContext *s)
35
- sd->ocr |= 1 << 30; /* High Capacity SD Memory Card */
37
{
36
}
38
/* Unallocated and reserved encodings are uncategorized */
37
}
39
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
40
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
41
default_exception_el(s));
42
}
43
44
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
45
return true;
46
}
47
48
- gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
49
- s->fp_excp_el);
50
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
51
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
52
return false;
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
56
bool sve_access_check(DisasContext *s)
57
{
58
if (s->sve_excp_el) {
59
- gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
60
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
61
s->sve_excp_el);
62
return false;
63
}
64
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
65
switch (op2_ll) {
66
case 1: /* SVC */
67
gen_ss_advance(s);
68
- gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16),
69
- default_exception_el(s));
70
+ gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
71
+ syn_aa64_svc(imm16), default_exception_el(s));
72
break;
73
case 2: /* HVC */
74
if (s->current_el == 0) {
75
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
76
gen_a64_set_pc_im(s->pc_curr);
77
gen_helper_pre_hvc(cpu_env);
78
gen_ss_advance(s);
79
- gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
80
+ gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
81
+ syn_aa64_hvc(imm16), 2);
82
break;
83
case 3: /* SMC */
84
if (s->current_el == 0) {
85
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
86
gen_helper_pre_smc(cpu_env, tmp);
87
tcg_temp_free_i32(tmp);
88
gen_ss_advance(s);
89
- gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
90
+ gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
91
+ syn_aa64_smc(imm16), 3);
92
break;
93
default:
94
unallocated_encoding(s);
95
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
96
if (s->btype != 0
97
&& s->guarded_page
98
&& !btype_destination_ok(insn, s->bt, s->btype)) {
99
- gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype),
100
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
101
+ syn_btitrap(s->btype),
102
default_exception_el(s));
103
return;
104
}
105
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/arm/translate-vfp.inc.c
108
+++ b/target/arm/translate-vfp.inc.c
109
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
110
{
111
if (s->fp_excp_el) {
112
if (arm_dc_feature(s, ARM_FEATURE_M)) {
113
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
114
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
115
s->fp_excp_el);
116
} else {
117
- gen_exception_insn(s, 4, EXCP_UDEF,
118
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
119
syn_fp_access_trap(1, 0xe, false),
120
s->fp_excp_el);
121
}
122
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
123
124
if (!s->vfp_enabled && !ignore_vfp_enabled) {
125
assert(!arm_dc_feature(s, ARM_FEATURE_M));
126
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
127
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
128
default_exception_el(s));
129
return false;
130
}
131
diff --git a/target/arm/translate.c b/target/arm/translate.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/translate.c
134
+++ b/target/arm/translate.c
135
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
136
s->base.is_jmp = DISAS_NORETURN;
137
}
138
139
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
140
+static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
141
int syn, uint32_t target_el)
142
{
143
gen_set_condexec(s);
144
- gen_set_pc_im(s, s->base.pc_next - offset);
145
+ gen_set_pc_im(s, pc);
146
gen_exception(excp, syn, target_el);
147
s->base.is_jmp = DISAS_NORETURN;
148
}
149
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
150
return;
151
}
152
153
- gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(),
154
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
155
default_exception_el(s));
156
}
157
158
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
159
160
undef:
161
/* If we get here then some access check did not pass */
162
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
163
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
164
+ syn_uncategorized(), exc_target);
165
return false;
166
}
167
168
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
169
* for attempts to execute invalid vfp/neon encodings with FP disabled.
170
*/
171
if (s->fp_excp_el) {
172
- gen_exception_insn(s, 4, EXCP_UDEF,
173
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
174
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
175
return 0;
176
}
177
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
178
* for attempts to execute invalid vfp/neon encodings with FP disabled.
179
*/
180
if (s->fp_excp_el) {
181
- gen_exception_insn(s, 4, EXCP_UDEF,
182
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
183
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
184
return 0;
185
}
186
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
187
}
188
189
if (s->fp_excp_el) {
190
- gen_exception_insn(s, 4, EXCP_UDEF,
191
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
192
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
193
return 0;
194
}
195
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
196
off_rm = vfp_reg_offset(0, rm);
197
}
198
if (s->fp_excp_el) {
199
- gen_exception_insn(s, 4, EXCP_UDEF,
200
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
201
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
202
return 0;
203
}
204
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
205
* For the UNPREDICTABLE cases we choose to UNDEF.
206
*/
207
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
208
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
209
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
210
return;
211
}
212
213
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
214
}
215
216
if (undef) {
217
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
218
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
219
default_exception_el(s));
220
return;
221
}
222
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
223
* UsageFault exception.
224
*/
225
if (arm_dc_feature(s, ARM_FEATURE_M)) {
226
- gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
227
+ gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
228
default_exception_el(s));
229
return;
230
}
231
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
232
break;
233
default:
234
illegal_op:
235
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
236
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
237
default_exception_el(s));
238
break;
239
}
240
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
241
}
242
243
/* All other insns: NOCP */
244
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
245
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
246
default_exception_el(s));
247
break;
248
}
249
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
250
}
251
return;
252
illegal_op:
253
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
254
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
255
default_exception_el(s));
256
}
257
258
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
259
return;
260
illegal_op:
261
undef:
262
- gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
263
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
264
default_exception_el(s));
265
}
38
266
39
--
267
--
40
2.16.1
268
2.20.1
41
269
42
270
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/32] sdcard: use the registerfields API to access the OCR register
[Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The offset is variable depending on the instruction set.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
Passing in the actual value is clearer in intent.
5
Message-id: 20180215220540.6556-12-f4bug@amsat.org
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-9-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
include/hw/sd/sd.h | 1 -
12
target/arm/translate-a64.c | 8 ++++----
9
hw/sd/sd.c | 21 +++++++++++++--------
13
target/arm/translate.c | 8 ++++----
10
2 files changed, 13 insertions(+), 9 deletions(-)
14
2 files changed, 8 insertions(+), 8 deletions(-)
11
15
12
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/sd/sd.h
18
--- a/target/arm/translate-a64.c
15
+++ b/include/hw/sd/sd.h
19
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
17
#define READY_FOR_DATA        (1 << 8)
21
tcg_temp_free_i32(tcg_excp);
18
#define APP_CMD            (1 << 5)
22
}
19
#define AKE_SEQ_ERROR        (1 << 3)
23
20
-#define OCR_CCS_BITN 30
24
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
21
25
+static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
22
typedef enum {
26
{
23
SD_VOLTAGE_0_4V = 400, /* currently not supported */
27
- gen_a64_set_pc_im(s->base.pc_next - offset);
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
28
+ gen_a64_set_pc_im(pc);
29
gen_exception_internal(excp);
30
s->base.is_jmp = DISAS_NORETURN;
31
}
32
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
33
break;
34
}
35
#endif
36
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
37
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
38
} else {
39
unsupported_encoding(s, insn);
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
42
/* End the TB early; it likely won't be executed */
43
dc->base.is_jmp = DISAS_TOO_MANY;
44
} else {
45
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
46
+ gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
47
/* The address covered by the breakpoint must be
48
included in [tb->pc, tb->pc + tb->size) in order
49
to for it to be properly cleared -- thus we
50
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
52
--- a/target/arm/translate.c
27
+++ b/hw/sd/sd.c
53
+++ b/target/arm/translate.c
28
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
29
#include "qemu/osdep.h"
55
s->base.is_jmp = DISAS_SMC;
30
#include "hw/qdev.h"
31
#include "hw/hw.h"
32
+#include "hw/registerfields.h"
33
#include "sysemu/block-backend.h"
34
#include "hw/sd/sd.h"
35
#include "qapi/error.h"
36
@@ -XXX,XX +XXX,XX @@
37
//#define DEBUG_SD 1
38
39
#define ACMD41_ENQUIRY_MASK 0x00ffffff
40
-#define OCR_POWER_UP 0x80000000
41
-#define OCR_POWER_DELAY_NS 500000 /* 0.5ms */
42
43
typedef enum {
44
sd_r0 = 0, /* no response */
45
@@ -XXX,XX +XXX,XX @@ static uint16_t sd_crc16(void *message, size_t width)
46
return shift_reg;
47
}
56
}
48
57
49
+#define OCR_POWER_DELAY_NS 500000 /* 0.5ms */
58
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
50
+
59
+static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
51
+FIELD(OCR, CARD_CAPACITY, 30, 1) /* 0:SDSC, 1:SDHC/SDXC */
52
+FIELD(OCR, CARD_POWER_UP, 31, 1)
53
+
54
static void sd_set_ocr(SDState *sd)
55
{
60
{
56
/* All voltages OK, Standard Capacity SD Memory Card, not yet powered up */
61
gen_set_condexec(s);
57
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
62
- gen_set_pc_im(s, s->base.pc_next - offset);
58
SDState *sd = opaque;
63
+ gen_set_pc_im(s, pc);
59
64
gen_exception_internal(excp);
60
trace_sdcard_powerup();
65
s->base.is_jmp = DISAS_NORETURN;
61
- /* Set powered up bit in OCR */
62
- assert(!(sd->ocr & OCR_POWER_UP));
63
- sd->ocr |= OCR_POWER_UP;
64
+ assert(!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP));
65
+
66
+ /* card power-up OK */
67
+ sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
68
}
66
}
69
67
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
70
static void sd_set_scr(SDState *sd)
68
s->current_el != 0 &&
71
@@ -XXX,XX +XXX,XX @@ static bool sd_ocr_vmstate_needed(void *opaque)
69
#endif
72
SDState *sd = opaque;
70
(imm == (s->thumb ? 0x3c : 0xf000))) {
73
71
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
74
/* Include the OCR state (and timer) if it is not yet powered up */
72
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
75
- return !(sd->ocr & OCR_POWER_UP);
76
+ return !FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP);
77
}
78
79
static const VMStateDescription sd_ocr_vmstate = {
80
@@ -XXX,XX +XXX,XX @@ static void sd_erase(SDState *sd)
81
return;
73
return;
82
}
74
}
83
75
84
- if (extract32(sd->ocr, OCR_CCS_BITN, 1)) {
76
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
85
+ if (FIELD_EX32(sd->ocr, OCR, CARD_CAPACITY)) {
77
/* End the TB early; it's likely not going to be executed */
86
/* High capacity memory card: erase units are 512 byte blocks */
78
dc->base.is_jmp = DISAS_TOO_MANY;
87
erase_start *= 512;
79
} else {
88
erase_end *= 512;
80
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
89
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_app_command(SDState *sd,
81
+ gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
90
* UEFI, which sends an initial enquiry ACMD41, but
82
/* The address covered by the breakpoint must be
91
* assumes that the card is in ready state as soon as it
83
included in [tb->pc, tb->pc + tb->size) in order
92
* sees the power up bit set. */
84
to for it to be properly cleared -- thus we
93
- if (!(sd->ocr & OCR_POWER_UP)) {
94
+ if (!FIELD_EX32(sd->ocr, OCR, CARD_POWER_UP)) {
95
if ((req.arg & ACMD41_ENQUIRY_MASK) != 0) {
96
timer_del(sd->ocr_power_timer);
97
sd_ocr_powerup(sd);
98
--
85
--
99
2.16.1
86
2.20.1
100
87
101
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/32] hw/sd/milkymist-memcard: expose a SDBus and connect the SDCard to it
[Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
using the sdbus_*() API.
3
Unlike the other more generic gen_exception{,_internal}_insn
4
interfaces, breakpoints always refer to the current instruction.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Acked-by: Michael Walle <michael@walle.cc>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20180216022933.10945-4-f4bug@amsat.org
9
Message-id: 20190807045335.1361-10-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/sd/milkymist-memcard.c | 38 +++++++++++++++++++++-----------------
12
target/arm/translate-a64.c | 7 +++----
12
1 file changed, 21 insertions(+), 17 deletions(-)
13
target/arm/translate.c | 8 ++++----
14
2 files changed, 7 insertions(+), 8 deletions(-)
13
15
14
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/sd/milkymist-memcard.c
18
--- a/target/arm/translate-a64.c
17
+++ b/hw/sd/milkymist-memcard.c
19
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ struct MilkymistMemcardState {
20
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
19
SysBusDevice parent_obj;
21
s->base.is_jmp = DISAS_NORETURN;
20
22
}
21
MemoryRegion regs_region;
23
22
- SDState *card;
24
-static void gen_exception_bkpt_insn(DisasContext *s, int offset,
23
+ SDBus sdbus;
25
- uint32_t syndrome)
24
26
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
25
int command_write_ptr;
27
{
26
int response_read_ptr;
28
TCGv_i32 tcg_syn;
27
@@ -XXX,XX +XXX,XX @@ static void memcard_sd_command(MilkymistMemcardState *s)
29
28
req.crc = s->command[5];
30
- gen_a64_set_pc_im(s->base.pc_next - offset);
29
31
+ gen_a64_set_pc_im(s->pc_curr);
30
s->response[0] = req.cmd;
32
tcg_syn = tcg_const_i32(syndrome);
31
- s->response_len = sd_do_command(s->card, &req, s->response+1);
33
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
32
+ s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
34
tcg_temp_free_i32(tcg_syn);
33
s->response_read_ptr = 0;
35
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
34
35
if (s->response_len == 16) {
36
@@ -XXX,XX +XXX,XX @@ static uint64_t memcard_read(void *opaque, hwaddr addr,
37
r = 0xffffffff;
38
} else {
39
r = 0;
40
- r |= sd_read_data(s->card) << 24;
41
- r |= sd_read_data(s->card) << 16;
42
- r |= sd_read_data(s->card) << 8;
43
- r |= sd_read_data(s->card);
44
+ r |= sdbus_read_data(&s->sdbus) << 24;
45
+ r |= sdbus_read_data(&s->sdbus) << 16;
46
+ r |= sdbus_read_data(&s->sdbus) << 8;
47
+ r |= sdbus_read_data(&s->sdbus);
48
}
49
break;
50
case R_CLK2XDIV:
51
@@ -XXX,XX +XXX,XX @@ static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
52
if (!s->enabled) {
53
break;
36
break;
54
}
37
}
55
- sd_write_data(s->card, (value >> 24) & 0xff);
38
/* BRK */
56
- sd_write_data(s->card, (value >> 16) & 0xff);
39
- gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16));
57
- sd_write_data(s->card, (value >> 8) & 0xff);
40
+ gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
58
- sd_write_data(s->card, value & 0xff);
59
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
60
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
61
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
62
+ sdbus_write_data(&s->sdbus, value & 0xff);
63
break;
41
break;
64
case R_ENABLE:
42
case 2:
65
s->regs[addr] = value;
43
if (op2_ll != 0) {
66
@@ -XXX,XX +XXX,XX @@ static void milkymist_memcard_reset(DeviceState *d)
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
67
for (i = 0; i < R_MAX; i++) {
45
index XXXXXXX..XXXXXXX 100644
68
s->regs[i] = 0;
46
--- a/target/arm/translate.c
69
}
47
+++ b/target/arm/translate.c
70
- /* Since we're still using the legacy SD API the card is not plugged
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
71
- * into any bus, and we must reset it manually.
49
s->base.is_jmp = DISAS_NORETURN;
72
- */
73
- device_reset(DEVICE(s->card));
74
}
50
}
75
51
76
static void milkymist_memcard_init(Object *obj)
52
-static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
77
@@ -XXX,XX +XXX,XX @@ static void milkymist_memcard_init(Object *obj)
53
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
78
static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
79
{
54
{
80
MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
55
TCGv_i32 tcg_syn;
81
+ DeviceState *carddev;
56
82
BlockBackend *blk;
57
gen_set_condexec(s);
83
DriveInfo *dinfo;
58
- gen_set_pc_im(s, s->base.pc_next - offset);
84
+ Error *err = NULL;
59
+ gen_set_pc_im(s, s->pc_curr);
85
60
tcg_syn = tcg_const_i32(syn);
86
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
61
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
87
+ dev, "sd-bus");
62
tcg_temp_free_i32(tcg_syn);
88
+
63
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
89
+ /* Create and plug in the sd card */
64
case 1:
90
/* FIXME use a qdev drive property instead of drive_get_next() */
65
/* bkpt */
91
dinfo = drive_get_next(IF_SD);
66
ARCH(5);
92
blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
67
- gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
93
- s->card = sd_init(blk, false);
68
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
94
- if (s->card == NULL) {
69
break;
95
- error_setg(errp, "failed to init SD card");
70
case 2:
96
+ carddev = qdev_create(&s->sdbus.qbus, TYPE_SD_CARD);
71
/* Hypervisor call (v7) */
97
+ qdev_prop_set_drive(carddev, "drive", blk, &err);
72
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
98
+ object_property_set_bool(OBJECT(carddev), true, "realized", &err);
73
{
99
+ if (err) {
74
int imm8 = extract32(insn, 0, 8);
100
+ error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
75
ARCH(5);
101
return;
76
- gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
102
}
77
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
103
s->enabled = blk && blk_is_inserted(blk);
78
break;
79
}
80
104
--
81
--
105
2.16.1
82
2.20.1
106
83
107
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/32] sdcard: define SDMMC_CMD_MAX instead of using the magic '64'
[Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Promote this function from aarch64 to fully general use.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
Use it to unify the code sequences for generating illegal
5
Message-id: 20180215220540.6556-8-f4bug@amsat.org
5
opcode exceptions.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190807045335.1361-11-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/sd/sdmmc-internal.h | 15 +++++++++++++++
13
target/arm/translate-a64.h | 2 --
9
hw/sd/sd.c | 22 ++++++++++++++++------
14
target/arm/translate.h | 2 ++
10
2 files changed, 31 insertions(+), 6 deletions(-)
15
target/arm/translate-a64.c | 7 -------
11
create mode 100644 hw/sd/sdmmc-internal.h
16
target/arm/translate-vfp.inc.c | 3 +--
17
target/arm/translate.c | 22 ++++++++++++----------
18
5 files changed, 15 insertions(+), 21 deletions(-)
12
19
13
diff --git a/hw/sd/sdmmc-internal.h b/hw/sd/sdmmc-internal.h
20
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
14
new file mode 100644
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX
22
--- a/target/arm/translate-a64.h
16
--- /dev/null
23
+++ b/target/arm/translate-a64.h
17
+++ b/hw/sd/sdmmc-internal.h
18
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
19
+/*
25
#ifndef TARGET_ARM_TRANSLATE_A64_H
20
+ * SD/MMC cards common
26
#define TARGET_ARM_TRANSLATE_A64_H
21
+ *
27
22
+ * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>
28
-void unallocated_encoding(DisasContext *s);
23
+ *
29
-
24
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
30
#define unsupported_encoding(s, insn) \
25
+ * See the COPYING file in the top-level directory.
31
do { \
26
+ * SPDX-License-Identifier: GPL-2.0-or-later
32
qemu_log_mask(LOG_UNIMP, \
27
+ */
33
diff --git a/target/arm/translate.h b/target/arm/translate.h
28
+#ifndef SD_INTERNAL_H
34
index XXXXXXX..XXXXXXX 100644
29
+#define SD_INTERNAL_H
35
--- a/target/arm/translate.h
36
+++ b/target/arm/translate.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct DisasCompare {
38
bool value_global;
39
} DisasCompare;
40
41
+void unallocated_encoding(DisasContext *s);
30
+
42
+
31
+#define SDMMC_CMD_MAX 64
43
/* Share the TCG temporaries common between 32 and 64 bit modes. */
32
+
44
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
33
+#endif
45
extern TCGv_i64 cpu_exclusive_addr;
34
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
46
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
35
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/sd/sd.c
48
--- a/target/arm/translate-a64.c
37
+++ b/hw/sd/sd.c
49
+++ b/target/arm/translate-a64.c
38
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
39
#include "qemu/error-report.h"
40
#include "qemu/timer.h"
41
#include "qemu/log.h"
42
+#include "sdmmc-internal.h"
43
#include "trace.h"
44
45
//#define DEBUG_SD 1
46
@@ -XXX,XX +XXX,XX @@ static void sd_set_mode(SDState *sd)
47
}
51
}
48
}
52
}
49
53
50
-static const sd_cmd_type_t sd_cmd_type[64] = {
54
-void unallocated_encoding(DisasContext *s)
51
+static const sd_cmd_type_t sd_cmd_type[SDMMC_CMD_MAX] = {
55
-{
52
sd_bc, sd_none, sd_bcr, sd_bcr, sd_none, sd_none, sd_none, sd_ac,
56
- /* Unallocated and reserved encodings are uncategorized */
53
sd_bcr, sd_ac, sd_ac, sd_adtc, sd_ac, sd_ac, sd_none, sd_ac,
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
54
+ /* 16 */
58
- default_exception_el(s));
55
sd_ac, sd_adtc, sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none,
59
-}
56
sd_adtc, sd_adtc, sd_adtc, sd_adtc, sd_ac, sd_ac, sd_adtc, sd_none,
60
-
57
+ /* 32 */
61
static void init_tmp_a64_array(DisasContext *s)
58
sd_ac, sd_ac, sd_none, sd_none, sd_none, sd_none, sd_ac, sd_none,
62
{
59
sd_none, sd_none, sd_bc, sd_none, sd_none, sd_none, sd_none, sd_none,
63
#ifdef CONFIG_DEBUG_TCG
60
+ /* 48 */
64
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
61
sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_ac,
65
index XXXXXXX..XXXXXXX 100644
62
sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none,
66
--- a/target/arm/translate-vfp.inc.c
63
};
67
+++ b/target/arm/translate-vfp.inc.c
64
68
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
65
-static const int sd_cmd_class[64] = {
69
66
+static const int sd_cmd_class[SDMMC_CMD_MAX] = {
70
if (!s->vfp_enabled && !ignore_vfp_enabled) {
67
0, 0, 0, 0, 0, 9, 10, 0, 0, 0, 0, 1, 0, 0, 0, 0,
71
assert(!arm_dc_feature(s, ARM_FEATURE_M));
68
2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 6, 6, 6, 6,
72
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
69
5, 5, 10, 10, 10, 10, 5, 9, 9, 9, 7, 7, 7, 7, 7, 7,
73
- default_exception_el(s));
70
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
74
+ unallocated_encoding(s);
71
/* Not interpreting this as an app command */
75
return false;
72
sd->card_status &= ~APP_CMD;
73
74
- if (sd_cmd_type[req.cmd & 0x3F] == sd_ac
75
- || sd_cmd_type[req.cmd & 0x3F] == sd_adtc) {
76
+ if (sd_cmd_type[req.cmd] == sd_ac
77
+ || sd_cmd_type[req.cmd] == sd_adtc) {
78
rca = req.arg >> 16;
79
}
76
}
80
77
81
@@ -XXX,XX +XXX,XX @@ static int cmd_valid_while_locked(SDState *sd, SDRequest *req)
78
diff --git a/target/arm/translate.c b/target/arm/translate.c
82
if (req->cmd == 16 || req->cmd == 55) {
79
index XXXXXXX..XXXXXXX 100644
83
return 1;
80
--- a/target/arm/translate.c
81
+++ b/target/arm/translate.c
82
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
83
s->base.is_jmp = DISAS_NORETURN;
84
}
85
86
+void unallocated_encoding(DisasContext *s)
87
+{
88
+ /* Unallocated and reserved encodings are uncategorized */
89
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
90
+ default_exception_el(s));
91
+}
92
+
93
/* Force a TB lookup after an instruction that changes the CPU state. */
94
static inline void gen_lookup_tb(DisasContext *s)
95
{
96
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
97
return;
84
}
98
}
85
- return sd_cmd_class[req->cmd & 0x3F] == 0
99
86
- || sd_cmd_class[req->cmd & 0x3F] == 7;
100
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
87
+ return sd_cmd_class[req->cmd] == 0
101
- default_exception_el(s));
88
+ || sd_cmd_class[req->cmd] == 7;
102
+ unallocated_encoding(s);
89
}
103
}
90
104
91
int sd_do_command(SDState *sd, SDRequest *req,
105
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
92
@@ -XXX,XX +XXX,XX @@ int sd_do_command(SDState *sd, SDRequest *req,
106
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
93
goto send_response;
94
}
107
}
95
108
96
+ if (req->cmd >= SDMMC_CMD_MAX) {
109
if (undef) {
97
+ qemu_log_mask(LOG_GUEST_ERROR, "SD: incorrect command 0x%02x\n",
110
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
98
+ req->cmd);
111
- default_exception_el(s));
99
+ req->cmd &= 0x3f;
112
+ unallocated_encoding(s);
100
+ }
113
return;
101
+
114
}
102
if (sd->card_status & CARD_IS_LOCKED) {
115
103
if (!cmd_valid_while_locked(sd, req)) {
116
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
104
sd->card_status |= ILLEGAL_COMMAND;
117
break;
118
default:
119
illegal_op:
120
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
121
- default_exception_el(s));
122
+ unallocated_encoding(s);
123
break;
124
}
125
}
126
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
127
}
128
return;
129
illegal_op:
130
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
131
- default_exception_el(s));
132
+ unallocated_encoding(s);
133
}
134
135
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
136
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
137
return;
138
illegal_op:
139
undef:
140
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
141
- default_exception_el(s));
142
+ unallocated_encoding(s);
143
}
144
145
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
105
--
146
--
106
2.16.1
147
2.20.1
107
148
108
149
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/32] sdcard: update the CSD CRC register regardless the CSD structure version
[Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Replace x = double_saturate(y) with x = add_saturate(y, y).
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
There is no need for a separate more specialized helper.
5
Message-id: 20180215221325.7611-3-f4bug@amsat.org
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190807045335.1361-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
hw/sd/sd.c | 3 +--
12
target/arm/helper.h | 1 -
9
1 file changed, 1 insertion(+), 2 deletions(-)
13
target/arm/op_helper.c | 15 ---------------
14
target/arm/translate.c | 4 ++--
15
3 files changed, 2 insertions(+), 18 deletions(-)
10
16
11
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sd.c
19
--- a/target/arm/helper.h
14
+++ b/hw/sd/sd.c
20
+++ b/target/arm/helper.h
15
@@ -XXX,XX +XXX,XX @@ static void sd_set_csd(SDState *sd, uint64_t size)
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32)
16
sd->csd[13] = 0x20 |    /* Max. write data block length */
22
DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
17
((HWBLOCK_SHIFT << 6) & 0xc0);
23
DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
18
sd->csd[14] = 0x00;    /* File format group */
24
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
19
- sd->csd[15] = (sd_crc7(sd->csd, 15) << 1) | 1;
25
-DEF_HELPER_2(double_saturate, i32, env, s32)
20
} else {            /* SDHC */
26
DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32)
21
size /= 512 * 1024;
27
DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32)
22
size -= 1;
28
DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
23
@@ -XXX,XX +XXX,XX @@ static void sd_set_csd(SDState *sd, uint64_t size)
29
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
24
sd->csd[12] = 0x0a;
30
index XXXXXXX..XXXXXXX 100644
25
sd->csd[13] = 0x40;
31
--- a/target/arm/op_helper.c
26
sd->csd[14] = 0x00;
32
+++ b/target/arm/op_helper.c
27
- sd->csd[15] = 0x00;
33
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
28
}
34
return res;
29
+ sd->csd[15] = (sd_crc7(sd->csd, 15) << 1) | 1;
30
}
35
}
31
36
32
static void sd_set_rca(SDState *sd)
37
-uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
38
-{
39
- uint32_t res;
40
- if (val >= 0x40000000) {
41
- res = ~SIGNBIT;
42
- env->QF = 1;
43
- } else if (val <= (int32_t)0xc0000000) {
44
- res = SIGNBIT;
45
- env->QF = 1;
46
- } else {
47
- res = val << 1;
48
- }
49
- return res;
50
-}
51
-
52
uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
53
{
54
uint32_t res = a + b;
55
diff --git a/target/arm/translate.c b/target/arm/translate.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/translate.c
58
+++ b/target/arm/translate.c
59
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
60
tmp = load_reg(s, rm);
61
tmp2 = load_reg(s, rn);
62
if (op1 & 2)
63
- gen_helper_double_saturate(tmp2, cpu_env, tmp2);
64
+ gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2);
65
if (op1 & 1)
66
gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
67
else
68
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
69
tmp = load_reg(s, rn);
70
tmp2 = load_reg(s, rm);
71
if (op & 1)
72
- gen_helper_double_saturate(tmp, cpu_env, tmp);
73
+ gen_helper_add_saturate(tmp, cpu_env, tmp, tmp);
74
if (op & 2)
75
gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
76
else
33
--
77
--
34
2.16.1
78
2.20.1
35
79
36
80
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/32] hw/sd/milkymist-memcard: split realize() out of SysBusDevice init()
[Qemu-devel] [PULL 17/29] target/arm/cpu64: Ensure kvm really supports aarch64=off
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Create the SDCard in the realize() function.
3
If -cpu <cpu>,aarch64=off is used then KVM must also be used, and it
4
and the host must support running the vcpu in 32-bit mode. Also, if
5
-cpu <cpu>,aarch64=on is used, then it doesn't matter if kvm is
6
enabled or not.
4
7
5
Suggested-by: Michael Walle <michael@walle.cc>
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Acked-by: Michael Walle <michael@walle.cc>
9
Message-id: 20180216022933.10945-3-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
hw/sd/milkymist-memcard.c | 28 ++++++++++++++++------------
12
target/arm/kvm_arm.h | 14 ++++++++++++++
13
1 file changed, 16 insertions(+), 12 deletions(-)
13
target/arm/cpu64.c | 12 ++++++------
14
target/arm/kvm64.c | 9 +++++++++
15
3 files changed, 29 insertions(+), 6 deletions(-)
14
16
15
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
17
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/sd/milkymist-memcard.c
19
--- a/target/arm/kvm_arm.h
18
+++ b/hw/sd/milkymist-memcard.c
20
+++ b/target/arm/kvm_arm.h
19
@@ -XXX,XX +XXX,XX @@ static void milkymist_memcard_reset(DeviceState *d)
21
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
20
device_reset(DEVICE(s->card));
22
*/
23
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
24
25
+/**
26
+ * kvm_arm_aarch32_supported:
27
+ * @cs: CPUState
28
+ *
29
+ * Returns: true if the KVM VCPU can enable AArch32 mode
30
+ * and false otherwise.
31
+ */
32
+bool kvm_arm_aarch32_supported(CPUState *cs);
33
+
34
/**
35
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
36
* IPA address space supported by KVM
37
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
38
cpu->host_cpu_probe_failed = true;
21
}
39
}
22
40
23
-static int milkymist_memcard_init(SysBusDevice *dev)
41
+static inline bool kvm_arm_aarch32_supported(CPUState *cs)
24
+static void milkymist_memcard_init(Object *obj)
25
+{
42
+{
26
+ MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
43
+ return false;
27
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
28
+
29
+ memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
30
+ "milkymist-memcard", R_MAX * 4);
31
+ sysbus_init_mmio(dev, &s->regs_region);
32
+}
44
+}
33
+
45
+
34
+static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
46
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
35
{
47
{
36
MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
48
return -ENOENT;
37
- DriveInfo *dinfo;
49
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
38
BlockBackend *blk;
50
index XXXXXXX..XXXXXXX 100644
39
+ DriveInfo *dinfo;
51
--- a/target/arm/cpu64.c
40
52
+++ b/target/arm/cpu64.c
41
/* FIXME use a qdev drive property instead of drive_get_next() */
53
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
42
dinfo = drive_get_next(IF_SD);
54
* restriction allows us to avoid fixing up functionality that assumes a
43
blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
55
* uniform execution state like do_interrupt.
44
s->card = sd_init(blk, false);
56
*/
45
if (s->card == NULL) {
57
- if (!kvm_enabled()) {
46
- return -1;
58
- error_setg(errp, "'aarch64' feature cannot be disabled "
47
+ error_setg(errp, "failed to init SD card");
59
- "unless KVM is enabled");
48
+ return;
60
- return;
49
}
61
- }
50
-
62
-
51
s->enabled = blk && blk_is_inserted(blk);
63
if (value == false) {
52
-
64
+ if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
53
- memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
65
+ error_setg(errp, "'aarch64' feature cannot be disabled "
54
- "milkymist-memcard", R_MAX * 4);
66
+ "unless KVM is enabled and 32-bit EL1 "
55
- sysbus_init_mmio(dev, &s->regs_region);
67
+ "is supported");
56
-
68
+ return;
57
- return 0;
69
+ }
70
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
71
} else {
72
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
73
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/arm/kvm64.c
76
+++ b/target/arm/kvm64.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "exec/gdbstub.h"
79
#include "sysemu/sysemu.h"
80
#include "sysemu/kvm.h"
81
+#include "sysemu/kvm_int.h"
82
#include "kvm_arm.h"
83
+#include "hw/boards.h"
84
#include "internals.h"
85
86
static bool have_guest_debug;
87
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
88
return true;
58
}
89
}
59
90
60
static const VMStateDescription vmstate_milkymist_memcard = {
91
+bool kvm_arm_aarch32_supported(CPUState *cpu)
61
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_milkymist_memcard = {
92
+{
62
static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
93
+ KVMState *s = KVM_STATE(current_machine->accelerator);
63
{
94
+
64
DeviceClass *dc = DEVICE_CLASS(klass);
95
+ return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
65
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
96
+}
66
97
+
67
- k->init = milkymist_memcard_init;
98
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
68
+ dc->realize = milkymist_memcard_realize;
99
69
dc->reset = milkymist_memcard_reset;
100
int kvm_arch_init_vcpu(CPUState *cs)
70
dc->vmsd = &vmstate_milkymist_memcard;
71
/* Reason: init() method uses drive_get_next() */
72
@@ -XXX,XX +XXX,XX @@ static const TypeInfo milkymist_memcard_info = {
73
.name = TYPE_MILKYMIST_MEMCARD,
74
.parent = TYPE_SYS_BUS_DEVICE,
75
.instance_size = sizeof(MilkymistMemcardState),
76
+ .instance_init = milkymist_memcard_init,
77
.class_init = milkymist_memcard_class_init,
78
};
79
80
--
101
--
81
2.16.1
102
2.20.1
82
103
83
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/32] sdcard: replace DPRINTF() by trace events
[Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
We first convert the pmu property from a static property to one with
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
its own accessors. Then we use the set accessor to check if the PMU is
5
Message-id: 20180215220540.6556-3-f4bug@amsat.org
5
supported when using KVM. Indeed a 32-bit KVM host does not support
6
the PMU, so this check will catch an attempt to use it at property-set
7
time.
8
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/sd/sd.c | 32 ++++++++++++++++++++++++++------
13
target/arm/kvm_arm.h | 14 ++++++++++++++
9
hw/sd/trace-events | 6 ++++++
14
target/arm/cpu.c | 30 +++++++++++++++++++++++++-----
10
2 files changed, 32 insertions(+), 6 deletions(-)
15
target/arm/kvm.c | 7 +++++++
16
3 files changed, 46 insertions(+), 5 deletions(-)
11
17
12
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
18
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
13
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sd.c
20
--- a/target/arm/kvm_arm.h
15
+++ b/hw/sd/sd.c
21
+++ b/target/arm/kvm_arm.h
16
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
17
#include "qemu/error-report.h"
23
*/
18
#include "qemu/timer.h"
24
bool kvm_arm_aarch32_supported(CPUState *cs);
19
#include "qemu/log.h"
25
20
+#include "trace.h"
26
+/**
21
27
+ * bool kvm_arm_pmu_supported:
22
//#define DEBUG_SD 1
28
+ * @cs: CPUState
23
29
+ *
24
@@ -XXX,XX +XXX,XX @@ struct SDState {
30
+ * Returns: true if the KVM VCPU can enable its PMU
25
bool cmd_line;
31
+ * and false otherwise.
26
};
32
+ */
27
33
+bool kvm_arm_pmu_supported(CPUState *cs);
28
+static const char *sd_state_name(enum SDCardStates state)
34
+
35
/**
36
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
37
* IPA address space supported by KVM
38
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_aarch32_supported(CPUState *cs)
39
return false;
40
}
41
42
+static inline bool kvm_arm_pmu_supported(CPUState *cs)
29
+{
43
+{
30
+ static const char *state_name[] = {
44
+ return false;
31
+ [sd_idle_state] = "idle",
32
+ [sd_ready_state] = "ready",
33
+ [sd_identification_state] = "identification",
34
+ [sd_standby_state] = "standby",
35
+ [sd_transfer_state] = "transfer",
36
+ [sd_sendingdata_state] = "sendingdata",
37
+ [sd_receivingdata_state] = "receivingdata",
38
+ [sd_programming_state] = "programming",
39
+ [sd_disconnect_state] = "disconnect",
40
+ };
41
+ if (state == sd_inactive_state) {
42
+ return "inactive";
43
+ }
44
+ assert(state <= ARRAY_SIZE(state_name));
45
+ return state_name[state];
46
+}
45
+}
47
+
46
+
48
static uint8_t sd_get_dat_lines(SDState *sd)
47
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
49
{
48
{
50
return sd->enable ? sd->dat_lines : 0;
49
return -ENOENT;
51
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
50
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
52
uint32_t rca = 0x0000;
51
index XXXXXXX..XXXXXXX 100644
53
uint64_t addr = (sd->ocr & (1 << 30)) ? (uint64_t) req.arg << 9 : req.arg;
52
--- a/target/arm/cpu.c
54
53
+++ b/target/arm/cpu.c
55
+ trace_sdcard_normal_command(req.cmd, req.arg, sd_state_name(sd->state));
54
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el3_property =
55
static Property arm_cpu_cfgend_property =
56
DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
57
58
-/* use property name "pmu" to match other archs and virt tools */
59
-static Property arm_cpu_has_pmu_property =
60
- DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
61
-
62
static Property arm_cpu_has_vfp_property =
63
DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
64
65
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
66
pmsav7_dregion,
67
qdev_prop_uint32, uint32_t);
68
69
+static bool arm_get_pmu(Object *obj, Error **errp)
70
+{
71
+ ARMCPU *cpu = ARM_CPU(obj);
56
+
72
+
57
/* Not interpreting this as an app command */
73
+ return cpu->has_pmu;
58
sd->card_status &= ~APP_CMD;
74
+}
59
75
+
60
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
76
+static void arm_set_pmu(Object *obj, bool value, Error **errp)
61
sd->multi_blk_cnt = 0;
77
+{
78
+ ARMCPU *cpu = ARM_CPU(obj);
79
+
80
+ if (value) {
81
+ if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
82
+ error_setg(errp, "'pmu' feature not supported by KVM on this host");
83
+ return;
84
+ }
85
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
86
+ } else {
87
+ unset_feature(&cpu->env, ARM_FEATURE_PMU);
88
+ }
89
+ cpu->has_pmu = value;
90
+}
91
+
92
static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
93
void *opaque, Error **errp)
94
{
95
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
62
}
96
}
63
97
64
- DPRINTF("CMD%d 0x%08x state %d\n", req.cmd, req.arg, sd->state);
98
if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
65
switch (req.cmd) {
99
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
66
/* Basic commands (Class 0 and Class 1) */
100
+ cpu->has_pmu = true;
67
case 0:    /* CMD0: GO_IDLE_STATE */
101
+ object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
68
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
102
&error_abort);
69
return sd_r1;
103
}
70
104
71
case 56:    /* CMD56: GEN_CMD */
105
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
72
- fprintf(stderr, "SD: GEN_CMD 0x%08x\n", req.arg);
106
index XXXXXXX..XXXXXXX 100644
73
-
107
--- a/target/arm/kvm.c
74
switch (sd->state) {
108
+++ b/target/arm/kvm.c
75
case sd_transfer_state:
109
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
76
sd->data_offset = 0;
110
env->features = arm_host_cpu_features.features;
77
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
111
}
78
static sd_rsp_type_t sd_app_command(SDState *sd,
112
79
SDRequest req)
113
+bool kvm_arm_pmu_supported(CPUState *cpu)
114
+{
115
+ KVMState *s = KVM_STATE(current_machine->accelerator);
116
+
117
+ return kvm_check_extension(s, KVM_CAP_ARM_PMU_V3);
118
+}
119
+
120
int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
80
{
121
{
81
- DPRINTF("ACMD%d 0x%08x\n", req.cmd, req.arg);
122
KVMState *s = KVM_STATE(ms->accelerator);
82
+ trace_sdcard_app_command(req.cmd, req.arg);
83
sd->card_status |= APP_CMD;
84
switch (req.cmd) {
85
case 6:    /* ACMD6: SET_BUS_WIDTH */
86
@@ -XXX,XX +XXX,XX @@ send_response:
87
88
static void sd_blk_read(SDState *sd, uint64_t addr, uint32_t len)
89
{
90
- DPRINTF("sd_blk_read: addr = 0x%08llx, len = %d\n",
91
- (unsigned long long) addr, len);
92
+ trace_sdcard_read_block(addr, len);
93
if (!sd->blk || blk_pread(sd->blk, addr, sd->data, len) < 0) {
94
fprintf(stderr, "sd_blk_read: read error on host side\n");
95
}
96
@@ -XXX,XX +XXX,XX @@ static void sd_blk_read(SDState *sd, uint64_t addr, uint32_t len)
97
98
static void sd_blk_write(SDState *sd, uint64_t addr, uint32_t len)
99
{
100
+ trace_sdcard_write_block(addr, len);
101
if (!sd->blk || blk_pwrite(sd->blk, addr, sd->data, len, 0) < 0) {
102
fprintf(stderr, "sd_blk_write: write error on host side\n");
103
}
104
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/sd/trace-events
107
+++ b/hw/sd/trace-events
108
@@ -XXX,XX +XXX,XX @@ sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been read fr
109
sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u bytes of data"
110
sdhci_capareg(const char *desc, uint16_t val) "%s: %u"
111
112
+# hw/sd/sd.c
113
+sdcard_normal_command(uint8_t cmd, uint32_t arg, const char *state) "CMD%d arg 0x%08x (state %s)"
114
+sdcard_app_command(uint8_t acmd, uint32_t arg) "ACMD%d arg 0x%08x"
115
+sdcard_read_block(uint64_t addr, uint32_t len) "addr 0x%" PRIx64 " size 0x%x"
116
+sdcard_write_block(uint64_t addr, uint32_t len) "addr 0x%" PRIx64 " size 0x%x"
117
+
118
# hw/sd/milkymist-memcard.c
119
milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
120
milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
121
--
123
--
122
2.16.1
124
2.20.1
123
125
124
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/32] target/arm: Fix register definitions for VMIDR and VMPIDR
[Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption
1
The register definitions for VMIDR and VMPIDR have separate
1
From: Andrew Jones <drjones@redhat.com>
2
reginfo structs for the AArch32 and AArch64 registers. However
3
the 32-bit versions are wrong:
4
* they use offsetof instead of offsetoflow32 to mark where
5
the 32-bit value lives in the uint64_t CPU state field
6
* they don't mark themselves as ARM_CP_ALIAS
7
2
8
In particular this means that if you try to use an Arm guest CPU
3
The current implementation of ZCR_ELx matches the architecture, only
9
which enables EL2 on a big-endian host it will assert at reset:
4
implementing the lower four bits, with the rest RAZ/WI. This puts
10
target/arm/cpu.c:114: cp_reg_check_reset: Assertion `oldvalue == newvalue' failed.
5
a strict limit on ARM_MAX_VQ of 16. Make sure we don't let ARM_MAX_VQ
6
grow without a corresponding update here.
11
7
12
because the reset of the 32-bit register writes to the top
8
Suggested-by: Dave Martin <Dave.Martin@arm.com>
13
half of the uint64_t.
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
14
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Correct the errors in the structures.
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
---
13
---
20
This is necessary for 'make check' to pass on big endian
14
target/arm/helper.c | 1 +
21
systems with the 'raspi3' board enabled, which is the
15
1 file changed, 1 insertion(+)
22
first board which has an EL2-enabled-by-default CPU.
23
---
24
target/arm/helper.c | 8 ++++----
25
1 file changed, 4 insertions(+), 4 deletions(-)
26
16
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
19
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
20
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
21
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
32
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
22
int new_len;
33
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
23
34
.access = PL2_RW, .accessfn = access_el3_aa32ns,
24
/* Bits other than [3:0] are RAZ/WI. */
35
- .resetvalue = cpu->midr,
25
+ QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
36
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
26
raw_write(env, ri, value & 0xf);
37
+ .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
27
38
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
28
/*
39
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
40
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
41
.access = PL2_RW, .resetvalue = cpu->midr,
42
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
43
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
44
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
45
.access = PL2_RW, .accessfn = access_el3_aa32ns,
46
- .resetvalue = vmpidr_def,
47
- .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
48
+ .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
49
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
50
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
51
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
52
.access = PL2_RW,
53
--
29
--
54
2.16.1
30
2.20.1
55
31
56
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/32] sdcard: fix the 'maximum data transfer rate' to 25MHz
[Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
To comply with Spec v1.10 (and 2.00, 3.01):
3
Unless we're guaranteed to always increase ARM_MAX_VQ by a multiple of
4
four, then we should use DIV_ROUND_UP to ensure we get an appropriate
5
array size.
4
6
5
. TRAN_SPEED
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
6
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
for current SD Memory Cards that field must be always 0_0110_010b (032h) which is
8
equal to 25MHz - the mandatory maximum operating frequency of SD Memory Card.
9
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
12
Message-id: 20180215221325.7611-4-f4bug@amsat.org
13
[PMM: fixed comment indent]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
hw/sd/sd.c | 2 +-
11
target/arm/cpu.h | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
18
13
19
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/sd/sd.c
16
--- a/target/arm/cpu.h
22
+++ b/hw/sd/sd.c
17
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ static void sd_set_csd(SDState *sd, uint64_t size)
18
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVectorReg {
24
sd->csd[0] = 0x00;    /* CSD structure */
19
#ifdef TARGET_AARCH64
25
sd->csd[1] = 0x26;    /* Data read access-time-1 */
20
/* In AArch32 mode, predicate registers do not exist at all. */
26
sd->csd[2] = 0x00;    /* Data read access-time-2 */
21
typedef struct ARMPredicateReg {
27
- sd->csd[3] = 0x5a;    /* Max. data transfer rate */
22
- uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
28
+ sd->csd[3] = 0x32; /* Max. data transfer rate: 25 MHz */
23
+ uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
29
sd->csd[4] = 0x5f;    /* Card Command Classes */
24
} ARMPredicateReg;
30
sd->csd[5] = 0x50 |    /* Max. read data block length */
25
31
HWBLOCK_SHIFT;
26
/* In AArch32 mode, PAC keys do not exist at all. */
32
--
27
--
33
2.16.1
28
2.20.1
34
29
35
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/32] sdcard: handles more commands in SPI mode
[Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
A couple return -EINVAL's forgot their '-'s.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180215221325.7611-13-f4bug@amsat.org
5
Signed-off-by: Andrew Jones <drjones@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
9
---
8
hw/sd/sd.c | 29 ++++++++++++++++++++++++++---
10
target/arm/kvm64.c | 4 ++--
9
1 file changed, 26 insertions(+), 3 deletions(-)
11
1 file changed, 2 insertions(+), 2 deletions(-)
10
12
11
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
13
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sd.c
15
--- a/target/arm/kvm64.c
14
+++ b/hw/sd/sd.c
16
+++ b/target/arm/kvm64.c
15
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
17
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
16
18
write_cpustate_to_list(cpu, true);
17
/* Application specific commands (Class 8) */
19
18
case 55:    /* CMD55: APP_CMD */
20
if (!write_list_to_kvmstate(cpu, level)) {
19
- if (sd->rca != rca)
21
- return EINVAL;
20
- return sd_r0;
22
+ return -EINVAL;
21
-
22
+ if (!sd->spi) {
23
+ if (sd->rca != rca) {
24
+ return sd_r0;
25
+ }
26
+ }
27
sd->expecting_acmd = true;
28
sd->card_status |= APP_CMD;
29
return sd_r1;
30
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
31
}
32
break;
33
34
+ case 58: /* CMD58: READ_OCR (SPI) */
35
+ if (!sd->spi) {
36
+ goto bad_cmd;
37
+ }
38
+ return sd_r3;
39
+
40
+ case 59: /* CMD59: CRC_ON_OFF (SPI) */
41
+ if (!sd->spi) {
42
+ goto bad_cmd;
43
+ }
44
+ goto unimplemented_spi_cmd;
45
+
46
default:
47
bad_cmd:
48
qemu_log_mask(LOG_GUEST_ERROR, "SD: Unknown CMD%i\n", req.cmd);
49
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_app_command(SDState *sd,
50
sd->card_status |= APP_CMD;
51
switch (req.cmd) {
52
case 6:    /* ACMD6: SET_BUS_WIDTH */
53
+ if (sd->spi) {
54
+ goto unimplemented_spi_cmd;
55
+ }
56
switch (sd->state) {
57
case sd_transfer_state:
58
sd->sd_status[0] &= 0x3f;
59
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_app_command(SDState *sd,
60
default:
61
/* Fall back to standard commands. */
62
return sd_normal_command(sd, req);
63
+
64
+ unimplemented_spi_cmd:
65
+ /* Commands that are recognised but not yet implemented in SPI mode. */
66
+ qemu_log_mask(LOG_UNIMP, "SD: CMD%i not implemented in SPI mode\n",
67
+ req.cmd);
68
+ return sd_illegal;
69
}
23
}
70
24
71
qemu_log_mask(LOG_GUEST_ERROR, "SD: ACMD%i in a wrong state\n", req.cmd);
25
kvm_arm_sync_mpstate_to_kvm(cpu);
26
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
27
}
28
29
if (!write_kvmstate_to_list(cpu)) {
30
- return EINVAL;
31
+ return -EINVAL;
32
}
33
/* Note that it's OK to have registers which aren't in CPUState,
34
* so we can ignore a failure return here.
72
--
35
--
73
2.16.1
36
2.20.1
74
37
75
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/32] raspi: Add "raspi3" machine type
[Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out
1
From: Pekka Enberg <penberg@iki.fi>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
This patch adds a "raspi3" machine type, which can now be selected as
3
Move the getting/putting of the fpsimd registers out of
4
the machine to run on by users via the "-M" command line option to QEMU.
4
kvm_arch_get/put_registers() into their own helper functions
5
5
to prepare for alternatively getting/putting SVE registers.
6
The machine type does *not* ignore memory transaction failures so we
6
7
likely need to add some dummy devices later when people run something
7
No functional change.
8
more complicated than what I'm using for testing.
8
9
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
10
Signed-off-by: Pekka Enberg <penberg@iki.fi>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
[PMM: added #ifdef TARGET_AARCH64 so we don't provide the 64-bit
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
board in the 32-bit only arm-softmmu build.]
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
hw/arm/raspi.c | 23 +++++++++++++++++++++++
14
target/arm/kvm64.c | 148 +++++++++++++++++++++++++++------------------
18
1 file changed, 23 insertions(+)
15
1 file changed, 88 insertions(+), 60 deletions(-)
19
16
20
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/raspi.c
19
--- a/target/arm/kvm64.c
23
+++ b/hw/arm/raspi.c
20
+++ b/target/arm/kvm64.c
24
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
21
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
25
mc->ignore_memory_transaction_failures = true;
22
#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
26
};
23
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
27
DEFINE_MACHINE("raspi2", raspi2_machine_init)
24
28
+
25
+static int kvm_arch_put_fpsimd(CPUState *cs)
29
+#ifdef TARGET_AARCH64
30
+static void raspi3_init(MachineState *machine)
31
+{
26
+{
32
+ raspi_init(machine, 3);
27
+ ARMCPU *cpu = ARM_CPU(cs);
28
+ CPUARMState *env = &cpu->env;
29
+ struct kvm_one_reg reg;
30
+ uint32_t fpr;
31
+ int i, ret;
32
+
33
+ for (i = 0; i < 32; i++) {
34
+ uint64_t *q = aa64_vfp_qreg(env, i);
35
+#ifdef HOST_WORDS_BIGENDIAN
36
+ uint64_t fp_val[2] = { q[1], q[0] };
37
+ reg.addr = (uintptr_t)fp_val;
38
+#else
39
+ reg.addr = (uintptr_t)q;
40
+#endif
41
+ reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
42
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
43
+ if (ret) {
44
+ return ret;
45
+ }
46
+ }
47
+
48
+ reg.addr = (uintptr_t)(&fpr);
49
+ fpr = vfp_get_fpsr(env);
50
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
51
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
52
+ if (ret) {
53
+ return ret;
54
+ }
55
+
56
+ reg.addr = (uintptr_t)(&fpr);
57
+ fpr = vfp_get_fpcr(env);
58
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
59
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
60
+ if (ret) {
61
+ return ret;
62
+ }
63
+
64
+ return 0;
33
+}
65
+}
34
+
66
+
35
+static void raspi3_machine_init(MachineClass *mc)
67
int kvm_arch_put_registers(CPUState *cs, int level)
68
{
69
struct kvm_one_reg reg;
70
- uint32_t fpr;
71
uint64_t val;
72
- int i;
73
- int ret;
74
+ int i, ret;
75
unsigned int el;
76
77
ARMCPU *cpu = ARM_CPU(cs);
78
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
79
}
80
}
81
82
- /* Advanced SIMD and FP registers. */
83
- for (i = 0; i < 32; i++) {
84
- uint64_t *q = aa64_vfp_qreg(env, i);
85
-#ifdef HOST_WORDS_BIGENDIAN
86
- uint64_t fp_val[2] = { q[1], q[0] };
87
- reg.addr = (uintptr_t)fp_val;
88
-#else
89
- reg.addr = (uintptr_t)q;
90
-#endif
91
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
92
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
93
- if (ret) {
94
- return ret;
95
- }
96
- }
97
-
98
- reg.addr = (uintptr_t)(&fpr);
99
- fpr = vfp_get_fpsr(env);
100
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
101
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
102
- if (ret) {
103
- return ret;
104
- }
105
-
106
- fpr = vfp_get_fpcr(env);
107
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
108
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
109
+ ret = kvm_arch_put_fpsimd(cs);
110
if (ret) {
111
return ret;
112
}
113
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
114
return ret;
115
}
116
117
+static int kvm_arch_get_fpsimd(CPUState *cs)
36
+{
118
+{
37
+ mc->desc = "Raspberry Pi 3";
119
+ ARMCPU *cpu = ARM_CPU(cs);
38
+ mc->init = raspi3_init;
120
+ CPUARMState *env = &cpu->env;
39
+ mc->block_default_type = IF_SD;
121
+ struct kvm_one_reg reg;
40
+ mc->no_parallel = 1;
122
+ uint32_t fpr;
41
+ mc->no_floppy = 1;
123
+ int i, ret;
42
+ mc->no_cdrom = 1;
124
+
43
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
125
+ for (i = 0; i < 32; i++) {
44
+ mc->max_cpus = BCM2836_NCPUS;
126
+ uint64_t *q = aa64_vfp_qreg(env, i);
45
+ mc->min_cpus = BCM2836_NCPUS;
127
+ reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
46
+ mc->default_cpus = BCM2836_NCPUS;
128
+ reg.addr = (uintptr_t)q;
47
+ mc->default_ram_size = 1024 * 1024 * 1024;
129
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
130
+ if (ret) {
131
+ return ret;
132
+ } else {
133
+#ifdef HOST_WORDS_BIGENDIAN
134
+ uint64_t t;
135
+ t = q[0], q[0] = q[1], q[1] = t;
136
+#endif
137
+ }
138
+ }
139
+
140
+ reg.addr = (uintptr_t)(&fpr);
141
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
142
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
143
+ if (ret) {
144
+ return ret;
145
+ }
146
+ vfp_set_fpsr(env, fpr);
147
+
148
+ reg.addr = (uintptr_t)(&fpr);
149
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
150
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
151
+ if (ret) {
152
+ return ret;
153
+ }
154
+ vfp_set_fpcr(env, fpr);
155
+
156
+ return 0;
48
+}
157
+}
49
+DEFINE_MACHINE("raspi3", raspi3_machine_init)
158
+
50
+#endif
159
int kvm_arch_get_registers(CPUState *cs)
160
{
161
struct kvm_one_reg reg;
162
uint64_t val;
163
- uint32_t fpr;
164
unsigned int el;
165
- int i;
166
- int ret;
167
+ int i, ret;
168
169
ARMCPU *cpu = ARM_CPU(cs);
170
CPUARMState *env = &cpu->env;
171
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
172
env->spsr = env->banked_spsr[i];
173
}
174
175
- /* Advanced SIMD and FP registers */
176
- for (i = 0; i < 32; i++) {
177
- uint64_t *q = aa64_vfp_qreg(env, i);
178
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
179
- reg.addr = (uintptr_t)q;
180
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
181
- if (ret) {
182
- return ret;
183
- } else {
184
-#ifdef HOST_WORDS_BIGENDIAN
185
- uint64_t t;
186
- t = q[0], q[0] = q[1], q[1] = t;
187
-#endif
188
- }
189
- }
190
-
191
- reg.addr = (uintptr_t)(&fpr);
192
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
193
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
194
+ ret = kvm_arch_get_fpsimd(cs);
195
if (ret) {
196
return ret;
197
}
198
- vfp_set_fpsr(env, fpr);
199
-
200
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
201
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
202
- if (ret) {
203
- return ret;
204
- }
205
- vfp_set_fpcr(env, fpr);
206
207
ret = kvm_get_vcpu_events(cpu);
208
if (ret) {
51
--
209
--
52
2.16.1
210
2.20.1
53
211
54
212
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/32] hw/char/stm32f2xx_usart: fix TXE/TC bit handling
Deleted patch
1
From: Richard Braun <rbraun@sceen.net>
2
1
3
I/O currently being synchronous, there is no reason to ever clear the
4
SR_TXE bit. However the SR_TC bit may be cleared by software writing
5
to the SR register, so set it on each write.
6
7
In addition, fix the reset value of the USART status register.
8
9
Signed-off-by: Richard Braun <rbraun@sceen.net>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
[PMM: removed XXX tag from comment, since it isn't something
12
we need to come back and fix in QEMU]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/char/stm32f2xx_usart.h | 7 ++++++-
16
hw/char/stm32f2xx_usart.c | 12 ++++++++----
17
2 files changed, 14 insertions(+), 5 deletions(-)
18
19
diff --git a/include/hw/char/stm32f2xx_usart.h b/include/hw/char/stm32f2xx_usart.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/char/stm32f2xx_usart.h
22
+++ b/include/hw/char/stm32f2xx_usart.h
23
@@ -XXX,XX +XXX,XX @@
24
#define USART_CR3 0x14
25
#define USART_GTPR 0x18
26
27
-#define USART_SR_RESET 0x00C00000
28
+/*
29
+ * NB: The reset value mentioned in "24.6.1 Status register" seems bogus.
30
+ * Looking at "Table 98 USART register map and reset values", it seems it
31
+ * should be 0xc0, and that's how real hardware behaves.
32
+ */
33
+#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC)
34
35
#define USART_SR_TXE (1 << 7)
36
#define USART_SR_TC (1 << 6)
37
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/char/stm32f2xx_usart.c
40
+++ b/hw/char/stm32f2xx_usart.c
41
@@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
42
switch (addr) {
43
case USART_SR:
44
retvalue = s->usart_sr;
45
- s->usart_sr &= ~USART_SR_TC;
46
qemu_chr_fe_accept_input(&s->chr);
47
return retvalue;
48
case USART_DR:
49
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
50
- s->usart_sr |= USART_SR_TXE;
51
s->usart_sr &= ~USART_SR_RXNE;
52
qemu_chr_fe_accept_input(&s->chr);
53
qemu_set_irq(s->irq, 0);
54
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
55
switch (addr) {
56
case USART_SR:
57
if (value <= 0x3FF) {
58
- s->usart_sr = value;
59
+ /* I/O being synchronous, TXE is always set. In addition, it may
60
+ only be set by hardware, so keep it set here. */
61
+ s->usart_sr = value | USART_SR_TXE;
62
} else {
63
s->usart_sr &= value;
64
}
65
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
66
/* XXX this blocks entire thread. Rewrite to use
67
* qemu_chr_fe_write and background I/O callbacks */
68
qemu_chr_fe_write_all(&s->chr, &ch, 1);
69
+ /* XXX I/O are currently synchronous, making it impossible for
70
+ software to observe transient states where TXE or TC aren't
71
+ set. Unlike TXE however, which is read-only, software may
72
+ clear TC by writing 0 to the SR register, so set it again
73
+ on each write. */
74
s->usart_sr |= USART_SR_TC;
75
- s->usart_sr &= ~USART_SR_TXE;
76
}
77
return;
78
case USART_BRR:
79
--
80
2.16.1
81
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/32] sdcard: reorder SDState struct members
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
place card registers first, this will ease further code movements.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20180215220540.6556-2-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/sd/sd.c | 16 +++++++++-------
11
1 file changed, 9 insertions(+), 7 deletions(-)
12
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
16
+++ b/hw/sd/sd.c
17
@@ -XXX,XX +XXX,XX @@ enum SDCardStates {
18
struct SDState {
19
DeviceState parent_obj;
20
21
- uint32_t mode; /* current card mode, one of SDCardModes */
22
- int32_t state; /* current card state, one of SDCardStates */
23
+ /* SD Memory Card Registers */
24
uint32_t ocr;
25
- QEMUTimer *ocr_power_timer;
26
uint8_t scr[8];
27
uint8_t cid[16];
28
uint8_t csd[16];
29
uint16_t rca;
30
uint32_t card_status;
31
uint8_t sd_status[64];
32
+
33
+ /* Configurable properties */
34
+ BlockBackend *blk;
35
+ bool spi;
36
+
37
+ uint32_t mode; /* current card mode, one of SDCardModes */
38
+ int32_t state; /* current card state, one of SDCardStates */
39
uint32_t vhs;
40
bool wp_switch;
41
unsigned long *wp_groups;
42
@@ -XXX,XX +XXX,XX @@ struct SDState {
43
uint8_t pwd[16];
44
uint32_t pwd_len;
45
uint8_t function_group[6];
46
-
47
- bool spi;
48
uint8_t current_cmd;
49
/* True if we will handle the next command as an ACMD. Note that this does
50
* *not* track the APP_CMD status bit!
51
@@ -XXX,XX +XXX,XX @@ struct SDState {
52
uint8_t data[512];
53
qemu_irq readonly_cb;
54
qemu_irq inserted_cb;
55
- BlockBackend *blk;
56
-
57
+ QEMUTimer *ocr_power_timer;
58
bool enable;
59
uint8_t dat_lines;
60
bool cmd_line;
61
--
62
2.16.1
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/32] sdcard: use the registerfields API for the CARD_STATUS register masks
[Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Extract is a compact combination of shift + and.
4
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180215221325.7611-9-f4bug@amsat.org
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20190808202616.13782-2-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
---
9
hw/sd/sd.c | 48 +++++++++++++++++++++++++++++++++++++++++++++---
10
target/arm/translate.c | 9 +--------
10
1 file changed, 45 insertions(+), 3 deletions(-)
11
1 file changed, 1 insertion(+), 8 deletions(-)
11
12
12
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sd.c
15
--- a/target/arm/translate.c
15
+++ b/hw/sd/sd.c
16
+++ b/target/arm/translate.c
16
@@ -XXX,XX +XXX,XX @@ static void sd_set_rca(SDState *sd)
17
@@ -XXX,XX +XXX,XX @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
17
sd->rca += 0x4567;
18
19
static void shifter_out_im(TCGv_i32 var, int shift)
20
{
21
- if (shift == 0) {
22
- tcg_gen_andi_i32(cpu_CF, var, 1);
23
- } else {
24
- tcg_gen_shri_i32(cpu_CF, var, shift);
25
- if (shift != 31) {
26
- tcg_gen_andi_i32(cpu_CF, cpu_CF, 1);
27
- }
28
- }
29
+ tcg_gen_extract_i32(cpu_CF, var, shift, 1);
18
}
30
}
19
31
20
+FIELD(CSR, AKE_SEQ_ERROR, 3, 1)
32
/* Shift by immediate. Includes special handling for shift == 0. */
21
+FIELD(CSR, APP_CMD, 5, 1)
22
+FIELD(CSR, FX_EVENT, 6, 1)
23
+FIELD(CSR, READY_FOR_DATA, 8, 1)
24
+FIELD(CSR, CURRENT_STATE, 9, 4)
25
+FIELD(CSR, ERASE_RESET, 13, 1)
26
+FIELD(CSR, CARD_ECC_DISABLED, 14, 1)
27
+FIELD(CSR, WP_ERASE_SKIP, 15, 1)
28
+FIELD(CSR, CSD_OVERWRITE, 16, 1)
29
+FIELD(CSR, DEFERRED_RESPONSE, 17, 1)
30
+FIELD(CSR, ERROR, 19, 1)
31
+FIELD(CSR, CC_ERROR, 20, 1)
32
+FIELD(CSR, CARD_ECC_FAILED, 21, 1)
33
+FIELD(CSR, ILLEGAL_COMMAND, 22, 1)
34
+FIELD(CSR, COM_CRC_ERROR, 23, 1)
35
+FIELD(CSR, LOCK_UNLOCK_FAILED, 24, 1)
36
+FIELD(CSR, CARD_IS_LOCKED, 25, 1)
37
+FIELD(CSR, WP_VIOLATION, 26, 1)
38
+FIELD(CSR, ERASE_PARAM, 27, 1)
39
+FIELD(CSR, ERASE_SEQ_ERROR, 28, 1)
40
+FIELD(CSR, BLOCK_LEN_ERROR, 29, 1)
41
+FIELD(CSR, ADDRESS_ERROR, 30, 1)
42
+FIELD(CSR, OUT_OF_RANGE, 31, 1)
43
+
44
/* Card status bits, split by clear condition:
45
* A : According to the card current state
46
* B : Always related to the previous command
47
* C : Cleared by read
48
*/
49
-#define CARD_STATUS_A    0x02004100
50
-#define CARD_STATUS_B    0x00c01e00
51
-#define CARD_STATUS_C    0xfd39a028
52
+#define CARD_STATUS_A (R_CSR_READY_FOR_DATA_MASK \
53
+ | R_CSR_CARD_ECC_DISABLED_MASK \
54
+ | R_CSR_CARD_IS_LOCKED_MASK)
55
+#define CARD_STATUS_B (R_CSR_CURRENT_STATE_MASK \
56
+ | R_CSR_ILLEGAL_COMMAND_MASK \
57
+ | R_CSR_COM_CRC_ERROR_MASK)
58
+#define CARD_STATUS_C (R_CSR_AKE_SEQ_ERROR_MASK \
59
+ | R_CSR_APP_CMD_MASK \
60
+ | R_CSR_ERASE_RESET_MASK \
61
+ | R_CSR_WP_ERASE_SKIP_MASK \
62
+ | R_CSR_CSD_OVERWRITE_MASK \
63
+ | R_CSR_ERROR_MASK \
64
+ | R_CSR_CC_ERROR_MASK \
65
+ | R_CSR_CARD_ECC_FAILED_MASK \
66
+ | R_CSR_LOCK_UNLOCK_FAILED_MASK \
67
+ | R_CSR_WP_VIOLATION_MASK \
68
+ | R_CSR_ERASE_PARAM_MASK \
69
+ | R_CSR_ERASE_SEQ_ERROR_MASK \
70
+ | R_CSR_BLOCK_LEN_ERROR_MASK \
71
+ | R_CSR_ADDRESS_ERROR_MASK \
72
+ | R_CSR_OUT_OF_RANGE_MASK)
73
74
static void sd_set_cardstatus(SDState *sd)
75
{
76
--
33
--
77
2.16.1
34
2.20.1
78
35
79
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/32] sdcard: handle CMD54 (SDIO)
[Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Linux uses it to poll the bus before polling for a card.
3
Use deposit as the composit operation to merge the
4
bits from the two inputs.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20190808202616.13782-3-richard.henderson@linaro.org
7
Message-id: 20180215221325.7611-10-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
hw/sd/sd.c | 5 ++---
11
target/arm/translate.c | 26 ++++++++++----------------
11
1 file changed, 2 insertions(+), 3 deletions(-)
12
1 file changed, 10 insertions(+), 16 deletions(-)
12
13
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
16
--- a/target/arm/translate.c
16
+++ b/hw/sd/sd.c
17
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
18
}
19
shift = (insn >> 7) & 0x1f;
19
break;
20
if (insn & (1 << 6)) {
20
21
/* pkhtb */
21
- case 52:
22
- if (shift == 0)
22
- case 53:
23
+ if (shift == 0) {
23
- /* CMD52, CMD53: reserved for SDIO cards
24
shift = 31;
24
+ case 52 ... 54:
25
+ }
25
+ /* CMD52, CMD53, CMD54: reserved for SDIO cards
26
tcg_gen_sari_i32(tmp2, tmp2, shift);
26
* (see the SDIO Simplified Specification V2.0)
27
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
27
* Handle as illegal command but do not complain
28
- tcg_gen_ext16u_i32(tmp2, tmp2);
28
* on stderr, as some OSes may use these in their
29
+ tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16);
30
} else {
31
/* pkhbt */
32
- if (shift)
33
- tcg_gen_shli_i32(tmp2, tmp2, shift);
34
- tcg_gen_ext16u_i32(tmp, tmp);
35
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
36
+ tcg_gen_shli_i32(tmp2, tmp2, shift);
37
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16);
38
}
39
- tcg_gen_or_i32(tmp, tmp, tmp2);
40
tcg_temp_free_i32(tmp2);
41
store_reg(s, rd, tmp);
42
} else if ((insn & 0x00200020) == 0x00200000) {
43
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
44
shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
45
if (insn & (1 << 5)) {
46
/* pkhtb */
47
- if (shift == 0)
48
+ if (shift == 0) {
49
shift = 31;
50
+ }
51
tcg_gen_sari_i32(tmp2, tmp2, shift);
52
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
53
- tcg_gen_ext16u_i32(tmp2, tmp2);
54
+ tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16);
55
} else {
56
/* pkhbt */
57
- if (shift)
58
- tcg_gen_shli_i32(tmp2, tmp2, shift);
59
- tcg_gen_ext16u_i32(tmp, tmp);
60
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
61
+ tcg_gen_shli_i32(tmp2, tmp2, shift);
62
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16);
63
}
64
- tcg_gen_or_i32(tmp, tmp, tmp2);
65
tcg_temp_free_i32(tmp2);
66
store_reg(s, rd, tmp);
67
} else {
29
--
68
--
30
2.16.1
69
2.20.1
31
70
32
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/32] sdcard: clean the SCR register and add few comments
[Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The immediate shift generator functions already test for,
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
and eliminate, the case of a shift by zero.
5
Message-id: 20180215221325.7611-5-f4bug@amsat.org
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/sd/sd.c | 9 ++++++---
11
target/arm/translate.c | 19 +++++++------------
9
1 file changed, 6 insertions(+), 3 deletions(-)
12
1 file changed, 7 insertions(+), 12 deletions(-)
10
13
11
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sd.c
16
--- a/target/arm/translate.c
14
+++ b/hw/sd/sd.c
17
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
16
19
shift = (insn >> 10) & 3;
17
static void sd_set_scr(SDState *sd)
20
/* ??? In many cases it's not necessary to do a
18
{
21
rotate, a shift is sufficient. */
19
- sd->scr[0] = 0x00;        /* SCR Structure */
22
- if (shift != 0)
20
- sd->scr[1] = 0x2f;        /* SD Security Support */
23
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
21
- sd->scr[2] = 0x00;
24
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
22
+ sd->scr[0] = (0 << 4) /* SCR version 1.0 */
25
op1 = (insn >> 20) & 7;
23
+ | 0; /* Spec Versions 1.0 and 1.01 */
26
switch (op1) {
24
+ sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
27
case 0: gen_sxtb16(tmp); break;
25
+ | 0b0101; /* 1-bit or 4-bit width bus modes */
28
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
26
+ sd->scr[2] = 0x00; /* Extended Security is not supported. */
29
shift = (insn >> 4) & 3;
27
sd->scr[3] = 0x00;
30
/* ??? In many cases it's not necessary to do a
28
+ /* reserved for manufacturer usage */
31
rotate, a shift is sufficient. */
29
sd->scr[4] = 0x00;
32
- if (shift != 0)
30
sd->scr[5] = 0x00;
33
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
31
sd->scr[6] = 0x00;
34
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
35
op = (insn >> 20) & 7;
36
switch (op) {
37
case 0: gen_sxth(tmp); break;
38
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
39
case 7:
40
goto illegal_op;
41
default: /* Saturate. */
42
- if (shift) {
43
- if (op & 1)
44
- tcg_gen_sari_i32(tmp, tmp, shift);
45
- else
46
- tcg_gen_shli_i32(tmp, tmp, shift);
47
+ if (op & 1) {
48
+ tcg_gen_sari_i32(tmp, tmp, shift);
49
+ } else {
50
+ tcg_gen_shli_i32(tmp, tmp, shift);
51
}
52
tmp2 = tcg_const_i32(imm);
53
if (op & 4) {
54
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
55
goto illegal_op;
56
}
57
tmp = load_reg(s, rm);
58
- if (shift) {
59
- tcg_gen_shli_i32(tmp, tmp, shift);
60
- }
61
+ tcg_gen_shli_i32(tmp, tmp, shift);
62
tcg_gen_add_i32(addr, addr, tmp);
63
tcg_temp_free_i32(tmp);
64
break;
32
--
65
--
33
2.16.1
66
2.20.1
34
67
35
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/32] sdcard: add more trace events
[Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The helper function is more documentary, and also already
4
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
4
handles the case of rotate by zero.
5
Message-id: 20180215220540.6556-6-f4bug@amsat.org
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190808202616.13782-5-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
hw/sd/sd.c | 32 ++++++++++++++++++++++++++------
11
target/arm/translate.c | 7 ++-----
10
hw/sd/trace-events | 13 +++++++++++++
12
1 file changed, 2 insertions(+), 5 deletions(-)
11
2 files changed, 39 insertions(+), 6 deletions(-)
12
13
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
16
--- a/target/arm/translate.c
16
+++ b/hw/sd/sd.c
17
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static bool sd_get_cmd_line(SDState *sd)
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
18
19
/* CPSR = immediate */
19
static void sd_set_voltage(SDState *sd, uint16_t millivolts)
20
val = insn & 0xff;
20
{
21
shift = ((insn >> 8) & 0xf) * 2;
21
+ trace_sdcard_set_voltage(millivolts);
22
- if (shift)
22
+
23
- val = (val >> shift) | (val << (32 - shift));
23
switch (millivolts) {
24
+ val = ror32(val, shift);
24
case 3001 ... 3600: /* SD_VOLTAGE_3_3V */
25
i = ((insn & (1 << 22)) != 0);
25
case 2001 ... 3000: /* SD_VOLTAGE_3_0V */
26
if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
26
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
27
i, val)) {
27
{
28
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
28
SDState *sd = opaque;
29
/* immediate operand */
29
30
val = insn & 0xff;
30
+ trace_sdcard_powerup();
31
shift = ((insn >> 8) & 0xf) * 2;
31
/* Set powered up bit in OCR */
32
- if (shift) {
32
assert(!(sd->ocr & OCR_POWER_UP));
33
- val = (val >> shift) | (val << (32 - shift));
33
sd->ocr |= OCR_POWER_UP;
34
- }
34
@@ -XXX,XX +XXX,XX @@ static void sd_reset(DeviceState *dev)
35
+ val = ror32(val, shift);
35
uint64_t size;
36
tmp2 = tcg_temp_new_i32();
36
uint64_t sect;
37
tcg_gen_movi_i32(tmp2, val);
37
38
if (logic_cc && shift) {
38
+ trace_sdcard_reset();
39
if (sd->blk) {
40
blk_get_geometry(sd->blk, &sect);
41
} else {
42
@@ -XXX,XX +XXX,XX @@ static void sd_cardchange(void *opaque, bool load, Error **errp)
43
bool readonly = sd_get_readonly(sd);
44
45
if (inserted) {
46
+ trace_sdcard_inserted(readonly);
47
sd_reset(dev);
48
+ } else {
49
+ trace_sdcard_ejected();
50
}
51
52
/* The IRQ notification is for legacy non-QOM SD controller devices;
53
@@ -XXX,XX +XXX,XX @@ static void sd_erase(SDState *sd)
54
uint64_t erase_start = sd->erase_start;
55
uint64_t erase_end = sd->erase_end;
56
57
+ trace_sdcard_erase();
58
if (!sd->erase_start || !sd->erase_end) {
59
sd->card_status |= ERASE_SEQ_ERROR;
60
return;
61
@@ -XXX,XX +XXX,XX @@ static void sd_lock_command(SDState *sd)
62
else
63
pwd_len = 0;
64
65
+ if (lock) {
66
+ trace_sdcard_lock();
67
+ } else {
68
+ trace_sdcard_unlock();
69
+ }
70
if (erase) {
71
if (!(sd->card_status & CARD_IS_LOCKED) || sd->blk_len > 1 ||
72
set_pwd || clr_pwd || lock || sd->wp_switch ||
73
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
74
case 16:    /* CMD16: SET_BLOCKLEN */
75
switch (sd->state) {
76
case sd_transfer_state:
77
- if (req.arg > (1 << HWBLOCK_SHIFT))
78
+ if (req.arg > (1 << HWBLOCK_SHIFT)) {
79
sd->card_status |= BLOCK_LEN_ERROR;
80
- else
81
+ } else {
82
+ trace_sdcard_set_blocklen(req.arg);
83
sd->blk_len = req.arg;
84
+ }
85
86
return sd_r1;
87
88
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_app_command(SDState *sd,
89
if ((req.arg & ACMD41_ENQUIRY_MASK) != 0) {
90
timer_del(sd->ocr_power_timer);
91
sd_ocr_powerup(sd);
92
- } else if (!timer_pending(sd->ocr_power_timer)) {
93
- timer_mod_ns(sd->ocr_power_timer,
94
- (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
95
- + OCR_POWER_DELAY_NS));
96
+ } else {
97
+ trace_sdcard_inquiry_cmd41();
98
+ if (!timer_pending(sd->ocr_power_timer)) {
99
+ timer_mod_ns(sd->ocr_power_timer,
100
+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
101
+ + OCR_POWER_DELAY_NS));
102
+ }
103
}
104
}
105
106
@@ -XXX,XX +XXX,XX @@ void sd_write_data(SDState *sd, uint8_t value)
107
if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION))
108
return;
109
110
+ trace_sdcard_write_data(sd->current_cmd, value);
111
switch (sd->current_cmd) {
112
case 24:    /* CMD24: WRITE_SINGLE_BLOCK */
113
sd->data[sd->data_offset ++] = value;
114
@@ -XXX,XX +XXX,XX @@ uint8_t sd_read_data(SDState *sd)
115
116
io_len = (sd->ocr & (1 << 30)) ? 512 : sd->blk_len;
117
118
+ trace_sdcard_read_data(sd->current_cmd, io_len);
119
switch (sd->current_cmd) {
120
case 6:    /* CMD6: SWITCH_FUNCTION */
121
ret = sd->data[sd->data_offset ++];
122
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/sd/trace-events
125
+++ b/hw/sd/trace-events
126
@@ -XXX,XX +XXX,XX @@ sdhci_capareg(const char *desc, uint16_t val) "%s: %u"
127
sdcard_normal_command(uint8_t cmd, uint32_t arg, const char *state) "CMD%d arg 0x%08x (state %s)"
128
sdcard_app_command(uint8_t acmd, uint32_t arg) "ACMD%d arg 0x%08x"
129
sdcard_response(const char *rspdesc, int rsplen) "%s (sz:%d)"
130
+sdcard_powerup(void) ""
131
+sdcard_inquiry_cmd41(void) ""
132
+sdcard_set_enable(bool current_state, bool new_state) "%u -> %u"
133
+sdcard_reset(void) ""
134
+sdcard_set_blocklen(uint16_t length) "0x%04x"
135
+sdcard_inserted(bool readonly) "read_only: %u"
136
+sdcard_ejected(void) ""
137
+sdcard_erase(void) ""
138
+sdcard_lock(void) ""
139
+sdcard_unlock(void) ""
140
sdcard_read_block(uint64_t addr, uint32_t len) "addr 0x%" PRIx64 " size 0x%x"
141
sdcard_write_block(uint64_t addr, uint32_t len) "addr 0x%" PRIx64 " size 0x%x"
142
+sdcard_write_data(uint8_t cmd, uint8_t value) "CMD%02d value 0x%02x"
143
+sdcard_read_data(uint8_t cmd, int length) "CMD%02d len %d"
144
+sdcard_set_voltage(uint16_t millivolts) "%u mV"
145
146
# hw/sd/milkymist-memcard.c
147
milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
148
--
39
--
149
2.16.1
40
2.20.1
150
41
151
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/32] sdcard: simplify using the ldst API
[Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
the code is easier to review/refactor.
3
Rotate is the more compact and obvious way to swap 16-bit
4
elements of a 32-bit word.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20190808202616.13782-6-richard.henderson@linaro.org
7
Message-id: 20180215221325.7611-7-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/sd/sd.c | 38 +++++++++-----------------------------
11
target/arm/translate.c | 6 +-----
12
1 file changed, 9 insertions(+), 29 deletions(-)
12
1 file changed, 1 insertion(+), 5 deletions(-)
13
13
14
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/sd/sd.c
16
--- a/target/arm/translate.c
17
+++ b/hw/sd/sd.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static int sd_req_crc_validate(SDRequest *req)
18
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b)
19
/* Swap low and high halfwords. */
20
static void gen_swap_half(TCGv_i32 var)
19
{
21
{
20
uint8_t buffer[5];
22
- TCGv_i32 tmp = tcg_temp_new_i32();
21
buffer[0] = 0x40 | req->cmd;
23
- tcg_gen_shri_i32(tmp, var, 16);
22
- buffer[1] = (req->arg >> 24) & 0xff;
24
- tcg_gen_shli_i32(var, var, 16);
23
- buffer[2] = (req->arg >> 16) & 0xff;
25
- tcg_gen_or_i32(var, var, tmp);
24
- buffer[3] = (req->arg >> 8) & 0xff;
26
- tcg_temp_free_i32(tmp);
25
- buffer[4] = (req->arg >> 0) & 0xff;
27
+ tcg_gen_rotri_i32(var, var, 16);
26
+ stl_be_p(&buffer[1], req->arg);
27
return 0;
28
return sd_crc7(buffer, 5) != req->crc;    /* TODO */
29
}
28
}
30
29
31
static void sd_response_r1_make(SDState *sd, uint8_t *response)
30
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
32
{
33
- uint32_t status = sd->card_status;
34
+ stl_be_p(response, sd->card_status);
35
+
36
/* Clear the "clear on read" status bits */
37
sd->card_status &= ~CARD_STATUS_C;
38
-
39
- response[0] = (status >> 24) & 0xff;
40
- response[1] = (status >> 16) & 0xff;
41
- response[2] = (status >> 8) & 0xff;
42
- response[3] = (status >> 0) & 0xff;
43
}
44
45
static void sd_response_r3_make(SDState *sd, uint8_t *response)
46
{
47
- response[0] = (sd->ocr >> 24) & 0xff;
48
- response[1] = (sd->ocr >> 16) & 0xff;
49
- response[2] = (sd->ocr >> 8) & 0xff;
50
- response[3] = (sd->ocr >> 0) & 0xff;
51
+ stl_be_p(response, sd->ocr);
52
}
53
54
static void sd_response_r6_make(SDState *sd, uint8_t *response)
55
{
56
- uint16_t arg;
57
uint16_t status;
58
59
- arg = sd->rca;
60
status = ((sd->card_status >> 8) & 0xc000) |
61
((sd->card_status >> 6) & 0x2000) |
62
(sd->card_status & 0x1fff);
63
sd->card_status &= ~(CARD_STATUS_C & 0xc81fff);
64
-
65
- response[0] = (arg >> 8) & 0xff;
66
- response[1] = arg & 0xff;
67
- response[2] = (status >> 8) & 0xff;
68
- response[3] = status & 0xff;
69
+ stw_be_p(response + 0, sd->rca);
70
+ stw_be_p(response + 2, status);
71
}
72
73
static void sd_response_r7_make(SDState *sd, uint8_t *response)
74
{
75
- response[0] = (sd->vhs >> 24) & 0xff;
76
- response[1] = (sd->vhs >> 16) & 0xff;
77
- response[2] = (sd->vhs >> 8) & 0xff;
78
- response[3] = (sd->vhs >> 0) & 0xff;
79
+ stl_be_p(response, sd->vhs);
80
}
81
82
static inline uint64_t sd_addr_to_wpnum(uint64_t addr)
83
@@ -XXX,XX +XXX,XX @@ static uint32_t sd_wpbits(SDState *sd, uint64_t addr)
84
85
static void sd_function_switch(SDState *sd, uint32_t arg)
86
{
87
- int i, mode, new_func, crc;
88
+ int i, mode, new_func;
89
mode = !!(arg & 0x80000000);
90
91
sd->data[0] = 0x00;        /* Maximum current consumption */
92
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
93
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
94
}
95
memset(&sd->data[17], 0, 47);
96
- crc = sd_crc16(sd->data, 64);
97
- sd->data[65] = crc >> 8;
98
- sd->data[66] = crc & 0xff;
99
+ stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
100
}
101
102
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
103
--
31
--
104
2.16.1
32
2.20.1
105
33
106
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/32] sdcard: add a trace event for command responses
[Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
All of the inputs to these instructions are 32-bits. Rather than
4
Message-id: 20180215220540.6556-4-f4bug@amsat.org
4
extend each input to 64-bits and then extract the high 32-bits of
5
the output, use tcg_gen_muls2_i32 and other 32-bit generator functions.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190808202616.13782-7-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
hw/sd/sd.c | 27 ++++++++++++++++++++++++---
12
target/arm/translate.c | 72 +++++++++++++++---------------------------
9
hw/sd/trace-events | 1 +
13
1 file changed, 26 insertions(+), 46 deletions(-)
10
2 files changed, 25 insertions(+), 3 deletions(-)
11
14
12
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sd.c
17
--- a/target/arm/translate.c
15
+++ b/hw/sd/sd.c
18
+++ b/target/arm/translate.c
16
@@ -XXX,XX +XXX,XX @@ static const char *sd_state_name(enum SDCardStates state)
19
@@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 var)
17
return state_name[state];
20
tcg_gen_ext16s_i32(var, var);
18
}
21
}
19
22
20
+static const char *sd_response_name(sd_rsp_type_t rsp)
23
-/* Return (b << 32) + a. Mark inputs as dead */
21
+{
24
-static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b)
22
+ static const char *response_name[] = {
25
-{
23
+ [sd_r0] = "RESP#0 (no response)",
26
- TCGv_i64 tmp64 = tcg_temp_new_i64();
24
+ [sd_r1] = "RESP#1 (normal cmd)",
27
-
25
+ [sd_r2_i] = "RESP#2 (CID reg)",
28
- tcg_gen_extu_i32_i64(tmp64, b);
26
+ [sd_r2_s] = "RESP#2 (CSD reg)",
29
- tcg_temp_free_i32(b);
27
+ [sd_r3] = "RESP#3 (OCR reg)",
30
- tcg_gen_shli_i64(tmp64, tmp64, 32);
28
+ [sd_r6] = "RESP#6 (RCA)",
31
- tcg_gen_add_i64(a, tmp64, a);
29
+ [sd_r7] = "RESP#7 (operating voltage)",
32
-
30
+ };
33
- tcg_temp_free_i64(tmp64);
31
+ if (rsp == sd_illegal) {
34
- return a;
32
+ return "ILLEGAL RESP";
35
-}
33
+ }
36
-
34
+ if (rsp == sd_r1b) {
37
-/* Return (b << 32) - a. Mark inputs as dead. */
35
+ rsp = sd_r1;
38
-static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b)
36
+ }
39
-{
37
+ assert(rsp <= ARRAY_SIZE(response_name));
40
- TCGv_i64 tmp64 = tcg_temp_new_i64();
38
+ return response_name[rsp];
41
-
39
+}
42
- tcg_gen_extu_i32_i64(tmp64, b);
40
+
43
- tcg_temp_free_i32(b);
41
static uint8_t sd_get_dat_lines(SDState *sd)
44
- tcg_gen_shli_i64(tmp64, tmp64, 32);
45
- tcg_gen_sub_i64(a, tmp64, a);
46
-
47
- tcg_temp_free_i64(tmp64);
48
- return a;
49
-}
50
-
51
/* 32x32->64 multiply. Marks inputs as dead. */
52
static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b)
42
{
53
{
43
return sd->enable ? sd->dat_lines : 0;
54
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
44
@@ -XXX,XX +XXX,XX @@ send_response:
55
(SMMUL, SMMLA, SMMLS) */
45
56
tmp = load_reg(s, rm);
46
case sd_r0:
57
tmp2 = load_reg(s, rs);
47
case sd_illegal:
58
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
48
- default:
59
+ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
49
rsplen = 0;
60
50
break;
61
if (rd != 15) {
51
+ default:
62
- tmp = load_reg(s, rd);
52
+ g_assert_not_reached();
63
+ tmp3 = load_reg(s, rd);
53
}
64
if (insn & (1 << 6)) {
54
+ trace_sdcard_response(sd_response_name(rtype), rsplen);
65
- tmp64 = gen_subq_msw(tmp64, tmp);
55
66
+ tcg_gen_sub_i32(tmp, tmp, tmp3);
56
if (rtype != sd_illegal) {
67
} else {
57
/* Clear the "clear on valid command" status bits now we've
68
- tmp64 = gen_addq_msw(tmp64, tmp);
58
@@ -XXX,XX +XXX,XX @@ send_response:
69
+ tcg_gen_add_i32(tmp, tmp, tmp3);
59
DPRINTF(" %02x", response[i]);
70
}
60
}
71
+ tcg_temp_free_i32(tmp3);
61
DPRINTF(" state %d\n", sd->state);
72
}
62
- } else {
73
if (insn & (1 << 5)) {
63
- DPRINTF("No response %d\n", sd->state);
74
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
64
}
75
+ /*
65
#endif
76
+ * Adding 0x80000000 to the 64-bit quantity
66
77
+ * means that we have carry in to the high
67
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
78
+ * word when the low word has the high bit set.
68
index XXXXXXX..XXXXXXX 100644
79
+ */
69
--- a/hw/sd/trace-events
80
+ tcg_gen_shri_i32(tmp2, tmp2, 31);
70
+++ b/hw/sd/trace-events
81
+ tcg_gen_add_i32(tmp, tmp, tmp2);
71
@@ -XXX,XX +XXX,XX @@ sdhci_capareg(const char *desc, uint16_t val) "%s: %u"
82
}
72
# hw/sd/sd.c
83
- tcg_gen_shri_i64(tmp64, tmp64, 32);
73
sdcard_normal_command(uint8_t cmd, uint32_t arg, const char *state) "CMD%d arg 0x%08x (state %s)"
84
- tmp = tcg_temp_new_i32();
74
sdcard_app_command(uint8_t acmd, uint32_t arg) "ACMD%d arg 0x%08x"
85
- tcg_gen_extrl_i64_i32(tmp, tmp64);
75
+sdcard_response(const char *rspdesc, int rsplen) "%s (sz:%d)"
86
- tcg_temp_free_i64(tmp64);
76
sdcard_read_block(uint64_t addr, uint32_t len) "addr 0x%" PRIx64 " size 0x%x"
87
+ tcg_temp_free_i32(tmp2);
77
sdcard_write_block(uint64_t addr, uint32_t len) "addr 0x%" PRIx64 " size 0x%x"
88
store_reg(s, rn, tmp);
78
89
break;
90
case 0:
91
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
92
}
93
break;
94
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
95
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
96
+ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
97
if (rs != 15) {
98
- tmp = load_reg(s, rs);
99
+ tmp3 = load_reg(s, rs);
100
if (insn & (1 << 20)) {
101
- tmp64 = gen_addq_msw(tmp64, tmp);
102
+ tcg_gen_add_i32(tmp, tmp, tmp3);
103
} else {
104
- tmp64 = gen_subq_msw(tmp64, tmp);
105
+ tcg_gen_sub_i32(tmp, tmp, tmp3);
106
}
107
+ tcg_temp_free_i32(tmp3);
108
}
109
if (insn & (1 << 4)) {
110
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
111
+ /*
112
+ * Adding 0x80000000 to the 64-bit quantity
113
+ * means that we have carry in to the high
114
+ * word when the low word has the high bit set.
115
+ */
116
+ tcg_gen_shri_i32(tmp2, tmp2, 31);
117
+ tcg_gen_add_i32(tmp, tmp, tmp2);
118
}
119
- tcg_gen_shri_i64(tmp64, tmp64, 32);
120
- tmp = tcg_temp_new_i32();
121
- tcg_gen_extrl_i64_i32(tmp, tmp64);
122
- tcg_temp_free_i64(tmp64);
123
+ tcg_temp_free_i32(tmp2);
124
break;
125
case 7: /* Unsigned sum of absolute differences. */
126
gen_helper_usad8(tmp, tmp, tmp2);
79
--
127
--
80
2.16.1
128
2.20.1
81
129
82
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/32] sdcard: use G_BYTE from cutils
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
code is now easier to read.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20180215220540.6556-11-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/sd/sd.c | 3 ++-
11
1 file changed, 2 insertions(+), 1 deletion(-)
12
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
16
+++ b/hw/sd/sd.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/sd/sd.h"
19
#include "qapi/error.h"
20
#include "qemu/bitmap.h"
21
+#include "qemu/cutils.h"
22
#include "hw/qdev-properties.h"
23
#include "qemu/error-report.h"
24
#include "qemu/timer.h"
25
@@ -XXX,XX +XXX,XX @@ static void sd_set_csd(SDState *sd, uint64_t size)
26
uint32_t sectsize = (1 << (SECTOR_SHIFT + 1)) - 1;
27
uint32_t wpsize = (1 << (WPGROUP_SHIFT + 1)) - 1;
28
29
- if (size <= 0x40000000) {    /* Standard Capacity SD */
30
+ if (size <= 1 * G_BYTE) { /* Standard Capacity SD */
31
sd->csd[0] = 0x00;    /* CSD structure */
32
sd->csd[1] = 0x26;    /* Data read access-time-1 */
33
sd->csd[2] = 0x00;    /* Data read access-time-2 */
34
--
35
2.16.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/32] sdcard: remove commands from unsupported old MMC specification
[Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This device does not model MMCA Specification previous to v4.2
3
Separate shift + extract low will result in one extra insn
4
for hosts like RISC-V, MIPS, and Sparc.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20190808202616.13782-8-richard.henderson@linaro.org
7
Message-id: 20180215221325.7611-6-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
hw/sd/sd.c | 33 ---------------------------------
11
target/arm/translate.c | 18 ++++++------------
11
1 file changed, 33 deletions(-)
12
1 file changed, 6 insertions(+), 12 deletions(-)
12
13
13
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sd.c
16
--- a/target/arm/translate.c
16
+++ b/hw/sd/sd.c
17
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd,
18
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
18
}
19
if (insn & ARM_CP_RW_BIT) { /* TMRRC */
19
break;
20
iwmmxt_load_reg(cpu_V0, wrd);
20
21
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
21
- case 11:    /* CMD11: READ_DAT_UNTIL_STOP */
22
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
22
- if (sd->spi)
23
- tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
23
- goto bad_cmd;
24
+ tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
24
- switch (sd->state) {
25
} else { /* TMCRR */
25
- case sd_transfer_state:
26
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
26
- sd->state = sd_sendingdata_state;
27
iwmmxt_store_reg(cpu_V0, wrd);
27
- sd->data_start = req.arg;
28
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
28
- sd->data_offset = 0;
29
if (insn & ARM_CP_RW_BIT) { /* MRA */
29
-
30
iwmmxt_load_reg(cpu_V0, acc);
30
- if (sd->data_start + sd->blk_len > sd->size)
31
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
31
- sd->card_status |= ADDRESS_ERROR;
32
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
32
- return sd_r0;
33
- tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
33
-
34
+ tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
34
- default:
35
tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
35
- break;
36
} else { /* MAR */
36
- }
37
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
37
- break;
38
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
38
-
39
gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
39
case 12:    /* CMD12: STOP_TRANSMISSION */
40
break;
40
switch (sd->state) {
41
case 2:
41
case sd_sendingdata_state:
42
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
42
@@ -XXX,XX +XXX,XX @@ uint8_t sd_read_data(SDState *sd)
43
- tcg_gen_extrl_i64_i32(tmp, cpu_V0);
43
sd->state = sd_transfer_state;
44
+ tcg_gen_extrh_i64_i32(tmp, cpu_V0);
44
break;
45
break;
45
46
default: abort();
46
- case 11:    /* CMD11: READ_DAT_UNTIL_STOP */
47
}
47
- if (sd->data_offset == 0)
48
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
48
- BLK_READ_BLOCK(sd->data_start, io_len);
49
break;
49
- ret = sd->data[sd->data_offset ++];
50
case 2:
50
-
51
tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
51
- if (sd->data_offset >= io_len) {
52
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
52
- sd->data_start += io_len;
53
- tcg_gen_extrl_i64_i32(tmp, cpu_V0);
53
- sd->data_offset = 0;
54
+ tcg_gen_extrh_i64_i32(tmp, cpu_V0);
54
- if (sd->data_start + io_len > sd->size) {
55
break;
55
- sd->card_status |= ADDRESS_ERROR;
56
default: abort();
56
- break;
57
}
57
- }
58
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
58
- }
59
tmp = tcg_temp_new_i32();
59
- break;
60
tcg_gen_extrl_i64_i32(tmp, tmp64);
60
-
61
store_reg(s, rt, tmp);
61
case 13:    /* ACMD13: SD_STATUS */
62
- tcg_gen_shri_i64(tmp64, tmp64, 32);
62
ret = sd->sd_status[sd->data_offset ++];
63
tmp = tcg_temp_new_i32();
64
- tcg_gen_extrl_i64_i32(tmp, tmp64);
65
+ tcg_gen_extrh_i64_i32(tmp, tmp64);
66
tcg_temp_free_i64(tmp64);
67
store_reg(s, rt2, tmp);
68
} else {
69
@@ -XXX,XX +XXX,XX @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
70
tcg_gen_extrl_i64_i32(tmp, val);
71
store_reg(s, rlow, tmp);
72
tmp = tcg_temp_new_i32();
73
- tcg_gen_shri_i64(val, val, 32);
74
- tcg_gen_extrl_i64_i32(tmp, val);
75
+ tcg_gen_extrh_i64_i32(tmp, val);
76
store_reg(s, rhigh, tmp);
77
}
63
78
64
--
79
--
65
2.16.1
80
2.20.1
66
81
67
82
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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