On 17 February 2018 at 18:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-sve.c | 13 +++++++++++++
> target/arm/sve.decode | 6 ++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 207a22a0bc..fc2a295ab7 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -2422,6 +2422,19 @@ static void trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> do_last_general(s, a, true);
> }
>
> +static void trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> +{
> + do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn));
> +}
> +
> +static void trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> +{
> + int ofs = vec_reg_offset(s, a->rn, 0, a->esz);
> + TCGv_i64 t = load_esz(cpu_env, ofs, a->esz);
> + do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);
> + tcg_temp_free_i64(t);
> +}
> +
> /*
> *** SVE Memory - 32-bit Gather and Unsized Contiguous Group
> */
> diff --git a/target/arm/sve.decode b/target/arm/sve.decode
> index 1370802c12..5e127de88c 100644
> --- a/target/arm/sve.decode
> +++ b/target/arm/sve.decode
> @@ -451,6 +451,12 @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
> LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
> LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
>
> +# SVE copy element from SIMD&FP scalar register
> +CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
> +
> +# SVE copy element from general register to vector (predicated)
> +CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
> +
> ### SVE Predicate Logical Operations Group
>
> # SVE predicate logical operations
> --
> 2.14.3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
(if only every patch in the series was this size...)
thanks
-- PMM