[Qemu-devel] [PULL 00/20] target-arm queue
[PULL v2 0/7] target-arm queue
1
Changes v1->v2: it turns out that the raspi3 support exposes a
1
v2: added a missing #include qemu/error-report.h which only causes
2
preexisting bug in our register definitions for VMPIDR/VMIDR:
2
build failure in some configs, not all.
3
https://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04181.html
4
3
5
So I've dropped the final "enable raspi3 board" patch for the
4
The following changes since commit 853546f8128476eefb701d4a55b2781bb3a46faa:
6
moment. When that VMIDR/VMPIDR patch gets reviewed we can
7
put the raspi3 patch in with it.
8
5
9
6
Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into staging (2024-03-22 10:59:57 +0000)
10
thanks
11
-- PMM
12
13
The following changes since commit f003d07337a6d4d02c43429b26a4270459afb51a:
14
15
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2018-02-15 15:45:33 +0000)
16
7
17
are available in the Git repository at:
8
are available in the Git repository at:
18
9
19
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180215-1
10
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240325-1
20
11
21
for you to fetch changes up to bade58166f4466546600d824a2695a00269d10eb:
12
for you to fetch changes up to fe3e38390126c2202292911c49d46fc7ee4a163a:
22
13
23
raspi: Raspberry Pi 3 support (2018-02-15 18:33:46 +0000)
14
tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25 14:17:07 +0000)
24
15
25
----------------------------------------------------------------
16
----------------------------------------------------------------
26
target-arm queue:
17
target-arm queue:
27
* aspeed: code cleanup to use unimplemented_device
18
* Fixes for seven minor coverity issues
28
* preparatory work for 'raspi3' RaspberryPi 3 machine model
29
* more SVE prep work
30
* v8M: add minor missing registers
31
* v7M: fix bug where we weren't migrating v7m.other_sp
32
* v7M: fix bugs in handling of interrupt registers for
33
external interrupts beyond 32
34
19
35
----------------------------------------------------------------
20
----------------------------------------------------------------
36
Pekka Enberg (2):
21
Peter Maydell (7):
37
bcm2836: Make CPU type configurable
22
tests/qtest/npcm7xx_emc_test: Don't leak cmd_line
38
raspi: Raspberry Pi 3 support
23
tests/unit/socket-helpers: Don't close(-1)
24
net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp()
25
hw/misc/pca9554: Correct error check bounds in get/set pin functions
26
hw/nvram/mac_nvram: Report failure to write data
27
tests/unit/test-throttle: Avoid unintended integer division
28
tests/qtest/libqtest.c: Check for g_setenv() failure
39
29
40
Peter Maydell (11):
30
hw/misc/pca9554.c | 4 ++--
41
hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
31
hw/nvram/mac_nvram.c | 6 +++++-
42
hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
32
net/af-xdp.c | 3 +--
43
hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
33
tests/qtest/libqtest.c | 6 +++++-
44
hw/intc/armv7m_nvic: Implement v8M CPPWR register
34
tests/qtest/npcm7xx_emc-test.c | 4 ++--
45
hw/intc/armv7m_nvic: Implement cache ID registers
35
tests/unit/socket-helpers.c | 4 +++-
46
hw/intc/armv7m_nvic: Implement SCR
36
tests/unit/test-throttle.c | 4 ++--
47
target/arm: Implement writing to CONTROL_NS for v8M
37
7 files changed, 20 insertions(+), 11 deletions(-)
48
hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions
49
target/arm: Add AIRCR to vmstate struct
50
target/arm: Migrate v7m.other_sp
51
target/arm: Implement v8M MSPLIM and PSPLIM registers
52
53
Philippe Mathieu-Daudé (2):
54
hw/arm/aspeed: directly map the serial device to the system address space
55
hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io
56
57
Richard Henderson (5):
58
target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
59
target/arm: Enforce FP access to FPCR/FPSR
60
target/arm: Suppress TB end for FPCR/FPSR
61
target/arm: Enforce access to ZCR_EL at translation
62
target/arm: Handle SVE registers when using clear_vec_high
63
64
include/hw/arm/aspeed_soc.h | 1 -
65
include/hw/arm/bcm2836.h | 1 +
66
target/arm/cpu.h | 71 ++++++++++++-----
67
target/arm/internals.h | 6 ++
68
hw/arm/aspeed_soc.c | 35 ++-------
69
hw/arm/bcm2836.c | 17 +++--
70
hw/arm/raspi.c | 34 ++++++---
71
hw/intc/armv7m_nvic.c | 98 ++++++++++++++++++------
72
target/arm/cpu.c | 28 +++++++
73
target/arm/helper.c | 84 +++++++++++++++-----
74
target/arm/machine.c | 84 ++++++++++++++++++++
75
target/arm/translate-a64.c | 181 ++++++++++++++++++++------------------------
76
12 files changed, 429 insertions(+), 211 deletions(-)
77
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/20] hw/arm/aspeed: directly map the serial device to the system address space
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
(qemu) info mtree
4
address-space: cpu-memory-0
5
0000000000000000-ffffffffffffffff (prio 0, i/o): system
6
0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom
7
000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io
8
- 000000001e784000-000000001e78401f (prio 0, i/o): serial
9
000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc
10
000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1
11
[...]
12
000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram
13
000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer
14
+ 000000001e784000-000000001e78401f (prio 0, i/o): serial
15
000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt
16
000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt
17
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Reviewed-by: Cédric Le Goater <clg@kaod.org>
20
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
21
Message-id: 20180209085755.30414-2-f4bug@amsat.org
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
24
hw/arm/aspeed_soc.c | 3 ++-
25
1 file changed, 2 insertions(+), 1 deletion(-)
26
27
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/aspeed_soc.c
30
+++ b/hw/arm/aspeed_soc.c
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
32
/* UART - attach an 8250 to the IO space as our UART5 */
33
if (serial_hds[0]) {
34
qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
35
- serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
36
+ serial_mm_init(get_system_memory(),
37
+ ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
38
uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
39
}
40
41
--
42
2.16.1
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/20] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
(qemu) info mtree
4
address-space: cpu-memory-0
5
0000000000000000-ffffffffffffffff (prio 0, i/o): system
6
0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom
7
- 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io
8
+ 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io
9
000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc
10
000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1
11
000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2
12
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
16
Message-id: 20180209085755.30414-3-f4bug@amsat.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/arm/aspeed_soc.h | 1 -
20
hw/arm/aspeed_soc.c | 32 +++-----------------------------
21
2 files changed, 3 insertions(+), 30 deletions(-)
22
23
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/aspeed_soc.h
26
+++ b/include/hw/arm/aspeed_soc.h
27
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
28
29
/*< public >*/
30
ARMCPU cpu;
31
- MemoryRegion iomem;
32
MemoryRegion sram;
33
AspeedVICState vic;
34
AspeedTimerCtrlState timerctrl;
35
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/aspeed_soc.c
38
+++ b/hw/arm/aspeed_soc.c
39
@@ -XXX,XX +XXX,XX @@
40
#include "qemu-common.h"
41
#include "cpu.h"
42
#include "exec/address-spaces.h"
43
+#include "hw/misc/unimp.h"
44
#include "hw/arm/aspeed_soc.h"
45
#include "hw/char/serial.h"
46
#include "qemu/log.h"
47
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
48
},
49
};
50
51
-/*
52
- * IO handlers: simply catch any reads/writes to IO addresses that aren't
53
- * handled by a device mapping.
54
- */
55
-
56
-static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
57
-{
58
- qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
59
- __func__, offset, size);
60
- return 0;
61
-}
62
-
63
-static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
64
- unsigned size)
65
-{
66
- qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
67
- __func__, offset, value, size);
68
-}
69
-
70
-static const MemoryRegionOps aspeed_soc_io_ops = {
71
- .read = aspeed_soc_io_read,
72
- .write = aspeed_soc_io_write,
73
- .endianness = DEVICE_LITTLE_ENDIAN,
74
-};
75
-
76
static void aspeed_soc_init(Object *obj)
77
{
78
AspeedSoCState *s = ASPEED_SOC(obj);
79
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
80
Error *err = NULL, *local_err = NULL;
81
82
/* IO space */
83
- memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
84
- "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
85
- memory_region_add_subregion_overlap(get_system_memory(),
86
- ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
87
+ create_unimplemented_device("aspeed_soc.io",
88
+ ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
89
90
/* CPU */
91
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
92
--
93
2.16.1
94
95
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/20] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20180211205848.4568-2-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 8 ++++----
11
1 file changed, 4 insertions(+), 4 deletions(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
static const ARMCPRegInfo zcr_el1_reginfo = {
19
.name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
20
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
21
- .access = PL1_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
22
+ .access = PL1_RW, .accessfn = zcr_access,
23
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
24
.writefn = zcr_write, .raw_writefn = raw_write
25
};
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el1_reginfo = {
27
static const ARMCPRegInfo zcr_el2_reginfo = {
28
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
29
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
30
- .access = PL2_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
31
+ .access = PL2_RW, .accessfn = zcr_access,
32
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
33
.writefn = zcr_write, .raw_writefn = raw_write
34
};
35
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el2_reginfo = {
36
static const ARMCPRegInfo zcr_no_el2_reginfo = {
37
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
38
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
39
- .access = PL2_RW, .type = ARM_CP_64BIT,
40
+ .access = PL2_RW,
41
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
42
};
43
44
static const ARMCPRegInfo zcr_el3_reginfo = {
45
.name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
46
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
47
- .access = PL3_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
48
+ .access = PL3_RW, .accessfn = zcr_access,
49
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
50
.writefn = zcr_write, .raw_writefn = raw_write
51
};
52
--
53
2.16.1
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/20] target/arm: Enforce FP access to FPCR/FPSR
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20180211205848.4568-3-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/cpu.h | 35 ++++++++++++++++++-----------------
9
target/arm/helper.c | 6 ++++--
10
target/arm/translate-a64.c | 3 +++
11
3 files changed, 25 insertions(+), 19 deletions(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
18
}
19
20
/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
21
- * special-behaviour cp reg and bits [15..8] indicate what behaviour
22
+ * special-behaviour cp reg and bits [11..8] indicate what behaviour
23
* it has. Otherwise it is a simple cp reg, where CONST indicates that
24
* TCG can assume the value to be constant (ie load at translate time)
25
* and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
26
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
27
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
28
* registers which implement clocks or timers require this.
29
*/
30
-#define ARM_CP_SPECIAL 1
31
-#define ARM_CP_CONST 2
32
-#define ARM_CP_64BIT 4
33
-#define ARM_CP_SUPPRESS_TB_END 8
34
-#define ARM_CP_OVERRIDE 16
35
-#define ARM_CP_ALIAS 32
36
-#define ARM_CP_IO 64
37
-#define ARM_CP_NO_RAW 128
38
-#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
39
-#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
40
-#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
41
-#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
42
-#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
43
-#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
44
+#define ARM_CP_SPECIAL 0x0001
45
+#define ARM_CP_CONST 0x0002
46
+#define ARM_CP_64BIT 0x0004
47
+#define ARM_CP_SUPPRESS_TB_END 0x0008
48
+#define ARM_CP_OVERRIDE 0x0010
49
+#define ARM_CP_ALIAS 0x0020
50
+#define ARM_CP_IO 0x0040
51
+#define ARM_CP_NO_RAW 0x0080
52
+#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
53
+#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
54
+#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
55
+#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
56
+#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
57
+#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
58
+#define ARM_CP_FPU 0x1000
59
/* Used only as a terminator for ARMCPRegInfo lists */
60
-#define ARM_CP_SENTINEL 0xffff
61
+#define ARM_CP_SENTINEL 0xffff
62
/* Mask of only the flag bits in a type field */
63
-#define ARM_CP_FLAG_MASK 0xff
64
+#define ARM_CP_FLAG_MASK 0x10ff
65
66
/* Valid values for ARMCPRegInfo state field, indicating which of
67
* the AArch32 and AArch64 execution states this register is visible in.
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/helper.c
71
+++ b/target/arm/helper.c
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
73
.writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
74
{ .name = "FPCR", .state = ARM_CP_STATE_AA64,
75
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
76
- .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
77
+ .access = PL0_RW, .type = ARM_CP_FPU,
78
+ .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
79
{ .name = "FPSR", .state = ARM_CP_STATE_AA64,
80
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
81
- .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
82
+ .access = PL0_RW, .type = ARM_CP_FPU,
83
+ .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
84
{ .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
85
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
86
.access = PL0_R, .type = ARM_CP_NO_RAW,
87
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/translate-a64.c
90
+++ b/target/arm/translate-a64.c
91
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
92
default:
93
break;
94
}
95
+ if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
96
+ return;
97
+ }
98
99
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
100
gen_io_start();
101
--
102
2.16.1
103
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/20] target/arm: Suppress TB end for FPCR/FPSR
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Nothing in either register affects the TB.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20180211205848.4568-4-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
18
.writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
19
{ .name = "FPCR", .state = ARM_CP_STATE_AA64,
20
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
21
- .access = PL0_RW, .type = ARM_CP_FPU,
22
+ .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
23
.readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
24
{ .name = "FPSR", .state = ARM_CP_STATE_AA64,
25
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
26
- .access = PL0_RW, .type = ARM_CP_FPU,
27
+ .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
28
.readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
29
{ .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
30
.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
31
--
32
2.16.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/20] target/arm: Enforce access to ZCR_EL at translation
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This also makes sure that we get the correct ordering of
4
SVE vs FP exceptions.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180211205848.4568-5-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 3 ++-
12
target/arm/internals.h | 6 ++++++
13
target/arm/helper.c | 22 ++++------------------
14
target/arm/translate-a64.c | 16 ++++++++++++++++
15
4 files changed, 28 insertions(+), 19 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
22
#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
23
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
24
#define ARM_CP_FPU 0x1000
25
+#define ARM_CP_SVE 0x2000
26
/* Used only as a terminator for ARMCPRegInfo lists */
27
#define ARM_CP_SENTINEL 0xffff
28
/* Mask of only the flag bits in a type field */
29
-#define ARM_CP_FLAG_MASK 0x10ff
30
+#define ARM_CP_FLAG_MASK 0x30ff
31
32
/* Valid values for ARMCPRegInfo state field, indicating which of
33
* the AArch32 and AArch64 execution states this register is visible in.
34
diff --git a/target/arm/internals.h b/target/arm/internals.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/internals.h
37
+++ b/target/arm/internals.h
38
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
39
EC_AA64_HVC = 0x16,
40
EC_AA64_SMC = 0x17,
41
EC_SYSTEMREGISTERTRAP = 0x18,
42
+ EC_SVEACCESSTRAP = 0x19,
43
EC_INSNABORT = 0x20,
44
EC_INSNABORT_SAME_EL = 0x21,
45
EC_PCALIGNMENT = 0x22,
46
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
47
| (cv << 24) | (cond << 20);
48
}
49
50
+static inline uint32_t syn_sve_access_trap(void)
51
+{
52
+ return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
53
+}
54
+
55
static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
56
{
57
return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
58
diff --git a/target/arm/helper.c b/target/arm/helper.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/helper.c
61
+++ b/target/arm/helper.c
62
@@ -XXX,XX +XXX,XX @@ static int sve_exception_el(CPUARMState *env)
63
return 0;
64
}
65
66
-static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri,
67
- bool isread)
68
-{
69
- switch (sve_exception_el(env)) {
70
- case 3:
71
- return CP_ACCESS_TRAP_EL3;
72
- case 2:
73
- return CP_ACCESS_TRAP_EL2;
74
- case 1:
75
- return CP_ACCESS_TRAP;
76
- }
77
- return CP_ACCESS_OK;
78
-}
79
-
80
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
81
uint64_t value)
82
{
83
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
84
static const ARMCPRegInfo zcr_el1_reginfo = {
85
.name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
86
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
87
- .access = PL1_RW, .accessfn = zcr_access,
88
+ .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
89
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
90
.writefn = zcr_write, .raw_writefn = raw_write
91
};
92
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el1_reginfo = {
93
static const ARMCPRegInfo zcr_el2_reginfo = {
94
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
95
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
96
- .access = PL2_RW, .accessfn = zcr_access,
97
+ .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
98
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
99
.writefn = zcr_write, .raw_writefn = raw_write
100
};
101
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el2_reginfo = {
102
static const ARMCPRegInfo zcr_no_el2_reginfo = {
103
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
104
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
105
- .access = PL2_RW,
106
+ .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
107
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
108
};
109
110
static const ARMCPRegInfo zcr_el3_reginfo = {
111
.name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
112
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
113
- .access = PL3_RW, .accessfn = zcr_access,
114
+ .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
115
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
116
.writefn = zcr_write, .raw_writefn = raw_write
117
};
118
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/arm/translate-a64.c
121
+++ b/target/arm/translate-a64.c
122
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
123
return false;
124
}
125
126
+/* Check that SVE access is enabled. If it is, return true.
127
+ * If not, emit code to generate an appropriate exception and return false.
128
+ */
129
+static inline bool sve_access_check(DisasContext *s)
130
+{
131
+ if (s->sve_excp_el) {
132
+ gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
133
+ s->sve_excp_el);
134
+ return false;
135
+ }
136
+ return true;
137
+}
138
+
139
/*
140
* This utility function is for doing register extension with an
141
* optional shift. You will likely want to pass a temporary for the
142
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
143
default:
144
break;
145
}
146
+ if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
147
+ return;
148
+ }
149
if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
150
return;
151
}
152
--
153
2.16.1
154
155
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/20] target/arm: Handle SVE registers when using clear_vec_high
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
When storing to an AdvSIMD FP register, all of the high
4
bits of the SVE register are zeroed. Therefore, call it
5
more often with is_q as a parameter.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180211205848.4568-6-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 162 +++++++++++++++++----------------------------
13
1 file changed, 62 insertions(+), 100 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
20
return v;
21
}
22
23
+/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
24
+ * If SVE is not enabled, then there are only 128 bits in the vector.
25
+ */
26
+static void clear_vec_high(DisasContext *s, bool is_q, int rd)
27
+{
28
+ unsigned ofs = fp_reg_offset(s, rd, MO_64);
29
+ unsigned vsz = vec_full_reg_size(s);
30
+
31
+ if (!is_q) {
32
+ TCGv_i64 tcg_zero = tcg_const_i64(0);
33
+ tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
34
+ tcg_temp_free_i64(tcg_zero);
35
+ }
36
+ if (vsz > 16) {
37
+ tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);
38
+ }
39
+}
40
+
41
static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
42
{
43
- TCGv_i64 tcg_zero = tcg_const_i64(0);
44
+ unsigned ofs = fp_reg_offset(s, reg, MO_64);
45
46
- tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
47
- tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg));
48
- tcg_temp_free_i64(tcg_zero);
49
+ tcg_gen_st_i64(v, cpu_env, ofs);
50
+ clear_vec_high(s, false, reg);
51
}
52
53
static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
54
@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
55
56
tcg_temp_free_i64(tmplo);
57
tcg_temp_free_i64(tmphi);
58
+
59
+ clear_vec_high(s, true, destidx);
60
}
61
62
/*
63
@@ -XXX,XX +XXX,XX @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
64
}
65
}
66
67
-/* Clear the high 64 bits of a 128 bit vector (in general non-quad
68
- * vector ops all need to do this).
69
- */
70
-static void clear_vec_high(DisasContext *s, int rd)
71
-{
72
- TCGv_i64 tcg_zero = tcg_const_i64(0);
73
-
74
- write_vec_element(s, tcg_zero, rd, 1, MO_64);
75
- tcg_temp_free_i64(tcg_zero);
76
-}
77
-
78
/* Store from vector register to memory */
79
static void do_vec_st(DisasContext *s, int srcidx, int element,
80
TCGv_i64 tcg_addr, int size)
81
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
82
/* For non-quad operations, setting a slice of the low
83
* 64 bits of the register clears the high 64 bits (in
84
* the ARM ARM pseudocode this is implicit in the fact
85
- * that 'rval' is a 64 bit wide variable). We optimize
86
- * by noticing that we only need to do this the first
87
- * time we touch a register.
88
+ * that 'rval' is a 64 bit wide variable).
89
+ * For quad operations, we might still need to zero the
90
+ * high bits of SVE. We optimize by noticing that we only
91
+ * need to do this the first time we touch a register.
92
*/
93
- if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {
94
- clear_vec_high(s, tt);
95
+ if (e == 0 && (r == 0 || xs == selem - 1)) {
96
+ clear_vec_high(s, is_q, tt);
97
}
98
}
99
tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
100
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
101
write_vec_element(s, tcg_tmp, rt, 0, MO_64);
102
if (is_q) {
103
write_vec_element(s, tcg_tmp, rt, 1, MO_64);
104
- } else {
105
- clear_vec_high(s, rt);
106
}
107
tcg_temp_free_i64(tcg_tmp);
108
+ clear_vec_high(s, is_q, rt);
109
} else {
110
/* Load/store one element per register */
111
if (is_load) {
112
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
113
}
114
115
if (!is_q) {
116
- clear_vec_high(s, rd);
117
write_vec_element(s, tcg_final, rd, 0, MO_64);
118
} else {
119
write_vec_element(s, tcg_final, rd, 1, MO_64);
120
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
121
tcg_temp_free_i64(tcg_rd);
122
tcg_temp_free_i32(tcg_rd_narrowed);
123
tcg_temp_free_i64(tcg_final);
124
- return;
125
+
126
+ clear_vec_high(s, is_q, rd);
127
}
128
129
/* SQSHLU, UQSHL, SQSHL: saturating left shifts */
130
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
131
tcg_temp_free_i64(tcg_op);
132
}
133
tcg_temp_free_i64(tcg_shift);
134
-
135
- if (!is_q) {
136
- clear_vec_high(s, rd);
137
- }
138
+ clear_vec_high(s, is_q, rd);
139
} else {
140
TCGv_i32 tcg_shift = tcg_const_i32(shift);
141
static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
142
@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
143
}
144
tcg_temp_free_i32(tcg_shift);
145
146
- if (!is_q && !scalar) {
147
- clear_vec_high(s, rd);
148
+ if (!scalar) {
149
+ clear_vec_high(s, is_q, rd);
150
}
151
}
152
}
153
@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
154
}
155
}
156
157
- if (!is_double && elements == 2) {
158
- clear_vec_high(s, rd);
159
- }
160
-
161
tcg_temp_free_i64(tcg_int);
162
tcg_temp_free_ptr(tcg_fpst);
163
tcg_temp_free_i32(tcg_shift);
164
+
165
+ clear_vec_high(s, elements << size == 16, rd);
166
}
167
168
/* UCVTF/SCVTF - Integer to FP conversion */
169
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
170
write_vec_element(s, tcg_op, rd, pass, MO_64);
171
tcg_temp_free_i64(tcg_op);
172
}
173
- if (!is_q) {
174
- clear_vec_high(s, rd);
175
- }
176
+ clear_vec_high(s, is_q, rd);
177
} else {
178
int maxpass = is_scalar ? 1 : is_q ? 4 : 2;
179
for (pass = 0; pass < maxpass; pass++) {
180
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
181
}
182
tcg_temp_free_i32(tcg_op);
183
}
184
- if (!is_q && !is_scalar) {
185
- clear_vec_high(s, rd);
186
+ if (!is_scalar) {
187
+ clear_vec_high(s, is_q, rd);
188
}
189
}
190
191
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
192
193
tcg_temp_free_ptr(fpst);
194
195
- if ((elements << size) < 4) {
196
- /* scalar, or non-quad vector op */
197
- clear_vec_high(s, rd);
198
- }
199
+ clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd);
200
}
201
202
/* AdvSIMD scalar three same
203
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
204
}
205
write_vec_element(s, tcg_res, rd, pass, MO_64);
206
}
207
- if (is_scalar) {
208
- clear_vec_high(s, rd);
209
- }
210
-
211
tcg_temp_free_i64(tcg_res);
212
tcg_temp_free_i64(tcg_zero);
213
tcg_temp_free_i64(tcg_op);
214
+
215
+ clear_vec_high(s, !is_scalar, rd);
216
} else {
217
TCGv_i32 tcg_op = tcg_temp_new_i32();
218
TCGv_i32 tcg_zero = tcg_const_i32(0);
219
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
220
tcg_temp_free_i32(tcg_res);
221
tcg_temp_free_i32(tcg_zero);
222
tcg_temp_free_i32(tcg_op);
223
- if (!is_q && !is_scalar) {
224
- clear_vec_high(s, rd);
225
+ if (!is_scalar) {
226
+ clear_vec_high(s, is_q, rd);
227
}
228
}
229
230
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
231
}
232
write_vec_element(s, tcg_res, rd, pass, MO_64);
233
}
234
- if (is_scalar) {
235
- clear_vec_high(s, rd);
236
- }
237
-
238
tcg_temp_free_i64(tcg_res);
239
tcg_temp_free_i64(tcg_op);
240
+ clear_vec_high(s, !is_scalar, rd);
241
} else {
242
TCGv_i32 tcg_op = tcg_temp_new_i32();
243
TCGv_i32 tcg_res = tcg_temp_new_i32();
244
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
245
}
246
tcg_temp_free_i32(tcg_res);
247
tcg_temp_free_i32(tcg_op);
248
- if (!is_q && !is_scalar) {
249
- clear_vec_high(s, rd);
250
+ if (!is_scalar) {
251
+ clear_vec_high(s, is_q, rd);
252
}
253
}
254
tcg_temp_free_ptr(fpst);
255
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
256
write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
257
tcg_temp_free_i32(tcg_res[pass]);
258
}
259
- if (!is_q) {
260
- clear_vec_high(s, rd);
261
- }
262
+ clear_vec_high(s, is_q, rd);
263
}
264
265
/* Remaining saturating accumulating ops */
266
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
267
}
268
write_vec_element(s, tcg_rd, rd, pass, MO_64);
269
}
270
- if (is_scalar) {
271
- clear_vec_high(s, rd);
272
- }
273
-
274
tcg_temp_free_i64(tcg_rd);
275
tcg_temp_free_i64(tcg_rn);
276
+ clear_vec_high(s, !is_scalar, rd);
277
} else {
278
TCGv_i32 tcg_rn = tcg_temp_new_i32();
279
TCGv_i32 tcg_rd = tcg_temp_new_i32();
280
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
281
}
282
write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
283
}
284
-
285
- if (!is_q) {
286
- clear_vec_high(s, rd);
287
- }
288
-
289
tcg_temp_free_i32(tcg_rd);
290
tcg_temp_free_i32(tcg_rn);
291
+ clear_vec_high(s, is_q, rd);
292
}
293
}
294
295
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
296
tcg_temp_free_i64(tcg_round);
297
298
done:
299
- if (!is_q) {
300
- clear_vec_high(s, rd);
301
- }
302
+ clear_vec_high(s, is_q, rd);
303
}
304
305
static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
306
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
307
}
308
309
if (!is_q) {
310
- clear_vec_high(s, rd);
311
write_vec_element(s, tcg_final, rd, 0, MO_64);
312
} else {
313
write_vec_element(s, tcg_final, rd, 1, MO_64);
314
}
315
-
316
if (round) {
317
tcg_temp_free_i64(tcg_round);
318
}
319
tcg_temp_free_i64(tcg_rn);
320
tcg_temp_free_i64(tcg_rd);
321
tcg_temp_free_i64(tcg_final);
322
- return;
323
+
324
+ clear_vec_high(s, is_q, rd);
325
}
326
327
328
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
329
write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
330
tcg_temp_free_i32(tcg_res[pass]);
331
}
332
- if (!is_q) {
333
- clear_vec_high(s, rd);
334
- }
335
+ clear_vec_high(s, is_q, rd);
336
}
337
338
static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
339
@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
340
write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
341
tcg_temp_free_i32(tcg_res[pass]);
342
}
343
- if (!is_q) {
344
- clear_vec_high(s, rd);
345
- }
346
+ clear_vec_high(s, is_q, rd);
347
}
348
349
if (fpst) {
350
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
351
tcg_temp_free_i32(tcg_op2);
352
}
353
}
354
-
355
- if (!is_q) {
356
- clear_vec_high(s, rd);
357
- }
358
+ clear_vec_high(s, is_q, rd);
359
}
360
361
/* AdvSIMD three same
362
@@ -XXX,XX +XXX,XX @@ static void handle_rev(DisasContext *s, int opcode, bool u,
363
write_vec_element(s, tcg_tmp, rd, i, grp_size);
364
tcg_temp_free_i64(tcg_tmp);
365
}
366
- if (!is_q) {
367
- clear_vec_high(s, rd);
368
- }
369
+ clear_vec_high(s, is_q, rd);
370
} else {
371
int revmask = (1 << grp_size) - 1;
372
int esize = 8 << size;
373
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
374
tcg_temp_free_i32(tcg_op);
375
}
376
}
377
- if (!is_q) {
378
- clear_vec_high(s, rd);
379
- }
380
+ clear_vec_high(s, is_q, rd);
381
382
if (need_rmode) {
383
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
384
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
385
tcg_temp_free_i64(tcg_res);
386
}
387
388
- if (is_scalar) {
389
- clear_vec_high(s, rd);
390
- }
391
-
392
tcg_temp_free_i64(tcg_idx);
393
+ clear_vec_high(s, !is_scalar, rd);
394
} else if (!is_long) {
395
/* 32 bit floating point, or 16 or 32 bit integer.
396
* For the 16 bit scalar case we use the usual Neon helpers and
397
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
398
}
399
400
tcg_temp_free_i32(tcg_idx);
401
-
402
- if (!is_q) {
403
- clear_vec_high(s, rd);
404
- }
405
+ clear_vec_high(s, is_q, rd);
406
} else {
407
/* long ops: 16x16->32 or 32x32->64 */
408
TCGv_i64 tcg_res[2];
409
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
410
}
411
tcg_temp_free_i64(tcg_idx);
412
413
- if (is_scalar) {
414
- clear_vec_high(s, rd);
415
- }
416
+ clear_vec_high(s, !is_scalar, rd);
417
} else {
418
TCGv_i32 tcg_idx = tcg_temp_new_i32();
419
420
--
421
2.16.1
422
423
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/20] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
Deleted patch
1
Instead of hardcoding the values of M profile ID registers in the
2
NVIC, use the fields in the CPU struct. This will allow us to
3
give different M profile CPU types different ID register values.
4
1
5
This commit includes the addition of the missing ID_ISAR5,
6
which exists as RES0 in both v7M and v8M.
7
8
(The values of the ID registers might be wrong for the M4 --
9
this commit leaves the behaviour there unchanged.)
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20180209165810.6668-2-peter.maydell@linaro.org
15
---
16
hw/intc/armv7m_nvic.c | 30 ++++++++++++++++--------------
17
target/arm/cpu.c | 28 ++++++++++++++++++++++++++++
18
2 files changed, 44 insertions(+), 14 deletions(-)
19
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
23
+++ b/hw/intc/armv7m_nvic.c
24
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
25
"Aux Fault status registers unimplemented\n");
26
return 0;
27
case 0xd40: /* PFR0. */
28
- return 0x00000030;
29
- case 0xd44: /* PRF1. */
30
- return 0x00000200;
31
+ return cpu->id_pfr0;
32
+ case 0xd44: /* PFR1. */
33
+ return cpu->id_pfr1;
34
case 0xd48: /* DFR0. */
35
- return 0x00100000;
36
+ return cpu->id_dfr0;
37
case 0xd4c: /* AFR0. */
38
- return 0x00000000;
39
+ return cpu->id_afr0;
40
case 0xd50: /* MMFR0. */
41
- return 0x00000030;
42
+ return cpu->id_mmfr0;
43
case 0xd54: /* MMFR1. */
44
- return 0x00000000;
45
+ return cpu->id_mmfr1;
46
case 0xd58: /* MMFR2. */
47
- return 0x00000000;
48
+ return cpu->id_mmfr2;
49
case 0xd5c: /* MMFR3. */
50
- return 0x00000000;
51
+ return cpu->id_mmfr3;
52
case 0xd60: /* ISAR0. */
53
- return 0x01141110;
54
+ return cpu->id_isar0;
55
case 0xd64: /* ISAR1. */
56
- return 0x02111000;
57
+ return cpu->id_isar1;
58
case 0xd68: /* ISAR2. */
59
- return 0x21112231;
60
+ return cpu->id_isar2;
61
case 0xd6c: /* ISAR3. */
62
- return 0x01111110;
63
+ return cpu->id_isar3;
64
case 0xd70: /* ISAR4. */
65
- return 0x01310102;
66
+ return cpu->id_isar4;
67
+ case 0xd74: /* ISAR5. */
68
+ return cpu->id_isar5;
69
/* TODO: Implement debug registers. */
70
case 0xd90: /* MPU_TYPE */
71
/* Unified MPU; if the MPU is not present this value is zero */
72
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/cpu.c
75
+++ b/target/arm/cpu.c
76
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
77
set_feature(&cpu->env, ARM_FEATURE_M);
78
cpu->midr = 0x410fc231;
79
cpu->pmsav7_dregion = 8;
80
+ cpu->id_pfr0 = 0x00000030;
81
+ cpu->id_pfr1 = 0x00000200;
82
+ cpu->id_dfr0 = 0x00100000;
83
+ cpu->id_afr0 = 0x00000000;
84
+ cpu->id_mmfr0 = 0x00000030;
85
+ cpu->id_mmfr1 = 0x00000000;
86
+ cpu->id_mmfr2 = 0x00000000;
87
+ cpu->id_mmfr3 = 0x00000000;
88
+ cpu->id_isar0 = 0x01141110;
89
+ cpu->id_isar1 = 0x02111000;
90
+ cpu->id_isar2 = 0x21112231;
91
+ cpu->id_isar3 = 0x01111110;
92
+ cpu->id_isar4 = 0x01310102;
93
+ cpu->id_isar5 = 0x00000000;
94
}
95
96
static void cortex_m4_initfn(Object *obj)
97
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
98
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
99
cpu->midr = 0x410fc240; /* r0p0 */
100
cpu->pmsav7_dregion = 8;
101
+ cpu->id_pfr0 = 0x00000030;
102
+ cpu->id_pfr1 = 0x00000200;
103
+ cpu->id_dfr0 = 0x00100000;
104
+ cpu->id_afr0 = 0x00000000;
105
+ cpu->id_mmfr0 = 0x00000030;
106
+ cpu->id_mmfr1 = 0x00000000;
107
+ cpu->id_mmfr2 = 0x00000000;
108
+ cpu->id_mmfr3 = 0x00000000;
109
+ cpu->id_isar0 = 0x01141110;
110
+ cpu->id_isar1 = 0x02111000;
111
+ cpu->id_isar2 = 0x21112231;
112
+ cpu->id_isar3 = 0x01111110;
113
+ cpu->id_isar4 = 0x01310102;
114
+ cpu->id_isar5 = 0x00000000;
115
}
116
117
static void arm_v7m_class_init(ObjectClass *oc, void *data)
118
--
119
2.16.1
120
121
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/20] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
Deleted patch
1
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from
2
NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had
3
misimplemented this as making the bits RAZ/WI from both
4
Secure and NonSecure states. Fix this bug by checking
5
attrs.secure so that Secure code can pend and unpend NMIs.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180209165810.6668-3-peter.maydell@linaro.org
10
---
11
hw/intc/armv7m_nvic.c | 6 +++---
12
1 file changed, 3 insertions(+), 3 deletions(-)
13
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
19
}
20
}
21
/* NMIPENDSET */
22
- if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
23
- s->vectors[ARMV7M_EXCP_NMI].pending) {
24
+ if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))
25
+ && s->vectors[ARMV7M_EXCP_NMI].pending) {
26
val |= (1 << 31);
27
}
28
/* ISRPREEMPT: RES0 when halting debug not implemented */
29
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
30
break;
31
}
32
case 0xd04: /* Interrupt Control State (ICSR) */
33
- if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
34
+ if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
35
if (value & (1 << 31)) {
36
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
37
} else if (value & (1 << 30) &&
38
--
39
2.16.1
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/20] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
Deleted patch
1
For M profile cores, cache maintenance operations are done by
2
writing to special registers in the system register space.
3
For QEMU, cache operations are always NOPs, since we don't
4
implement the cache. Implementing these explicitly avoids
5
a spurious LOG_GUEST_ERROR when the guest uses them.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180209165810.6668-4-peter.maydell@linaro.org
10
---
11
hw/intc/armv7m_nvic.c | 12 ++++++++++++
12
1 file changed, 12 insertions(+)
13
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
19
}
20
break;
21
}
22
+ case 0xf50: /* ICIALLU */
23
+ case 0xf58: /* ICIMVAU */
24
+ case 0xf5c: /* DCIMVAC */
25
+ case 0xf60: /* DCISW */
26
+ case 0xf64: /* DCCMVAU */
27
+ case 0xf68: /* DCCMVAC */
28
+ case 0xf6c: /* DCCSW */
29
+ case 0xf70: /* DCCIMVAC */
30
+ case 0xf74: /* DCCISW */
31
+ case 0xf78: /* BPIALL */
32
+ /* Cache and branch predictor maintenance: for QEMU these always NOP */
33
+ break;
34
default:
35
bad_offset:
36
qemu_log_mask(LOG_GUEST_ERROR,
37
--
38
2.16.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/20] hw/intc/armv7m_nvic: Implement v8M CPPWR register
Deleted patch
1
The Coprocessor Power Control Register (CPPWR) is new in v8M.
2
It allows software to control whether coprocessors are allowed
3
to power down and lose their state. QEMU doesn't have any
4
notion of power control, so we choose the IMPDEF option of
5
making the whole register RAZ/WI (indicating that no coprocessors
6
can ever power down and lose state).
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180209165810.6668-5-peter.maydell@linaro.org
11
---
12
hw/intc/armv7m_nvic.c | 14 ++++++++++++++
13
1 file changed, 14 insertions(+)
14
15
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/armv7m_nvic.c
18
+++ b/hw/intc/armv7m_nvic.c
19
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
20
switch (offset) {
21
case 4: /* Interrupt Control Type. */
22
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
23
+ case 0xc: /* CPPWR */
24
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
25
+ goto bad_offset;
26
+ }
27
+ /* We make the IMPDEF choice that nothing can ever go into a
28
+ * non-retentive power state, which allows us to RAZ/WI this.
29
+ */
30
+ return 0;
31
case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
32
{
33
int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
34
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
35
ARMCPU *cpu = s->cpu;
36
37
switch (offset) {
38
+ case 0xc: /* CPPWR */
39
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
40
+ goto bad_offset;
41
+ }
42
+ /* Make the IMPDEF choice to RAZ/WI this. */
43
+ break;
44
case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
45
{
46
int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
47
--
48
2.16.1
49
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/20] hw/intc/armv7m_nvic: Implement cache ID registers
Deleted patch
1
M profile cores have a similar setup for cache ID registers
2
to A profile:
3
* Cache Level ID Register (CLIDR) is a fixed value
4
* Cache Type Register (CTR) is a fixed value
5
* Cache Size ID Registers (CCSIDR) are a bank of registers;
6
which one you see is selected by the Cache Size Selection
7
Register (CSSELR)
8
1
9
The only difference is that they're in the NVIC memory mapped
10
register space rather than being coprocessor registers.
11
Implement the M profile view of them.
12
13
Since neither Cortex-M3 nor Cortex-M4 implement caches,
14
we don't need to update their init functions and can leave
15
the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero.
16
Newer cores (like the Cortex-M33) will want to be able to
17
set these ID registers to non-zero values, though.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20180209165810.6668-6-peter.maydell@linaro.org
22
---
23
target/arm/cpu.h | 26 ++++++++++++++++++++++++++
24
hw/intc/armv7m_nvic.c | 16 ++++++++++++++++
25
target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++
26
3 files changed, 78 insertions(+)
27
28
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu.h
31
+++ b/target/arm/cpu.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
33
uint32_t faultmask[M_REG_NUM_BANKS];
34
uint32_t aircr; /* only holds r/w state if security extn implemented */
35
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
36
+ uint32_t csselr[M_REG_NUM_BANKS];
37
} v7m;
38
39
/* Information associated with an exception about to be taken:
40
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
41
FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
42
FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
43
44
+/* v7M CLIDR bits */
45
+FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
46
+FIELD(V7M_CLIDR, LOUIS, 21, 3)
47
+FIELD(V7M_CLIDR, LOC, 24, 3)
48
+FIELD(V7M_CLIDR, LOUU, 27, 3)
49
+FIELD(V7M_CLIDR, ICB, 30, 2)
50
+
51
+FIELD(V7M_CSSELR, IND, 0, 1)
52
+FIELD(V7M_CSSELR, LEVEL, 1, 3)
53
+/* We use the combination of InD and Level to index into cpu->ccsidr[];
54
+ * define a mask for this and check that it doesn't permit running off
55
+ * the end of the array.
56
+ */
57
+FIELD(V7M_CSSELR, INDEX, 0, 4)
58
+
59
+QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
60
+
61
/* If adding a feature bit which corresponds to a Linux ELF
62
* HWCAP bit, remember to update the feature-bit-to-hwcap
63
* mapping in linux-user/elfload.c:get_elf_hwcap().
64
@@ -XXX,XX +XXX,XX @@ static inline int arm_debug_target_el(CPUARMState *env)
65
}
66
}
67
68
+static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
69
+{
70
+ /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
71
+ * CSSELR is RAZ/WI.
72
+ */
73
+ return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
74
+}
75
+
76
static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
77
{
78
if (arm_is_secure(env)) {
79
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/intc/armv7m_nvic.c
82
+++ b/hw/intc/armv7m_nvic.c
83
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
84
return cpu->id_isar4;
85
case 0xd74: /* ISAR5. */
86
return cpu->id_isar5;
87
+ case 0xd78: /* CLIDR */
88
+ return cpu->clidr;
89
+ case 0xd7c: /* CTR */
90
+ return cpu->ctr;
91
+ case 0xd80: /* CSSIDR */
92
+ {
93
+ int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK;
94
+ return cpu->ccsidr[idx];
95
+ }
96
+ case 0xd84: /* CSSELR */
97
+ return cpu->env.v7m.csselr[attrs.secure];
98
/* TODO: Implement debug registers. */
99
case 0xd90: /* MPU_TYPE */
100
/* Unified MPU; if the MPU is not present this value is zero */
101
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
102
qemu_log_mask(LOG_UNIMP,
103
"NVIC: Aux fault status registers unimplemented\n");
104
break;
105
+ case 0xd84: /* CSSELR */
106
+ if (!arm_v7m_csselr_razwi(cpu)) {
107
+ cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK;
108
+ }
109
+ break;
110
case 0xd90: /* MPU_TYPE */
111
return; /* RO */
112
case 0xd94: /* MPU_CTRL */
113
diff --git a/target/arm/machine.c b/target/arm/machine.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/machine.c
116
+++ b/target/arm/machine.c
117
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = {
118
}
119
};
120
121
+/* CSSELR is in a subsection because we didn't implement it previously.
122
+ * Migration from an old implementation will leave it at zero, which
123
+ * is OK since the only CPUs in the old implementation make the
124
+ * register RAZ/WI.
125
+ * Since there was no version of QEMU which implemented the CSSELR for
126
+ * just non-secure, we transfer both banks here rather than putting
127
+ * the secure banked version in the m-security subsection.
128
+ */
129
+static bool csselr_vmstate_validate(void *opaque, int version_id)
130
+{
131
+ ARMCPU *cpu = opaque;
132
+
133
+ return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK
134
+ && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK;
135
+}
136
+
137
+static bool m_csselr_needed(void *opaque)
138
+{
139
+ ARMCPU *cpu = opaque;
140
+
141
+ return !arm_v7m_csselr_razwi(cpu);
142
+}
143
+
144
+static const VMStateDescription vmstate_m_csselr = {
145
+ .name = "cpu/m/csselr",
146
+ .version_id = 1,
147
+ .minimum_version_id = 1,
148
+ .needed = m_csselr_needed,
149
+ .fields = (VMStateField[]) {
150
+ VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
151
+ VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate),
152
+ VMSTATE_END_OF_LIST()
153
+ }
154
+};
155
+
156
static const VMStateDescription vmstate_m = {
157
.name = "cpu/m",
158
.version_id = 4,
159
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
160
},
161
.subsections = (const VMStateDescription*[]) {
162
&vmstate_m_faultmask_primask,
163
+ &vmstate_m_csselr,
164
NULL
165
}
166
};
167
--
168
2.16.1
169
170
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/20] hw/intc/armv7m_nvic: Implement SCR
Deleted patch
1
We were previously making the system control register (SCR)
2
just RAZ/WI. Although we don't implement the functionality
3
this register controls, we should at least provide the state,
4
including the banked state for v8M.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
9
---
10
target/arm/cpu.h | 7 +++++++
11
hw/intc/armv7m_nvic.c | 12 ++++++++----
12
target/arm/machine.c | 12 ++++++++++++
13
3 files changed, 27 insertions(+), 4 deletions(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
20
uint32_t aircr; /* only holds r/w state if security extn implemented */
21
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
22
uint32_t csselr[M_REG_NUM_BANKS];
23
+ uint32_t scr[M_REG_NUM_BANKS];
24
} v7m;
25
26
/* Information associated with an exception about to be taken:
27
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
28
FIELD(V7M_CCR, DC, 16, 1)
29
FIELD(V7M_CCR, IC, 17, 1)
30
31
+/* V7M SCR bits */
32
+FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
33
+FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
34
+FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
35
+FIELD(V7M_SCR, SEVONPEND, 4, 1)
36
+
37
/* V7M AIRCR bits */
38
FIELD(V7M_AIRCR, VECTRESET, 0, 1)
39
FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
40
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/intc/armv7m_nvic.c
43
+++ b/hw/intc/armv7m_nvic.c
44
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
45
}
46
return val;
47
case 0xd10: /* System Control. */
48
- /* TODO: Implement SLEEPONEXIT. */
49
- return 0;
50
+ return cpu->env.v7m.scr[attrs.secure];
51
case 0xd14: /* Configuration Control. */
52
/* The BFHFNMIGN bit is the only non-banked bit; we
53
* keep it in the non-secure copy of the register.
54
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
55
}
56
break;
57
case 0xd10: /* System Control. */
58
- /* TODO: Implement control registers. */
59
- qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n");
60
+ /* We don't implement deep-sleep so these bits are RAZ/WI.
61
+ * The other bits in the register are banked.
62
+ * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which
63
+ * is architecturally permitted.
64
+ */
65
+ value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK);
66
+ cpu->env.v7m.scr[attrs.secure] = value;
67
break;
68
case 0xd14: /* Configuration Control. */
69
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
70
diff --git a/target/arm/machine.c b/target/arm/machine.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/target/arm/machine.c
73
+++ b/target/arm/machine.c
74
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_csselr = {
75
}
76
};
77
78
+static const VMStateDescription vmstate_m_scr = {
79
+ .name = "cpu/m/scr",
80
+ .version_id = 1,
81
+ .minimum_version_id = 1,
82
+ .fields = (VMStateField[]) {
83
+ VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU),
84
+ VMSTATE_END_OF_LIST()
85
+ }
86
+};
87
+
88
static const VMStateDescription vmstate_m = {
89
.name = "cpu/m",
90
.version_id = 4,
91
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
92
.subsections = (const VMStateDescription*[]) {
93
&vmstate_m_faultmask_primask,
94
&vmstate_m_csselr,
95
+ &vmstate_m_scr,
96
NULL
97
}
98
};
99
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
100
VMSTATE_UINT32(env.sau.rnr, ARMCPU),
101
VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),
102
VMSTATE_UINT32(env.sau.ctrl, ARMCPU),
103
+ VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),
104
VMSTATE_END_OF_LIST()
105
}
106
};
107
--
108
2.16.1
109
110
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/20] target/arm: Implement writing to CONTROL_NS for v8M
Deleted patch
1
In commit 50f11062d4c896 we added support for MSR/MRS access
2
to the NS banked special registers, but we forgot to implement
3
the support for writing to CONTROL_NS. Correct the omission.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180209165810.6668-8-peter.maydell@linaro.org
8
---
9
target/arm/helper.c | 10 ++++++++++
10
1 file changed, 10 insertions(+)
11
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.c
15
+++ b/target/arm/helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
17
}
18
env->v7m.faultmask[M_REG_NS] = val & 1;
19
return;
20
+ case 0x94: /* CONTROL_NS */
21
+ if (!env->v7m.secure) {
22
+ return;
23
+ }
24
+ write_v7m_control_spsel_for_secstate(env,
25
+ val & R_V7M_CONTROL_SPSEL_MASK,
26
+ M_REG_NS);
27
+ env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
28
+ env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
29
+ return;
30
case 0x98: /* SP_NS */
31
{
32
/* This gives the non-secure SP selected based on whether we're
33
--
34
2.16.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions
Deleted patch
1
In many of the NVIC registers relating to interrupts, we
2
have to convert from a byte offset within a register set
3
into the number of the first interrupt which is affected.
4
We were getting this wrong for:
5
* reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>,
6
NVIC_IABR<n> -- in all these cases we were missing the "* 8"
7
needed to convert from the byte offset to the interrupt number
8
(since all these registers use one bit per interrupt)
9
* writes of NVIC_IPR<n> had the opposite problem of a spurious
10
"* 8" (since these registers use one byte per interrupt)
11
1
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20180209165810.6668-9-peter.maydell@linaro.org
15
---
16
hw/intc/armv7m_nvic.c | 8 ++++----
17
1 file changed, 4 insertions(+), 4 deletions(-)
18
19
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/armv7m_nvic.c
22
+++ b/hw/intc/armv7m_nvic.c
23
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
24
/* fall through */
25
case 0x180 ... 0x1bf: /* NVIC Clear enable */
26
val = 0;
27
- startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
28
+ startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */
29
30
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
31
if (s->vectors[startvec + i].enabled &&
32
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
33
/* fall through */
34
case 0x280 ... 0x2bf: /* NVIC Clear pend */
35
val = 0;
36
- startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
37
+ startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
38
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
39
if (s->vectors[startvec + i].pending &&
40
(attrs.secure || s->itns[startvec + i])) {
41
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
42
break;
43
case 0x300 ... 0x33f: /* NVIC Active */
44
val = 0;
45
- startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
46
+ startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */
47
48
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
49
if (s->vectors[startvec + i].active &&
50
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
51
case 0x300 ... 0x33f: /* NVIC Active */
52
return MEMTX_OK; /* R/O */
53
case 0x400 ... 0x5ef: /* NVIC Priority */
54
- startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
55
+ startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
56
57
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
58
if (attrs.secure || s->itns[startvec + i]) {
59
--
60
2.16.1
61
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/20] target/arm: Add AIRCR to vmstate struct
Deleted patch
1
In commit commit 3b2e934463121 we added support for the AIRCR
2
register holding state, but forgot to add it to the vmstate
3
structs. Since it only holds r/w state if the security extension
4
is implemented, we can just add it to vmstate_m_security.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180209165810.6668-10-peter.maydell@linaro.org
9
---
10
target/arm/machine.c | 4 ++++
11
1 file changed, 4 insertions(+)
12
13
diff --git a/target/arm/machine.c b/target/arm/machine.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/machine.c
16
+++ b/target/arm/machine.c
17
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
18
VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),
19
VMSTATE_UINT32(env.sau.ctrl, ARMCPU),
20
VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),
21
+ /* AIRCR is not secure-only, but our implementation is R/O if the
22
+ * security extension is unimplemented, so we migrate it here.
23
+ */
24
+ VMSTATE_UINT32(env.v7m.aircr, ARMCPU),
25
VMSTATE_END_OF_LIST()
26
}
27
};
28
--
29
2.16.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/20] target/arm: Migrate v7m.other_sp
Deleted patch
1
In commit abc24d86cc0364f we accidentally broke migration of
2
the stack pointer value for the mode (process, handler) the CPU
3
is not currently running as. (The commit correctly removed the
4
no-longer-used v7m.current_sp flag from the VMState but also
5
deleted the still very much in use v7m.other_sp SP value field.)
6
1
7
Add a subsection to migrate it again. (We don't need to care
8
about trying to retain compatibility with pre-abc24d86cc0364f
9
versions of QEMU, because that commit bumped the version_id
10
and we've since bumped it again a couple of times.)
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20180209165810.6668-11-peter.maydell@linaro.org
15
---
16
target/arm/machine.c | 11 +++++++++++
17
1 file changed, 11 insertions(+)
18
19
diff --git a/target/arm/machine.c b/target/arm/machine.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/machine.c
22
+++ b/target/arm/machine.c
23
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_scr = {
24
}
25
};
26
27
+static const VMStateDescription vmstate_m_other_sp = {
28
+ .name = "cpu/m/other-sp",
29
+ .version_id = 1,
30
+ .minimum_version_id = 1,
31
+ .fields = (VMStateField[]) {
32
+ VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
33
+ VMSTATE_END_OF_LIST()
34
+ }
35
+};
36
+
37
static const VMStateDescription vmstate_m = {
38
.name = "cpu/m",
39
.version_id = 4,
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
41
&vmstate_m_faultmask_primask,
42
&vmstate_m_csselr,
43
&vmstate_m_scr,
44
+ &vmstate_m_other_sp,
45
NULL
46
}
47
};
48
--
49
2.16.1
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/20] target/arm: Implement v8M MSPLIM and PSPLIM registers
Deleted patch
1
The v8M architecture includes hardware support for enforcing
2
stack pointer limits. We don't implement this behaviour yet,
3
but provide the MSPLIM and PSPLIM stack pointer limit registers
4
as reads-as-written, so that when we do implement the checks
5
in future this won't break guest migration.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180209165810.6668-12-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 2 ++
12
target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
13
target/arm/machine.c | 21 +++++++++++++++++++++
14
3 files changed, 69 insertions(+)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
21
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
22
uint32_t csselr[M_REG_NUM_BANKS];
23
uint32_t scr[M_REG_NUM_BANKS];
24
+ uint32_t msplim[M_REG_NUM_BANKS];
25
+ uint32_t psplim[M_REG_NUM_BANKS];
26
} v7m;
27
28
/* Information associated with an exception about to be taken:
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper.c
32
+++ b/target/arm/helper.c
33
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
34
return 0;
35
}
36
return env->v7m.other_ss_psp;
37
+ case 0x8a: /* MSPLIM_NS */
38
+ if (!env->v7m.secure) {
39
+ return 0;
40
+ }
41
+ return env->v7m.msplim[M_REG_NS];
42
+ case 0x8b: /* PSPLIM_NS */
43
+ if (!env->v7m.secure) {
44
+ return 0;
45
+ }
46
+ return env->v7m.psplim[M_REG_NS];
47
case 0x90: /* PRIMASK_NS */
48
if (!env->v7m.secure) {
49
return 0;
50
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
51
return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13];
52
case 9: /* PSP */
53
return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp;
54
+ case 10: /* MSPLIM */
55
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
56
+ goto bad_reg;
57
+ }
58
+ return env->v7m.msplim[env->v7m.secure];
59
+ case 11: /* PSPLIM */
60
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
61
+ goto bad_reg;
62
+ }
63
+ return env->v7m.psplim[env->v7m.secure];
64
case 16: /* PRIMASK */
65
return env->v7m.primask[env->v7m.secure];
66
case 17: /* BASEPRI */
67
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
68
case 19: /* FAULTMASK */
69
return env->v7m.faultmask[env->v7m.secure];
70
default:
71
+ bad_reg:
72
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"
73
" register %d\n", reg);
74
return 0;
75
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
76
}
77
env->v7m.other_ss_psp = val;
78
return;
79
+ case 0x8a: /* MSPLIM_NS */
80
+ if (!env->v7m.secure) {
81
+ return;
82
+ }
83
+ env->v7m.msplim[M_REG_NS] = val & ~7;
84
+ return;
85
+ case 0x8b: /* PSPLIM_NS */
86
+ if (!env->v7m.secure) {
87
+ return;
88
+ }
89
+ env->v7m.psplim[M_REG_NS] = val & ~7;
90
+ return;
91
case 0x90: /* PRIMASK_NS */
92
if (!env->v7m.secure) {
93
return;
94
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
95
env->v7m.other_sp = val;
96
}
97
break;
98
+ case 10: /* MSPLIM */
99
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
100
+ goto bad_reg;
101
+ }
102
+ env->v7m.msplim[env->v7m.secure] = val & ~7;
103
+ break;
104
+ case 11: /* PSPLIM */
105
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
106
+ goto bad_reg;
107
+ }
108
+ env->v7m.psplim[env->v7m.secure] = val & ~7;
109
+ break;
110
case 16: /* PRIMASK */
111
env->v7m.primask[env->v7m.secure] = val & 1;
112
break;
113
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
114
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
115
break;
116
default:
117
+ bad_reg:
118
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
119
" register %d\n", reg);
120
return;
121
diff --git a/target/arm/machine.c b/target/arm/machine.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/machine.c
124
+++ b/target/arm/machine.c
125
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_other_sp = {
126
}
127
};
128
129
+static bool m_v8m_needed(void *opaque)
130
+{
131
+ ARMCPU *cpu = opaque;
132
+ CPUARMState *env = &cpu->env;
133
+
134
+ return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8);
135
+}
136
+
137
+static const VMStateDescription vmstate_m_v8m = {
138
+ .name = "cpu/m/v8m",
139
+ .version_id = 1,
140
+ .minimum_version_id = 1,
141
+ .needed = m_v8m_needed,
142
+ .fields = (VMStateField[]) {
143
+ VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
144
+ VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
145
+ VMSTATE_END_OF_LIST()
146
+ }
147
+};
148
+
149
static const VMStateDescription vmstate_m = {
150
.name = "cpu/m",
151
.version_id = 4,
152
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
153
&vmstate_m_csselr,
154
&vmstate_m_scr,
155
&vmstate_m_other_sp,
156
+ &vmstate_m_v8m,
157
NULL
158
}
159
};
160
--
161
2.16.1
162
163
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/20] bcm2836: Make CPU type configurable
Deleted patch
1
From: Pekka Enberg <penberg@iki.fi>
2
1
3
This patch adds a "cpu-type" property to BCM2836 SoC in preparation for
4
reusing the code for the Raspberry Pi 3, which has a different processor
5
model.
6
7
Signed-off-by: Pekka Enberg <penberg@iki.fi>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/bcm2836.h | 1 +
12
hw/arm/bcm2836.c | 17 +++++++++--------
13
hw/arm/raspi.c | 3 +++
14
3 files changed, 13 insertions(+), 8 deletions(-)
15
16
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/bcm2836.h
19
+++ b/include/hw/arm/bcm2836.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
21
DeviceState parent_obj;
22
/*< public >*/
23
24
+ char *cpu_type;
25
uint32_t enabled_cpus;
26
27
ARMCPU cpus[BCM2836_NCPUS];
28
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/bcm2836.c
31
+++ b/hw/arm/bcm2836.c
32
@@ -XXX,XX +XXX,XX @@
33
static void bcm2836_init(Object *obj)
34
{
35
BCM2836State *s = BCM2836(obj);
36
- int n;
37
-
38
- for (n = 0; n < BCM2836_NCPUS; n++) {
39
- object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
40
- "cortex-a15-" TYPE_ARM_CPU);
41
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
42
- &error_abort);
43
- }
44
45
object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
46
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
47
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
48
49
/* common peripherals from bcm2835 */
50
51
+ obj = OBJECT(dev);
52
+ for (n = 0; n < BCM2836_NCPUS; n++) {
53
+ object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
54
+ s->cpu_type);
55
+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
56
+ &error_abort);
57
+ }
58
+
59
obj = object_property_get_link(OBJECT(dev), "ram", &err);
60
if (obj == NULL) {
61
error_setg(errp, "%s: required ram link not found: %s",
62
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
63
}
64
65
static Property bcm2836_props[] = {
66
+ DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
67
DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
68
DEFINE_PROP_END_OF_LIST()
69
};
70
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/raspi.c
73
+++ b/hw/arm/raspi.c
74
@@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine)
75
/* Setup the SOC */
76
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
77
&error_abort);
78
+ object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
79
+ &error_abort);
80
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
81
&error_abort);
82
object_property_set_int(OBJECT(&s->soc), 0xa21041, "board-rev",
83
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
84
mc->no_parallel = 1;
85
mc->no_floppy = 1;
86
mc->no_cdrom = 1;
87
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
88
mc->max_cpus = BCM2836_NCPUS;
89
mc->min_cpus = BCM2836_NCPUS;
90
mc->default_cpus = BCM2836_NCPUS;
91
--
92
2.16.1
93
94
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/20] raspi: Raspberry Pi 3 support
Deleted patch
1
From: Pekka Enberg <penberg@iki.fi>
2
1
3
This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The
4
differences to Pi 2 are:
5
6
- Firmware address
7
- Board ID
8
- Board revision
9
10
The CPU is different too, but that's going to be configured as part of
11
the machine default CPU when we introduce a new machine type.
12
13
The patch was written from scratch by me but the logic is similar to
14
Zoltán Baldaszti's previous work, which I used as a reference (with
15
permission from the author):
16
17
https://github.com/bztsrc/qemu-raspi3
18
19
Signed-off-by: Pekka Enberg <penberg@iki.fi>
20
[PMM: fixed trailing whitespace on one line]
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
24
hw/arm/raspi.c | 31 +++++++++++++++++++++----------
25
1 file changed, 21 insertions(+), 10 deletions(-)
26
27
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/raspi.c
30
+++ b/hw/arm/raspi.c
31
@@ -XXX,XX +XXX,XX @@
32
* Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
33
* Written by Andrew Baumann
34
*
35
+ * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
36
+ * Upstream code cleanup (c) 2018 Pekka Enberg
37
+ *
38
* This code is licensed under the GNU GPLv2 and later.
39
*/
40
41
@@ -XXX,XX +XXX,XX @@
42
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
43
#define MVBAR_ADDR 0x400 /* secure vectors */
44
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
45
-#define FIRMWARE_ADDR 0x8000 /* Pi loads kernel.img here by default */
46
+#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
47
+#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
48
49
/* Table of Linux board IDs for different Pi versions */
50
-static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43};
51
+static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
52
53
typedef struct RasPiState {
54
BCM2836State soc;
55
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
56
binfo.secure_board_setup = true;
57
binfo.secure_boot = true;
58
59
- /* Pi2 requires SMP setup */
60
- if (version == 2) {
61
+ /* Pi2 and Pi3 requires SMP setup */
62
+ if (version >= 2) {
63
binfo.smp_loader_start = SMPBOOT_ADDR;
64
binfo.write_secondary_boot = write_smpboot;
65
binfo.secondary_cpu_reset_hook = reset_secondary;
66
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
67
* the normal Linux boot process
68
*/
69
if (machine->firmware) {
70
+ hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
71
/* load the firmware image (typically kernel.img) */
72
- r = load_image_targphys(machine->firmware, FIRMWARE_ADDR,
73
- ram_size - FIRMWARE_ADDR);
74
+ r = load_image_targphys(machine->firmware, firmware_addr,
75
+ ram_size - firmware_addr);
76
if (r < 0) {
77
error_report("Failed to load firmware from %s", machine->firmware);
78
exit(1);
79
}
80
81
- binfo.entry = FIRMWARE_ADDR;
82
+ binfo.entry = firmware_addr;
83
binfo.firmware_loaded = true;
84
} else {
85
binfo.kernel_filename = machine->kernel_filename;
86
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
87
arm_load_kernel(ARM_CPU(first_cpu), &binfo);
88
}
89
90
-static void raspi2_init(MachineState *machine)
91
+static void raspi_init(MachineState *machine, int version)
92
{
93
RasPiState *s = g_new0(RasPiState, 1);
94
uint32_t vcram_size;
95
@@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine)
96
&error_abort);
97
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
98
&error_abort);
99
- object_property_set_int(OBJECT(&s->soc), 0xa21041, "board-rev",
100
+ int board_rev = version == 3 ? 0xa02082 : 0xa21041;
101
+ object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
102
&error_abort);
103
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);
104
105
@@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine)
106
107
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
108
&error_abort);
109
- setup_boot(machine, 2, machine->ram_size - vcram_size);
110
+ setup_boot(machine, version, machine->ram_size - vcram_size);
111
+}
112
+
113
+static void raspi2_init(MachineState *machine)
114
+{
115
+ raspi_init(machine, 2);
116
}
117
118
static void raspi2_machine_init(MachineClass *mc)
119
--
120
2.16.1
121
122
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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