1 | target-arm queue: mostly just cleanup/minor stuff, but this does | 1 | The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae: |
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2 | include the raspi3 board model. | ||
3 | 2 | ||
4 | -- PMM | 3 | Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000) |
5 | |||
6 | The following changes since commit 9f9c53368b219a9115eddb39f0ff5ad19c977134: | ||
7 | |||
8 | Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging (2018-02-15 10:14:11 +0000) | ||
9 | 4 | ||
10 | are available in the Git repository at: | 5 | are available in the Git repository at: |
11 | 6 | ||
12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180215 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215 |
13 | 8 | ||
14 | for you to fetch changes up to e545f0f9be1f9e60951017c1e6558216732cc14e: | 9 | for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2: |
15 | 10 | ||
16 | target/arm: Implement v8M MSPLIM and PSPLIM registers (2018-02-15 13:48:11 +0000) | 11 | docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000) |
17 | 12 | ||
18 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
19 | target-arm queue: | 14 | target-arm queue: |
20 | * aspeed: code cleanup to use unimplemented_device | 15 | * hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC |
21 | * add 'raspi3' RaspberryPi 3 machine model | 16 | * linux-user/aarch64: Choose SYNC as the preferred MTE mode |
22 | * more SVE prep work | 17 | * Fix some errors in SVE/SME handling of MTE tags |
23 | * v8M: add minor missing registers | 18 | * hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses |
24 | * v7M: fix bug where we weren't migrating v7m.other_sp | 19 | * hw/block/tc58128: Don't emit deprecation warning under qtest |
25 | * v7M: fix bugs in handling of interrupt registers for | 20 | * tests/qtest: Fix handling of npcm7xx and GMAC tests |
26 | external interrupts beyond 32 | 21 | * hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ |
22 | * tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend | ||
23 | * Don't assert on vmload/vmsave of M-profile CPUs | ||
24 | * hw/arm/smmuv3: add support for stage 1 access fault | ||
25 | * hw/arm/stellaris: QOM cleanups | ||
26 | * Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs | ||
27 | * Improve Cortex_R52 IMPDEF sysreg modelling | ||
28 | * Allow access to SPSR_hyp from hyp mode | ||
29 | * New board model mps3-an536 (Cortex-R52) | ||
27 | 30 | ||
28 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
29 | Pekka Enberg (3): | 32 | Luc Michel (1): |
30 | bcm2836: Make CPU type configurable | 33 | hw/arm/smmuv3: add support for stage 1 access fault |
31 | raspi: Raspberry Pi 3 support | ||
32 | raspi: Add "raspi3" machine type | ||
33 | 34 | ||
34 | Peter Maydell (11): | 35 | Nabih Estefan (1): |
35 | hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC | 36 | tests/qtest: Fix GMAC test to run on a machine in upstream QEMU |
36 | hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling | ||
37 | hw/intc/armv7m_nvic: Implement M profile cache maintenance ops | ||
38 | hw/intc/armv7m_nvic: Implement v8M CPPWR register | ||
39 | hw/intc/armv7m_nvic: Implement cache ID registers | ||
40 | hw/intc/armv7m_nvic: Implement SCR | ||
41 | target/arm: Implement writing to CONTROL_NS for v8M | ||
42 | hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions | ||
43 | target/arm: Add AIRCR to vmstate struct | ||
44 | target/arm: Migrate v7m.other_sp | ||
45 | target/arm: Implement v8M MSPLIM and PSPLIM registers | ||
46 | 37 | ||
47 | Philippe Mathieu-Daudé (2): | 38 | Peter Maydell (22): |
48 | hw/arm/aspeed: directly map the serial device to the system address space | 39 | hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses |
49 | hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io | 40 | hw/block/tc58128: Don't emit deprecation warning under qtest |
41 | tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64 | ||
42 | tests/qtest/bios-tables-test: Allow changes to virt GTDT | ||
43 | hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ | ||
44 | tests/qtest/bios-tables-tests: Update virt golden reference | ||
45 | hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules | ||
46 | tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend | ||
47 | target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU | ||
48 | target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs | ||
49 | target/arm: The Cortex-R52 has a read-only CBAR | ||
50 | target/arm: Add Cortex-R52 IMPDEF sysregs | ||
51 | target/arm: Allow access to SPSR_hyp from hyp mode | ||
52 | hw/misc/mps2-scc: Fix condition for CFG3 register | ||
53 | hw/misc/mps2-scc: Factor out which-board conditionals | ||
54 | hw/misc/mps2-scc: Make changes needed for AN536 FPGA image | ||
55 | hw/arm/mps3r: Initial skeleton for mps3-an536 board | ||
56 | hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM | ||
57 | hw/arm/mps3r: Add UARTs | ||
58 | hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices | ||
59 | hw/arm/mps3r: Add remaining devices | ||
60 | docs: Add documentation for the mps3-an536 board | ||
50 | 61 | ||
51 | Richard Henderson (5): | 62 | Philippe Mathieu-Daudé (5): |
52 | target/arm: Remove ARM_CP_64BIT from ZCR_EL registers | 63 | hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC |
53 | target/arm: Enforce FP access to FPCR/FPSR | 64 | hw/arm/stellaris: Convert ADC controller to Resettable interface |
54 | target/arm: Suppress TB end for FPCR/FPSR | 65 | hw/arm/stellaris: Convert I2C controller to Resettable interface |
55 | target/arm: Enforce access to ZCR_EL at translation | 66 | hw/arm/stellaris: Add missing QOM 'machine' parent |
56 | target/arm: Handle SVE registers when using clear_vec_high | 67 | hw/arm/stellaris: Add missing QOM 'SoC' parent |
57 | 68 | ||
58 | include/hw/arm/aspeed_soc.h | 1 - | 69 | Richard Henderson (6): |
59 | include/hw/arm/bcm2836.h | 1 + | 70 | linux-user/aarch64: Choose SYNC as the preferred MTE mode |
60 | target/arm/cpu.h | 71 ++++++++++++----- | 71 | target/arm: Fix nregs computation in do_{ld,st}_zpa |
61 | target/arm/internals.h | 6 ++ | 72 | target/arm: Adjust and validate mtedesc sizem1 |
62 | hw/arm/aspeed_soc.c | 35 ++------- | 73 | target/arm: Split out make_svemte_desc |
63 | hw/arm/bcm2836.c | 17 +++-- | 74 | target/arm: Handle mte in do_ldrq, do_ldro |
64 | hw/arm/raspi.c | 57 +++++++++++--- | 75 | target/arm: Fix SVE/SME gross MTE suppression checks |
65 | hw/intc/armv7m_nvic.c | 98 ++++++++++++++++++------ | ||
66 | target/arm/cpu.c | 28 +++++++ | ||
67 | target/arm/helper.c | 84 +++++++++++++++----- | ||
68 | target/arm/machine.c | 84 ++++++++++++++++++++ | ||
69 | target/arm/translate-a64.c | 181 ++++++++++++++++++++------------------------ | ||
70 | 12 files changed, 452 insertions(+), 211 deletions(-) | ||
71 | 76 | ||
77 | MAINTAINERS | 3 +- | ||
78 | docs/system/arm/mps2.rst | 37 +- | ||
79 | configs/devices/arm-softmmu/default.mak | 1 + | ||
80 | hw/arm/smmuv3-internal.h | 1 + | ||
81 | include/hw/arm/smmu-common.h | 1 + | ||
82 | include/hw/arm/virt.h | 2 + | ||
83 | include/hw/misc/mps2-scc.h | 1 + | ||
84 | linux-user/aarch64/target_prctl.h | 29 +- | ||
85 | target/arm/internals.h | 2 +- | ||
86 | target/arm/tcg/translate-a64.h | 2 + | ||
87 | hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++ | ||
88 | hw/arm/npcm7xx.c | 1 + | ||
89 | hw/arm/smmu-common.c | 11 + | ||
90 | hw/arm/smmuv3.c | 1 + | ||
91 | hw/arm/stellaris.c | 47 ++- | ||
92 | hw/arm/virt-acpi-build.c | 20 +- | ||
93 | hw/arm/virt.c | 60 ++- | ||
94 | hw/arm/xilinx_zynq.c | 2 + | ||
95 | hw/block/tc58128.c | 4 +- | ||
96 | hw/misc/mps2-scc.c | 138 ++++++- | ||
97 | hw/pci-host/raven.c | 1 + | ||
98 | target/arm/helper.c | 14 +- | ||
99 | target/arm/tcg/cpu32.c | 109 ++++++ | ||
100 | target/arm/tcg/op_helper.c | 43 ++- | ||
101 | target/arm/tcg/sme_helper.c | 8 +- | ||
102 | target/arm/tcg/sve_helper.c | 12 +- | ||
103 | target/arm/tcg/translate-sme.c | 15 +- | ||
104 | target/arm/tcg/translate-sve.c | 83 +++-- | ||
105 | target/arm/tcg/translate.c | 19 +- | ||
106 | tests/qtest/npcm7xx_emc-test.c | 5 +- | ||
107 | tests/qtest/npcm_gmac-test.c | 84 +---- | ||
108 | hw/arm/Kconfig | 5 + | ||
109 | hw/arm/meson.build | 1 + | ||
110 | tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes | ||
111 | tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes | ||
112 | tests/qtest/meson.build | 4 +- | ||
113 | 36 files changed, 1184 insertions(+), 222 deletions(-) | ||
114 | create mode 100644 hw/arm/mps3r.c | ||
115 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Nothing in either register affects the TB. | 3 | Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards, |
4 | connect FIQ output of the GIC CPU interfaces to the CPU. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
6 | Message-id: 20180211205848.4568-4-richard.henderson@linaro.org | 7 | Message-id: 20240130152548.17855-1-philmd@linaro.org |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/helper.c | 4 ++-- | 11 | hw/arm/xilinx_zynq.c | 2 ++ |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 2 insertions(+) |
12 | 13 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 16 | --- a/hw/arm/xilinx_zynq.c |
16 | +++ b/target/arm/helper.c | 17 | +++ b/hw/arm/xilinx_zynq.c |
17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 18 | @@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine) |
18 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | 19 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
19 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, | 20 | sysbus_connect_irq(busdev, 0, |
20 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | 21 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
21 | - .access = PL0_RW, .type = ARM_CP_FPU, | 22 | + sysbus_connect_irq(busdev, 1, |
22 | + .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, | 23 | + qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ)); |
23 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | 24 | |
24 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | 25 | for (n = 0; n < 64; n++) { |
25 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | 26 | pic[n] = qdev_get_gpio_in(dev, n); |
26 | - .access = PL0_RW, .type = ARM_CP_FPU, | ||
27 | + .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, | ||
28 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | ||
29 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, | ||
30 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | ||
31 | -- | 27 | -- |
32 | 2.16.1 | 28 | 2.34.1 |
33 | 29 | ||
34 | 30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | The API does not generate an error for setting ASYNC | SYNC; that merely | ||
4 | constrains the selection vs the per-cpu default. For qemu linux-user, | ||
5 | choose SYNC as the default. | ||
6 | |||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Reported-by: Gustavo Romero <gustavo.romero@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> | ||
11 | Message-id: 20240207025210.8837-2-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------ | ||
15 | 1 file changed, 17 insertions(+), 12 deletions(-) | ||
16 | |||
17 | diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/linux-user/aarch64/target_prctl.h | ||
20 | +++ b/linux-user/aarch64/target_prctl.h | ||
21 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) | ||
22 | env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; | ||
23 | |||
24 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
25 | - switch (arg2 & PR_MTE_TCF_MASK) { | ||
26 | - case PR_MTE_TCF_NONE: | ||
27 | - case PR_MTE_TCF_SYNC: | ||
28 | - case PR_MTE_TCF_ASYNC: | ||
29 | - break; | ||
30 | - default: | ||
31 | - return -EINVAL; | ||
32 | - } | ||
33 | - | ||
34 | /* | ||
35 | * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. | ||
36 | - * Note that the syscall values are consistent with hw. | ||
37 | + * | ||
38 | + * The kernel has a per-cpu configuration for the sysadmin, | ||
39 | + * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred, | ||
40 | + * which qemu does not implement. | ||
41 | + * | ||
42 | + * Because there is no performance difference between the modes, and | ||
43 | + * because SYNC is most useful for debugging MTE errors, choose SYNC | ||
44 | + * as the preferred mode. With this preference, and the way the API | ||
45 | + * uses only two bits, there is no way for the program to select | ||
46 | + * ASYMM mode. | ||
47 | */ | ||
48 | - env->cp15.sctlr_el[1] = | ||
49 | - deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT); | ||
50 | + unsigned tcf = 0; | ||
51 | + if (arg2 & PR_MTE_TCF_SYNC) { | ||
52 | + tcf = 1; | ||
53 | + } else if (arg2 & PR_MTE_TCF_ASYNC) { | ||
54 | + tcf = 2; | ||
55 | + } | ||
56 | + env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); | ||
57 | |||
58 | /* | ||
59 | * Write PR_MTE_TAG to GCR_EL1[Exclude]. | ||
60 | -- | ||
61 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The field is encoded as [0-3], which is convenient for | ||
4 | indexing our array of function pointers, but the true | ||
5 | value is [1-4]. Adjust before calling do_mem_zpa. | ||
6 | |||
7 | Add an assert, and move the comment re passing ZT to | ||
8 | the helper back next to the relevant code. | ||
9 | |||
10 | Cc: qemu-stable@nongnu.org | ||
11 | Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads") | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Message-id: 20180211205848.4568-3-richard.henderson@linaro.org | 13 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
14 | Message-id: 20240207025210.8837-3-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 17 | --- |
8 | target/arm/cpu.h | 35 ++++++++++++++++++----------------- | 18 | target/arm/tcg/translate-sve.c | 16 ++++++++-------- |
9 | target/arm/helper.c | 6 ++++-- | 19 | 1 file changed, 8 insertions(+), 8 deletions(-) |
10 | target/arm/translate-a64.c | 3 +++ | ||
11 | 3 files changed, 25 insertions(+), 19 deletions(-) | ||
12 | 20 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 21 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c |
14 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 23 | --- a/target/arm/tcg/translate-sve.c |
16 | +++ b/target/arm/cpu.h | 24 | +++ b/target/arm/tcg/translate-sve.c |
17 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | 25 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
26 | TCGv_ptr t_pg; | ||
27 | int desc = 0; | ||
28 | |||
29 | - /* | ||
30 | - * For e.g. LD4, there are not enough arguments to pass all 4 | ||
31 | - * registers as pointers, so encode the regno into the data field. | ||
32 | - * For consistency, do this even for LD1. | ||
33 | - */ | ||
34 | + assert(mte_n >= 1 && mte_n <= 4); | ||
35 | if (s->mte_active[0]) { | ||
36 | int msz = dtype_msz(dtype); | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
39 | addr = clean_data_tbi(s, addr); | ||
40 | } | ||
41 | |||
42 | + /* | ||
43 | + * For e.g. LD4, there are not enough arguments to pass all 4 | ||
44 | + * registers as pointers, so encode the regno into the data field. | ||
45 | + * For consistency, do this even for LD1. | ||
46 | + */ | ||
47 | desc = simd_desc(vsz, vsz, zt | desc); | ||
48 | t_pg = tcg_temp_new_ptr(); | ||
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg, | ||
51 | * accessible via the instruction encoding. | ||
52 | */ | ||
53 | assert(fn != NULL); | ||
54 | - do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); | ||
55 | + do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn); | ||
18 | } | 56 | } |
19 | 57 | ||
20 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a | 58 | static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) |
21 | - * special-behaviour cp reg and bits [15..8] indicate what behaviour | 59 | @@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
22 | + * special-behaviour cp reg and bits [11..8] indicate what behaviour | 60 | if (nreg == 0) { |
23 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | 61 | /* ST1 */ |
24 | * TCG can assume the value to be constant (ie load at translate time) | 62 | fn = fn_single[s->mte_active[0]][be][msz][esz]; |
25 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | 63 | - nreg = 1; |
26 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | 64 | } else { |
27 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | 65 | /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */ |
28 | * registers which implement clocks or timers require this. | 66 | assert(msz == esz); |
29 | */ | 67 | fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; |
30 | -#define ARM_CP_SPECIAL 1 | ||
31 | -#define ARM_CP_CONST 2 | ||
32 | -#define ARM_CP_64BIT 4 | ||
33 | -#define ARM_CP_SUPPRESS_TB_END 8 | ||
34 | -#define ARM_CP_OVERRIDE 16 | ||
35 | -#define ARM_CP_ALIAS 32 | ||
36 | -#define ARM_CP_IO 64 | ||
37 | -#define ARM_CP_NO_RAW 128 | ||
38 | -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) | ||
39 | -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | ||
40 | -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) | ||
41 | -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) | ||
42 | -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) | ||
43 | -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA | ||
44 | +#define ARM_CP_SPECIAL 0x0001 | ||
45 | +#define ARM_CP_CONST 0x0002 | ||
46 | +#define ARM_CP_64BIT 0x0004 | ||
47 | +#define ARM_CP_SUPPRESS_TB_END 0x0008 | ||
48 | +#define ARM_CP_OVERRIDE 0x0010 | ||
49 | +#define ARM_CP_ALIAS 0x0020 | ||
50 | +#define ARM_CP_IO 0x0040 | ||
51 | +#define ARM_CP_NO_RAW 0x0080 | ||
52 | +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | ||
53 | +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | ||
54 | +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | ||
55 | +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | ||
56 | +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
57 | +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA | ||
58 | +#define ARM_CP_FPU 0x1000 | ||
59 | /* Used only as a terminator for ARMCPRegInfo lists */ | ||
60 | -#define ARM_CP_SENTINEL 0xffff | ||
61 | +#define ARM_CP_SENTINEL 0xffff | ||
62 | /* Mask of only the flag bits in a type field */ | ||
63 | -#define ARM_CP_FLAG_MASK 0xff | ||
64 | +#define ARM_CP_FLAG_MASK 0x10ff | ||
65 | |||
66 | /* Valid values for ARMCPRegInfo state field, indicating which of | ||
67 | * the AArch32 and AArch64 execution states this register is visible in. | ||
68 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/target/arm/helper.c | ||
71 | +++ b/target/arm/helper.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
73 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | ||
74 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, | ||
75 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | ||
76 | - .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | ||
77 | + .access = PL0_RW, .type = ARM_CP_FPU, | ||
78 | + .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | ||
79 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | ||
80 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | ||
81 | - .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | ||
82 | + .access = PL0_RW, .type = ARM_CP_FPU, | ||
83 | + .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | ||
84 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, | ||
85 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | ||
86 | .access = PL0_R, .type = ARM_CP_NO_RAW, | ||
87 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
88 | index XXXXXXX..XXXXXXX 100644 | ||
89 | --- a/target/arm/translate-a64.c | ||
90 | +++ b/target/arm/translate-a64.c | ||
91 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
92 | default: | ||
93 | break; | ||
94 | } | 68 | } |
95 | + if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { | 69 | assert(fn != NULL); |
96 | + return; | 70 | - do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); |
97 | + } | 71 | + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn); |
98 | 72 | } | |
99 | if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { | 73 | |
100 | gen_io_start(); | 74 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) |
101 | -- | 75 | -- |
102 | 2.16.1 | 76 | 2.34.1 |
103 | |||
104 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This also makes sure that we get the correct ordering of | 3 | When we added SVE_MTEDESC_SHIFT, we effectively limited the |
4 | SVE vs FP exceptions. | 4 | maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining |
5 | bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored | ||
6 | fits within the field (expecting 8 * 4 - 1 == 31, exact fit). | ||
5 | 7 | ||
8 | Cc: qemu-stable@nongnu.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180211205848.4568-5-richard.henderson@linaro.org | 11 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Message-id: 20240207025210.8837-4-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | target/arm/cpu.h | 3 ++- | 15 | target/arm/internals.h | 2 +- |
12 | target/arm/internals.h | 6 ++++++ | 16 | target/arm/tcg/translate-sve.c | 7 ++++--- |
13 | target/arm/helper.c | 22 ++++------------------ | 17 | 2 files changed, 5 insertions(+), 4 deletions(-) |
14 | target/arm/translate-a64.c | 16 ++++++++++++++++ | ||
15 | 4 files changed, 28 insertions(+), 19 deletions(-) | ||
16 | 18 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
22 | #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | ||
23 | #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA | ||
24 | #define ARM_CP_FPU 0x1000 | ||
25 | +#define ARM_CP_SVE 0x2000 | ||
26 | /* Used only as a terminator for ARMCPRegInfo lists */ | ||
27 | #define ARM_CP_SENTINEL 0xffff | ||
28 | /* Mask of only the flag bits in a type field */ | ||
29 | -#define ARM_CP_FLAG_MASK 0x10ff | ||
30 | +#define ARM_CP_FLAG_MASK 0x30ff | ||
31 | |||
32 | /* Valid values for ARMCPRegInfo state field, indicating which of | ||
33 | * the AArch32 and AArch64 execution states this register is visible in. | ||
34 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
35 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/target/arm/internals.h | 21 | --- a/target/arm/internals.h |
37 | +++ b/target/arm/internals.h | 22 | +++ b/target/arm/internals.h |
38 | @@ -XXX,XX +XXX,XX @@ enum arm_exception_class { | 23 | @@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2) |
39 | EC_AA64_HVC = 0x16, | 24 | FIELD(MTEDESC, TCMA, 6, 2) |
40 | EC_AA64_SMC = 0x17, | 25 | FIELD(MTEDESC, WRITE, 8, 1) |
41 | EC_SYSTEMREGISTERTRAP = 0x18, | 26 | FIELD(MTEDESC, ALIGN, 9, 3) |
42 | + EC_SVEACCESSTRAP = 0x19, | 27 | -FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */ |
43 | EC_INSNABORT = 0x20, | 28 | +FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */ |
44 | EC_INSNABORT_SAME_EL = 0x21, | 29 | |
45 | EC_PCALIGNMENT = 0x22, | 30 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); |
46 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) | 31 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); |
47 | | (cv << 24) | (cond << 20); | 32 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c |
48 | } | 33 | index XXXXXXX..XXXXXXX 100644 |
49 | 34 | --- a/target/arm/tcg/translate-sve.c | |
50 | +static inline uint32_t syn_sve_access_trap(void) | 35 | +++ b/target/arm/tcg/translate-sve.c |
51 | +{ | 36 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
52 | + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; | ||
53 | +} | ||
54 | + | ||
55 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | ||
56 | { | 37 | { |
57 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | 38 | unsigned vsz = vec_full_reg_size(s); |
58 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 39 | TCGv_ptr t_pg; |
59 | index XXXXXXX..XXXXXXX 100644 | 40 | + uint32_t sizem1; |
60 | --- a/target/arm/helper.c | 41 | int desc = 0; |
61 | +++ b/target/arm/helper.c | 42 | |
62 | @@ -XXX,XX +XXX,XX @@ static int sve_exception_el(CPUARMState *env) | 43 | assert(mte_n >= 1 && mte_n <= 4); |
63 | return 0; | 44 | + sizem1 = (mte_n << dtype_msz(dtype)) - 1; |
64 | } | 45 | + assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT); |
65 | 46 | if (s->mte_active[0]) { | |
66 | -static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri, | 47 | - int msz = dtype_msz(dtype); |
67 | - bool isread) | ||
68 | -{ | ||
69 | - switch (sve_exception_el(env)) { | ||
70 | - case 3: | ||
71 | - return CP_ACCESS_TRAP_EL3; | ||
72 | - case 2: | ||
73 | - return CP_ACCESS_TRAP_EL2; | ||
74 | - case 1: | ||
75 | - return CP_ACCESS_TRAP; | ||
76 | - } | ||
77 | - return CP_ACCESS_OK; | ||
78 | -} | ||
79 | - | 48 | - |
80 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 49 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); |
81 | uint64_t value) | 50 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); |
82 | { | 51 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); |
83 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 52 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); |
84 | static const ARMCPRegInfo zcr_el1_reginfo = { | 53 | - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); |
85 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | 54 | + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1); |
86 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | 55 | desc <<= SVE_MTEDESC_SHIFT; |
87 | - .access = PL1_RW, .accessfn = zcr_access, | 56 | } else { |
88 | + .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU, | 57 | addr = clean_data_tbi(s, addr); |
89 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
90 | .writefn = zcr_write, .raw_writefn = raw_write | ||
91 | }; | ||
92 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el1_reginfo = { | ||
93 | static const ARMCPRegInfo zcr_el2_reginfo = { | ||
94 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
95 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
96 | - .access = PL2_RW, .accessfn = zcr_access, | ||
97 | + .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU, | ||
98 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
99 | .writefn = zcr_write, .raw_writefn = raw_write | ||
100 | }; | ||
101 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el2_reginfo = { | ||
102 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | ||
103 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
104 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
105 | - .access = PL2_RW, | ||
106 | + .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU, | ||
107 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | ||
108 | }; | ||
109 | |||
110 | static const ARMCPRegInfo zcr_el3_reginfo = { | ||
111 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
112 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
113 | - .access = PL3_RW, .accessfn = zcr_access, | ||
114 | + .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU, | ||
115 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
116 | .writefn = zcr_write, .raw_writefn = raw_write | ||
117 | }; | ||
118 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
119 | index XXXXXXX..XXXXXXX 100644 | ||
120 | --- a/target/arm/translate-a64.c | ||
121 | +++ b/target/arm/translate-a64.c | ||
122 | @@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s) | ||
123 | return false; | ||
124 | } | ||
125 | |||
126 | +/* Check that SVE access is enabled. If it is, return true. | ||
127 | + * If not, emit code to generate an appropriate exception and return false. | ||
128 | + */ | ||
129 | +static inline bool sve_access_check(DisasContext *s) | ||
130 | +{ | ||
131 | + if (s->sve_excp_el) { | ||
132 | + gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(), | ||
133 | + s->sve_excp_el); | ||
134 | + return false; | ||
135 | + } | ||
136 | + return true; | ||
137 | +} | ||
138 | + | ||
139 | /* | ||
140 | * This utility function is for doing register extension with an | ||
141 | * optional shift. You will likely want to pass a temporary for the | ||
142 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
143 | default: | ||
144 | break; | ||
145 | } | ||
146 | + if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { | ||
147 | + return; | ||
148 | + } | ||
149 | if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { | ||
150 | return; | ||
151 | } | ||
152 | -- | 58 | -- |
153 | 2.16.1 | 59 | 2.34.1 |
154 | |||
155 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Share code that creates mtedesc and embeds within simd_desc. | ||
4 | |||
5 | Cc: qemu-stable@nongnu.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> | ||
9 | Message-id: 20240207025210.8837-5-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/tcg/translate-a64.h | 2 ++ | ||
13 | target/arm/tcg/translate-sme.c | 15 +++-------- | ||
14 | target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++---------------- | ||
15 | 3 files changed, 31 insertions(+), 33 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/tcg/translate-a64.h | ||
20 | +++ b/target/arm/tcg/translate-a64.h | ||
21 | @@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | ||
22 | bool sve_access_check(DisasContext *s); | ||
23 | bool sme_enabled_check(DisasContext *s); | ||
24 | bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); | ||
25 | +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, | ||
26 | + uint32_t msz, bool is_write, uint32_t data); | ||
27 | |||
28 | /* This function corresponds to CheckStreamingSVEEnabled. */ | ||
29 | static inline bool sme_sm_enabled_check(DisasContext *s) | ||
30 | diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/tcg/translate-sme.c | ||
33 | +++ b/target/arm/tcg/translate-sme.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) | ||
35 | |||
36 | TCGv_ptr t_za, t_pg; | ||
37 | TCGv_i64 addr; | ||
38 | - int svl, desc = 0; | ||
39 | + uint32_t desc; | ||
40 | bool be = s->be_data == MO_BE; | ||
41 | bool mte = s->mte_active[0]; | ||
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) | ||
44 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); | ||
45 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | ||
46 | |||
47 | - if (mte) { | ||
48 | - desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
49 | - desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
50 | - desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
51 | - desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st); | ||
52 | - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); | ||
53 | - desc <<= SVE_MTEDESC_SHIFT; | ||
54 | - } else { | ||
55 | + if (!mte) { | ||
56 | addr = clean_data_tbi(s, addr); | ||
57 | } | ||
58 | - svl = streaming_vec_reg_size(s); | ||
59 | - desc = simd_desc(svl, svl, desc); | ||
60 | + | ||
61 | + desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0); | ||
62 | |||
63 | fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr, | ||
64 | tcg_constant_i32(desc)); | ||
65 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/tcg/translate-sve.c | ||
68 | +++ b/target/arm/tcg/translate-sve.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = { | ||
70 | 3, 2, 1, 3 | ||
71 | }; | ||
72 | |||
73 | -static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
74 | - int dtype, uint32_t mte_n, bool is_write, | ||
75 | - gen_helper_gvec_mem *fn) | ||
76 | +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, | ||
77 | + uint32_t msz, bool is_write, uint32_t data) | ||
78 | { | ||
79 | - unsigned vsz = vec_full_reg_size(s); | ||
80 | - TCGv_ptr t_pg; | ||
81 | uint32_t sizem1; | ||
82 | - int desc = 0; | ||
83 | + uint32_t desc = 0; | ||
84 | |||
85 | - assert(mte_n >= 1 && mte_n <= 4); | ||
86 | - sizem1 = (mte_n << dtype_msz(dtype)) - 1; | ||
87 | + /* Assert all of the data fits, with or without MTE enabled. */ | ||
88 | + assert(nregs >= 1 && nregs <= 4); | ||
89 | + sizem1 = (nregs << msz) - 1; | ||
90 | assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT); | ||
91 | + assert(data < 1u << SVE_MTEDESC_SHIFT); | ||
92 | + | ||
93 | if (s->mte_active[0]) { | ||
94 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
95 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
96 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
97 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
98 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1); | ||
99 | desc <<= SVE_MTEDESC_SHIFT; | ||
100 | - } else { | ||
101 | + } | ||
102 | + return simd_desc(vsz, vsz, desc | data); | ||
103 | +} | ||
104 | + | ||
105 | +static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
106 | + int dtype, uint32_t nregs, bool is_write, | ||
107 | + gen_helper_gvec_mem *fn) | ||
108 | +{ | ||
109 | + TCGv_ptr t_pg; | ||
110 | + uint32_t desc; | ||
111 | + | ||
112 | + if (!s->mte_active[0]) { | ||
113 | addr = clean_data_tbi(s, addr); | ||
114 | } | ||
115 | |||
116 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
117 | * registers as pointers, so encode the regno into the data field. | ||
118 | * For consistency, do this even for LD1. | ||
119 | */ | ||
120 | - desc = simd_desc(vsz, vsz, zt | desc); | ||
121 | + desc = make_svemte_desc(s, vec_full_reg_size(s), nregs, | ||
122 | + dtype_msz(dtype), is_write, zt); | ||
123 | t_pg = tcg_temp_new_ptr(); | ||
124 | |||
125 | tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); | ||
126 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | ||
127 | int scale, TCGv_i64 scalar, int msz, bool is_write, | ||
128 | gen_helper_gvec_mem_scatter *fn) | ||
129 | { | ||
130 | - unsigned vsz = vec_full_reg_size(s); | ||
131 | TCGv_ptr t_zm = tcg_temp_new_ptr(); | ||
132 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | ||
133 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | ||
134 | - int desc = 0; | ||
135 | - | ||
136 | - if (s->mte_active[0]) { | ||
137 | - desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
138 | - desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
139 | - desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
140 | - desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
141 | - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); | ||
142 | - desc <<= SVE_MTEDESC_SHIFT; | ||
143 | - } | ||
144 | - desc = simd_desc(vsz, vsz, desc | scale); | ||
145 | + uint32_t desc; | ||
146 | |||
147 | tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); | ||
148 | tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm)); | ||
149 | tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt)); | ||
150 | + | ||
151 | + desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale); | ||
152 | fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); | ||
153 | } | ||
154 | |||
155 | -- | ||
156 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | These functions "use the standard load helpers", but | ||
4 | fail to clean_data_tbi or populate mtedesc. | ||
5 | |||
6 | Cc: qemu-stable@nongnu.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> | ||
10 | Message-id: 20240207025210.8837-6-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/tcg/translate-sve.c | 15 +++++++++++++-- | ||
14 | 1 file changed, 13 insertions(+), 2 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/tcg/translate-sve.c | ||
19 | +++ b/target/arm/tcg/translate-sve.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
21 | unsigned vsz = vec_full_reg_size(s); | ||
22 | TCGv_ptr t_pg; | ||
23 | int poff; | ||
24 | + uint32_t desc; | ||
25 | |||
26 | /* Load the first quadword using the normal predicated load helpers. */ | ||
27 | + if (!s->mte_active[0]) { | ||
28 | + addr = clean_data_tbi(s, addr); | ||
29 | + } | ||
30 | + | ||
31 | poff = pred_full_reg_offset(s, pg); | ||
32 | if (vsz > 16) { | ||
33 | /* | ||
34 | @@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
35 | |||
36 | gen_helper_gvec_mem *fn | ||
37 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | ||
38 | - fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); | ||
39 | + desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt); | ||
40 | + fn(tcg_env, t_pg, addr, tcg_constant_i32(desc)); | ||
41 | |||
42 | /* Replicate that first quadword. */ | ||
43 | if (vsz > 16) { | ||
44 | @@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
45 | unsigned vsz_r32; | ||
46 | TCGv_ptr t_pg; | ||
47 | int poff, doff; | ||
48 | + uint32_t desc; | ||
49 | |||
50 | if (vsz < 32) { | ||
51 | /* | ||
52 | @@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
53 | } | ||
54 | |||
55 | /* Load the first octaword using the normal predicated load helpers. */ | ||
56 | + if (!s->mte_active[0]) { | ||
57 | + addr = clean_data_tbi(s, addr); | ||
58 | + } | ||
59 | |||
60 | poff = pred_full_reg_offset(s, pg); | ||
61 | if (vsz > 32) { | ||
62 | @@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
63 | |||
64 | gen_helper_gvec_mem *fn | ||
65 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; | ||
66 | - fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); | ||
67 | + desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt); | ||
68 | + fn(tcg_env, t_pg, addr, tcg_constant_i32(desc)); | ||
69 | |||
70 | /* | ||
71 | * Replicate that first octaword. | ||
72 | -- | ||
73 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When storing to an AdvSIMD FP register, all of the high | 3 | The TBI and TCMA bits are located within mtedesc, not desc. |
4 | bits of the SVE register are zeroed. Therefore, call it | ||
5 | more often with is_q as a parameter. | ||
6 | 4 | ||
5 | Cc: qemu-stable@nongnu.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180211205848.4568-6-richard.henderson@linaro.org | 8 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: 20240207025210.8837-7-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | target/arm/translate-a64.c | 162 +++++++++++++++++---------------------------- | 12 | target/arm/tcg/sme_helper.c | 8 ++++---- |
13 | 1 file changed, 62 insertions(+), 100 deletions(-) | 13 | target/arm/tcg/sve_helper.c | 12 ++++++------ |
14 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
14 | 15 | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 16 | diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 18 | --- a/target/arm/tcg/sme_helper.c |
18 | +++ b/target/arm/translate-a64.c | 19 | +++ b/target/arm/tcg/sme_helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | 20 | @@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, |
20 | return v; | 21 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
21 | } | 22 | |
22 | 23 | /* Perform gross MTE suppression early. */ | |
23 | +/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). | 24 | - if (!tbi_check(desc, bit55) || |
24 | + * If SVE is not enabled, then there are only 128 bits in the vector. | 25 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
25 | + */ | 26 | + if (!tbi_check(mtedesc, bit55) || |
26 | +static void clear_vec_high(DisasContext *s, bool is_q, int rd) | 27 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
27 | +{ | 28 | mtedesc = 0; |
28 | + unsigned ofs = fp_reg_offset(s, rd, MO_64); | ||
29 | + unsigned vsz = vec_full_reg_size(s); | ||
30 | + | ||
31 | + if (!is_q) { | ||
32 | + TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
33 | + tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); | ||
34 | + tcg_temp_free_i64(tcg_zero); | ||
35 | + } | ||
36 | + if (vsz > 16) { | ||
37 | + tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0); | ||
38 | + } | ||
39 | +} | ||
40 | + | ||
41 | static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) | ||
42 | { | ||
43 | - TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
44 | + unsigned ofs = fp_reg_offset(s, reg, MO_64); | ||
45 | |||
46 | - tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); | ||
47 | - tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); | ||
48 | - tcg_temp_free_i64(tcg_zero); | ||
49 | + tcg_gen_st_i64(v, cpu_env, ofs); | ||
50 | + clear_vec_high(s, false, reg); | ||
51 | } | ||
52 | |||
53 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | ||
54 | @@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | ||
55 | |||
56 | tcg_temp_free_i64(tmplo); | ||
57 | tcg_temp_free_i64(tmphi); | ||
58 | + | ||
59 | + clear_vec_high(s, true, destidx); | ||
60 | } | ||
61 | |||
62 | /* | ||
63 | @@ -XXX,XX +XXX,XX @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, | ||
64 | } | 29 | } |
65 | } | 30 | |
66 | 31 | @@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr, | |
67 | -/* Clear the high 64 bits of a 128 bit vector (in general non-quad | 32 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
68 | - * vector ops all need to do this). | 33 | |
69 | - */ | 34 | /* Perform gross MTE suppression early. */ |
70 | -static void clear_vec_high(DisasContext *s, int rd) | 35 | - if (!tbi_check(desc, bit55) || |
71 | -{ | 36 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
72 | - TCGv_i64 tcg_zero = tcg_const_i64(0); | 37 | + if (!tbi_check(mtedesc, bit55) || |
73 | - | 38 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
74 | - write_vec_element(s, tcg_zero, rd, 1, MO_64); | 39 | mtedesc = 0; |
75 | - tcg_temp_free_i64(tcg_zero); | ||
76 | -} | ||
77 | - | ||
78 | /* Store from vector register to memory */ | ||
79 | static void do_vec_st(DisasContext *s, int srcidx, int element, | ||
80 | TCGv_i64 tcg_addr, int size) | ||
81 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
82 | /* For non-quad operations, setting a slice of the low | ||
83 | * 64 bits of the register clears the high 64 bits (in | ||
84 | * the ARM ARM pseudocode this is implicit in the fact | ||
85 | - * that 'rval' is a 64 bit wide variable). We optimize | ||
86 | - * by noticing that we only need to do this the first | ||
87 | - * time we touch a register. | ||
88 | + * that 'rval' is a 64 bit wide variable). | ||
89 | + * For quad operations, we might still need to zero the | ||
90 | + * high bits of SVE. We optimize by noticing that we only | ||
91 | + * need to do this the first time we touch a register. | ||
92 | */ | ||
93 | - if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) { | ||
94 | - clear_vec_high(s, tt); | ||
95 | + if (e == 0 && (r == 0 || xs == selem - 1)) { | ||
96 | + clear_vec_high(s, is_q, tt); | ||
97 | } | ||
98 | } | ||
99 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | ||
100 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
101 | write_vec_element(s, tcg_tmp, rt, 0, MO_64); | ||
102 | if (is_q) { | ||
103 | write_vec_element(s, tcg_tmp, rt, 1, MO_64); | ||
104 | - } else { | ||
105 | - clear_vec_high(s, rt); | ||
106 | } | ||
107 | tcg_temp_free_i64(tcg_tmp); | ||
108 | + clear_vec_high(s, is_q, rt); | ||
109 | } else { | ||
110 | /* Load/store one element per register */ | ||
111 | if (is_load) { | ||
112 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | ||
113 | } | 40 | } |
114 | 41 | ||
115 | if (!is_q) { | 42 | diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c |
116 | - clear_vec_high(s, rd); | 43 | index XXXXXXX..XXXXXXX 100644 |
117 | write_vec_element(s, tcg_final, rd, 0, MO_64); | 44 | --- a/target/arm/tcg/sve_helper.c |
118 | } else { | 45 | +++ b/target/arm/tcg/sve_helper.c |
119 | write_vec_element(s, tcg_final, rd, 1, MO_64); | 46 | @@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, |
120 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | 47 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
121 | tcg_temp_free_i64(tcg_rd); | 48 | |
122 | tcg_temp_free_i32(tcg_rd_narrowed); | 49 | /* Perform gross MTE suppression early. */ |
123 | tcg_temp_free_i64(tcg_final); | 50 | - if (!tbi_check(desc, bit55) || |
124 | - return; | 51 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
125 | + | 52 | + if (!tbi_check(mtedesc, bit55) || |
126 | + clear_vec_high(s, is_q, rd); | 53 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
127 | } | 54 | mtedesc = 0; |
128 | |||
129 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ | ||
130 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | ||
131 | tcg_temp_free_i64(tcg_op); | ||
132 | } | ||
133 | tcg_temp_free_i64(tcg_shift); | ||
134 | - | ||
135 | - if (!is_q) { | ||
136 | - clear_vec_high(s, rd); | ||
137 | - } | ||
138 | + clear_vec_high(s, is_q, rd); | ||
139 | } else { | ||
140 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | ||
141 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | ||
142 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | ||
143 | } | ||
144 | tcg_temp_free_i32(tcg_shift); | ||
145 | |||
146 | - if (!is_q && !scalar) { | ||
147 | - clear_vec_high(s, rd); | ||
148 | + if (!scalar) { | ||
149 | + clear_vec_high(s, is_q, rd); | ||
150 | } | ||
151 | } | 55 | } |
152 | } | 56 | |
153 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | 57 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr, |
154 | } | 58 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
59 | |||
60 | /* Perform gross MTE suppression early. */ | ||
61 | - if (!tbi_check(desc, bit55) || | ||
62 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { | ||
63 | + if (!tbi_check(mtedesc, bit55) || | ||
64 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { | ||
65 | mtedesc = 0; | ||
155 | } | 66 | } |
156 | 67 | ||
157 | - if (!is_double && elements == 2) { | 68 | @@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, |
158 | - clear_vec_high(s, rd); | 69 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
159 | - } | 70 | |
160 | - | 71 | /* Perform gross MTE suppression early. */ |
161 | tcg_temp_free_i64(tcg_int); | 72 | - if (!tbi_check(desc, bit55) || |
162 | tcg_temp_free_ptr(tcg_fpst); | 73 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
163 | tcg_temp_free_i32(tcg_shift); | 74 | + if (!tbi_check(mtedesc, bit55) || |
164 | + | 75 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
165 | + clear_vec_high(s, elements << size == 16, rd); | 76 | mtedesc = 0; |
166 | } | ||
167 | |||
168 | /* UCVTF/SCVTF - Integer to FP conversion */ | ||
169 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | ||
170 | write_vec_element(s, tcg_op, rd, pass, MO_64); | ||
171 | tcg_temp_free_i64(tcg_op); | ||
172 | } | ||
173 | - if (!is_q) { | ||
174 | - clear_vec_high(s, rd); | ||
175 | - } | ||
176 | + clear_vec_high(s, is_q, rd); | ||
177 | } else { | ||
178 | int maxpass = is_scalar ? 1 : is_q ? 4 : 2; | ||
179 | for (pass = 0; pass < maxpass; pass++) { | ||
180 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | ||
181 | } | ||
182 | tcg_temp_free_i32(tcg_op); | ||
183 | } | ||
184 | - if (!is_q && !is_scalar) { | ||
185 | - clear_vec_high(s, rd); | ||
186 | + if (!is_scalar) { | ||
187 | + clear_vec_high(s, is_q, rd); | ||
188 | } | ||
189 | } | 77 | } |
190 | 78 | ||
191 | @@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements, | ||
192 | |||
193 | tcg_temp_free_ptr(fpst); | ||
194 | |||
195 | - if ((elements << size) < 4) { | ||
196 | - /* scalar, or non-quad vector op */ | ||
197 | - clear_vec_high(s, rd); | ||
198 | - } | ||
199 | + clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); | ||
200 | } | ||
201 | |||
202 | /* AdvSIMD scalar three same | ||
203 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
204 | } | ||
205 | write_vec_element(s, tcg_res, rd, pass, MO_64); | ||
206 | } | ||
207 | - if (is_scalar) { | ||
208 | - clear_vec_high(s, rd); | ||
209 | - } | ||
210 | - | ||
211 | tcg_temp_free_i64(tcg_res); | ||
212 | tcg_temp_free_i64(tcg_zero); | ||
213 | tcg_temp_free_i64(tcg_op); | ||
214 | + | ||
215 | + clear_vec_high(s, !is_scalar, rd); | ||
216 | } else { | ||
217 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
218 | TCGv_i32 tcg_zero = tcg_const_i32(0); | ||
219 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
220 | tcg_temp_free_i32(tcg_res); | ||
221 | tcg_temp_free_i32(tcg_zero); | ||
222 | tcg_temp_free_i32(tcg_op); | ||
223 | - if (!is_q && !is_scalar) { | ||
224 | - clear_vec_high(s, rd); | ||
225 | + if (!is_scalar) { | ||
226 | + clear_vec_high(s, is_q, rd); | ||
227 | } | ||
228 | } | ||
229 | |||
230 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, | ||
231 | } | ||
232 | write_vec_element(s, tcg_res, rd, pass, MO_64); | ||
233 | } | ||
234 | - if (is_scalar) { | ||
235 | - clear_vec_high(s, rd); | ||
236 | - } | ||
237 | - | ||
238 | tcg_temp_free_i64(tcg_res); | ||
239 | tcg_temp_free_i64(tcg_op); | ||
240 | + clear_vec_high(s, !is_scalar, rd); | ||
241 | } else { | ||
242 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
243 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
244 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, | ||
245 | } | ||
246 | tcg_temp_free_i32(tcg_res); | ||
247 | tcg_temp_free_i32(tcg_op); | ||
248 | - if (!is_q && !is_scalar) { | ||
249 | - clear_vec_high(s, rd); | ||
250 | + if (!is_scalar) { | ||
251 | + clear_vec_high(s, is_q, rd); | ||
252 | } | ||
253 | } | ||
254 | tcg_temp_free_ptr(fpst); | ||
255 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar, | ||
256 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | ||
257 | tcg_temp_free_i32(tcg_res[pass]); | ||
258 | } | ||
259 | - if (!is_q) { | ||
260 | - clear_vec_high(s, rd); | ||
261 | - } | ||
262 | + clear_vec_high(s, is_q, rd); | ||
263 | } | ||
264 | |||
265 | /* Remaining saturating accumulating ops */ | ||
266 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | ||
267 | } | ||
268 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | ||
269 | } | ||
270 | - if (is_scalar) { | ||
271 | - clear_vec_high(s, rd); | ||
272 | - } | ||
273 | - | ||
274 | tcg_temp_free_i64(tcg_rd); | ||
275 | tcg_temp_free_i64(tcg_rn); | ||
276 | + clear_vec_high(s, !is_scalar, rd); | ||
277 | } else { | ||
278 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | ||
279 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | ||
280 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | ||
281 | } | ||
282 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | ||
283 | } | ||
284 | - | ||
285 | - if (!is_q) { | ||
286 | - clear_vec_high(s, rd); | ||
287 | - } | ||
288 | - | ||
289 | tcg_temp_free_i32(tcg_rd); | ||
290 | tcg_temp_free_i32(tcg_rn); | ||
291 | + clear_vec_high(s, is_q, rd); | ||
292 | } | ||
293 | } | ||
294 | |||
295 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | ||
296 | tcg_temp_free_i64(tcg_round); | ||
297 | |||
298 | done: | ||
299 | - if (!is_q) { | ||
300 | - clear_vec_high(s, rd); | ||
301 | - } | ||
302 | + clear_vec_high(s, is_q, rd); | ||
303 | } | ||
304 | |||
305 | static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) | ||
306 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | ||
307 | } | ||
308 | |||
309 | if (!is_q) { | ||
310 | - clear_vec_high(s, rd); | ||
311 | write_vec_element(s, tcg_final, rd, 0, MO_64); | ||
312 | } else { | ||
313 | write_vec_element(s, tcg_final, rd, 1, MO_64); | ||
314 | } | ||
315 | - | ||
316 | if (round) { | ||
317 | tcg_temp_free_i64(tcg_round); | ||
318 | } | ||
319 | tcg_temp_free_i64(tcg_rn); | ||
320 | tcg_temp_free_i64(tcg_rd); | ||
321 | tcg_temp_free_i64(tcg_final); | ||
322 | - return; | ||
323 | + | ||
324 | + clear_vec_high(s, is_q, rd); | ||
325 | } | ||
326 | |||
327 | |||
328 | @@ -XXX,XX +XXX,XX @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | ||
329 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | ||
330 | tcg_temp_free_i32(tcg_res[pass]); | ||
331 | } | ||
332 | - if (!is_q) { | ||
333 | - clear_vec_high(s, rd); | ||
334 | - } | ||
335 | + clear_vec_high(s, is_q, rd); | ||
336 | } | ||
337 | |||
338 | static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm) | ||
339 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | ||
340 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | ||
341 | tcg_temp_free_i32(tcg_res[pass]); | ||
342 | } | ||
343 | - if (!is_q) { | ||
344 | - clear_vec_high(s, rd); | ||
345 | - } | ||
346 | + clear_vec_high(s, is_q, rd); | ||
347 | } | ||
348 | |||
349 | if (fpst) { | ||
350 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | ||
351 | tcg_temp_free_i32(tcg_op2); | ||
352 | } | ||
353 | } | ||
354 | - | ||
355 | - if (!is_q) { | ||
356 | - clear_vec_high(s, rd); | ||
357 | - } | ||
358 | + clear_vec_high(s, is_q, rd); | ||
359 | } | ||
360 | |||
361 | /* AdvSIMD three same | ||
362 | @@ -XXX,XX +XXX,XX @@ static void handle_rev(DisasContext *s, int opcode, bool u, | ||
363 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | ||
364 | tcg_temp_free_i64(tcg_tmp); | ||
365 | } | ||
366 | - if (!is_q) { | ||
367 | - clear_vec_high(s, rd); | ||
368 | - } | ||
369 | + clear_vec_high(s, is_q, rd); | ||
370 | } else { | ||
371 | int revmask = (1 << grp_size) - 1; | ||
372 | int esize = 8 << size; | ||
373 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | ||
374 | tcg_temp_free_i32(tcg_op); | ||
375 | } | ||
376 | } | ||
377 | - if (!is_q) { | ||
378 | - clear_vec_high(s, rd); | ||
379 | - } | ||
380 | + clear_vec_high(s, is_q, rd); | ||
381 | |||
382 | if (need_rmode) { | ||
383 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | ||
384 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
385 | tcg_temp_free_i64(tcg_res); | ||
386 | } | ||
387 | |||
388 | - if (is_scalar) { | ||
389 | - clear_vec_high(s, rd); | ||
390 | - } | ||
391 | - | ||
392 | tcg_temp_free_i64(tcg_idx); | ||
393 | + clear_vec_high(s, !is_scalar, rd); | ||
394 | } else if (!is_long) { | ||
395 | /* 32 bit floating point, or 16 or 32 bit integer. | ||
396 | * For the 16 bit scalar case we use the usual Neon helpers and | ||
397 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
398 | } | ||
399 | |||
400 | tcg_temp_free_i32(tcg_idx); | ||
401 | - | ||
402 | - if (!is_q) { | ||
403 | - clear_vec_high(s, rd); | ||
404 | - } | ||
405 | + clear_vec_high(s, is_q, rd); | ||
406 | } else { | ||
407 | /* long ops: 16x16->32 or 32x32->64 */ | ||
408 | TCGv_i64 tcg_res[2]; | ||
409 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) | ||
410 | } | ||
411 | tcg_temp_free_i64(tcg_idx); | ||
412 | |||
413 | - if (is_scalar) { | ||
414 | - clear_vec_high(s, rd); | ||
415 | - } | ||
416 | + clear_vec_high(s, !is_scalar, rd); | ||
417 | } else { | ||
418 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | ||
419 | |||
420 | -- | 79 | -- |
421 | 2.16.1 | 80 | 2.34.1 |
422 | |||
423 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | The raven_io_ops MemoryRegionOps is the only one in the source tree |
---|---|---|---|
2 | which sets .valid.unaligned to indicate that it should support | ||
3 | unaligned accesses and which does not also set .impl.unaligned to | ||
4 | indicate that its read and write functions can do the unaligned | ||
5 | handling themselves. This is a problem, because at the moment the | ||
6 | core memory system does not implement the support for handling | ||
7 | unaligned accesses by doing a series of aligned accesses and | ||
8 | combining them (system/memory.c:access_with_adjusted_size() has a | ||
9 | TODO comment noting this). | ||
2 | 10 | ||
3 | (qemu) info mtree | 11 | Fortunately raven_io_read() and raven_io_write() will correctly deal |
4 | address-space: cpu-memory-0 | 12 | with the case of being passed an unaligned address, so we can fix the |
5 | 0000000000000000-ffffffffffffffff (prio 0, i/o): system | 13 | missing unaligned access support by setting .impl.unaligned in the |
6 | 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom | 14 | MemoryRegionOps struct. |
7 | 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io | ||
8 | - 000000001e784000-000000001e78401f (prio 0, i/o): serial | ||
9 | 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc | ||
10 | 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 | ||
11 | [...] | ||
12 | 000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram | ||
13 | 000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer | ||
14 | + 000000001e784000-000000001e78401f (prio 0, i/o): serial | ||
15 | 000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt | ||
16 | 000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt | ||
17 | 15 | ||
18 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 16 | Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") |
19 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
20 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | ||
21 | Message-id: 20180209085755.30414-2-f4bug@amsat.org | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Tested-by: Cédric Le Goater <clg@redhat.com> | ||
19 | Reviewed-by: Cédric Le Goater <clg@redhat.com> | ||
20 | Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org | ||
23 | --- | 21 | --- |
24 | hw/arm/aspeed_soc.c | 3 ++- | 22 | hw/pci-host/raven.c | 1 + |
25 | 1 file changed, 2 insertions(+), 1 deletion(-) | 23 | 1 file changed, 1 insertion(+) |
26 | 24 | ||
27 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 25 | diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c |
28 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/arm/aspeed_soc.c | 27 | --- a/hw/pci-host/raven.c |
30 | +++ b/hw/arm/aspeed_soc.c | 28 | +++ b/hw/pci-host/raven.c |
31 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 29 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = { |
32 | /* UART - attach an 8250 to the IO space as our UART5 */ | 30 | .write = raven_io_write, |
33 | if (serial_hds[0]) { | 31 | .endianness = DEVICE_LITTLE_ENDIAN, |
34 | qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); | 32 | .impl.max_access_size = 4, |
35 | - serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2, | 33 | + .impl.unaligned = true, |
36 | + serial_mm_init(get_system_memory(), | 34 | .valid.unaligned = true, |
37 | + ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, | 35 | }; |
38 | uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN); | ||
39 | } | ||
40 | 36 | ||
41 | -- | 37 | -- |
42 | 2.16.1 | 38 | 2.34.1 |
43 | 39 | ||
44 | 40 | diff view generated by jsdifflib |
1 | In many of the NVIC registers relating to interrupts, we | 1 | Suppress the deprecation warning when we're running under qtest, |
---|---|---|---|
2 | have to convert from a byte offset within a register set | 2 | to avoid "make check" including warning messages in its output. |
3 | into the number of the first interrupt which is affected. | ||
4 | We were getting this wrong for: | ||
5 | * reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>, | ||
6 | NVIC_IABR<n> -- in all these cases we were missing the "* 8" | ||
7 | needed to convert from the byte offset to the interrupt number | ||
8 | (since all these registers use one bit per interrupt) | ||
9 | * writes of NVIC_IPR<n> had the opposite problem of a spurious | ||
10 | "* 8" (since these registers use one byte per interrupt) | ||
11 | 3 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
14 | Message-id: 20180209165810.6668-9-peter.maydell@linaro.org | 6 | Message-id: 20240206154151.155620-1-peter.maydell@linaro.org |
15 | --- | 7 | --- |
16 | hw/intc/armv7m_nvic.c | 8 ++++---- | 8 | hw/block/tc58128.c | 4 +++- |
17 | 1 file changed, 4 insertions(+), 4 deletions(-) | 9 | 1 file changed, 3 insertions(+), 1 deletion(-) |
18 | 10 | ||
19 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 11 | diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c |
20 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/intc/armv7m_nvic.c | 13 | --- a/hw/block/tc58128.c |
22 | +++ b/hw/intc/armv7m_nvic.c | 14 | +++ b/hw/block/tc58128.c |
23 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | 15 | @@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = { |
24 | /* fall through */ | 16 | |
25 | case 0x180 ... 0x1bf: /* NVIC Clear enable */ | 17 | int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) |
26 | val = 0; | 18 | { |
27 | - startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ | 19 | - warn_report_once("The TC58128 flash device is deprecated"); |
28 | + startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ | 20 | + if (!qtest_enabled()) { |
29 | 21 | + warn_report_once("The TC58128 flash device is deprecated"); | |
30 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | 22 | + } |
31 | if (s->vectors[startvec + i].enabled && | 23 | init_dev(&tc58128_devs[0], zone1); |
32 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | 24 | init_dev(&tc58128_devs[1], zone2); |
33 | /* fall through */ | 25 | return sh7750_register_io_device(s, &tc58128); |
34 | case 0x280 ... 0x2bf: /* NVIC Clear pend */ | ||
35 | val = 0; | ||
36 | - startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ | ||
37 | + startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ | ||
38 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | ||
39 | if (s->vectors[startvec + i].pending && | ||
40 | (attrs.secure || s->itns[startvec + i])) { | ||
41 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | ||
42 | break; | ||
43 | case 0x300 ... 0x33f: /* NVIC Active */ | ||
44 | val = 0; | ||
45 | - startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ | ||
46 | + startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ | ||
47 | |||
48 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | ||
49 | if (s->vectors[startvec + i].active && | ||
50 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, | ||
51 | case 0x300 ... 0x33f: /* NVIC Active */ | ||
52 | return MEMTX_OK; /* R/O */ | ||
53 | case 0x400 ... 0x5ef: /* NVIC Priority */ | ||
54 | - startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ | ||
55 | + startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ | ||
56 | |||
57 | for (i = 0; i < size && startvec + i < s->num_irq; i++) { | ||
58 | if (attrs.secure || s->itns[startvec + i]) { | ||
59 | -- | 26 | -- |
60 | 2.16.1 | 27 | 2.34.1 |
61 | 28 | ||
62 | 29 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We deliberately don't include qtests_npcm7xx in qtests_aarch64, | ||
2 | because we already get the coverage of those tests via qtests_arm, | ||
3 | and we don't want to use extra CI minutes testing them twice. | ||
1 | 4 | ||
5 | In commit 327b680877b79c4b we added it to qtests_aarch64; revert | ||
6 | that change. | ||
7 | |||
8 | Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module") | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Message-id: 20240206163043.315535-1-peter.maydell@linaro.org | ||
12 | --- | ||
13 | tests/qtest/meson.build | 1 - | ||
14 | 1 file changed, 1 deletion(-) | ||
15 | |||
16 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/tests/qtest/meson.build | ||
19 | +++ b/tests/qtest/meson.build | ||
20 | @@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \ | ||
21 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ | ||
22 | (config_all_accel.has_key('CONFIG_TCG') and \ | ||
23 | config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ | ||
24 | - (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ | ||
25 | ['arm-cpu-features', | ||
26 | 'numa-test', | ||
27 | 'boot-serial-test', | ||
28 | -- | ||
29 | 2.34.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Allow changes to the virt GTDT -- we are going to add the IRQ | ||
2 | entry for a new timer to it. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Ard Biesheuvel <ardb@kernel.org> | ||
6 | Message-id: 20240122143537.233498-2-peter.maydell@linaro.org | ||
7 | --- | ||
8 | tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ | ||
9 | 1 file changed, 2 insertions(+) | ||
10 | |||
11 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
14 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
15 | @@ -1 +1,3 @@ | ||
16 | /* List of comma-separated changed AML files to ignore */ | ||
17 | +"tests/data/acpi/virt/FACP", | ||
18 | +"tests/data/acpi/virt/GTDT", | ||
19 | -- | ||
20 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a | |
2 | non-secure EL2 virtual timer. We implemented the timer itself in the | ||
3 | CPU model, but never wired up its IRQ line to the GIC. | ||
4 | |||
5 | Wire up the IRQ line (this is always safe whether the CPU has the | ||
6 | interrupt or not, since it always creates the outbound IRQ line). | ||
7 | Report it to the guest via dtb and ACPI if the CPU has the feature. | ||
8 | |||
9 | The DTB binding is documented in the kernel's | ||
10 | Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml | ||
11 | and the ACPI table entries are documented in the ACPI specification | ||
12 | version 6.3 or later. | ||
13 | |||
14 | Because the IRQ line ACPI binding is new in 6.3, we need to bump the | ||
15 | FADT table rev to show that we might be using 6.3 features. | ||
16 | |||
17 | Note that exposing this IRQ in the DTB will trigger a bug in EDK2 | ||
18 | versions prior to edk2-stable202311, for users who use the virt board | ||
19 | with 'virtualization=on' to enable EL2 emulation and are booting an | ||
20 | EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is | ||
21 | that EDK2 will assert on bootup: | ||
22 | |||
23 | ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48 | ||
24 | |||
25 | If you see that assertion you should do one of: | ||
26 | * update your EDK2 binaries to edk2-stable202311 or newer | ||
27 | * use the 'virt-8.2' versioned machine type | ||
28 | * not use 'virtualization=on' | ||
29 | |||
30 | (The versions shipped with QEMU itself have the fix.) | ||
31 | |||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | Reviewed-by: Ard Biesheuvel <ardb@kernel.org> | ||
34 | Message-id: 20240122143537.233498-3-peter.maydell@linaro.org | ||
35 | --- | ||
36 | include/hw/arm/virt.h | 2 ++ | ||
37 | hw/arm/virt-acpi-build.c | 20 ++++++++++---- | ||
38 | hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------ | ||
39 | 3 files changed, 67 insertions(+), 15 deletions(-) | ||
40 | |||
41 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/include/hw/arm/virt.h | ||
44 | +++ b/include/hw/arm/virt.h | ||
45 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineClass { | ||
46 | /* Machines < 6.2 have no support for describing cpu topology to guest */ | ||
47 | bool no_cpu_topology; | ||
48 | bool no_tcg_lpa2; | ||
49 | + bool no_ns_el2_virt_timer_irq; | ||
50 | }; | ||
51 | |||
52 | struct VirtMachineState { | ||
53 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { | ||
54 | PCIBus *bus; | ||
55 | char *oem_id; | ||
56 | char *oem_table_id; | ||
57 | + bool ns_el2_virt_timer_irq; | ||
58 | }; | ||
59 | |||
60 | #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) | ||
61 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/virt-acpi-build.c | ||
64 | +++ b/hw/arm/virt-acpi-build.c | ||
65 | @@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
66 | } | ||
67 | |||
68 | /* | ||
69 | - * ACPI spec, Revision 5.1 | ||
70 | - * 5.2.24 Generic Timer Description Table (GTDT) | ||
71 | + * ACPI spec, Revision 6.5 | ||
72 | + * 5.2.25 Generic Timer Description Table (GTDT) | ||
73 | */ | ||
74 | static void | ||
75 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
76 | @@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
77 | uint32_t irqflags = vmc->claim_edge_triggered_timers ? | ||
78 | 1 : /* Interrupt is Edge triggered */ | ||
79 | 0; /* Interrupt is Level triggered */ | ||
80 | - AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id, | ||
81 | + AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, | ||
82 | .oem_table_id = vms->oem_table_id }; | ||
83 | |||
84 | acpi_table_begin(&table, table_data); | ||
85 | @@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
86 | build_append_int_noprefix(table_data, 0, 4); | ||
87 | /* Platform Timer Offset */ | ||
88 | build_append_int_noprefix(table_data, 0, 4); | ||
89 | - | ||
90 | + if (vms->ns_el2_virt_timer_irq) { | ||
91 | + /* Virtual EL2 Timer GSIV */ | ||
92 | + build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); | ||
93 | + /* Virtual EL2 Timer Flags */ | ||
94 | + build_append_int_noprefix(table_data, irqflags, 4); | ||
95 | + } else { | ||
96 | + build_append_int_noprefix(table_data, 0, 4); | ||
97 | + build_append_int_noprefix(table_data, 0, 4); | ||
98 | + } | ||
99 | acpi_table_end(linker, &table); | ||
100 | } | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
103 | static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, | ||
104 | VirtMachineState *vms, unsigned dsdt_tbl_offset) | ||
105 | { | ||
106 | - /* ACPI v6.0 */ | ||
107 | + /* ACPI v6.3 */ | ||
108 | AcpiFadtData fadt = { | ||
109 | .rev = 6, | ||
110 | - .minor_ver = 0, | ||
111 | + .minor_ver = 3, | ||
112 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, | ||
113 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | ||
114 | }; | ||
115 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
116 | index XXXXXXX..XXXXXXX 100644 | ||
117 | --- a/hw/arm/virt.c | ||
118 | +++ b/hw/arm/virt.c | ||
119 | @@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node) | ||
120 | qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); | ||
121 | } | ||
122 | |||
123 | +/* | ||
124 | + * The CPU object always exposes the NS EL2 virt timer IRQ line, | ||
125 | + * but we don't want to advertise it to the guest in the dtb or ACPI | ||
126 | + * table unless it's really going to do something. | ||
127 | + */ | ||
128 | +static bool ns_el2_virt_timer_present(void) | ||
129 | +{ | ||
130 | + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); | ||
131 | + CPUARMState *env = &cpu->env; | ||
132 | + | ||
133 | + return arm_feature(env, ARM_FEATURE_AARCH64) && | ||
134 | + arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); | ||
135 | +} | ||
136 | + | ||
137 | static void create_fdt(VirtMachineState *vms) | ||
138 | { | ||
139 | MachineState *ms = MACHINE(vms); | ||
140 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) | ||
141 | "arm,armv7-timer"); | ||
142 | } | ||
143 | qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); | ||
144 | - qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", | ||
145 | - GIC_FDT_IRQ_TYPE_PPI, | ||
146 | - INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, | ||
147 | - GIC_FDT_IRQ_TYPE_PPI, | ||
148 | - INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, | ||
149 | - GIC_FDT_IRQ_TYPE_PPI, | ||
150 | - INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, | ||
151 | - GIC_FDT_IRQ_TYPE_PPI, | ||
152 | - INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); | ||
153 | + if (vms->ns_el2_virt_timer_irq) { | ||
154 | + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", | ||
155 | + GIC_FDT_IRQ_TYPE_PPI, | ||
156 | + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, | ||
157 | + GIC_FDT_IRQ_TYPE_PPI, | ||
158 | + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, | ||
159 | + GIC_FDT_IRQ_TYPE_PPI, | ||
160 | + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, | ||
161 | + GIC_FDT_IRQ_TYPE_PPI, | ||
162 | + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, | ||
163 | + GIC_FDT_IRQ_TYPE_PPI, | ||
164 | + INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); | ||
165 | + } else { | ||
166 | + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", | ||
167 | + GIC_FDT_IRQ_TYPE_PPI, | ||
168 | + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, | ||
169 | + GIC_FDT_IRQ_TYPE_PPI, | ||
170 | + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, | ||
171 | + GIC_FDT_IRQ_TYPE_PPI, | ||
172 | + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, | ||
173 | + GIC_FDT_IRQ_TYPE_PPI, | ||
174 | + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); | ||
175 | + } | ||
176 | } | ||
177 | |||
178 | static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
179 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) | ||
180 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | ||
181 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | ||
182 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | ||
183 | + [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, | ||
184 | }; | ||
185 | |||
186 | for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | ||
187 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
188 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); | ||
189 | object_unref(cpuobj); | ||
190 | } | ||
191 | + | ||
192 | + /* Now we've created the CPUs we can see if they have the hypvirt timer */ | ||
193 | + vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && | ||
194 | + !vmc->no_ns_el2_virt_timer_irq; | ||
195 | + | ||
196 | fdt_add_timer_nodes(vms); | ||
197 | fdt_add_cpu_nodes(vms); | ||
198 | |||
199 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) | ||
200 | |||
201 | static void virt_machine_8_2_options(MachineClass *mc) | ||
202 | { | ||
203 | + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); | ||
204 | + | ||
205 | virt_machine_9_0_options(mc); | ||
206 | compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); | ||
207 | + /* | ||
208 | + * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and | ||
209 | + * earlier machines. (Exposing it tickles a bug in older EDK2 | ||
210 | + * guest BIOS binaries.) | ||
211 | + */ | ||
212 | + vmc->no_ns_el2_virt_timer_irq = true; | ||
213 | } | ||
214 | DEFINE_VIRT_MACHINE(8, 2) | ||
215 | |||
216 | -- | ||
217 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Update the virt golden reference files to say that the FACP is ACPI | |
2 | v6.3, and the GTDT table is a revision 3 table with space for the | ||
3 | virtual EL2 timer. | ||
4 | |||
5 | Diffs from iasl: | ||
6 | |||
7 | @@ -XXX,XX +XXX,XX @@ | ||
8 | /* | ||
9 | * Intel ACPI Component Architecture | ||
10 | * AML/ASL+ Disassembler version 20200925 (64-bit version) | ||
11 | * Copyright (c) 2000 - 2020 Intel Corporation | ||
12 | * | ||
13 | - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024 | ||
14 | + * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024 | ||
15 | * | ||
16 | * ACPI Data Table [FACP] | ||
17 | * | ||
18 | * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue | ||
19 | */ | ||
20 | |||
21 | [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] | ||
22 | [004h 0004 4] Table Length : 00000114 | ||
23 | [008h 0008 1] Revision : 06 | ||
24 | -[009h 0009 1] Checksum : 15 | ||
25 | +[009h 0009 1] Checksum : 12 | ||
26 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
27 | [010h 0016 8] Oem Table ID : "BXPC " | ||
28 | [018h 0024 4] Oem Revision : 00000001 | ||
29 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
30 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
31 | |||
32 | [024h 0036 4] FACS Address : 00000000 | ||
33 | [028h 0040 4] DSDT Address : 00000000 | ||
34 | [02Ch 0044 1] Model : 00 | ||
35 | [02Dh 0045 1] PM Profile : 00 [Unspecified] | ||
36 | [02Eh 0046 2] SCI Interrupt : 0000 | ||
37 | [030h 0048 4] SMI Command Port : 00000000 | ||
38 | [034h 0052 1] ACPI Enable Value : 00 | ||
39 | [035h 0053 1] ACPI Disable Value : 00 | ||
40 | [036h 0054 1] S4BIOS Command : 00 | ||
41 | [037h 0055 1] P-State Control : 00 | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | Use APIC Physical Destination Mode (V4) : 0 | ||
44 | Hardware Reduced (V5) : 1 | ||
45 | Low Power S0 Idle (V5) : 0 | ||
46 | |||
47 | [074h 0116 12] Reset Register : [Generic Address Structure] | ||
48 | [074h 0116 1] Space ID : 00 [SystemMemory] | ||
49 | [075h 0117 1] Bit Width : 00 | ||
50 | [076h 0118 1] Bit Offset : 00 | ||
51 | [077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
52 | [078h 0120 8] Address : 0000000000000000 | ||
53 | |||
54 | [080h 0128 1] Value to cause reset : 00 | ||
55 | [081h 0129 2] ARM Flags (decoded below) : 0003 | ||
56 | PSCI Compliant : 1 | ||
57 | Must use HVC for PSCI : 1 | ||
58 | |||
59 | -[083h 0131 1] FADT Minor Revision : 00 | ||
60 | +[083h 0131 1] FADT Minor Revision : 03 | ||
61 | [084h 0132 8] FACS Address : 0000000000000000 | ||
62 | [08Ch 0140 8] DSDT Address : 0000000000000000 | ||
63 | [094h 0148 12] PM1A Event Block : [Generic Address Structure] | ||
64 | [094h 0148 1] Space ID : 00 [SystemMemory] | ||
65 | [095h 0149 1] Bit Width : 00 | ||
66 | [096h 0150 1] Bit Offset : 00 | ||
67 | [097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
68 | [098h 0152 8] Address : 0000000000000000 | ||
69 | |||
70 | [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] | ||
71 | [0A0h 0160 1] Space ID : 00 [SystemMemory] | ||
72 | [0A1h 0161 1] Bit Width : 00 | ||
73 | [0A2h 0162 1] Bit Offset : 00 | ||
74 | [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
75 | [0A4h 0164 8] Address : 0000000000000000 | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ | ||
78 | [0F5h 0245 1] Bit Width : 00 | ||
79 | [0F6h 0246 1] Bit Offset : 00 | ||
80 | [0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
81 | [0F8h 0248 8] Address : 0000000000000000 | ||
82 | |||
83 | [100h 0256 12] Sleep Status Register : [Generic Address Structure] | ||
84 | [100h 0256 1] Space ID : 00 [SystemMemory] | ||
85 | [101h 0257 1] Bit Width : 00 | ||
86 | [102h 0258 1] Bit Offset : 00 | ||
87 | [103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
88 | [104h 0260 8] Address : 0000000000000000 | ||
89 | |||
90 | [10Ch 0268 8] Hypervisor ID : 00000000554D4551 | ||
91 | |||
92 | Raw Table Data: Length 276 (0x114) | ||
93 | |||
94 | - 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS | ||
95 | + 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS | ||
96 | 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC | ||
97 | 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
98 | 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
99 | 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
100 | 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
101 | 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
102 | 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
103 | - 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
104 | + 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
105 | 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
106 | 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
107 | 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
108 | 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
109 | 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
110 | 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
111 | 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
112 | 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU | ||
113 | 0110: 00 00 00 00 // .... | ||
114 | |||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | /* | ||
117 | * Intel ACPI Component Architecture | ||
118 | * AML/ASL+ Disassembler version 20200925 (64-bit version) | ||
119 | * Copyright (c) 2000 - 2020 Intel Corporation | ||
120 | * | ||
121 | - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024 | ||
122 | + * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024 | ||
123 | * | ||
124 | * ACPI Data Table [GTDT] | ||
125 | * | ||
126 | * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue | ||
127 | */ | ||
128 | |||
129 | [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] | ||
130 | -[004h 0004 4] Table Length : 00000060 | ||
131 | -[008h 0008 1] Revision : 02 | ||
132 | -[009h 0009 1] Checksum : 9C | ||
133 | +[004h 0004 4] Table Length : 00000068 | ||
134 | +[008h 0008 1] Revision : 03 | ||
135 | +[009h 0009 1] Checksum : 93 | ||
136 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
137 | [010h 0016 8] Oem Table ID : "BXPC " | ||
138 | [018h 0024 4] Oem Revision : 00000001 | ||
139 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
140 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
141 | |||
142 | [024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF | ||
143 | [02Ch 0044 4] Reserved : 00000000 | ||
144 | |||
145 | [030h 0048 4] Secure EL1 Interrupt : 0000001D | ||
146 | [034h 0052 4] EL1 Flags (decoded below) : 00000000 | ||
147 | Trigger Mode : 0 | ||
148 | Polarity : 0 | ||
149 | Always On : 0 | ||
150 | |||
151 | [038h 0056 4] Non-Secure EL1 Interrupt : 0000001E | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | |||
154 | [040h 0064 4] Virtual Timer Interrupt : 0000001B | ||
155 | [044h 0068 4] VT Flags (decoded below) : 00000000 | ||
156 | Trigger Mode : 0 | ||
157 | Polarity : 0 | ||
158 | Always On : 0 | ||
159 | |||
160 | [048h 0072 4] Non-Secure EL2 Interrupt : 0000001A | ||
161 | [04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 | ||
162 | Trigger Mode : 0 | ||
163 | Polarity : 0 | ||
164 | Always On : 0 | ||
165 | [050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF | ||
166 | |||
167 | [058h 0088 4] Platform Timer Count : 00000000 | ||
168 | [05Ch 0092 4] Platform Timer Offset : 00000000 | ||
169 | +[060h 0096 4] Virtual EL2 Timer GSIV : 00000000 | ||
170 | +[064h 0100 4] Virtual EL2 Timer Flags : 00000000 | ||
171 | |||
172 | -Raw Table Data: Length 96 (0x60) | ||
173 | +Raw Table Data: Length 104 (0x68) | ||
174 | |||
175 | - 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS | ||
176 | + 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS | ||
177 | 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC | ||
178 | 0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................ | ||
179 | 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ | ||
180 | 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ | ||
181 | 0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................ | ||
182 | + 0060: 00 00 00 00 00 00 00 00 // ........ | ||
183 | |||
184 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
185 | Reviewed-by: Ard Biesheuvel <ardb@kernel.org> | ||
186 | Message-id: 20240122143537.233498-4-peter.maydell@linaro.org | ||
187 | --- | ||
188 | tests/qtest/bios-tables-test-allowed-diff.h | 2 -- | ||
189 | tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes | ||
190 | tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes | ||
191 | 3 files changed, 2 deletions(-) | ||
192 | |||
193 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
194 | index XXXXXXX..XXXXXXX 100644 | ||
195 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
196 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
197 | @@ -1,3 +1 @@ | ||
198 | /* List of comma-separated changed AML files to ignore */ | ||
199 | -"tests/data/acpi/virt/FACP", | ||
200 | -"tests/data/acpi/virt/GTDT", | ||
201 | diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP | ||
202 | index XXXXXXX..XXXXXXX 100644 | ||
203 | GIT binary patch | ||
204 | delta 25 | ||
205 | gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh | ||
206 | |||
207 | delta 28 | ||
208 | kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20 | ||
209 | |||
210 | diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT | ||
211 | index XXXXXXX..XXXXXXX 100644 | ||
212 | GIT binary patch | ||
213 | delta 25 | ||
214 | bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L | ||
215 | |||
216 | delta 16 | ||
217 | Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u | ||
218 | |||
219 | -- | ||
220 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The patchset adding the GMAC ethernet to this SoC crossed in the | ||
2 | mail with the patchset cleaning up the NIC handling. When we | ||
3 | create the GMAC modules we must call qemu_configure_nic_device() | ||
4 | so that the user has the opportunity to use the -nic commandline | ||
5 | option to create a network backend and connect it to the GMACs. | ||
1 | 6 | ||
7 | Add the missing call. | ||
8 | |||
9 | Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC") | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> | ||
12 | Message-id: 20240206171231.396392-2-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/npcm7xx.c | 1 + | ||
15 | 1 file changed, 1 insertion(+) | ||
16 | |||
17 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/npcm7xx.c | ||
20 | +++ b/hw/arm/npcm7xx.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
22 | for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { | ||
23 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]); | ||
24 | |||
25 | + qemu_configure_nic_device(DEVICE(sbd), false, NULL); | ||
26 | /* | ||
27 | * The device exists regardless of whether it's connected to a QEMU | ||
28 | * netdev backend. So always instantiate it even if there is no | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Currently QEMU will warn if there is a NIC on the board that | ||
2 | is not connected to a backend. By default the '-nic user' will | ||
3 | get used for all NICs, but if you manually connect a specific | ||
4 | NIC to a specific backend, then the other NICs on the board | ||
5 | have no backend and will be warned about: | ||
1 | 6 | ||
7 | qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer | ||
8 | qemu-system-arm: warning: nic npcm-gmac.0 has no peer | ||
9 | qemu-system-arm: warning: nic npcm-gmac.1 has no peer | ||
10 | |||
11 | So suppress those warnings by manually connecting every NIC | ||
12 | on the board to some backend. | ||
13 | |||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> | ||
16 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
17 | Message-id: 20240206171231.396392-3-peter.maydell@linaro.org | ||
18 | --- | ||
19 | tests/qtest/npcm7xx_emc-test.c | 5 ++++- | ||
20 | 1 file changed, 4 insertions(+), 1 deletion(-) | ||
21 | |||
22 | diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/tests/qtest/npcm7xx_emc-test.c | ||
25 | +++ b/tests/qtest/npcm7xx_emc-test.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line) | ||
27 | * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases | ||
28 | * in the 'model' field to specify the device to match. | ||
29 | */ | ||
30 | - g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ", | ||
31 | + g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d " | ||
32 | + "-nic user,model=npcm7xx-emc " | ||
33 | + "-nic user,model=npcm-gmac " | ||
34 | + "-nic user,model=npcm-gmac", | ||
35 | test_sockets[1], module_num); | ||
36 | |||
37 | g_test_queue_destroy(packet_test_clear, test_sockets); | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile |
---|---|---|---|
2 | CPU, and in fact if you try to do it we will assert: | ||
2 | 3 | ||
3 | Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. | 4 | #6 0x00007ffff4b95e96 in __GI___assert_fail |
5 | (assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101 | ||
6 | #7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600 | ||
7 | #8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595 | ||
8 | #9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512 | ||
4 | 9 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | We might call pmu_counter_enabled() on an M-profile CPU (for example |
6 | Message-id: 20180211205848.4568-2-richard.henderson@linaro.org | 11 | from the migration pre/post hooks in machine.c); this should always |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | return false because these CPUs don't set ARM_FEATURE_PMU. |
13 | |||
14 | Avoid the assertion by not calling arm_mdcr_el2_eff() before we | ||
15 | have done the early return for "PMU not present". | ||
16 | |||
17 | This fixes an assertion failure if you try to do a loadvm or | ||
18 | savevm for an M-profile board. | ||
19 | |||
20 | Cc: qemu-stable@nongnu.org | ||
21 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
25 | Message-id: 20240208153346.970021-1-peter.maydell@linaro.org | ||
9 | --- | 26 | --- |
10 | target/arm/helper.c | 8 ++++---- | 27 | target/arm/helper.c | 12 ++++++++++-- |
11 | 1 file changed, 4 insertions(+), 4 deletions(-) | 28 | 1 file changed, 10 insertions(+), 2 deletions(-) |
12 | 29 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 30 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
14 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 32 | --- a/target/arm/helper.c |
16 | +++ b/target/arm/helper.c | 33 | +++ b/target/arm/helper.c |
17 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 34 | @@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) |
18 | static const ARMCPRegInfo zcr_el1_reginfo = { | 35 | bool enabled, prohibited = false, filtered; |
19 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | 36 | bool secure = arm_is_secure(env); |
20 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | 37 | int el = arm_current_el(env); |
21 | - .access = PL1_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT, | 38 | - uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
22 | + .access = PL1_RW, .accessfn = zcr_access, | 39 | - uint8_t hpmn = mdcr_el2 & MDCR_HPMN; |
23 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | 40 | + uint64_t mdcr_el2; |
24 | .writefn = zcr_write, .raw_writefn = raw_write | 41 | + uint8_t hpmn; |
25 | }; | 42 | |
26 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el1_reginfo = { | 43 | + /* |
27 | static const ARMCPRegInfo zcr_el2_reginfo = { | 44 | + * We might be called for M-profile cores where MDCR_EL2 doesn't |
28 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 45 | + * exist and arm_mdcr_el2_eff() will assert, so this early-exit check |
29 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 46 | + * must be before we read that value. |
30 | - .access = PL2_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT, | 47 | + */ |
31 | + .access = PL2_RW, .accessfn = zcr_access, | 48 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
32 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | 49 | return false; |
33 | .writefn = zcr_write, .raw_writefn = raw_write | 50 | } |
34 | }; | 51 | |
35 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo zcr_el2_reginfo = { | 52 | + mdcr_el2 = arm_mdcr_el2_eff(env); |
36 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | 53 | + hpmn = mdcr_el2 & MDCR_HPMN; |
37 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | 54 | + |
38 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | 55 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
39 | - .access = PL2_RW, .type = ARM_CP_64BIT, | 56 | (counter < hpmn || counter == 31)) { |
40 | + .access = PL2_RW, | 57 | e = env->cp15.c9_pmcr & PMCRE; |
41 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | ||
42 | }; | ||
43 | |||
44 | static const ARMCPRegInfo zcr_el3_reginfo = { | ||
45 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
46 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
47 | - .access = PL3_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT, | ||
48 | + .access = PL3_RW, .accessfn = zcr_access, | ||
49 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
50 | .writefn = zcr_write, .raw_writefn = raw_write | ||
51 | }; | ||
52 | -- | 58 | -- |
53 | 2.16.1 | 59 | 2.34.1 |
54 | 60 | ||
55 | 61 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Nabih Estefan <nabihestefan@google.com> |
---|---|---|---|
2 | 2 | ||
3 | (qemu) info mtree | 3 | Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead |
4 | address-space: cpu-memory-0 | 4 | of 8xx. Also fix comments referencing this and values expecting 8xx. |
5 | 0000000000000000-ffffffffffffffff (prio 0, i/o): system | ||
6 | 0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom | ||
7 | - 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io | ||
8 | + 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io | ||
9 | 000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc | ||
10 | 000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1 | ||
11 | 000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2 | ||
12 | 5 | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8 |
14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 7 | Signed-Off-By: Nabih Estefan <nabihestefan@google.com> |
15 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | 8 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> |
16 | Message-id: 20180209085755.30414-3-f4bug@amsat.org | 9 | Message-id: 20240208194759.2858582-2-nabihestefan@google.com |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | [PMM: commit message tweaks] | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 13 | --- |
19 | include/hw/arm/aspeed_soc.h | 1 - | 14 | tests/qtest/npcm_gmac-test.c | 84 +----------------------------------- |
20 | hw/arm/aspeed_soc.c | 32 +++----------------------------- | 15 | tests/qtest/meson.build | 3 +- |
21 | 2 files changed, 3 insertions(+), 30 deletions(-) | 16 | 2 files changed, 4 insertions(+), 83 deletions(-) |
22 | 17 | ||
23 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 18 | diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c |
24 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/include/hw/arm/aspeed_soc.h | 20 | --- a/tests/qtest/npcm_gmac-test.c |
26 | +++ b/include/hw/arm/aspeed_soc.h | 21 | +++ b/tests/qtest/npcm_gmac-test.c |
27 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct TestData { |
28 | 23 | const GMACModule *module; | |
29 | /*< public >*/ | 24 | } TestData; |
30 | ARMCPU cpu; | 25 | |
31 | - MemoryRegion iomem; | 26 | -/* Values extracted from hw/arm/npcm8xx.c */ |
32 | MemoryRegion sram; | 27 | +/* Values extracted from hw/arm/npcm7xx.c */ |
33 | AspeedVICState vic; | 28 | static const GMACModule gmac_module_list[] = { |
34 | AspeedTimerCtrlState timerctrl; | 29 | { |
35 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | 30 | .irq = 14, |
36 | index XXXXXXX..XXXXXXX 100644 | 31 | @@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = { |
37 | --- a/hw/arm/aspeed_soc.c | 32 | .irq = 15, |
38 | +++ b/hw/arm/aspeed_soc.c | 33 | .base_addr = 0xf0804000 |
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | #include "qemu-common.h" | ||
41 | #include "cpu.h" | ||
42 | #include "exec/address-spaces.h" | ||
43 | +#include "hw/misc/unimp.h" | ||
44 | #include "hw/arm/aspeed_soc.h" | ||
45 | #include "hw/char/serial.h" | ||
46 | #include "qemu/log.h" | ||
47 | @@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = { | ||
48 | }, | 34 | }, |
35 | - { | ||
36 | - .irq = 16, | ||
37 | - .base_addr = 0xf0806000 | ||
38 | - }, | ||
39 | - { | ||
40 | - .irq = 17, | ||
41 | - .base_addr = 0xf0808000 | ||
42 | - } | ||
49 | }; | 43 | }; |
50 | 44 | ||
51 | -/* | 45 | /* Returns the index of the GMAC module. */ |
52 | - * IO handlers: simply catch any reads/writes to IO addresses that aren't | 46 | @@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, |
53 | - * handled by a device mapping. | 47 | return qtest_readl(qts, mod->base_addr + regno); |
54 | - */ | 48 | } |
55 | - | 49 | |
56 | -static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size) | 50 | -static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, |
51 | - NPCMRegister regno) | ||
57 | -{ | 52 | -{ |
58 | - qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | 53 | - uint32_t write_value = (regno & 0x3ffe00) >> 9; |
59 | - __func__, offset, size); | 54 | - qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); |
60 | - return 0; | 55 | - uint32_t read_offset = regno & 0x1ff; |
56 | - return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); | ||
61 | -} | 57 | -} |
62 | - | 58 | - |
63 | -static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value, | 59 | /* Check that GMAC registers are reset to default value */ |
64 | - unsigned size) | 60 | static void test_init(gconstpointer test_data) |
65 | -{ | 61 | { |
66 | - qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", | 62 | const TestData *td = test_data; |
67 | - __func__, offset, value, size); | 63 | const GMACModule *mod = td->module; |
68 | -} | 64 | - QTestState *qts = qtest_init("-machine npcm845-evb"); |
65 | + QTestState *qts = qtest_init("-machine npcm750-evb"); | ||
66 | |||
67 | #define CHECK_REG32(regno, value) \ | ||
68 | do { \ | ||
69 | g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \ | ||
70 | } while (0) | ||
71 | |||
72 | -#define CHECK_REG_PCS(regno, value) \ | ||
73 | - do { \ | ||
74 | - g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \ | ||
75 | - } while (0) | ||
69 | - | 76 | - |
70 | -static const MemoryRegionOps aspeed_soc_io_ops = { | 77 | CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); |
71 | - .read = aspeed_soc_io_read, | 78 | CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); |
72 | - .write = aspeed_soc_io_write, | 79 | CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0); |
73 | - .endianness = DEVICE_LITTLE_ENDIAN, | 80 | @@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data) |
74 | -}; | 81 | CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); |
82 | CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); | ||
83 | |||
84 | - /* TODO Add registers PCS */ | ||
85 | - if (mod->base_addr == 0xf0802000) { | ||
86 | - CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e); | ||
87 | - CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0); | ||
88 | - CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000); | ||
75 | - | 89 | - |
76 | static void aspeed_soc_init(Object *obj) | 90 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140); |
77 | { | 91 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109); |
78 | AspeedSoCState *s = ASPEED_SOC(obj); | 92 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e); |
79 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 93 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0); |
80 | Error *err = NULL, *local_err = NULL; | 94 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020); |
81 | 95 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0); | |
82 | /* IO space */ | 96 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0); |
83 | - memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL, | 97 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000); |
84 | - "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE); | 98 | - |
85 | - memory_region_add_subregion_overlap(get_system_memory(), | 99 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003); |
86 | - ASPEED_SOC_IOMEM_BASE, &s->iomem, -1); | 100 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038); |
87 | + create_unimplemented_device("aspeed_soc.io", | 101 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0); |
88 | + ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE); | 102 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038); |
89 | 103 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0); | |
90 | /* CPU */ | 104 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058); |
91 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | 105 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0); |
106 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048); | ||
107 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0); | ||
108 | - | ||
109 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400); | ||
110 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0); | ||
111 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a); | ||
112 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0); | ||
113 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0); | ||
114 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c); | ||
115 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0); | ||
116 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0); | ||
117 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0); | ||
118 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0); | ||
119 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010); | ||
120 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0); | ||
121 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0); | ||
122 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0); | ||
123 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a); | ||
124 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f); | ||
125 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001); | ||
126 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0); | ||
127 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0); | ||
128 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100); | ||
129 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100); | ||
130 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e); | ||
131 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100); | ||
132 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032); | ||
133 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001); | ||
134 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0); | ||
135 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019); | ||
136 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0); | ||
137 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0); | ||
138 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0); | ||
139 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0); | ||
140 | - } | ||
141 | - | ||
142 | qtest_quit(qts); | ||
143 | } | ||
144 | |||
145 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
146 | index XXXXXXX..XXXXXXX 100644 | ||
147 | --- a/tests/qtest/meson.build | ||
148 | +++ b/tests/qtest/meson.build | ||
149 | @@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \ | ||
150 | 'npcm7xx_sdhci-test', | ||
151 | 'npcm7xx_smbus-test', | ||
152 | 'npcm7xx_timer-test', | ||
153 | - 'npcm7xx_watchdog_timer-test'] + \ | ||
154 | + 'npcm7xx_watchdog_timer-test', | ||
155 | + 'npcm_gmac-test'] + \ | ||
156 | (slirp.found() ? ['npcm7xx_emc-test'] : []) | ||
157 | qtests_aspeed = \ | ||
158 | ['aspeed_hace-test', | ||
92 | -- | 159 | -- |
93 | 2.16.1 | 160 | 2.34.1 |
94 | |||
95 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Luc Michel <luc.michel@amd.com> | ||
1 | 2 | ||
3 | An access fault is raised when the Access Flag is not set in the | ||
4 | looked-up PTE and the AFFD field is not set in the corresponding context | ||
5 | descriptor. This was already implemented for stage 2. Implement it for | ||
6 | stage 1 as well. | ||
7 | |||
8 | Signed-off-by: Luc Michel <luc.michel@amd.com> | ||
9 | Reviewed-by: Mostafa Saleh <smostafa@google.com> | ||
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
11 | Tested-by: Mostafa Saleh <smostafa@google.com> | ||
12 | Message-id: 20240213082211.3330400-1-luc.michel@amd.com | ||
13 | [PMM: tweaked comment text] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/arm/smmuv3-internal.h | 1 + | ||
17 | include/hw/arm/smmu-common.h | 1 + | ||
18 | hw/arm/smmu-common.c | 11 +++++++++++ | ||
19 | hw/arm/smmuv3.c | 1 + | ||
20 | 4 files changed, 14 insertions(+) | ||
21 | |||
22 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/arm/smmuv3-internal.h | ||
25 | +++ b/hw/arm/smmuv3-internal.h | ||
26 | @@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste) | ||
27 | #define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) | ||
28 | #define CD_ENDI(x) extract32((x)->word[0], 15, 1) | ||
29 | #define CD_IPS(x) extract32((x)->word[1], 0 , 3) | ||
30 | +#define CD_AFFD(x) extract32((x)->word[1], 3 , 1) | ||
31 | #define CD_TBI(x) extract32((x)->word[1], 6 , 2) | ||
32 | #define CD_HD(x) extract32((x)->word[1], 10 , 1) | ||
33 | #define CD_HA(x) extract32((x)->word[1], 11 , 1) | ||
34 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/smmu-common.h | ||
37 | +++ b/include/hw/arm/smmu-common.h | ||
38 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg { | ||
39 | bool disabled; /* smmu is disabled */ | ||
40 | bool bypassed; /* translation is bypassed */ | ||
41 | bool aborted; /* translation is aborted */ | ||
42 | + bool affd; /* AF fault disable */ | ||
43 | uint32_t iotlb_hits; /* counts IOTLB hits */ | ||
44 | uint32_t iotlb_misses; /* counts IOTLB misses*/ | ||
45 | /* Used by stage-1 only. */ | ||
46 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/smmu-common.c | ||
49 | +++ b/hw/arm/smmu-common.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, | ||
51 | pte_addr, pte, iova, gpa, | ||
52 | block_size >> 20); | ||
53 | } | ||
54 | + | ||
55 | + /* | ||
56 | + * QEMU does not currently implement HTTU, so if AFFD and PTE.AF | ||
57 | + * are 0 we take an Access flag fault. (5.4. Context Descriptor) | ||
58 | + * An Access flag fault takes priority over a Permission fault. | ||
59 | + */ | ||
60 | + if (!PTE_AF(pte) && !cfg->affd) { | ||
61 | + info->type = SMMU_PTW_ERR_ACCESS; | ||
62 | + goto error; | ||
63 | + } | ||
64 | + | ||
65 | ap = PTE_AP(pte); | ||
66 | if (is_permission_fault(ap, perm)) { | ||
67 | info->type = SMMU_PTW_ERR_PERMISSION; | ||
68 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/arm/smmuv3.c | ||
71 | +++ b/hw/arm/smmuv3.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) | ||
73 | cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); | ||
74 | cfg->tbi = CD_TBI(cd); | ||
75 | cfg->asid = CD_ASID(cd); | ||
76 | + cfg->affd = CD_AFFD(cd); | ||
77 | |||
78 | trace_smmuv3_decode_cd(cfg->oas); | ||
79 | |||
80 | -- | ||
81 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Pekka Enberg <penberg@iki.fi> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds a "cpu-type" property to BCM2836 SoC in preparation for | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | reusing the code for the Raspberry Pi 3, which has a different processor | ||
5 | model. | ||
6 | |||
7 | Signed-off-by: Pekka Enberg <penberg@iki.fi> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20240213155214.13619-2-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 7 | --- |
11 | include/hw/arm/bcm2836.h | 1 + | 8 | hw/arm/stellaris.c | 6 ++++-- |
12 | hw/arm/bcm2836.c | 17 +++++++++-------- | 9 | 1 file changed, 4 insertions(+), 2 deletions(-) |
13 | hw/arm/raspi.c | 3 +++ | ||
14 | 3 files changed, 13 insertions(+), 8 deletions(-) | ||
15 | 10 | ||
16 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | 11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/bcm2836.h | 13 | --- a/hw/arm/stellaris.c |
19 | +++ b/include/hw/arm/bcm2836.h | 14 | +++ b/hw/arm/stellaris.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State { | 15 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level) |
21 | DeviceState parent_obj; | 16 | } |
22 | /*< public >*/ | 17 | } |
23 | 18 | ||
24 | + char *cpu_type; | 19 | -static void stellaris_adc_reset(StellarisADCState *s) |
25 | uint32_t enabled_cpus; | 20 | +static void stellaris_adc_reset_hold(Object *obj) |
26 | |||
27 | ARMCPU cpus[BCM2836_NCPUS]; | ||
28 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/arm/bcm2836.c | ||
31 | +++ b/hw/arm/bcm2836.c | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | static void bcm2836_init(Object *obj) | ||
34 | { | 21 | { |
35 | BCM2836State *s = BCM2836(obj); | 22 | + StellarisADCState *s = STELLARIS_ADC(obj); |
36 | - int n; | 23 | int n; |
37 | - | 24 | |
38 | - for (n = 0; n < BCM2836_NCPUS; n++) { | 25 | for (n = 0; n < 4; n++) { |
39 | - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | 26 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj) |
40 | - "cortex-a15-" TYPE_ARM_CPU); | 27 | memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, |
41 | - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | 28 | "adc", 0x1000); |
42 | - &error_abort); | 29 | sysbus_init_mmio(sbd, &s->iomem); |
43 | - } | 30 | - stellaris_adc_reset(s); |
44 | 31 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); | |
45 | object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); | ||
46 | object_property_add_child(obj, "control", OBJECT(&s->control), NULL); | ||
47 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
48 | |||
49 | /* common peripherals from bcm2835 */ | ||
50 | |||
51 | + obj = OBJECT(dev); | ||
52 | + for (n = 0; n < BCM2836_NCPUS; n++) { | ||
53 | + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), | ||
54 | + s->cpu_type); | ||
55 | + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), | ||
56 | + &error_abort); | ||
57 | + } | ||
58 | + | ||
59 | obj = object_property_get_link(OBJECT(dev), "ram", &err); | ||
60 | if (obj == NULL) { | ||
61 | error_setg(errp, "%s: required ram link not found: %s", | ||
62 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp) | ||
63 | } | 32 | } |
64 | 33 | ||
65 | static Property bcm2836_props[] = { | 34 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = { |
66 | + DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), | 35 | static void stellaris_adc_class_init(ObjectClass *klass, void *data) |
67 | DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), | 36 | { |
68 | DEFINE_PROP_END_OF_LIST() | 37 | DeviceClass *dc = DEVICE_CLASS(klass); |
69 | }; | 38 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
70 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 39 | |
71 | index XXXXXXX..XXXXXXX 100644 | 40 | + rc->phases.hold = stellaris_adc_reset_hold; |
72 | --- a/hw/arm/raspi.c | 41 | dc->vmsd = &vmstate_stellaris_adc; |
73 | +++ b/hw/arm/raspi.c | 42 | } |
74 | @@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine) | 43 | |
75 | /* Setup the SOC */ | ||
76 | object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), | ||
77 | &error_abort); | ||
78 | + object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", | ||
79 | + &error_abort); | ||
80 | object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", | ||
81 | &error_abort); | ||
82 | object_property_set_int(OBJECT(&s->soc), 0xa21041, "board-rev", | ||
83 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | ||
84 | mc->no_parallel = 1; | ||
85 | mc->no_floppy = 1; | ||
86 | mc->no_cdrom = 1; | ||
87 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | ||
88 | mc->max_cpus = BCM2836_NCPUS; | ||
89 | mc->min_cpus = BCM2836_NCPUS; | ||
90 | mc->default_cpus = BCM2836_NCPUS; | ||
91 | -- | 44 | -- |
92 | 2.16.1 | 45 | 2.34.1 |
93 | 46 | ||
94 | 47 | diff view generated by jsdifflib |
1 | From: Pekka Enberg <penberg@iki.fi> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The | 3 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> |
4 | differences to Pi 2 are: | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | 5 | Message-id: 20240213155214.13619-3-philmd@linaro.org | |
6 | - Firmware address | ||
7 | - Board ID | ||
8 | - Board revision | ||
9 | |||
10 | The CPU is different too, but that's going to be configured as part of | ||
11 | the machine default CPU when we introduce a new machine type. | ||
12 | |||
13 | The patch was written from scratch by me but the logic is similar to | ||
14 | Zoltán Baldaszti's previous work, which I used as a reference (with | ||
15 | permission from the author): | ||
16 | |||
17 | https://github.com/bztsrc/qemu-raspi3 | ||
18 | |||
19 | Signed-off-by: Pekka Enberg <penberg@iki.fi> | ||
20 | [PMM: fixed trailing whitespace on one line] | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | --- | 8 | --- |
24 | hw/arm/raspi.c | 31 +++++++++++++++++++++---------- | 9 | hw/arm/stellaris.c | 26 ++++++++++++++++++++++---- |
25 | 1 file changed, 21 insertions(+), 10 deletions(-) | 10 | 1 file changed, 22 insertions(+), 4 deletions(-) |
26 | 11 | ||
27 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 12 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
28 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/arm/raspi.c | 14 | --- a/hw/arm/stellaris.c |
30 | +++ b/hw/arm/raspi.c | 15 | +++ b/hw/arm/stellaris.c |
31 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj) |
32 | * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft | 17 | s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); |
33 | * Written by Andrew Baumann | ||
34 | * | ||
35 | + * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti | ||
36 | + * Upstream code cleanup (c) 2018 Pekka Enberg | ||
37 | + * | ||
38 | * This code is licensed under the GNU GPLv2 and later. | ||
39 | */ | ||
40 | |||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ | ||
43 | #define MVBAR_ADDR 0x400 /* secure vectors */ | ||
44 | #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ | ||
45 | -#define FIRMWARE_ADDR 0x8000 /* Pi loads kernel.img here by default */ | ||
46 | +#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ | ||
47 | +#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ | ||
48 | |||
49 | /* Table of Linux board IDs for different Pi versions */ | ||
50 | -static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43}; | ||
51 | +static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; | ||
52 | |||
53 | typedef struct RasPiState { | ||
54 | BCM2836State soc; | ||
55 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
56 | binfo.secure_board_setup = true; | ||
57 | binfo.secure_boot = true; | ||
58 | |||
59 | - /* Pi2 requires SMP setup */ | ||
60 | - if (version == 2) { | ||
61 | + /* Pi2 and Pi3 requires SMP setup */ | ||
62 | + if (version >= 2) { | ||
63 | binfo.smp_loader_start = SMPBOOT_ADDR; | ||
64 | binfo.write_secondary_boot = write_smpboot; | ||
65 | binfo.secondary_cpu_reset_hook = reset_secondary; | ||
66 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
67 | * the normal Linux boot process | ||
68 | */ | ||
69 | if (machine->firmware) { | ||
70 | + hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2; | ||
71 | /* load the firmware image (typically kernel.img) */ | ||
72 | - r = load_image_targphys(machine->firmware, FIRMWARE_ADDR, | ||
73 | - ram_size - FIRMWARE_ADDR); | ||
74 | + r = load_image_targphys(machine->firmware, firmware_addr, | ||
75 | + ram_size - firmware_addr); | ||
76 | if (r < 0) { | ||
77 | error_report("Failed to load firmware from %s", machine->firmware); | ||
78 | exit(1); | ||
79 | } | ||
80 | |||
81 | - binfo.entry = FIRMWARE_ADDR; | ||
82 | + binfo.entry = firmware_addr; | ||
83 | binfo.firmware_loaded = true; | ||
84 | } else { | ||
85 | binfo.kernel_filename = machine->kernel_filename; | ||
86 | @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) | ||
87 | arm_load_kernel(ARM_CPU(first_cpu), &binfo); | ||
88 | } | 18 | } |
89 | 19 | ||
90 | -static void raspi2_init(MachineState *machine) | 20 | -/* I2C controller. */ |
91 | +static void raspi_init(MachineState *machine, int version) | 21 | +/* |
22 | + * I2C controller. | ||
23 | + * ??? For now we only implement the master interface. | ||
24 | + */ | ||
25 | |||
26 | #define TYPE_STELLARIS_I2C "stellaris-i2c" | ||
27 | OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) | ||
28 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset, | ||
29 | stellaris_i2c_update(s); | ||
30 | } | ||
31 | |||
32 | -static void stellaris_i2c_reset(stellaris_i2c_state *s) | ||
33 | +static void stellaris_i2c_reset_enter(Object *obj, ResetType type) | ||
92 | { | 34 | { |
93 | RasPiState *s = g_new0(RasPiState, 1); | 35 | + stellaris_i2c_state *s = STELLARIS_I2C(obj); |
94 | uint32_t vcram_size; | 36 | + |
95 | @@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine) | 37 | if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) |
96 | &error_abort); | 38 | i2c_end_transfer(s->bus); |
97 | object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", | ||
98 | &error_abort); | ||
99 | - object_property_set_int(OBJECT(&s->soc), 0xa21041, "board-rev", | ||
100 | + int board_rev = version == 3 ? 0xa02082 : 0xa21041; | ||
101 | + object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", | ||
102 | &error_abort); | ||
103 | object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); | ||
104 | |||
105 | @@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine) | ||
106 | |||
107 | vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", | ||
108 | &error_abort); | ||
109 | - setup_boot(machine, 2, machine->ram_size - vcram_size); | ||
110 | + setup_boot(machine, version, machine->ram_size - vcram_size); | ||
111 | +} | 39 | +} |
112 | + | 40 | + |
113 | +static void raspi2_init(MachineState *machine) | 41 | +static void stellaris_i2c_reset_hold(Object *obj) |
114 | +{ | 42 | +{ |
115 | + raspi_init(machine, 2); | 43 | + stellaris_i2c_state *s = STELLARIS_I2C(obj); |
44 | |||
45 | s->msa = 0; | ||
46 | s->mcs = 0; | ||
47 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s) | ||
48 | s->mimr = 0; | ||
49 | s->mris = 0; | ||
50 | s->mcr = 0; | ||
51 | +} | ||
52 | + | ||
53 | +static void stellaris_i2c_reset_exit(Object *obj) | ||
54 | +{ | ||
55 | + stellaris_i2c_state *s = STELLARIS_I2C(obj); | ||
56 | + | ||
57 | stellaris_i2c_update(s); | ||
116 | } | 58 | } |
117 | 59 | ||
118 | static void raspi2_machine_init(MachineClass *mc) | 60 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj) |
61 | memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, | ||
62 | "i2c", 0x1000); | ||
63 | sysbus_init_mmio(sbd, &s->iomem); | ||
64 | - /* ??? For now we only implement the master interface. */ | ||
65 | - stellaris_i2c_reset(s); | ||
66 | } | ||
67 | |||
68 | /* Analogue to Digital Converter. This is only partially implemented, | ||
69 | @@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init) | ||
70 | static void stellaris_i2c_class_init(ObjectClass *klass, void *data) | ||
71 | { | ||
72 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
73 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
74 | |||
75 | + rc->phases.enter = stellaris_i2c_reset_enter; | ||
76 | + rc->phases.hold = stellaris_i2c_reset_hold; | ||
77 | + rc->phases.exit = stellaris_i2c_reset_exit; | ||
78 | dc->vmsd = &vmstate_stellaris_i2c; | ||
79 | } | ||
80 | |||
119 | -- | 81 | -- |
120 | 2.16.1 | 82 | 2.34.1 |
121 | 83 | ||
122 | 84 | diff view generated by jsdifflib |
1 | In commit commit 3b2e934463121 we added support for the AIRCR | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | register holding state, but forgot to add it to the vmstate | ||
3 | structs. Since it only holds r/w state if the security extension | ||
4 | is implemented, we can just add it to vmstate_m_security. | ||
5 | 2 | ||
3 | QDev objects created with qdev_new() need to manually add | ||
4 | their parent relationship with object_property_add_child(). | ||
5 | |||
6 | This commit plug the devices which aren't part of the SoC; | ||
7 | they will be plugged into a SoC container in the next one. | ||
8 | |||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20240213155214.13619-4-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180209165810.6668-10-peter.maydell@linaro.org | ||
9 | --- | 13 | --- |
10 | target/arm/machine.c | 4 ++++ | 14 | hw/arm/stellaris.c | 4 ++++ |
11 | 1 file changed, 4 insertions(+) | 15 | 1 file changed, 4 insertions(+) |
12 | 16 | ||
13 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 17 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/machine.c | 19 | --- a/hw/arm/stellaris.c |
16 | +++ b/target/arm/machine.c | 20 | +++ b/hw/arm/stellaris.c |
17 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 21 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
18 | VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), | 22 | &error_fatal); |
19 | VMSTATE_UINT32(env.sau.ctrl, ARMCPU), | 23 | |
20 | VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), | 24 | ssddev = qdev_new("ssd0323"); |
21 | + /* AIRCR is not secure-only, but our implementation is R/O if the | 25 | + object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev)); |
22 | + * security extension is unimplemented, so we migrate it here. | 26 | qdev_prop_set_uint8(ssddev, "cs", 1); |
23 | + */ | 27 | qdev_realize_and_unref(ssddev, bus, &error_fatal); |
24 | + VMSTATE_UINT32(env.v7m.aircr, ARMCPU), | 28 | |
25 | VMSTATE_END_OF_LIST() | 29 | gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); |
26 | } | 30 | + object_property_add_child(OBJECT(ms), "splitter", |
27 | }; | 31 | + OBJECT(gpio_d_splitter)); |
32 | qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); | ||
33 | qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); | ||
34 | qdev_connect_gpio_out( | ||
35 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
36 | DeviceState *gpad; | ||
37 | |||
38 | gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); | ||
39 | + object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad)); | ||
40 | for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { | ||
41 | qlist_append_int(gpad_keycode_list, gpad_keycode[i]); | ||
42 | } | ||
28 | -- | 43 | -- |
29 | 2.16.1 | 44 | 2.34.1 |
30 | 45 | ||
31 | 46 | diff view generated by jsdifflib |
1 | From: Pekka Enberg <penberg@iki.fi> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds a "raspi3" machine type, which can now be selected as | 3 | QDev objects created with qdev_new() need to manually add |
4 | the machine to run on by users via the "-M" command line option to QEMU. | 4 | their parent relationship with object_property_add_child(). |
5 | 5 | ||
6 | The machine type does *not* ignore memory transaction failures so we | 6 | Since we don't model the SoC, just use a QOM container. |
7 | likely need to add some dummy devices later when people run something | ||
8 | more complicated than what I'm using for testing. | ||
9 | 7 | ||
10 | Signed-off-by: Pekka Enberg <penberg@iki.fi> | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | [PMM: added #ifdef TARGET_AARCH64 so we don't provide the 64-bit | ||
12 | board in the 32-bit only arm-softmmu build.] | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Message-id: 20240213155214.13619-5-philmd@linaro.org |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 12 | --- |
17 | hw/arm/raspi.c | 23 +++++++++++++++++++++++ | 13 | hw/arm/stellaris.c | 11 ++++++++++- |
18 | 1 file changed, 23 insertions(+) | 14 | 1 file changed, 10 insertions(+), 1 deletion(-) |
19 | 15 | ||
20 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | 16 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
21 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/arm/raspi.c | 18 | --- a/hw/arm/stellaris.c |
23 | +++ b/hw/arm/raspi.c | 19 | +++ b/hw/arm/stellaris.c |
24 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | 20 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
25 | mc->ignore_memory_transaction_failures = true; | 21 | * 400fe000 system control |
26 | }; | 22 | */ |
27 | DEFINE_MACHINE("raspi2", raspi2_machine_init) | 23 | |
24 | + Object *soc_container; | ||
25 | DeviceState *gpio_dev[7], *nvic; | ||
26 | qemu_irq gpio_in[7][8]; | ||
27 | qemu_irq gpio_out[7][8]; | ||
28 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
29 | flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; | ||
30 | sram_size = ((board->dc0 >> 18) + 1) * 1024; | ||
31 | |||
32 | + soc_container = object_new("container"); | ||
33 | + object_property_add_child(OBJECT(ms), "soc", soc_container); | ||
28 | + | 34 | + |
29 | +#ifdef TARGET_AARCH64 | 35 | /* Flash programming is done via the SCU, so pretend it is ROM. */ |
30 | +static void raspi3_init(MachineState *machine) | 36 | memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, |
31 | +{ | 37 | &error_fatal); |
32 | + raspi_init(machine, 3); | 38 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
33 | +} | 39 | * need its sysclk output. |
34 | + | 40 | */ |
35 | +static void raspi3_machine_init(MachineClass *mc) | 41 | ssys_dev = qdev_new(TYPE_STELLARIS_SYS); |
36 | +{ | 42 | + object_property_add_child(soc_container, "sys", OBJECT(ssys_dev)); |
37 | + mc->desc = "Raspberry Pi 3"; | 43 | |
38 | + mc->init = raspi3_init; | 44 | /* |
39 | + mc->block_default_type = IF_SD; | 45 | * Most devices come preprogrammed with a MAC address in the user data. |
40 | + mc->no_parallel = 1; | 46 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
41 | + mc->no_floppy = 1; | 47 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); |
42 | + mc->no_cdrom = 1; | 48 | |
43 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); | 49 | nvic = qdev_new(TYPE_ARMV7M); |
44 | + mc->max_cpus = BCM2836_NCPUS; | 50 | + object_property_add_child(soc_container, "v7m", OBJECT(nvic)); |
45 | + mc->min_cpus = BCM2836_NCPUS; | 51 | qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); |
46 | + mc->default_cpus = BCM2836_NCPUS; | 52 | qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); |
47 | + mc->default_ram_size = 1024 * 1024 * 1024; | 53 | qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); |
48 | +} | 54 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
49 | +DEFINE_MACHINE("raspi3", raspi3_machine_init) | 55 | |
50 | +#endif | 56 | dev = qdev_new(TYPE_STELLARIS_GPTM); |
57 | sbd = SYS_BUS_DEVICE(dev); | ||
58 | + object_property_add_child(soc_container, "gptm[*]", OBJECT(dev)); | ||
59 | qdev_connect_clock_in(dev, "clk", | ||
60 | qdev_get_clock_out(ssys_dev, "SYSCLK")); | ||
61 | sysbus_realize_and_unref(sbd, &error_fatal); | ||
62 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
63 | |||
64 | if (board->dc1 & (1 << 3)) { /* watchdog present */ | ||
65 | dev = qdev_new(TYPE_LUMINARY_WATCHDOG); | ||
66 | - | ||
67 | + object_property_add_child(soc_container, "wdg", OBJECT(dev)); | ||
68 | qdev_connect_clock_in(dev, "WDOGCLK", | ||
69 | qdev_get_clock_out(ssys_dev, "SYSCLK")); | ||
70 | |||
71 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
72 | SysBusDevice *sbd; | ||
73 | |||
74 | dev = qdev_new("pl011_luminary"); | ||
75 | + object_property_add_child(soc_container, "uart[*]", OBJECT(dev)); | ||
76 | sbd = SYS_BUS_DEVICE(dev); | ||
77 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); | ||
78 | sysbus_realize_and_unref(sbd, &error_fatal); | ||
79 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
80 | DeviceState *enet; | ||
81 | |||
82 | enet = qdev_new("stellaris_enet"); | ||
83 | + object_property_add_child(soc_container, "enet", OBJECT(enet)); | ||
84 | if (nd) { | ||
85 | qdev_set_nic_properties(enet, nd); | ||
86 | } else { | ||
51 | -- | 87 | -- |
52 | 2.16.1 | 88 | 2.34.1 |
53 | 89 | ||
54 | 90 | diff view generated by jsdifflib |
1 | In commit 50f11062d4c896 we added support for MSR/MRS access | 1 | We support two different encodings for the AArch32 IMPDEF |
---|---|---|---|
2 | to the NS banked special registers, but we forgot to implement | 2 | CBAR register -- older cores like the Cortex A9, A7, A15 |
3 | the support for writing to CONTROL_NS. Correct the omission. | 3 | have this at 4, c15, c0, 0; newer cores like the |
4 | Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0. | ||
5 | |||
6 | When we implemented this we picked which encoding to | ||
7 | use based on whether the CPU set ARM_FEATURE_AARCH64. | ||
8 | However this isn't right for three cases: | ||
9 | * the qemu-system-arm 'max' CPU, which is supposed to be | ||
10 | a variant on a Cortex-A57; it ought to use the same | ||
11 | encoding the A57 does and which the AArch64 'max' | ||
12 | exposes to AArch32 guest code | ||
13 | * the Cortex-R52, which is AArch32-only but has the CBAR | ||
14 | at the newer encoding (and where we incorrectly are | ||
15 | not yet setting ARM_FEATURE_CBAR_RO anyway) | ||
16 | * any possible future support for other v8 AArch32 | ||
17 | only CPUs, or for supporting "boot the CPU into | ||
18 | AArch32 mode" on our existing cores like the A57 etc | ||
19 | |||
20 | Make the decision of the encoding be based on whether | ||
21 | the CPU implements the ARM_FEATURE_V8 flag instead. | ||
22 | |||
23 | This changes the behaviour only for the qemu-system-arm | ||
24 | '-cpu max'. We don't expect anybody to be relying on the | ||
25 | old behaviour because: | ||
26 | * it's not what the real hardware Cortex-A57 does | ||
27 | (and that's what our ID register claims we are) | ||
28 | * we don't implement the memory-mapped GICv3 support | ||
29 | which is the only thing that exists at the peripheral | ||
30 | base address pointed to by the register | ||
4 | 31 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 33 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20180209165810.6668-8-peter.maydell@linaro.org | 34 | Message-id: 20240206132931.38376-2-peter.maydell@linaro.org |
8 | --- | 35 | --- |
9 | target/arm/helper.c | 10 ++++++++++ | 36 | target/arm/helper.c | 2 +- |
10 | 1 file changed, 10 insertions(+) | 37 | 1 file changed, 1 insertion(+), 1 deletion(-) |
11 | 38 | ||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 39 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
13 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.c | 41 | --- a/target/arm/helper.c |
15 | +++ b/target/arm/helper.c | 42 | +++ b/target/arm/helper.c |
16 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 43 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
17 | } | 44 | * AArch64 cores we might need to add a specific feature flag |
18 | env->v7m.faultmask[M_REG_NS] = val & 1; | 45 | * to indicate cores with "flavour 2" CBAR. |
19 | return; | 46 | */ |
20 | + case 0x94: /* CONTROL_NS */ | 47 | - if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
21 | + if (!env->v7m.secure) { | 48 | + if (arm_feature(env, ARM_FEATURE_V8)) { |
22 | + return; | 49 | /* 32 bit view is [31:18] 0...0 [43:32]. */ |
23 | + } | 50 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) |
24 | + write_v7m_control_spsel_for_secstate(env, | 51 | | extract64(cpu->reset_cbar, 32, 12); |
25 | + val & R_V7M_CONTROL_SPSEL_MASK, | ||
26 | + M_REG_NS); | ||
27 | + env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; | ||
28 | + env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; | ||
29 | + return; | ||
30 | case 0x98: /* SP_NS */ | ||
31 | { | ||
32 | /* This gives the non-secure SP selected based on whether we're | ||
33 | -- | 52 | -- |
34 | 2.16.1 | 53 | 2.34.1 |
35 | |||
36 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The Cortex-R52 implements the Configuration Base Address Register | ||
2 | (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU | ||
3 | type, so that our implementation provides the register and the | ||
4 | associated qdev property. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20240206132931.38376-3-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/cpu32.c | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/tcg/cpu32.c | ||
16 | +++ b/target/arm/tcg/cpu32.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) | ||
18 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | ||
19 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
20 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
21 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
22 | cpu->midr = 0x411fd133; /* r1p3 */ | ||
23 | cpu->revidr = 0x00000000; | ||
24 | cpu->reset_fpsid = 0x41034023; | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Add the Cortex-R52 IMPDEF sysregs, by defining them here and | ||
2 | also by enabling the AUXCR feature which defines the ACTLR | ||
3 | and HACTLR registers. As is our usual practice, we make these | ||
4 | simple reads-as-zero stubs for now. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20240206132931.38376-4-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++ | ||
11 | 1 file changed, 108 insertions(+) | ||
12 | |||
13 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/tcg/cpu32.c | ||
16 | +++ b/target/arm/tcg/cpu32.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj) | ||
18 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); | ||
19 | } | ||
20 | |||
21 | +static const ARMCPRegInfo cortex_r52_cp_reginfo[] = { | ||
22 | + { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15, | ||
23 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
24 | + { .name = "IMP_ATCMREGIONR", | ||
25 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | ||
26 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
27 | + { .name = "IMP_BTCMREGIONR", | ||
28 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | ||
29 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
30 | + { .name = "IMP_CTCMREGIONR", | ||
31 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2, | ||
32 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
33 | + { .name = "IMP_CSCTLR", | ||
34 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0, | ||
35 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
36 | + { .name = "IMP_BPCTLR", | ||
37 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1, | ||
38 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
39 | + { .name = "IMP_MEMPROTCLR", | ||
40 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2, | ||
41 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
42 | + { .name = "IMP_SLAVEPCTLR", | ||
43 | + .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0, | ||
44 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
45 | + { .name = "IMP_PERIPHREGIONR", | ||
46 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, | ||
47 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
48 | + { .name = "IMP_FLASHIFREGIONR", | ||
49 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1, | ||
50 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
51 | + { .name = "IMP_BUILDOPTR", | ||
52 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
53 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
54 | + { .name = "IMP_PINOPTR", | ||
55 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | ||
56 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
57 | + { .name = "IMP_QOSR", | ||
58 | + .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1, | ||
59 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
60 | + { .name = "IMP_BUSTIMEOUTR", | ||
61 | + .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2, | ||
62 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
63 | + { .name = "IMP_INTMONR", | ||
64 | + .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4, | ||
65 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
66 | + { .name = "IMP_ICERR0", | ||
67 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0, | ||
68 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
69 | + { .name = "IMP_ICERR1", | ||
70 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1, | ||
71 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
72 | + { .name = "IMP_DCERR0", | ||
73 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0, | ||
74 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
75 | + { .name = "IMP_DCERR1", | ||
76 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1, | ||
77 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
78 | + { .name = "IMP_TCMERR0", | ||
79 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0, | ||
80 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
81 | + { .name = "IMP_TCMERR1", | ||
82 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1, | ||
83 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
84 | + { .name = "IMP_TCMSYNDR0", | ||
85 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2, | ||
86 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
87 | + { .name = "IMP_TCMSYNDR1", | ||
88 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3, | ||
89 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
90 | + { .name = "IMP_FLASHERR0", | ||
91 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0, | ||
92 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
93 | + { .name = "IMP_FLASHERR1", | ||
94 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1, | ||
95 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
96 | + { .name = "IMP_CDBGDR0", | ||
97 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0, | ||
98 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
99 | + { .name = "IMP_CBDGBR1", | ||
100 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1, | ||
101 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
102 | + { .name = "IMP_TESTR0", | ||
103 | + .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0, | ||
104 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
105 | + { .name = "IMP_TESTR1", | ||
106 | + .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1, | ||
107 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
108 | + { .name = "IMP_CDBGDCI", | ||
109 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0, | ||
110 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
111 | + { .name = "IMP_CDBGDCT", | ||
112 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0, | ||
113 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
114 | + { .name = "IMP_CDBGICT", | ||
115 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1, | ||
116 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
117 | + { .name = "IMP_CDBGDCD", | ||
118 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0, | ||
119 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
120 | + { .name = "IMP_CDBGICD", | ||
121 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1, | ||
122 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
123 | +}; | ||
124 | + | ||
125 | + | ||
126 | static void cortex_r52_initfn(Object *obj) | ||
127 | { | ||
128 | ARMCPU *cpu = ARM_CPU(obj); | ||
129 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) | ||
130 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
131 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
132 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
133 | + set_feature(&cpu->env, ARM_FEATURE_AUXCR); | ||
134 | cpu->midr = 0x411fd133; /* r1p3 */ | ||
135 | cpu->revidr = 0x00000000; | ||
136 | cpu->reset_fpsid = 0x41034023; | ||
137 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) | ||
138 | |||
139 | cpu->pmsav7_dregion = 16; | ||
140 | cpu->pmsav8r_hdregion = 16; | ||
141 | + | ||
142 | + define_arm_cp_regs(cpu, cortex_r52_cp_reginfo); | ||
143 | } | ||
144 | |||
145 | static void cortex_r5f_initfn(Object *obj) | ||
146 | -- | ||
147 | 2.34.1 | diff view generated by jsdifflib |
1 | For M profile cores, cache maintenance operations are done by | 1 | Architecturally, the AArch32 MSR/MRS to/from banked register |
---|---|---|---|
2 | writing to special registers in the system register space. | 2 | instructions are UNPREDICTABLE for attempts to access a banked |
3 | For QEMU, cache operations are always NOPs, since we don't | 3 | register that the guest could access in a more direct way (e.g. |
4 | implement the cache. Implementing these explicitly avoids | 4 | using this insn to access r8_fiq when already in FIQ mode). QEMU has |
5 | a spurious LOG_GUEST_ERROR when the guest uses them. | 5 | chosen to UNDEF on all of these. |
6 | |||
7 | However, for the case of accessing SPSR_hyp from hyp mode, it turns | ||
8 | out that real hardware permits this, with the same effect as if the | ||
9 | guest had directly written to SPSR. Further, there is some | ||
10 | guest code out there that assumes it can do this, because it | ||
11 | happens to work on hardware: an example Cortex-R52 startup code | ||
12 | fragment uses this, and it got copied into various other places, | ||
13 | including Zephyr. Zephyr was fixed to not use this: | ||
14 | https://github.com/zephyrproject-rtos/zephyr/issues/47330 | ||
15 | but other examples are still out there, like the selftest | ||
16 | binary for the MPS3-AN536. | ||
17 | |||
18 | For convenience of being able to run guest code, permit | ||
19 | this UNPREDICTABLE access instead of UNDEFing it. | ||
6 | 20 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20180209165810.6668-4-peter.maydell@linaro.org | 23 | Message-id: 20240206132931.38376-5-peter.maydell@linaro.org |
10 | --- | 24 | --- |
11 | hw/intc/armv7m_nvic.c | 12 ++++++++++++ | 25 | target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------ |
12 | 1 file changed, 12 insertions(+) | 26 | target/arm/tcg/translate.c | 19 +++++++++++------ |
27 | 2 files changed, 43 insertions(+), 19 deletions(-) | ||
13 | 28 | ||
14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 29 | diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/intc/armv7m_nvic.c | 31 | --- a/target/arm/tcg/op_helper.c |
17 | +++ b/hw/intc/armv7m_nvic.c | 32 | +++ b/target/arm/tcg/op_helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 33 | @@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, |
34 | */ | ||
35 | int curmode = env->uncached_cpsr & CPSR_M; | ||
36 | |||
37 | - if (regno == 17) { | ||
38 | - /* ELR_Hyp: a special case because access from tgtmode is OK */ | ||
39 | - if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { | ||
40 | - goto undef; | ||
41 | + if (tgtmode == ARM_CPU_MODE_HYP) { | ||
42 | + /* | ||
43 | + * Handle Hyp target regs first because some are special cases | ||
44 | + * which don't want the usual "not accessible from tgtmode" check. | ||
45 | + */ | ||
46 | + switch (regno) { | ||
47 | + case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */ | ||
48 | + if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { | ||
49 | + goto undef; | ||
50 | + } | ||
51 | + break; | ||
52 | + case 13: | ||
53 | + if (curmode != ARM_CPU_MODE_MON) { | ||
54 | + goto undef; | ||
55 | + } | ||
56 | + break; | ||
57 | + default: | ||
58 | + g_assert_not_reached(); | ||
59 | } | ||
60 | return; | ||
61 | } | ||
62 | @@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, | ||
63 | } | ||
64 | } | ||
65 | |||
66 | - if (tgtmode == ARM_CPU_MODE_HYP) { | ||
67 | - /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */ | ||
68 | - if (curmode != ARM_CPU_MODE_MON) { | ||
69 | - goto undef; | ||
70 | - } | ||
71 | - } | ||
72 | - | ||
73 | return; | ||
74 | |||
75 | undef: | ||
76 | @@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, | ||
77 | |||
78 | switch (regno) { | ||
79 | case 16: /* SPSRs */ | ||
80 | - env->banked_spsr[bank_number(tgtmode)] = value; | ||
81 | + if (tgtmode == (env->uncached_cpsr & CPSR_M)) { | ||
82 | + /* Only happens for SPSR_Hyp access in Hyp mode */ | ||
83 | + env->spsr = value; | ||
84 | + } else { | ||
85 | + env->banked_spsr[bank_number(tgtmode)] = value; | ||
86 | + } | ||
87 | break; | ||
88 | case 17: /* ELR_Hyp */ | ||
89 | env->elr_el[2] = value; | ||
90 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) | ||
91 | |||
92 | switch (regno) { | ||
93 | case 16: /* SPSRs */ | ||
94 | - return env->banked_spsr[bank_number(tgtmode)]; | ||
95 | + if (tgtmode == (env->uncached_cpsr & CPSR_M)) { | ||
96 | + /* Only happens for SPSR_Hyp access in Hyp mode */ | ||
97 | + return env->spsr; | ||
98 | + } else { | ||
99 | + return env->banked_spsr[bank_number(tgtmode)]; | ||
100 | + } | ||
101 | case 17: /* ELR_Hyp */ | ||
102 | return env->elr_el[2]; | ||
103 | case 13: | ||
104 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/target/arm/tcg/translate.c | ||
107 | +++ b/target/arm/tcg/translate.c | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
109 | break; | ||
110 | case ARM_CPU_MODE_HYP: | ||
111 | /* | ||
112 | - * SPSR_hyp and r13_hyp can only be accessed from Monitor mode | ||
113 | - * (and so we can forbid accesses from EL2 or below). elr_hyp | ||
114 | - * can be accessed also from Hyp mode, so forbid accesses from | ||
115 | - * EL0 or EL1. | ||
116 | + * r13_hyp can only be accessed from Monitor mode, and so we | ||
117 | + * can forbid accesses from EL2 or below. | ||
118 | + * elr_hyp can be accessed also from Hyp mode, so forbid | ||
119 | + * accesses from EL0 or EL1. | ||
120 | + * SPSR_hyp is supposed to be in the same category as r13_hyp | ||
121 | + * and UNPREDICTABLE if accessed from anything except Monitor | ||
122 | + * mode. However there is some real-world code that will do | ||
123 | + * it because at least some hardware happens to permit the | ||
124 | + * access. (Notably a standard Cortex-R52 startup code fragment | ||
125 | + * does this.) So we permit SPSR_hyp from Hyp mode also, to allow | ||
126 | + * this (incorrect) guest code to run. | ||
127 | */ | ||
128 | - if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 || | ||
129 | - (s->current_el < 3 && *regno != 17)) { | ||
130 | + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 | ||
131 | + || (s->current_el < 3 && *regno != 16 && *regno != 17)) { | ||
132 | goto undef; | ||
19 | } | 133 | } |
20 | break; | 134 | break; |
21 | } | ||
22 | + case 0xf50: /* ICIALLU */ | ||
23 | + case 0xf58: /* ICIMVAU */ | ||
24 | + case 0xf5c: /* DCIMVAC */ | ||
25 | + case 0xf60: /* DCISW */ | ||
26 | + case 0xf64: /* DCCMVAU */ | ||
27 | + case 0xf68: /* DCCMVAC */ | ||
28 | + case 0xf6c: /* DCCSW */ | ||
29 | + case 0xf70: /* DCCIMVAC */ | ||
30 | + case 0xf74: /* DCCISW */ | ||
31 | + case 0xf78: /* BPIALL */ | ||
32 | + /* Cache and branch predictor maintenance: for QEMU these always NOP */ | ||
33 | + break; | ||
34 | default: | ||
35 | bad_offset: | ||
36 | qemu_log_mask(LOG_GUEST_ERROR, | ||
37 | -- | 135 | -- |
38 | 2.16.1 | 136 | 2.34.1 |
39 | |||
40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We currently guard the CFG3 register read with | ||
2 | (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) | ||
3 | which is clearly wrong as it is never true. | ||
1 | 4 | ||
5 | This register is present on all board types except AN524 | ||
6 | and AN527; correct the condition. | ||
7 | |||
8 | Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547") | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20240206132931.38376-6-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/misc/mps2-scc.c | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/misc/mps2-scc.c | ||
20 | +++ b/hw/misc/mps2-scc.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
22 | r = s->cfg2; | ||
23 | break; | ||
24 | case A_CFG3: | ||
25 | - if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) { | ||
26 | + if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) { | ||
27 | /* CFG3 reserved on AN524 */ | ||
28 | goto bad_offset; | ||
29 | } | ||
30 | -- | ||
31 | 2.34.1 | ||
32 | |||
33 | diff view generated by jsdifflib |
1 | M profile cores have a similar setup for cache ID registers | 1 | The MPS SCC device has a lot of different flavours for the various |
---|---|---|---|
2 | to A profile: | 2 | different MPS FPGA images, which look mostly similar but have |
3 | * Cache Level ID Register (CLIDR) is a fixed value | 3 | differences in how particular registers are handled. Currently we |
4 | * Cache Type Register (CTR) is a fixed value | 4 | deal with this with a lot of open-coded checks on scc_partno(), but |
5 | * Cache Size ID Registers (CCSIDR) are a bank of registers; | 5 | as we add more board types this is getting a bit hard to read. |
6 | which one you see is selected by the Cache Size Selection | ||
7 | Register (CSSELR) | ||
8 | 6 | ||
9 | The only difference is that they're in the NVIC memory mapped | 7 | Factor out the conditions into some functions which we can |
10 | register space rather than being coprocessor registers. | 8 | give more descriptive names to. |
11 | Implement the M profile view of them. | ||
12 | |||
13 | Since neither Cortex-M3 nor Cortex-M4 implement caches, | ||
14 | we don't need to update their init functions and can leave | ||
15 | the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. | ||
16 | Newer cores (like the Cortex-M33) will want to be able to | ||
17 | set these ID registers to non-zero values, though. | ||
18 | 9 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
21 | Message-id: 20180209165810.6668-6-peter.maydell@linaro.org | 13 | Message-id: 20240206132931.38376-7-peter.maydell@linaro.org |
22 | --- | 14 | --- |
23 | target/arm/cpu.h | 26 ++++++++++++++++++++++++++ | 15 | hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++-------------- |
24 | hw/intc/armv7m_nvic.c | 16 ++++++++++++++++ | 16 | 1 file changed, 31 insertions(+), 14 deletions(-) |
25 | target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++ | ||
26 | 3 files changed, 78 insertions(+) | ||
27 | 17 | ||
28 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 18 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c |
29 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/cpu.h | 20 | --- a/hw/misc/mps2-scc.c |
31 | +++ b/target/arm/cpu.h | 21 | +++ b/hw/misc/mps2-scc.c |
32 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 22 | @@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s) |
33 | uint32_t faultmask[M_REG_NUM_BANKS]; | 23 | return extract32(s->id, 4, 8); |
34 | uint32_t aircr; /* only holds r/w state if security extn implemented */ | ||
35 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | ||
36 | + uint32_t csselr[M_REG_NUM_BANKS]; | ||
37 | } v7m; | ||
38 | |||
39 | /* Information associated with an exception about to be taken: | ||
40 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) | ||
41 | FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) | ||
42 | FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) | ||
43 | |||
44 | +/* v7M CLIDR bits */ | ||
45 | +FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) | ||
46 | +FIELD(V7M_CLIDR, LOUIS, 21, 3) | ||
47 | +FIELD(V7M_CLIDR, LOC, 24, 3) | ||
48 | +FIELD(V7M_CLIDR, LOUU, 27, 3) | ||
49 | +FIELD(V7M_CLIDR, ICB, 30, 2) | ||
50 | + | ||
51 | +FIELD(V7M_CSSELR, IND, 0, 1) | ||
52 | +FIELD(V7M_CSSELR, LEVEL, 1, 3) | ||
53 | +/* We use the combination of InD and Level to index into cpu->ccsidr[]; | ||
54 | + * define a mask for this and check that it doesn't permit running off | ||
55 | + * the end of the array. | ||
56 | + */ | ||
57 | +FIELD(V7M_CSSELR, INDEX, 0, 4) | ||
58 | + | ||
59 | +QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); | ||
60 | + | ||
61 | /* If adding a feature bit which corresponds to a Linux ELF | ||
62 | * HWCAP bit, remember to update the feature-bit-to-hwcap | ||
63 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | ||
64 | @@ -XXX,XX +XXX,XX @@ static inline int arm_debug_target_el(CPUARMState *env) | ||
65 | } | ||
66 | } | 24 | } |
67 | 25 | ||
68 | +static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) | 26 | +/* Is CFG_REG2 present? */ |
27 | +static bool have_cfg2(MPS2SCC *s) | ||
69 | +{ | 28 | +{ |
70 | + /* If all the CLIDR.Ctypem bits are 0 there are no caches, and | 29 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; |
71 | + * CSSELR is RAZ/WI. | ||
72 | + */ | ||
73 | + return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; | ||
74 | +} | 30 | +} |
75 | + | 31 | + |
76 | static inline bool aa64_generate_debug_exceptions(CPUARMState *env) | 32 | +/* Is CFG_REG3 present? */ |
77 | { | 33 | +static bool have_cfg3(MPS2SCC *s) |
78 | if (arm_is_secure(env)) { | ||
79 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/intc/armv7m_nvic.c | ||
82 | +++ b/hw/intc/armv7m_nvic.c | ||
83 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
84 | return cpu->id_isar4; | ||
85 | case 0xd74: /* ISAR5. */ | ||
86 | return cpu->id_isar5; | ||
87 | + case 0xd78: /* CLIDR */ | ||
88 | + return cpu->clidr; | ||
89 | + case 0xd7c: /* CTR */ | ||
90 | + return cpu->ctr; | ||
91 | + case 0xd80: /* CSSIDR */ | ||
92 | + { | ||
93 | + int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; | ||
94 | + return cpu->ccsidr[idx]; | ||
95 | + } | ||
96 | + case 0xd84: /* CSSELR */ | ||
97 | + return cpu->env.v7m.csselr[attrs.secure]; | ||
98 | /* TODO: Implement debug registers. */ | ||
99 | case 0xd90: /* MPU_TYPE */ | ||
100 | /* Unified MPU; if the MPU is not present this value is zero */ | ||
101 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
102 | qemu_log_mask(LOG_UNIMP, | ||
103 | "NVIC: Aux fault status registers unimplemented\n"); | ||
104 | break; | ||
105 | + case 0xd84: /* CSSELR */ | ||
106 | + if (!arm_v7m_csselr_razwi(cpu)) { | ||
107 | + cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; | ||
108 | + } | ||
109 | + break; | ||
110 | case 0xd90: /* MPU_TYPE */ | ||
111 | return; /* RO */ | ||
112 | case 0xd94: /* MPU_CTRL */ | ||
113 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
114 | index XXXXXXX..XXXXXXX 100644 | ||
115 | --- a/target/arm/machine.c | ||
116 | +++ b/target/arm/machine.c | ||
117 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = { | ||
118 | } | ||
119 | }; | ||
120 | |||
121 | +/* CSSELR is in a subsection because we didn't implement it previously. | ||
122 | + * Migration from an old implementation will leave it at zero, which | ||
123 | + * is OK since the only CPUs in the old implementation make the | ||
124 | + * register RAZ/WI. | ||
125 | + * Since there was no version of QEMU which implemented the CSSELR for | ||
126 | + * just non-secure, we transfer both banks here rather than putting | ||
127 | + * the secure banked version in the m-security subsection. | ||
128 | + */ | ||
129 | +static bool csselr_vmstate_validate(void *opaque, int version_id) | ||
130 | +{ | 34 | +{ |
131 | + ARMCPU *cpu = opaque; | 35 | + return scc_partno(s) != 0x524 && scc_partno(s) != 0x547; |
132 | + | ||
133 | + return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK | ||
134 | + && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; | ||
135 | +} | 36 | +} |
136 | + | 37 | + |
137 | +static bool m_csselr_needed(void *opaque) | 38 | +/* Is CFG_REG5 present? */ |
39 | +static bool have_cfg5(MPS2SCC *s) | ||
138 | +{ | 40 | +{ |
139 | + ARMCPU *cpu = opaque; | 41 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; |
140 | + | ||
141 | + return !arm_v7m_csselr_razwi(cpu); | ||
142 | +} | 42 | +} |
143 | + | 43 | + |
144 | +static const VMStateDescription vmstate_m_csselr = { | 44 | +/* Is CFG_REG6 present? */ |
145 | + .name = "cpu/m/csselr", | 45 | +static bool have_cfg6(MPS2SCC *s) |
146 | + .version_id = 1, | 46 | +{ |
147 | + .minimum_version_id = 1, | 47 | + return scc_partno(s) == 0x524; |
148 | + .needed = m_csselr_needed, | 48 | +} |
149 | + .fields = (VMStateField[]) { | ||
150 | + VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), | ||
151 | + VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), | ||
152 | + VMSTATE_END_OF_LIST() | ||
153 | + } | ||
154 | +}; | ||
155 | + | 49 | + |
156 | static const VMStateDescription vmstate_m = { | 50 | /* Handle a write via the SYS_CFG channel to the specified function/device. |
157 | .name = "cpu/m", | 51 | * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). |
158 | .version_id = 4, | 52 | */ |
159 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 53 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) |
160 | }, | 54 | r = s->cfg1; |
161 | .subsections = (const VMStateDescription*[]) { | 55 | break; |
162 | &vmstate_m_faultmask_primask, | 56 | case A_CFG2: |
163 | + &vmstate_m_csselr, | 57 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { |
164 | NULL | 58 | - /* CFG2 reserved on other boards */ |
165 | } | 59 | + if (!have_cfg2(s)) { |
166 | }; | 60 | goto bad_offset; |
61 | } | ||
62 | r = s->cfg2; | ||
63 | break; | ||
64 | case A_CFG3: | ||
65 | - if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) { | ||
66 | - /* CFG3 reserved on AN524 */ | ||
67 | + if (!have_cfg3(s)) { | ||
68 | goto bad_offset; | ||
69 | } | ||
70 | /* These are user-settable DIP switches on the board. We don't | ||
71 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
72 | r = s->cfg4; | ||
73 | break; | ||
74 | case A_CFG5: | ||
75 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
76 | - /* CFG5 reserved on other boards */ | ||
77 | + if (!have_cfg5(s)) { | ||
78 | goto bad_offset; | ||
79 | } | ||
80 | r = s->cfg5; | ||
81 | break; | ||
82 | case A_CFG6: | ||
83 | - if (scc_partno(s) != 0x524) { | ||
84 | - /* CFG6 reserved on other boards */ | ||
85 | + if (!have_cfg6(s)) { | ||
86 | goto bad_offset; | ||
87 | } | ||
88 | r = s->cfg6; | ||
89 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
90 | } | ||
91 | break; | ||
92 | case A_CFG2: | ||
93 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
94 | - /* CFG2 reserved on other boards */ | ||
95 | + if (!have_cfg2(s)) { | ||
96 | goto bad_offset; | ||
97 | } | ||
98 | /* AN524: QSPI Select signal */ | ||
99 | s->cfg2 = value; | ||
100 | break; | ||
101 | case A_CFG5: | ||
102 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
103 | - /* CFG5 reserved on other boards */ | ||
104 | + if (!have_cfg5(s)) { | ||
105 | goto bad_offset; | ||
106 | } | ||
107 | /* AN524: ACLK frequency in Hz */ | ||
108 | s->cfg5 = value; | ||
109 | break; | ||
110 | case A_CFG6: | ||
111 | - if (scc_partno(s) != 0x524) { | ||
112 | - /* CFG6 reserved on other boards */ | ||
113 | + if (!have_cfg6(s)) { | ||
114 | goto bad_offset; | ||
115 | } | ||
116 | /* AN524: Clock divider for BRAM */ | ||
167 | -- | 117 | -- |
168 | 2.16.1 | 118 | 2.34.1 |
169 | 119 | ||
170 | 120 | diff view generated by jsdifflib |
1 | In commit abc24d86cc0364f we accidentally broke migration of | 1 | The MPS2 SCC device is broadly the same for all FPGA images, but has |
---|---|---|---|
2 | the stack pointer value for the mode (process, handler) the CPU | 2 | minor differences in the behaviour of the CFG registers depending on |
3 | is not currently running as. (The commit correctly removed the | 3 | the image. In many cases we don't really care about the functionality |
4 | no-longer-used v7m.current_sp flag from the VMState but also | 4 | controlled by these registers and a reads-as-written or similar |
5 | deleted the still very much in use v7m.other_sp SP value field.) | 5 | behaviour is sufficient for the moment. |
6 | 6 | ||
7 | Add a subsection to migrate it again. (We don't need to care | 7 | For the AN536 the required behaviour is: |
8 | about trying to retain compatibility with pre-abc24d86cc0364f | 8 | |
9 | versions of QEMU, because that commit bumped the version_id | 9 | * A_CFG0 has CPU reset and halt bits |
10 | and we've since bumped it again a couple of times.) | 10 | - implement as reads-as-written for the moment |
11 | * A_CFG1 has flash or ATCM address 0 remap handling | ||
12 | - QEMU doesn't model this; implement as reads-as-written | ||
13 | * A_CFG2 has QSPI select (like AN524) | ||
14 | - implemented (no behaviour, as with AN524) | ||
15 | * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits" | ||
16 | - QEMU doesn't care about these, so use the existing | ||
17 | RAZ behaviour for convenience | ||
18 | * A_CFG4 is board rev (like all other images) | ||
19 | - no change needed | ||
20 | * A_CFG5 is ACLK frq in hz (like AN524) | ||
21 | - implemented as reads-as-written, as for other boards | ||
22 | * A_CFG6 is core 0 vector table base address | ||
23 | - implemented as reads-as-written for the moment | ||
24 | * A_CFG7 is core 1 vector table base address | ||
25 | - implemented as reads-as-written for the moment | ||
26 | |||
27 | Make the changes necessary for this; leave TODO comments where | ||
28 | appropriate to indicate where we might want to come back and | ||
29 | implement things like CPU reset. | ||
30 | |||
31 | The other aspects of the device specific to this FPGA image (like the | ||
32 | values of the board ID and similar registers) will be set via the | ||
33 | device's qdev properties. | ||
11 | 34 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 35 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 36 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20180209165810.6668-11-peter.maydell@linaro.org | 37 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
38 | Message-id: 20240206132931.38376-8-peter.maydell@linaro.org | ||
15 | --- | 39 | --- |
16 | target/arm/machine.c | 11 +++++++++++ | 40 | include/hw/misc/mps2-scc.h | 1 + |
17 | 1 file changed, 11 insertions(+) | 41 | hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++---- |
18 | 42 | 2 files changed, 92 insertions(+), 10 deletions(-) | |
19 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 43 | |
44 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/machine.c | 46 | --- a/include/hw/misc/mps2-scc.h |
22 | +++ b/target/arm/machine.c | 47 | +++ b/include/hw/misc/mps2-scc.h |
23 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_scr = { | 48 | @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { |
24 | } | 49 | uint32_t cfg4; |
25 | }; | 50 | uint32_t cfg5; |
26 | 51 | uint32_t cfg6; | |
27 | +static const VMStateDescription vmstate_m_other_sp = { | 52 | + uint32_t cfg7; |
28 | + .name = "cpu/m/other-sp", | 53 | uint32_t cfgdata_rtn; |
54 | uint32_t cfgdata_out; | ||
55 | uint32_t cfgctrl; | ||
56 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/misc/mps2-scc.c | ||
59 | +++ b/hw/misc/mps2-scc.c | ||
60 | @@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc) | ||
61 | REG32(CFG4, 0x10) | ||
62 | REG32(CFG5, 0x14) | ||
63 | REG32(CFG6, 0x18) | ||
64 | +REG32(CFG7, 0x1c) | ||
65 | REG32(CFGDATA_RTN, 0xa0) | ||
66 | REG32(CFGDATA_OUT, 0xa4) | ||
67 | REG32(CFGCTRL, 0xa8) | ||
68 | @@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s) | ||
69 | /* Is CFG_REG2 present? */ | ||
70 | static bool have_cfg2(MPS2SCC *s) | ||
71 | { | ||
72 | - return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; | ||
73 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 || | ||
74 | + scc_partno(s) == 0x536; | ||
75 | } | ||
76 | |||
77 | /* Is CFG_REG3 present? */ | ||
78 | static bool have_cfg3(MPS2SCC *s) | ||
79 | { | ||
80 | - return scc_partno(s) != 0x524 && scc_partno(s) != 0x547; | ||
81 | + return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 && | ||
82 | + scc_partno(s) != 0x536; | ||
83 | } | ||
84 | |||
85 | /* Is CFG_REG5 present? */ | ||
86 | static bool have_cfg5(MPS2SCC *s) | ||
87 | { | ||
88 | - return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; | ||
89 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 || | ||
90 | + scc_partno(s) == 0x536; | ||
91 | } | ||
92 | |||
93 | /* Is CFG_REG6 present? */ | ||
94 | static bool have_cfg6(MPS2SCC *s) | ||
95 | { | ||
96 | - return scc_partno(s) == 0x524; | ||
97 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x536; | ||
98 | +} | ||
99 | + | ||
100 | +/* Is CFG_REG7 present? */ | ||
101 | +static bool have_cfg7(MPS2SCC *s) | ||
102 | +{ | ||
103 | + return scc_partno(s) == 0x536; | ||
104 | +} | ||
105 | + | ||
106 | +/* Does CFG_REG0 drive the 'remap' GPIO output? */ | ||
107 | +static bool cfg0_is_remap(MPS2SCC *s) | ||
108 | +{ | ||
109 | + return scc_partno(s) != 0x536; | ||
110 | +} | ||
111 | + | ||
112 | +/* Is CFG_REG1 driving a set of LEDs? */ | ||
113 | +static bool cfg1_is_leds(MPS2SCC *s) | ||
114 | +{ | ||
115 | + return scc_partno(s) != 0x536; | ||
116 | } | ||
117 | |||
118 | /* Handle a write via the SYS_CFG channel to the specified function/device. | ||
119 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
120 | if (!have_cfg3(s)) { | ||
121 | goto bad_offset; | ||
122 | } | ||
123 | - /* These are user-settable DIP switches on the board. We don't | ||
124 | + /* | ||
125 | + * These are user-settable DIP switches on the board. We don't | ||
126 | * model that, so just return zeroes. | ||
127 | + * | ||
128 | + * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing | ||
129 | + * bits". These change which part of the DDR4 the motherboard | ||
130 | + * configuration controller can see in its memory map (see the | ||
131 | + * appnote section 2.4). QEMU doesn't model the MCC at all, so these | ||
132 | + * bits are not interesting to us; read-as-zero is as good as anything | ||
133 | + * else. | ||
134 | */ | ||
135 | r = 0; | ||
136 | break; | ||
137 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
138 | } | ||
139 | r = s->cfg6; | ||
140 | break; | ||
141 | + case A_CFG7: | ||
142 | + if (!have_cfg7(s)) { | ||
143 | + goto bad_offset; | ||
144 | + } | ||
145 | + r = s->cfg7; | ||
146 | + break; | ||
147 | case A_CFGDATA_RTN: | ||
148 | r = s->cfgdata_rtn; | ||
149 | break; | ||
150 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
151 | * we always reflect bit 0 in the 'remap' GPIO output line, | ||
152 | * and let the board wire it up or not as it chooses. | ||
153 | * TODO on some boards bit 1 is CPU_WAIT. | ||
154 | + * | ||
155 | + * TODO: on the AN536 this register controls reset and halt | ||
156 | + * for both CPUs. For the moment we don't implement this, so the | ||
157 | + * register just reads as written. | ||
158 | */ | ||
159 | s->cfg0 = value; | ||
160 | - qemu_set_irq(s->remap, s->cfg0 & 1); | ||
161 | + if (cfg0_is_remap(s)) { | ||
162 | + qemu_set_irq(s->remap, s->cfg0 & 1); | ||
163 | + } | ||
164 | break; | ||
165 | case A_CFG1: | ||
166 | s->cfg1 = value; | ||
167 | - for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { | ||
168 | - led_set_state(s->led[i], extract32(value, i, 1)); | ||
169 | + /* | ||
170 | + * On most boards this register drives LEDs. | ||
171 | + * | ||
172 | + * TODO: for AN536 this controls whether flash and ATCM are | ||
173 | + * enabled or disabled on reset. QEMU doesn't model this, and | ||
174 | + * always wires up RAM in the ATCM area and ROM in the flash area. | ||
175 | + */ | ||
176 | + if (cfg1_is_leds(s)) { | ||
177 | + for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { | ||
178 | + led_set_state(s->led[i], extract32(value, i, 1)); | ||
179 | + } | ||
180 | } | ||
181 | break; | ||
182 | case A_CFG2: | ||
183 | if (!have_cfg2(s)) { | ||
184 | goto bad_offset; | ||
185 | } | ||
186 | - /* AN524: QSPI Select signal */ | ||
187 | + /* AN524, AN536: QSPI Select signal */ | ||
188 | s->cfg2 = value; | ||
189 | break; | ||
190 | case A_CFG5: | ||
191 | if (!have_cfg5(s)) { | ||
192 | goto bad_offset; | ||
193 | } | ||
194 | - /* AN524: ACLK frequency in Hz */ | ||
195 | + /* AN524, AN536: ACLK frequency in Hz */ | ||
196 | s->cfg5 = value; | ||
197 | break; | ||
198 | case A_CFG6: | ||
199 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
200 | goto bad_offset; | ||
201 | } | ||
202 | /* AN524: Clock divider for BRAM */ | ||
203 | + /* AN536: Core 0 vector table base address */ | ||
204 | + s->cfg6 = value; | ||
205 | + break; | ||
206 | + case A_CFG7: | ||
207 | + if (!have_cfg7(s)) { | ||
208 | + goto bad_offset; | ||
209 | + } | ||
210 | + /* AN536: Core 1 vector table base address */ | ||
211 | s->cfg6 = value; | ||
212 | break; | ||
213 | case A_CFGDATA_OUT: | ||
214 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj) | ||
215 | g_free(s->oscclk_reset); | ||
216 | } | ||
217 | |||
218 | +static bool cfg7_needed(void *opaque) | ||
219 | +{ | ||
220 | + MPS2SCC *s = opaque; | ||
221 | + | ||
222 | + return have_cfg7(s); | ||
223 | +} | ||
224 | + | ||
225 | +static const VMStateDescription vmstate_cfg7 = { | ||
226 | + .name = "mps2-scc/cfg7", | ||
29 | + .version_id = 1, | 227 | + .version_id = 1, |
30 | + .minimum_version_id = 1, | 228 | + .minimum_version_id = 1, |
31 | + .fields = (VMStateField[]) { | 229 | + .needed = cfg7_needed, |
32 | + VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), | 230 | + .fields = (const VMStateField[]) { |
231 | + VMSTATE_UINT32(cfg7, MPS2SCC), | ||
33 | + VMSTATE_END_OF_LIST() | 232 | + VMSTATE_END_OF_LIST() |
34 | + } | 233 | + } |
35 | +}; | 234 | +}; |
36 | + | 235 | + |
37 | static const VMStateDescription vmstate_m = { | 236 | static const VMStateDescription mps2_scc_vmstate = { |
38 | .name = "cpu/m", | 237 | .name = "mps2-scc", |
39 | .version_id = 4, | 238 | .version_id = 3, |
40 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 239 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = { |
41 | &vmstate_m_faultmask_primask, | 240 | VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, |
42 | &vmstate_m_csselr, | 241 | 0, vmstate_info_uint32, uint32_t), |
43 | &vmstate_m_scr, | 242 | VMSTATE_END_OF_LIST() |
44 | + &vmstate_m_other_sp, | 243 | + }, |
45 | NULL | 244 | + .subsections = (const VMStateDescription * const []) { |
245 | + &vmstate_cfg7, | ||
246 | + NULL | ||
46 | } | 247 | } |
47 | }; | 248 | }; |
249 | |||
48 | -- | 250 | -- |
49 | 2.16.1 | 251 | 2.34.1 |
50 | 252 | ||
51 | 253 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | The AN536 is another FPGA image for the MPS3 development board. Unlike | |
2 | the existing FPGA images we already model, this board uses a Cortex-R | ||
3 | family CPU, and it does not use any equivalent to the M-profile | ||
4 | "Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c. | ||
5 | It's therefore more convenient for us to model it as a completely | ||
6 | separate C file. | ||
7 | |||
8 | This commit adds the basic skeleton of the board model, and the | ||
9 | code to create all the RAM and ROM. We assume that we're probably | ||
10 | going to want to add more images in future, so use the same | ||
11 | base class/subclass setup that mps2-tz.c uses, even though at | ||
12 | the moment there's only a single subclass. | ||
13 | |||
14 | Following commits will add the CPUs and the peripherals. | ||
15 | |||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
18 | Message-id: 20240206132931.38376-9-peter.maydell@linaro.org | ||
19 | --- | ||
20 | MAINTAINERS | 3 +- | ||
21 | configs/devices/arm-softmmu/default.mak | 1 + | ||
22 | hw/arm/mps3r.c | 239 ++++++++++++++++++++++++ | ||
23 | hw/arm/Kconfig | 5 + | ||
24 | hw/arm/meson.build | 1 + | ||
25 | 5 files changed, 248 insertions(+), 1 deletion(-) | ||
26 | create mode 100644 hw/arm/mps3r.c | ||
27 | |||
28 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/MAINTAINERS | ||
31 | +++ b/MAINTAINERS | ||
32 | @@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h | ||
33 | F: hw/pci-host/designware.c | ||
34 | F: include/hw/pci-host/designware.h | ||
35 | |||
36 | -MPS2 | ||
37 | +MPS2 / MPS3 | ||
38 | M: Peter Maydell <peter.maydell@linaro.org> | ||
39 | L: qemu-arm@nongnu.org | ||
40 | S: Maintained | ||
41 | F: hw/arm/mps2.c | ||
42 | F: hw/arm/mps2-tz.c | ||
43 | +F: hw/arm/mps3r.c | ||
44 | F: hw/misc/mps2-*.c | ||
45 | F: include/hw/misc/mps2-*.h | ||
46 | F: hw/arm/armsse.c | ||
47 | diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/configs/devices/arm-softmmu/default.mak | ||
50 | +++ b/configs/devices/arm-softmmu/default.mak | ||
51 | @@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y | ||
52 | # CONFIG_INTEGRATOR=n | ||
53 | # CONFIG_FSL_IMX31=n | ||
54 | # CONFIG_MUSICPAL=n | ||
55 | +# CONFIG_MPS3R=n | ||
56 | # CONFIG_MUSCA=n | ||
57 | # CONFIG_CHEETAH=n | ||
58 | # CONFIG_SX1=n | ||
59 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c | ||
60 | new file mode 100644 | ||
61 | index XXXXXXX..XXXXXXX | ||
62 | --- /dev/null | ||
63 | +++ b/hw/arm/mps3r.c | ||
64 | @@ -XXX,XX +XXX,XX @@ | ||
65 | +/* | ||
66 | + * Arm MPS3 board emulation for Cortex-R-based FPGA images. | ||
67 | + * (For M-profile images see mps2.c and mps2tz.c.) | ||
68 | + * | ||
69 | + * Copyright (c) 2017 Linaro Limited | ||
70 | + * Written by Peter Maydell | ||
71 | + * | ||
72 | + * This program is free software; you can redistribute it and/or modify | ||
73 | + * it under the terms of the GNU General Public License version 2 or | ||
74 | + * (at your option) any later version. | ||
75 | + */ | ||
76 | + | ||
77 | +/* | ||
78 | + * The MPS3 is an FPGA based dev board. This file handles FPGA images | ||
79 | + * which use the Cortex-R CPUs. We model these separately from the | ||
80 | + * M-profile images, because on M-profile the FPGA image is based on | ||
81 | + * a "Subsystem for Embedded" which is similar to an SoC, whereas | ||
82 | + * the R-profile FPGA images don't have that abstraction layer. | ||
83 | + * | ||
84 | + * We model the following FPGA images here: | ||
85 | + * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536 | ||
86 | + * | ||
87 | + * Application Note AN536: | ||
88 | + * https://developer.arm.com/documentation/dai0536/latest/ | ||
89 | + */ | ||
90 | + | ||
91 | +#include "qemu/osdep.h" | ||
92 | +#include "qemu/units.h" | ||
93 | +#include "qapi/error.h" | ||
94 | +#include "exec/address-spaces.h" | ||
95 | +#include "cpu.h" | ||
96 | +#include "hw/boards.h" | ||
97 | +#include "hw/arm/boot.h" | ||
98 | + | ||
99 | +/* Define the layout of RAM and ROM in a board */ | ||
100 | +typedef struct RAMInfo { | ||
101 | + const char *name; | ||
102 | + hwaddr base; | ||
103 | + hwaddr size; | ||
104 | + int mrindex; /* index into rams[]; -1 for the system RAM block */ | ||
105 | + int flags; | ||
106 | +} RAMInfo; | ||
107 | + | ||
108 | +/* | ||
109 | + * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit | ||
110 | + * emulation of that much guest RAM, so artificially make it smaller. | ||
111 | + */ | ||
112 | +#if HOST_LONG_BITS == 32 | ||
113 | +#define MPS3_DDR_SIZE (1 * GiB) | ||
114 | +#else | ||
115 | +#define MPS3_DDR_SIZE (3 * GiB) | ||
116 | +#endif | ||
117 | + | ||
118 | +/* | ||
119 | + * Flag values: | ||
120 | + * IS_MAIN: this is the main machine RAM | ||
121 | + * IS_ROM: this area is read-only | ||
122 | + */ | ||
123 | +#define IS_MAIN 1 | ||
124 | +#define IS_ROM 2 | ||
125 | + | ||
126 | +#define MPS3R_RAM_MAX 9 | ||
127 | + | ||
128 | +typedef enum MPS3RFPGAType { | ||
129 | + FPGA_AN536, | ||
130 | +} MPS3RFPGAType; | ||
131 | + | ||
132 | +struct MPS3RMachineClass { | ||
133 | + MachineClass parent; | ||
134 | + MPS3RFPGAType fpga_type; | ||
135 | + const RAMInfo *raminfo; | ||
136 | +}; | ||
137 | + | ||
138 | +struct MPS3RMachineState { | ||
139 | + MachineState parent; | ||
140 | + MemoryRegion ram[MPS3R_RAM_MAX]; | ||
141 | +}; | ||
142 | + | ||
143 | +#define TYPE_MPS3R_MACHINE "mps3r" | ||
144 | +#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536") | ||
145 | + | ||
146 | +OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) | ||
147 | + | ||
148 | +static const RAMInfo an536_raminfo[] = { | ||
149 | + { | ||
150 | + .name = "ATCM", | ||
151 | + .base = 0x00000000, | ||
152 | + .size = 0x00008000, | ||
153 | + .mrindex = 0, | ||
154 | + }, { | ||
155 | + /* We model the QSPI flash as simple ROM for now */ | ||
156 | + .name = "QSPI", | ||
157 | + .base = 0x08000000, | ||
158 | + .size = 0x00800000, | ||
159 | + .flags = IS_ROM, | ||
160 | + .mrindex = 1, | ||
161 | + }, { | ||
162 | + .name = "BRAM", | ||
163 | + .base = 0x10000000, | ||
164 | + .size = 0x00080000, | ||
165 | + .mrindex = 2, | ||
166 | + }, { | ||
167 | + .name = "DDR", | ||
168 | + .base = 0x20000000, | ||
169 | + .size = MPS3_DDR_SIZE, | ||
170 | + .mrindex = -1, | ||
171 | + }, { | ||
172 | + .name = "ATCM0", | ||
173 | + .base = 0xee000000, | ||
174 | + .size = 0x00008000, | ||
175 | + .mrindex = 3, | ||
176 | + }, { | ||
177 | + .name = "BTCM0", | ||
178 | + .base = 0xee100000, | ||
179 | + .size = 0x00008000, | ||
180 | + .mrindex = 4, | ||
181 | + }, { | ||
182 | + .name = "CTCM0", | ||
183 | + .base = 0xee200000, | ||
184 | + .size = 0x00008000, | ||
185 | + .mrindex = 5, | ||
186 | + }, { | ||
187 | + .name = "ATCM1", | ||
188 | + .base = 0xee400000, | ||
189 | + .size = 0x00008000, | ||
190 | + .mrindex = 6, | ||
191 | + }, { | ||
192 | + .name = "BTCM1", | ||
193 | + .base = 0xee500000, | ||
194 | + .size = 0x00008000, | ||
195 | + .mrindex = 7, | ||
196 | + }, { | ||
197 | + .name = "CTCM1", | ||
198 | + .base = 0xee600000, | ||
199 | + .size = 0x00008000, | ||
200 | + .mrindex = 8, | ||
201 | + }, { | ||
202 | + .name = NULL, | ||
203 | + } | ||
204 | +}; | ||
205 | + | ||
206 | +static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, | ||
207 | + const RAMInfo *raminfo) | ||
208 | +{ | ||
209 | + /* Return an initialized MemoryRegion for the RAMInfo. */ | ||
210 | + MemoryRegion *ram; | ||
211 | + | ||
212 | + if (raminfo->mrindex < 0) { | ||
213 | + /* Means this RAMInfo is for QEMU's "system memory" */ | ||
214 | + MachineState *machine = MACHINE(mms); | ||
215 | + assert(!(raminfo->flags & IS_ROM)); | ||
216 | + return machine->ram; | ||
217 | + } | ||
218 | + | ||
219 | + assert(raminfo->mrindex < MPS3R_RAM_MAX); | ||
220 | + ram = &mms->ram[raminfo->mrindex]; | ||
221 | + | ||
222 | + memory_region_init_ram(ram, NULL, raminfo->name, | ||
223 | + raminfo->size, &error_fatal); | ||
224 | + if (raminfo->flags & IS_ROM) { | ||
225 | + memory_region_set_readonly(ram, true); | ||
226 | + } | ||
227 | + return ram; | ||
228 | +} | ||
229 | + | ||
230 | +static void mps3r_common_init(MachineState *machine) | ||
231 | +{ | ||
232 | + MPS3RMachineState *mms = MPS3R_MACHINE(machine); | ||
233 | + MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); | ||
234 | + MemoryRegion *sysmem = get_system_memory(); | ||
235 | + | ||
236 | + for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { | ||
237 | + MemoryRegion *mr = mr_for_raminfo(mms, ri); | ||
238 | + memory_region_add_subregion(sysmem, ri->base, mr); | ||
239 | + } | ||
240 | +} | ||
241 | + | ||
242 | +static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) | ||
243 | +{ | ||
244 | + /* | ||
245 | + * Set mc->default_ram_size and default_ram_id from the | ||
246 | + * information in mmc->raminfo. | ||
247 | + */ | ||
248 | + MachineClass *mc = MACHINE_CLASS(mmc); | ||
249 | + const RAMInfo *p; | ||
250 | + | ||
251 | + for (p = mmc->raminfo; p->name; p++) { | ||
252 | + if (p->mrindex < 0) { | ||
253 | + /* Found the entry for "system memory" */ | ||
254 | + mc->default_ram_size = p->size; | ||
255 | + mc->default_ram_id = p->name; | ||
256 | + return; | ||
257 | + } | ||
258 | + } | ||
259 | + g_assert_not_reached(); | ||
260 | +} | ||
261 | + | ||
262 | +static void mps3r_class_init(ObjectClass *oc, void *data) | ||
263 | +{ | ||
264 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
265 | + | ||
266 | + mc->init = mps3r_common_init; | ||
267 | +} | ||
268 | + | ||
269 | +static void mps3r_an536_class_init(ObjectClass *oc, void *data) | ||
270 | +{ | ||
271 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
272 | + MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc); | ||
273 | + static const char * const valid_cpu_types[] = { | ||
274 | + ARM_CPU_TYPE_NAME("cortex-r52"), | ||
275 | + NULL | ||
276 | + }; | ||
277 | + | ||
278 | + mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52"; | ||
279 | + mc->default_cpus = 2; | ||
280 | + mc->min_cpus = mc->default_cpus; | ||
281 | + mc->max_cpus = mc->default_cpus; | ||
282 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52"); | ||
283 | + mc->valid_cpu_types = valid_cpu_types; | ||
284 | + mmc->raminfo = an536_raminfo; | ||
285 | + mps3r_set_default_ram_info(mmc); | ||
286 | +} | ||
287 | + | ||
288 | +static const TypeInfo mps3r_machine_types[] = { | ||
289 | + { | ||
290 | + .name = TYPE_MPS3R_MACHINE, | ||
291 | + .parent = TYPE_MACHINE, | ||
292 | + .abstract = true, | ||
293 | + .instance_size = sizeof(MPS3RMachineState), | ||
294 | + .class_size = sizeof(MPS3RMachineClass), | ||
295 | + .class_init = mps3r_class_init, | ||
296 | + }, { | ||
297 | + .name = TYPE_MPS3R_AN536_MACHINE, | ||
298 | + .parent = TYPE_MPS3R_MACHINE, | ||
299 | + .class_init = mps3r_an536_class_init, | ||
300 | + }, | ||
301 | +}; | ||
302 | + | ||
303 | +DEFINE_TYPES(mps3r_machine_types); | ||
304 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
305 | index XXXXXXX..XXXXXXX 100644 | ||
306 | --- a/hw/arm/Kconfig | ||
307 | +++ b/hw/arm/Kconfig | ||
308 | @@ -XXX,XX +XXX,XX @@ config MAINSTONE | ||
309 | select PFLASH_CFI01 | ||
310 | select SMC91C111 | ||
311 | |||
312 | +config MPS3R | ||
313 | + bool | ||
314 | + default y | ||
315 | + depends on TCG && ARM | ||
316 | + | ||
317 | config MUSCA | ||
318 | bool | ||
319 | default y | ||
320 | diff --git a/hw/arm/meson.build b/hw/arm/meson.build | ||
321 | index XXXXXXX..XXXXXXX 100644 | ||
322 | --- a/hw/arm/meson.build | ||
323 | +++ b/hw/arm/meson.build | ||
324 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) | ||
325 | arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) | ||
326 | arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) | ||
327 | arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) | ||
328 | +arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c')) | ||
329 | arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) | ||
330 | arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) | ||
331 | arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c')) | ||
332 | -- | ||
333 | 2.34.1 | ||
334 | |||
335 | diff view generated by jsdifflib |
1 | Instead of hardcoding the values of M profile ID registers in the | 1 | Create the CPUs, the GIC, and the per-CPU RAM block for |
---|---|---|---|
2 | NVIC, use the fields in the CPU struct. This will allow us to | 2 | the mps3-an536 board. |
3 | give different M profile CPU types different ID register values. | ||
4 | |||
5 | This commit includes the addition of the missing ID_ISAR5, | ||
6 | which exists as RES0 in both v7M and v8M. | ||
7 | |||
8 | (The values of the ID registers might be wrong for the M4 -- | ||
9 | this commit leaves the behaviour there unchanged.) | ||
10 | 3 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Message-id: 20240206132931.38376-10-peter.maydell@linaro.org |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20180209165810.6668-2-peter.maydell@linaro.org | ||
15 | --- | 6 | --- |
16 | hw/intc/armv7m_nvic.c | 30 ++++++++++++++++-------------- | 7 | hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++- |
17 | target/arm/cpu.c | 28 ++++++++++++++++++++++++++++ | 8 | 1 file changed, 177 insertions(+), 3 deletions(-) |
18 | 2 files changed, 44 insertions(+), 14 deletions(-) | ||
19 | 9 | ||
20 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 10 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
21 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/intc/armv7m_nvic.c | 12 | --- a/hw/arm/mps3r.c |
23 | +++ b/hw/intc/armv7m_nvic.c | 13 | +++ b/hw/arm/mps3r.c |
24 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 14 | @@ -XXX,XX +XXX,XX @@ |
25 | "Aux Fault status registers unimplemented\n"); | 15 | #include "qemu/osdep.h" |
26 | return 0; | 16 | #include "qemu/units.h" |
27 | case 0xd40: /* PFR0. */ | 17 | #include "qapi/error.h" |
28 | - return 0x00000030; | 18 | +#include "qapi/qmp/qlist.h" |
29 | - case 0xd44: /* PRF1. */ | 19 | #include "exec/address-spaces.h" |
30 | - return 0x00000200; | 20 | #include "cpu.h" |
31 | + return cpu->id_pfr0; | 21 | #include "hw/boards.h" |
32 | + case 0xd44: /* PFR1. */ | 22 | +#include "hw/qdev-properties.h" |
33 | + return cpu->id_pfr1; | 23 | #include "hw/arm/boot.h" |
34 | case 0xd48: /* DFR0. */ | 24 | +#include "hw/arm/bsa.h" |
35 | - return 0x00100000; | 25 | +#include "hw/intc/arm_gicv3.h" |
36 | + return cpu->id_dfr0; | 26 | |
37 | case 0xd4c: /* AFR0. */ | 27 | /* Define the layout of RAM and ROM in a board */ |
38 | - return 0x00000000; | 28 | typedef struct RAMInfo { |
39 | + return cpu->id_afr0; | 29 | @@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo { |
40 | case 0xd50: /* MMFR0. */ | 30 | #define IS_ROM 2 |
41 | - return 0x00000030; | 31 | |
42 | + return cpu->id_mmfr0; | 32 | #define MPS3R_RAM_MAX 9 |
43 | case 0xd54: /* MMFR1. */ | 33 | +#define MPS3R_CPU_MAX 2 |
44 | - return 0x00000000; | 34 | + |
45 | + return cpu->id_mmfr1; | 35 | +#define PERIPHBASE 0xf0000000 |
46 | case 0xd58: /* MMFR2. */ | 36 | +#define NUM_SPIS 96 |
47 | - return 0x00000000; | 37 | |
48 | + return cpu->id_mmfr2; | 38 | typedef enum MPS3RFPGAType { |
49 | case 0xd5c: /* MMFR3. */ | 39 | FPGA_AN536, |
50 | - return 0x00000000; | 40 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass { |
51 | + return cpu->id_mmfr3; | 41 | MachineClass parent; |
52 | case 0xd60: /* ISAR0. */ | 42 | MPS3RFPGAType fpga_type; |
53 | - return 0x01141110; | 43 | const RAMInfo *raminfo; |
54 | + return cpu->id_isar0; | 44 | + hwaddr loader_start; |
55 | case 0xd64: /* ISAR1. */ | 45 | }; |
56 | - return 0x02111000; | 46 | |
57 | + return cpu->id_isar1; | 47 | struct MPS3RMachineState { |
58 | case 0xd68: /* ISAR2. */ | 48 | MachineState parent; |
59 | - return 0x21112231; | 49 | + struct arm_boot_info bootinfo; |
60 | + return cpu->id_isar2; | 50 | MemoryRegion ram[MPS3R_RAM_MAX]; |
61 | case 0xd6c: /* ISAR3. */ | 51 | + Object *cpu[MPS3R_CPU_MAX]; |
62 | - return 0x01111110; | 52 | + MemoryRegion cpu_sysmem[MPS3R_CPU_MAX]; |
63 | + return cpu->id_isar3; | 53 | + MemoryRegion sysmem_alias[MPS3R_CPU_MAX]; |
64 | case 0xd70: /* ISAR4. */ | 54 | + MemoryRegion cpu_ram[MPS3R_CPU_MAX]; |
65 | - return 0x01310102; | 55 | + GICv3State gic; |
66 | + return cpu->id_isar4; | 56 | }; |
67 | + case 0xd74: /* ISAR5. */ | 57 | |
68 | + return cpu->id_isar5; | 58 | #define TYPE_MPS3R_MACHINE "mps3r" |
69 | /* TODO: Implement debug registers. */ | 59 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, |
70 | case 0xd90: /* MPU_TYPE */ | 60 | return ram; |
71 | /* Unified MPU; if the MPU is not present this value is zero */ | ||
72 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/target/arm/cpu.c | ||
75 | +++ b/target/arm/cpu.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj) | ||
77 | set_feature(&cpu->env, ARM_FEATURE_M); | ||
78 | cpu->midr = 0x410fc231; | ||
79 | cpu->pmsav7_dregion = 8; | ||
80 | + cpu->id_pfr0 = 0x00000030; | ||
81 | + cpu->id_pfr1 = 0x00000200; | ||
82 | + cpu->id_dfr0 = 0x00100000; | ||
83 | + cpu->id_afr0 = 0x00000000; | ||
84 | + cpu->id_mmfr0 = 0x00000030; | ||
85 | + cpu->id_mmfr1 = 0x00000000; | ||
86 | + cpu->id_mmfr2 = 0x00000000; | ||
87 | + cpu->id_mmfr3 = 0x00000000; | ||
88 | + cpu->id_isar0 = 0x01141110; | ||
89 | + cpu->id_isar1 = 0x02111000; | ||
90 | + cpu->id_isar2 = 0x21112231; | ||
91 | + cpu->id_isar3 = 0x01111110; | ||
92 | + cpu->id_isar4 = 0x01310102; | ||
93 | + cpu->id_isar5 = 0x00000000; | ||
94 | } | 61 | } |
95 | 62 | ||
96 | static void cortex_m4_initfn(Object *obj) | 63 | +/* |
97 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | 64 | + * There is no defined secondary boot protocol for Linux for the AN536, |
98 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 65 | + * because real hardware has a restriction that atomic operations between |
99 | cpu->midr = 0x410fc240; /* r0p0 */ | 66 | + * the two CPUs do not function correctly, and so true SMP is not |
100 | cpu->pmsav7_dregion = 8; | 67 | + * possible. Therefore for cases where the user is directly booting |
101 | + cpu->id_pfr0 = 0x00000030; | 68 | + * a kernel, we treat the system as essentially uniprocessor, and |
102 | + cpu->id_pfr1 = 0x00000200; | 69 | + * put the secondary CPU into power-off state (as if the user on the |
103 | + cpu->id_dfr0 = 0x00100000; | 70 | + * real hardware had configured the secondary to be halted via the |
104 | + cpu->id_afr0 = 0x00000000; | 71 | + * SCC config registers). |
105 | + cpu->id_mmfr0 = 0x00000030; | 72 | + * |
106 | + cpu->id_mmfr1 = 0x00000000; | 73 | + * Note that the default secondary boot code would not work here anyway |
107 | + cpu->id_mmfr2 = 0x00000000; | 74 | + * as it assumes a GICv2, and we have a GICv3. |
108 | + cpu->id_mmfr3 = 0x00000000; | 75 | + */ |
109 | + cpu->id_isar0 = 0x01141110; | 76 | +static void mps3r_write_secondary_boot(ARMCPU *cpu, |
110 | + cpu->id_isar1 = 0x02111000; | 77 | + const struct arm_boot_info *info) |
111 | + cpu->id_isar2 = 0x21112231; | 78 | +{ |
112 | + cpu->id_isar3 = 0x01111110; | 79 | + /* |
113 | + cpu->id_isar4 = 0x01310102; | 80 | + * Power the secondary CPU off. This means we don't need to write any |
114 | + cpu->id_isar5 = 0x00000000; | 81 | + * boot code into guest memory. Note that the 'cpu' argument to this |
82 | + * function is the primary CPU we passed to arm_load_kernel(), not | ||
83 | + * the secondary. Loop around all the other CPUs, as the boot.c | ||
84 | + * code does for the "disable secondaries if PSCI is enabled" case. | ||
85 | + */ | ||
86 | + for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | ||
87 | + if (cs != first_cpu) { | ||
88 | + object_property_set_bool(OBJECT(cs), "start-powered-off", true, | ||
89 | + &error_abort); | ||
90 | + } | ||
91 | + } | ||
92 | +} | ||
93 | + | ||
94 | +static void mps3r_secondary_cpu_reset(ARMCPU *cpu, | ||
95 | + const struct arm_boot_info *info) | ||
96 | +{ | ||
97 | + /* We don't need to do anything here because the CPU will be off */ | ||
98 | +} | ||
99 | + | ||
100 | +static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem) | ||
101 | +{ | ||
102 | + MachineState *machine = MACHINE(mms); | ||
103 | + DeviceState *gicdev; | ||
104 | + QList *redist_region_count; | ||
105 | + | ||
106 | + object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3); | ||
107 | + gicdev = DEVICE(&mms->gic); | ||
108 | + qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus); | ||
109 | + qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL); | ||
110 | + redist_region_count = qlist_new(); | ||
111 | + qlist_append_int(redist_region_count, machine->smp.cpus); | ||
112 | + qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); | ||
113 | + object_property_set_link(OBJECT(&mms->gic), "sysmem", | ||
114 | + OBJECT(sysmem), &error_fatal); | ||
115 | + sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal); | ||
116 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE); | ||
117 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000); | ||
118 | + /* | ||
119 | + * Wire the outputs from each CPU's generic timer and the GICv3 | ||
120 | + * maintenance interrupt signal to the appropriate GIC PPI inputs, | ||
121 | + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | ||
122 | + */ | ||
123 | + for (int i = 0; i < machine->smp.cpus; i++) { | ||
124 | + DeviceState *cpudev = DEVICE(mms->cpu[i]); | ||
125 | + SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic); | ||
126 | + int intidbase = NUM_SPIS + i * GIC_INTERNAL; | ||
127 | + int irq; | ||
128 | + /* | ||
129 | + * Mapping from the output timer irq lines from the CPU to the | ||
130 | + * GIC PPI inputs used for this board. This isn't a BSA board, | ||
131 | + * but it uses the standard convention for the PPI numbers. | ||
132 | + */ | ||
133 | + const int timer_irq[] = { | ||
134 | + [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | ||
135 | + [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | ||
136 | + [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | ||
137 | + }; | ||
138 | + | ||
139 | + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | ||
140 | + qdev_connect_gpio_out(cpudev, irq, | ||
141 | + qdev_get_gpio_in(gicdev, | ||
142 | + intidbase + timer_irq[irq])); | ||
143 | + } | ||
144 | + | ||
145 | + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, | ||
146 | + qdev_get_gpio_in(gicdev, | ||
147 | + intidbase + ARCH_GIC_MAINT_IRQ)); | ||
148 | + | ||
149 | + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, | ||
150 | + qdev_get_gpio_in(gicdev, | ||
151 | + intidbase + VIRTUAL_PMU_IRQ)); | ||
152 | + | ||
153 | + sysbus_connect_irq(gicsbd, i, | ||
154 | + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | ||
155 | + sysbus_connect_irq(gicsbd, i + machine->smp.cpus, | ||
156 | + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | ||
157 | + sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus, | ||
158 | + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | ||
159 | + sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus, | ||
160 | + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | ||
161 | + } | ||
162 | +} | ||
163 | + | ||
164 | static void mps3r_common_init(MachineState *machine) | ||
165 | { | ||
166 | MPS3RMachineState *mms = MPS3R_MACHINE(machine); | ||
167 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
168 | MemoryRegion *mr = mr_for_raminfo(mms, ri); | ||
169 | memory_region_add_subregion(sysmem, ri->base, mr); | ||
170 | } | ||
171 | + | ||
172 | + assert(machine->smp.cpus <= MPS3R_CPU_MAX); | ||
173 | + for (int i = 0; i < machine->smp.cpus; i++) { | ||
174 | + g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i); | ||
175 | + g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i); | ||
176 | + g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i); | ||
177 | + | ||
178 | + /* | ||
179 | + * Each CPU has some private RAM/peripherals, so create the container | ||
180 | + * which will house those, with the whole-machine system memory being | ||
181 | + * used where there's no CPU-specific device. Note that we need the | ||
182 | + * sysmem_alias aliases because we can't put one MR (the original | ||
183 | + * 'sysmem') into more than one other MR. | ||
184 | + */ | ||
185 | + memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine), | ||
186 | + sysmem_name, UINT64_MAX); | ||
187 | + memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine), | ||
188 | + alias_name, sysmem, 0, UINT64_MAX); | ||
189 | + memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0, | ||
190 | + &mms->sysmem_alias[i], -1); | ||
191 | + | ||
192 | + mms->cpu[i] = object_new(machine->cpu_type); | ||
193 | + object_property_set_link(mms->cpu[i], "memory", | ||
194 | + OBJECT(&mms->cpu_sysmem[i]), &error_abort); | ||
195 | + object_property_set_int(mms->cpu[i], "reset-cbar", | ||
196 | + PERIPHBASE, &error_abort); | ||
197 | + qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal); | ||
198 | + object_unref(mms->cpu[i]); | ||
199 | + | ||
200 | + /* Per-CPU RAM */ | ||
201 | + memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname, | ||
202 | + 0x1000, &error_fatal); | ||
203 | + memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000, | ||
204 | + &mms->cpu_ram[i]); | ||
205 | + } | ||
206 | + | ||
207 | + create_gic(mms, sysmem); | ||
208 | + | ||
209 | + mms->bootinfo.ram_size = machine->ram_size; | ||
210 | + mms->bootinfo.board_id = -1; | ||
211 | + mms->bootinfo.loader_start = mmc->loader_start; | ||
212 | + mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot; | ||
213 | + mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset; | ||
214 | + arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo); | ||
115 | } | 215 | } |
116 | 216 | ||
117 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | 217 | static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) |
218 | @@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) | ||
219 | /* Found the entry for "system memory" */ | ||
220 | mc->default_ram_size = p->size; | ||
221 | mc->default_ram_id = p->name; | ||
222 | + mmc->loader_start = p->base; | ||
223 | return; | ||
224 | } | ||
225 | } | ||
226 | @@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data) | ||
227 | }; | ||
228 | |||
229 | mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52"; | ||
230 | - mc->default_cpus = 2; | ||
231 | - mc->min_cpus = mc->default_cpus; | ||
232 | - mc->max_cpus = mc->default_cpus; | ||
233 | + /* | ||
234 | + * In the real FPGA image there are always two cores, but the standard | ||
235 | + * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning | ||
236 | + * that the second core is held in reset and halted. Many images built for | ||
237 | + * the board do not expect the second core to run at startup (especially | ||
238 | + * since on the real FPGA image it is not possible to use LDREX/STREX | ||
239 | + * in RAM between the two cores, so a true SMP setup isn't supported). | ||
240 | + * | ||
241 | + * As QEMU's equivalent of this, we support both -smp 1 and -smp 2, | ||
242 | + * with the default being -smp 1. This seems a more intuitive UI for | ||
243 | + * QEMU users than, for instance, having a machine property to allow | ||
244 | + * the user to set the initial value of the SYSCON 0x000 register. | ||
245 | + */ | ||
246 | + mc->default_cpus = 1; | ||
247 | + mc->min_cpus = 1; | ||
248 | + mc->max_cpus = 2; | ||
249 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52"); | ||
250 | mc->valid_cpu_types = valid_cpu_types; | ||
251 | mmc->raminfo = an536_raminfo; | ||
118 | -- | 252 | -- |
119 | 2.16.1 | 253 | 2.34.1 |
120 | |||
121 | diff view generated by jsdifflib |
1 | The v8M architecture includes hardware support for enforcing | 1 | This board has a lot of UARTs: there is one UART per CPU in the |
---|---|---|---|
2 | stack pointer limits. We don't implement this behaviour yet, | 2 | per-CPU peripheral part of the address map, whose interrupts are |
3 | but provide the MSPLIM and PSPLIM stack pointer limit registers | 3 | connected as per-CPU interrupt lines. Then there are 4 UARTs in the |
4 | as reads-as-written, so that when we do implement the checks | 4 | normal part of the peripheral space, whose interrupts are shared |
5 | in future this won't break guest migration. | 5 | peripheral interrupts. |
6 | |||
7 | Connect and wire them all up; this involves some OR gates where | ||
8 | multiple overflow interrupts are wired into one GIC input. | ||
6 | 9 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20180209165810.6668-12-peter.maydell@linaro.org | 12 | Message-id: 20240206132931.38376-11-peter.maydell@linaro.org |
10 | --- | 13 | --- |
11 | target/arm/cpu.h | 2 ++ | 14 | hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++ |
12 | target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ | 15 | 1 file changed, 94 insertions(+) |
13 | target/arm/machine.c | 21 +++++++++++++++++++++ | ||
14 | 3 files changed, 69 insertions(+) | ||
15 | 16 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 19 | --- a/hw/arm/mps3r.c |
19 | +++ b/target/arm/cpu.h | 20 | +++ b/hw/arm/mps3r.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 21 | @@ -XXX,XX +XXX,XX @@ |
21 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | 22 | #include "qapi/qmp/qlist.h" |
22 | uint32_t csselr[M_REG_NUM_BANKS]; | 23 | #include "exec/address-spaces.h" |
23 | uint32_t scr[M_REG_NUM_BANKS]; | 24 | #include "cpu.h" |
24 | + uint32_t msplim[M_REG_NUM_BANKS]; | 25 | +#include "sysemu/sysemu.h" |
25 | + uint32_t psplim[M_REG_NUM_BANKS]; | 26 | #include "hw/boards.h" |
26 | } v7m; | 27 | +#include "hw/or-irq.h" |
27 | 28 | #include "hw/qdev-properties.h" | |
28 | /* Information associated with an exception about to be taken: | 29 | #include "hw/arm/boot.h" |
29 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 30 | #include "hw/arm/bsa.h" |
30 | index XXXXXXX..XXXXXXX 100644 | 31 | +#include "hw/char/cmsdk-apb-uart.h" |
31 | --- a/target/arm/helper.c | 32 | #include "hw/intc/arm_gicv3.h" |
32 | +++ b/target/arm/helper.c | 33 | |
33 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 34 | /* Define the layout of RAM and ROM in a board */ |
34 | return 0; | 35 | @@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo { |
35 | } | 36 | |
36 | return env->v7m.other_ss_psp; | 37 | #define MPS3R_RAM_MAX 9 |
37 | + case 0x8a: /* MSPLIM_NS */ | 38 | #define MPS3R_CPU_MAX 2 |
38 | + if (!env->v7m.secure) { | 39 | +#define MPS3R_UART_MAX 4 /* shared UART count */ |
39 | + return 0; | 40 | |
40 | + } | 41 | #define PERIPHBASE 0xf0000000 |
41 | + return env->v7m.msplim[M_REG_NS]; | 42 | #define NUM_SPIS 96 |
42 | + case 0x8b: /* PSPLIM_NS */ | 43 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { |
43 | + if (!env->v7m.secure) { | 44 | MemoryRegion sysmem_alias[MPS3R_CPU_MAX]; |
44 | + return 0; | 45 | MemoryRegion cpu_ram[MPS3R_CPU_MAX]; |
45 | + } | 46 | GICv3State gic; |
46 | + return env->v7m.psplim[M_REG_NS]; | 47 | + /* per-CPU UARTs followed by the shared UARTs */ |
47 | case 0x90: /* PRIMASK_NS */ | 48 | + CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; |
48 | if (!env->v7m.secure) { | 49 | + OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; |
49 | return 0; | 50 | + OrIRQState uart_oflow; |
50 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 51 | }; |
51 | return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; | 52 | |
52 | case 9: /* PSP */ | 53 | #define TYPE_MPS3R_MACHINE "mps3r" |
53 | return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; | 54 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { |
54 | + case 10: /* MSPLIM */ | 55 | |
55 | + if (!arm_feature(env, ARM_FEATURE_V8)) { | 56 | OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) |
56 | + goto bad_reg; | 57 | |
57 | + } | 58 | +/* |
58 | + return env->v7m.msplim[env->v7m.secure]; | 59 | + * Main clock frequency CLK in Hz (50MHz). In the image there are also |
59 | + case 11: /* PSPLIM */ | 60 | + * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our |
60 | + if (!arm_feature(env, ARM_FEATURE_V8)) { | 61 | + * model we just roll them all into one. |
61 | + goto bad_reg; | 62 | + */ |
62 | + } | 63 | +#define CLK_FRQ 50000000 |
63 | + return env->v7m.psplim[env->v7m.secure]; | 64 | + |
64 | case 16: /* PRIMASK */ | 65 | static const RAMInfo an536_raminfo[] = { |
65 | return env->v7m.primask[env->v7m.secure]; | 66 | { |
66 | case 17: /* BASEPRI */ | 67 | .name = "ATCM", |
67 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 68 | @@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem) |
68 | case 19: /* FAULTMASK */ | ||
69 | return env->v7m.faultmask[env->v7m.secure]; | ||
70 | default: | ||
71 | + bad_reg: | ||
72 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" | ||
73 | " register %d\n", reg); | ||
74 | return 0; | ||
75 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
76 | } | ||
77 | env->v7m.other_ss_psp = val; | ||
78 | return; | ||
79 | + case 0x8a: /* MSPLIM_NS */ | ||
80 | + if (!env->v7m.secure) { | ||
81 | + return; | ||
82 | + } | ||
83 | + env->v7m.msplim[M_REG_NS] = val & ~7; | ||
84 | + return; | ||
85 | + case 0x8b: /* PSPLIM_NS */ | ||
86 | + if (!env->v7m.secure) { | ||
87 | + return; | ||
88 | + } | ||
89 | + env->v7m.psplim[M_REG_NS] = val & ~7; | ||
90 | + return; | ||
91 | case 0x90: /* PRIMASK_NS */ | ||
92 | if (!env->v7m.secure) { | ||
93 | return; | ||
94 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
95 | env->v7m.other_sp = val; | ||
96 | } | ||
97 | break; | ||
98 | + case 10: /* MSPLIM */ | ||
99 | + if (!arm_feature(env, ARM_FEATURE_V8)) { | ||
100 | + goto bad_reg; | ||
101 | + } | ||
102 | + env->v7m.msplim[env->v7m.secure] = val & ~7; | ||
103 | + break; | ||
104 | + case 11: /* PSPLIM */ | ||
105 | + if (!arm_feature(env, ARM_FEATURE_V8)) { | ||
106 | + goto bad_reg; | ||
107 | + } | ||
108 | + env->v7m.psplim[env->v7m.secure] = val & ~7; | ||
109 | + break; | ||
110 | case 16: /* PRIMASK */ | ||
111 | env->v7m.primask[env->v7m.secure] = val & 1; | ||
112 | break; | ||
113 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
114 | env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | ||
115 | break; | ||
116 | default: | ||
117 | + bad_reg: | ||
118 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" | ||
119 | " register %d\n", reg); | ||
120 | return; | ||
121 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/target/arm/machine.c | ||
124 | +++ b/target/arm/machine.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_other_sp = { | ||
126 | } | 69 | } |
127 | }; | 70 | } |
128 | 71 | ||
129 | +static bool m_v8m_needed(void *opaque) | 72 | +/* |
73 | + * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr. | ||
74 | + * The qemu_irq arguments are where we connect the various IRQs from the UART. | ||
75 | + */ | ||
76 | +static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem, | ||
77 | + hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq, | ||
78 | + qemu_irq txoverirq, qemu_irq rxoverirq, | ||
79 | + qemu_irq combirq) | ||
130 | +{ | 80 | +{ |
131 | + ARMCPU *cpu = opaque; | 81 | + g_autofree char *s = g_strdup_printf("uart%d", uartno); |
132 | + CPUARMState *env = &cpu->env; | 82 | + SysBusDevice *sbd; |
133 | + | 83 | + |
134 | + return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); | 84 | + assert(uartno < ARRAY_SIZE(mms->uart)); |
85 | + object_initialize_child(OBJECT(mms), s, &mms->uart[uartno], | ||
86 | + TYPE_CMSDK_APB_UART); | ||
87 | + qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); | ||
88 | + qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno)); | ||
89 | + sbd = SYS_BUS_DEVICE(&mms->uart[uartno]); | ||
90 | + sysbus_realize(sbd, &error_fatal); | ||
91 | + memory_region_add_subregion(mem, baseaddr, | ||
92 | + sysbus_mmio_get_region(sbd, 0)); | ||
93 | + sysbus_connect_irq(sbd, 0, txirq); | ||
94 | + sysbus_connect_irq(sbd, 1, rxirq); | ||
95 | + sysbus_connect_irq(sbd, 2, txoverirq); | ||
96 | + sysbus_connect_irq(sbd, 3, rxoverirq); | ||
97 | + sysbus_connect_irq(sbd, 4, combirq); | ||
135 | +} | 98 | +} |
136 | + | 99 | + |
137 | +static const VMStateDescription vmstate_m_v8m = { | 100 | static void mps3r_common_init(MachineState *machine) |
138 | + .name = "cpu/m/v8m", | 101 | { |
139 | + .version_id = 1, | 102 | MPS3RMachineState *mms = MPS3R_MACHINE(machine); |
140 | + .minimum_version_id = 1, | 103 | MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); |
141 | + .needed = m_v8m_needed, | 104 | MemoryRegion *sysmem = get_system_memory(); |
142 | + .fields = (VMStateField[]) { | 105 | + DeviceState *gicdev; |
143 | + VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), | 106 | |
144 | + VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), | 107 | for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { |
145 | + VMSTATE_END_OF_LIST() | 108 | MemoryRegion *mr = mr_for_raminfo(mms, ri); |
109 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
110 | } | ||
111 | |||
112 | create_gic(mms, sysmem); | ||
113 | + gicdev = DEVICE(&mms->gic); | ||
114 | + | ||
115 | + /* | ||
116 | + * UARTs 0 and 1 are per-CPU; their interrupts are wired to | ||
117 | + * the relevant CPU's PPI 0..3, aka INTID 16..19 | ||
118 | + */ | ||
119 | + for (int i = 0; i < machine->smp.cpus; i++) { | ||
120 | + int intidbase = NUM_SPIS + i * GIC_INTERNAL; | ||
121 | + g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i); | ||
122 | + DeviceState *orgate; | ||
123 | + | ||
124 | + /* The two overflow IRQs from the UART are ORed together into PPI 3 */ | ||
125 | + object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i], | ||
126 | + TYPE_OR_IRQ); | ||
127 | + orgate = DEVICE(&mms->cpu_uart_oflow[i]); | ||
128 | + qdev_prop_set_uint32(orgate, "num-lines", 2); | ||
129 | + qdev_realize(orgate, NULL, &error_fatal); | ||
130 | + qdev_connect_gpio_out(orgate, 0, | ||
131 | + qdev_get_gpio_in(gicdev, intidbase + 19)); | ||
132 | + | ||
133 | + create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000, | ||
134 | + qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */ | ||
135 | + qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */ | ||
136 | + qdev_get_gpio_in(orgate, 0), /* txover */ | ||
137 | + qdev_get_gpio_in(orgate, 1), /* rxover */ | ||
138 | + qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */); | ||
146 | + } | 139 | + } |
147 | +}; | 140 | + /* |
141 | + * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed | ||
142 | + * together into IRQ 17 | ||
143 | + */ | ||
144 | + object_initialize_child(OBJECT(mms), "uart-oflow-orgate", | ||
145 | + &mms->uart_oflow, TYPE_OR_IRQ); | ||
146 | + qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines", | ||
147 | + MPS3R_UART_MAX * 2); | ||
148 | + qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal); | ||
149 | + qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0, | ||
150 | + qdev_get_gpio_in(gicdev, 17)); | ||
148 | + | 151 | + |
149 | static const VMStateDescription vmstate_m = { | 152 | + for (int i = 0; i < MPS3R_UART_MAX; i++) { |
150 | .name = "cpu/m", | 153 | + hwaddr baseaddr = 0xe0205000 + i * 0x1000; |
151 | .version_id = 4, | 154 | + int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i; |
152 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 155 | + |
153 | &vmstate_m_csselr, | 156 | + create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr, |
154 | &vmstate_m_scr, | 157 | + qdev_get_gpio_in(gicdev, txirq), |
155 | &vmstate_m_other_sp, | 158 | + qdev_get_gpio_in(gicdev, rxirq), |
156 | + &vmstate_m_v8m, | 159 | + qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2), |
157 | NULL | 160 | + qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1), |
158 | } | 161 | + qdev_get_gpio_in(gicdev, combirq)); |
159 | }; | 162 | + } |
163 | |||
164 | mms->bootinfo.ram_size = machine->ram_size; | ||
165 | mms->bootinfo.board_id = -1; | ||
160 | -- | 166 | -- |
161 | 2.16.1 | 167 | 2.34.1 |
162 | 168 | ||
163 | 169 | diff view generated by jsdifflib |
1 | The Coprocessor Power Control Register (CPPWR) is new in v8M. | 1 | Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536 |
---|---|---|---|
2 | It allows software to control whether coprocessors are allowed | 2 | board. These are all simple devices that just need to be created and |
3 | to power down and lose their state. QEMU doesn't have any | 3 | wired up. |
4 | notion of power control, so we choose the IMPDEF option of | ||
5 | making the whole register RAZ/WI (indicating that no coprocessors | ||
6 | can ever power down and lose state). | ||
7 | 4 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Message-id: 20180209165810.6668-5-peter.maydell@linaro.org | 7 | Message-id: 20240206132931.38376-12-peter.maydell@linaro.org |
11 | --- | 8 | --- |
12 | hw/intc/armv7m_nvic.c | 14 ++++++++++++++ | 9 | hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ |
13 | 1 file changed, 14 insertions(+) | 10 | 1 file changed, 59 insertions(+) |
14 | 11 | ||
15 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 12 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/intc/armv7m_nvic.c | 14 | --- a/hw/arm/mps3r.c |
18 | +++ b/hw/intc/armv7m_nvic.c | 15 | +++ b/hw/arm/mps3r.c |
19 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 16 | @@ -XXX,XX +XXX,XX @@ |
20 | switch (offset) { | 17 | #include "sysemu/sysemu.h" |
21 | case 4: /* Interrupt Control Type. */ | 18 | #include "hw/boards.h" |
22 | return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; | 19 | #include "hw/or-irq.h" |
23 | + case 0xc: /* CPPWR */ | 20 | +#include "hw/qdev-clock.h" |
24 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 21 | #include "hw/qdev-properties.h" |
25 | + goto bad_offset; | 22 | #include "hw/arm/boot.h" |
23 | #include "hw/arm/bsa.h" | ||
24 | #include "hw/char/cmsdk-apb-uart.h" | ||
25 | +#include "hw/i2c/arm_sbcon_i2c.h" | ||
26 | #include "hw/intc/arm_gicv3.h" | ||
27 | +#include "hw/misc/unimp.h" | ||
28 | +#include "hw/timer/cmsdk-apb-dualtimer.h" | ||
29 | +#include "hw/watchdog/cmsdk-apb-watchdog.h" | ||
30 | |||
31 | /* Define the layout of RAM and ROM in a board */ | ||
32 | typedef struct RAMInfo { | ||
33 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { | ||
34 | CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; | ||
35 | OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; | ||
36 | OrIRQState uart_oflow; | ||
37 | + CMSDKAPBWatchdog watchdog; | ||
38 | + CMSDKAPBDualTimer dualtimer; | ||
39 | + ArmSbconI2CState i2c[5]; | ||
40 | + Clock *clk; | ||
41 | }; | ||
42 | |||
43 | #define TYPE_MPS3R_MACHINE "mps3r" | ||
44 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
45 | MemoryRegion *sysmem = get_system_memory(); | ||
46 | DeviceState *gicdev; | ||
47 | |||
48 | + mms->clk = clock_new(OBJECT(machine), "CLK"); | ||
49 | + clock_set_hz(mms->clk, CLK_FRQ); | ||
50 | + | ||
51 | for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { | ||
52 | MemoryRegion *mr = mr_for_raminfo(mms, ri); | ||
53 | memory_region_add_subregion(sysmem, ri->base, mr); | ||
54 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
55 | qdev_get_gpio_in(gicdev, combirq)); | ||
56 | } | ||
57 | |||
58 | + for (int i = 0; i < 4; i++) { | ||
59 | + /* CMSDK GPIO controllers */ | ||
60 | + g_autofree char *s = g_strdup_printf("gpio%d", i); | ||
61 | + create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000); | ||
62 | + } | ||
63 | + | ||
64 | + object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, | ||
65 | + TYPE_CMSDK_APB_WATCHDOG); | ||
66 | + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk); | ||
67 | + sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); | ||
68 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, | ||
69 | + qdev_get_gpio_in(gicdev, 0)); | ||
70 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000); | ||
71 | + | ||
72 | + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, | ||
73 | + TYPE_CMSDK_APB_DUALTIMER); | ||
74 | + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk); | ||
75 | + sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); | ||
76 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, | ||
77 | + qdev_get_gpio_in(gicdev, 3)); | ||
78 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1, | ||
79 | + qdev_get_gpio_in(gicdev, 1)); | ||
80 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2, | ||
81 | + qdev_get_gpio_in(gicdev, 2)); | ||
82 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000); | ||
83 | + | ||
84 | + for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) { | ||
85 | + static const hwaddr i2cbase[] = {0xe0102000, /* Touch */ | ||
86 | + 0xe0103000, /* Audio */ | ||
87 | + 0xe0107000, /* Shield0 */ | ||
88 | + 0xe0108000, /* Shield1 */ | ||
89 | + 0xe0109000}; /* DDR4 EEPROM */ | ||
90 | + g_autofree char *s = g_strdup_printf("i2c%d", i); | ||
91 | + | ||
92 | + object_initialize_child(OBJECT(mms), s, &mms->i2c[i], | ||
93 | + TYPE_ARM_SBCON_I2C); | ||
94 | + sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal); | ||
95 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]); | ||
96 | + if (i != 2 && i != 3) { | ||
97 | + /* | ||
98 | + * internal-only bus: mark it full to avoid user-created | ||
99 | + * i2c devices being plugged into it. | ||
100 | + */ | ||
101 | + qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c")); | ||
26 | + } | 102 | + } |
27 | + /* We make the IMPDEF choice that nothing can ever go into a | 103 | + } |
28 | + * non-retentive power state, which allows us to RAZ/WI this. | 104 | + |
29 | + */ | 105 | mms->bootinfo.ram_size = machine->ram_size; |
30 | + return 0; | 106 | mms->bootinfo.board_id = -1; |
31 | case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ | 107 | mms->bootinfo.loader_start = mmc->loader_start; |
32 | { | ||
33 | int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; | ||
34 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
35 | ARMCPU *cpu = s->cpu; | ||
36 | |||
37 | switch (offset) { | ||
38 | + case 0xc: /* CPPWR */ | ||
39 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
40 | + goto bad_offset; | ||
41 | + } | ||
42 | + /* Make the IMPDEF choice to RAZ/WI this. */ | ||
43 | + break; | ||
44 | case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ | ||
45 | { | ||
46 | int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; | ||
47 | -- | 108 | -- |
48 | 2.16.1 | 109 | 2.34.1 |
49 | 110 | ||
50 | 111 | diff view generated by jsdifflib |
1 | We were previously making the system control register (SCR) | 1 | Add the remaining devices (or unimplemented-device stubs) for |
---|---|---|---|
2 | just RAZ/WI. Although we don't implement the functionality | 2 | this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the |
3 | this register controls, we should at least provide the state, | 3 | QSPI write-config block, and ethernet. |
4 | including the banked state for v8M. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20180209165810.6668-7-peter.maydell@linaro.org | 7 | Message-id: 20240206132931.38376-13-peter.maydell@linaro.org |
9 | --- | 8 | --- |
10 | target/arm/cpu.h | 7 +++++++ | 9 | hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ |
11 | hw/intc/armv7m_nvic.c | 12 ++++++++---- | 10 | 1 file changed, 74 insertions(+) |
12 | target/arm/machine.c | 12 ++++++++++++ | ||
13 | 3 files changed, 27 insertions(+), 4 deletions(-) | ||
14 | 11 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 12 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 14 | --- a/hw/arm/mps3r.c |
18 | +++ b/target/arm/cpu.h | 15 | +++ b/hw/arm/mps3r.c |
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 16 | @@ -XXX,XX +XXX,XX @@ |
20 | uint32_t aircr; /* only holds r/w state if security extn implemented */ | 17 | #include "hw/char/cmsdk-apb-uart.h" |
21 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | 18 | #include "hw/i2c/arm_sbcon_i2c.h" |
22 | uint32_t csselr[M_REG_NUM_BANKS]; | 19 | #include "hw/intc/arm_gicv3.h" |
23 | + uint32_t scr[M_REG_NUM_BANKS]; | 20 | +#include "hw/misc/mps2-scc.h" |
24 | } v7m; | 21 | +#include "hw/misc/mps2-fpgaio.h" |
25 | 22 | #include "hw/misc/unimp.h" | |
26 | /* Information associated with an exception about to be taken: | 23 | +#include "hw/net/lan9118.h" |
27 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1) | 24 | +#include "hw/rtc/pl031.h" |
28 | FIELD(V7M_CCR, DC, 16, 1) | 25 | +#include "hw/ssi/pl022.h" |
29 | FIELD(V7M_CCR, IC, 17, 1) | 26 | #include "hw/timer/cmsdk-apb-dualtimer.h" |
30 | 27 | #include "hw/watchdog/cmsdk-apb-watchdog.h" | |
31 | +/* V7M SCR bits */ | 28 | |
32 | +FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) | 29 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { |
33 | +FIELD(V7M_SCR, SLEEPDEEP, 2, 1) | 30 | CMSDKAPBWatchdog watchdog; |
34 | +FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) | 31 | CMSDKAPBDualTimer dualtimer; |
35 | +FIELD(V7M_SCR, SEVONPEND, 4, 1) | 32 | ArmSbconI2CState i2c[5]; |
36 | + | 33 | + PL022State spi[3]; |
37 | /* V7M AIRCR bits */ | 34 | + MPS2SCC scc; |
38 | FIELD(V7M_AIRCR, VECTRESET, 0, 1) | 35 | + MPS2FPGAIO fpgaio; |
39 | FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) | 36 | + UnimplementedDeviceState i2s_audio; |
40 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 37 | + PL031State rtc; |
41 | index XXXXXXX..XXXXXXX 100644 | 38 | Clock *clk; |
42 | --- a/hw/intc/armv7m_nvic.c | 39 | }; |
43 | +++ b/hw/intc/armv7m_nvic.c | 40 | |
44 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 41 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = { |
45 | } | ||
46 | return val; | ||
47 | case 0xd10: /* System Control. */ | ||
48 | - /* TODO: Implement SLEEPONEXIT. */ | ||
49 | - return 0; | ||
50 | + return cpu->env.v7m.scr[attrs.secure]; | ||
51 | case 0xd14: /* Configuration Control. */ | ||
52 | /* The BFHFNMIGN bit is the only non-banked bit; we | ||
53 | * keep it in the non-secure copy of the register. | ||
54 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
55 | } | ||
56 | break; | ||
57 | case 0xd10: /* System Control. */ | ||
58 | - /* TODO: Implement control registers. */ | ||
59 | - qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); | ||
60 | + /* We don't implement deep-sleep so these bits are RAZ/WI. | ||
61 | + * The other bits in the register are banked. | ||
62 | + * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which | ||
63 | + * is architecturally permitted. | ||
64 | + */ | ||
65 | + value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); | ||
66 | + cpu->env.v7m.scr[attrs.secure] = value; | ||
67 | break; | ||
68 | case 0xd14: /* Configuration Control. */ | ||
69 | /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ | ||
70 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/machine.c | ||
73 | +++ b/target/arm/machine.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_csselr = { | ||
75 | } | 42 | } |
76 | }; | 43 | }; |
77 | 44 | ||
78 | +static const VMStateDescription vmstate_m_scr = { | 45 | +static const int an536_oscclk[] = { |
79 | + .name = "cpu/m/scr", | 46 | + 24000000, /* 24MHz reference for RTC and timers */ |
80 | + .version_id = 1, | 47 | + 50000000, /* 50MHz ACLK */ |
81 | + .minimum_version_id = 1, | 48 | + 50000000, /* 50MHz MCLK */ |
82 | + .fields = (VMStateField[]) { | 49 | + 50000000, /* 50MHz GPUCLK */ |
83 | + VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), | 50 | + 24576000, /* 24.576MHz AUDCLK */ |
84 | + VMSTATE_END_OF_LIST() | 51 | + 23750000, /* 23.75MHz HDLCDCLK */ |
85 | + } | 52 | + 100000000, /* 100MHz DDR4_REF_CLK */ |
86 | +}; | 53 | +}; |
87 | + | 54 | + |
88 | static const VMStateDescription vmstate_m = { | 55 | static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, |
89 | .name = "cpu/m", | 56 | const RAMInfo *raminfo) |
90 | .version_id = 4, | 57 | { |
91 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 58 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) |
92 | .subsections = (const VMStateDescription*[]) { | 59 | MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); |
93 | &vmstate_m_faultmask_primask, | 60 | MemoryRegion *sysmem = get_system_memory(); |
94 | &vmstate_m_csselr, | 61 | DeviceState *gicdev; |
95 | + &vmstate_m_scr, | 62 | + QList *oscclk; |
96 | NULL | 63 | |
64 | mms->clk = clock_new(OBJECT(machine), "CLK"); | ||
65 | clock_set_hz(mms->clk, CLK_FRQ); | ||
66 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
67 | } | ||
97 | } | 68 | } |
98 | }; | 69 | |
99 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 70 | + for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) { |
100 | VMSTATE_UINT32(env.sau.rnr, ARMCPU), | 71 | + g_autofree char *s = g_strdup_printf("spi%d", i); |
101 | VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), | 72 | + hwaddr baseaddr = 0xe0104000 + i * 0x1000; |
102 | VMSTATE_UINT32(env.sau.ctrl, ARMCPU), | 73 | + |
103 | + VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), | 74 | + object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022); |
104 | VMSTATE_END_OF_LIST() | 75 | + sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal); |
105 | } | 76 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr); |
106 | }; | 77 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0, |
78 | + qdev_get_gpio_in(gicdev, 22 + i)); | ||
79 | + } | ||
80 | + | ||
81 | + object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); | ||
82 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0); | ||
83 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2); | ||
84 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008); | ||
85 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360); | ||
86 | + oscclk = qlist_new(); | ||
87 | + for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) { | ||
88 | + qlist_append_int(oscclk, an536_oscclk[i]); | ||
89 | + } | ||
90 | + qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk); | ||
91 | + sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); | ||
92 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000); | ||
93 | + | ||
94 | + create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000); | ||
95 | + | ||
96 | + object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio, | ||
97 | + TYPE_MPS2_FPGAIO); | ||
98 | + qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]); | ||
99 | + qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10); | ||
100 | + qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true); | ||
101 | + qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false); | ||
102 | + sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); | ||
103 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000); | ||
104 | + | ||
105 | + create_unimplemented_device("clcd", 0xe0209000, 0x1000); | ||
106 | + | ||
107 | + object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031); | ||
108 | + sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal); | ||
109 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000); | ||
110 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0, | ||
111 | + qdev_get_gpio_in(gicdev, 4)); | ||
112 | + | ||
113 | + /* | ||
114 | + * In hardware this is a LAN9220; the LAN9118 is software compatible | ||
115 | + * except that it doesn't support the checksum-offload feature. | ||
116 | + */ | ||
117 | + lan9118_init(0xe0300000, | ||
118 | + qdev_get_gpio_in(gicdev, 18)); | ||
119 | + | ||
120 | + create_unimplemented_device("usb", 0xe0301000, 0x1000); | ||
121 | + create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000); | ||
122 | + | ||
123 | mms->bootinfo.ram_size = machine->ram_size; | ||
124 | mms->bootinfo.board_id = -1; | ||
125 | mms->bootinfo.loader_start = mmc->loader_start; | ||
107 | -- | 126 | -- |
108 | 2.16.1 | 127 | 2.34.1 |
109 | 128 | ||
110 | 129 | diff view generated by jsdifflib |
1 | The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from | 1 | Add documentation for the mps3-an536 board type. |
---|---|---|---|
2 | NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had | ||
3 | misimplemented this as making the bits RAZ/WI from both | ||
4 | Secure and NonSecure states. Fix this bug by checking | ||
5 | attrs.secure so that Secure code can pend and unpend NMIs. | ||
6 | 2 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20180209165810.6668-3-peter.maydell@linaro.org | 5 | Message-id: 20240206132931.38376-14-peter.maydell@linaro.org |
10 | --- | 6 | --- |
11 | hw/intc/armv7m_nvic.c | 6 +++--- | 7 | docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++--- |
12 | 1 file changed, 3 insertions(+), 3 deletions(-) | 8 | 1 file changed, 34 insertions(+), 3 deletions(-) |
13 | 9 | ||
14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 10 | diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/intc/armv7m_nvic.c | 12 | --- a/docs/system/arm/mps2.rst |
17 | +++ b/hw/intc/armv7m_nvic.c | 13 | +++ b/docs/system/arm/mps2.rst |
18 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 14 | @@ -XXX,XX +XXX,XX @@ |
19 | } | 15 | -Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``) |
20 | } | 16 | -========================================================================================================================================================= |
21 | /* NMIPENDSET */ | 17 | +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``) |
22 | - if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && | 18 | +========================================================================================================================================================================= |
23 | - s->vectors[ARMV7M_EXCP_NMI].pending) { | 19 | |
24 | + if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) | 20 | -These board models all use Arm M-profile CPUs. |
25 | + && s->vectors[ARMV7M_EXCP_NMI].pending) { | 21 | +These board models use Arm M-profile or R-profile CPUs. |
26 | val |= (1 << 31); | 22 | |
27 | } | 23 | The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a |
28 | /* ISRPREEMPT: RES0 when halting debug not implemented */ | 24 | bigger FPGA but is otherwise the same as the 2; the 3 has a bigger |
29 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 25 | @@ -XXX,XX +XXX,XX @@ FPGA image. |
30 | break; | 26 | |
31 | } | 27 | QEMU models the following FPGA images: |
32 | case 0xd04: /* Interrupt Control State (ICSR) */ | 28 | |
33 | - if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { | 29 | +FPGA images using M-profile CPUs: |
34 | + if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { | 30 | + |
35 | if (value & (1 << 31)) { | 31 | ``mps2-an385`` |
36 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); | 32 | Cortex-M3 as documented in Arm Application Note AN385 |
37 | } else if (value & (1 << 30) && | 33 | ``mps2-an386`` |
34 | @@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images: | ||
35 | ``mps3-an547`` | ||
36 | Cortex-M55 on an MPS3, as documented in Arm Application Note AN547 | ||
37 | |||
38 | +FPGA images using R-profile CPUs: | ||
39 | + | ||
40 | +``mps3-an536`` | ||
41 | + Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536 | ||
42 | + | ||
43 | Differences between QEMU and real hardware: | ||
44 | |||
45 | - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to | ||
46 | @@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware: | ||
47 | flash, but only as simple ROM, so attempting to rewrite the flash | ||
48 | from the guest will fail | ||
49 | - QEMU does not model the USB controller in MPS3 boards | ||
50 | +- AN536 does not support runtime control of CPU reset and halt via | ||
51 | + the SCC CFG_REG0 register. | ||
52 | +- AN536 does not support enabling or disabling the flash and ATCM | ||
53 | + interfaces via the SCC CFG_REG1 register. | ||
54 | +- AN536 does not support setting of the initial vector table | ||
55 | + base address via the SCC CFG_REG6 and CFG_REG7 register config, | ||
56 | + and does not provide a mechanism for specifying these values at | ||
57 | + startup, so all guest images must be built to start from TCM | ||
58 | + (i.e. to expect the interrupt vector base at 0 from reset). | ||
59 | +- AN536 defaults to only creating a single CPU; this is the equivalent | ||
60 | + of the way the real FPGA image usually runs with the second Cortex-R52 | ||
61 | + held in halt via the initial SCC CFG_REG0 register setting. You can | ||
62 | + create the second CPU with ``-smp 2``; both CPUs will then start | ||
63 | + execution immediately on startup. | ||
64 | + | ||
65 | +Note that for the AN536 the first UART is accessible only by | ||
66 | +CPU0, and the second UART is accessible only by CPU1. The | ||
67 | +first UART accessible shared between both CPUs is the third | ||
68 | +UART. Guest software might therefore be built to use either | ||
69 | +the first UART or the third UART; if you don't see any output | ||
70 | +from the UART you are looking at, try one of the others. | ||
71 | +(Even if the AN536 machine is started with a single CPU and so | ||
72 | +no "CPU1-only UART", the UART numbering remains the same, | ||
73 | +with the third UART being the first of the shared ones.) | ||
74 | |||
75 | Machine-specific options | ||
76 | """""""""""""""""""""""" | ||
38 | -- | 77 | -- |
39 | 2.16.1 | 78 | 2.34.1 |
40 | 79 | ||
41 | 80 | diff view generated by jsdifflib |