target-arm queue: mostly just cleanup/minor stuff, but this does

include the raspi3 board model.

The following changes since commit 9f9c53368b219a9115eddb39f0ff5ad19c977134:

Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging (2018-02-15 10:14:11 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180215

for you to fetch changes up to e545f0f9be1f9e60951017c1e6558216732cc14e:

target/arm: Implement v8M MSPLIM and PSPLIM registers (2018-02-15 13:48:11 +0000)

* aspeed: code cleanup to use unimplemented_device

* add 'raspi3' RaspberryPi 3 machine model

* more SVE prep work

* v8M: add minor missing registers

* v7M: fix bug where we weren't migrating v7m.other_sp

* v7M: fix bugs in handling of interrupt registers for

external interrupts beyond 32

Pekka Enberg (3):

bcm2836: Make CPU type configurable

raspi: Raspberry Pi 3 support

raspi: Add "raspi3" machine type

Peter Maydell (11):

hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC

hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling

hw/intc/armv7m_nvic: Implement M profile cache maintenance ops

hw/intc/armv7m_nvic: Implement v8M CPPWR register

hw/intc/armv7m_nvic: Implement cache ID registers

hw/intc/armv7m_nvic: Implement SCR

target/arm: Implement writing to CONTROL_NS for v8M

hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions

target/arm: Add AIRCR to vmstate struct

target/arm: Migrate v7m.other_sp

target/arm: Implement v8M MSPLIM and PSPLIM registers

Philippe Mathieu-Daudé (2):

hw/arm/aspeed: directly map the serial device to the system address space

hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

Richard Henderson (5):

target/arm: Remove ARM_CP_64BIT from ZCR_EL registers

target/arm: Enforce FP access to FPCR/FPSR

target/arm: Suppress TB end for FPCR/FPSR

target/arm: Enforce access to ZCR_EL at translation

target/arm: Handle SVE registers when using clear_vec_high

include/hw/arm/aspeed_soc.h | 1 -

include/hw/arm/bcm2836.h | 1 +

target/arm/cpu.h | 71 ++++++++++++-----

target/arm/internals.h | 6 ++

hw/arm/aspeed_soc.c | 35 ++-------

hw/arm/bcm2836.c | 17 +++--

hw/arm/raspi.c | 57 +++++++++++---

hw/intc/armv7m_nvic.c | 98 ++++++++++++++++++------

target/arm/cpu.c | 28 +++++++

target/arm/helper.c | 84 +++++++++++++++-----

target/arm/machine.c | 84 ++++++++++++++++++++

target/arm/translate-a64.c | 181 ++++++++++++++++++++------------------------

12 files changed, 452 insertions(+), 211 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

When storing to an AdvSIMD FP register, all of the high

bits of the SVE register are zeroed. Therefore, call it

more often with is_q as a parameter.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180211205848.4568-6-richard.henderson@linaro.org

target/arm/translate-a64.c | 162 +++++++++++++++++----------------------------

1 file changed, 62 insertions(+), 100 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)

return v;

}

+/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).

+ * If SVE is not enabled, then there are only 128 bits in the vector.

+ */

+static void clear_vec_high(DisasContext *s, bool is_q, int rd)

+{

+ unsigned ofs = fp_reg_offset(s, rd, MO_64);

+ unsigned vsz = vec_full_reg_size(s);

+

+ if (!is_q) {

+ TCGv_i64 tcg_zero = tcg_const_i64(0);

+ tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);

+ tcg_temp_free_i64(tcg_zero);

+ }

+ if (vsz > 16) {

+ tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);

+ }

+}

+

static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)

{

- TCGv_i64 tcg_zero = tcg_const_i64(0);

+ unsigned ofs = fp_reg_offset(s, reg, MO_64);

- tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));

- tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg));

- tcg_temp_free_i64(tcg_zero);

+ tcg_gen_st_i64(v, cpu_env, ofs);

+ clear_vec_high(s, false, reg);

}

static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)

@@ -XXX,XX +XXX,XX @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)

tcg_temp_free_i64(tmplo);

tcg_temp_free_i64(tmphi);

+

+ clear_vec_high(s, true, destidx);

}

/*

@@ -XXX,XX +XXX,XX @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,

}

}

-/* Clear the high 64 bits of a 128 bit vector (in general non-quad

- * vector ops all need to do this).

- */

-static void clear_vec_high(DisasContext *s, int rd)

-{

- TCGv_i64 tcg_zero = tcg_const_i64(0);

-

- write_vec_element(s, tcg_zero, rd, 1, MO_64);

- tcg_temp_free_i64(tcg_zero);

-}

-

/* Store from vector register to memory */

static void do_vec_st(DisasContext *s, int srcidx, int element,

TCGv_i64 tcg_addr, int size)

@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)

/* For non-quad operations, setting a slice of the low

* 64 bits of the register clears the high 64 bits (in

* the ARM ARM pseudocode this is implicit in the fact

- * that 'rval' is a 64 bit wide variable). We optimize

- * by noticing that we only need to do this the first

- * time we touch a register.

+ * that 'rval' is a 64 bit wide variable).

+ * For quad operations, we might still need to zero the

+ * high bits of SVE. We optimize by noticing that we only

+ * need to do this the first time we touch a register.

*/

- if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {

- clear_vec_high(s, tt);

+ if (e == 0 && (r == 0 || xs == selem - 1)) {

+ clear_vec_high(s, is_q, tt);

}

}

tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);

@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)

write_vec_element(s, tcg_tmp, rt, 0, MO_64);

if (is_q) {

write_vec_element(s, tcg_tmp, rt, 1, MO_64);

- } else {

- clear_vec_high(s, rt);

}

tcg_temp_free_i64(tcg_tmp);

+ clear_vec_high(s, is_q, rt);

} else {

/* Load/store one element per register */

if (is_load) {

@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,

}

if (!is_q) {

- clear_vec_high(s, rd);

write_vec_element(s, tcg_final, rd, 0, MO_64);

} else {

write_vec_element(s, tcg_final, rd, 1, MO_64);

@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,

tcg_temp_free_i64(tcg_rd);

tcg_temp_free_i32(tcg_rd_narrowed);

tcg_temp_free_i64(tcg_final);

- return;

+

+ clear_vec_high(s, is_q, rd);

}

/* SQSHLU, UQSHL, SQSHL: saturating left shifts */

@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,

tcg_temp_free_i64(tcg_op);

}

tcg_temp_free_i64(tcg_shift);

-

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

} else {

TCGv_i32 tcg_shift = tcg_const_i32(shift);

static NeonGenTwoOpEnvFn * const fns[2][2][3] = {

@@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,

}

tcg_temp_free_i32(tcg_shift);

- if (!is_q && !scalar) {

- clear_vec_high(s, rd);

+ if (!scalar) {

+ clear_vec_high(s, is_q, rd);

}

}

}

@@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,

}

}

- if (!is_double && elements == 2) {

- clear_vec_high(s, rd);

- }

-

tcg_temp_free_i64(tcg_int);

tcg_temp_free_ptr(tcg_fpst);

tcg_temp_free_i32(tcg_shift);

+

+ clear_vec_high(s, elements << size == 16, rd);

}

/* UCVTF/SCVTF - Integer to FP conversion */

@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,

write_vec_element(s, tcg_op, rd, pass, MO_64);

tcg_temp_free_i64(tcg_op);

}

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

} else {

int maxpass = is_scalar ? 1 : is_q ? 4 : 2;

for (pass = 0; pass < maxpass; pass++) {

@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,

}

tcg_temp_free_i32(tcg_op);

}

- if (!is_q && !is_scalar) {

- clear_vec_high(s, rd);

+ if (!is_scalar) {

+ clear_vec_high(s, is_q, rd);

}

}

@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,

tcg_temp_free_ptr(fpst);

- if ((elements << size) < 4) {

- /* scalar, or non-quad vector op */

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd);

}

/* AdvSIMD scalar three same

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,

}

write_vec_element(s, tcg_res, rd, pass, MO_64);

}

- if (is_scalar) {

- clear_vec_high(s, rd);

- }

-

tcg_temp_free_i64(tcg_res);

tcg_temp_free_i64(tcg_zero);

tcg_temp_free_i64(tcg_op);

+

+ clear_vec_high(s, !is_scalar, rd);

} else {

TCGv_i32 tcg_op = tcg_temp_new_i32();

TCGv_i32 tcg_zero = tcg_const_i32(0);

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,

tcg_temp_free_i32(tcg_res);

tcg_temp_free_i32(tcg_zero);

tcg_temp_free_i32(tcg_op);

- if (!is_q && !is_scalar) {

- clear_vec_high(s, rd);

+ if (!is_scalar) {

+ clear_vec_high(s, is_q, rd);

}

}

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,

}

write_vec_element(s, tcg_res, rd, pass, MO_64);

}

- if (is_scalar) {

- clear_vec_high(s, rd);

- }

-

tcg_temp_free_i64(tcg_res);

tcg_temp_free_i64(tcg_op);

+ clear_vec_high(s, !is_scalar, rd);

} else {

TCGv_i32 tcg_op = tcg_temp_new_i32();

TCGv_i32 tcg_res = tcg_temp_new_i32();

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,

}

tcg_temp_free_i32(tcg_res);

tcg_temp_free_i32(tcg_op);

- if (!is_q && !is_scalar) {

- clear_vec_high(s, rd);

+ if (!is_scalar) {

+ clear_vec_high(s, is_q, rd);

}

}

tcg_temp_free_ptr(fpst);

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,

write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);

tcg_temp_free_i32(tcg_res[pass]);

}

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

}

/* Remaining saturating accumulating ops */

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,

}

write_vec_element(s, tcg_rd, rd, pass, MO_64);

}

- if (is_scalar) {

- clear_vec_high(s, rd);

- }

-

tcg_temp_free_i64(tcg_rd);

tcg_temp_free_i64(tcg_rn);

+ clear_vec_high(s, !is_scalar, rd);

} else {

TCGv_i32 tcg_rn = tcg_temp_new_i32();

TCGv_i32 tcg_rd = tcg_temp_new_i32();

@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,

}

write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);

}

-

- if (!is_q) {

- clear_vec_high(s, rd);

- }

-

tcg_temp_free_i32(tcg_rd);

tcg_temp_free_i32(tcg_rn);

+ clear_vec_high(s, is_q, rd);

}

}

@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,

tcg_temp_free_i64(tcg_round);

done:

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

}

static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)

@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,

}

if (!is_q) {

- clear_vec_high(s, rd);

write_vec_element(s, tcg_final, rd, 0, MO_64);

} else {

write_vec_element(s, tcg_final, rd, 1, MO_64);

}

-

if (round) {

tcg_temp_free_i64(tcg_round);

}

tcg_temp_free_i64(tcg_rn);

tcg_temp_free_i64(tcg_rd);

tcg_temp_free_i64(tcg_final);

- return;

+

+ clear_vec_high(s, is_q, rd);

}

@@ -XXX,XX +XXX,XX @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,

write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);

tcg_temp_free_i32(tcg_res[pass]);

}

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

}

static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)

@@ -XXX,XX +XXX,XX @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,

write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);

tcg_temp_free_i32(tcg_res[pass]);

}

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

}

if (fpst) {

@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)

tcg_temp_free_i32(tcg_op2);

}

}

-

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

}

/* AdvSIMD three same

@@ -XXX,XX +XXX,XX @@ static void handle_rev(DisasContext *s, int opcode, bool u,

write_vec_element(s, tcg_tmp, rd, i, grp_size);

tcg_temp_free_i64(tcg_tmp);

}

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

} else {

int revmask = (1 << grp_size) - 1;

int esize = 8 << size;

@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)

tcg_temp_free_i32(tcg_op);

}

}

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

if (need_rmode) {

gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)

tcg_temp_free_i64(tcg_res);

}

- if (is_scalar) {

- clear_vec_high(s, rd);

- }

-

tcg_temp_free_i64(tcg_idx);

+ clear_vec_high(s, !is_scalar, rd);

} else if (!is_long) {

/* 32 bit floating point, or 16 or 32 bit integer.

* For the 16 bit scalar case we use the usual Neon helpers and

@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)

}

tcg_temp_free_i32(tcg_idx);

-

- if (!is_q) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, is_q, rd);

} else {

/* long ops: 16x16->32 or 32x32->64 */

TCGv_i64 tcg_res[2];

@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)

}

tcg_temp_free_i64(tcg_idx);

- if (is_scalar) {

- clear_vec_high(s, rd);

- }

+ clear_vec_high(s, !is_scalar, rd);

} else {

TCGv_i32 tcg_idx = tcg_temp_new_i32();

2.16.1

In commit abc24d86cc0364f we accidentally broke migration of

the stack pointer value for the mode (process, handler) the CPU

is not currently running as. (The commit correctly removed the

no-longer-used v7m.current_sp flag from the VMState but also

deleted the still very much in use v7m.other_sp SP value field.)

Add a subsection to migrate it again. (We don't need to care

about trying to retain compatibility with pre-abc24d86cc0364f

versions of QEMU, because that commit bumped the version_id

and we've since bumped it again a couple of times.)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180209165810.6668-11-peter.maydell@linaro.org

target/arm/machine.c | 11 +++++++++++

1 file changed, 11 insertions(+)

diff --git a/target/arm/machine.c b/target/arm/machine.c

--- a/target/arm/machine.c

+++ b/target/arm/machine.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_scr = {

}

};

+static const VMStateDescription vmstate_m_other_sp = {

+ .name = "cpu/m/other-sp",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),

+ VMSTATE_END_OF_LIST()

+ }

+};

static const VMStateDescription vmstate_m = {

.name = "cpu/m",

.version_id = 4,

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {

&vmstate_m_faultmask_primask,

&vmstate_m_csselr,

&vmstate_m_scr,

+ &vmstate_m_other_sp,

NULL

}

};

2.16.1

The v8M architecture includes hardware support for enforcing

stack pointer limits. We don't implement this behaviour yet,

but provide the MSPLIM and PSPLIM stack pointer limit registers

as reads-as-written, so that when we do implement the checks

in future this won't break guest migration.

Message-id: 20180209165810.6668-12-peter.maydell@linaro.org

target/arm/cpu.h | 2 ++

target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++

target/arm/machine.c | 21 +++++++++++++++++++++

3 files changed, 69 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {

uint32_t secure; /* Is CPU in Secure state? (not guest visible) */

uint32_t csselr[M_REG_NUM_BANKS];

uint32_t scr[M_REG_NUM_BANKS];

+ uint32_t msplim[M_REG_NUM_BANKS];

+ uint32_t psplim[M_REG_NUM_BANKS];

} v7m;

/* Information associated with an exception about to be taken:

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)

return 0;

}

return env->v7m.other_ss_psp;

+ case 0x8a: /* MSPLIM_NS */

+ if (!env->v7m.secure) {

+ return 0;

+ }

+ return env->v7m.msplim[M_REG_NS];

+ case 0x8b: /* PSPLIM_NS */

+ if (!env->v7m.secure) {

+ return 0;

+ }

+ return env->v7m.psplim[M_REG_NS];

case 0x90: /* PRIMASK_NS */

if (!env->v7m.secure) {

return 0;

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)

return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13];

case 9: /* PSP */

return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp;

+ case 10: /* MSPLIM */

+ if (!arm_feature(env, ARM_FEATURE_V8)) {

+ goto bad_reg;

+ }

+ return env->v7m.msplim[env->v7m.secure];

+ case 11: /* PSPLIM */

+ if (!arm_feature(env, ARM_FEATURE_V8)) {

+ goto bad_reg;

+ }

+ return env->v7m.psplim[env->v7m.secure];

case 16: /* PRIMASK */

return env->v7m.primask[env->v7m.secure];

case 17: /* BASEPRI */

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)

case 19: /* FAULTMASK */

return env->v7m.faultmask[env->v7m.secure];

default:

+ bad_reg:

qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"

" register %d\n", reg);

return 0;

env->v7m.other_sp = val;

+ case 10: /* MSPLIM */

+ if (!arm_feature(env, ARM_FEATURE_V8)) {

+ goto bad_reg;

+ }

+ env->v7m.msplim[env->v7m.secure] = val & ~7;

+ break;

+ case 11: /* PSPLIM */

+ if (!arm_feature(env, ARM_FEATURE_V8)) {

+ goto bad_reg;

+ }

+ env->v7m.psplim[env->v7m.secure] = val & ~7;

+ break;

case 16: /* PRIMASK */

env->v7m.primask[env->v7m.secure] = val & 1;

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)

env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;

break;

default:

+ bad_reg:

qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"

" register %d\n", reg);

return;

diff --git a/target/arm/machine.c b/target/arm/machine.c

--- a/target/arm/machine.c

+++ b/target/arm/machine.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_other_sp = {

};

+static bool m_v8m_needed(void *opaque)

+{

+ ARMCPU *cpu = opaque;

+ CPUARMState *env = &cpu->env;

+

+ return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8);

+}

+

+static const VMStateDescription vmstate_m_v8m = {

+ .name = "cpu/m/v8m",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .needed = m_v8m_needed,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),

+ VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

static const VMStateDescription vmstate_m = {

.name = "cpu/m",

.version_id = 4,

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {

&vmstate_m_csselr,

&vmstate_m_scr,

&vmstate_m_other_sp,

+ &vmstate_m_v8m,

NULL

}

};

2.16.1

In commit commit 3b2e934463121 we added support for the AIRCR

register holding state, but forgot to add it to the vmstate

structs. Since it only holds r/w state if the security extension

is implemented, we can just add it to vmstate_m_security.

Message-id: 20180209165810.6668-10-peter.maydell@linaro.org

target/arm/machine.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/target/arm/machine.c b/target/arm/machine.c

--- a/target/arm/machine.c

+++ b/target/arm/machine.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {

VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),

VMSTATE_UINT32(env.sau.ctrl, ARMCPU),

VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),

+ /* AIRCR is not secure-only, but our implementation is R/O if the

+ * security extension is unimplemented, so we migrate it here.

+ */

+ VMSTATE_UINT32(env.v7m.aircr, ARMCPU),

VMSTATE_END_OF_LIST()

}

};

2.16.1

In commit 50f11062d4c896 we added support for MSR/MRS access

to the NS banked special registers, but we forgot to implement

the support for writing to CONTROL_NS. Correct the omission.

Message-id: 20180209165810.6668-8-peter.maydell@linaro.org

target/arm/helper.c | 10 ++++++++++

1 file changed, 10 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)

env->v7m.faultmask[M_REG_NS] = val & 1;

return;

+ case 0x94: /* CONTROL_NS */

+ if (!env->v7m.secure) {

+ return;

+ }

+ write_v7m_control_spsel_for_secstate(env,

+ val & R_V7M_CONTROL_SPSEL_MASK,

+ M_REG_NS);

+ env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;

+ env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;

+ return;

case 0x98: /* SP_NS */

{

/* This gives the non-secure SP selected based on whether we're

2.16.1

The Coprocessor Power Control Register (CPPWR) is new in v8M.

It allows software to control whether coprocessors are allowed

to power down and lose their state. QEMU doesn't have any

notion of power control, so we choose the IMPDEF option of

making the whole register RAZ/WI (indicating that no coprocessors

can ever power down and lose state).

Message-id: 20180209165810.6668-5-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 14 ++++++++++++++

1 file changed, 14 insertions(+)

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

switch (offset) {

case 4: /* Interrupt Control Type. */

return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;

+ case 0xc: /* CPPWR */

+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

+ goto bad_offset;

+ }

+ /* We make the IMPDEF choice that nothing can ever go into a

+ * non-retentive power state, which allows us to RAZ/WI this.

+ */

+ return 0;

case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */

{

int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

ARMCPU *cpu = s->cpu;

switch (offset) {

+ case 0xc: /* CPPWR */

+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {

+ goto bad_offset;

+ }

+ /* Make the IMPDEF choice to RAZ/WI this. */

+ break;

case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */

{

int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;

2.16.1

The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from

NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had

misimplemented this as making the bits RAZ/WI from both

Secure and NonSecure states. Fix this bug by checking

attrs.secure so that Secure code can pend and unpend NMIs.

Message-id: 20180209165810.6668-3-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 6 +++---

1 file changed, 3 insertions(+), 3 deletions(-)

}

}

/* NMIPENDSET */

- if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&

- s->vectors[ARMV7M_EXCP_NMI].pending) {

+ if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))

+ && s->vectors[ARMV7M_EXCP_NMI].pending) {

val |= (1 << 31);

}

/* ISRPREEMPT: RES0 when halting debug not implemented */

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

break;

}

case 0xd04: /* Interrupt Control State (ICSR) */

- if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {

+ if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {

if (value & (1 << 31)) {

armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);

} else if (value & (1 << 30) &&

2.16.1

M profile cores have a similar setup for cache ID registers

to A profile:

* Cache Level ID Register (CLIDR) is a fixed value

* Cache Type Register (CTR) is a fixed value

* Cache Size ID Registers (CCSIDR) are a bank of registers;

which one you see is selected by the Cache Size Selection

Register (CSSELR)

The only difference is that they're in the NVIC memory mapped

register space rather than being coprocessor registers.

Implement the M profile view of them.

Since neither Cortex-M3 nor Cortex-M4 implement caches,

we don't need to update their init functions and can leave

the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero.

Newer cores (like the Cortex-M33) will want to be able to

set these ID registers to non-zero values, though.

Message-id: 20180209165810.6668-6-peter.maydell@linaro.org

target/arm/cpu.h | 26 ++++++++++++++++++++++++++

hw/intc/armv7m_nvic.c | 16 ++++++++++++++++

target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++

3 files changed, 78 insertions(+)

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

return cpu->id_isar4;

case 0xd74: /* ISAR5. */

return cpu->id_isar5;

+ case 0xd78: /* CLIDR */

+ return cpu->clidr;

+ case 0xd7c: /* CTR */

+ return cpu->ctr;

+ case 0xd80: /* CSSIDR */

+ {

+ int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK;

+ return cpu->ccsidr[idx];

+ case 0xd84: /* CSSELR */

+ return cpu->env.v7m.csselr[attrs.secure];

/* TODO: Implement debug registers. */

case 0xd90: /* MPU_TYPE */

/* Unified MPU; if the MPU is not present this value is zero */

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

qemu_log_mask(LOG_UNIMP,

"NVIC: Aux fault status registers unimplemented\n");

break;

+ case 0xd84: /* CSSELR */

+ if (!arm_v7m_csselr_razwi(cpu)) {

+ cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK;

+ }

+ break;

case 0xd90: /* MPU_TYPE */

return; /* RO */

case 0xd94: /* MPU_CTRL */

diff --git a/target/arm/machine.c b/target/arm/machine.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/machine.c

+++ b/target/arm/machine.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = {

}

};

+/* CSSELR is in a subsection because we didn't implement it previously.

+ * Migration from an old implementation will leave it at zero, which

+ * is OK since the only CPUs in the old implementation make the

+ * register RAZ/WI.

+ * Since there was no version of QEMU which implemented the CSSELR for

+ * just non-secure, we transfer both banks here rather than putting

+ * the secure banked version in the m-security subsection.

+ */

+static bool csselr_vmstate_validate(void *opaque, int version_id)

+{

+ ARMCPU *cpu = opaque;

+

+ return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK

+ && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK;

+static bool m_csselr_needed(void *opaque)

+{

+ ARMCPU *cpu = opaque;

+

+ return !arm_v7m_csselr_razwi(cpu);

+}

+

+static const VMStateDescription vmstate_m_csselr = {

+ .name = "cpu/m/csselr",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .needed = m_csselr_needed,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),

+ VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

static const VMStateDescription vmstate_m = {

.name = "cpu/m",

.version_id = 4,

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {

},

.subsections = (const VMStateDescription*[]) {

&vmstate_m_faultmask_primask,

+ &vmstate_m_csselr,

NULL

}

};

2.16.1

From: Pekka Enberg <penberg@iki.fi>

This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The

differences to Pi 2 are:

- Firmware address

- Board ID

- Board revision

The CPU is different too, but that's going to be configured as part of

the machine default CPU when we introduce a new machine type.

The patch was written from scratch by me but the logic is similar to

Zoltán Baldaszti's previous work, which I used as a reference (with

permission from the author):

https://github.com/bztsrc/qemu-raspi3

Signed-off-by: Pekka Enberg <penberg@iki.fi>

[PMM: fixed trailing whitespace on one line]

hw/arm/raspi.c | 31 +++++++++++++++++++++----------

1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c

--- a/hw/arm/raspi.c

+++ b/hw/arm/raspi.c

@@ -XXX,XX +XXX,XX @@

* Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft

* Written by Andrew Baumann

*

+ * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti